dp_rx.c 17 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "dp_types.h"
  19. #include "dp_rx.h"
  20. #include "dp_peer.h"
  21. #include "hal_rx.h"
  22. #include "hal_api.h"
  23. #include "qdf_nbuf.h"
  24. #include <ieee80211.h>
  25. #ifdef MESH_MODE_SUPPORT
  26. #include "if_meta_hdr.h"
  27. #endif
  28. /*
  29. * dp_rx_buffers_replenish() - replenish rxdma ring with rx nbufs
  30. * called during dp rx initialization
  31. * and at the end of dp_rx_process.
  32. *
  33. * @soc: core txrx main context
  34. * @mac_id: mac_id which is one of 3 mac_ids
  35. * @desc_list: list of descs if called from dp_rx_process
  36. * or NULL during dp rx initialization or out of buffer
  37. * interrupt.
  38. * @owner: who owns the nbuf (host, NSS etc...)
  39. * Return: return success or failure
  40. */
  41. QDF_STATUS dp_rx_buffers_replenish(struct dp_soc *dp_soc, uint32_t mac_id,
  42. uint32_t num_req_buffers,
  43. union dp_rx_desc_list_elem_t **desc_list,
  44. union dp_rx_desc_list_elem_t **tail,
  45. uint8_t owner)
  46. {
  47. uint32_t num_alloc_desc;
  48. uint16_t num_desc_to_free = 0;
  49. struct dp_pdev *dp_pdev = dp_soc->pdev_list[mac_id];
  50. uint32_t num_entries_avail;
  51. uint32_t count;
  52. int sync_hw_ptr = 1;
  53. qdf_dma_addr_t paddr;
  54. qdf_nbuf_t rx_netbuf;
  55. void *rxdma_ring_entry;
  56. union dp_rx_desc_list_elem_t *next;
  57. struct dp_srng *dp_rxdma_srng = &dp_pdev->rx_refill_buf_ring;
  58. void *rxdma_srng = dp_rxdma_srng->hal_srng;
  59. int32_t ret;
  60. if (!rxdma_srng) {
  61. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  62. "rxdma srng not initialized");
  63. return QDF_STATUS_E_FAILURE;
  64. }
  65. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  66. "requested %d buffers for replenish", num_req_buffers);
  67. /*
  68. * if desc_list is NULL, allocate the descs from freelist
  69. */
  70. if (!(*desc_list)) {
  71. num_alloc_desc = dp_rx_get_free_desc_list(dp_soc, mac_id,
  72. num_req_buffers,
  73. desc_list,
  74. tail);
  75. if (!num_alloc_desc) {
  76. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  77. "no free rx_descs in freelist");
  78. return QDF_STATUS_E_NOMEM;
  79. }
  80. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  81. "%d rx desc allocated", num_alloc_desc);
  82. num_req_buffers = num_alloc_desc;
  83. }
  84. hal_srng_access_start(dp_soc->hal_soc, rxdma_srng);
  85. num_entries_avail = hal_srng_src_num_avail(dp_soc->hal_soc,
  86. rxdma_srng,
  87. sync_hw_ptr);
  88. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  89. "no of availble entries in rxdma ring: %d",
  90. num_entries_avail);
  91. if (num_entries_avail < num_req_buffers) {
  92. num_desc_to_free = num_req_buffers - num_entries_avail;
  93. num_req_buffers = num_entries_avail;
  94. }
  95. count = 0;
  96. while (count < num_req_buffers) {
  97. rx_netbuf = qdf_nbuf_alloc(dp_pdev->osif_pdev,
  98. RX_BUFFER_SIZE,
  99. RX_BUFFER_RESERVATION,
  100. RX_BUFFER_ALIGNMENT,
  101. FALSE);
  102. if (rx_netbuf == NULL)
  103. continue;
  104. qdf_nbuf_map_single(dp_soc->osdev, rx_netbuf,
  105. QDF_DMA_BIDIRECTIONAL);
  106. paddr = qdf_nbuf_get_frag_paddr(rx_netbuf, 0);
  107. /*
  108. * check if the physical address of nbuf->data is
  109. * less then 0x50000000 then free the nbuf and try
  110. * allocating new nbuf. We can try for 100 times.
  111. * this is a temp WAR till we fix it properly.
  112. */
  113. ret = check_x86_paddr(dp_soc, &rx_netbuf, &paddr, dp_pdev);
  114. if (ret == QDF_STATUS_E_FAILURE)
  115. break;
  116. count++;
  117. rxdma_ring_entry = hal_srng_src_get_next(dp_soc->hal_soc,
  118. rxdma_srng);
  119. next = (*desc_list)->next;
  120. (*desc_list)->rx_desc.nbuf = rx_netbuf;
  121. hal_rxdma_buff_addr_info_set(rxdma_ring_entry, paddr,
  122. (*desc_list)->rx_desc.cookie,
  123. owner);
  124. *desc_list = next;
  125. }
  126. hal_srng_access_end(dp_soc->hal_soc, rxdma_srng);
  127. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  128. "successfully replenished %d buffers", num_req_buffers);
  129. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  130. "%d rx desc added back to free list", num_desc_to_free);
  131. /*
  132. * add any available free desc back to the free list
  133. */
  134. if (*desc_list)
  135. dp_rx_add_desc_list_to_free_list(dp_soc, desc_list,
  136. tail, mac_id);
  137. return QDF_STATUS_SUCCESS;
  138. }
  139. /*
  140. * dp_rx_deliver_raw() - process RAW mode pkts and hand over the
  141. * pkts to RAW mode simulation to
  142. * decapsulate the pkt.
  143. *
  144. * @vdev: vdev on which RAW mode is enabled
  145. * @nbuf_list: list of RAW pkts to process
  146. *
  147. * Return: void
  148. */
  149. static void
  150. dp_rx_deliver_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf_list)
  151. {
  152. qdf_nbuf_t deliver_list_head = NULL;
  153. qdf_nbuf_t deliver_list_tail = NULL;
  154. qdf_nbuf_t nbuf;
  155. nbuf = nbuf_list;
  156. while (nbuf) {
  157. qdf_nbuf_t next = qdf_nbuf_next(nbuf);
  158. DP_RX_LIST_APPEND(deliver_list_head, deliver_list_tail, nbuf);
  159. /*
  160. * reset the chfrag_start and chfrag_end bits in nbuf cb
  161. * as this is a non-amsdu pkt and RAW mode simulation expects
  162. * these bit s to be 0 for non-amsdu pkt.
  163. */
  164. if (qdf_nbuf_is_chfrag_start(nbuf) &&
  165. qdf_nbuf_is_chfrag_end(nbuf)) {
  166. qdf_nbuf_set_chfrag_start(nbuf, 0);
  167. qdf_nbuf_set_chfrag_end(nbuf, 0);
  168. }
  169. nbuf = next;
  170. }
  171. vdev->osif_rsim_rx_decap(vdev->osif_vdev, &deliver_list_head,
  172. &deliver_list_tail);
  173. vdev->osif_rx(vdev->osif_vdev, deliver_list_head);
  174. }
  175. /**
  176. * dp_rx_intrabss_fwd() - Implements the Intra-BSS forwarding logic
  177. *
  178. * @soc: core txrx main context
  179. * @sa_peer : source peer entry
  180. * @rx_tlv_hdr : start address of rx tlvs
  181. * @nbuf : nbuf that has to be intrabss forwarded
  182. *
  183. * Return: bool: true if it is forwarded else false
  184. */
  185. static bool
  186. dp_rx_intrabss_fwd(struct dp_soc *soc,
  187. struct dp_peer *sa_peer,
  188. uint8_t *rx_tlv_hdr,
  189. qdf_nbuf_t nbuf)
  190. {
  191. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  192. FL("Intra-BSS forwarding not implemented"));
  193. return false;
  194. }
  195. #ifdef MESH_MODE_SUPPORT
  196. /**
  197. * dp_rx_fill_mesh_stats() - Fills the mesh per packet receive stats
  198. *
  199. * @vdev: DP Virtual device handle
  200. * @nbuf: Buffer pointer
  201. *
  202. * This function allocated memory for mesh receive stats and fill the
  203. * required stats. Stores the memory address in skb cb.
  204. *
  205. * Return: void
  206. */
  207. static
  208. void dp_rx_fill_mesh_stats(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  209. {
  210. struct mesh_recv_hdr_s *rx_info = NULL;
  211. uint32_t pkt_type;
  212. uint32_t nss;
  213. uint32_t rate_mcs;
  214. uint8_t *rx_tlv_hdr = qdf_nbuf_data(nbuf);
  215. /* fill recv mesh stats */
  216. rx_info = qdf_mem_malloc(sizeof(struct mesh_recv_hdr_s));
  217. /* upper layers are resposible to free this memory */
  218. if (rx_info == NULL) {
  219. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  220. "Memory allocation failed for mesh rx stats");
  221. return;
  222. }
  223. if (qdf_nbuf_is_chfrag_start(nbuf))
  224. rx_info->rs_flags |= MESH_RX_FIRST_MSDU;
  225. if (qdf_nbuf_is_chfrag_end(nbuf))
  226. rx_info->rs_flags |= MESH_RX_LAST_MSDU;
  227. if (hal_rx_attn_msdu_get_is_decrypted(rx_tlv_hdr)) {
  228. rx_info->rs_flags |= MESH_RX_DECRYPTED;
  229. rx_info->rs_keyix = hal_rx_msdu_get_keyid(rx_tlv_hdr);
  230. rx_info->rs_flags |= MESH_KEY_NOTFILLED;
  231. }
  232. rx_info->rs_rssi = hal_rx_msdu_start_get_rssi(rx_tlv_hdr);
  233. rx_info->rs_channel = hal_rx_msdu_start_get_freq(rx_tlv_hdr);
  234. pkt_type = hal_rx_msdu_start_get_pkt_type(rx_tlv_hdr);
  235. rate_mcs = hal_rx_msdu_start_rate_mcs_get(rx_tlv_hdr);
  236. nss = hal_rx_msdu_start_nss_get(rx_tlv_hdr);
  237. rx_info->rs_ratephy1 = rate_mcs | (nss << 0x4) | (pkt_type << 6);
  238. qdf_nbuf_set_fctx_type(nbuf, (void *)rx_info, CB_FTYPE_MESH_RX_INFO);
  239. }
  240. #else
  241. static
  242. void dp_rx_fill_mesh_stats(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  243. {
  244. }
  245. #endif
  246. /**
  247. * dp_rx_process() - Brain of the Rx processing functionality
  248. * Called from the bottom half (tasklet/NET_RX_SOFTIRQ)
  249. * @soc: core txrx main context
  250. * @hal_ring: opaque pointer to the HAL Rx Ring, which will be serviced
  251. * @quota: No. of units (packets) that can be serviced in one shot.
  252. *
  253. * This function implements the core of Rx functionality. This is
  254. * expected to handle only non-error frames.
  255. *
  256. * Return: uint32_t: No. of elements processed
  257. */
  258. uint32_t
  259. dp_rx_process(struct dp_soc *soc, void *hal_ring, uint32_t quota)
  260. {
  261. void *hal_soc;
  262. void *ring_desc;
  263. struct dp_rx_desc *rx_desc;
  264. qdf_nbuf_t nbuf;
  265. union dp_rx_desc_list_elem_t *head[MAX_PDEV_CNT] = { NULL };
  266. union dp_rx_desc_list_elem_t *tail[MAX_PDEV_CNT] = { NULL };
  267. uint32_t rx_bufs_used = 0, rx_buf_cookie, l2_hdr_offset;
  268. uint16_t msdu_len;
  269. uint16_t peer_id;
  270. struct dp_peer *peer = NULL;
  271. struct dp_vdev *vdev = NULL;
  272. struct dp_vdev *vdev_list[WLAN_UMAC_PSOC_MAX_VDEVS] = { NULL };
  273. struct hal_rx_mpdu_desc_info mpdu_desc_info;
  274. struct hal_rx_msdu_desc_info msdu_desc_info;
  275. enum hal_reo_error_status error;
  276. uint32_t pkt_len;
  277. static uint32_t peer_mdata;
  278. uint8_t *rx_tlv_hdr;
  279. uint32_t rx_bufs_reaped[MAX_PDEV_CNT] = { 0 };
  280. uint32_t sgi, rate_mcs, tid;
  281. uint64_t vdev_map = 0;
  282. uint8_t mac_id;
  283. uint16_t i, vdev_cnt = 0;
  284. /* Debug -- Remove later */
  285. qdf_assert(soc && hal_ring);
  286. hal_soc = soc->hal_soc;
  287. /* Debug -- Remove later */
  288. qdf_assert(hal_soc);
  289. if (qdf_unlikely(hal_srng_access_start(hal_soc, hal_ring))) {
  290. /*
  291. * Need API to convert from hal_ring pointer to
  292. * Ring Type / Ring Id combo
  293. */
  294. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  295. FL("HAL RING Access Failed -- %p"), hal_ring);
  296. hal_srng_access_end(hal_soc, hal_ring);
  297. goto done;
  298. }
  299. /*
  300. * start reaping the buffers from reo ring and queue
  301. * them in per vdev queue.
  302. * Process the received pkts in a different per vdev loop.
  303. */
  304. while (qdf_likely((ring_desc =
  305. hal_srng_dst_get_next(hal_soc, hal_ring))
  306. && quota--)) {
  307. error = HAL_RX_ERROR_STATUS_GET(ring_desc);
  308. if (qdf_unlikely(error == HAL_REO_ERROR_DETECTED)) {
  309. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  310. FL("HAL RING 0x%p:error %d"), hal_ring, error);
  311. /* Don't know how to deal with this -- assert */
  312. qdf_assert(0);
  313. }
  314. rx_buf_cookie = HAL_RX_REO_BUF_COOKIE_GET(ring_desc);
  315. rx_desc = dp_rx_cookie_2_va(soc, rx_buf_cookie);
  316. qdf_assert(rx_desc);
  317. rx_bufs_reaped[rx_desc->pool_id]++;
  318. /* TODO */
  319. /*
  320. * Need a separate API for unmapping based on
  321. * phyiscal address
  322. */
  323. qdf_nbuf_unmap_single(soc->osdev, rx_desc->nbuf,
  324. QDF_DMA_BIDIRECTIONAL);
  325. /* Get MPDU DESC info */
  326. hal_rx_mpdu_desc_info_get(ring_desc, &mpdu_desc_info);
  327. peer_id = DP_PEER_METADATA_PEER_ID_GET(
  328. mpdu_desc_info.peer_meta_data);
  329. peer = dp_peer_find_by_id(soc, peer_id);
  330. if (!peer) {
  331. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  332. FL("peer look-up failed peer id %d"), peer_id);
  333. /* Drop & free packet */
  334. qdf_nbuf_free(rx_desc->nbuf);
  335. goto fail;
  336. }
  337. vdev = peer->vdev;
  338. if (!vdev) {
  339. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  340. FL("vdev is NULL"));
  341. qdf_nbuf_free(rx_desc->nbuf);
  342. goto fail;
  343. }
  344. if (!((vdev_map >> vdev->vdev_id) & 1)) {
  345. vdev_map |= 1 << vdev->vdev_id;
  346. vdev_list[vdev_cnt] = vdev;
  347. vdev_cnt++;
  348. }
  349. /* Get MSDU DESC info */
  350. hal_rx_msdu_desc_info_get(ring_desc, &msdu_desc_info);
  351. /*
  352. * save msdu flags first, last and continuation msdu in
  353. * nbuf->cb
  354. */
  355. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_FIRST_MSDU_IN_MPDU)
  356. qdf_nbuf_set_chfrag_start(rx_desc->nbuf, 1);
  357. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_MSDU_CONTINUATION)
  358. qdf_nbuf_set_chfrag_cont(rx_desc->nbuf, 1);
  359. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  360. qdf_nbuf_set_chfrag_end(rx_desc->nbuf, 1);
  361. qdf_nbuf_queue_add(&vdev->rxq, rx_desc->nbuf);
  362. fail:
  363. dp_rx_add_to_free_desc_list(&head[rx_desc->pool_id],
  364. &tail[rx_desc->pool_id],
  365. rx_desc);
  366. }
  367. done:
  368. hal_srng_access_end(hal_soc, hal_ring);
  369. for (mac_id = 0; mac_id < MAX_PDEV_CNT; mac_id++) {
  370. /*
  371. * continue with next mac_id if no pkts were reaped
  372. * from that pool
  373. */
  374. if (!rx_bufs_reaped[mac_id])
  375. continue;
  376. dp_rx_buffers_replenish(soc, mac_id,
  377. rx_bufs_reaped[mac_id],
  378. &head[mac_id],
  379. &tail[mac_id],
  380. HAL_RX_BUF_RBM_SW3_BM);
  381. }
  382. for (i = 0; i < vdev_cnt; i++) {
  383. qdf_nbuf_t deliver_list_head = NULL;
  384. qdf_nbuf_t deliver_list_tail = NULL;
  385. vdev = vdev_list[i];
  386. while ((nbuf = qdf_nbuf_queue_remove(&vdev->rxq))) {
  387. rx_tlv_hdr = qdf_nbuf_data(nbuf);
  388. /*
  389. * Check if DMA completed -- msdu_done is the last bit
  390. * to be written
  391. */
  392. if (!hal_rx_attn_msdu_done_get(rx_tlv_hdr)) {
  393. QDF_TRACE(QDF_MODULE_ID_DP,
  394. QDF_TRACE_LEVEL_ERROR,
  395. FL("HAL RING 0x%p"), hal_ring);
  396. print_hex_dump(KERN_ERR,
  397. "\t Pkt Desc:", DUMP_PREFIX_NONE, 32, 4,
  398. rx_tlv_hdr, 128, false);
  399. qdf_assert(0);
  400. }
  401. if (qdf_nbuf_is_chfrag_start(nbuf))
  402. peer_mdata = hal_rx_mpdu_peer_meta_data_get(rx_tlv_hdr);
  403. peer_id = DP_PEER_METADATA_PEER_ID_GET(peer_mdata);
  404. peer = dp_peer_find_by_id(soc, peer_id);
  405. /* TODO */
  406. /*
  407. * In case of roaming peer object may not be
  408. * immediately available -- need to handle this
  409. * Cannot drop these packets right away.
  410. */
  411. /* Peer lookup failed */
  412. if (!peer) {
  413. /* Drop & free packet */
  414. qdf_nbuf_free(nbuf);
  415. /* Statistics */
  416. continue;
  417. }
  418. if (qdf_unlikely(peer->bss_peer)) {
  419. QDF_TRACE(QDF_MODULE_ID_DP,
  420. QDF_TRACE_LEVEL_INFO,
  421. FL("received pkt with same src MAC"));
  422. /* Drop & free packet */
  423. qdf_nbuf_free(nbuf);
  424. /* Statistics */
  425. continue;
  426. }
  427. sgi = hal_rx_msdu_start_sgi_get(rx_tlv_hdr);
  428. rate_mcs = hal_rx_msdu_start_rate_mcs_get(rx_tlv_hdr);
  429. tid = hal_rx_mpdu_start_tid_get(rx_tlv_hdr);
  430. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  431. "%s: %d, SGI: %d, rate_mcs: %d, tid: %d",
  432. __func__, __LINE__, sgi, rate_mcs, tid);
  433. /*
  434. * HW structures call this L3 header padding --
  435. * even though this is actually the offset from
  436. * the buffer beginning where the L2 header
  437. * begins.
  438. */
  439. l2_hdr_offset =
  440. hal_rx_msdu_end_l3_hdr_padding_get(rx_tlv_hdr);
  441. msdu_len = hal_rx_msdu_start_msdu_len_get(rx_tlv_hdr);
  442. pkt_len = msdu_len + l2_hdr_offset + RX_PKT_TLVS_LEN;
  443. /* Set length in nbuf */
  444. qdf_nbuf_set_pktlen(nbuf, pkt_len);
  445. if (qdf_unlikely(vdev->mesh_vdev))
  446. dp_rx_fill_mesh_stats(vdev, nbuf);
  447. /*
  448. * Advance the packet start pointer by total size of
  449. * pre-header TLV's
  450. */
  451. qdf_nbuf_pull_head(nbuf,
  452. RX_PKT_TLVS_LEN + l2_hdr_offset);
  453. #ifdef QCA_WIFI_NAPIER_EMULATION /* Debug code, remove later */
  454. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  455. "p_id %d msdu_len %d hdr_off %d",
  456. peer_id, msdu_len, l2_hdr_offset);
  457. print_hex_dump(KERN_ERR,
  458. "\t Pkt Data:", DUMP_PREFIX_NONE, 32, 4,
  459. qdf_nbuf_data(nbuf), 128, false);
  460. #endif /* NAPIER_EMULATION */
  461. /* WDS Source Port Learning */
  462. dp_rx_wds_srcport_learn(soc, rx_tlv_hdr, peer, nbuf);
  463. /* Intrabss-fwd */
  464. if (dp_rx_intrabss_fwd(soc, peer, rx_tlv_hdr, nbuf))
  465. continue; /* Get next descriptor */
  466. rx_bufs_used++;
  467. DP_RX_LIST_APPEND(deliver_list_head,
  468. deliver_list_tail,
  469. nbuf);
  470. }
  471. if (qdf_unlikely(vdev->rx_decap_type == htt_pkt_type_raw))
  472. dp_rx_deliver_raw(vdev, deliver_list_head);
  473. else if (qdf_likely(vdev->osif_rx) && deliver_list_head)
  474. vdev->osif_rx(vdev->osif_vdev, deliver_list_head);
  475. }
  476. return rx_bufs_used; /* Assume no scale factor for now */
  477. }
  478. /**
  479. * dp_rx_detach() - detach dp rx
  480. * @soc: core txrx main context
  481. *
  482. * This function will detach DP RX into main device context
  483. * will free DP Rx resources.
  484. *
  485. * Return: void
  486. */
  487. void
  488. dp_rx_pdev_detach(struct dp_pdev *pdev)
  489. {
  490. uint8_t pdev_id = pdev->pdev_id;
  491. struct dp_soc *soc = pdev->soc;
  492. dp_rx_desc_pool_free(soc, pdev_id);
  493. qdf_spinlock_destroy(&soc->rx_desc_mutex[pdev_id]);
  494. return;
  495. }
  496. /**
  497. * dp_rx_attach() - attach DP RX
  498. * @soc: core txrx main context
  499. *
  500. * This function will attach a DP RX instance into the main
  501. * device (SOC) context. Will allocate dp rx resource and
  502. * initialize resources.
  503. *
  504. * Return: QDF_STATUS_SUCCESS: success
  505. * QDF_STATUS_E_RESOURCES: Error return
  506. */
  507. QDF_STATUS
  508. dp_rx_pdev_attach(struct dp_pdev *pdev)
  509. {
  510. uint8_t pdev_id = pdev->pdev_id;
  511. struct dp_soc *soc = pdev->soc;
  512. struct dp_srng rxdma_srng;
  513. uint32_t rxdma_entries;
  514. union dp_rx_desc_list_elem_t *desc_list = NULL;
  515. union dp_rx_desc_list_elem_t *tail = NULL;
  516. qdf_spinlock_create(&soc->rx_desc_mutex[pdev_id]);
  517. pdev = soc->pdev_list[pdev_id];
  518. rxdma_srng = pdev->rx_refill_buf_ring;
  519. rxdma_entries = rxdma_srng.alloc_size/hal_srng_get_entrysize(
  520. soc->hal_soc, RXDMA_BUF);
  521. dp_rx_desc_pool_alloc(soc, pdev_id);
  522. /* For Rx buffers, WBM release ring is SW RING 3,for all pdev's */
  523. dp_rx_buffers_replenish(soc, pdev_id, rxdma_entries,
  524. &desc_list, &tail, HAL_RX_BUF_RBM_SW3_BM);
  525. return QDF_STATUS_SUCCESS;
  526. }