dp_tx.c 115 KB

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  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #include "dp_ipa.h"
  31. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  32. #include "if_meta_hdr.h"
  33. #endif
  34. #include "enet.h"
  35. #include "dp_internal.h"
  36. #ifdef FEATURE_WDS
  37. #include "dp_txrx_wds.h"
  38. #endif
  39. #ifdef ATH_SUPPORT_IQUE
  40. #include "dp_txrx_me.h"
  41. #endif
  42. /* TODO Add support in TSO */
  43. #define DP_DESC_NUM_FRAG(x) 0
  44. /* disable TQM_BYPASS */
  45. #define TQM_BYPASS_WAR 0
  46. /* invalid peer id for reinject*/
  47. #define DP_INVALID_PEER 0XFFFE
  48. /*mapping between hal encrypt type and cdp_sec_type*/
  49. #define MAX_CDP_SEC_TYPE 12
  50. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  51. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  52. HAL_TX_ENCRYPT_TYPE_WEP_128,
  53. HAL_TX_ENCRYPT_TYPE_WEP_104,
  54. HAL_TX_ENCRYPT_TYPE_WEP_40,
  55. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  56. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  57. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  58. HAL_TX_ENCRYPT_TYPE_WAPI,
  59. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  60. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  61. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  62. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  63. #ifdef QCA_TX_LIMIT_CHECK
  64. /**
  65. * dp_tx_limit_check - Check if allocated tx descriptors reached
  66. * soc max limit and pdev max limit
  67. * @vdev: DP vdev handle
  68. *
  69. * Return: true if allocated tx descriptors reached max configured value, else
  70. * false
  71. */
  72. static inline bool
  73. dp_tx_limit_check(struct dp_vdev *vdev)
  74. {
  75. struct dp_pdev *pdev = vdev->pdev;
  76. struct dp_soc *soc = pdev->soc;
  77. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  78. soc->num_tx_allowed) {
  79. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  80. "%s: queued packets are more than max tx, drop the frame",
  81. __func__);
  82. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  83. return true;
  84. }
  85. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  86. pdev->num_tx_allowed) {
  87. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  88. "%s: queued packets are more than max tx, drop the frame",
  89. __func__);
  90. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  91. return true;
  92. }
  93. return false;
  94. }
  95. /**
  96. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  97. * @vdev: DP pdev handle
  98. *
  99. * Return: void
  100. */
  101. static inline void
  102. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  103. {
  104. struct dp_soc *soc = pdev->soc;
  105. qdf_atomic_inc(&pdev->num_tx_outstanding);
  106. qdf_atomic_inc(&soc->num_tx_outstanding);
  107. }
  108. /**
  109. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  110. * @vdev: DP pdev handle
  111. *
  112. * Return: void
  113. */
  114. static inline void
  115. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  116. {
  117. struct dp_soc *soc = pdev->soc;
  118. qdf_atomic_dec(&pdev->num_tx_outstanding);
  119. qdf_atomic_dec(&soc->num_tx_outstanding);
  120. }
  121. #else //QCA_TX_LIMIT_CHECK
  122. static inline bool
  123. dp_tx_limit_check(struct dp_vdev *vdev)
  124. {
  125. return false;
  126. }
  127. static inline void
  128. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  129. {
  130. qdf_atomic_inc(&pdev->num_tx_outstanding);
  131. }
  132. static inline void
  133. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  134. {
  135. qdf_atomic_dec(&pdev->num_tx_outstanding);
  136. }
  137. #endif //QCA_TX_LIMIT_CHECK
  138. #if defined(FEATURE_TSO)
  139. /**
  140. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  141. *
  142. * @soc - core txrx main context
  143. * @seg_desc - tso segment descriptor
  144. * @num_seg_desc - tso number segment descriptor
  145. */
  146. static void dp_tx_tso_unmap_segment(
  147. struct dp_soc *soc,
  148. struct qdf_tso_seg_elem_t *seg_desc,
  149. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  150. {
  151. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  152. if (qdf_unlikely(!seg_desc)) {
  153. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  154. __func__, __LINE__);
  155. qdf_assert(0);
  156. } else if (qdf_unlikely(!num_seg_desc)) {
  157. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  158. __func__, __LINE__);
  159. qdf_assert(0);
  160. } else {
  161. bool is_last_seg;
  162. /* no tso segment left to do dma unmap */
  163. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  164. return;
  165. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  166. true : false;
  167. qdf_nbuf_unmap_tso_segment(soc->osdev,
  168. seg_desc, is_last_seg);
  169. num_seg_desc->num_seg.tso_cmn_num_seg--;
  170. }
  171. }
  172. /**
  173. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  174. * back to the freelist
  175. *
  176. * @soc - soc device handle
  177. * @tx_desc - Tx software descriptor
  178. */
  179. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  180. struct dp_tx_desc_s *tx_desc)
  181. {
  182. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  183. if (qdf_unlikely(!tx_desc->tso_desc)) {
  184. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  185. "%s %d TSO desc is NULL!",
  186. __func__, __LINE__);
  187. qdf_assert(0);
  188. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  189. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  190. "%s %d TSO num desc is NULL!",
  191. __func__, __LINE__);
  192. qdf_assert(0);
  193. } else {
  194. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  195. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  196. /* Add the tso num segment into the free list */
  197. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  198. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  199. tx_desc->tso_num_desc);
  200. tx_desc->tso_num_desc = NULL;
  201. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  202. }
  203. /* Add the tso segment into the free list*/
  204. dp_tx_tso_desc_free(soc,
  205. tx_desc->pool_id, tx_desc->tso_desc);
  206. tx_desc->tso_desc = NULL;
  207. }
  208. }
  209. #else
  210. static void dp_tx_tso_unmap_segment(
  211. struct dp_soc *soc,
  212. struct qdf_tso_seg_elem_t *seg_desc,
  213. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  214. {
  215. }
  216. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  217. struct dp_tx_desc_s *tx_desc)
  218. {
  219. }
  220. #endif
  221. /**
  222. * dp_tx_desc_release() - Release Tx Descriptor
  223. * @tx_desc : Tx Descriptor
  224. * @desc_pool_id: Descriptor Pool ID
  225. *
  226. * Deallocate all resources attached to Tx descriptor and free the Tx
  227. * descriptor.
  228. *
  229. * Return:
  230. */
  231. static void
  232. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  233. {
  234. struct dp_pdev *pdev = tx_desc->pdev;
  235. struct dp_soc *soc;
  236. uint8_t comp_status = 0;
  237. qdf_assert(pdev);
  238. soc = pdev->soc;
  239. if (tx_desc->frm_type == dp_tx_frm_tso)
  240. dp_tx_tso_desc_release(soc, tx_desc);
  241. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  242. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  243. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  244. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  245. dp_tx_outstanding_dec(pdev);
  246. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  247. qdf_atomic_dec(&pdev->num_tx_exception);
  248. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  249. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  250. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  251. soc->hal_soc);
  252. else
  253. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  254. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  255. "Tx Completion Release desc %d status %d outstanding %d",
  256. tx_desc->id, comp_status,
  257. qdf_atomic_read(&pdev->num_tx_outstanding));
  258. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  259. return;
  260. }
  261. /**
  262. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  263. * @vdev: DP vdev Handle
  264. * @nbuf: skb
  265. * @msdu_info: msdu_info required to create HTT metadata
  266. *
  267. * Prepares and fills HTT metadata in the frame pre-header for special frames
  268. * that should be transmitted using varying transmit parameters.
  269. * There are 2 VDEV modes that currently needs this special metadata -
  270. * 1) Mesh Mode
  271. * 2) DSRC Mode
  272. *
  273. * Return: HTT metadata size
  274. *
  275. */
  276. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  277. struct dp_tx_msdu_info_s *msdu_info)
  278. {
  279. uint32_t *meta_data = msdu_info->meta_data;
  280. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  281. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  282. uint8_t htt_desc_size;
  283. /* Size rounded of multiple of 8 bytes */
  284. uint8_t htt_desc_size_aligned;
  285. uint8_t *hdr = NULL;
  286. /*
  287. * Metadata - HTT MSDU Extension header
  288. */
  289. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  290. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  291. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  292. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  293. meta_data[0])) {
  294. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  295. htt_desc_size_aligned)) {
  296. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  297. htt_desc_size_aligned);
  298. if (!nbuf) {
  299. /*
  300. * qdf_nbuf_realloc_headroom won't do skb_clone
  301. * as skb_realloc_headroom does. so, no free is
  302. * needed here.
  303. */
  304. DP_STATS_INC(vdev,
  305. tx_i.dropped.headroom_insufficient,
  306. 1);
  307. qdf_print(" %s[%d] skb_realloc_headroom failed",
  308. __func__, __LINE__);
  309. return 0;
  310. }
  311. }
  312. /* Fill and add HTT metaheader */
  313. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  314. if (!hdr) {
  315. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  316. "Error in filling HTT metadata");
  317. return 0;
  318. }
  319. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  320. } else if (vdev->opmode == wlan_op_mode_ocb) {
  321. /* Todo - Add support for DSRC */
  322. }
  323. return htt_desc_size_aligned;
  324. }
  325. /**
  326. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  327. * @tso_seg: TSO segment to process
  328. * @ext_desc: Pointer to MSDU extension descriptor
  329. *
  330. * Return: void
  331. */
  332. #if defined(FEATURE_TSO)
  333. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  334. void *ext_desc)
  335. {
  336. uint8_t num_frag;
  337. uint32_t tso_flags;
  338. /*
  339. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  340. * tcp_flag_mask
  341. *
  342. * Checksum enable flags are set in TCL descriptor and not in Extension
  343. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  344. */
  345. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  346. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  347. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  348. tso_seg->tso_flags.ip_len);
  349. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  350. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  351. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  352. uint32_t lo = 0;
  353. uint32_t hi = 0;
  354. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  355. (tso_seg->tso_frags[num_frag].length));
  356. qdf_dmaaddr_to_32s(
  357. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  358. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  359. tso_seg->tso_frags[num_frag].length);
  360. }
  361. return;
  362. }
  363. #else
  364. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  365. void *ext_desc)
  366. {
  367. return;
  368. }
  369. #endif
  370. #if defined(FEATURE_TSO)
  371. /**
  372. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  373. * allocated and free them
  374. *
  375. * @soc: soc handle
  376. * @free_seg: list of tso segments
  377. * @msdu_info: msdu descriptor
  378. *
  379. * Return - void
  380. */
  381. static void dp_tx_free_tso_seg_list(
  382. struct dp_soc *soc,
  383. struct qdf_tso_seg_elem_t *free_seg,
  384. struct dp_tx_msdu_info_s *msdu_info)
  385. {
  386. struct qdf_tso_seg_elem_t *next_seg;
  387. while (free_seg) {
  388. next_seg = free_seg->next;
  389. dp_tx_tso_desc_free(soc,
  390. msdu_info->tx_queue.desc_pool_id,
  391. free_seg);
  392. free_seg = next_seg;
  393. }
  394. }
  395. /**
  396. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  397. * allocated and free them
  398. *
  399. * @soc: soc handle
  400. * @free_num_seg: list of tso number segments
  401. * @msdu_info: msdu descriptor
  402. * Return - void
  403. */
  404. static void dp_tx_free_tso_num_seg_list(
  405. struct dp_soc *soc,
  406. struct qdf_tso_num_seg_elem_t *free_num_seg,
  407. struct dp_tx_msdu_info_s *msdu_info)
  408. {
  409. struct qdf_tso_num_seg_elem_t *next_num_seg;
  410. while (free_num_seg) {
  411. next_num_seg = free_num_seg->next;
  412. dp_tso_num_seg_free(soc,
  413. msdu_info->tx_queue.desc_pool_id,
  414. free_num_seg);
  415. free_num_seg = next_num_seg;
  416. }
  417. }
  418. /**
  419. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  420. * do dma unmap for each segment
  421. *
  422. * @soc: soc handle
  423. * @free_seg: list of tso segments
  424. * @num_seg_desc: tso number segment descriptor
  425. *
  426. * Return - void
  427. */
  428. static void dp_tx_unmap_tso_seg_list(
  429. struct dp_soc *soc,
  430. struct qdf_tso_seg_elem_t *free_seg,
  431. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  432. {
  433. struct qdf_tso_seg_elem_t *next_seg;
  434. if (qdf_unlikely(!num_seg_desc)) {
  435. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  436. return;
  437. }
  438. while (free_seg) {
  439. next_seg = free_seg->next;
  440. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  441. free_seg = next_seg;
  442. }
  443. }
  444. #ifdef FEATURE_TSO_STATS
  445. /**
  446. * dp_tso_get_stats_idx: Retrieve the tso packet id
  447. * @pdev - pdev handle
  448. *
  449. * Return: id
  450. */
  451. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  452. {
  453. uint32_t stats_idx;
  454. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  455. % CDP_MAX_TSO_PACKETS);
  456. return stats_idx;
  457. }
  458. #else
  459. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  460. {
  461. return 0;
  462. }
  463. #endif /* FEATURE_TSO_STATS */
  464. /**
  465. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  466. * free the tso segments descriptor and
  467. * tso num segments descriptor
  468. *
  469. * @soc: soc handle
  470. * @msdu_info: msdu descriptor
  471. * @tso_seg_unmap: flag to show if dma unmap is necessary
  472. *
  473. * Return - void
  474. */
  475. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  476. struct dp_tx_msdu_info_s *msdu_info,
  477. bool tso_seg_unmap)
  478. {
  479. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  480. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  481. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  482. tso_info->tso_num_seg_list;
  483. /* do dma unmap for each segment */
  484. if (tso_seg_unmap)
  485. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  486. /* free all tso number segment descriptor though looks only have 1 */
  487. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  488. /* free all tso segment descriptor */
  489. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  490. }
  491. /**
  492. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  493. * @vdev: virtual device handle
  494. * @msdu: network buffer
  495. * @msdu_info: meta data associated with the msdu
  496. *
  497. * Return: QDF_STATUS_SUCCESS success
  498. */
  499. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  500. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  501. {
  502. struct qdf_tso_seg_elem_t *tso_seg;
  503. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  504. struct dp_soc *soc = vdev->pdev->soc;
  505. struct dp_pdev *pdev = vdev->pdev;
  506. struct qdf_tso_info_t *tso_info;
  507. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  508. tso_info = &msdu_info->u.tso_info;
  509. tso_info->curr_seg = NULL;
  510. tso_info->tso_seg_list = NULL;
  511. tso_info->num_segs = num_seg;
  512. msdu_info->frm_type = dp_tx_frm_tso;
  513. tso_info->tso_num_seg_list = NULL;
  514. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  515. while (num_seg) {
  516. tso_seg = dp_tx_tso_desc_alloc(
  517. soc, msdu_info->tx_queue.desc_pool_id);
  518. if (tso_seg) {
  519. tso_seg->next = tso_info->tso_seg_list;
  520. tso_info->tso_seg_list = tso_seg;
  521. num_seg--;
  522. } else {
  523. dp_err_rl("Failed to alloc tso seg desc");
  524. DP_STATS_INC_PKT(vdev->pdev,
  525. tso_stats.tso_no_mem_dropped, 1,
  526. qdf_nbuf_len(msdu));
  527. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  528. return QDF_STATUS_E_NOMEM;
  529. }
  530. }
  531. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  532. tso_num_seg = dp_tso_num_seg_alloc(soc,
  533. msdu_info->tx_queue.desc_pool_id);
  534. if (tso_num_seg) {
  535. tso_num_seg->next = tso_info->tso_num_seg_list;
  536. tso_info->tso_num_seg_list = tso_num_seg;
  537. } else {
  538. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  539. __func__);
  540. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  541. return QDF_STATUS_E_NOMEM;
  542. }
  543. msdu_info->num_seg =
  544. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  545. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  546. msdu_info->num_seg);
  547. if (!(msdu_info->num_seg)) {
  548. /*
  549. * Free allocated TSO seg desc and number seg desc,
  550. * do unmap for segments if dma map has done.
  551. */
  552. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  553. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  554. return QDF_STATUS_E_INVAL;
  555. }
  556. tso_info->curr_seg = tso_info->tso_seg_list;
  557. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  558. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  559. msdu, msdu_info->num_seg);
  560. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  561. tso_info->msdu_stats_idx);
  562. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  563. return QDF_STATUS_SUCCESS;
  564. }
  565. #else
  566. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  567. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  568. {
  569. return QDF_STATUS_E_NOMEM;
  570. }
  571. #endif
  572. /**
  573. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  574. * @vdev: DP Vdev handle
  575. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  576. * @desc_pool_id: Descriptor Pool ID
  577. *
  578. * Return:
  579. */
  580. static
  581. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  582. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  583. {
  584. uint8_t i;
  585. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  586. struct dp_tx_seg_info_s *seg_info;
  587. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  588. struct dp_soc *soc = vdev->pdev->soc;
  589. /* Allocate an extension descriptor */
  590. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  591. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  592. if (!msdu_ext_desc) {
  593. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  594. return NULL;
  595. }
  596. if (msdu_info->exception_fw &&
  597. qdf_unlikely(vdev->mesh_vdev)) {
  598. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  599. &msdu_info->meta_data[0],
  600. sizeof(struct htt_tx_msdu_desc_ext2_t));
  601. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  602. }
  603. switch (msdu_info->frm_type) {
  604. case dp_tx_frm_sg:
  605. case dp_tx_frm_me:
  606. case dp_tx_frm_raw:
  607. seg_info = msdu_info->u.sg_info.curr_seg;
  608. /* Update the buffer pointers in MSDU Extension Descriptor */
  609. for (i = 0; i < seg_info->frag_cnt; i++) {
  610. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  611. seg_info->frags[i].paddr_lo,
  612. seg_info->frags[i].paddr_hi,
  613. seg_info->frags[i].len);
  614. }
  615. break;
  616. case dp_tx_frm_tso:
  617. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  618. &cached_ext_desc[0]);
  619. break;
  620. default:
  621. break;
  622. }
  623. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  624. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  625. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  626. msdu_ext_desc->vaddr);
  627. return msdu_ext_desc;
  628. }
  629. /**
  630. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  631. *
  632. * @skb: skb to be traced
  633. * @msdu_id: msdu_id of the packet
  634. * @vdev_id: vdev_id of the packet
  635. *
  636. * Return: None
  637. */
  638. #ifdef DP_DISABLE_TX_PKT_TRACE
  639. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  640. uint8_t vdev_id)
  641. {
  642. }
  643. #else
  644. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  645. uint8_t vdev_id)
  646. {
  647. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  648. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  649. DPTRACE(qdf_dp_trace_ptr(skb,
  650. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  651. QDF_TRACE_DEFAULT_PDEV_ID,
  652. qdf_nbuf_data_addr(skb),
  653. sizeof(qdf_nbuf_data(skb)),
  654. msdu_id, vdev_id));
  655. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  656. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  657. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  658. msdu_id, QDF_TX));
  659. }
  660. #endif
  661. /**
  662. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  663. * @vdev: DP vdev handle
  664. * @nbuf: skb
  665. * @desc_pool_id: Descriptor pool ID
  666. * @meta_data: Metadata to the fw
  667. * @tx_exc_metadata: Handle that holds exception path metadata
  668. * Allocate and prepare Tx descriptor with msdu information.
  669. *
  670. * Return: Pointer to Tx Descriptor on success,
  671. * NULL on failure
  672. */
  673. static
  674. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  675. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  676. struct dp_tx_msdu_info_s *msdu_info,
  677. struct cdp_tx_exception_metadata *tx_exc_metadata)
  678. {
  679. uint8_t align_pad;
  680. uint8_t is_exception = 0;
  681. uint8_t htt_hdr_size;
  682. qdf_ether_header_t *eh;
  683. struct dp_tx_desc_s *tx_desc;
  684. struct dp_pdev *pdev = vdev->pdev;
  685. struct dp_soc *soc = pdev->soc;
  686. if (dp_tx_limit_check(vdev))
  687. return NULL;
  688. /* Allocate software Tx descriptor */
  689. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  690. if (qdf_unlikely(!tx_desc)) {
  691. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  692. return NULL;
  693. }
  694. dp_tx_outstanding_inc(pdev);
  695. /* Initialize the SW tx descriptor */
  696. tx_desc->nbuf = nbuf;
  697. tx_desc->frm_type = dp_tx_frm_std;
  698. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  699. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  700. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  701. tx_desc->vdev = vdev;
  702. tx_desc->pdev = pdev;
  703. tx_desc->msdu_ext_desc = NULL;
  704. tx_desc->pkt_offset = 0;
  705. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  706. if (qdf_unlikely(vdev->multipass_en)) {
  707. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  708. goto failure;
  709. }
  710. /*
  711. * For special modes (vdev_type == ocb or mesh), data frames should be
  712. * transmitted using varying transmit parameters (tx spec) which include
  713. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  714. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  715. * These frames are sent as exception packets to firmware.
  716. *
  717. * HW requirement is that metadata should always point to a
  718. * 8-byte aligned address. So we add alignment pad to start of buffer.
  719. * HTT Metadata should be ensured to be multiple of 8-bytes,
  720. * to get 8-byte aligned start address along with align_pad added
  721. *
  722. * |-----------------------------|
  723. * | |
  724. * |-----------------------------| <-----Buffer Pointer Address given
  725. * | | ^ in HW descriptor (aligned)
  726. * | HTT Metadata | |
  727. * | | |
  728. * | | | Packet Offset given in descriptor
  729. * | | |
  730. * |-----------------------------| |
  731. * | Alignment Pad | v
  732. * |-----------------------------| <----- Actual buffer start address
  733. * | SKB Data | (Unaligned)
  734. * | |
  735. * | |
  736. * | |
  737. * | |
  738. * | |
  739. * |-----------------------------|
  740. */
  741. if (qdf_unlikely((msdu_info->exception_fw)) ||
  742. (vdev->opmode == wlan_op_mode_ocb) ||
  743. (tx_exc_metadata &&
  744. tx_exc_metadata->is_tx_sniffer)) {
  745. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  746. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  747. DP_STATS_INC(vdev,
  748. tx_i.dropped.headroom_insufficient, 1);
  749. goto failure;
  750. }
  751. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  752. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  753. "qdf_nbuf_push_head failed");
  754. goto failure;
  755. }
  756. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  757. msdu_info);
  758. if (htt_hdr_size == 0)
  759. goto failure;
  760. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  761. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  762. is_exception = 1;
  763. }
  764. if (qdf_unlikely(vdev->nawds_enabled)) {
  765. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  766. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  767. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  768. is_exception = 1;
  769. }
  770. }
  771. #if !TQM_BYPASS_WAR
  772. if (is_exception || tx_exc_metadata)
  773. #endif
  774. {
  775. /* Temporary WAR due to TQM VP issues */
  776. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  777. qdf_atomic_inc(&pdev->num_tx_exception);
  778. }
  779. return tx_desc;
  780. failure:
  781. dp_tx_desc_release(tx_desc, desc_pool_id);
  782. return NULL;
  783. }
  784. /**
  785. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  786. * @vdev: DP vdev handle
  787. * @nbuf: skb
  788. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  789. * @desc_pool_id : Descriptor Pool ID
  790. *
  791. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  792. * information. For frames wth fragments, allocate and prepare
  793. * an MSDU extension descriptor
  794. *
  795. * Return: Pointer to Tx Descriptor on success,
  796. * NULL on failure
  797. */
  798. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  799. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  800. uint8_t desc_pool_id)
  801. {
  802. struct dp_tx_desc_s *tx_desc;
  803. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  804. struct dp_pdev *pdev = vdev->pdev;
  805. struct dp_soc *soc = pdev->soc;
  806. if (dp_tx_limit_check(vdev))
  807. return NULL;
  808. /* Allocate software Tx descriptor */
  809. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  810. if (!tx_desc) {
  811. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  812. return NULL;
  813. }
  814. dp_tx_outstanding_inc(pdev);
  815. /* Initialize the SW tx descriptor */
  816. tx_desc->nbuf = nbuf;
  817. tx_desc->frm_type = msdu_info->frm_type;
  818. tx_desc->tx_encap_type = vdev->tx_encap_type;
  819. tx_desc->vdev = vdev;
  820. tx_desc->pdev = pdev;
  821. tx_desc->pkt_offset = 0;
  822. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  823. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  824. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  825. /* Handle scattered frames - TSO/SG/ME */
  826. /* Allocate and prepare an extension descriptor for scattered frames */
  827. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  828. if (!msdu_ext_desc) {
  829. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  830. "%s Tx Extension Descriptor Alloc Fail",
  831. __func__);
  832. goto failure;
  833. }
  834. #if TQM_BYPASS_WAR
  835. /* Temporary WAR due to TQM VP issues */
  836. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  837. qdf_atomic_inc(&pdev->num_tx_exception);
  838. #endif
  839. if (qdf_unlikely(msdu_info->exception_fw))
  840. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  841. tx_desc->msdu_ext_desc = msdu_ext_desc;
  842. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  843. return tx_desc;
  844. failure:
  845. dp_tx_desc_release(tx_desc, desc_pool_id);
  846. return NULL;
  847. }
  848. /**
  849. * dp_tx_prepare_raw() - Prepare RAW packet TX
  850. * @vdev: DP vdev handle
  851. * @nbuf: buffer pointer
  852. * @seg_info: Pointer to Segment info Descriptor to be prepared
  853. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  854. * descriptor
  855. *
  856. * Return:
  857. */
  858. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  859. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  860. {
  861. qdf_nbuf_t curr_nbuf = NULL;
  862. uint16_t total_len = 0;
  863. qdf_dma_addr_t paddr;
  864. int32_t i;
  865. int32_t mapped_buf_num = 0;
  866. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  867. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  868. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  869. /* Continue only if frames are of DATA type */
  870. if (!DP_FRAME_IS_DATA(qos_wh)) {
  871. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  872. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  873. "Pkt. recd is of not data type");
  874. goto error;
  875. }
  876. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  877. if (vdev->raw_mode_war &&
  878. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  879. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  880. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  881. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  882. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  883. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  884. QDF_DMA_TO_DEVICE)) {
  885. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  886. "%s dma map error ", __func__);
  887. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  888. mapped_buf_num = i;
  889. goto error;
  890. }
  891. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  892. seg_info->frags[i].paddr_lo = paddr;
  893. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  894. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  895. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  896. total_len += qdf_nbuf_len(curr_nbuf);
  897. }
  898. seg_info->frag_cnt = i;
  899. seg_info->total_len = total_len;
  900. seg_info->next = NULL;
  901. sg_info->curr_seg = seg_info;
  902. msdu_info->frm_type = dp_tx_frm_raw;
  903. msdu_info->num_seg = 1;
  904. return nbuf;
  905. error:
  906. i = 0;
  907. while (nbuf) {
  908. curr_nbuf = nbuf;
  909. if (i < mapped_buf_num) {
  910. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  911. i++;
  912. }
  913. nbuf = qdf_nbuf_next(nbuf);
  914. qdf_nbuf_free(curr_nbuf);
  915. }
  916. return NULL;
  917. }
  918. /**
  919. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  920. * @soc: DP soc handle
  921. * @nbuf: Buffer pointer
  922. *
  923. * unmap the chain of nbufs that belong to this RAW frame.
  924. *
  925. * Return: None
  926. */
  927. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  928. qdf_nbuf_t nbuf)
  929. {
  930. qdf_nbuf_t cur_nbuf = nbuf;
  931. do {
  932. qdf_nbuf_unmap(soc->osdev, cur_nbuf, QDF_DMA_TO_DEVICE);
  933. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  934. } while (cur_nbuf);
  935. }
  936. #ifdef VDEV_PEER_PROTOCOL_COUNT
  937. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, nbuf) \
  938. { \
  939. qdf_nbuf_t nbuf_local; \
  940. struct dp_vdev *vdev_local = vdev_hdl; \
  941. do { \
  942. if (qdf_likely(!((vdev_local)->peer_protocol_count_track))) \
  943. break; \
  944. nbuf_local = nbuf; \
  945. if (qdf_unlikely(((vdev_local)->tx_encap_type) == \
  946. htt_cmn_pkt_type_raw)) \
  947. break; \
  948. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local)))) \
  949. break; \
  950. else if (qdf_nbuf_is_tso((nbuf_local))) \
  951. break; \
  952. dp_vdev_peer_stats_update_protocol_cnt((vdev_local), \
  953. (nbuf_local), \
  954. NULL, 1, 0); \
  955. } while (0); \
  956. }
  957. #else
  958. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, skb)
  959. #endif
  960. /**
  961. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  962. * @soc: DP Soc Handle
  963. * @vdev: DP vdev handle
  964. * @tx_desc: Tx Descriptor Handle
  965. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  966. * @fw_metadata: Metadata to send to Target Firmware along with frame
  967. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  968. * @tx_exc_metadata: Handle that holds exception path meta data
  969. *
  970. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  971. * from software Tx descriptor
  972. *
  973. * Return: QDF_STATUS_SUCCESS: success
  974. * QDF_STATUS_E_RESOURCES: Error return
  975. */
  976. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  977. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  978. uint16_t fw_metadata, uint8_t ring_id,
  979. struct cdp_tx_exception_metadata
  980. *tx_exc_metadata)
  981. {
  982. uint8_t type;
  983. uint16_t length;
  984. void *hal_tx_desc;
  985. uint32_t *hal_tx_desc_cached;
  986. qdf_dma_addr_t dma_addr;
  987. /*
  988. * Setting it initialization statically here to avoid
  989. * a memset call jump with qdf_mem_set call
  990. */
  991. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  992. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  993. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  994. tx_exc_metadata->sec_type : vdev->sec_type);
  995. /* Return Buffer Manager ID */
  996. uint8_t bm_id = ring_id;
  997. hal_ring_handle_t hal_ring_hdl = soc->tcl_data_ring[ring_id].hal_srng;
  998. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  999. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  1000. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1001. return QDF_STATUS_E_RESOURCES;
  1002. }
  1003. hal_tx_desc_cached = (void *) cached_desc;
  1004. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  1005. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1006. type = HAL_TX_BUF_TYPE_EXT_DESC;
  1007. dma_addr = tx_desc->msdu_ext_desc->paddr;
  1008. } else {
  1009. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  1010. type = HAL_TX_BUF_TYPE_BUFFER;
  1011. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1012. }
  1013. qdf_assert_always(dma_addr);
  1014. hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
  1015. dma_addr, bm_id, tx_desc->id,
  1016. type);
  1017. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  1018. vdev->lmac_id);
  1019. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  1020. vdev->search_type);
  1021. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  1022. vdev->bss_ast_idx);
  1023. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  1024. vdev->dscp_tid_map_id);
  1025. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  1026. sec_type_map[sec_type]);
  1027. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1028. (vdev->bss_ast_hash & 0xF));
  1029. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1030. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  1031. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1032. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  1033. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  1034. vdev->hal_desc_addr_search_flags);
  1035. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1036. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1037. /* verify checksum offload configuration*/
  1038. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  1039. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  1040. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  1041. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1042. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1043. }
  1044. if (tid != HTT_TX_EXT_TID_INVALID)
  1045. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1046. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  1047. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  1048. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  1049. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  1050. length, type, (uint64_t)dma_addr,
  1051. tx_desc->pkt_offset, tx_desc->id);
  1052. hal_ring_hdl = soc->tcl_data_ring[ring_id].hal_srng;
  1053. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_ring_hdl))) {
  1054. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1055. "%s %d : HAL RING Access Failed -- %pK",
  1056. __func__, __LINE__, hal_ring_hdl);
  1057. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1058. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1059. return status;
  1060. }
  1061. /* Sync cached descriptor with HW */
  1062. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1063. if (qdf_unlikely(!hal_tx_desc)) {
  1064. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1065. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1066. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1067. goto ring_access_fail;
  1068. }
  1069. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1070. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1071. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  1072. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  1073. status = QDF_STATUS_SUCCESS;
  1074. ring_access_fail:
  1075. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1076. hal_srng_access_end(soc->hal_soc, hal_ring_hdl);
  1077. hif_pm_runtime_put(soc->hif_handle);
  1078. } else {
  1079. hal_srng_access_end_reap(soc->hal_soc, hal_ring_hdl);
  1080. }
  1081. return status;
  1082. }
  1083. /**
  1084. * dp_cce_classify() - Classify the frame based on CCE rules
  1085. * @vdev: DP vdev handle
  1086. * @nbuf: skb
  1087. *
  1088. * Classify frames based on CCE rules
  1089. * Return: bool( true if classified,
  1090. * else false)
  1091. */
  1092. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1093. {
  1094. qdf_ether_header_t *eh = NULL;
  1095. uint16_t ether_type;
  1096. qdf_llc_t *llcHdr;
  1097. qdf_nbuf_t nbuf_clone = NULL;
  1098. qdf_dot3_qosframe_t *qos_wh = NULL;
  1099. /* for mesh packets don't do any classification */
  1100. if (qdf_unlikely(vdev->mesh_vdev))
  1101. return false;
  1102. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1103. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1104. ether_type = eh->ether_type;
  1105. llcHdr = (qdf_llc_t *)(nbuf->data +
  1106. sizeof(qdf_ether_header_t));
  1107. } else {
  1108. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1109. /* For encrypted packets don't do any classification */
  1110. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1111. return false;
  1112. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1113. if (qdf_unlikely(
  1114. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1115. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1116. ether_type = *(uint16_t *)(nbuf->data
  1117. + QDF_IEEE80211_4ADDR_HDR_LEN
  1118. + sizeof(qdf_llc_t)
  1119. - sizeof(ether_type));
  1120. llcHdr = (qdf_llc_t *)(nbuf->data +
  1121. QDF_IEEE80211_4ADDR_HDR_LEN);
  1122. } else {
  1123. ether_type = *(uint16_t *)(nbuf->data
  1124. + QDF_IEEE80211_3ADDR_HDR_LEN
  1125. + sizeof(qdf_llc_t)
  1126. - sizeof(ether_type));
  1127. llcHdr = (qdf_llc_t *)(nbuf->data +
  1128. QDF_IEEE80211_3ADDR_HDR_LEN);
  1129. }
  1130. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1131. && (ether_type ==
  1132. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1133. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1134. return true;
  1135. }
  1136. }
  1137. return false;
  1138. }
  1139. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1140. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1141. sizeof(*llcHdr));
  1142. nbuf_clone = qdf_nbuf_clone(nbuf);
  1143. if (qdf_unlikely(nbuf_clone)) {
  1144. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1145. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1146. qdf_nbuf_pull_head(nbuf_clone,
  1147. sizeof(qdf_net_vlanhdr_t));
  1148. }
  1149. }
  1150. } else {
  1151. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1152. nbuf_clone = qdf_nbuf_clone(nbuf);
  1153. if (qdf_unlikely(nbuf_clone)) {
  1154. qdf_nbuf_pull_head(nbuf_clone,
  1155. sizeof(qdf_net_vlanhdr_t));
  1156. }
  1157. }
  1158. }
  1159. if (qdf_unlikely(nbuf_clone))
  1160. nbuf = nbuf_clone;
  1161. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1162. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1163. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1164. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1165. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1166. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1167. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1168. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1169. if (qdf_unlikely(nbuf_clone))
  1170. qdf_nbuf_free(nbuf_clone);
  1171. return true;
  1172. }
  1173. if (qdf_unlikely(nbuf_clone))
  1174. qdf_nbuf_free(nbuf_clone);
  1175. return false;
  1176. }
  1177. /**
  1178. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1179. * @vdev: DP vdev handle
  1180. * @nbuf: skb
  1181. *
  1182. * Extract the DSCP or PCP information from frame and map into TID value.
  1183. *
  1184. * Return: void
  1185. */
  1186. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1187. struct dp_tx_msdu_info_s *msdu_info)
  1188. {
  1189. uint8_t tos = 0, dscp_tid_override = 0;
  1190. uint8_t *hdr_ptr, *L3datap;
  1191. uint8_t is_mcast = 0;
  1192. qdf_ether_header_t *eh = NULL;
  1193. qdf_ethervlan_header_t *evh = NULL;
  1194. uint16_t ether_type;
  1195. qdf_llc_t *llcHdr;
  1196. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1197. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1198. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1199. eh = (qdf_ether_header_t *)nbuf->data;
  1200. hdr_ptr = eh->ether_dhost;
  1201. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1202. } else {
  1203. qdf_dot3_qosframe_t *qos_wh =
  1204. (qdf_dot3_qosframe_t *) nbuf->data;
  1205. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1206. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1207. return;
  1208. }
  1209. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1210. ether_type = eh->ether_type;
  1211. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1212. /*
  1213. * Check if packet is dot3 or eth2 type.
  1214. */
  1215. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1216. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1217. sizeof(*llcHdr));
  1218. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1219. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1220. sizeof(*llcHdr);
  1221. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1222. + sizeof(*llcHdr) +
  1223. sizeof(qdf_net_vlanhdr_t));
  1224. } else {
  1225. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1226. sizeof(*llcHdr);
  1227. }
  1228. } else {
  1229. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1230. evh = (qdf_ethervlan_header_t *) eh;
  1231. ether_type = evh->ether_type;
  1232. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1233. }
  1234. }
  1235. /*
  1236. * Find priority from IP TOS DSCP field
  1237. */
  1238. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1239. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1240. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1241. /* Only for unicast frames */
  1242. if (!is_mcast) {
  1243. /* send it on VO queue */
  1244. msdu_info->tid = DP_VO_TID;
  1245. }
  1246. } else {
  1247. /*
  1248. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1249. * from TOS byte.
  1250. */
  1251. tos = ip->ip_tos;
  1252. dscp_tid_override = 1;
  1253. }
  1254. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1255. /* TODO
  1256. * use flowlabel
  1257. *igmpmld cases to be handled in phase 2
  1258. */
  1259. unsigned long ver_pri_flowlabel;
  1260. unsigned long pri;
  1261. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1262. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1263. DP_IPV6_PRIORITY_SHIFT;
  1264. tos = pri;
  1265. dscp_tid_override = 1;
  1266. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1267. msdu_info->tid = DP_VO_TID;
  1268. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1269. /* Only for unicast frames */
  1270. if (!is_mcast) {
  1271. /* send ucast arp on VO queue */
  1272. msdu_info->tid = DP_VO_TID;
  1273. }
  1274. }
  1275. /*
  1276. * Assign all MCAST packets to BE
  1277. */
  1278. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1279. if (is_mcast) {
  1280. tos = 0;
  1281. dscp_tid_override = 1;
  1282. }
  1283. }
  1284. if (dscp_tid_override == 1) {
  1285. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1286. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1287. }
  1288. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1289. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1290. return;
  1291. }
  1292. /**
  1293. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1294. * @vdev: DP vdev handle
  1295. * @nbuf: skb
  1296. *
  1297. * Software based TID classification is required when more than 2 DSCP-TID
  1298. * mapping tables are needed.
  1299. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1300. *
  1301. * Return: void
  1302. */
  1303. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1304. struct dp_tx_msdu_info_s *msdu_info)
  1305. {
  1306. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1307. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1308. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1309. return;
  1310. /* for mesh packets don't do any classification */
  1311. if (qdf_unlikely(vdev->mesh_vdev))
  1312. return;
  1313. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1314. }
  1315. #ifdef FEATURE_WLAN_TDLS
  1316. /**
  1317. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1318. * @tx_desc: TX descriptor
  1319. *
  1320. * Return: None
  1321. */
  1322. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1323. {
  1324. if (tx_desc->vdev) {
  1325. if (tx_desc->vdev->is_tdls_frame) {
  1326. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1327. tx_desc->vdev->is_tdls_frame = false;
  1328. }
  1329. }
  1330. }
  1331. /**
  1332. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1333. * @tx_desc: TX descriptor
  1334. * @vdev: datapath vdev handle
  1335. *
  1336. * Return: None
  1337. */
  1338. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1339. struct dp_vdev *vdev)
  1340. {
  1341. struct hal_tx_completion_status ts = {0};
  1342. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1343. if (qdf_unlikely(!vdev)) {
  1344. dp_err("vdev is null!");
  1345. return;
  1346. }
  1347. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1348. if (vdev->tx_non_std_data_callback.func) {
  1349. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1350. vdev->tx_non_std_data_callback.func(
  1351. vdev->tx_non_std_data_callback.ctxt,
  1352. nbuf, ts.status);
  1353. return;
  1354. }
  1355. }
  1356. #else
  1357. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1358. {
  1359. }
  1360. static inline void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1361. struct dp_vdev *vdev)
  1362. {
  1363. }
  1364. #endif
  1365. /**
  1366. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1367. * @vdev: DP vdev handle
  1368. * @nbuf: skb
  1369. *
  1370. * Return: 1 if frame needs to be dropped else 0
  1371. */
  1372. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1373. {
  1374. struct dp_pdev *pdev = NULL;
  1375. struct dp_ast_entry *src_ast_entry = NULL;
  1376. struct dp_ast_entry *dst_ast_entry = NULL;
  1377. struct dp_soc *soc = NULL;
  1378. qdf_assert(vdev);
  1379. pdev = vdev->pdev;
  1380. qdf_assert(pdev);
  1381. soc = pdev->soc;
  1382. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1383. (soc, dstmac, vdev->pdev->pdev_id);
  1384. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1385. (soc, srcmac, vdev->pdev->pdev_id);
  1386. if (dst_ast_entry && src_ast_entry) {
  1387. if (dst_ast_entry->peer->peer_ids[0] ==
  1388. src_ast_entry->peer->peer_ids[0])
  1389. return 1;
  1390. }
  1391. return 0;
  1392. }
  1393. /**
  1394. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1395. * @vdev: DP vdev handle
  1396. * @nbuf: skb
  1397. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1398. * @meta_data: Metadata to the fw
  1399. * @tx_q: Tx queue to be used for this Tx frame
  1400. * @peer_id: peer_id of the peer in case of NAWDS frames
  1401. * @tx_exc_metadata: Handle that holds exception path metadata
  1402. *
  1403. * Return: NULL on success,
  1404. * nbuf when it fails to send
  1405. */
  1406. qdf_nbuf_t
  1407. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1408. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1409. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1410. {
  1411. struct dp_pdev *pdev = vdev->pdev;
  1412. struct dp_soc *soc = pdev->soc;
  1413. struct dp_tx_desc_s *tx_desc;
  1414. QDF_STATUS status;
  1415. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1416. uint16_t htt_tcl_metadata = 0;
  1417. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1418. uint8_t tid = msdu_info->tid;
  1419. struct cdp_tid_tx_stats *tid_stats = NULL;
  1420. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1421. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1422. msdu_info, tx_exc_metadata);
  1423. if (!tx_desc) {
  1424. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1425. vdev, tx_q->desc_pool_id);
  1426. drop_code = TX_DESC_ERR;
  1427. goto fail_return;
  1428. }
  1429. if (qdf_unlikely(soc->cce_disable)) {
  1430. if (dp_cce_classify(vdev, nbuf) == true) {
  1431. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1432. tid = DP_VO_TID;
  1433. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1434. }
  1435. }
  1436. dp_tx_update_tdls_flags(tx_desc);
  1437. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1438. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1439. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1440. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1441. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1442. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1443. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1444. peer_id);
  1445. } else
  1446. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1447. if (msdu_info->exception_fw) {
  1448. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1449. }
  1450. if (qdf_unlikely(qdf_nbuf_map(soc->osdev, nbuf,
  1451. QDF_DMA_TO_DEVICE)
  1452. != QDF_STATUS_SUCCESS)) {
  1453. /* Handle failure */
  1454. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1455. "qdf_nbuf_map failed");
  1456. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1457. drop_code = TX_DMA_MAP_ERR;
  1458. goto release_desc;
  1459. }
  1460. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1461. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1462. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1463. if (status != QDF_STATUS_SUCCESS) {
  1464. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1465. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1466. __func__, tx_desc, tx_q->ring_id);
  1467. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1468. drop_code = TX_HW_ENQUEUE;
  1469. goto release_desc;
  1470. }
  1471. return NULL;
  1472. release_desc:
  1473. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1474. fail_return:
  1475. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1476. tid_stats = &pdev->stats.tid_stats.
  1477. tid_tx_stats[tx_q->ring_id][tid];
  1478. tid_stats->swdrop_cnt[drop_code]++;
  1479. return nbuf;
  1480. }
  1481. /**
  1482. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1483. * @vdev: DP vdev handle
  1484. * @nbuf: skb
  1485. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1486. *
  1487. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1488. *
  1489. * Return: NULL on success,
  1490. * nbuf when it fails to send
  1491. */
  1492. #if QDF_LOCK_STATS
  1493. noinline
  1494. #else
  1495. #endif
  1496. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1497. struct dp_tx_msdu_info_s *msdu_info)
  1498. {
  1499. uint8_t i;
  1500. struct dp_pdev *pdev = vdev->pdev;
  1501. struct dp_soc *soc = pdev->soc;
  1502. struct dp_tx_desc_s *tx_desc;
  1503. bool is_cce_classified = false;
  1504. QDF_STATUS status;
  1505. uint16_t htt_tcl_metadata = 0;
  1506. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1507. struct cdp_tid_tx_stats *tid_stats = NULL;
  1508. if (qdf_unlikely(soc->cce_disable)) {
  1509. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1510. if (is_cce_classified) {
  1511. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1512. msdu_info->tid = DP_VO_TID;
  1513. }
  1514. }
  1515. if (msdu_info->frm_type == dp_tx_frm_me)
  1516. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1517. i = 0;
  1518. /* Print statement to track i and num_seg */
  1519. /*
  1520. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1521. * descriptors using information in msdu_info
  1522. */
  1523. while (i < msdu_info->num_seg) {
  1524. /*
  1525. * Setup Tx descriptor for an MSDU, and MSDU extension
  1526. * descriptor
  1527. */
  1528. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1529. tx_q->desc_pool_id);
  1530. if (!tx_desc) {
  1531. if (msdu_info->frm_type == dp_tx_frm_me) {
  1532. dp_tx_me_free_buf(pdev,
  1533. (void *)(msdu_info->u.sg_info
  1534. .curr_seg->frags[0].vaddr));
  1535. i++;
  1536. continue;
  1537. }
  1538. goto done;
  1539. }
  1540. if (msdu_info->frm_type == dp_tx_frm_me) {
  1541. tx_desc->me_buffer =
  1542. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1543. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1544. }
  1545. if (is_cce_classified)
  1546. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1547. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1548. if (msdu_info->exception_fw) {
  1549. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1550. }
  1551. /*
  1552. * Enqueue the Tx MSDU descriptor to HW for transmit
  1553. */
  1554. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1555. htt_tcl_metadata, tx_q->ring_id, NULL);
  1556. if (status != QDF_STATUS_SUCCESS) {
  1557. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1558. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1559. __func__, tx_desc, tx_q->ring_id);
  1560. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1561. tid_stats = &pdev->stats.tid_stats.
  1562. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1563. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1564. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1565. if (msdu_info->frm_type == dp_tx_frm_me) {
  1566. i++;
  1567. continue;
  1568. }
  1569. goto done;
  1570. }
  1571. /*
  1572. * TODO
  1573. * if tso_info structure can be modified to have curr_seg
  1574. * as first element, following 2 blocks of code (for TSO and SG)
  1575. * can be combined into 1
  1576. */
  1577. /*
  1578. * For frames with multiple segments (TSO, ME), jump to next
  1579. * segment.
  1580. */
  1581. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1582. if (msdu_info->u.tso_info.curr_seg->next) {
  1583. msdu_info->u.tso_info.curr_seg =
  1584. msdu_info->u.tso_info.curr_seg->next;
  1585. /*
  1586. * If this is a jumbo nbuf, then increment the number of
  1587. * nbuf users for each additional segment of the msdu.
  1588. * This will ensure that the skb is freed only after
  1589. * receiving tx completion for all segments of an nbuf
  1590. */
  1591. qdf_nbuf_inc_users(nbuf);
  1592. /* Check with MCL if this is needed */
  1593. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1594. }
  1595. }
  1596. /*
  1597. * For Multicast-Unicast converted packets,
  1598. * each converted frame (for a client) is represented as
  1599. * 1 segment
  1600. */
  1601. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1602. (msdu_info->frm_type == dp_tx_frm_me)) {
  1603. if (msdu_info->u.sg_info.curr_seg->next) {
  1604. msdu_info->u.sg_info.curr_seg =
  1605. msdu_info->u.sg_info.curr_seg->next;
  1606. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1607. }
  1608. }
  1609. i++;
  1610. }
  1611. nbuf = NULL;
  1612. done:
  1613. return nbuf;
  1614. }
  1615. /**
  1616. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1617. * for SG frames
  1618. * @vdev: DP vdev handle
  1619. * @nbuf: skb
  1620. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1621. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1622. *
  1623. * Return: NULL on success,
  1624. * nbuf when it fails to send
  1625. */
  1626. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1627. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1628. {
  1629. uint32_t cur_frag, nr_frags;
  1630. qdf_dma_addr_t paddr;
  1631. struct dp_tx_sg_info_s *sg_info;
  1632. sg_info = &msdu_info->u.sg_info;
  1633. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1634. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1635. QDF_DMA_TO_DEVICE)) {
  1636. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1637. "dma map error");
  1638. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1639. qdf_nbuf_free(nbuf);
  1640. return NULL;
  1641. }
  1642. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  1643. seg_info->frags[0].paddr_lo = paddr;
  1644. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1645. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1646. seg_info->frags[0].vaddr = (void *) nbuf;
  1647. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1648. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1649. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1650. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1651. "frag dma map error");
  1652. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1653. qdf_nbuf_free(nbuf);
  1654. return NULL;
  1655. }
  1656. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  1657. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1658. seg_info->frags[cur_frag + 1].paddr_hi =
  1659. ((uint64_t) paddr) >> 32;
  1660. seg_info->frags[cur_frag + 1].len =
  1661. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1662. }
  1663. seg_info->frag_cnt = (cur_frag + 1);
  1664. seg_info->total_len = qdf_nbuf_len(nbuf);
  1665. seg_info->next = NULL;
  1666. sg_info->curr_seg = seg_info;
  1667. msdu_info->frm_type = dp_tx_frm_sg;
  1668. msdu_info->num_seg = 1;
  1669. return nbuf;
  1670. }
  1671. /**
  1672. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  1673. * @vdev: DP vdev handle
  1674. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1675. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  1676. *
  1677. * Return: NULL on failure,
  1678. * nbuf when extracted successfully
  1679. */
  1680. static
  1681. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  1682. struct dp_tx_msdu_info_s *msdu_info,
  1683. uint16_t ppdu_cookie)
  1684. {
  1685. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1686. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1687. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1688. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  1689. (msdu_info->meta_data[5], 1);
  1690. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  1691. (msdu_info->meta_data[5], 1);
  1692. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  1693. (msdu_info->meta_data[6], ppdu_cookie);
  1694. msdu_info->exception_fw = 1;
  1695. msdu_info->is_tx_sniffer = 1;
  1696. }
  1697. #ifdef MESH_MODE_SUPPORT
  1698. /**
  1699. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1700. and prepare msdu_info for mesh frames.
  1701. * @vdev: DP vdev handle
  1702. * @nbuf: skb
  1703. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1704. *
  1705. * Return: NULL on failure,
  1706. * nbuf when extracted successfully
  1707. */
  1708. static
  1709. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1710. struct dp_tx_msdu_info_s *msdu_info)
  1711. {
  1712. struct meta_hdr_s *mhdr;
  1713. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1714. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1715. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1716. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1717. msdu_info->exception_fw = 0;
  1718. goto remove_meta_hdr;
  1719. }
  1720. msdu_info->exception_fw = 1;
  1721. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1722. meta_data->host_tx_desc_pool = 1;
  1723. meta_data->update_peer_cache = 1;
  1724. meta_data->learning_frame = 1;
  1725. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1726. meta_data->power = mhdr->power;
  1727. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1728. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1729. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1730. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1731. meta_data->dyn_bw = 1;
  1732. meta_data->valid_pwr = 1;
  1733. meta_data->valid_mcs_mask = 1;
  1734. meta_data->valid_nss_mask = 1;
  1735. meta_data->valid_preamble_type = 1;
  1736. meta_data->valid_retries = 1;
  1737. meta_data->valid_bw_info = 1;
  1738. }
  1739. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1740. meta_data->encrypt_type = 0;
  1741. meta_data->valid_encrypt_type = 1;
  1742. meta_data->learning_frame = 0;
  1743. }
  1744. meta_data->valid_key_flags = 1;
  1745. meta_data->key_flags = (mhdr->keyix & 0x3);
  1746. remove_meta_hdr:
  1747. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1748. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1749. "qdf_nbuf_pull_head failed");
  1750. qdf_nbuf_free(nbuf);
  1751. return NULL;
  1752. }
  1753. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1754. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1755. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1756. " tid %d to_fw %d",
  1757. __func__, msdu_info->meta_data[0],
  1758. msdu_info->meta_data[1],
  1759. msdu_info->meta_data[2],
  1760. msdu_info->meta_data[3],
  1761. msdu_info->meta_data[4],
  1762. msdu_info->meta_data[5],
  1763. msdu_info->tid, msdu_info->exception_fw);
  1764. return nbuf;
  1765. }
  1766. #else
  1767. static
  1768. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1769. struct dp_tx_msdu_info_s *msdu_info)
  1770. {
  1771. return nbuf;
  1772. }
  1773. #endif
  1774. /**
  1775. * dp_check_exc_metadata() - Checks if parameters are valid
  1776. * @tx_exc - holds all exception path parameters
  1777. *
  1778. * Returns true when all the parameters are valid else false
  1779. *
  1780. */
  1781. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1782. {
  1783. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1784. HTT_INVALID_TID);
  1785. bool invalid_encap_type =
  1786. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  1787. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  1788. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  1789. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  1790. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  1791. tx_exc->ppdu_cookie == 0);
  1792. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  1793. invalid_cookie) {
  1794. return false;
  1795. }
  1796. return true;
  1797. }
  1798. /**
  1799. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1800. * @soc: DP soc handle
  1801. * @vdev_id: id of DP vdev handle
  1802. * @nbuf: skb
  1803. * @tx_exc_metadata: Handle that holds exception path meta data
  1804. *
  1805. * Entry point for Core Tx layer (DP_TX) invoked from
  1806. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1807. *
  1808. * Return: NULL on success,
  1809. * nbuf when it fails to send
  1810. */
  1811. qdf_nbuf_t
  1812. dp_tx_send_exception(struct cdp_soc_t *soc, uint8_t vdev_id, qdf_nbuf_t nbuf,
  1813. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1814. {
  1815. qdf_ether_header_t *eh = NULL;
  1816. struct dp_tx_msdu_info_s msdu_info;
  1817. struct dp_vdev *vdev =
  1818. dp_get_vdev_from_soc_vdev_id_wifi3((struct dp_soc *)soc,
  1819. vdev_id);
  1820. if (qdf_unlikely(!vdev))
  1821. goto fail;
  1822. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1823. if (!tx_exc_metadata)
  1824. goto fail;
  1825. msdu_info.tid = tx_exc_metadata->tid;
  1826. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1827. dp_verbose_debug("skb %pM", nbuf->data);
  1828. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1829. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1830. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1831. "Invalid parameters in exception path");
  1832. goto fail;
  1833. }
  1834. /* Basic sanity checks for unsupported packets */
  1835. /* MESH mode */
  1836. if (qdf_unlikely(vdev->mesh_vdev)) {
  1837. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1838. "Mesh mode is not supported in exception path");
  1839. goto fail;
  1840. }
  1841. /* TSO or SG */
  1842. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1843. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1844. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1845. "TSO and SG are not supported in exception path");
  1846. goto fail;
  1847. }
  1848. /* RAW */
  1849. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1850. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1851. "Raw frame is not supported in exception path");
  1852. goto fail;
  1853. }
  1854. /* Mcast enhancement*/
  1855. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1856. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1857. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1858. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1859. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1860. }
  1861. }
  1862. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  1863. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  1864. qdf_nbuf_len(nbuf));
  1865. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  1866. tx_exc_metadata->ppdu_cookie);
  1867. }
  1868. /*
  1869. * Get HW Queue to use for this frame.
  1870. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1871. * dedicated for data and 1 for command.
  1872. * "queue_id" maps to one hardware ring.
  1873. * With each ring, we also associate a unique Tx descriptor pool
  1874. * to minimize lock contention for these resources.
  1875. */
  1876. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1877. /* Single linear frame */
  1878. /*
  1879. * If nbuf is a simple linear frame, use send_single function to
  1880. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1881. * SRNG. There is no need to setup a MSDU extension descriptor.
  1882. */
  1883. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1884. tx_exc_metadata->peer_id, tx_exc_metadata);
  1885. return nbuf;
  1886. fail:
  1887. dp_verbose_debug("pkt send failed");
  1888. return nbuf;
  1889. }
  1890. /**
  1891. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1892. * @soc: DP soc handle
  1893. * @vdev_id: DP vdev handle
  1894. * @nbuf: skb
  1895. *
  1896. * Entry point for Core Tx layer (DP_TX) invoked from
  1897. * hard_start_xmit in OSIF/HDD
  1898. *
  1899. * Return: NULL on success,
  1900. * nbuf when it fails to send
  1901. */
  1902. #ifdef MESH_MODE_SUPPORT
  1903. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  1904. qdf_nbuf_t nbuf)
  1905. {
  1906. struct meta_hdr_s *mhdr;
  1907. qdf_nbuf_t nbuf_mesh = NULL;
  1908. qdf_nbuf_t nbuf_clone = NULL;
  1909. struct dp_vdev *vdev;
  1910. uint8_t no_enc_frame = 0;
  1911. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1912. if (!nbuf_mesh) {
  1913. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1914. "qdf_nbuf_unshare failed");
  1915. return nbuf;
  1916. }
  1917. vdev = dp_get_vdev_from_soc_vdev_id_wifi3((struct dp_soc *)soc,
  1918. vdev_id);
  1919. if (!vdev) {
  1920. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1921. "vdev is NULL for vdev_id %d", vdev_id);
  1922. return nbuf;
  1923. }
  1924. nbuf = nbuf_mesh;
  1925. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1926. if ((vdev->sec_type != cdp_sec_type_none) &&
  1927. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1928. no_enc_frame = 1;
  1929. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1930. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  1931. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1932. !no_enc_frame) {
  1933. nbuf_clone = qdf_nbuf_clone(nbuf);
  1934. if (!nbuf_clone) {
  1935. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1936. "qdf_nbuf_clone failed");
  1937. return nbuf;
  1938. }
  1939. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1940. }
  1941. if (nbuf_clone) {
  1942. if (!dp_tx_send(soc, vdev_id, nbuf_clone)) {
  1943. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1944. } else {
  1945. qdf_nbuf_free(nbuf_clone);
  1946. }
  1947. }
  1948. if (no_enc_frame)
  1949. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1950. else
  1951. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1952. nbuf = dp_tx_send(soc, vdev_id, nbuf);
  1953. if ((!nbuf) && no_enc_frame) {
  1954. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1955. }
  1956. return nbuf;
  1957. }
  1958. #else
  1959. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  1960. qdf_nbuf_t nbuf)
  1961. {
  1962. return dp_tx_send(soc, vdev_id, nbuf);
  1963. }
  1964. #endif
  1965. /**
  1966. * dp_tx_send() - Transmit a frame on a given VAP
  1967. * @soc: DP soc handle
  1968. * @vdev_id: id of DP vdev handle
  1969. * @nbuf: skb
  1970. *
  1971. * Entry point for Core Tx layer (DP_TX) invoked from
  1972. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1973. * cases
  1974. *
  1975. * Return: NULL on success,
  1976. * nbuf when it fails to send
  1977. */
  1978. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc, uint8_t vdev_id, qdf_nbuf_t nbuf)
  1979. {
  1980. qdf_ether_header_t *eh = NULL;
  1981. struct dp_tx_msdu_info_s msdu_info;
  1982. struct dp_tx_seg_info_s seg_info;
  1983. uint16_t peer_id = HTT_INVALID_PEER;
  1984. qdf_nbuf_t nbuf_mesh = NULL;
  1985. struct dp_vdev *vdev =
  1986. dp_get_vdev_from_soc_vdev_id_wifi3((struct dp_soc *)soc,
  1987. vdev_id);
  1988. if (qdf_unlikely(!vdev))
  1989. return nbuf;
  1990. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1991. qdf_mem_zero(&seg_info, sizeof(seg_info));
  1992. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1993. dp_verbose_debug("skb %pM", nbuf->data);
  1994. /*
  1995. * Set Default Host TID value to invalid TID
  1996. * (TID override disabled)
  1997. */
  1998. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1999. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2000. if (qdf_unlikely(vdev->mesh_vdev)) {
  2001. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2002. &msdu_info);
  2003. if (!nbuf_mesh) {
  2004. dp_verbose_debug("Extracting mesh metadata failed");
  2005. return nbuf;
  2006. }
  2007. nbuf = nbuf_mesh;
  2008. }
  2009. /*
  2010. * Get HW Queue to use for this frame.
  2011. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2012. * dedicated for data and 1 for command.
  2013. * "queue_id" maps to one hardware ring.
  2014. * With each ring, we also associate a unique Tx descriptor pool
  2015. * to minimize lock contention for these resources.
  2016. */
  2017. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2018. /*
  2019. * TCL H/W supports 2 DSCP-TID mapping tables.
  2020. * Table 1 - Default DSCP-TID mapping table
  2021. * Table 2 - 1 DSCP-TID override table
  2022. *
  2023. * If we need a different DSCP-TID mapping for this vap,
  2024. * call tid_classify to extract DSCP/ToS from frame and
  2025. * map to a TID and store in msdu_info. This is later used
  2026. * to fill in TCL Input descriptor (per-packet TID override).
  2027. */
  2028. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2029. /*
  2030. * Classify the frame and call corresponding
  2031. * "prepare" function which extracts the segment (TSO)
  2032. * and fragmentation information (for TSO , SG, ME, or Raw)
  2033. * into MSDU_INFO structure which is later used to fill
  2034. * SW and HW descriptors.
  2035. */
  2036. if (qdf_nbuf_is_tso(nbuf)) {
  2037. dp_verbose_debug("TSO frame %pK", vdev);
  2038. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2039. qdf_nbuf_len(nbuf));
  2040. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2041. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2042. qdf_nbuf_len(nbuf));
  2043. return nbuf;
  2044. }
  2045. goto send_multiple;
  2046. }
  2047. /* SG */
  2048. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2049. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2050. if (!nbuf)
  2051. return NULL;
  2052. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2053. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2054. qdf_nbuf_len(nbuf));
  2055. goto send_multiple;
  2056. }
  2057. #ifdef ATH_SUPPORT_IQUE
  2058. /* Mcast to Ucast Conversion*/
  2059. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  2060. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2061. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2062. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2063. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2064. DP_STATS_INC_PKT(vdev,
  2065. tx_i.mcast_en.mcast_pkt, 1,
  2066. qdf_nbuf_len(nbuf));
  2067. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2068. QDF_STATUS_SUCCESS) {
  2069. return NULL;
  2070. }
  2071. }
  2072. }
  2073. #endif
  2074. /* RAW */
  2075. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2076. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2077. if (!nbuf)
  2078. return NULL;
  2079. dp_verbose_debug("Raw frame %pK", vdev);
  2080. goto send_multiple;
  2081. }
  2082. /* Single linear frame */
  2083. /*
  2084. * If nbuf is a simple linear frame, use send_single function to
  2085. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2086. * SRNG. There is no need to setup a MSDU extension descriptor.
  2087. */
  2088. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2089. return nbuf;
  2090. send_multiple:
  2091. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2092. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2093. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2094. return nbuf;
  2095. }
  2096. /**
  2097. * dp_tx_reinject_handler() - Tx Reinject Handler
  2098. * @tx_desc: software descriptor head pointer
  2099. * @status : Tx completion status from HTT descriptor
  2100. *
  2101. * This function reinjects frames back to Target.
  2102. * Todo - Host queue needs to be added
  2103. *
  2104. * Return: none
  2105. */
  2106. static
  2107. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2108. {
  2109. struct dp_vdev *vdev;
  2110. struct dp_peer *peer = NULL;
  2111. uint32_t peer_id = HTT_INVALID_PEER;
  2112. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2113. qdf_nbuf_t nbuf_copy = NULL;
  2114. struct dp_tx_msdu_info_s msdu_info;
  2115. struct dp_peer *sa_peer = NULL;
  2116. struct dp_ast_entry *ast_entry = NULL;
  2117. struct dp_soc *soc = NULL;
  2118. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2119. #ifdef WDS_VENDOR_EXTENSION
  2120. int is_mcast = 0, is_ucast = 0;
  2121. int num_peers_3addr = 0;
  2122. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2123. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2124. #endif
  2125. vdev = tx_desc->vdev;
  2126. soc = vdev->pdev->soc;
  2127. qdf_assert(vdev);
  2128. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2129. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2130. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2131. "%s Tx reinject path", __func__);
  2132. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2133. qdf_nbuf_len(tx_desc->nbuf));
  2134. qdf_spin_lock_bh(&(soc->ast_lock));
  2135. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2136. (soc,
  2137. (uint8_t *)(eh->ether_shost),
  2138. vdev->pdev->pdev_id);
  2139. if (ast_entry)
  2140. sa_peer = ast_entry->peer;
  2141. qdf_spin_unlock_bh(&(soc->ast_lock));
  2142. #ifdef WDS_VENDOR_EXTENSION
  2143. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2144. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2145. } else {
  2146. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2147. }
  2148. is_ucast = !is_mcast;
  2149. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2150. if (peer->bss_peer)
  2151. continue;
  2152. /* Detect wds peers that use 3-addr framing for mcast.
  2153. * if there are any, the bss_peer is used to send the
  2154. * the mcast frame using 3-addr format. all wds enabled
  2155. * peers that use 4-addr framing for mcast frames will
  2156. * be duplicated and sent as 4-addr frames below.
  2157. */
  2158. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2159. num_peers_3addr = 1;
  2160. break;
  2161. }
  2162. }
  2163. #endif
  2164. if (qdf_unlikely(vdev->mesh_vdev)) {
  2165. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2166. } else {
  2167. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2168. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  2169. #ifdef WDS_VENDOR_EXTENSION
  2170. /*
  2171. * . if 3-addr STA, then send on BSS Peer
  2172. * . if Peer WDS enabled and accept 4-addr mcast,
  2173. * send mcast on that peer only
  2174. * . if Peer WDS enabled and accept 4-addr ucast,
  2175. * send ucast on that peer only
  2176. */
  2177. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2178. (peer->wds_enabled &&
  2179. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2180. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2181. #else
  2182. ((peer->bss_peer &&
  2183. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  2184. peer->nawds_enabled)) {
  2185. #endif
  2186. peer_id = DP_INVALID_PEER;
  2187. if (peer->nawds_enabled) {
  2188. peer_id = peer->peer_ids[0];
  2189. if (sa_peer == peer) {
  2190. QDF_TRACE(
  2191. QDF_MODULE_ID_DP,
  2192. QDF_TRACE_LEVEL_DEBUG,
  2193. " %s: multicast packet",
  2194. __func__);
  2195. DP_STATS_INC(peer,
  2196. tx.nawds_mcast_drop, 1);
  2197. continue;
  2198. }
  2199. }
  2200. nbuf_copy = qdf_nbuf_copy(nbuf);
  2201. if (!nbuf_copy) {
  2202. QDF_TRACE(QDF_MODULE_ID_DP,
  2203. QDF_TRACE_LEVEL_DEBUG,
  2204. FL("nbuf copy failed"));
  2205. break;
  2206. }
  2207. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2208. nbuf_copy,
  2209. &msdu_info,
  2210. peer_id,
  2211. NULL);
  2212. if (nbuf_copy) {
  2213. QDF_TRACE(QDF_MODULE_ID_DP,
  2214. QDF_TRACE_LEVEL_DEBUG,
  2215. FL("pkt send failed"));
  2216. qdf_nbuf_free(nbuf_copy);
  2217. } else {
  2218. if (peer_id != DP_INVALID_PEER)
  2219. DP_STATS_INC_PKT(peer,
  2220. tx.nawds_mcast,
  2221. 1, qdf_nbuf_len(nbuf));
  2222. }
  2223. }
  2224. }
  2225. }
  2226. if (vdev->nawds_enabled) {
  2227. peer_id = DP_INVALID_PEER;
  2228. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2229. 1, qdf_nbuf_len(nbuf));
  2230. nbuf = dp_tx_send_msdu_single(vdev,
  2231. nbuf,
  2232. &msdu_info,
  2233. peer_id, NULL);
  2234. if (nbuf) {
  2235. QDF_TRACE(QDF_MODULE_ID_DP,
  2236. QDF_TRACE_LEVEL_DEBUG,
  2237. FL("pkt send failed"));
  2238. qdf_nbuf_free(nbuf);
  2239. }
  2240. } else
  2241. qdf_nbuf_free(nbuf);
  2242. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2243. }
  2244. /**
  2245. * dp_tx_inspect_handler() - Tx Inspect Handler
  2246. * @tx_desc: software descriptor head pointer
  2247. * @status : Tx completion status from HTT descriptor
  2248. *
  2249. * Handles Tx frames sent back to Host for inspection
  2250. * (ProxyARP)
  2251. *
  2252. * Return: none
  2253. */
  2254. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2255. {
  2256. struct dp_soc *soc;
  2257. struct dp_pdev *pdev = tx_desc->pdev;
  2258. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2259. "%s Tx inspect path",
  2260. __func__);
  2261. qdf_assert(pdev);
  2262. soc = pdev->soc;
  2263. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2264. qdf_nbuf_len(tx_desc->nbuf));
  2265. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2266. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2267. }
  2268. #ifdef FEATURE_PERPKT_INFO
  2269. /**
  2270. * dp_get_completion_indication_for_stack() - send completion to stack
  2271. * @soc : dp_soc handle
  2272. * @pdev: dp_pdev handle
  2273. * @peer: dp peer handle
  2274. * @ts: transmit completion status structure
  2275. * @netbuf: Buffer pointer for free
  2276. *
  2277. * This function is used for indication whether buffer needs to be
  2278. * sent to stack for freeing or not
  2279. */
  2280. QDF_STATUS
  2281. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2282. struct dp_pdev *pdev,
  2283. struct dp_peer *peer,
  2284. struct hal_tx_completion_status *ts,
  2285. qdf_nbuf_t netbuf,
  2286. uint64_t time_latency)
  2287. {
  2288. struct tx_capture_hdr *ppdu_hdr;
  2289. uint16_t peer_id = ts->peer_id;
  2290. uint32_t ppdu_id = ts->ppdu_id;
  2291. uint8_t first_msdu = ts->first_msdu;
  2292. uint8_t last_msdu = ts->last_msdu;
  2293. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2294. !pdev->latency_capture_enable))
  2295. return QDF_STATUS_E_NOSUPPORT;
  2296. if (!peer) {
  2297. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2298. FL("Peer Invalid"));
  2299. return QDF_STATUS_E_INVAL;
  2300. }
  2301. if (pdev->mcopy_mode) {
  2302. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2303. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2304. return QDF_STATUS_E_INVAL;
  2305. }
  2306. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2307. pdev->m_copy_id.tx_peer_id = peer_id;
  2308. }
  2309. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2310. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2311. FL("No headroom"));
  2312. return QDF_STATUS_E_NOMEM;
  2313. }
  2314. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2315. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2316. QDF_MAC_ADDR_SIZE);
  2317. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2318. QDF_MAC_ADDR_SIZE);
  2319. ppdu_hdr->ppdu_id = ppdu_id;
  2320. ppdu_hdr->peer_id = peer_id;
  2321. ppdu_hdr->first_msdu = first_msdu;
  2322. ppdu_hdr->last_msdu = last_msdu;
  2323. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2324. ppdu_hdr->tsf = ts->tsf;
  2325. ppdu_hdr->time_latency = time_latency;
  2326. }
  2327. return QDF_STATUS_SUCCESS;
  2328. }
  2329. /**
  2330. * dp_send_completion_to_stack() - send completion to stack
  2331. * @soc : dp_soc handle
  2332. * @pdev: dp_pdev handle
  2333. * @peer_id: peer_id of the peer for which completion came
  2334. * @ppdu_id: ppdu_id
  2335. * @netbuf: Buffer pointer for free
  2336. *
  2337. * This function is used to send completion to stack
  2338. * to free buffer
  2339. */
  2340. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2341. uint16_t peer_id, uint32_t ppdu_id,
  2342. qdf_nbuf_t netbuf)
  2343. {
  2344. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2345. netbuf, peer_id,
  2346. WDI_NO_VAL, pdev->pdev_id);
  2347. }
  2348. #else
  2349. static QDF_STATUS
  2350. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2351. struct dp_pdev *pdev,
  2352. struct dp_peer *peer,
  2353. struct hal_tx_completion_status *ts,
  2354. qdf_nbuf_t netbuf,
  2355. uint64_t time_latency)
  2356. {
  2357. return QDF_STATUS_E_NOSUPPORT;
  2358. }
  2359. static void
  2360. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2361. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2362. {
  2363. }
  2364. #endif
  2365. /**
  2366. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2367. * @soc: Soc handle
  2368. * @desc: software Tx descriptor to be processed
  2369. *
  2370. * Return: none
  2371. */
  2372. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2373. struct dp_tx_desc_s *desc)
  2374. {
  2375. struct dp_vdev *vdev = desc->vdev;
  2376. qdf_nbuf_t nbuf = desc->nbuf;
  2377. /* nbuf already freed in vdev detach path */
  2378. if (!nbuf)
  2379. return;
  2380. /* If it is TDLS mgmt, don't unmap or free the frame */
  2381. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2382. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2383. /* 0 : MSDU buffer, 1 : MLE */
  2384. if (desc->msdu_ext_desc) {
  2385. /* TSO free */
  2386. if (hal_tx_ext_desc_get_tso_enable(
  2387. desc->msdu_ext_desc->vaddr)) {
  2388. /* unmap eash TSO seg before free the nbuf */
  2389. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2390. desc->tso_num_desc);
  2391. qdf_nbuf_free(nbuf);
  2392. return;
  2393. }
  2394. }
  2395. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2396. if (qdf_unlikely(!vdev)) {
  2397. qdf_nbuf_free(nbuf);
  2398. return;
  2399. }
  2400. if (qdf_likely(!vdev->mesh_vdev))
  2401. qdf_nbuf_free(nbuf);
  2402. else {
  2403. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2404. qdf_nbuf_free(nbuf);
  2405. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2406. } else
  2407. vdev->osif_tx_free_ext((nbuf));
  2408. }
  2409. }
  2410. #ifdef MESH_MODE_SUPPORT
  2411. /**
  2412. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2413. * in mesh meta header
  2414. * @tx_desc: software descriptor head pointer
  2415. * @ts: pointer to tx completion stats
  2416. * Return: none
  2417. */
  2418. static
  2419. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2420. struct hal_tx_completion_status *ts)
  2421. {
  2422. struct meta_hdr_s *mhdr;
  2423. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2424. if (!tx_desc->msdu_ext_desc) {
  2425. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2426. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2427. "netbuf %pK offset %d",
  2428. netbuf, tx_desc->pkt_offset);
  2429. return;
  2430. }
  2431. }
  2432. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2433. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2434. "netbuf %pK offset %lu", netbuf,
  2435. sizeof(struct meta_hdr_s));
  2436. return;
  2437. }
  2438. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2439. mhdr->rssi = ts->ack_frame_rssi;
  2440. mhdr->band = tx_desc->pdev->operating_channel.band;
  2441. mhdr->channel = tx_desc->pdev->operating_channel.num;
  2442. }
  2443. #else
  2444. static
  2445. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2446. struct hal_tx_completion_status *ts)
  2447. {
  2448. }
  2449. #endif
  2450. /**
  2451. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2452. * to pass in correct fields
  2453. *
  2454. * @vdev: pdev handle
  2455. * @tx_desc: tx descriptor
  2456. * @tid: tid value
  2457. * @ring_id: TCL or WBM ring number for transmit path
  2458. * Return: none
  2459. */
  2460. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2461. struct dp_tx_desc_s *tx_desc,
  2462. uint8_t tid, uint8_t ring_id)
  2463. {
  2464. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2465. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2466. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2467. return;
  2468. current_timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  2469. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2470. timestamp_hw_enqueue = tx_desc->timestamp;
  2471. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2472. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2473. timestamp_hw_enqueue);
  2474. interframe_delay = (uint32_t)(timestamp_ingress -
  2475. vdev->prev_tx_enq_tstamp);
  2476. /*
  2477. * Delay in software enqueue
  2478. */
  2479. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2480. CDP_DELAY_STATS_SW_ENQ, ring_id);
  2481. /*
  2482. * Delay between packet enqueued to HW and Tx completion
  2483. */
  2484. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2485. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  2486. /*
  2487. * Update interframe delay stats calculated at hardstart receive point.
  2488. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2489. * interframe delay will not be calculate correctly for 1st frame.
  2490. * On the other side, this will help in avoiding extra per packet check
  2491. * of !vdev->prev_tx_enq_tstamp.
  2492. */
  2493. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2494. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  2495. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2496. }
  2497. /**
  2498. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2499. * per wbm ring
  2500. *
  2501. * @tx_desc: software descriptor head pointer
  2502. * @ts: Tx completion status
  2503. * @peer: peer handle
  2504. * @ring_id: ring number
  2505. *
  2506. * Return: None
  2507. */
  2508. static inline void
  2509. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2510. struct hal_tx_completion_status *ts,
  2511. struct dp_peer *peer, uint8_t ring_id)
  2512. {
  2513. struct dp_pdev *pdev = peer->vdev->pdev;
  2514. struct dp_soc *soc = NULL;
  2515. uint8_t mcs, pkt_type;
  2516. uint8_t tid = ts->tid;
  2517. uint32_t length;
  2518. struct cdp_tid_tx_stats *tid_stats;
  2519. if (!pdev)
  2520. return;
  2521. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2522. tid = CDP_MAX_DATA_TIDS - 1;
  2523. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2524. soc = pdev->soc;
  2525. mcs = ts->mcs;
  2526. pkt_type = ts->pkt_type;
  2527. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2528. dp_err("Release source is not from TQM");
  2529. return;
  2530. }
  2531. length = qdf_nbuf_len(tx_desc->nbuf);
  2532. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2533. if (qdf_unlikely(pdev->delay_stats_flag))
  2534. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  2535. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2536. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2537. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2538. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2539. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2540. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2541. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2542. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2543. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2544. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2545. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2546. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2547. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2548. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2549. /*
  2550. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  2551. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  2552. * are no completions for failed cases. Hence updating tx_failed from
  2553. * data path. Please note that if tx_failed is fixed to be from ppdu,
  2554. * then this has to be removed
  2555. */
  2556. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  2557. peer->stats.tx.dropped.fw_rem_notx +
  2558. peer->stats.tx.dropped.fw_rem_tx +
  2559. peer->stats.tx.dropped.age_out +
  2560. peer->stats.tx.dropped.fw_reason1 +
  2561. peer->stats.tx.dropped.fw_reason2 +
  2562. peer->stats.tx.dropped.fw_reason3;
  2563. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  2564. tid_stats->tqm_status_cnt[ts->status]++;
  2565. }
  2566. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2567. return;
  2568. }
  2569. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2570. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2571. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2572. /*
  2573. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2574. * Return from here if HTT PPDU events are enabled.
  2575. */
  2576. if (!(soc->process_tx_status))
  2577. return;
  2578. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2579. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2580. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2581. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2582. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2583. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2584. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2585. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2586. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2587. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2588. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2589. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2590. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2591. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2592. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2593. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2594. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2595. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2596. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2597. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2598. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2599. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2600. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2601. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2602. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2603. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2604. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2605. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2606. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2607. &peer->stats, ts->peer_id,
  2608. UPDATE_PEER_STATS, pdev->pdev_id);
  2609. #endif
  2610. }
  2611. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2612. /**
  2613. * dp_tx_flow_pool_lock() - take flow pool lock
  2614. * @soc: core txrx main context
  2615. * @tx_desc: tx desc
  2616. *
  2617. * Return: None
  2618. */
  2619. static inline
  2620. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2621. struct dp_tx_desc_s *tx_desc)
  2622. {
  2623. struct dp_tx_desc_pool_s *pool;
  2624. uint8_t desc_pool_id;
  2625. desc_pool_id = tx_desc->pool_id;
  2626. pool = &soc->tx_desc[desc_pool_id];
  2627. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2628. }
  2629. /**
  2630. * dp_tx_flow_pool_unlock() - release flow pool lock
  2631. * @soc: core txrx main context
  2632. * @tx_desc: tx desc
  2633. *
  2634. * Return: None
  2635. */
  2636. static inline
  2637. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2638. struct dp_tx_desc_s *tx_desc)
  2639. {
  2640. struct dp_tx_desc_pool_s *pool;
  2641. uint8_t desc_pool_id;
  2642. desc_pool_id = tx_desc->pool_id;
  2643. pool = &soc->tx_desc[desc_pool_id];
  2644. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2645. }
  2646. #else
  2647. static inline
  2648. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2649. {
  2650. }
  2651. static inline
  2652. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2653. {
  2654. }
  2655. #endif
  2656. /**
  2657. * dp_tx_notify_completion() - Notify tx completion for this desc
  2658. * @soc: core txrx main context
  2659. * @tx_desc: tx desc
  2660. * @netbuf: buffer
  2661. *
  2662. * Return: none
  2663. */
  2664. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2665. struct dp_tx_desc_s *tx_desc,
  2666. qdf_nbuf_t netbuf)
  2667. {
  2668. void *osif_dev;
  2669. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2670. qdf_assert(tx_desc);
  2671. dp_tx_flow_pool_lock(soc, tx_desc);
  2672. if (!tx_desc->vdev ||
  2673. !tx_desc->vdev->osif_vdev) {
  2674. dp_tx_flow_pool_unlock(soc, tx_desc);
  2675. return;
  2676. }
  2677. osif_dev = tx_desc->vdev->osif_vdev;
  2678. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2679. dp_tx_flow_pool_unlock(soc, tx_desc);
  2680. if (tx_compl_cbk)
  2681. tx_compl_cbk(netbuf, osif_dev);
  2682. }
  2683. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2684. * @pdev: pdev handle
  2685. * @tid: tid value
  2686. * @txdesc_ts: timestamp from txdesc
  2687. * @ppdu_id: ppdu id
  2688. *
  2689. * Return: none
  2690. */
  2691. #ifdef FEATURE_PERPKT_INFO
  2692. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2693. struct dp_peer *peer,
  2694. uint8_t tid,
  2695. uint64_t txdesc_ts,
  2696. uint32_t ppdu_id)
  2697. {
  2698. uint64_t delta_ms;
  2699. struct cdp_tx_sojourn_stats *sojourn_stats;
  2700. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  2701. return;
  2702. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  2703. tid >= CDP_DATA_TID_MAX))
  2704. return;
  2705. if (qdf_unlikely(!pdev->sojourn_buf))
  2706. return;
  2707. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2708. qdf_nbuf_data(pdev->sojourn_buf);
  2709. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  2710. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2711. txdesc_ts;
  2712. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  2713. delta_ms);
  2714. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  2715. sojourn_stats->num_msdus[tid] = 1;
  2716. sojourn_stats->avg_sojourn_msdu[tid].internal =
  2717. peer->avg_sojourn_msdu[tid].internal;
  2718. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2719. pdev->sojourn_buf, HTT_INVALID_PEER,
  2720. WDI_NO_VAL, pdev->pdev_id);
  2721. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  2722. sojourn_stats->num_msdus[tid] = 0;
  2723. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  2724. }
  2725. #else
  2726. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2727. struct dp_peer *peer,
  2728. uint8_t tid,
  2729. uint64_t txdesc_ts,
  2730. uint32_t ppdu_id)
  2731. {
  2732. }
  2733. #endif
  2734. /**
  2735. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2736. * @soc: DP Soc handle
  2737. * @tx_desc: software Tx descriptor
  2738. * @ts : Tx completion status from HAL/HTT descriptor
  2739. *
  2740. * Return: none
  2741. */
  2742. static inline void
  2743. dp_tx_comp_process_desc(struct dp_soc *soc,
  2744. struct dp_tx_desc_s *desc,
  2745. struct hal_tx_completion_status *ts,
  2746. struct dp_peer *peer)
  2747. {
  2748. uint64_t time_latency = 0;
  2749. /*
  2750. * m_copy/tx_capture modes are not supported for
  2751. * scatter gather packets
  2752. */
  2753. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  2754. time_latency = (qdf_ktime_to_ms(qdf_ktime_get()) -
  2755. desc->timestamp);
  2756. }
  2757. if (!(desc->msdu_ext_desc)) {
  2758. if (QDF_STATUS_SUCCESS ==
  2759. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  2760. return;
  2761. }
  2762. if (QDF_STATUS_SUCCESS ==
  2763. dp_get_completion_indication_for_stack(soc,
  2764. desc->pdev,
  2765. peer, ts,
  2766. desc->nbuf,
  2767. time_latency)) {
  2768. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2769. QDF_DMA_TO_DEVICE);
  2770. dp_send_completion_to_stack(soc,
  2771. desc->pdev,
  2772. ts->peer_id,
  2773. ts->ppdu_id,
  2774. desc->nbuf);
  2775. return;
  2776. }
  2777. }
  2778. dp_tx_comp_free_buf(soc, desc);
  2779. }
  2780. /**
  2781. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2782. * @tx_desc: software descriptor head pointer
  2783. * @ts: Tx completion status
  2784. * @peer: peer handle
  2785. * @ring_id: ring number
  2786. *
  2787. * Return: none
  2788. */
  2789. static inline
  2790. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2791. struct hal_tx_completion_status *ts,
  2792. struct dp_peer *peer, uint8_t ring_id)
  2793. {
  2794. uint32_t length;
  2795. qdf_ether_header_t *eh;
  2796. struct dp_soc *soc = NULL;
  2797. struct dp_vdev *vdev = tx_desc->vdev;
  2798. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2799. if (!vdev || !nbuf) {
  2800. dp_info_rl("invalid tx descriptor. vdev or nbuf NULL");
  2801. goto out;
  2802. }
  2803. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2804. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2805. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2806. QDF_TRACE_DEFAULT_PDEV_ID,
  2807. qdf_nbuf_data_addr(nbuf),
  2808. sizeof(qdf_nbuf_data(nbuf)),
  2809. tx_desc->id,
  2810. ts->status));
  2811. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2812. "-------------------- \n"
  2813. "Tx Completion Stats: \n"
  2814. "-------------------- \n"
  2815. "ack_frame_rssi = %d \n"
  2816. "first_msdu = %d \n"
  2817. "last_msdu = %d \n"
  2818. "msdu_part_of_amsdu = %d \n"
  2819. "rate_stats valid = %d \n"
  2820. "bw = %d \n"
  2821. "pkt_type = %d \n"
  2822. "stbc = %d \n"
  2823. "ldpc = %d \n"
  2824. "sgi = %d \n"
  2825. "mcs = %d \n"
  2826. "ofdma = %d \n"
  2827. "tones_in_ru = %d \n"
  2828. "tsf = %d \n"
  2829. "ppdu_id = %d \n"
  2830. "transmit_cnt = %d \n"
  2831. "tid = %d \n"
  2832. "peer_id = %d\n",
  2833. ts->ack_frame_rssi, ts->first_msdu,
  2834. ts->last_msdu, ts->msdu_part_of_amsdu,
  2835. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2836. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2837. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2838. ts->transmit_cnt, ts->tid, ts->peer_id);
  2839. soc = vdev->pdev->soc;
  2840. /* Update SoC level stats */
  2841. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2842. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2843. /* Update per-packet stats for mesh mode */
  2844. if (qdf_unlikely(vdev->mesh_vdev) &&
  2845. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2846. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2847. length = qdf_nbuf_len(nbuf);
  2848. /* Update peer level stats */
  2849. if (!peer) {
  2850. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2851. "peer is null or deletion in progress");
  2852. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2853. goto out;
  2854. }
  2855. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  2856. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2857. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2858. if ((peer->vdev->tx_encap_type ==
  2859. htt_cmn_pkt_type_ethernet) &&
  2860. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  2861. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2862. }
  2863. }
  2864. } else {
  2865. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2866. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2867. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2868. }
  2869. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  2870. #ifdef QCA_SUPPORT_RDK_STATS
  2871. if (soc->wlanstats_enabled)
  2872. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  2873. tx_desc->timestamp,
  2874. ts->ppdu_id);
  2875. #endif
  2876. out:
  2877. return;
  2878. }
  2879. /**
  2880. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2881. * @soc: core txrx main context
  2882. * @comp_head: software descriptor head pointer
  2883. * @ring_id: ring number
  2884. *
  2885. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2886. * and release the software descriptors after processing is complete
  2887. *
  2888. * Return: none
  2889. */
  2890. static void
  2891. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2892. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  2893. {
  2894. struct dp_tx_desc_s *desc;
  2895. struct dp_tx_desc_s *next;
  2896. struct hal_tx_completion_status ts = {0};
  2897. struct dp_peer *peer;
  2898. qdf_nbuf_t netbuf;
  2899. desc = comp_head;
  2900. while (desc) {
  2901. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2902. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2903. dp_tx_comp_process_tx_status(desc, &ts, peer, ring_id);
  2904. netbuf = desc->nbuf;
  2905. /* check tx complete notification */
  2906. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  2907. dp_tx_notify_completion(soc, desc, netbuf);
  2908. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2909. if (peer)
  2910. dp_peer_unref_del_find_by_id(peer);
  2911. next = desc->next;
  2912. dp_tx_desc_release(desc, desc->pool_id);
  2913. desc = next;
  2914. }
  2915. }
  2916. /**
  2917. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2918. * @tx_desc: software descriptor head pointer
  2919. * @status : Tx completion status from HTT descriptor
  2920. * @ring_id: ring number
  2921. *
  2922. * This function will process HTT Tx indication messages from Target
  2923. *
  2924. * Return: none
  2925. */
  2926. static
  2927. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  2928. uint8_t ring_id)
  2929. {
  2930. uint8_t tx_status;
  2931. struct dp_pdev *pdev;
  2932. struct dp_vdev *vdev;
  2933. struct dp_soc *soc;
  2934. struct hal_tx_completion_status ts = {0};
  2935. uint32_t *htt_desc = (uint32_t *)status;
  2936. struct dp_peer *peer;
  2937. struct cdp_tid_tx_stats *tid_stats = NULL;
  2938. struct htt_soc *htt_handle;
  2939. qdf_assert(tx_desc->pdev);
  2940. pdev = tx_desc->pdev;
  2941. vdev = tx_desc->vdev;
  2942. soc = pdev->soc;
  2943. if (!vdev)
  2944. return;
  2945. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2946. htt_handle = (struct htt_soc *)soc->htt_handle;
  2947. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  2948. switch (tx_status) {
  2949. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2950. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2951. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2952. {
  2953. uint8_t tid;
  2954. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2955. ts.peer_id =
  2956. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2957. htt_desc[2]);
  2958. ts.tid =
  2959. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2960. htt_desc[2]);
  2961. } else {
  2962. ts.peer_id = HTT_INVALID_PEER;
  2963. ts.tid = HTT_INVALID_TID;
  2964. }
  2965. ts.ppdu_id =
  2966. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2967. htt_desc[1]);
  2968. ts.ack_frame_rssi =
  2969. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2970. htt_desc[1]);
  2971. ts.first_msdu = 1;
  2972. ts.last_msdu = 1;
  2973. tid = ts.tid;
  2974. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2975. tid = CDP_MAX_DATA_TIDS - 1;
  2976. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2977. if (qdf_unlikely(pdev->delay_stats_flag))
  2978. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  2979. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  2980. tid_stats->htt_status_cnt[tx_status]++;
  2981. }
  2982. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2983. if (qdf_likely(peer))
  2984. dp_peer_unref_del_find_by_id(peer);
  2985. dp_tx_comp_process_tx_status(tx_desc, &ts, peer, ring_id);
  2986. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2987. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2988. break;
  2989. }
  2990. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2991. {
  2992. dp_tx_reinject_handler(tx_desc, status);
  2993. break;
  2994. }
  2995. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2996. {
  2997. dp_tx_inspect_handler(tx_desc, status);
  2998. break;
  2999. }
  3000. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  3001. {
  3002. dp_tx_mec_handler(vdev, status);
  3003. break;
  3004. }
  3005. default:
  3006. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3007. "%s Invalid HTT tx_status %d\n",
  3008. __func__, tx_status);
  3009. break;
  3010. }
  3011. }
  3012. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3013. static inline
  3014. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3015. {
  3016. bool limit_hit = false;
  3017. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3018. limit_hit =
  3019. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  3020. if (limit_hit)
  3021. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3022. return limit_hit;
  3023. }
  3024. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3025. {
  3026. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3027. }
  3028. #else
  3029. static inline
  3030. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3031. {
  3032. return false;
  3033. }
  3034. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3035. {
  3036. return false;
  3037. }
  3038. #endif
  3039. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3040. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3041. uint32_t quota)
  3042. {
  3043. void *tx_comp_hal_desc;
  3044. uint8_t buffer_src;
  3045. uint8_t pool_id;
  3046. uint32_t tx_desc_id;
  3047. struct dp_tx_desc_s *tx_desc = NULL;
  3048. struct dp_tx_desc_s *head_desc = NULL;
  3049. struct dp_tx_desc_s *tail_desc = NULL;
  3050. uint32_t num_processed = 0;
  3051. uint32_t count = 0;
  3052. bool force_break = false;
  3053. DP_HIST_INIT();
  3054. more_data:
  3055. /* Re-initialize local variables to be re-used */
  3056. head_desc = NULL;
  3057. tail_desc = NULL;
  3058. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  3059. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  3060. return 0;
  3061. }
  3062. /* Find head descriptor from completion ring */
  3063. while (qdf_likely(tx_comp_hal_desc =
  3064. hal_srng_dst_get_next(soc->hal_soc, hal_ring_hdl))) {
  3065. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  3066. /* If this buffer was not released by TQM or FW, then it is not
  3067. * Tx completion indication, assert */
  3068. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  3069. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3070. uint8_t wbm_internal_error;
  3071. dp_err_rl(
  3072. "Tx comp release_src != TQM | FW but from %d",
  3073. buffer_src);
  3074. hal_dump_comp_desc(tx_comp_hal_desc);
  3075. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  3076. /* When WBM sees NULL buffer_addr_info in any of
  3077. * ingress rings it sends an error indication,
  3078. * with wbm_internal_error=1, to a specific ring.
  3079. * The WBM2SW ring used to indicate these errors is
  3080. * fixed in HW, and that ring is being used as Tx
  3081. * completion ring. These errors are not related to
  3082. * Tx completions, and should just be ignored
  3083. */
  3084. wbm_internal_error = hal_get_wbm_internal_error(
  3085. soc->hal_soc,
  3086. tx_comp_hal_desc);
  3087. if (wbm_internal_error) {
  3088. dp_err_rl("Tx comp wbm_internal_error!!");
  3089. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  3090. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  3091. buffer_src)
  3092. dp_handle_wbm_internal_error(
  3093. soc,
  3094. tx_comp_hal_desc,
  3095. hal_tx_comp_get_buffer_type(
  3096. tx_comp_hal_desc));
  3097. } else {
  3098. dp_err_rl("Tx comp wbm_internal_error false");
  3099. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  3100. }
  3101. continue;
  3102. }
  3103. /* Get descriptor id */
  3104. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  3105. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3106. DP_TX_DESC_ID_POOL_OS;
  3107. /* Find Tx descriptor */
  3108. tx_desc = dp_tx_desc_find(soc, pool_id,
  3109. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3110. DP_TX_DESC_ID_PAGE_OS,
  3111. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3112. DP_TX_DESC_ID_OFFSET_OS);
  3113. /*
  3114. * If the descriptor is already freed in vdev_detach,
  3115. * continue to next descriptor
  3116. */
  3117. if (!tx_desc->vdev && !tx_desc->flags) {
  3118. QDF_TRACE(QDF_MODULE_ID_DP,
  3119. QDF_TRACE_LEVEL_INFO,
  3120. "Descriptor freed in vdev_detach %d",
  3121. tx_desc_id);
  3122. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3123. count++;
  3124. continue;
  3125. }
  3126. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3127. QDF_TRACE(QDF_MODULE_ID_DP,
  3128. QDF_TRACE_LEVEL_INFO,
  3129. "pdev in down state %d",
  3130. tx_desc_id);
  3131. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3132. count++;
  3133. dp_tx_comp_free_buf(soc, tx_desc);
  3134. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3135. continue;
  3136. }
  3137. /*
  3138. * If the release source is FW, process the HTT status
  3139. */
  3140. if (qdf_unlikely(buffer_src ==
  3141. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3142. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  3143. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  3144. htt_tx_status);
  3145. dp_tx_process_htt_completion(tx_desc,
  3146. htt_tx_status, ring_id);
  3147. } else {
  3148. /* Pool id is not matching. Error */
  3149. if (tx_desc->pool_id != pool_id) {
  3150. QDF_TRACE(QDF_MODULE_ID_DP,
  3151. QDF_TRACE_LEVEL_FATAL,
  3152. "Tx Comp pool id %d not matched %d",
  3153. pool_id, tx_desc->pool_id);
  3154. qdf_assert_always(0);
  3155. }
  3156. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  3157. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  3158. QDF_TRACE(QDF_MODULE_ID_DP,
  3159. QDF_TRACE_LEVEL_FATAL,
  3160. "Txdesc invalid, flgs = %x,id = %d",
  3161. tx_desc->flags, tx_desc_id);
  3162. qdf_assert_always(0);
  3163. }
  3164. /* First ring descriptor on the cycle */
  3165. if (!head_desc) {
  3166. head_desc = tx_desc;
  3167. tail_desc = tx_desc;
  3168. }
  3169. tail_desc->next = tx_desc;
  3170. tx_desc->next = NULL;
  3171. tail_desc = tx_desc;
  3172. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  3173. /* Collect hw completion contents */
  3174. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  3175. &tx_desc->comp, 1);
  3176. }
  3177. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3178. /*
  3179. * Processed packet count is more than given quota
  3180. * stop to processing
  3181. */
  3182. if (num_processed >= quota) {
  3183. force_break = true;
  3184. break;
  3185. }
  3186. count++;
  3187. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  3188. break;
  3189. }
  3190. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  3191. /* Process the reaped descriptors */
  3192. if (head_desc)
  3193. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  3194. if (dp_tx_comp_enable_eol_data_check(soc)) {
  3195. if (!force_break &&
  3196. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  3197. hal_ring_hdl)) {
  3198. DP_STATS_INC(soc, tx.hp_oos2, 1);
  3199. if (!hif_exec_should_yield(soc->hif_handle,
  3200. int_ctx->dp_intr_id))
  3201. goto more_data;
  3202. }
  3203. }
  3204. DP_TX_HIST_STATS_PER_PDEV();
  3205. return num_processed;
  3206. }
  3207. #ifdef FEATURE_WLAN_TDLS
  3208. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3209. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3210. {
  3211. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3212. struct dp_vdev *vdev = dp_get_vdev_from_soc_vdev_id_wifi3(soc, vdev_id);
  3213. if (!vdev) {
  3214. dp_err("vdev handle for id %d is NULL", vdev_id);
  3215. return NULL;
  3216. }
  3217. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3218. vdev->is_tdls_frame = true;
  3219. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  3220. }
  3221. #endif
  3222. /**
  3223. * dp_tx_vdev_attach() - attach vdev to dp tx
  3224. * @vdev: virtual device instance
  3225. *
  3226. * Return: QDF_STATUS_SUCCESS: success
  3227. * QDF_STATUS_E_RESOURCES: Error return
  3228. */
  3229. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3230. {
  3231. int pdev_id;
  3232. /*
  3233. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3234. */
  3235. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3236. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3237. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3238. vdev->vdev_id);
  3239. pdev_id =
  3240. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  3241. vdev->pdev->pdev_id);
  3242. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  3243. /*
  3244. * Set HTT Extension Valid bit to 0 by default
  3245. */
  3246. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3247. dp_tx_vdev_update_search_flags(vdev);
  3248. return QDF_STATUS_SUCCESS;
  3249. }
  3250. #ifndef FEATURE_WDS
  3251. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3252. {
  3253. return false;
  3254. }
  3255. #endif
  3256. /**
  3257. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3258. * @vdev: virtual device instance
  3259. *
  3260. * Return: void
  3261. *
  3262. */
  3263. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3264. {
  3265. struct dp_soc *soc = vdev->pdev->soc;
  3266. /*
  3267. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3268. * for TDLS link
  3269. *
  3270. * Enable AddrY (SA based search) only for non-WDS STA and
  3271. * ProxySTA VAP (in HKv1) modes.
  3272. *
  3273. * In all other VAP modes, only DA based search should be
  3274. * enabled
  3275. */
  3276. if (vdev->opmode == wlan_op_mode_sta &&
  3277. vdev->tdls_link_connected)
  3278. vdev->hal_desc_addr_search_flags =
  3279. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3280. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3281. !dp_tx_da_search_override(vdev))
  3282. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3283. else
  3284. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3285. /* Set search type only when peer map v2 messaging is enabled
  3286. * as we will have the search index (AST hash) only when v2 is
  3287. * enabled
  3288. */
  3289. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3290. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3291. else
  3292. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3293. }
  3294. static inline bool
  3295. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3296. struct dp_vdev *vdev,
  3297. struct dp_tx_desc_s *tx_desc)
  3298. {
  3299. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3300. return false;
  3301. /*
  3302. * if vdev is given, then only check whether desc
  3303. * vdev match. if vdev is NULL, then check whether
  3304. * desc pdev match.
  3305. */
  3306. return vdev ? (tx_desc->vdev == vdev) : (tx_desc->pdev == pdev);
  3307. }
  3308. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3309. /**
  3310. * dp_tx_desc_flush() - release resources associated
  3311. * to TX Desc
  3312. *
  3313. * @dp_pdev: Handle to DP pdev structure
  3314. * @vdev: virtual device instance
  3315. * NULL: no specific Vdev is required and check all allcated TX desc
  3316. * on this pdev.
  3317. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3318. *
  3319. * @force_free:
  3320. * true: flush the TX desc.
  3321. * false: only reset the Vdev in each allocated TX desc
  3322. * that associated to current Vdev.
  3323. *
  3324. * This function will go through the TX desc pool to flush
  3325. * the outstanding TX data or reset Vdev to NULL in associated TX
  3326. * Desc.
  3327. */
  3328. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3329. struct dp_vdev *vdev,
  3330. bool force_free)
  3331. {
  3332. uint8_t i;
  3333. uint32_t j;
  3334. uint32_t num_desc, page_id, offset;
  3335. uint16_t num_desc_per_page;
  3336. struct dp_soc *soc = pdev->soc;
  3337. struct dp_tx_desc_s *tx_desc = NULL;
  3338. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3339. if (!vdev && !force_free) {
  3340. dp_err("Reset TX desc vdev, Vdev param is required!");
  3341. return;
  3342. }
  3343. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3344. tx_desc_pool = &soc->tx_desc[i];
  3345. if (!(tx_desc_pool->pool_size) ||
  3346. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3347. !(tx_desc_pool->desc_pages.cacheable_pages))
  3348. continue;
  3349. /*
  3350. * Add flow pool lock protection in case pool is freed
  3351. * due to all tx_desc is recycled when handle TX completion.
  3352. * this is not necessary when do force flush as:
  3353. * a. double lock will happen if dp_tx_desc_release is
  3354. * also trying to acquire it.
  3355. * b. dp interrupt has been disabled before do force TX desc
  3356. * flush in dp_pdev_deinit().
  3357. */
  3358. if (!force_free)
  3359. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  3360. num_desc = tx_desc_pool->pool_size;
  3361. num_desc_per_page =
  3362. tx_desc_pool->desc_pages.num_element_per_page;
  3363. for (j = 0; j < num_desc; j++) {
  3364. page_id = j / num_desc_per_page;
  3365. offset = j % num_desc_per_page;
  3366. if (qdf_unlikely(!(tx_desc_pool->
  3367. desc_pages.cacheable_pages)))
  3368. break;
  3369. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3370. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3371. /*
  3372. * Free TX desc if force free is
  3373. * required, otherwise only reset vdev
  3374. * in this TX desc.
  3375. */
  3376. if (force_free) {
  3377. dp_tx_comp_free_buf(soc, tx_desc);
  3378. dp_tx_desc_release(tx_desc, i);
  3379. } else {
  3380. tx_desc->vdev = NULL;
  3381. }
  3382. }
  3383. }
  3384. if (!force_free)
  3385. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  3386. }
  3387. }
  3388. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3389. /**
  3390. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3391. *
  3392. * @soc: Handle to DP soc structure
  3393. * @tx_desc: pointer of one TX desc
  3394. * @desc_pool_id: TX Desc pool id
  3395. */
  3396. static inline void
  3397. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3398. uint8_t desc_pool_id)
  3399. {
  3400. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3401. tx_desc->vdev = NULL;
  3402. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3403. }
  3404. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3405. struct dp_vdev *vdev,
  3406. bool force_free)
  3407. {
  3408. uint8_t i, num_pool;
  3409. uint32_t j;
  3410. uint32_t num_desc, page_id, offset;
  3411. uint16_t num_desc_per_page;
  3412. struct dp_soc *soc = pdev->soc;
  3413. struct dp_tx_desc_s *tx_desc = NULL;
  3414. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3415. if (!vdev && !force_free) {
  3416. dp_err("Reset TX desc vdev, Vdev param is required!");
  3417. return;
  3418. }
  3419. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3420. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3421. for (i = 0; i < num_pool; i++) {
  3422. tx_desc_pool = &soc->tx_desc[i];
  3423. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3424. continue;
  3425. num_desc_per_page =
  3426. tx_desc_pool->desc_pages.num_element_per_page;
  3427. for (j = 0; j < num_desc; j++) {
  3428. page_id = j / num_desc_per_page;
  3429. offset = j % num_desc_per_page;
  3430. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3431. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3432. if (force_free) {
  3433. dp_tx_comp_free_buf(soc, tx_desc);
  3434. dp_tx_desc_release(tx_desc, i);
  3435. } else {
  3436. dp_tx_desc_reset_vdev(soc, tx_desc,
  3437. i);
  3438. }
  3439. }
  3440. }
  3441. }
  3442. }
  3443. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3444. /**
  3445. * dp_tx_vdev_detach() - detach vdev from dp tx
  3446. * @vdev: virtual device instance
  3447. *
  3448. * Return: QDF_STATUS_SUCCESS: success
  3449. * QDF_STATUS_E_RESOURCES: Error return
  3450. */
  3451. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3452. {
  3453. struct dp_pdev *pdev = vdev->pdev;
  3454. /* Reset TX desc associated to this Vdev as NULL */
  3455. dp_tx_desc_flush(pdev, vdev, false);
  3456. dp_tx_vdev_multipass_deinit(vdev);
  3457. return QDF_STATUS_SUCCESS;
  3458. }
  3459. /**
  3460. * dp_tx_pdev_attach() - attach pdev to dp tx
  3461. * @pdev: physical device instance
  3462. *
  3463. * Return: QDF_STATUS_SUCCESS: success
  3464. * QDF_STATUS_E_RESOURCES: Error return
  3465. */
  3466. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3467. {
  3468. struct dp_soc *soc = pdev->soc;
  3469. /* Initialize Flow control counters */
  3470. qdf_atomic_init(&pdev->num_tx_exception);
  3471. qdf_atomic_init(&pdev->num_tx_outstanding);
  3472. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3473. /* Initialize descriptors in TCL Ring */
  3474. hal_tx_init_data_ring(soc->hal_soc,
  3475. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3476. }
  3477. return QDF_STATUS_SUCCESS;
  3478. }
  3479. /**
  3480. * dp_tx_pdev_detach() - detach pdev from dp tx
  3481. * @pdev: physical device instance
  3482. *
  3483. * Return: QDF_STATUS_SUCCESS: success
  3484. * QDF_STATUS_E_RESOURCES: Error return
  3485. */
  3486. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3487. {
  3488. /* flush TX outstanding data per pdev */
  3489. dp_tx_desc_flush(pdev, NULL, true);
  3490. dp_tx_me_exit(pdev);
  3491. return QDF_STATUS_SUCCESS;
  3492. }
  3493. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3494. /* Pools will be allocated dynamically */
  3495. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3496. int num_desc)
  3497. {
  3498. uint8_t i;
  3499. for (i = 0; i < num_pool; i++) {
  3500. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3501. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3502. }
  3503. return 0;
  3504. }
  3505. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3506. {
  3507. uint8_t i;
  3508. for (i = 0; i < num_pool; i++)
  3509. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3510. }
  3511. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3512. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3513. int num_desc)
  3514. {
  3515. uint8_t i;
  3516. /* Allocate software Tx descriptor pools */
  3517. for (i = 0; i < num_pool; i++) {
  3518. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3519. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3520. "%s Tx Desc Pool alloc %d failed %pK",
  3521. __func__, i, soc);
  3522. return ENOMEM;
  3523. }
  3524. }
  3525. return 0;
  3526. }
  3527. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3528. {
  3529. uint8_t i;
  3530. for (i = 0; i < num_pool; i++) {
  3531. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3532. if (dp_tx_desc_pool_free(soc, i)) {
  3533. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3534. "%s Tx Desc Pool Free failed", __func__);
  3535. }
  3536. }
  3537. }
  3538. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3539. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3540. /**
  3541. * dp_tso_attach_wifi3() - TSO attach handler
  3542. * @txrx_soc: Opaque Dp handle
  3543. *
  3544. * Reserve TSO descriptor buffers
  3545. *
  3546. * Return: QDF_STATUS_E_FAILURE on failure or
  3547. * QDF_STATUS_SUCCESS on success
  3548. */
  3549. static
  3550. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3551. {
  3552. return dp_tso_soc_attach(txrx_soc);
  3553. }
  3554. /**
  3555. * dp_tso_detach_wifi3() - TSO Detach handler
  3556. * @txrx_soc: Opaque Dp handle
  3557. *
  3558. * Deallocate TSO descriptor buffers
  3559. *
  3560. * Return: QDF_STATUS_E_FAILURE on failure or
  3561. * QDF_STATUS_SUCCESS on success
  3562. */
  3563. static
  3564. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3565. {
  3566. return dp_tso_soc_detach(txrx_soc);
  3567. }
  3568. #else
  3569. static
  3570. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3571. {
  3572. return QDF_STATUS_SUCCESS;
  3573. }
  3574. static
  3575. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3576. {
  3577. return QDF_STATUS_SUCCESS;
  3578. }
  3579. #endif
  3580. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  3581. {
  3582. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3583. uint8_t i;
  3584. uint8_t num_pool;
  3585. uint32_t num_desc;
  3586. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3587. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3588. for (i = 0; i < num_pool; i++)
  3589. dp_tx_tso_desc_pool_free(soc, i);
  3590. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3591. __func__, num_pool, num_desc);
  3592. for (i = 0; i < num_pool; i++)
  3593. dp_tx_tso_num_seg_pool_free(soc, i);
  3594. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3595. __func__, num_pool, num_desc);
  3596. return QDF_STATUS_SUCCESS;
  3597. }
  3598. /**
  3599. * dp_tso_attach() - TSO attach handler
  3600. * @txrx_soc: Opaque Dp handle
  3601. *
  3602. * Reserve TSO descriptor buffers
  3603. *
  3604. * Return: QDF_STATUS_E_FAILURE on failure or
  3605. * QDF_STATUS_SUCCESS on success
  3606. */
  3607. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  3608. {
  3609. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3610. uint8_t i;
  3611. uint8_t num_pool;
  3612. uint32_t num_desc;
  3613. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3614. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3615. for (i = 0; i < num_pool; i++) {
  3616. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3617. dp_err("TSO Desc Pool alloc %d failed %pK",
  3618. i, soc);
  3619. return QDF_STATUS_E_FAILURE;
  3620. }
  3621. }
  3622. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3623. __func__, num_pool, num_desc);
  3624. for (i = 0; i < num_pool; i++) {
  3625. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3626. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3627. i, soc);
  3628. return QDF_STATUS_E_FAILURE;
  3629. }
  3630. }
  3631. return QDF_STATUS_SUCCESS;
  3632. }
  3633. /**
  3634. * dp_tx_soc_detach() - detach soc from dp tx
  3635. * @soc: core txrx main context
  3636. *
  3637. * This function will detach dp tx into main device context
  3638. * will free dp tx resource and initialize resources
  3639. *
  3640. * Return: QDF_STATUS_SUCCESS: success
  3641. * QDF_STATUS_E_RESOURCES: Error return
  3642. */
  3643. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3644. {
  3645. uint8_t num_pool;
  3646. uint16_t num_desc;
  3647. uint16_t num_ext_desc;
  3648. uint8_t i;
  3649. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3650. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3651. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3652. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3653. dp_tx_flow_control_deinit(soc);
  3654. dp_tx_delete_static_pools(soc, num_pool);
  3655. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3656. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3657. __func__, num_pool, num_desc);
  3658. for (i = 0; i < num_pool; i++) {
  3659. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3660. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3661. "%s Tx Ext Desc Pool Free failed",
  3662. __func__);
  3663. return QDF_STATUS_E_RESOURCES;
  3664. }
  3665. }
  3666. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3667. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3668. __func__, num_pool, num_ext_desc);
  3669. status = dp_tso_detach_wifi3(soc);
  3670. if (status != QDF_STATUS_SUCCESS)
  3671. return status;
  3672. return QDF_STATUS_SUCCESS;
  3673. }
  3674. /**
  3675. * dp_tx_soc_attach() - attach soc to dp tx
  3676. * @soc: core txrx main context
  3677. *
  3678. * This function will attach dp tx into main device context
  3679. * will allocate dp tx resource and initialize resources
  3680. *
  3681. * Return: QDF_STATUS_SUCCESS: success
  3682. * QDF_STATUS_E_RESOURCES: Error return
  3683. */
  3684. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3685. {
  3686. uint8_t i;
  3687. uint8_t num_pool;
  3688. uint32_t num_desc;
  3689. uint32_t num_ext_desc;
  3690. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3691. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3692. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3693. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3694. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3695. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3696. __func__, num_pool, num_desc);
  3697. if ((num_pool > MAX_TXDESC_POOLS) ||
  3698. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  3699. goto fail;
  3700. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3701. goto fail;
  3702. dp_tx_flow_control_init(soc);
  3703. /* Allocate extension tx descriptor pools */
  3704. for (i = 0; i < num_pool; i++) {
  3705. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3706. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3707. "MSDU Ext Desc Pool alloc %d failed %pK",
  3708. i, soc);
  3709. goto fail;
  3710. }
  3711. }
  3712. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3713. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3714. __func__, num_pool, num_ext_desc);
  3715. status = dp_tso_attach_wifi3((void *)soc);
  3716. if (status != QDF_STATUS_SUCCESS)
  3717. goto fail;
  3718. /* Initialize descriptors in TCL Rings */
  3719. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3720. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3721. hal_tx_init_data_ring(soc->hal_soc,
  3722. soc->tcl_data_ring[i].hal_srng);
  3723. }
  3724. if (wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  3725. hal_tx_init_data_ring(soc->hal_soc,
  3726. soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng);
  3727. }
  3728. /*
  3729. * Initialize command/credit ring descriptor
  3730. * Command/CREDIT ring also used for sending DATA cmds
  3731. */
  3732. hal_tx_init_cmd_credit_ring(soc->hal_soc,
  3733. soc->tcl_cmd_credit_ring.hal_srng);
  3734. /*
  3735. * todo - Add a runtime config option to enable this.
  3736. */
  3737. /*
  3738. * Due to multiple issues on NPR EMU, enable it selectively
  3739. * only for NPR EMU, should be removed, once NPR platforms
  3740. * are stable.
  3741. */
  3742. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3743. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3744. "%s HAL Tx init Success", __func__);
  3745. return QDF_STATUS_SUCCESS;
  3746. fail:
  3747. /* Detach will take care of freeing only allocated resources */
  3748. dp_tx_soc_detach(soc);
  3749. return QDF_STATUS_E_RESOURCES;
  3750. }