36637cf177
Added ipq5332 target header files under qca5332 to make fw-api project compatible to host. Change-Id: Iee6b3f2a809f31e62b45a0f6e9a7cbb66e070fa0
869 行
35 KiB
C
869 行
35 KiB
C
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/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _TX_PEER_ENTRY_H_
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#define _TX_PEER_ENTRY_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#define NUM_OF_DWORDS_TX_PEER_ENTRY 18
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#define NUM_OF_QWORDS_TX_PEER_ENTRY 9
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struct tx_peer_entry {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t mac_addr_a_31_0 : 32; // [31:0]
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uint32_t mac_addr_a_47_32 : 16, // [15:0]
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mac_addr_b_15_0 : 16; // [31:16]
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uint32_t mac_addr_b_47_16 : 32; // [31:0]
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uint32_t use_ad_b : 1, // [0:0]
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strip_insert_vlan_inner : 1, // [1:1]
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strip_insert_vlan_outer : 1, // [2:2]
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vlan_llc_mode : 1, // [3:3]
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key_type : 4, // [7:4]
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a_msdu_wds_ad3_ad4 : 3, // [10:8]
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ignore_hard_filters : 1, // [11:11]
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ignore_soft_filters : 1, // [12:12]
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epd_output : 1, // [13:13]
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wds : 1, // [14:14]
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insert_or_strip : 1, // [15:15]
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sw_filter_id : 16; // [31:16]
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uint32_t temporal_key_31_0 : 32; // [31:0]
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uint32_t temporal_key_63_32 : 32; // [31:0]
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uint32_t temporal_key_95_64 : 32; // [31:0]
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uint32_t temporal_key_127_96 : 32; // [31:0]
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uint32_t temporal_key_159_128 : 32; // [31:0]
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uint32_t temporal_key_191_160 : 32; // [31:0]
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uint32_t temporal_key_223_192 : 32; // [31:0]
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uint32_t temporal_key_255_224 : 32; // [31:0]
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uint32_t sta_partial_aid : 11, // [10:0]
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transmit_vif : 4, // [14:11]
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block_this_user : 1, // [15:15]
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mesh_amsdu_mode : 2, // [17:16]
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use_qos_alt_mute_mask : 1, // [18:18]
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dl_ul_direction : 1, // [19:19]
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reserved_12 : 12; // [31:20]
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uint32_t insert_vlan_outer_tci : 16, // [15:0]
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insert_vlan_inner_tci : 16; // [31:16]
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uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0]
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uint32_t multi_link_addr_ad1_47_32 : 16, // [15:0]
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multi_link_addr_ad2_15_0 : 16; // [31:16]
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uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0]
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uint32_t multi_link_addr_crypto_enable : 1, // [0:0]
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reserved_17a : 15, // [15:1]
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sw_peer_id : 16; // [31:16]
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#else
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uint32_t mac_addr_a_31_0 : 32; // [31:0]
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uint32_t mac_addr_b_15_0 : 16, // [31:16]
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mac_addr_a_47_32 : 16; // [15:0]
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uint32_t mac_addr_b_47_16 : 32; // [31:0]
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uint32_t sw_filter_id : 16, // [31:16]
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insert_or_strip : 1, // [15:15]
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wds : 1, // [14:14]
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epd_output : 1, // [13:13]
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ignore_soft_filters : 1, // [12:12]
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ignore_hard_filters : 1, // [11:11]
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a_msdu_wds_ad3_ad4 : 3, // [10:8]
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key_type : 4, // [7:4]
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vlan_llc_mode : 1, // [3:3]
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strip_insert_vlan_outer : 1, // [2:2]
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strip_insert_vlan_inner : 1, // [1:1]
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use_ad_b : 1; // [0:0]
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uint32_t temporal_key_31_0 : 32; // [31:0]
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uint32_t temporal_key_63_32 : 32; // [31:0]
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uint32_t temporal_key_95_64 : 32; // [31:0]
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uint32_t temporal_key_127_96 : 32; // [31:0]
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uint32_t temporal_key_159_128 : 32; // [31:0]
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uint32_t temporal_key_191_160 : 32; // [31:0]
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uint32_t temporal_key_223_192 : 32; // [31:0]
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uint32_t temporal_key_255_224 : 32; // [31:0]
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uint32_t reserved_12 : 12, // [31:20]
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dl_ul_direction : 1, // [19:19]
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use_qos_alt_mute_mask : 1, // [18:18]
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mesh_amsdu_mode : 2, // [17:16]
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block_this_user : 1, // [15:15]
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transmit_vif : 4, // [14:11]
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sta_partial_aid : 11; // [10:0]
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uint32_t insert_vlan_inner_tci : 16, // [31:16]
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insert_vlan_outer_tci : 16; // [15:0]
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uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0]
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uint32_t multi_link_addr_ad2_15_0 : 16, // [31:16]
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multi_link_addr_ad1_47_32 : 16; // [15:0]
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uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0]
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uint32_t sw_peer_id : 16, // [31:16]
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reserved_17a : 15, // [15:1]
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multi_link_addr_crypto_enable : 1; // [0:0]
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#endif
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};
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/* Description MAC_ADDR_A_31_0
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Consumer: TX OLE
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Producer: SW
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Lower 32 bits of the MAC address A used by HW for encapsulating
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802.11
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<legal all>
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*/
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#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET 0x0000000000000000
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#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB 0
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#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB 31
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#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK 0x00000000ffffffff
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/* Description MAC_ADDR_A_47_32
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Consumer: TX OLE
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Producer: SW
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Upper 16 bits of the MAC address A used by HW for encapsulating
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802.11
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<legal all>
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*/
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#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET 0x0000000000000000
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#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB 32
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#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB 47
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#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK 0x0000ffff00000000
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/* Description MAC_ADDR_B_15_0
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Consumer: TX OLE
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Producer: SW
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Lower 16 bits of the MAC address B used by HW for encapsulating
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802.11
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<legal all>
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*/
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#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET 0x0000000000000000
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#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB 48
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#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB 63
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#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK 0xffff000000000000
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/* Description MAC_ADDR_B_47_16
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Consumer: TX OLE
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Producer: SW
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Upper 32 bits of the MAC address B used by HW for encapsulating
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802.11
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<legal all>
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*/
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#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET 0x0000000000000008
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#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB 0
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#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB 31
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#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK 0x00000000ffffffff
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/* Description USE_AD_B
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Consumer: TX OLE
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Producer: SW
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The bit is only evaluated when this MSDU is the first MSDU
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in an MPDU. For other MSDUs this bit setting is ignored.
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It is part of the sw_msdu_param coming from the QM ADD frame
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command.
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Normally in AP mode the DA address is used as the RA. This
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is normally fine but the use_ad_b bit should be set when
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DA is a multicast/broadcast address but we want to send
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this packet using the destination STA address which will
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be held in the mac_addr_b field of the peer descriptor.
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<legal all>
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*/
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#define TX_PEER_ENTRY_USE_AD_B_OFFSET 0x0000000000000008
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#define TX_PEER_ENTRY_USE_AD_B_LSB 32
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#define TX_PEER_ENTRY_USE_AD_B_MSB 32
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#define TX_PEER_ENTRY_USE_AD_B_MASK 0x0000000100000000
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/* Description STRIP_INSERT_VLAN_INNER
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Consumer: TX OLE
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Producer: SW
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Strip or insert C-VLAN during encapsulation.
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Insert_or_strip determines whether C-VLAN is to be stripped
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or inserted.
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<legal all>
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*/
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#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET 0x0000000000000008
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#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB 33
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#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB 33
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#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK 0x0000000200000000
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/* Description STRIP_INSERT_VLAN_OUTER
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Consumer: TX OLE
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Producer: SW
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Strip or insert S-VLAN during encapsulation.
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Insert or strip determines whether S-VLAN is to be stripped
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or inserted.
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<legal all>
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*/
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#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET 0x0000000000000008
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#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB 34
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#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB 34
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#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK 0x0000000400000000
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/* Description VLAN_LLC_MODE
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Consumer: TX OLE
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Producer: SW
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If set encapsulate/decapsulate using the Scorpion compatible
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VLAN LLC format
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*/
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#define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET 0x0000000000000008
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#define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB 35
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#define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB 35
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#define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK 0x0000000800000000
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/* Description KEY_TYPE
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Consumer: TX OLE, TX CRYPTO
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Producer: SW
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The key_type indicates the cipher suite corresponding to
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this peer entry:
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<enum 0 wep_40> WEP 40-bit
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<enum 1 wep_104> WEP 104-bit
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<enum 2 tkip_no_mic> TKIP without MIC
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<enum 3 wep_128> WEP 128-bit
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<enum 4 tkip_with_mic> TKIP with MIC
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<enum 5 wapi> WAPI
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<enum 6 aes_ccmp_128> AES CCMP 128
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<enum 7 no_cipher> No crypto
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<enum 8 aes_ccmp_256> AES CCMP 256
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<enum 9 aes_gcmp_128> AES GCMP 128
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<enum 10 aes_gcmp_256> AES GCMP 256
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<enum 11 wapi_gcm_sm4> WAPI GCM SM4
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<enum 12 wep_varied_width> DO NOT USE. This Key type ONLY
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to be used for RX side
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<legal 0-12>
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*/
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#define TX_PEER_ENTRY_KEY_TYPE_OFFSET 0x0000000000000008
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#define TX_PEER_ENTRY_KEY_TYPE_LSB 36
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#define TX_PEER_ENTRY_KEY_TYPE_MSB 39
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#define TX_PEER_ENTRY_KEY_TYPE_MASK 0x000000f000000000
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/* Description A_MSDU_WDS_AD3_AD4
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Consumer: TX OLE
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Producer: SW
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Determines the selection of AD3 and AD4 for A-MSDU 4 address
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frames (WDS):
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<enum 0 ad3_a__ad4_a> AD3 = AD_A, AD4 = AD_A
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<enum 1 ad3_a__ad4_b> AD3 = AD_A, AD4 = AD_B
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<enum 2 ad3_b__ad4_a> AD3 = AD_B, AD4 = AD_A
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<enum 3 ad3_b__ad4_b> AD3 = AD_B, AD4 = AD_B
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<enum 4 ad3_da__ad4_sa> AD3 = DA, AD4 = SA
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<legal 0-4>
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*/
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#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET 0x0000000000000008
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#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB 40
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#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB 42
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#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK 0x0000070000000000
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/* Description IGNORE_HARD_FILTERS
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SW can program this bit to 0x1 to ignore HARD filter conditions
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and HWSCH will proceed with transmission, even if the HARD
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filter bit is set in Filter LUT.
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Note that SOFT filter conditions will filter the command,
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even if this bit is set and ignore_soft_filters is not set
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For filtering all frames marked in the Filter LUT, both
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ignore_soft_filters and ignore_hard_filters should be set
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<legal all>
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*/
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#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET 0x0000000000000008
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#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB 43
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#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB 43
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#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK 0x0000080000000000
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/* Description IGNORE_SOFT_FILTERS
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SW can program this bit to 0x1 to ignore SOFT filter conditions
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and HWSCH will proceed with transmission, even if the SOFT
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filter bit is set in Filter LUT.
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Note that HARD filter conditions will filter the command,
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even if this bit is set and ignore_hard_filters is not set
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For filtering all frames marked in the Filter LUT, both
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ignore_soft_filters and ignore_hard_filters should be set
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<legal all>
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*/
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#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET 0x0000000000000008
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#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB 44
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#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB 44
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#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK 0x0000100000000000
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/* Description EPD_OUTPUT
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Consumer: TX OLE
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Producer: SW
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If set use EPD instead of LPD
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*/
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#define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET 0x0000000000000008
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#define TX_PEER_ENTRY_EPD_OUTPUT_LSB 45
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#define TX_PEER_ENTRY_EPD_OUTPUT_MSB 45
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#define TX_PEER_ENTRY_EPD_OUTPUT_MASK 0x0000200000000000
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/* Description WDS
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If set all the frames in this transmission (for this user)
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are 4-address frame.
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If not all frames need to use 4 address format, SW has per
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frame 'wds' control, by using the 'wds' flag in the MSDU_EXTENSION
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descriptor
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Used by the OLE during encapsulation.
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<legal all>
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*/
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#define TX_PEER_ENTRY_WDS_OFFSET 0x0000000000000008
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#define TX_PEER_ENTRY_WDS_LSB 46
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#define TX_PEER_ENTRY_WDS_MSB 46
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#define TX_PEER_ENTRY_WDS_MASK 0x0000400000000000
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/* Description INSERT_OR_STRIP
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<enum 0 TXOLE_STRIP_VLAN> TXOLE will strip inner or outer
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VLAN (if present in the frame) based on Strip_insert_vlan_{inner,
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outer}
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<enum 1 TXOLE_INSERT_VLAN> TXOLE will insert inner or outer
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VLAN (only if absent in the frame) based on Strip_insert_vlan_{inner,
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outer} with the TCI(s) given by Insert_vlan_{inner, outer}_tci
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NOTE: Strip VLAN is not supported by TCL.
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<legal all>
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*/
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#define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET 0x0000000000000008
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#define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB 47
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#define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB 47
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#define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK 0x0000800000000000
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/* Description SW_FILTER_ID
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Consumer: SCH
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Producer: SW
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The full STA AID.
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Use by SCH to determine if transmission for this STA should
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be filtered as it just went into power save state.
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In case of MU transmission, it means only this STA needs
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to be removed from the transmission...
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<legal all>
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*/
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#define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET 0x0000000000000008
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#define TX_PEER_ENTRY_SW_FILTER_ID_LSB 48
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#define TX_PEER_ENTRY_SW_FILTER_ID_MSB 63
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#define TX_PEER_ENTRY_SW_FILTER_ID_MASK 0xffff000000000000
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/* Description TEMPORAL_KEY_31_0
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Consumer: TX CRYPTO
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Producer: SW
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First 32 bits of the temporal key material. The temporal
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key for WEP 40-bit uses the first 40 bits, WEP 104-bit
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uses the first 104 bits, WEP 128-bit uses all 128 bits,
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TKIP with/without MIC uses 128 bits, WAPI uses all 128 bits,
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and AES-CCM uses all 128 bits.
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Note that for TKIP, the 64 MIC bits are located in fields
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'temporal_key[255:192]
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<legal all>
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*/
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#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET 0x0000000000000010
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#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB 0
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#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB 31
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#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK 0x00000000ffffffff
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/* Description TEMPORAL_KEY_63_32
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Consumer: TX CRYPTO
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|
Producer: SW
|
|
|
|
Second 32 bits of the temporal key material. See the description
|
|
of temporal_key_31_0.
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET 0x0000000000000010
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB 32
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB 63
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK 0xffffffff00000000
|
|
|
|
|
|
/* Description TEMPORAL_KEY_95_64
|
|
|
|
Consumer: TX CRYPTO
|
|
Producer: SW
|
|
|
|
Third 32 bits of the temporal key material. See the description
|
|
of temporal_key_31_0.
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET 0x0000000000000018
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB 0
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB 31
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK 0x00000000ffffffff
|
|
|
|
|
|
/* Description TEMPORAL_KEY_127_96
|
|
|
|
Consumer: TX CRYPTO
|
|
Producer: SW
|
|
|
|
Fourth 32 bits of the temporal key material. See the description
|
|
of temporal_key_31_0.
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET 0x0000000000000018
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB 32
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB 63
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK 0xffffffff00000000
|
|
|
|
|
|
/* Description TEMPORAL_KEY_159_128
|
|
|
|
Consumer: TX CRYPTO
|
|
Producer: SW
|
|
|
|
Fifth 32 bits of the temporal key material. See the description
|
|
of temporal_key_31_0.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET 0x0000000000000020
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB 0
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB 31
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK 0x00000000ffffffff
|
|
|
|
|
|
/* Description TEMPORAL_KEY_191_160
|
|
|
|
Consumer: TX CRYPTO
|
|
Producer: SW
|
|
|
|
Final 32 bits of the temporal key material. See the description
|
|
of temporal_key_31_0.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET 0x0000000000000020
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB 32
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB 63
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK 0xffffffff00000000
|
|
|
|
|
|
/* Description TEMPORAL_KEY_223_192
|
|
|
|
Consumer: TX CRYPTO
|
|
Producer: SW
|
|
|
|
Final 32 bits of the temporal key material. See the description
|
|
of temporal_key_31_0.
|
|
|
|
For TKIP this is the TX MIC key[31:0].
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET 0x0000000000000028
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB 0
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB 31
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK 0x00000000ffffffff
|
|
|
|
|
|
/* Description TEMPORAL_KEY_255_224
|
|
|
|
Consumer: TX CRYPTO
|
|
Producer: SW
|
|
|
|
Final 32 bits of the temporal key material. See the description
|
|
of temporal_key_31_0.
|
|
|
|
For TKIP this is the TX MIC key[63:32].
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET 0x0000000000000028
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB 32
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB 63
|
|
#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK 0xffffffff00000000
|
|
|
|
|
|
/* Description STA_PARTIAL_AID
|
|
|
|
This field in only used by the PDG. All other modules should
|
|
ignore this field.
|
|
|
|
This field is only valid in case of a transmission at VHT
|
|
rates or HE rates.
|
|
|
|
For VHT:
|
|
This field is the Partial AID to be filled in to the VHT
|
|
preamble.
|
|
|
|
For HE:
|
|
This field is the sta_aid to be filled into the SIG B field.
|
|
|
|
|
|
In 11ah mode of operation, this field is provided by SW
|
|
to populate the the ID value of the SIG preamble of the
|
|
PPDU
|
|
*/
|
|
|
|
#define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET 0x0000000000000030
|
|
#define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB 0
|
|
#define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB 10
|
|
#define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK 0x00000000000007ff
|
|
|
|
|
|
/* Description TRANSMIT_VIF
|
|
|
|
Consumer: TXOLE
|
|
Producer: SW
|
|
|
|
The VIF for this transmission. Used in MCC mode to control/overwrite
|
|
the PM bit settings.
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET 0x0000000000000030
|
|
#define TX_PEER_ENTRY_TRANSMIT_VIF_LSB 11
|
|
#define TX_PEER_ENTRY_TRANSMIT_VIF_MSB 14
|
|
#define TX_PEER_ENTRY_TRANSMIT_VIF_MASK 0x0000000000007800
|
|
|
|
|
|
/* Description BLOCK_THIS_USER
|
|
|
|
Consumer: PDG
|
|
Producer: SCH
|
|
|
|
Set by SCH when a MU transmission is started and this STA
|
|
has (just) entered or is in power save mode.
|
|
Due to the MU transmission SCH shall not terminate this
|
|
MU transmission (as is done with SU transmission), but continue
|
|
with the transmissions for all other STAs.
|
|
|
|
As a result of this bit being set, PDG will at certain moment
|
|
generate the MPDU limit TLV with field Num_mpdu_user set
|
|
to 0
|
|
|
|
PDG shall treat this user as a user without any data. All
|
|
rules related to terminating MU transmissions when too
|
|
many users do not have any data shall include this user
|
|
as a user having zero data.
|
|
|
|
When clear, PDG can ignore this bit
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET 0x0000000000000030
|
|
#define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB 15
|
|
#define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB 15
|
|
#define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK 0x0000000000008000
|
|
|
|
|
|
/* Description MESH_AMSDU_MODE
|
|
|
|
Consumer: TX OLE
|
|
Producer: SW
|
|
|
|
This field is used only when the first MSDU of any MPDU
|
|
that TX OLE encounters is in Native WiFi format and includes
|
|
a 'Mesh Control' field between the header and the LLC.
|
|
|
|
The creation of the A-MSDU 'Length' field in the MPDU (if
|
|
aggregating multiple MSDUs) is decided by the value of
|
|
this field.
|
|
|
|
<enum 0 MESH_MODE_0> DO NOT USE
|
|
<enum 1 MESH_MODE_Q2Q> A-MSDU 'Length' is big endian and
|
|
includes the length of Mesh Control.
|
|
<enum 2 MESH_MODE_11S_BE> A-MSDU 'Length' is big endian
|
|
and excludes the length of Mesh Control.
|
|
<enum 3 MESH_MODE_11S_LE> A-MSDU 'Length' is little endian
|
|
and excludes the length of Mesh Control. This is 802.11s-compliant.
|
|
|
|
|
|
NOTE 1: For compatibility TXOLE treats MESH_MODE_0 identically
|
|
to MESH_MODE_Q2Q.
|
|
|
|
NOTE 2: This e-numeration is different from other fields
|
|
named Mesh_sta or mesh_enable where the value zero disables
|
|
mesh processing.
|
|
<legal 0-3>
|
|
*/
|
|
|
|
#define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET 0x0000000000000030
|
|
#define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB 16
|
|
#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB 17
|
|
#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK 0x0000000000030000
|
|
|
|
|
|
/* Description USE_QOS_ALT_MUTE_MASK
|
|
|
|
Lithium and prior generation WAPI implementations did not
|
|
mute any QoS Control bits when generating the AAD. Setting
|
|
this bit chooses an alternative configurable QoS Control
|
|
mute mask in Crypto for compatibility with those chips.
|
|
|
|
|
|
For AES, alternative configurable QoS Control mute mask
|
|
is required in Crypto to support SPP A-MSDUs for increased
|
|
security.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET 0x0000000000000030
|
|
#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB 18
|
|
#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB 18
|
|
#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK 0x0000000000040000
|
|
|
|
|
|
/* Description DL_UL_DIRECTION
|
|
|
|
'Direction' to be inferred for raw WiFi esp. management
|
|
frames sent to a multi-link peer, for translating RA and/or
|
|
TA.
|
|
|
|
<enum 0 DL_UL_FLAG_IS_DL_OR_TDLS>
|
|
<enum 1 DL_UL_FLAG_IS_UL>
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET 0x0000000000000030
|
|
#define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB 19
|
|
#define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB 19
|
|
#define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK 0x0000000000080000
|
|
|
|
|
|
/* Description RESERVED_12
|
|
|
|
<legal 0>
|
|
*/
|
|
|
|
#define TX_PEER_ENTRY_RESERVED_12_OFFSET 0x0000000000000030
|
|
#define TX_PEER_ENTRY_RESERVED_12_LSB 20
|
|
#define TX_PEER_ENTRY_RESERVED_12_MSB 31
|
|
#define TX_PEER_ENTRY_RESERVED_12_MASK 0x00000000fff00000
|
|
|
|
|
|
/* Description INSERT_VLAN_OUTER_TCI
|
|
|
|
The tag control info to use when TXOLE inserts outer VLAN
|
|
if enabled by Strip_insert_vlan_outer and Insert_or_strip
|
|
|
|
*/
|
|
|
|
#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET 0x0000000000000030
|
|
#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB 32
|
|
#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB 47
|
|
#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK 0x0000ffff00000000
|
|
|
|
|
|
/* Description INSERT_VLAN_INNER_TCI
|
|
|
|
The tag control info to use when TXOLE inserts inner VLAN
|
|
if enabled by Strip_insert_vlan_inner and Insert_or_strip
|
|
|
|
*/
|
|
|
|
#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET 0x0000000000000030
|
|
#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB 48
|
|
#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB 63
|
|
#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK 0xffff000000000000
|
|
|
|
|
|
/* Description MULTI_LINK_ADDR_AD1_31_0
|
|
|
|
Consumer: TX CRYPTO
|
|
Producer: FW
|
|
|
|
Field only valid if Multi_link_addr_crypto_enable is set
|
|
|
|
|
|
Multi-link receiver address (address1) for transmissions
|
|
matching this peer entry, bits [31:0]
|
|
*/
|
|
|
|
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_OFFSET 0x0000000000000038
|
|
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_LSB 0
|
|
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_MSB 31
|
|
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_MASK 0x00000000ffffffff
|
|
|
|
|
|
/* Description MULTI_LINK_ADDR_AD1_47_32
|
|
|
|
Consumer: TX CRYPTO
|
|
Producer: FW
|
|
|
|
Field only valid if Multi_link_addr_crypto_enable is set
|
|
|
|
|
|
Multi-link receiver address (address1) for transmissions
|
|
matching this peer entry, bits [47:32]
|
|
*/
|
|
|
|
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_OFFSET 0x0000000000000038
|
|
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_LSB 32
|
|
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_MSB 47
|
|
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_MASK 0x0000ffff00000000
|
|
|
|
|
|
/* Description MULTI_LINK_ADDR_AD2_15_0
|
|
|
|
Consumer: TX CRYPTO
|
|
Producer: FW
|
|
|
|
Field only valid if Multi_link_addr_crypto_enable is set
|
|
|
|
|
|
Multi-link transmitter address (address2) for transmissions
|
|
matching this peer entry, bits [15:0]
|
|
*/
|
|
|
|
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_OFFSET 0x0000000000000038
|
|
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_LSB 48
|
|
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_MSB 63
|
|
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_MASK 0xffff000000000000
|
|
|
|
|
|
/* Description MULTI_LINK_ADDR_AD2_47_16
|
|
|
|
Consumer: TX CRYPTO
|
|
Producer: FW
|
|
|
|
Field only valid if Multi_link_addr_crypto_enable is set
|
|
|
|
|
|
Multi-link transmitter address (address2) for transmissions
|
|
matching this peer entry, bits [47:16]
|
|
*/
|
|
|
|
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_OFFSET 0x0000000000000040
|
|
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_LSB 0
|
|
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_MSB 31
|
|
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_MASK 0x00000000ffffffff
|
|
|
|
|
|
/* Description MULTI_LINK_ADDR_CRYPTO_ENABLE
|
|
|
|
Consumer: TX CRYPTO
|
|
Producer: FW
|
|
|
|
If set, TX CRYPTO shall convert Address1, Address2 and BSSID
|
|
of received data frames to multi-link addresses for the
|
|
AAD and Nonce during encryption.
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET 0x0000000000000040
|
|
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB 32
|
|
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB 32
|
|
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK 0x0000000100000000
|
|
|
|
|
|
/* Description RESERVED_17A
|
|
|
|
<legal 0>
|
|
*/
|
|
|
|
#define TX_PEER_ENTRY_RESERVED_17A_OFFSET 0x0000000000000040
|
|
#define TX_PEER_ENTRY_RESERVED_17A_LSB 33
|
|
#define TX_PEER_ENTRY_RESERVED_17A_MSB 47
|
|
#define TX_PEER_ENTRY_RESERVED_17A_MASK 0x0000fffe00000000
|
|
|
|
|
|
/* Description SW_PEER_ID
|
|
|
|
This field indicates a unique peer identifier provided by
|
|
FW, to be logged via TXMON to host SW.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_PEER_ENTRY_SW_PEER_ID_OFFSET 0x0000000000000040
|
|
#define TX_PEER_ENTRY_SW_PEER_ID_LSB 48
|
|
#define TX_PEER_ENTRY_SW_PEER_ID_MSB 63
|
|
#define TX_PEER_ENTRY_SW_PEER_ID_MASK 0xffff000000000000
|
|
|
|
|
|
|
|
#endif // TX_PEER_ENTRY
|