36637cf177
Added ipq5332 target header files under qca5332 to make fw-api project compatible to host. Change-Id: Iee6b3f2a809f31e62b45a0f6e9a7cbb66e070fa0
311 行
13 KiB
C
311 行
13 KiB
C
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/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _TCL_STATUS_RING_H_
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#define _TCL_STATUS_RING_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#define NUM_OF_DWORDS_TCL_STATUS_RING 8
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struct tcl_status_ring {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t gse_ctrl : 4, // [3:0]
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ase_fse_sel : 1, // [4:4]
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cache_op_res : 2, // [6:5]
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index_search_en : 1, // [7:7]
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msdu_cnt_n : 24; // [31:8]
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uint32_t msdu_byte_cnt_n : 32; // [31:0]
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uint32_t msdu_timestmp_n : 32; // [31:0]
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uint32_t cmd_meta_data_31_0 : 32; // [31:0]
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uint32_t cmd_meta_data_63_32 : 32; // [31:0]
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uint32_t hash_indx_val : 20, // [19:0]
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cache_set_num : 4, // [23:20]
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reserved_5a : 8; // [31:24]
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uint32_t reserved_6a : 32; // [31:0]
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uint32_t reserved_7a : 20, // [19:0]
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ring_id : 8, // [27:20]
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looping_count : 4; // [31:28]
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#else
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uint32_t msdu_cnt_n : 24, // [31:8]
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index_search_en : 1, // [7:7]
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cache_op_res : 2, // [6:5]
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ase_fse_sel : 1, // [4:4]
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gse_ctrl : 4; // [3:0]
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uint32_t msdu_byte_cnt_n : 32; // [31:0]
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uint32_t msdu_timestmp_n : 32; // [31:0]
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uint32_t cmd_meta_data_31_0 : 32; // [31:0]
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uint32_t cmd_meta_data_63_32 : 32; // [31:0]
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uint32_t reserved_5a : 8, // [31:24]
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cache_set_num : 4, // [23:20]
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hash_indx_val : 20; // [19:0]
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uint32_t reserved_6a : 32; // [31:0]
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uint32_t looping_count : 4, // [31:28]
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ring_id : 8, // [27:20]
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reserved_7a : 20; // [19:0]
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#endif
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};
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/* Description GSE_CTRL
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GSE control operations. This includes cache operations and
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table entry statistics read/clear operation.
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<enum 0 rd_stat> Report or Read statistics
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<enum 1 srch_dis> Search disable. Report only Hash
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<enum 2 Wr_bk_single> Write Back single entry
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<enum 3 wr_bk_all> Write Back entire cache entry
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<enum 4 inval_single> Invalidate single cache entry
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<enum 5 inval_all> Invalidate entire cache
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<enum 6 wr_bk_inval_single> Write back and Invalidate single
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entry in cache
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<enum 7 wr_bk_inval_all> write back and invalidate entire
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cache
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<enum 8 clr_stat_single> Clear statistics for single entry
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<legal 0-8>
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Rest of the values reserved.
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For all single entry control operations (write back, Invalidate
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or both)Statistics will be reported
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*/
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#define TCL_STATUS_RING_GSE_CTRL_OFFSET 0x00000000
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#define TCL_STATUS_RING_GSE_CTRL_LSB 0
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#define TCL_STATUS_RING_GSE_CTRL_MSB 3
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#define TCL_STATUS_RING_GSE_CTRL_MASK 0x0000000f
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/* Description ASE_FSE_SEL
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Search Engine for which operation is done.
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1'b0: Address Search Engine Result
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1'b1: Flow Search Engine result
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*/
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#define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET 0x00000000
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#define TCL_STATUS_RING_ASE_FSE_SEL_LSB 4
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#define TCL_STATUS_RING_ASE_FSE_SEL_MSB 4
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#define TCL_STATUS_RING_ASE_FSE_SEL_MASK 0x00000010
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/* Description CACHE_OP_RES
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Cache operation result. Following are results of cache operation.
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<enum 0 op_done> Operation successful
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<enum 1 not_fnd> Entry not found in Table
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<enum 2 timeout_er> Timeout Error
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<legal 0-2>
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*/
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#define TCL_STATUS_RING_CACHE_OP_RES_OFFSET 0x00000000
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#define TCL_STATUS_RING_CACHE_OP_RES_LSB 5
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#define TCL_STATUS_RING_CACHE_OP_RES_MSB 6
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#define TCL_STATUS_RING_CACHE_OP_RES_MASK 0x00000060
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/* Description INDEX_SEARCH_EN
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When this bit is set to 1 control_buffer_addr[19:0] will
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be considered as index of the AST or Flow table and GSE
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commands will be executed accordingly on the entry pointed
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by the index.
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This feature is disabled by setting this bit to 0.
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<enum 0 index_based_cmd_disable>
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<enum 1 index_based_cmd_enable>
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<legal all>
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*/
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#define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET 0x00000000
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#define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB 7
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#define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB 7
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#define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK 0x00000080
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/* Description MSDU_CNT_N
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MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and
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4'b1000
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*/
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#define TCL_STATUS_RING_MSDU_CNT_N_OFFSET 0x00000000
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#define TCL_STATUS_RING_MSDU_CNT_N_LSB 8
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#define TCL_STATUS_RING_MSDU_CNT_N_MSB 31
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#define TCL_STATUS_RING_MSDU_CNT_N_MASK 0xffffff00
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/* Description MSDU_BYTE_CNT_N
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MSDU byte count for entry 1. Valid when GSE_CTRL is 4'b0111
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and 4'b1000
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*/
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#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET 0x00000004
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#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB 0
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#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB 31
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#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK 0xffffffff
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/* Description MSDU_TIMESTMP_N
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MSDU timestamp for entry 1. Valid when GSE_CTRL is 4'b0111
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and 4'b1000
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*/
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#define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET 0x00000008
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#define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB 0
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#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB 31
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#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK 0xffffffff
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/* Description CMD_META_DATA_31_0
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Meta data from input ring
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<legal all>
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*/
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#define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET 0x0000000c
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#define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB 0
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#define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB 31
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#define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK 0xffffffff
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/* Description CMD_META_DATA_63_32
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Meta data from input ring
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<legal all>
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*/
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#define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET 0x00000010
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#define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB 0
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#define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB 31
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#define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK 0xffffffff
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/* Description HASH_INDX_VAL
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Index of entry in the table in case of search pass (or)
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Hash value of the entry in table in case of search failed
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or search disable.
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<legal all>
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*/
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#define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET 0x00000014
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#define TCL_STATUS_RING_HASH_INDX_VAL_LSB 0
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#define TCL_STATUS_RING_HASH_INDX_VAL_MSB 19
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#define TCL_STATUS_RING_HASH_INDX_VAL_MASK 0x000fffff
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/* Description CACHE_SET_NUM
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Cache set number copied from TCL_GSE_CMD
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*/
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#define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET 0x00000014
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#define TCL_STATUS_RING_CACHE_SET_NUM_LSB 20
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#define TCL_STATUS_RING_CACHE_SET_NUM_MSB 23
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#define TCL_STATUS_RING_CACHE_SET_NUM_MASK 0x00f00000
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/* Description RESERVED_5A
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<legal 0>
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*/
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#define TCL_STATUS_RING_RESERVED_5A_OFFSET 0x00000014
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#define TCL_STATUS_RING_RESERVED_5A_LSB 24
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#define TCL_STATUS_RING_RESERVED_5A_MSB 31
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#define TCL_STATUS_RING_RESERVED_5A_MASK 0xff000000
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/* Description RESERVED_6A
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<legal 0>
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*/
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#define TCL_STATUS_RING_RESERVED_6A_OFFSET 0x00000018
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#define TCL_STATUS_RING_RESERVED_6A_LSB 0
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#define TCL_STATUS_RING_RESERVED_6A_MSB 31
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#define TCL_STATUS_RING_RESERVED_6A_MASK 0xffffffff
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/* Description RESERVED_7A
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<legal 0>
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*/
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#define TCL_STATUS_RING_RESERVED_7A_OFFSET 0x0000001c
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#define TCL_STATUS_RING_RESERVED_7A_LSB 0
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#define TCL_STATUS_RING_RESERVED_7A_MSB 19
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#define TCL_STATUS_RING_RESERVED_7A_MASK 0x000fffff
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/* Description RING_ID
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The buffer pointer ring ID.
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Helps with debugging when dumping ring contents.
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<legal all>
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*/
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#define TCL_STATUS_RING_RING_ID_OFFSET 0x0000001c
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#define TCL_STATUS_RING_RING_ID_LSB 20
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#define TCL_STATUS_RING_RING_ID_MSB 27
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#define TCL_STATUS_RING_RING_ID_MASK 0x0ff00000
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/* Description LOOPING_COUNT
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A count value that indicates the number of times the producer
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of entries into the Ring has looped around the ring.
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At initialization time, this value is set to 0. On the first
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loop, this value is set to 1. After the max value is reached
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allowed by the number of bits for this field, the count
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value continues with 0 again.
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In case SW is the consumer of the ring entries, it can use
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this field to figure out up to where the producer of entries
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has created new entries. This eliminates the need to check
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where the "head pointer' of the ring is located once the
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SW starts processing an interrupt indicating that new entries
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have been put into this ring...
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Also note that SW if it wants only needs to look at the
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LSB bit of this count value.
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<legal all>
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*/
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#define TCL_STATUS_RING_LOOPING_COUNT_OFFSET 0x0000001c
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#define TCL_STATUS_RING_LOOPING_COUNT_LSB 28
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#define TCL_STATUS_RING_LOOPING_COUNT_MSB 31
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#define TCL_STATUS_RING_LOOPING_COUNT_MASK 0xf0000000
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#endif // TCL_STATUS_RING
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