36637cf177
Added ipq5332 target header files under qca5332 to make fw-api project compatible to host. Change-Id: Iee6b3f2a809f31e62b45a0f6e9a7cbb66e070fa0
346 行
15 KiB
C
346 行
15 KiB
C
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/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _TCL_GSE_CMD_H_
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#define _TCL_GSE_CMD_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#define NUM_OF_DWORDS_TCL_GSE_CMD 8
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struct tcl_gse_cmd {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t control_buffer_addr_31_0 : 32; // [31:0]
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uint32_t control_buffer_addr_39_32 : 8, // [7:0]
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gse_ctrl : 4, // [11:8]
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gse_sel : 1, // [12:12]
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status_destination_ring_id : 1, // [13:13]
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swap : 1, // [14:14]
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index_search_en : 1, // [15:15]
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cache_set_num : 4, // [19:16]
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reserved_1a : 12; // [31:20]
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uint32_t tcl_cmd_type : 1, // [0:0]
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reserved_2a : 31; // [31:1]
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uint32_t cmd_meta_data_31_0 : 32; // [31:0]
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uint32_t cmd_meta_data_63_32 : 32; // [31:0]
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uint32_t reserved_5a : 32; // [31:0]
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uint32_t reserved_6a : 32; // [31:0]
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uint32_t reserved_7a : 20, // [19:0]
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ring_id : 8, // [27:20]
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looping_count : 4; // [31:28]
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#else
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uint32_t control_buffer_addr_31_0 : 32; // [31:0]
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uint32_t reserved_1a : 12, // [31:20]
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cache_set_num : 4, // [19:16]
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index_search_en : 1, // [15:15]
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swap : 1, // [14:14]
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status_destination_ring_id : 1, // [13:13]
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gse_sel : 1, // [12:12]
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gse_ctrl : 4, // [11:8]
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control_buffer_addr_39_32 : 8; // [7:0]
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uint32_t reserved_2a : 31, // [31:1]
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tcl_cmd_type : 1; // [0:0]
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uint32_t cmd_meta_data_31_0 : 32; // [31:0]
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uint32_t cmd_meta_data_63_32 : 32; // [31:0]
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uint32_t reserved_5a : 32; // [31:0]
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uint32_t reserved_6a : 32; // [31:0]
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uint32_t looping_count : 4, // [31:28]
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ring_id : 8, // [27:20]
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reserved_7a : 20; // [19:0]
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#endif
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};
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/* Description CONTROL_BUFFER_ADDR_31_0
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Address (lower 32 bits) of a control buffer containing additional
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info needed for this command execution.
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<legal all>
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*/
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#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000
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#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB 0
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#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB 31
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#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff
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/* Description CONTROL_BUFFER_ADDR_39_32
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Address (upper 8 bits) of a control buffer containing additional
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info needed for this command execution.
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<legal all>
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*/
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#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004
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#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB 0
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#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB 7
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#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff
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/* Description GSE_CTRL
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GSE control operations. This includes cache operations and
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table entry statistics read/clear operation.
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<enum 0 rd_stat> Report or Read statistics
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<enum 1 srch_dis> Search disable. Report only Hash
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<enum 2 Wr_bk_single> Write Back single entry
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<enum 3 wr_bk_all> Write Back entire cache entry
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<enum 4 inval_single> Invalidate single cache entry
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<enum 5 inval_all> Invalidate entire cache
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<enum 6 wr_bk_inval_single> Write back and Invalidate single
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entry in cache
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<enum 7 wr_bk_inval_all> write back and invalidate entire
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cache
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<enum 8 clr_stat_single> Clear statistics for single entry
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<legal 0-8>
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Rest of the values reserved.
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For all single entry control operations (write back, Invalidate
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or both)Statistics will be reported
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*/
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#define TCL_GSE_CMD_GSE_CTRL_OFFSET 0x00000004
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#define TCL_GSE_CMD_GSE_CTRL_LSB 8
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#define TCL_GSE_CMD_GSE_CTRL_MSB 11
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#define TCL_GSE_CMD_GSE_CTRL_MASK 0x00000f00
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/* Description GSE_SEL
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Bit to select the ASE or FSE to do the operation mention
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by GSE_ctrl bit
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0: FSE select
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1: ASE select
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*/
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#define TCL_GSE_CMD_GSE_SEL_OFFSET 0x00000004
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#define TCL_GSE_CMD_GSE_SEL_LSB 12
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#define TCL_GSE_CMD_GSE_SEL_MSB 12
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#define TCL_GSE_CMD_GSE_SEL_MASK 0x00001000
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/* Description STATUS_DESTINATION_RING_ID
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The TCL status ring to which the GSE status needs to be
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send.
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<enum 0 tcl_status_0_ring>
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<enum 1 tcl_status_1_ring>
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<legal all>
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*/
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#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004
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#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB 13
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#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB 13
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#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK 0x00002000
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/* Description SWAP
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Bit to enable byte swapping of contents of buffer
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<enum 0 Byte_swap_disable >
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<enum 1 byte_swap_enable >
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<legal all>
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*/
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#define TCL_GSE_CMD_SWAP_OFFSET 0x00000004
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#define TCL_GSE_CMD_SWAP_LSB 14
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#define TCL_GSE_CMD_SWAP_MSB 14
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#define TCL_GSE_CMD_SWAP_MASK 0x00004000
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/* Description INDEX_SEARCH_EN
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When this bit is set to 1 control_buffer_addr[19:0] will
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be considered as index of the AST or Flow table and GSE
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commands will be executed accordingly on the entry pointed
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by the index.
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This feature is disabled by setting this bit to 0.
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<enum 0 index_based_cmd_disable>
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<enum 1 index_based_cmd_enable>
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<legal all>
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*/
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#define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET 0x00000004
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#define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB 15
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#define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB 15
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#define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK 0x00008000
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/* Description CACHE_SET_NUM
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Cache set number that should be used to cache the index
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based search results, for address and flow search. This
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value should be equal to value of cache_set_num for the
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index that is issued in TCL_DATA_CMD during search index
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based ASE or FSE. This field is valid for index based GSE
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commands
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<legal all>
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*/
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#define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET 0x00000004
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#define TCL_GSE_CMD_CACHE_SET_NUM_LSB 16
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#define TCL_GSE_CMD_CACHE_SET_NUM_MSB 19
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#define TCL_GSE_CMD_CACHE_SET_NUM_MASK 0x000f0000
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/* Description RESERVED_1A
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<legal 0>
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*/
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#define TCL_GSE_CMD_RESERVED_1A_OFFSET 0x00000004
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#define TCL_GSE_CMD_RESERVED_1A_LSB 20
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#define TCL_GSE_CMD_RESERVED_1A_MSB 31
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#define TCL_GSE_CMD_RESERVED_1A_MASK 0xfff00000
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/* Description TCL_CMD_TYPE
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This field is used to select the type of TCL Command decriptor
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that is queued by SW/FW. For 'TCL_GSE_CMD' this has to
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be 1.
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<legal 1>
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*/
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#define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET 0x00000008
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#define TCL_GSE_CMD_TCL_CMD_TYPE_LSB 0
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#define TCL_GSE_CMD_TCL_CMD_TYPE_MSB 0
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#define TCL_GSE_CMD_TCL_CMD_TYPE_MASK 0x00000001
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/* Description RESERVED_2A
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<legal 0>
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*/
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#define TCL_GSE_CMD_RESERVED_2A_OFFSET 0x00000008
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#define TCL_GSE_CMD_RESERVED_2A_LSB 1
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#define TCL_GSE_CMD_RESERVED_2A_MSB 31
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#define TCL_GSE_CMD_RESERVED_2A_MASK 0xfffffffe
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/* Description CMD_META_DATA_31_0
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Meta data to be returned in the status descriptor
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<legal all>
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*/
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#define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET 0x0000000c
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#define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB 0
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#define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB 31
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#define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK 0xffffffff
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/* Description CMD_META_DATA_63_32
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Meta data to be returned in the status descriptor
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<legal all>
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*/
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#define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET 0x00000010
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#define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB 0
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#define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB 31
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#define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK 0xffffffff
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/* Description RESERVED_5A
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<legal 0>
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*/
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#define TCL_GSE_CMD_RESERVED_5A_OFFSET 0x00000014
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#define TCL_GSE_CMD_RESERVED_5A_LSB 0
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#define TCL_GSE_CMD_RESERVED_5A_MSB 31
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#define TCL_GSE_CMD_RESERVED_5A_MASK 0xffffffff
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/* Description RESERVED_6A
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<legal 0>
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*/
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#define TCL_GSE_CMD_RESERVED_6A_OFFSET 0x00000018
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#define TCL_GSE_CMD_RESERVED_6A_LSB 0
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#define TCL_GSE_CMD_RESERVED_6A_MSB 31
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#define TCL_GSE_CMD_RESERVED_6A_MASK 0xffffffff
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/* Description RESERVED_7A
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<legal 0>
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*/
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#define TCL_GSE_CMD_RESERVED_7A_OFFSET 0x0000001c
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#define TCL_GSE_CMD_RESERVED_7A_LSB 0
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#define TCL_GSE_CMD_RESERVED_7A_MSB 19
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#define TCL_GSE_CMD_RESERVED_7A_MASK 0x000fffff
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/* Description RING_ID
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Helps with debugging when dumping ring contents.
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<legal all>
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*/
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#define TCL_GSE_CMD_RING_ID_OFFSET 0x0000001c
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#define TCL_GSE_CMD_RING_ID_LSB 20
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#define TCL_GSE_CMD_RING_ID_MSB 27
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#define TCL_GSE_CMD_RING_ID_MASK 0x0ff00000
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/* Description LOOPING_COUNT
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A count value that indicates the number of times the producer
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of entries into the Ring has looped around the ring.
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At initialization time, this value is set to 0. On the first
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loop, this value is set to 1. After the max value is reached
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allowed by the number of bits for this field, the count
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value continues with 0 again.
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In case SW is the consumer of the ring entries, it can use
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this field to figure out up to where the producer of entries
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has created new entries. This eliminates the need to check
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where the "head pointer' of the ring is located once the
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SW starts processing an interrupt indicating that new entries
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have been put into this ring...
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Also note that SW if it wants only needs to look at the
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LSB bit of this count value.
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<legal all>
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*/
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#define TCL_GSE_CMD_LOOPING_COUNT_OFFSET 0x0000001c
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#define TCL_GSE_CMD_LOOPING_COUNT_LSB 28
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#define TCL_GSE_CMD_LOOPING_COUNT_MSB 31
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#define TCL_GSE_CMD_LOOPING_COUNT_MASK 0xf0000000
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#endif // TCL_GSE_CMD
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