36637cf177
Added ipq5332 target header files under qca5332 to make fw-api project compatible to host. Change-Id: Iee6b3f2a809f31e62b45a0f6e9a7cbb66e070fa0
556 行
23 KiB
C
556 行
23 KiB
C
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/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _RX_REO_QUEUE_1K_H_
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#define _RX_REO_QUEUE_1K_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#include "uniform_descriptor_header.h"
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#define NUM_OF_DWORDS_RX_REO_QUEUE_1K 32
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struct rx_reo_queue_1k {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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struct uniform_descriptor_header descriptor_header;
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uint32_t rx_bitmap_319_288 : 32; // [31:0]
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uint32_t rx_bitmap_351_320 : 32; // [31:0]
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uint32_t rx_bitmap_383_352 : 32; // [31:0]
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uint32_t rx_bitmap_415_384 : 32; // [31:0]
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uint32_t rx_bitmap_447_416 : 32; // [31:0]
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uint32_t rx_bitmap_479_448 : 32; // [31:0]
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uint32_t rx_bitmap_511_480 : 32; // [31:0]
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uint32_t rx_bitmap_543_512 : 32; // [31:0]
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uint32_t rx_bitmap_575_544 : 32; // [31:0]
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uint32_t rx_bitmap_607_576 : 32; // [31:0]
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uint32_t rx_bitmap_639_608 : 32; // [31:0]
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uint32_t rx_bitmap_671_640 : 32; // [31:0]
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uint32_t rx_bitmap_703_672 : 32; // [31:0]
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uint32_t rx_bitmap_735_704 : 32; // [31:0]
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uint32_t rx_bitmap_767_736 : 32; // [31:0]
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uint32_t rx_bitmap_799_768 : 32; // [31:0]
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uint32_t rx_bitmap_831_800 : 32; // [31:0]
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uint32_t rx_bitmap_863_832 : 32; // [31:0]
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uint32_t rx_bitmap_895_864 : 32; // [31:0]
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uint32_t rx_bitmap_927_896 : 32; // [31:0]
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uint32_t rx_bitmap_959_928 : 32; // [31:0]
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uint32_t rx_bitmap_991_960 : 32; // [31:0]
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uint32_t rx_bitmap_1023_992 : 32; // [31:0]
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uint32_t reserved_24 : 32; // [31:0]
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uint32_t reserved_25 : 32; // [31:0]
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uint32_t reserved_26 : 32; // [31:0]
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uint32_t reserved_27 : 32; // [31:0]
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uint32_t reserved_28 : 32; // [31:0]
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uint32_t reserved_29 : 32; // [31:0]
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uint32_t reserved_30 : 32; // [31:0]
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uint32_t reserved_31 : 32; // [31:0]
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#else
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struct uniform_descriptor_header descriptor_header;
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uint32_t rx_bitmap_319_288 : 32; // [31:0]
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uint32_t rx_bitmap_351_320 : 32; // [31:0]
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uint32_t rx_bitmap_383_352 : 32; // [31:0]
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uint32_t rx_bitmap_415_384 : 32; // [31:0]
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uint32_t rx_bitmap_447_416 : 32; // [31:0]
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uint32_t rx_bitmap_479_448 : 32; // [31:0]
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uint32_t rx_bitmap_511_480 : 32; // [31:0]
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uint32_t rx_bitmap_543_512 : 32; // [31:0]
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uint32_t rx_bitmap_575_544 : 32; // [31:0]
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uint32_t rx_bitmap_607_576 : 32; // [31:0]
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uint32_t rx_bitmap_639_608 : 32; // [31:0]
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uint32_t rx_bitmap_671_640 : 32; // [31:0]
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uint32_t rx_bitmap_703_672 : 32; // [31:0]
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uint32_t rx_bitmap_735_704 : 32; // [31:0]
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uint32_t rx_bitmap_767_736 : 32; // [31:0]
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uint32_t rx_bitmap_799_768 : 32; // [31:0]
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uint32_t rx_bitmap_831_800 : 32; // [31:0]
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uint32_t rx_bitmap_863_832 : 32; // [31:0]
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uint32_t rx_bitmap_895_864 : 32; // [31:0]
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uint32_t rx_bitmap_927_896 : 32; // [31:0]
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uint32_t rx_bitmap_959_928 : 32; // [31:0]
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uint32_t rx_bitmap_991_960 : 32; // [31:0]
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uint32_t rx_bitmap_1023_992 : 32; // [31:0]
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uint32_t reserved_24 : 32; // [31:0]
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uint32_t reserved_25 : 32; // [31:0]
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uint32_t reserved_26 : 32; // [31:0]
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uint32_t reserved_27 : 32; // [31:0]
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uint32_t reserved_28 : 32; // [31:0]
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uint32_t reserved_29 : 32; // [31:0]
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uint32_t reserved_30 : 32; // [31:0]
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uint32_t reserved_31 : 32; // [31:0]
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#endif
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};
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/* Description DESCRIPTOR_HEADER
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Details about which module owns this struct.
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Note that sub field "Buffer_type" shall be set to "Receive_REO_queue_1k_descriptor"
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*/
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/* Description OWNER
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Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
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Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
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The owner of this data structure:
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<enum 0 WBM_owned> Buffer Manager currently owns this data
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structure.
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<enum 1 SW_OR_FW_owned> Software of FW currently owns this
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data structure.
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<enum 2 TQM_owned> Transmit Queue Manager currently owns
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this data structure.
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<enum 3 RXDMA_owned> Receive DMA currently owns this data
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structure.
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<enum 4 REO_owned> Reorder currently owns this data structure.
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<enum 5 SWITCH_owned> SWITCH currently owns this data structure.
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<legal 0-5>
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*/
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#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000
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#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_LSB 0
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#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MSB 3
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#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f
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/* Description BUFFER_TYPE
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Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
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Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
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Field describing what contents format is of this descriptor
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<enum 0 Transmit_MSDU_Link_descriptor>
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<enum 1 Transmit_MPDU_Link_descriptor>
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<enum 2 Transmit_MPDU_Queue_head_descriptor>
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<enum 3 Transmit_MPDU_Queue_ext_descriptor>
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<enum 4 Transmit_flow_descriptor>
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<enum 5 Transmit_buffer> NOT TO BE USED:
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<enum 6 Receive_MSDU_Link_descriptor>
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<enum 7 Receive_MPDU_Link_descriptor>
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<enum 8 Receive_REO_queue_descriptor>
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<enum 9 Receive_REO_queue_1k_descriptor>
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<enum 10 Receive_REO_queue_ext_descriptor>
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<enum 11 Receive_buffer>
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<enum 12 Idle_link_list_entry>
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<legal 0-12>
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*/
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#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000
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#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4
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#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7
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#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
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/* Description RESERVED_0A
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<legal 0>
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*/
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#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
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#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8
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#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31
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#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00
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/* Description RX_BITMAP_319_288
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When a bit is set, the corresponding frame is currently
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held in the re-order queue.
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The bitmap is Fully managed by HW.
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SW shall init this to 0, and then never ever change it
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<legal all>
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*/
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#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_OFFSET 0x00000004
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#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_LSB 0
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#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MSB 31
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#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MASK 0xffffffff
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/* Description RX_BITMAP_351_320
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See Rx_bitmap_319_288 description
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<legal all>
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*/
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#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_OFFSET 0x00000008
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#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_LSB 0
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#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MSB 31
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#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MASK 0xffffffff
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/* Description RX_BITMAP_383_352
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See Rx_bitmap_319_288 description
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<legal all>
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*/
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#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_OFFSET 0x0000000c
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#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_LSB 0
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#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MSB 31
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#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MASK 0xffffffff
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/* Description RX_BITMAP_415_384
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See Rx_bitmap_319_288 description
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<legal all>
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*/
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#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_OFFSET 0x00000010
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#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_LSB 0
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#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MSB 31
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#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MASK 0xffffffff
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/* Description RX_BITMAP_447_416
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See Rx_bitmap_319_288 description
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<legal all>
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*/
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#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_OFFSET 0x00000014
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#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_LSB 0
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#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MSB 31
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#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MASK 0xffffffff
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/* Description RX_BITMAP_479_448
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See Rx_bitmap_319_288 description
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<legal all>
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*/
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#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_OFFSET 0x00000018
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#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_LSB 0
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#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MSB 31
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#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MASK 0xffffffff
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/* Description RX_BITMAP_511_480
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See Rx_bitmap_319_288 description
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<legal all>
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*/
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#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_OFFSET 0x0000001c
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#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_LSB 0
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#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MSB 31
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#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MASK 0xffffffff
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/* Description RX_BITMAP_543_512
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See Rx_bitmap_319_288 description
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<legal all>
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*/
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#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_OFFSET 0x00000020
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#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_LSB 0
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#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MSB 31
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#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MASK 0xffffffff
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/* Description RX_BITMAP_575_544
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See Rx_bitmap_319_288 description
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<legal all>
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*/
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#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_OFFSET 0x00000024
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#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_LSB 0
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#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MSB 31
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#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MASK 0xffffffff
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/* Description RX_BITMAP_607_576
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See Rx_bitmap_319_288 description
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<legal all>
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*/
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#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_OFFSET 0x00000028
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#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_LSB 0
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#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MSB 31
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#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MASK 0xffffffff
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/* Description RX_BITMAP_639_608
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See Rx_bitmap_319_288 description
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<legal all>
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*/
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#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_OFFSET 0x0000002c
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#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_LSB 0
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#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MSB 31
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#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MASK 0xffffffff
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/* Description RX_BITMAP_671_640
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See Rx_bitmap_319_288 description
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<legal all>
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*/
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#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_OFFSET 0x00000030
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#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_LSB 0
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#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MSB 31
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#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MASK 0xffffffff
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/* Description RX_BITMAP_703_672
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See Rx_bitmap_319_288 description
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<legal all>
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*/
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#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_OFFSET 0x00000034
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#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_LSB 0
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#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MSB 31
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#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MASK 0xffffffff
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/* Description RX_BITMAP_735_704
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See Rx_bitmap_319_288 description
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<legal all>
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*/
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#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_OFFSET 0x00000038
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#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_LSB 0
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#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MSB 31
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#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MASK 0xffffffff
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/* Description RX_BITMAP_767_736
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See Rx_bitmap_319_288 description
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<legal all>
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*/
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#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_OFFSET 0x0000003c
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#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_LSB 0
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#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MSB 31
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#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MASK 0xffffffff
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/* Description RX_BITMAP_799_768
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See Rx_bitmap_319_288 description
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<legal all>
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*/
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#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_OFFSET 0x00000040
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#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_LSB 0
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#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MSB 31
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#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MASK 0xffffffff
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/* Description RX_BITMAP_831_800
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See Rx_bitmap_319_288 description
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<legal all>
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*/
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#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_OFFSET 0x00000044
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#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_LSB 0
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#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MSB 31
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#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MASK 0xffffffff
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/* Description RX_BITMAP_863_832
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See Rx_bitmap_319_288 description
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<legal all>
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*/
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#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_OFFSET 0x00000048
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#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_LSB 0
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#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MSB 31
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#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MASK 0xffffffff
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/* Description RX_BITMAP_895_864
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See Rx_bitmap_319_288 description
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<legal all>
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*/
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#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_OFFSET 0x0000004c
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#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_LSB 0
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#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MSB 31
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#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MASK 0xffffffff
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/* Description RX_BITMAP_927_896
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See Rx_bitmap_319_288 description
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<legal all>
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*/
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#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_OFFSET 0x00000050
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#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_LSB 0
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#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MSB 31
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#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MASK 0xffffffff
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/* Description RX_BITMAP_959_928
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See Rx_bitmap_319_288 description
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<legal all>
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*/
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#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_OFFSET 0x00000054
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#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_LSB 0
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#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MSB 31
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#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MASK 0xffffffff
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/* Description RX_BITMAP_991_960
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See Rx_bitmap_319_288 description
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<legal all>
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*/
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#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_OFFSET 0x00000058
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#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_LSB 0
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#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MSB 31
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#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MASK 0xffffffff
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/* Description RX_BITMAP_1023_992
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See Rx_bitmap_319_288 description
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<legal all>
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*/
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#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_OFFSET 0x0000005c
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#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_LSB 0
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#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MSB 31
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#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MASK 0xffffffff
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/* Description RESERVED_24
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<legal 0>
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*/
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#define RX_REO_QUEUE_1K_RESERVED_24_OFFSET 0x00000060
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#define RX_REO_QUEUE_1K_RESERVED_24_LSB 0
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#define RX_REO_QUEUE_1K_RESERVED_24_MSB 31
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#define RX_REO_QUEUE_1K_RESERVED_24_MASK 0xffffffff
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/* Description RESERVED_25
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<legal 0>
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*/
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#define RX_REO_QUEUE_1K_RESERVED_25_OFFSET 0x00000064
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#define RX_REO_QUEUE_1K_RESERVED_25_LSB 0
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#define RX_REO_QUEUE_1K_RESERVED_25_MSB 31
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#define RX_REO_QUEUE_1K_RESERVED_25_MASK 0xffffffff
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/* Description RESERVED_26
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<legal 0>
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*/
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#define RX_REO_QUEUE_1K_RESERVED_26_OFFSET 0x00000068
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#define RX_REO_QUEUE_1K_RESERVED_26_LSB 0
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#define RX_REO_QUEUE_1K_RESERVED_26_MSB 31
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#define RX_REO_QUEUE_1K_RESERVED_26_MASK 0xffffffff
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/* Description RESERVED_27
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<legal 0>
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*/
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#define RX_REO_QUEUE_1K_RESERVED_27_OFFSET 0x0000006c
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#define RX_REO_QUEUE_1K_RESERVED_27_LSB 0
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#define RX_REO_QUEUE_1K_RESERVED_27_MSB 31
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#define RX_REO_QUEUE_1K_RESERVED_27_MASK 0xffffffff
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/* Description RESERVED_28
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<legal 0>
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*/
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#define RX_REO_QUEUE_1K_RESERVED_28_OFFSET 0x00000070
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#define RX_REO_QUEUE_1K_RESERVED_28_LSB 0
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#define RX_REO_QUEUE_1K_RESERVED_28_MSB 31
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#define RX_REO_QUEUE_1K_RESERVED_28_MASK 0xffffffff
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/* Description RESERVED_29
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<legal 0>
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*/
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#define RX_REO_QUEUE_1K_RESERVED_29_OFFSET 0x00000074
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#define RX_REO_QUEUE_1K_RESERVED_29_LSB 0
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#define RX_REO_QUEUE_1K_RESERVED_29_MSB 31
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#define RX_REO_QUEUE_1K_RESERVED_29_MASK 0xffffffff
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/* Description RESERVED_30
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<legal 0>
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*/
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#define RX_REO_QUEUE_1K_RESERVED_30_OFFSET 0x00000078
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#define RX_REO_QUEUE_1K_RESERVED_30_LSB 0
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#define RX_REO_QUEUE_1K_RESERVED_30_MSB 31
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#define RX_REO_QUEUE_1K_RESERVED_30_MASK 0xffffffff
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/* Description RESERVED_31
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<legal 0>
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*/
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#define RX_REO_QUEUE_1K_RESERVED_31_OFFSET 0x0000007c
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#define RX_REO_QUEUE_1K_RESERVED_31_LSB 0
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#define RX_REO_QUEUE_1K_RESERVED_31_MSB 31
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#define RX_REO_QUEUE_1K_RESERVED_31_MASK 0xffffffff
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#endif // RX_REO_QUEUE_1K
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