36637cf177
Added ipq5332 target header files under qca5332 to make fw-api project compatible to host. Change-Id: Iee6b3f2a809f31e62b45a0f6e9a7cbb66e070fa0
542 regels
23 KiB
C
542 regels
23 KiB
C
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/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _RX_MPDU_END_H_
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#define _RX_MPDU_END_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#define NUM_OF_DWORDS_RX_MPDU_END 4
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#define NUM_OF_QWORDS_RX_MPDU_END 2
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struct rx_mpdu_end {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0]
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sw_frame_group_id : 7, // [8:2]
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reserved_0 : 7, // [15:9]
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phy_ppdu_id : 16; // [31:16]
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uint32_t reserved_1a : 11, // [10:0]
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unsup_ktype_short_frame : 1, // [11:11]
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rx_in_tx_decrypt_byp : 1, // [12:12]
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overflow_err : 1, // [13:13]
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mpdu_length_err : 1, // [14:14]
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tkip_mic_err : 1, // [15:15]
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decrypt_err : 1, // [16:16]
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unencrypted_frame_err : 1, // [17:17]
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pn_fields_contain_valid_info : 1, // [18:18]
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fcs_err : 1, // [19:19]
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msdu_length_err : 1, // [20:20]
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rxdma0_destination_ring : 3, // [23:21]
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rxdma1_destination_ring : 3, // [26:24]
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decrypt_status_code : 3, // [29:27]
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rx_bitmap_not_updated : 1, // [30:30]
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reserved_1b : 1; // [31:31]
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uint32_t reserved_2a : 15, // [14:0]
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rxpcu_mgmt_sequence_nr_valid : 1, // [15:15]
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rxpcu_mgmt_sequence_nr : 16; // [31:16]
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uint32_t rxframe_assert_mlo_timestamp : 32; // [31:0]
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#else
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uint32_t phy_ppdu_id : 16, // [31:16]
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reserved_0 : 7, // [15:9]
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sw_frame_group_id : 7, // [8:2]
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rxpcu_mpdu_filter_in_category : 2; // [1:0]
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uint32_t reserved_1b : 1, // [31:31]
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rx_bitmap_not_updated : 1, // [30:30]
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decrypt_status_code : 3, // [29:27]
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rxdma1_destination_ring : 3, // [26:24]
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rxdma0_destination_ring : 3, // [23:21]
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msdu_length_err : 1, // [20:20]
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fcs_err : 1, // [19:19]
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pn_fields_contain_valid_info : 1, // [18:18]
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unencrypted_frame_err : 1, // [17:17]
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decrypt_err : 1, // [16:16]
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tkip_mic_err : 1, // [15:15]
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mpdu_length_err : 1, // [14:14]
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overflow_err : 1, // [13:13]
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rx_in_tx_decrypt_byp : 1, // [12:12]
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unsup_ktype_short_frame : 1, // [11:11]
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reserved_1a : 11; // [10:0]
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uint32_t rxpcu_mgmt_sequence_nr : 16, // [31:16]
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rxpcu_mgmt_sequence_nr_valid : 1, // [15:15]
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reserved_2a : 15; // [14:0]
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uint32_t rxframe_assert_mlo_timestamp : 32; // [31:0]
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#endif
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};
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/* Description RXPCU_MPDU_FILTER_IN_CATEGORY
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Field indicates what the reason was that this MPDU frame
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was allowed to come into the receive path by RXPCU
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<enum 0 rxpcu_filter_pass> This MPDU passed the normal frame
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filter programming of rxpcu
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<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
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regular frame filter and would have been dropped, were
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it not for the frame fitting into the 'monitor_client' category.
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<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
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regular frame filter and also did not pass the rxpcu_monitor_client
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filter. It would have been dropped accept that it did pass
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the 'monitor_other' category.
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<enum 3 rxpcu_filter_pass_monitor_ovrd> This MPDU passed
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the normal frame filter programming of RXPCU but additionally
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fit into the 'monitor_override_client' category.
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<legal 0-3>
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*/
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#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000
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#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
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#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1
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#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003
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/* Description SW_FRAME_GROUP_ID
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SW processes frames based on certain classifications. This
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field indicates to what sw classification this MPDU is
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mapped.
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The classification is given in priority order
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<enum 0 sw_frame_group_NDP_frame>
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<enum 1 sw_frame_group_Multicast_data>
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<enum 2 sw_frame_group_Unicast_data>
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<enum 3 sw_frame_group_Null_data > This includes mpdus of
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type Data Null.
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Hamilton v1 included QoS Data Null as well here.
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<enum 38 sw_frame_group_QoS_Null_data> This includes QoS
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Null frames except in UL MU or TB PPDUs.
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<enum 39 sw_frame_group_QoS_Null_data_TB> This includes
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QoS Null frames in UL MU or TB PPDUs.
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<enum 4 sw_frame_group_mgmt_0000 >
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<enum 5 sw_frame_group_mgmt_0001 >
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<enum 6 sw_frame_group_mgmt_0010 >
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<enum 7 sw_frame_group_mgmt_0011 >
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<enum 8 sw_frame_group_mgmt_0100 >
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<enum 9 sw_frame_group_mgmt_0101 >
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<enum 10 sw_frame_group_mgmt_0110 >
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<enum 11 sw_frame_group_mgmt_0111 >
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<enum 12 sw_frame_group_mgmt_1000 >
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<enum 13 sw_frame_group_mgmt_1001 >
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<enum 14 sw_frame_group_mgmt_1010 >
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<enum 15 sw_frame_group_mgmt_1011 >
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<enum 16 sw_frame_group_mgmt_1100 >
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<enum 17 sw_frame_group_mgmt_1101 >
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<enum 18 sw_frame_group_mgmt_1110 >
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<enum 19 sw_frame_group_mgmt_1111 >
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<enum 20 sw_frame_group_ctrl_0000 >
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<enum 21 sw_frame_group_ctrl_0001 >
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<enum 22 sw_frame_group_ctrl_0010 >
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<enum 23 sw_frame_group_ctrl_0011 >
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<enum 24 sw_frame_group_ctrl_0100 >
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<enum 25 sw_frame_group_ctrl_0101 >
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<enum 26 sw_frame_group_ctrl_0110 >
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<enum 27 sw_frame_group_ctrl_0111 >
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<enum 28 sw_frame_group_ctrl_1000 >
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<enum 29 sw_frame_group_ctrl_1001 >
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<enum 30 sw_frame_group_ctrl_1010 >
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<enum 31 sw_frame_group_ctrl_1011 >
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<enum 32 sw_frame_group_ctrl_1100 >
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<enum 33 sw_frame_group_ctrl_1101 >
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<enum 34 sw_frame_group_ctrl_1110 >
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<enum 35 sw_frame_group_ctrl_1111 >
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<enum 36 sw_frame_group_unsupported> This covers type 3
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and protocol version != 0
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<enum 37 sw_frame_group_phy_error> PHY reported an error
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<legal 0-39>
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*/
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#define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000
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#define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2
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#define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8
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#define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc
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/* Description RESERVED_0
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<legal 0>
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*/
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#define RX_MPDU_END_RESERVED_0_OFFSET 0x0000000000000000
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#define RX_MPDU_END_RESERVED_0_LSB 9
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#define RX_MPDU_END_RESERVED_0_MSB 15
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#define RX_MPDU_END_RESERVED_0_MASK 0x000000000000fe00
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/* Description PHY_PPDU_ID
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A ppdu counter value that PHY increments for every PPDU
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received. The counter value wraps around
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<legal all>
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*/
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#define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000
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#define RX_MPDU_END_PHY_PPDU_ID_LSB 16
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#define RX_MPDU_END_PHY_PPDU_ID_MSB 31
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#define RX_MPDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000
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/* Description RESERVED_1A
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<legal 0>
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*/
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#define RX_MPDU_END_RESERVED_1A_OFFSET 0x0000000000000000
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#define RX_MPDU_END_RESERVED_1A_LSB 32
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#define RX_MPDU_END_RESERVED_1A_MSB 42
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#define RX_MPDU_END_RESERVED_1A_MASK 0x000007ff00000000
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/* Description UNSUP_KTYPE_SHORT_FRAME
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This bit will be '1' when WEP or TKIP or WAPI key type is
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received for 11ah short frame. Crypto will bypass the
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received packet without decryption to RxOLE after setting
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this bit.
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*/
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#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x0000000000000000
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#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 43
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#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 43
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#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x0000080000000000
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/* Description RX_IN_TX_DECRYPT_BYP
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Indicates that RX packet is not decrypted as Crypto is busy
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with TX packet processing.
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*/
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#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000
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#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 44
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#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 44
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#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000100000000000
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/* Description OVERFLOW_ERR
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RXPCU Receive FIFO ran out of space to receive the full
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MPDU. Therefor this MPDU is terminated early and is thus
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corrupted.
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This MPDU will not be ACKed.
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RXPCU might still be able to correctly receive the following
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MPDUs in the PPDU if enough fifo space became available
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in time
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*/
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#define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000000
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#define RX_MPDU_END_OVERFLOW_ERR_LSB 45
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#define RX_MPDU_END_OVERFLOW_ERR_MSB 45
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#define RX_MPDU_END_OVERFLOW_ERR_MASK 0x0000200000000000
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/* Description MPDU_LENGTH_ERR
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Set by RXPCU if the expected MPDU length does not correspond
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with the actually received number of bytes in the MPDU.
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*/
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#define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000
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#define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 46
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#define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 46
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#define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x0000400000000000
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/* Description TKIP_MIC_ERR
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Set by RX CRYPTO when CRYPTO detected a TKIP MIC error for
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this MPDU
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*/
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#define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000000
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#define RX_MPDU_END_TKIP_MIC_ERR_LSB 47
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#define RX_MPDU_END_TKIP_MIC_ERR_MSB 47
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#define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x0000800000000000
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/* Description DECRYPT_ERR
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Set by RX CRYPTO when CRYPTO detected a decrypt error for
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this MPDU or CRYPTO received an encrypted frame, but did
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not get a valid corresponding key id in the peer entry.
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*/
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#define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x0000000000000000
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#define RX_MPDU_END_DECRYPT_ERR_LSB 48
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#define RX_MPDU_END_DECRYPT_ERR_MSB 48
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#define RX_MPDU_END_DECRYPT_ERR_MASK 0x0001000000000000
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/* Description UNENCRYPTED_FRAME_ERR
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Set by RX CRYPTO when CRYPTO detected an unencrypted frame
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while in the peer entry field 'All_frames_shall_be_encrypted'
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is set.
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*/
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#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000
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#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 49
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#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 49
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#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0002000000000000
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/* Description PN_FIELDS_CONTAIN_VALID_INFO
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Set by RX CRYPTO to indicate that there is a valid PN field
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present in this MPDU
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*/
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#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000000000000
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#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 50
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#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 50
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#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x0004000000000000
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/* Description FCS_ERR
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Set by RXPCU when there is an FCS error detected for this
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MPDU
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NOTE that when this field is set, all other (error) field
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settings should be ignored as modules could have made wrong
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decisions based on the corrupted data.
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*/
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#define RX_MPDU_END_FCS_ERR_OFFSET 0x0000000000000000
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#define RX_MPDU_END_FCS_ERR_LSB 51
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#define RX_MPDU_END_FCS_ERR_MSB 51
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#define RX_MPDU_END_FCS_ERR_MASK 0x0008000000000000
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/* Description MSDU_LENGTH_ERR
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Set by RXOLE when there is an msdu length error detected
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in at least 1 of the MSDUs embedded within the MPDU
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*/
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#define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000
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#define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 52
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#define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 52
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#define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x0010000000000000
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/* Description RXDMA0_DESTINATION_RING
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The ring to which RXDMA0 shall push the frame, assuming
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no MPDU level errors are detected. In case of MPDU level
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errors, RXDMA0 might change the RXDMA0 destination
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<enum 0 rxdma_release_ring > RXDMA0 shall push the frame
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to the Release ring. Effectively this means the frame needs
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to be dropped.
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<enum 1 rxdma2fw_pmac0_ring > RXDMA0 shall push the frame
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to the FW ring for PMAC0.
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<enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to
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the SW ring
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<enum 3 rxdma2reo_ring > RXDMA0 shall push the frame to
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the REO entrance ring
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<enum 4 rxdma2fw_pmac1_ring> RXDMA0 shall push the frame
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to the FW ring for PMAC1.
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<enum 5 rxdma2reo_remote0_ring> RXDMA0 shall push the frame
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to the first MLO REO entrance ring.
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<enum 6 rxdma2reo_remote1_ring> RXDMA0 shall push the frame
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to the second MLO REO entrance ring.
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<legal 0 - 6>
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*/
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#define RX_MPDU_END_RXDMA0_DESTINATION_RING_OFFSET 0x0000000000000000
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#define RX_MPDU_END_RXDMA0_DESTINATION_RING_LSB 53
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#define RX_MPDU_END_RXDMA0_DESTINATION_RING_MSB 55
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#define RX_MPDU_END_RXDMA0_DESTINATION_RING_MASK 0x00e0000000000000
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/* Description RXDMA1_DESTINATION_RING
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The ring to which RXDMA1 shall push the frame, assuming
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no MPDU level errors are detected. In case of MPDU level
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errors, RXDMA1 might change the RXDMA destination
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<enum 0 rxdma_release_ring > DO NOT USE.
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<enum 1 rxdma2fw_pmac0_ring > DO NOT USE.
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<enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to
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the SW ring
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<enum 3 rxdma2reo_ring > DO NOT USE.
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<enum 4 rxdma2fw_pmac1_ring> DO NOT USE.
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<enum 5 rxdma2reo_remote0_ring> DO NOT USE.
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<enum 6 rxdma2reo_remote1_ring> DO NOT USE.
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<legal 0 - 6>
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*/
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#define RX_MPDU_END_RXDMA1_DESTINATION_RING_OFFSET 0x0000000000000000
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#define RX_MPDU_END_RXDMA1_DESTINATION_RING_LSB 56
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#define RX_MPDU_END_RXDMA1_DESTINATION_RING_MSB 58
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#define RX_MPDU_END_RXDMA1_DESTINATION_RING_MASK 0x0700000000000000
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/* Description DECRYPT_STATUS_CODE
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Field provides insight into the decryption performed
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<enum 0 decrypt_ok> Frame had protection enabled and decrypted
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properly
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<enum 1 decrypt_unprotected_frame > Frame is unprotected
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and hence bypassed
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<enum 2 decrypt_data_err > Frame has protection enabled
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and could not be properly decrypted due to MIC/ICV mismatch
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etc.
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<enum 3 decrypt_key_invalid > Frame has protection enabled
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but the key that was required to decrypt this frame was
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not valid
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<enum 4 decrypt_peer_entry_invalid > Frame has protection
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enabled but the key that was required to decrypt this frame
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was not valid
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<enum 5 decrypt_other > Reserved for other indications
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<legal 0 - 5>
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*/
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#define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000000
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#define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 59
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#define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 61
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#define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x3800000000000000
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/* Description RX_BITMAP_NOT_UPDATED
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Frame is received, but RXPCU could not update the receive
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bitmap due to (temporary) fifo contraints.
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<legal all>
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*/
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#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000000
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#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 62
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#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 62
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#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x4000000000000000
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/* Description RESERVED_1B
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|
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|
<legal 0>
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*/
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|
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#define RX_MPDU_END_RESERVED_1B_OFFSET 0x0000000000000000
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#define RX_MPDU_END_RESERVED_1B_LSB 63
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#define RX_MPDU_END_RESERVED_1B_MSB 63
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#define RX_MPDU_END_RESERVED_1B_MASK 0x8000000000000000
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|
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/* Description RESERVED_2A
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|
|
|
<legal 0>
|
|
*/
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|
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#define RX_MPDU_END_RESERVED_2A_OFFSET 0x0000000000000008
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#define RX_MPDU_END_RESERVED_2A_LSB 0
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#define RX_MPDU_END_RESERVED_2A_MSB 14
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#define RX_MPDU_END_RESERVED_2A_MASK 0x0000000000007fff
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|
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/* Description RXPCU_MGMT_SEQUENCE_NR_VALID
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|
|
|
This field gets set by RXPCU when the received management
|
|
frame is destined to this device, passes FCS and is categorized
|
|
as one for which RXPCU should assign a rxpcu_mgmt_sequence_number.
|
|
After assigning a number, the RXPCU will increment the sequence
|
|
number for the next management frame that meets these criteria.
|
|
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x0000000000000008
|
|
#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15
|
|
#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15
|
|
#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x0000000000008000
|
|
|
|
|
|
/* Description RXPCU_MGMT_SEQUENCE_NR
|
|
|
|
Field only valid when rxpcu_mgmt_sequence_nr_valid is set
|
|
|
|
|
|
This RXPCU generated sequence number is assigned to this
|
|
management frame. It is used by FW and host SW for management
|
|
frame reordering across multiple bands/links.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x0000000000000008
|
|
#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16
|
|
#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31
|
|
#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0x00000000ffff0000
|
|
|
|
|
|
/* Description RXFRAME_ASSERT_MLO_TIMESTAMP
|
|
|
|
'mlo_global_timestamp' that indicates when for the PPDU
|
|
that contained this MPDU, the 'rx_frame' signal got asserted.
|
|
|
|
|
|
This field is always valid, irrespective of the frame being
|
|
related to MLO reception or not. It is used by FW and host
|
|
SW for management frame reordering purposes.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_OFFSET 0x0000000000000008
|
|
#define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_LSB 32
|
|
#define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MSB 63
|
|
#define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MASK 0xffffffff00000000
|
|
|
|
|
|
|
|
#endif // RX_MPDU_END
|