36637cf177
Added ipq5332 target header files under qca5332 to make fw-api project compatible to host. Change-Id: Iee6b3f2a809f31e62b45a0f6e9a7cbb66e070fa0
1066 行
44 KiB
C
1066 行
44 KiB
C
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/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _REO_UPDATE_RX_REO_QUEUE_H_
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#define _REO_UPDATE_RX_REO_QUEUE_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#include "uniform_reo_cmd_header.h"
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#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 10
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#define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE 5
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struct reo_update_rx_reo_queue {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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struct uniform_reo_cmd_header cmd_header;
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uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0]
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uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0]
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update_receive_queue_number : 1, // [8:8]
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update_vld : 1, // [9:9]
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update_associated_link_descriptor_counter : 1, // [10:10]
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update_disable_duplicate_detection : 1, // [11:11]
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update_soft_reorder_enable : 1, // [12:12]
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update_ac : 1, // [13:13]
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update_bar : 1, // [14:14]
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update_rty : 1, // [15:15]
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update_chk_2k_mode : 1, // [16:16]
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update_oor_mode : 1, // [17:17]
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update_ba_window_size : 1, // [18:18]
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update_pn_check_needed : 1, // [19:19]
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update_pn_shall_be_even : 1, // [20:20]
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update_pn_shall_be_uneven : 1, // [21:21]
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update_pn_handling_enable : 1, // [22:22]
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update_pn_size : 1, // [23:23]
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update_ignore_ampdu_flag : 1, // [24:24]
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update_svld : 1, // [25:25]
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update_ssn : 1, // [26:26]
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update_seq_2k_error_detected_flag : 1, // [27:27]
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update_pn_error_detected_flag : 1, // [28:28]
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update_pn_valid : 1, // [29:29]
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update_pn : 1, // [30:30]
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clear_stat_counters : 1; // [31:31]
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uint32_t receive_queue_number : 16, // [15:0]
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vld : 1, // [16:16]
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associated_link_descriptor_counter : 2, // [18:17]
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disable_duplicate_detection : 1, // [19:19]
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soft_reorder_enable : 1, // [20:20]
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ac : 2, // [22:21]
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bar : 1, // [23:23]
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rty : 1, // [24:24]
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chk_2k_mode : 1, // [25:25]
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oor_mode : 1, // [26:26]
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pn_check_needed : 1, // [27:27]
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pn_shall_be_even : 1, // [28:28]
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pn_shall_be_uneven : 1, // [29:29]
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pn_handling_enable : 1, // [30:30]
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ignore_ampdu_flag : 1; // [31:31]
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uint32_t ba_window_size : 10, // [9:0]
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pn_size : 2, // [11:10]
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svld : 1, // [12:12]
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ssn : 12, // [24:13]
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seq_2k_error_detected_flag : 1, // [25:25]
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pn_error_detected_flag : 1, // [26:26]
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pn_valid : 1, // [27:27]
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flush_from_cache : 1, // [28:28]
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reserved_4a : 3; // [31:29]
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uint32_t pn_31_0 : 32; // [31:0]
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uint32_t pn_63_32 : 32; // [31:0]
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uint32_t pn_95_64 : 32; // [31:0]
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uint32_t pn_127_96 : 32; // [31:0]
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uint32_t tlv64_padding : 32; // [31:0]
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#else
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struct uniform_reo_cmd_header cmd_header;
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uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0]
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uint32_t clear_stat_counters : 1, // [31:31]
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update_pn : 1, // [30:30]
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update_pn_valid : 1, // [29:29]
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update_pn_error_detected_flag : 1, // [28:28]
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update_seq_2k_error_detected_flag : 1, // [27:27]
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update_ssn : 1, // [26:26]
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update_svld : 1, // [25:25]
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update_ignore_ampdu_flag : 1, // [24:24]
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update_pn_size : 1, // [23:23]
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update_pn_handling_enable : 1, // [22:22]
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update_pn_shall_be_uneven : 1, // [21:21]
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update_pn_shall_be_even : 1, // [20:20]
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update_pn_check_needed : 1, // [19:19]
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update_ba_window_size : 1, // [18:18]
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update_oor_mode : 1, // [17:17]
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update_chk_2k_mode : 1, // [16:16]
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update_rty : 1, // [15:15]
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update_bar : 1, // [14:14]
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update_ac : 1, // [13:13]
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update_soft_reorder_enable : 1, // [12:12]
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update_disable_duplicate_detection : 1, // [11:11]
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update_associated_link_descriptor_counter : 1, // [10:10]
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update_vld : 1, // [9:9]
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update_receive_queue_number : 1, // [8:8]
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rx_reo_queue_desc_addr_39_32 : 8; // [7:0]
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uint32_t ignore_ampdu_flag : 1, // [31:31]
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pn_handling_enable : 1, // [30:30]
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pn_shall_be_uneven : 1, // [29:29]
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pn_shall_be_even : 1, // [28:28]
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pn_check_needed : 1, // [27:27]
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oor_mode : 1, // [26:26]
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chk_2k_mode : 1, // [25:25]
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rty : 1, // [24:24]
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bar : 1, // [23:23]
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ac : 2, // [22:21]
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soft_reorder_enable : 1, // [20:20]
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disable_duplicate_detection : 1, // [19:19]
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associated_link_descriptor_counter : 2, // [18:17]
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vld : 1, // [16:16]
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receive_queue_number : 16; // [15:0]
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uint32_t reserved_4a : 3, // [31:29]
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flush_from_cache : 1, // [28:28]
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pn_valid : 1, // [27:27]
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pn_error_detected_flag : 1, // [26:26]
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seq_2k_error_detected_flag : 1, // [25:25]
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ssn : 12, // [24:13]
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svld : 1, // [12:12]
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pn_size : 2, // [11:10]
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ba_window_size : 10; // [9:0]
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uint32_t pn_31_0 : 32; // [31:0]
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uint32_t pn_63_32 : 32; // [31:0]
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uint32_t pn_95_64 : 32; // [31:0]
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uint32_t pn_127_96 : 32; // [31:0]
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uint32_t tlv64_padding : 32; // [31:0]
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#endif
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};
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/* Description CMD_HEADER
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Consumer: REO
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Producer: SW
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Details for command execution tracking purposes.
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*/
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/* Description REO_CMD_NUMBER
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Consumer: REO/SW/DEBUG
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Producer: SW
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This number can be used by SW to track, identify and link
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the created commands with the command statusses
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<legal all>
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*/
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#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
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#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0
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#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15
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#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
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/* Description REO_STATUS_REQUIRED
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Consumer: REO
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Producer: SW
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<enum 0 NoStatus> REO does not need to generate a status
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TLV for the execution of this command
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<enum 1 StatusRequired> REO shall generate a status TLV
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for the execution of this command
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<legal all>
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*/
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#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
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#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
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#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
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#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
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/* Description RESERVED_0A
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<legal 0>
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*/
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#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
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#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17
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#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31
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#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
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/* Description RX_REO_QUEUE_DESC_ADDR_31_0
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Consumer: REO
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Producer: SW
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Address (lower 32 bits) of the REO queue descriptor
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<legal all>
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*/
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#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000
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#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32
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#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63
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#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000
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/* Description RX_REO_QUEUE_DESC_ADDR_39_32
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Consumer: REO
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Producer: SW
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Address (upper 8 bits) of the REO queue descriptor
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<legal all>
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*/
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#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008
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#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
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#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7
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#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff
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/* Description UPDATE_RECEIVE_QUEUE_NUMBER
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Consumer: REO
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Producer: SW
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When set, receive_queue_number from this command will be
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updated in the descriptor.
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<legal all>
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*/
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MSB 8
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x0000000000000100
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/* Description UPDATE_VLD
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Consumer: REO
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Producer: SW
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When clear, REO will NOT update the VLD bit setting. For
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this setting, SW MUST set the Flush_from_cache bit in this
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command.
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When set, VLD from this command will be updated in the descriptor.
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<legal all>
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*/
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_OFFSET 0x0000000000000008
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_LSB 9
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MSB 9
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MASK 0x0000000000000200
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/* Description UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER
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Consumer: REO
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Producer: SW
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When set, Associated_link_descriptor_counter from this command
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will be updated in the descriptor.
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<legal all>
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*/
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 10
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0000000000000400
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/* Description UPDATE_DISABLE_DUPLICATE_DETECTION
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Consumer: REO
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Producer: SW
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When set, Disable_duplicate_detection from this command
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will be updated in the descriptor.
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<legal all>
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*/
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MSB 11
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x0000000000000800
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/* Description UPDATE_SOFT_REORDER_ENABLE
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Consumer: REO
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Producer: SW
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When set, Soft_reorder_enable from this command will be
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updated in the descriptor.
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<legal all>
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*/
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_LSB 12
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MSB 12
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MASK 0x0000000000001000
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/* Description UPDATE_AC
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Consumer: REO
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Producer: SW
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When set, AC from this command will be updated in the descriptor.
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<legal all>
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*/
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_OFFSET 0x0000000000000008
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_LSB 13
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MSB 13
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MASK 0x0000000000002000
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/* Description UPDATE_BAR
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Consumer: REO
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Producer: SW
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When set, BAR from this command will be updated in the descriptor.
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<legal all>
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*/
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_OFFSET 0x0000000000000008
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_LSB 14
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MSB 14
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MASK 0x0000000000004000
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/* Description UPDATE_RTY
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Consumer: REO
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Producer: SW
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When set, RTY from this command will be updated in the descriptor.
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<legal all>
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*/
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_OFFSET 0x0000000000000008
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_LSB 15
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MSB 15
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MASK 0x0000000000008000
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/* Description UPDATE_CHK_2K_MODE
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Consumer: REO
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Producer: SW
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When set, Chk_2k_mode from this command will be updated
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in the descriptor.
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<legal all>
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*/
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_OFFSET 0x0000000000000008
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_LSB 16
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MSB 16
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MASK 0x0000000000010000
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/* Description UPDATE_OOR_MODE
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Consumer: REO
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Producer: SW
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When set, OOR_Mode from this command will be updated in
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the descriptor.
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<legal all>
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*/
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_OFFSET 0x0000000000000008
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_LSB 17
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MSB 17
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MASK 0x0000000000020000
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/* Description UPDATE_BA_WINDOW_SIZE
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Consumer: REO
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Producer: SW
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When set, BA_window_size from this command will be updated
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in the descriptor.
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<legal all>
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*/
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_OFFSET 0x0000000000000008
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_LSB 18
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MSB 18
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MASK 0x0000000000040000
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/* Description UPDATE_PN_CHECK_NEEDED
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Consumer: REO
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Producer: SW
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When set, Pn_check_needed from this command will be updated
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in the descriptor.
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<legal all>
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*/
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_LSB 19
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MSB 19
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#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MASK 0x0000000000080000
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/* Description UPDATE_PN_SHALL_BE_EVEN
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Consumer: REO
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Producer: SW
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When set, Pn_shall_be_even from this command will be updated
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in the descriptor.
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_LSB 20
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MSB 20
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MASK 0x0000000000100000
|
|
|
|
|
|
/* Description UPDATE_PN_SHALL_BE_UNEVEN
|
|
|
|
Consumer: REO
|
|
Producer: SW
|
|
When set, Pn_shall_be_uneven from this command will be updated
|
|
in the descriptor.
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MSB 21
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x0000000000200000
|
|
|
|
|
|
/* Description UPDATE_PN_HANDLING_ENABLE
|
|
|
|
Consumer: REO
|
|
Producer: SW
|
|
When set, Pn_handling_enable from this command will be updated
|
|
in the descriptor.
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_LSB 22
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MSB 22
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MASK 0x0000000000400000
|
|
|
|
|
|
/* Description UPDATE_PN_SIZE
|
|
|
|
Consumer: REO
|
|
Producer: SW
|
|
When set, Pn_size from this command will be updated in the
|
|
descriptor.
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_LSB 23
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MSB 23
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MASK 0x0000000000800000
|
|
|
|
|
|
/* Description UPDATE_IGNORE_AMPDU_FLAG
|
|
|
|
Consumer: REO
|
|
Producer: SW
|
|
When set, Ignore_ampdu_flag from this command will be updated
|
|
in the descriptor.
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_LSB 24
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MSB 24
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x0000000001000000
|
|
|
|
|
|
/* Description UPDATE_SVLD
|
|
|
|
Consumer: REO
|
|
Producer: SW
|
|
When set, Svld from this command will be updated in the
|
|
descriptor.
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_LSB 25
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MSB 25
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MASK 0x0000000002000000
|
|
|
|
|
|
/* Description UPDATE_SSN
|
|
|
|
Consumer: REO
|
|
Producer: SW
|
|
When set, SSN from this command will be updated in the descriptor.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_LSB 26
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MSB 26
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MASK 0x0000000004000000
|
|
|
|
|
|
/* Description UPDATE_SEQ_2K_ERROR_DETECTED_FLAG
|
|
|
|
Consumer: REO
|
|
Producer: SW
|
|
When set, Seq_2k_error_detected_flag from this command will
|
|
be updated in the descriptor.
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 27
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000008000000
|
|
|
|
|
|
/* Description UPDATE_PN_ERROR_DETECTED_FLAG
|
|
|
|
Consumer: REO
|
|
Producer: SW
|
|
When set, pn_error_detected_flag from this command will
|
|
be updated in the descriptor.
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MSB 28
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000010000000
|
|
|
|
|
|
/* Description UPDATE_PN_VALID
|
|
|
|
Consumer: REO
|
|
Producer: SW
|
|
When set, pn_valid from this command will be updated in
|
|
the descriptor.
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_LSB 29
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MSB 29
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MASK 0x0000000020000000
|
|
|
|
|
|
/* Description UPDATE_PN
|
|
|
|
Consumer: REO
|
|
Producer: SW
|
|
When set, all pn_... fields from this command will be updated
|
|
in the descriptor.
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_LSB 30
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MSB 30
|
|
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MASK 0x0000000040000000
|
|
|
|
|
|
/* Description CLEAR_STAT_COUNTERS
|
|
|
|
Consumer: REO
|
|
Producer: SW
|
|
When set, REO will clear (=> set to 0) the following stat
|
|
counters in the REO_QUEUE_STRUCT
|
|
|
|
Last_rx_enqueue_TimeStamp
|
|
Last_rx_dequeue_Timestamp
|
|
Rx_bitmap (not a counter, but bitmap is cleared)
|
|
Timeout_count
|
|
Forward_due_to_bar_count
|
|
Duplicate_count
|
|
Frames_in_order_count
|
|
BAR_received_count
|
|
MPDU_Frames_processed_count
|
|
MSDU_Frames_processed_count
|
|
Total_processed_byte_count
|
|
Late_receive_MPDU_count
|
|
window_jump_2k
|
|
Hole_count
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_LSB 31
|
|
#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MSB 31
|
|
#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MASK 0x0000000080000000
|
|
|
|
|
|
/* Description RECEIVE_QUEUE_NUMBER
|
|
|
|
Field only valid when Update_receive_queue_number is set
|
|
|
|
|
|
Field value to be copied over into the RX_REO_QUEUE descriptor.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 32
|
|
#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 47
|
|
#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff00000000
|
|
|
|
|
|
/* Description VLD
|
|
|
|
Field only valid when Update_VLD is set
|
|
|
|
For Update_VLD set and VLD clear, SW MUST set the Flush_from_cache
|
|
bit in this command.
|
|
|
|
Field value to be copied over into the RX_REO_QUEUE descriptor.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_VLD_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_VLD_LSB 48
|
|
#define REO_UPDATE_RX_REO_QUEUE_VLD_MSB 48
|
|
#define REO_UPDATE_RX_REO_QUEUE_VLD_MASK 0x0001000000000000
|
|
|
|
|
|
/* Description ASSOCIATED_LINK_DESCRIPTOR_COUNTER
|
|
|
|
Field only valid when Update_Associated_link_descriptor_counter
|
|
is set
|
|
|
|
Field value to be copied over into the RX_REO_QUEUE descriptor.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 49
|
|
#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 50
|
|
#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0006000000000000
|
|
|
|
|
|
/* Description DISABLE_DUPLICATE_DETECTION
|
|
|
|
Field only valid when Update_Disable_duplicate_detection
|
|
is set
|
|
|
|
Field value to be copied over into the RX_REO_QUEUE descriptor.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 51
|
|
#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 51
|
|
#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x0008000000000000
|
|
|
|
|
|
/* Description SOFT_REORDER_ENABLE
|
|
|
|
Field only valid when Update_Soft_reorder_enable is set
|
|
|
|
Field value to be copied over into the RX_REO_QUEUE descriptor.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 52
|
|
#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 52
|
|
#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x0010000000000000
|
|
|
|
|
|
/* Description AC
|
|
|
|
Field only valid when Update_AC is set
|
|
|
|
Field value to be copied over into the RX_REO_QUEUE descriptor.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_AC_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_AC_LSB 53
|
|
#define REO_UPDATE_RX_REO_QUEUE_AC_MSB 54
|
|
#define REO_UPDATE_RX_REO_QUEUE_AC_MASK 0x0060000000000000
|
|
|
|
|
|
/* Description BAR
|
|
|
|
Field only valid when Update_BAR is set
|
|
|
|
Field value to be copied over into the RX_REO_QUEUE descriptor.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_BAR_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_BAR_LSB 55
|
|
#define REO_UPDATE_RX_REO_QUEUE_BAR_MSB 55
|
|
#define REO_UPDATE_RX_REO_QUEUE_BAR_MASK 0x0080000000000000
|
|
|
|
|
|
/* Description RTY
|
|
|
|
Field only valid when Update_RTY is set
|
|
|
|
Field value to be copied over into the RX_REO_QUEUE descriptor.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_RTY_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_RTY_LSB 56
|
|
#define REO_UPDATE_RX_REO_QUEUE_RTY_MSB 56
|
|
#define REO_UPDATE_RX_REO_QUEUE_RTY_MASK 0x0100000000000000
|
|
|
|
|
|
/* Description CHK_2K_MODE
|
|
|
|
Field only valid when Update_Chk_2k_Mode is set
|
|
|
|
Field value to be copied over into the RX_REO_QUEUE descriptor.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_LSB 57
|
|
#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MSB 57
|
|
#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MASK 0x0200000000000000
|
|
|
|
|
|
/* Description OOR_MODE
|
|
|
|
Field only valid when Update_OOR_Mode is set
|
|
|
|
Field value to be copied over into the RX_REO_QUEUE descriptor.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_LSB 58
|
|
#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MSB 58
|
|
#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MASK 0x0400000000000000
|
|
|
|
|
|
/* Description PN_CHECK_NEEDED
|
|
|
|
Field only valid when Update_Pn_check_needed is set
|
|
|
|
Field value to be copied over into the RX_REO_QUEUE descriptor.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 59
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 59
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x0800000000000000
|
|
|
|
|
|
/* Description PN_SHALL_BE_EVEN
|
|
|
|
Field only valid when Update_Pn_shall_be_even is set
|
|
|
|
Field value to be copied over into the RX_REO_QUEUE descriptor.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 60
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 60
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x1000000000000000
|
|
|
|
|
|
/* Description PN_SHALL_BE_UNEVEN
|
|
|
|
Field only valid when Update_Pn_shall_be_uneven is set
|
|
|
|
Field value to be copied over into the RX_REO_QUEUE descriptor.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 61
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 61
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x2000000000000000
|
|
|
|
|
|
/* Description PN_HANDLING_ENABLE
|
|
|
|
Field only valid when Update_Pn_handling_enable is set
|
|
|
|
Field value to be copied over into the RX_REO_QUEUE descriptor.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 62
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 62
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x4000000000000000
|
|
|
|
|
|
/* Description IGNORE_AMPDU_FLAG
|
|
|
|
Field only valid when Update_Ignore_ampdu_flag is set
|
|
|
|
Field value to be copied over into the RX_REO_QUEUE descriptor.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008
|
|
#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 63
|
|
#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 63
|
|
#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x8000000000000000
|
|
|
|
|
|
/* Description BA_WINDOW_SIZE
|
|
|
|
Field only valid when Update_BA_window_size is set
|
|
|
|
Field value to be copied over into the RX_REO_QUEUE descriptor.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x0000000000000010
|
|
#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 0
|
|
#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 9
|
|
#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x00000000000003ff
|
|
|
|
|
|
/* Description PN_SIZE
|
|
|
|
Field only valid when Update_Pn_size is set
|
|
|
|
Field value to be copied over into the RX_REO_QUEUE descriptor.
|
|
|
|
|
|
<enum 0 pn_size_24>
|
|
<enum 1 pn_size_48>
|
|
<enum 2 pn_size_128>
|
|
|
|
<legal 0-2>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_OFFSET 0x0000000000000010
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_LSB 10
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MSB 11
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MASK 0x0000000000000c00
|
|
|
|
|
|
/* Description SVLD
|
|
|
|
Field only valid when Update_Svld is set
|
|
|
|
Field value to be copied over into the RX_REO_QUEUE descriptor.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_SVLD_OFFSET 0x0000000000000010
|
|
#define REO_UPDATE_RX_REO_QUEUE_SVLD_LSB 12
|
|
#define REO_UPDATE_RX_REO_QUEUE_SVLD_MSB 12
|
|
#define REO_UPDATE_RX_REO_QUEUE_SVLD_MASK 0x0000000000001000
|
|
|
|
|
|
/* Description SSN
|
|
|
|
Field only valid when Update_SSN is set
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Field value to be copied over into the RX_REO_QUEUE descriptor.
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<legal all>
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*/
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#define REO_UPDATE_RX_REO_QUEUE_SSN_OFFSET 0x0000000000000010
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#define REO_UPDATE_RX_REO_QUEUE_SSN_LSB 13
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#define REO_UPDATE_RX_REO_QUEUE_SSN_MSB 24
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#define REO_UPDATE_RX_REO_QUEUE_SSN_MASK 0x0000000001ffe000
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/* Description SEQ_2K_ERROR_DETECTED_FLAG
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Field only valid when Update_Seq_2k_error_detected_flag
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is set
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Field value to be copied over into the RX_REO_QUEUE descriptor.
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<legal all>
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*/
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#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010
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#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 25
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#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 25
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#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000002000000
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/* Description PN_ERROR_DETECTED_FLAG
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Field only valid when Update_pn_error_detected_flag is set
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Field value to be copied over into the RX_REO_QUEUE descriptor.
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<legal all>
|
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*/
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#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010
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#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 26
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#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 26
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#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000004000000
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/* Description PN_VALID
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Field only valid when Update_pn_valid is set
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Field value to be copied over into the RX_REO_QUEUE descriptor.
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|
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<legal all>
|
|
*/
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#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000000000010
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|
#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_LSB 27
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#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MSB 27
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#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MASK 0x0000000008000000
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|
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/* Description FLUSH_FROM_CACHE
|
|
|
|
When set, REO shall, after finishing the execution of this
|
|
command, flush the related descriptor from the cache.
|
|
<legal all>
|
|
*/
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|
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|
#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_OFFSET 0x0000000000000010
|
|
#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_LSB 28
|
|
#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MSB 28
|
|
#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MASK 0x0000000010000000
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|
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/* Description RESERVED_4A
|
|
|
|
<legal 0>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010
|
|
#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_LSB 29
|
|
#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MSB 31
|
|
#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MASK 0x00000000e0000000
|
|
|
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|
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/* Description PN_31_0
|
|
|
|
Field only valid when Update_Pn is set
|
|
|
|
Field value to be copied over into the RX_REO_QUEUE descriptor.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_OFFSET 0x0000000000000010
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_LSB 32
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MSB 63
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MASK 0xffffffff00000000
|
|
|
|
|
|
/* Description PN_63_32
|
|
|
|
Field only valid when Update_pn is set
|
|
|
|
Field value to be copied over into the RX_REO_QUEUE descriptor.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_OFFSET 0x0000000000000018
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_LSB 0
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MSB 31
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MASK 0x00000000ffffffff
|
|
|
|
|
|
/* Description PN_95_64
|
|
|
|
Field only valid when Update_pn is set
|
|
|
|
Field value to be copied over into the RX_REO_QUEUE descriptor.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_OFFSET 0x0000000000000018
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_LSB 32
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MSB 63
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MASK 0xffffffff00000000
|
|
|
|
|
|
/* Description PN_127_96
|
|
|
|
Field only valid when Update_pn is set
|
|
|
|
Field value to be copied over into the RX_REO_QUEUE descriptor.
|
|
|
|
<legal all>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_OFFSET 0x0000000000000020
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_LSB 0
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MSB 31
|
|
#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MASK 0x00000000ffffffff
|
|
|
|
|
|
/* Description TLV64_PADDING
|
|
|
|
Automatic DWORD padding inserted while converting TLV32
|
|
to TLV64 for 64 bit ARCH
|
|
<legal 0>
|
|
*/
|
|
|
|
#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020
|
|
#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_LSB 32
|
|
#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MSB 63
|
|
#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000
|
|
|
|
|
|
|
|
#endif // REO_UPDATE_RX_REO_QUEUE
|