36637cf177
Added ipq5332 target header files under qca5332 to make fw-api project compatible to host. Change-Id: Iee6b3f2a809f31e62b45a0f6e9a7cbb66e070fa0
404 lines
16 KiB
C
404 lines
16 KiB
C
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/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _REO_FLUSH_CACHE_H_
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#define _REO_FLUSH_CACHE_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#include "uniform_reo_cmd_header.h"
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#define NUM_OF_DWORDS_REO_FLUSH_CACHE 10
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#define NUM_OF_QWORDS_REO_FLUSH_CACHE 5
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struct reo_flush_cache {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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struct uniform_reo_cmd_header cmd_header;
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uint32_t flush_addr_31_0 : 32; // [31:0]
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uint32_t flush_addr_39_32 : 8, // [7:0]
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forward_all_mpdus_in_queue : 1, // [8:8]
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release_cache_block_index : 1, // [9:9]
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cache_block_resource_index : 2, // [11:10]
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flush_without_invalidate : 1, // [12:12]
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block_cache_usage_after_flush : 1, // [13:13]
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flush_entire_cache : 1, // [14:14]
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flush_queue_1k_desc : 1, // [15:15]
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reserved_2b : 16; // [31:16]
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uint32_t reserved_3a : 32; // [31:0]
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uint32_t reserved_4a : 32; // [31:0]
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uint32_t reserved_5a : 32; // [31:0]
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uint32_t reserved_6a : 32; // [31:0]
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uint32_t reserved_7a : 32; // [31:0]
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uint32_t reserved_8a : 32; // [31:0]
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uint32_t tlv64_padding : 32; // [31:0]
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#else
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struct uniform_reo_cmd_header cmd_header;
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uint32_t flush_addr_31_0 : 32; // [31:0]
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uint32_t reserved_2b : 16, // [31:16]
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flush_queue_1k_desc : 1, // [15:15]
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flush_entire_cache : 1, // [14:14]
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block_cache_usage_after_flush : 1, // [13:13]
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flush_without_invalidate : 1, // [12:12]
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cache_block_resource_index : 2, // [11:10]
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release_cache_block_index : 1, // [9:9]
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forward_all_mpdus_in_queue : 1, // [8:8]
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flush_addr_39_32 : 8; // [7:0]
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uint32_t reserved_3a : 32; // [31:0]
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uint32_t reserved_4a : 32; // [31:0]
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uint32_t reserved_5a : 32; // [31:0]
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uint32_t reserved_6a : 32; // [31:0]
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uint32_t reserved_7a : 32; // [31:0]
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uint32_t reserved_8a : 32; // [31:0]
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uint32_t tlv64_padding : 32; // [31:0]
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#endif
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};
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/* Description CMD_HEADER
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Consumer: REO
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Producer: SW
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Details for command execution tracking purposes.
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*/
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/* Description REO_CMD_NUMBER
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Consumer: REO/SW/DEBUG
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Producer: SW
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This number can be used by SW to track, identify and link
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the created commands with the command statusses
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<legal all>
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*/
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#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
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#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0
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#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15
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#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
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/* Description REO_STATUS_REQUIRED
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Consumer: REO
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Producer: SW
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<enum 0 NoStatus> REO does not need to generate a status
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TLV for the execution of this command
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<enum 1 StatusRequired> REO shall generate a status TLV
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for the execution of this command
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<legal all>
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*/
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#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
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#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
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#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
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#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
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/* Description RESERVED_0A
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<legal 0>
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*/
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#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
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#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB 17
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#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB 31
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#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
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/* Description FLUSH_ADDR_31_0
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Consumer: REO
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Producer: SW
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Address (lower 32 bits) of the descriptor to flush
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<legal all>
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*/
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#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET 0x0000000000000000
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#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB 32
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#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB 63
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#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK 0xffffffff00000000
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/* Description FLUSH_ADDR_39_32
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Consumer: REO
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Producer: SW
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Address (upper 8 bits) of the descriptor to flush
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<legal all>
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*/
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#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET 0x0000000000000008
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#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB 0
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#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB 7
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#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK 0x00000000000000ff
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/* Description FORWARD_ALL_MPDUS_IN_QUEUE
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Is only allowed to be set when the flush address corresponds
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with a REO descriptor.
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When set, REO shall first forward all the MPDUs held in
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the indicated re-order queue, before flushing the descriptor
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from the cache.
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<legal all>
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*/
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#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x0000000000000008
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#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8
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#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB 8
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#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x0000000000000100
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/* Description RELEASE_CACHE_BLOCK_INDEX
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Field not valid when Flush_entire_cache is set.
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If SW has previously used a blocking resource that it now
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wants to re-use for this command, this bit shall be set.
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It prevents SW from having to send a separate REO_UNBLOCK_CACHE
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command.
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When set, HW will first release the blocking resource (indicated
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in field 'Cache_block_resouce_index') before this command
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gets executed.
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If that resource was already unblocked, this will be considered
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an error. This command will not be executed, and an error
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shall be returned.
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<legal all>
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*/
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#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x0000000000000008
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#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB 9
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#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB 9
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#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK 0x0000000000000200
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/* Description CACHE_BLOCK_RESOURCE_INDEX
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Field not valid when Flush_entire_cache is set.
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Indicates which of the four blocking resources in REO will
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be assigned for managing the blocking of this (descriptor)
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address
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<legal all>
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*/
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#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008
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#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 10
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#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 11
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#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000c00
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/* Description FLUSH_WITHOUT_INVALIDATE
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Field not valid when Flush_entire_cache is set.
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When set, REO shall flush the cache line contents from the
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cache, but there is NO need to invalidate the cache line
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entry... The contents in the cache can be maintained. This
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feature can be used by SW (and DV) to get a current snapshot
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of the contents in the cache
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<legal all>
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*/
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#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x0000000000000008
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#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB 12
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#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB 12
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#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK 0x0000000000001000
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/* Description BLOCK_CACHE_USAGE_AFTER_FLUSH
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Field not valid when Flush_entire_cache is set.
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When set, REO shall block any cache accesses to this address
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till explicitly unblocked.
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Whenever SW sets this bit, SW shall also set bit 'Forward_all_mpdus_in_queue'
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to ensure all packets are flushed out in order to make sure
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this queue desc is not in one of the aging link lists.
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In case SW does not want to flush the MPDUs in the queue,
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see the recipe description below this TLV definition.
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The 'blocking' index to be used for this is indicated in
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field 'cache_block_resource_index'. If SW had previously
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used this blocking resource and was not freed up yet, SW
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shall first unblock that index (by setting bit Release_cache_block_index)
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or use an unblock command.
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If the resource indicated here was already blocked (and
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did not get unblocked in this command), it is considered
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an error scenario...
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No flush shall happen. The status for this command shall
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indicate error.
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<legal all>
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*/
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#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008
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#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13
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#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB 13
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#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x0000000000002000
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/* Description FLUSH_ENTIRE_CACHE
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When set, the entire cache shall be flushed. The entire
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cache will also remain blocked, till the 'REO_UNBLOCK_COMMAND'
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is received with bit unblock type set to unblock_cache.
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All other fields in this command are to be ignored.
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Note that flushing the entire cache has no changes to the
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current settings of the blocking resource settings
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<legal all>
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*/
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#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET 0x0000000000000008
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#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB 14
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#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB 14
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#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK 0x0000000000004000
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/* Description FLUSH_QUEUE_1K_DESC
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When set, REO will flush the 'RX_REO_QUEUE_1K' descriptor
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after flushing the 'RX_REO_QUEUE' descriptor.
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This bit shall only be set when the BA_window_size > 255
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in 'RX_REO_QUEUE.'
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<legal all>
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*/
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#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008
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#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB 15
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#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB 15
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#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK 0x0000000000008000
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/* Description RESERVED_2B
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<legal 0>
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*/
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#define REO_FLUSH_CACHE_RESERVED_2B_OFFSET 0x0000000000000008
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#define REO_FLUSH_CACHE_RESERVED_2B_LSB 16
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#define REO_FLUSH_CACHE_RESERVED_2B_MSB 31
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#define REO_FLUSH_CACHE_RESERVED_2B_MASK 0x00000000ffff0000
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/* Description RESERVED_3A
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<legal 0>
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*/
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#define REO_FLUSH_CACHE_RESERVED_3A_OFFSET 0x0000000000000008
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#define REO_FLUSH_CACHE_RESERVED_3A_LSB 32
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#define REO_FLUSH_CACHE_RESERVED_3A_MSB 63
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#define REO_FLUSH_CACHE_RESERVED_3A_MASK 0xffffffff00000000
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/* Description RESERVED_4A
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<legal 0>
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*/
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#define REO_FLUSH_CACHE_RESERVED_4A_OFFSET 0x0000000000000010
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#define REO_FLUSH_CACHE_RESERVED_4A_LSB 0
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#define REO_FLUSH_CACHE_RESERVED_4A_MSB 31
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#define REO_FLUSH_CACHE_RESERVED_4A_MASK 0x00000000ffffffff
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/* Description RESERVED_5A
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<legal 0>
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*/
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#define REO_FLUSH_CACHE_RESERVED_5A_OFFSET 0x0000000000000010
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#define REO_FLUSH_CACHE_RESERVED_5A_LSB 32
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#define REO_FLUSH_CACHE_RESERVED_5A_MSB 63
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#define REO_FLUSH_CACHE_RESERVED_5A_MASK 0xffffffff00000000
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/* Description RESERVED_6A
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<legal 0>
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*/
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#define REO_FLUSH_CACHE_RESERVED_6A_OFFSET 0x0000000000000018
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#define REO_FLUSH_CACHE_RESERVED_6A_LSB 0
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#define REO_FLUSH_CACHE_RESERVED_6A_MSB 31
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#define REO_FLUSH_CACHE_RESERVED_6A_MASK 0x00000000ffffffff
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/* Description RESERVED_7A
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<legal 0>
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*/
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#define REO_FLUSH_CACHE_RESERVED_7A_OFFSET 0x0000000000000018
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#define REO_FLUSH_CACHE_RESERVED_7A_LSB 32
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#define REO_FLUSH_CACHE_RESERVED_7A_MSB 63
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#define REO_FLUSH_CACHE_RESERVED_7A_MASK 0xffffffff00000000
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/* Description RESERVED_8A
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<legal 0>
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*/
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#define REO_FLUSH_CACHE_RESERVED_8A_OFFSET 0x0000000000000020
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#define REO_FLUSH_CACHE_RESERVED_8A_LSB 0
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#define REO_FLUSH_CACHE_RESERVED_8A_MSB 31
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#define REO_FLUSH_CACHE_RESERVED_8A_MASK 0x00000000ffffffff
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/* Description TLV64_PADDING
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Automatic DWORD padding inserted while converting TLV32
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to TLV64 for 64 bit ARCH
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<legal 0>
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*/
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#define REO_FLUSH_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020
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#define REO_FLUSH_CACHE_TLV64_PADDING_LSB 32
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#define REO_FLUSH_CACHE_TLV64_PADDING_MSB 63
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#define REO_FLUSH_CACHE_TLV64_PADDING_MASK 0xffffffff00000000
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#endif // REO_FLUSH_CACHE
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