36637cf177
Added ipq5332 target header files under qca5332 to make fw-api project compatible to host. Change-Id: Iee6b3f2a809f31e62b45a0f6e9a7cbb66e070fa0
224 line
8.3 KiB
C
224 line
8.3 KiB
C
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/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _PHYRX_ABORT_REQUEST_INFO_H_
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#define _PHYRX_ABORT_REQUEST_INFO_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1
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struct phyrx_abort_request_info {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t phyrx_abort_reason : 8, // [7:0]
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phy_enters_nap_state : 1, // [8:8]
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phy_enters_defer_state : 1, // [9:9]
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reserved_0 : 6, // [15:10]
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receive_duration : 16; // [31:16]
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#else
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uint32_t receive_duration : 16, // [31:16]
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reserved_0 : 6, // [15:10]
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phy_enters_defer_state : 1, // [9:9]
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phy_enters_nap_state : 1, // [8:8]
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phyrx_abort_reason : 8; // [7:0]
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#endif
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};
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/* Description PHYRX_ABORT_REASON
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<enum 0 phyrx_err_phy_off> Reception aborted due to receiving
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a PHY_OFF TLV
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<enum 1 phyrx_err_synth_off>
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<enum 2 phyrx_err_ofdma_timing>
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<enum 3 phyrx_err_ofdma_signal_parity>
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<enum 4 phyrx_err_ofdma_rate_illegal>
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<enum 5 phyrx_err_ofdma_length_illegal>
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<enum 6 phyrx_err_ofdma_restart>
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<enum 7 phyrx_err_ofdma_service>
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<enum 8 phyrx_err_ppdu_ofdma_power_drop>
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<enum 9 phyrx_err_cck_blokker>
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<enum 10 phyrx_err_cck_timing>
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<enum 11 phyrx_err_cck_header_crc>
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<enum 12 phyrx_err_cck_rate_illegal>
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<enum 13 phyrx_err_cck_length_illegal>
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<enum 14 phyrx_err_cck_restart>
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<enum 15 phyrx_err_cck_service>
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<enum 16 phyrx_err_cck_power_drop>
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<enum 17 phyrx_err_ht_crc_err>
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<enum 18 phyrx_err_ht_length_illegal>
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<enum 19 phyrx_err_ht_rate_illegal>
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<enum 20 phyrx_err_ht_zlf>
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<enum 21 phyrx_err_false_radar_ext>
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<enum 22 phyrx_err_green_field>
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<enum 60 phyrx_err_ht_nsym_lt_zero>
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<enum 23 phyrx_err_bw_gt_dyn_bw>
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<enum 24 phyrx_err_leg_ht_mismatch>
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<enum 25 phyrx_err_vht_crc_error>
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<enum 26 phyrx_err_vht_siga_unsupported>
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<enum 27 phyrx_err_vht_lsig_len_invalid>
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<enum 28 phyrx_err_vht_ndp_or_zlf>
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<enum 29 phyrx_err_vht_nsym_lt_zero>
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<enum 30 phyrx_err_vht_rx_extra_symbol_mismatch>
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<enum 31 phyrx_err_vht_rx_skip_group_id0>
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<enum 32 phyrx_err_vht_rx_skip_group_id1to62>
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<enum 33 phyrx_err_vht_rx_skip_group_id63>
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<enum 34 phyrx_err_ofdm_ldpc_decoder_disabled>
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<enum 35 phyrx_err_defer_nap>
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<enum 61 phyrx_err_vht_lsig_rate_mismatch>
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<enum 62 phyrx_err_vht_paid_gid_mismatch>
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<enum 63 phyrx_err_vht_unsupported_bw>
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<enum 64 phyrx_err_vht_gi_disam_mismatch>
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<enum 36 phyrx_err_fdomain_timeout>
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<enum 37 phyrx_err_lsig_rel_check>
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<enum 38 phyrx_err_bt_collision>
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<enum 39 phyrx_err_unsupported_mu_feedback>
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<enum 40 phyrx_err_ppdu_tx_interrupt_rx>
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<enum 41 phyrx_err_unsupported_cbf>
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<enum 42 phyrx_err_other> Should not really be used. If
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needed, ask for documentation update
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<enum 43 phyrx_err_he_siga_unsupported > <enum 44 phyrx_err_he_crc_error
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> <enum 45 phyrx_err_he_sigb_unsupported > <enum 46 phyrx_err_he_mu_mode_unsupported
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> <enum 47 phyrx_err_he_ndp_or_zlf > <enum 48 phyrx_err_he_nsym_lt_zero
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> <enum 49 phyrx_err_he_ru_params_unsupported > <enum 50
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phyrx_err_he_num_users_unsupported ><enum 51 phyrx_err_he_sounding_params_unsupported
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>
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<enum 54 phyrx_err_he_sigb_crc_error>
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<enum 55 phyrx_err_he_ext_su_unsupported>
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<enum 56 phyrx_err_he_trig_unsupported>
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<enum 57 phyrx_err_he_lsig_len_invalid>
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<enum 58 phyrx_err_he_lsig_rate_mismatch>
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<enum 59 phyrx_err_ofdma_signal_reliability>
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<enum 77 phyrx_err_wur_detection>
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<enum 72 phyrx_err_u_sig_crc_error>
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<enum 73 phyrx_err_u_sig_unsupported_mode>
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<enum 74 phyrx_err_u_sig_rsvd_err>
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<enum 75 phyrx_err_u_sig_mcs_error>
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<enum 76 phyrx_err_u_sig_bw_error>
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<enum 79 phyrx_err_u_sig_320_channel_mismatch>
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<enum 71 phyrx_err_eht_sig_crc_error>
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<enum 78 phyrx_err_eht_sig_unsupported_mode>
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<enum 80 phyrx_err_ehtplus_er_detection>
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<enum 52 phyrx_err_MU_UL_no_power_detected>
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<enum 53 phyrx_err_MU_UL_not_for_me>
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<enum 65 phyrx_err_rx_wdg_timeout>
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<enum 66 phyrx_err_sizing_evt_unexpected>
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<enum 67 phyrx_err_spectralscan>
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<enum 68 phyrx_err_radar_misdetected_as_ofdm>
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<enum 69 phyrx_err_rx_stuck>
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<enum 70 phyrx_err_invalid_11b_state>
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<legal 0 - 80>
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*/
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#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET 0x00000000
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#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB 0
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#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB 7
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#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK 0x000000ff
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/* Description PHY_ENTERS_NAP_STATE
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When set, PHY enters PHY NAP state after sending this abort
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Note that nap and defer state are mutually exclusive.
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Field put pro-actively in place....usage still to be agreed
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upon.
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<legal all>
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*/
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#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000
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#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB 8
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#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB 8
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#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK 0x00000100
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/* Description PHY_ENTERS_DEFER_STATE
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When set, PHY enters PHY defer state after sending this
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abort
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Note that nap and defer state are mutually exclusive.
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Field put pro-actively in place....usage still to be agreed
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upon.
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<legal all>
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*/
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#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000
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#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB 9
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#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB 9
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#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK 0x00000200
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/* Description RESERVED_0
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<legal 0>
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*/
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#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000
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#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 10
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#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15
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#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000fc00
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/* Description RECEIVE_DURATION
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The remaining receive duration of this PPDU in the medium
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(in us). When PHY does not know this duration when this
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TLV is generated, the field will be set to 0.
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The timing reference point is the reception by the MAC of
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this TLV. The value shall be accurate to within 2us.
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In case Phy_enters_nap_state and/or Phy_enters_defer_state
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is set, there is a possibility that MAC PMM can also decide
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to go into a low(er) power state.
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<legal all>
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*/
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#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET 0x00000000
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#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB 16
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#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB 31
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#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK 0xffff0000
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#endif // PHYRX_ABORT_REQUEST_INFO
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