dp_tx.c 144 KB

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  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #include "dp_ipa.h"
  31. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  32. #include "if_meta_hdr.h"
  33. #endif
  34. #include "enet.h"
  35. #include "dp_internal.h"
  36. #ifdef FEATURE_WDS
  37. #include "dp_txrx_wds.h"
  38. #endif
  39. #ifdef ATH_SUPPORT_IQUE
  40. #include "dp_txrx_me.h"
  41. #endif
  42. #include "dp_hist.h"
  43. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  44. #include <dp_swlm.h>
  45. #endif
  46. /* Flag to skip CCE classify when mesh or tid override enabled */
  47. #define DP_TX_SKIP_CCE_CLASSIFY \
  48. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  49. /* TODO Add support in TSO */
  50. #define DP_DESC_NUM_FRAG(x) 0
  51. /* disable TQM_BYPASS */
  52. #define TQM_BYPASS_WAR 0
  53. /* invalid peer id for reinject*/
  54. #define DP_INVALID_PEER 0XFFFE
  55. /*mapping between hal encrypt type and cdp_sec_type*/
  56. #define MAX_CDP_SEC_TYPE 12
  57. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  58. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  59. HAL_TX_ENCRYPT_TYPE_WEP_128,
  60. HAL_TX_ENCRYPT_TYPE_WEP_104,
  61. HAL_TX_ENCRYPT_TYPE_WEP_40,
  62. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  63. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  64. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  65. HAL_TX_ENCRYPT_TYPE_WAPI,
  66. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  67. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  68. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  69. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  70. #ifdef QCA_TX_LIMIT_CHECK
  71. /**
  72. * dp_tx_limit_check - Check if allocated tx descriptors reached
  73. * soc max limit and pdev max limit
  74. * @vdev: DP vdev handle
  75. *
  76. * Return: true if allocated tx descriptors reached max configured value, else
  77. * false
  78. */
  79. static inline bool
  80. dp_tx_limit_check(struct dp_vdev *vdev)
  81. {
  82. struct dp_pdev *pdev = vdev->pdev;
  83. struct dp_soc *soc = pdev->soc;
  84. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  85. soc->num_tx_allowed) {
  86. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  87. "%s: queued packets are more than max tx, drop the frame",
  88. __func__);
  89. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  90. return true;
  91. }
  92. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  93. pdev->num_tx_allowed) {
  94. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  95. "%s: queued packets are more than max tx, drop the frame",
  96. __func__);
  97. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  98. return true;
  99. }
  100. return false;
  101. }
  102. /**
  103. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  104. * reached soc max limit
  105. * @vdev: DP vdev handle
  106. *
  107. * Return: true if allocated tx descriptors reached max configured value, else
  108. * false
  109. */
  110. static inline bool
  111. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  112. {
  113. struct dp_pdev *pdev = vdev->pdev;
  114. struct dp_soc *soc = pdev->soc;
  115. if (qdf_atomic_read(&soc->num_tx_exception) >=
  116. soc->num_msdu_exception_desc) {
  117. dp_info("exc packets are more than max drop the exc pkt");
  118. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  119. return true;
  120. }
  121. return false;
  122. }
  123. /**
  124. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  125. * @vdev: DP pdev handle
  126. *
  127. * Return: void
  128. */
  129. static inline void
  130. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  131. {
  132. struct dp_soc *soc = pdev->soc;
  133. qdf_atomic_inc(&pdev->num_tx_outstanding);
  134. qdf_atomic_inc(&soc->num_tx_outstanding);
  135. }
  136. /**
  137. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  138. * @vdev: DP pdev handle
  139. *
  140. * Return: void
  141. */
  142. static inline void
  143. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  144. {
  145. struct dp_soc *soc = pdev->soc;
  146. qdf_atomic_dec(&pdev->num_tx_outstanding);
  147. qdf_atomic_dec(&soc->num_tx_outstanding);
  148. }
  149. #else //QCA_TX_LIMIT_CHECK
  150. static inline bool
  151. dp_tx_limit_check(struct dp_vdev *vdev)
  152. {
  153. return false;
  154. }
  155. static inline bool
  156. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  157. {
  158. return false;
  159. }
  160. static inline void
  161. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  162. {
  163. qdf_atomic_inc(&pdev->num_tx_outstanding);
  164. }
  165. static inline void
  166. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  167. {
  168. qdf_atomic_dec(&pdev->num_tx_outstanding);
  169. }
  170. #endif //QCA_TX_LIMIT_CHECK
  171. #if defined(FEATURE_TSO)
  172. /**
  173. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  174. *
  175. * @soc - core txrx main context
  176. * @seg_desc - tso segment descriptor
  177. * @num_seg_desc - tso number segment descriptor
  178. */
  179. static void dp_tx_tso_unmap_segment(
  180. struct dp_soc *soc,
  181. struct qdf_tso_seg_elem_t *seg_desc,
  182. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  183. {
  184. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  185. if (qdf_unlikely(!seg_desc)) {
  186. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  187. __func__, __LINE__);
  188. qdf_assert(0);
  189. } else if (qdf_unlikely(!num_seg_desc)) {
  190. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  191. __func__, __LINE__);
  192. qdf_assert(0);
  193. } else {
  194. bool is_last_seg;
  195. /* no tso segment left to do dma unmap */
  196. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  197. return;
  198. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  199. true : false;
  200. qdf_nbuf_unmap_tso_segment(soc->osdev,
  201. seg_desc, is_last_seg);
  202. num_seg_desc->num_seg.tso_cmn_num_seg--;
  203. }
  204. }
  205. /**
  206. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  207. * back to the freelist
  208. *
  209. * @soc - soc device handle
  210. * @tx_desc - Tx software descriptor
  211. */
  212. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  213. struct dp_tx_desc_s *tx_desc)
  214. {
  215. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  216. if (qdf_unlikely(!tx_desc->tso_desc)) {
  217. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  218. "%s %d TSO desc is NULL!",
  219. __func__, __LINE__);
  220. qdf_assert(0);
  221. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  222. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  223. "%s %d TSO num desc is NULL!",
  224. __func__, __LINE__);
  225. qdf_assert(0);
  226. } else {
  227. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  228. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  229. /* Add the tso num segment into the free list */
  230. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  231. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  232. tx_desc->tso_num_desc);
  233. tx_desc->tso_num_desc = NULL;
  234. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  235. }
  236. /* Add the tso segment into the free list*/
  237. dp_tx_tso_desc_free(soc,
  238. tx_desc->pool_id, tx_desc->tso_desc);
  239. tx_desc->tso_desc = NULL;
  240. }
  241. }
  242. #else
  243. static void dp_tx_tso_unmap_segment(
  244. struct dp_soc *soc,
  245. struct qdf_tso_seg_elem_t *seg_desc,
  246. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  247. {
  248. }
  249. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  250. struct dp_tx_desc_s *tx_desc)
  251. {
  252. }
  253. #endif
  254. /**
  255. * dp_tx_desc_release() - Release Tx Descriptor
  256. * @tx_desc : Tx Descriptor
  257. * @desc_pool_id: Descriptor Pool ID
  258. *
  259. * Deallocate all resources attached to Tx descriptor and free the Tx
  260. * descriptor.
  261. *
  262. * Return:
  263. */
  264. static void
  265. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  266. {
  267. struct dp_pdev *pdev = tx_desc->pdev;
  268. struct dp_soc *soc;
  269. uint8_t comp_status = 0;
  270. qdf_assert(pdev);
  271. soc = pdev->soc;
  272. dp_tx_outstanding_dec(pdev);
  273. if (tx_desc->frm_type == dp_tx_frm_tso)
  274. dp_tx_tso_desc_release(soc, tx_desc);
  275. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  276. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  277. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  278. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  279. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  280. qdf_atomic_dec(&soc->num_tx_exception);
  281. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  282. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  283. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  284. soc->hal_soc);
  285. else
  286. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  287. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  288. "Tx Completion Release desc %d status %d outstanding %d",
  289. tx_desc->id, comp_status,
  290. qdf_atomic_read(&pdev->num_tx_outstanding));
  291. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  292. return;
  293. }
  294. /**
  295. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  296. * @vdev: DP vdev Handle
  297. * @nbuf: skb
  298. * @msdu_info: msdu_info required to create HTT metadata
  299. *
  300. * Prepares and fills HTT metadata in the frame pre-header for special frames
  301. * that should be transmitted using varying transmit parameters.
  302. * There are 2 VDEV modes that currently needs this special metadata -
  303. * 1) Mesh Mode
  304. * 2) DSRC Mode
  305. *
  306. * Return: HTT metadata size
  307. *
  308. */
  309. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  310. struct dp_tx_msdu_info_s *msdu_info)
  311. {
  312. uint32_t *meta_data = msdu_info->meta_data;
  313. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  314. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  315. uint8_t htt_desc_size;
  316. /* Size rounded of multiple of 8 bytes */
  317. uint8_t htt_desc_size_aligned;
  318. uint8_t *hdr = NULL;
  319. /*
  320. * Metadata - HTT MSDU Extension header
  321. */
  322. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  323. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  324. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  325. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  326. meta_data[0])) {
  327. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  328. htt_desc_size_aligned)) {
  329. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  330. htt_desc_size_aligned);
  331. if (!nbuf) {
  332. /*
  333. * qdf_nbuf_realloc_headroom won't do skb_clone
  334. * as skb_realloc_headroom does. so, no free is
  335. * needed here.
  336. */
  337. DP_STATS_INC(vdev,
  338. tx_i.dropped.headroom_insufficient,
  339. 1);
  340. qdf_print(" %s[%d] skb_realloc_headroom failed",
  341. __func__, __LINE__);
  342. return 0;
  343. }
  344. }
  345. /* Fill and add HTT metaheader */
  346. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  347. if (!hdr) {
  348. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  349. "Error in filling HTT metadata");
  350. return 0;
  351. }
  352. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  353. } else if (vdev->opmode == wlan_op_mode_ocb) {
  354. /* Todo - Add support for DSRC */
  355. }
  356. return htt_desc_size_aligned;
  357. }
  358. /**
  359. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  360. * @tso_seg: TSO segment to process
  361. * @ext_desc: Pointer to MSDU extension descriptor
  362. *
  363. * Return: void
  364. */
  365. #if defined(FEATURE_TSO)
  366. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  367. void *ext_desc)
  368. {
  369. uint8_t num_frag;
  370. uint32_t tso_flags;
  371. /*
  372. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  373. * tcp_flag_mask
  374. *
  375. * Checksum enable flags are set in TCL descriptor and not in Extension
  376. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  377. */
  378. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  379. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  380. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  381. tso_seg->tso_flags.ip_len);
  382. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  383. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  384. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  385. uint32_t lo = 0;
  386. uint32_t hi = 0;
  387. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  388. (tso_seg->tso_frags[num_frag].length));
  389. qdf_dmaaddr_to_32s(
  390. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  391. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  392. tso_seg->tso_frags[num_frag].length);
  393. }
  394. return;
  395. }
  396. #else
  397. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  398. void *ext_desc)
  399. {
  400. return;
  401. }
  402. #endif
  403. #if defined(FEATURE_TSO)
  404. /**
  405. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  406. * allocated and free them
  407. *
  408. * @soc: soc handle
  409. * @free_seg: list of tso segments
  410. * @msdu_info: msdu descriptor
  411. *
  412. * Return - void
  413. */
  414. static void dp_tx_free_tso_seg_list(
  415. struct dp_soc *soc,
  416. struct qdf_tso_seg_elem_t *free_seg,
  417. struct dp_tx_msdu_info_s *msdu_info)
  418. {
  419. struct qdf_tso_seg_elem_t *next_seg;
  420. while (free_seg) {
  421. next_seg = free_seg->next;
  422. dp_tx_tso_desc_free(soc,
  423. msdu_info->tx_queue.desc_pool_id,
  424. free_seg);
  425. free_seg = next_seg;
  426. }
  427. }
  428. /**
  429. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  430. * allocated and free them
  431. *
  432. * @soc: soc handle
  433. * @free_num_seg: list of tso number segments
  434. * @msdu_info: msdu descriptor
  435. * Return - void
  436. */
  437. static void dp_tx_free_tso_num_seg_list(
  438. struct dp_soc *soc,
  439. struct qdf_tso_num_seg_elem_t *free_num_seg,
  440. struct dp_tx_msdu_info_s *msdu_info)
  441. {
  442. struct qdf_tso_num_seg_elem_t *next_num_seg;
  443. while (free_num_seg) {
  444. next_num_seg = free_num_seg->next;
  445. dp_tso_num_seg_free(soc,
  446. msdu_info->tx_queue.desc_pool_id,
  447. free_num_seg);
  448. free_num_seg = next_num_seg;
  449. }
  450. }
  451. /**
  452. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  453. * do dma unmap for each segment
  454. *
  455. * @soc: soc handle
  456. * @free_seg: list of tso segments
  457. * @num_seg_desc: tso number segment descriptor
  458. *
  459. * Return - void
  460. */
  461. static void dp_tx_unmap_tso_seg_list(
  462. struct dp_soc *soc,
  463. struct qdf_tso_seg_elem_t *free_seg,
  464. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  465. {
  466. struct qdf_tso_seg_elem_t *next_seg;
  467. if (qdf_unlikely(!num_seg_desc)) {
  468. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  469. return;
  470. }
  471. while (free_seg) {
  472. next_seg = free_seg->next;
  473. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  474. free_seg = next_seg;
  475. }
  476. }
  477. #ifdef FEATURE_TSO_STATS
  478. /**
  479. * dp_tso_get_stats_idx: Retrieve the tso packet id
  480. * @pdev - pdev handle
  481. *
  482. * Return: id
  483. */
  484. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  485. {
  486. uint32_t stats_idx;
  487. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  488. % CDP_MAX_TSO_PACKETS);
  489. return stats_idx;
  490. }
  491. #else
  492. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  493. {
  494. return 0;
  495. }
  496. #endif /* FEATURE_TSO_STATS */
  497. /**
  498. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  499. * free the tso segments descriptor and
  500. * tso num segments descriptor
  501. *
  502. * @soc: soc handle
  503. * @msdu_info: msdu descriptor
  504. * @tso_seg_unmap: flag to show if dma unmap is necessary
  505. *
  506. * Return - void
  507. */
  508. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  509. struct dp_tx_msdu_info_s *msdu_info,
  510. bool tso_seg_unmap)
  511. {
  512. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  513. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  514. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  515. tso_info->tso_num_seg_list;
  516. /* do dma unmap for each segment */
  517. if (tso_seg_unmap)
  518. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  519. /* free all tso number segment descriptor though looks only have 1 */
  520. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  521. /* free all tso segment descriptor */
  522. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  523. }
  524. /**
  525. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  526. * @vdev: virtual device handle
  527. * @msdu: network buffer
  528. * @msdu_info: meta data associated with the msdu
  529. *
  530. * Return: QDF_STATUS_SUCCESS success
  531. */
  532. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  533. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  534. {
  535. struct qdf_tso_seg_elem_t *tso_seg;
  536. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  537. struct dp_soc *soc = vdev->pdev->soc;
  538. struct dp_pdev *pdev = vdev->pdev;
  539. struct qdf_tso_info_t *tso_info;
  540. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  541. tso_info = &msdu_info->u.tso_info;
  542. tso_info->curr_seg = NULL;
  543. tso_info->tso_seg_list = NULL;
  544. tso_info->num_segs = num_seg;
  545. msdu_info->frm_type = dp_tx_frm_tso;
  546. tso_info->tso_num_seg_list = NULL;
  547. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  548. while (num_seg) {
  549. tso_seg = dp_tx_tso_desc_alloc(
  550. soc, msdu_info->tx_queue.desc_pool_id);
  551. if (tso_seg) {
  552. tso_seg->next = tso_info->tso_seg_list;
  553. tso_info->tso_seg_list = tso_seg;
  554. num_seg--;
  555. } else {
  556. dp_err_rl("Failed to alloc tso seg desc");
  557. DP_STATS_INC_PKT(vdev->pdev,
  558. tso_stats.tso_no_mem_dropped, 1,
  559. qdf_nbuf_len(msdu));
  560. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  561. return QDF_STATUS_E_NOMEM;
  562. }
  563. }
  564. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  565. tso_num_seg = dp_tso_num_seg_alloc(soc,
  566. msdu_info->tx_queue.desc_pool_id);
  567. if (tso_num_seg) {
  568. tso_num_seg->next = tso_info->tso_num_seg_list;
  569. tso_info->tso_num_seg_list = tso_num_seg;
  570. } else {
  571. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  572. __func__);
  573. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  574. return QDF_STATUS_E_NOMEM;
  575. }
  576. msdu_info->num_seg =
  577. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  578. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  579. msdu_info->num_seg);
  580. if (!(msdu_info->num_seg)) {
  581. /*
  582. * Free allocated TSO seg desc and number seg desc,
  583. * do unmap for segments if dma map has done.
  584. */
  585. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  586. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  587. return QDF_STATUS_E_INVAL;
  588. }
  589. tso_info->curr_seg = tso_info->tso_seg_list;
  590. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  591. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  592. msdu, msdu_info->num_seg);
  593. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  594. tso_info->msdu_stats_idx);
  595. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  596. return QDF_STATUS_SUCCESS;
  597. }
  598. #else
  599. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  600. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  601. {
  602. return QDF_STATUS_E_NOMEM;
  603. }
  604. #endif
  605. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  606. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  607. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  608. /**
  609. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  610. * @vdev: DP Vdev handle
  611. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  612. * @desc_pool_id: Descriptor Pool ID
  613. *
  614. * Return:
  615. */
  616. static
  617. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  618. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  619. {
  620. uint8_t i;
  621. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  622. struct dp_tx_seg_info_s *seg_info;
  623. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  624. struct dp_soc *soc = vdev->pdev->soc;
  625. /* Allocate an extension descriptor */
  626. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  627. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  628. if (!msdu_ext_desc) {
  629. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  630. return NULL;
  631. }
  632. if (msdu_info->exception_fw &&
  633. qdf_unlikely(vdev->mesh_vdev)) {
  634. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  635. &msdu_info->meta_data[0],
  636. sizeof(struct htt_tx_msdu_desc_ext2_t));
  637. qdf_atomic_inc(&soc->num_tx_exception);
  638. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  639. }
  640. switch (msdu_info->frm_type) {
  641. case dp_tx_frm_sg:
  642. case dp_tx_frm_me:
  643. case dp_tx_frm_raw:
  644. seg_info = msdu_info->u.sg_info.curr_seg;
  645. /* Update the buffer pointers in MSDU Extension Descriptor */
  646. for (i = 0; i < seg_info->frag_cnt; i++) {
  647. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  648. seg_info->frags[i].paddr_lo,
  649. seg_info->frags[i].paddr_hi,
  650. seg_info->frags[i].len);
  651. }
  652. break;
  653. case dp_tx_frm_tso:
  654. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  655. &cached_ext_desc[0]);
  656. break;
  657. default:
  658. break;
  659. }
  660. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  661. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  662. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  663. msdu_ext_desc->vaddr);
  664. return msdu_ext_desc;
  665. }
  666. /**
  667. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  668. *
  669. * @skb: skb to be traced
  670. * @msdu_id: msdu_id of the packet
  671. * @vdev_id: vdev_id of the packet
  672. *
  673. * Return: None
  674. */
  675. #ifdef DP_DISABLE_TX_PKT_TRACE
  676. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  677. uint8_t vdev_id)
  678. {
  679. }
  680. #else
  681. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  682. uint8_t vdev_id)
  683. {
  684. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  685. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  686. DPTRACE(qdf_dp_trace_ptr(skb,
  687. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  688. QDF_TRACE_DEFAULT_PDEV_ID,
  689. qdf_nbuf_data_addr(skb),
  690. sizeof(qdf_nbuf_data(skb)),
  691. msdu_id, vdev_id));
  692. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  693. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  694. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  695. msdu_id, QDF_TX));
  696. }
  697. #endif
  698. #ifdef QCA_SUPPORT_WDS_EXTENDED
  699. /**
  700. * dp_is_tx_extended() - Configure AST override from peer ast entry
  701. *
  702. * @vdev: DP vdev handle
  703. * @tx_exc_metadata: Handle that holds exception path metadata
  704. *
  705. * Return: if this packet needs to exception to FW or not
  706. * (false: exception to wlan FW, true: do not exception)
  707. */
  708. static inline bool
  709. dp_is_tx_extended(struct dp_vdev *vdev, struct cdp_tx_exception_metadata
  710. *tx_exc_metadata)
  711. {
  712. if (qdf_likely(!vdev->wds_ext_enabled))
  713. return false;
  714. if (tx_exc_metadata && !tx_exc_metadata->is_wds_extended)
  715. return false;
  716. return true;
  717. }
  718. /**
  719. * dp_tx_wds_ext() - Configure AST override from peer ast entry
  720. *
  721. * @soc: DP soc handle
  722. * @vdev: DP vdev handle
  723. * @peer_id: peer_id of the peer for which packet is destined
  724. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  725. *
  726. * Return: None
  727. */
  728. static inline void
  729. dp_tx_wds_ext(struct dp_soc *soc, struct dp_vdev *vdev, uint16_t peer_id,
  730. struct dp_tx_msdu_info_s *msdu_info)
  731. {
  732. struct dp_peer *peer = NULL;
  733. msdu_info->search_type = vdev->search_type;
  734. msdu_info->ast_idx = vdev->bss_ast_idx;
  735. msdu_info->ast_hash = vdev->bss_ast_hash;
  736. if (qdf_likely(!vdev->wds_ext_enabled))
  737. return;
  738. peer = dp_peer_get_ref_by_id(soc, peer_id, DP_MOD_ID_TX);
  739. if (qdf_unlikely(!peer))
  740. return;
  741. msdu_info->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  742. msdu_info->ast_idx = peer->self_ast_entry->ast_idx;
  743. msdu_info->ast_hash = peer->self_ast_entry->ast_hash_value;
  744. dp_peer_unref_delete(peer, DP_MOD_ID_TX);
  745. msdu_info->exception_fw = 0;
  746. }
  747. #else
  748. static inline bool
  749. dp_is_tx_extended(struct dp_vdev *vdev, struct cdp_tx_exception_metadata
  750. *tx_exc_metadata)
  751. {
  752. return false;
  753. }
  754. static inline void
  755. dp_tx_wds_ext(struct dp_soc *soc, struct dp_vdev *vdev, uint16_t peer_id,
  756. struct dp_tx_msdu_info_s *msdu_info)
  757. {
  758. msdu_info->search_type = vdev->search_type;
  759. msdu_info->ast_idx = vdev->bss_ast_idx;
  760. msdu_info->ast_hash = vdev->bss_ast_hash;
  761. }
  762. #endif
  763. /**
  764. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  765. * @vdev: DP vdev handle
  766. * @nbuf: skb
  767. * @desc_pool_id: Descriptor pool ID
  768. * @meta_data: Metadata to the fw
  769. * @tx_exc_metadata: Handle that holds exception path metadata
  770. * Allocate and prepare Tx descriptor with msdu information.
  771. *
  772. * Return: Pointer to Tx Descriptor on success,
  773. * NULL on failure
  774. */
  775. static
  776. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  777. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  778. struct dp_tx_msdu_info_s *msdu_info,
  779. struct cdp_tx_exception_metadata *tx_exc_metadata)
  780. {
  781. uint8_t align_pad;
  782. uint8_t is_exception = 0;
  783. uint8_t htt_hdr_size;
  784. struct dp_tx_desc_s *tx_desc;
  785. struct dp_pdev *pdev = vdev->pdev;
  786. struct dp_soc *soc = pdev->soc;
  787. if (dp_tx_limit_check(vdev))
  788. return NULL;
  789. /* Allocate software Tx descriptor */
  790. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  791. if (qdf_unlikely(!tx_desc)) {
  792. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  793. return NULL;
  794. }
  795. dp_tx_outstanding_inc(pdev);
  796. /* Initialize the SW tx descriptor */
  797. tx_desc->nbuf = nbuf;
  798. tx_desc->frm_type = dp_tx_frm_std;
  799. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  800. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  801. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  802. tx_desc->vdev_id = vdev->vdev_id;
  803. tx_desc->pdev = pdev;
  804. tx_desc->msdu_ext_desc = NULL;
  805. tx_desc->pkt_offset = 0;
  806. tx_desc->length = qdf_nbuf_headlen(nbuf);
  807. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  808. if (qdf_unlikely(vdev->multipass_en)) {
  809. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  810. goto failure;
  811. }
  812. if (qdf_unlikely(dp_is_tx_extended(vdev, tx_exc_metadata)))
  813. return tx_desc;
  814. /*
  815. * For special modes (vdev_type == ocb or mesh), data frames should be
  816. * transmitted using varying transmit parameters (tx spec) which include
  817. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  818. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  819. * These frames are sent as exception packets to firmware.
  820. *
  821. * HW requirement is that metadata should always point to a
  822. * 8-byte aligned address. So we add alignment pad to start of buffer.
  823. * HTT Metadata should be ensured to be multiple of 8-bytes,
  824. * to get 8-byte aligned start address along with align_pad added
  825. *
  826. * |-----------------------------|
  827. * | |
  828. * |-----------------------------| <-----Buffer Pointer Address given
  829. * | | ^ in HW descriptor (aligned)
  830. * | HTT Metadata | |
  831. * | | |
  832. * | | | Packet Offset given in descriptor
  833. * | | |
  834. * |-----------------------------| |
  835. * | Alignment Pad | v
  836. * |-----------------------------| <----- Actual buffer start address
  837. * | SKB Data | (Unaligned)
  838. * | |
  839. * | |
  840. * | |
  841. * | |
  842. * | |
  843. * |-----------------------------|
  844. */
  845. if (qdf_unlikely((msdu_info->exception_fw)) ||
  846. (vdev->opmode == wlan_op_mode_ocb) ||
  847. (tx_exc_metadata &&
  848. tx_exc_metadata->is_tx_sniffer)) {
  849. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  850. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  851. DP_STATS_INC(vdev,
  852. tx_i.dropped.headroom_insufficient, 1);
  853. goto failure;
  854. }
  855. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  856. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  857. "qdf_nbuf_push_head failed");
  858. goto failure;
  859. }
  860. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  861. msdu_info);
  862. if (htt_hdr_size == 0)
  863. goto failure;
  864. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  865. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  866. is_exception = 1;
  867. tx_desc->length -= tx_desc->pkt_offset;
  868. }
  869. #if !TQM_BYPASS_WAR
  870. if (is_exception || tx_exc_metadata)
  871. #endif
  872. {
  873. /* Temporary WAR due to TQM VP issues */
  874. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  875. qdf_atomic_inc(&soc->num_tx_exception);
  876. }
  877. return tx_desc;
  878. failure:
  879. dp_tx_desc_release(tx_desc, desc_pool_id);
  880. return NULL;
  881. }
  882. /**
  883. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  884. * @vdev: DP vdev handle
  885. * @nbuf: skb
  886. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  887. * @desc_pool_id : Descriptor Pool ID
  888. *
  889. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  890. * information. For frames wth fragments, allocate and prepare
  891. * an MSDU extension descriptor
  892. *
  893. * Return: Pointer to Tx Descriptor on success,
  894. * NULL on failure
  895. */
  896. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  897. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  898. uint8_t desc_pool_id)
  899. {
  900. struct dp_tx_desc_s *tx_desc;
  901. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  902. struct dp_pdev *pdev = vdev->pdev;
  903. struct dp_soc *soc = pdev->soc;
  904. if (dp_tx_limit_check(vdev))
  905. return NULL;
  906. /* Allocate software Tx descriptor */
  907. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  908. if (!tx_desc) {
  909. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  910. return NULL;
  911. }
  912. dp_tx_outstanding_inc(pdev);
  913. /* Initialize the SW tx descriptor */
  914. tx_desc->nbuf = nbuf;
  915. tx_desc->frm_type = msdu_info->frm_type;
  916. tx_desc->tx_encap_type = vdev->tx_encap_type;
  917. tx_desc->vdev_id = vdev->vdev_id;
  918. tx_desc->pdev = pdev;
  919. tx_desc->pkt_offset = 0;
  920. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  921. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  922. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  923. /* Handle scattered frames - TSO/SG/ME */
  924. /* Allocate and prepare an extension descriptor for scattered frames */
  925. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  926. if (!msdu_ext_desc) {
  927. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  928. "%s Tx Extension Descriptor Alloc Fail",
  929. __func__);
  930. goto failure;
  931. }
  932. #if TQM_BYPASS_WAR
  933. /* Temporary WAR due to TQM VP issues */
  934. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  935. qdf_atomic_inc(&soc->num_tx_exception);
  936. #endif
  937. if (qdf_unlikely(msdu_info->exception_fw))
  938. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  939. tx_desc->msdu_ext_desc = msdu_ext_desc;
  940. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  941. tx_desc->dma_addr = msdu_ext_desc->paddr;
  942. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  943. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  944. else
  945. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  946. return tx_desc;
  947. failure:
  948. dp_tx_desc_release(tx_desc, desc_pool_id);
  949. return NULL;
  950. }
  951. /**
  952. * dp_tx_prepare_raw() - Prepare RAW packet TX
  953. * @vdev: DP vdev handle
  954. * @nbuf: buffer pointer
  955. * @seg_info: Pointer to Segment info Descriptor to be prepared
  956. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  957. * descriptor
  958. *
  959. * Return:
  960. */
  961. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  962. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  963. {
  964. qdf_nbuf_t curr_nbuf = NULL;
  965. uint16_t total_len = 0;
  966. qdf_dma_addr_t paddr;
  967. int32_t i;
  968. int32_t mapped_buf_num = 0;
  969. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  970. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  971. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  972. /* Continue only if frames are of DATA type */
  973. if (!DP_FRAME_IS_DATA(qos_wh)) {
  974. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  975. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  976. "Pkt. recd is of not data type");
  977. goto error;
  978. }
  979. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  980. if (vdev->raw_mode_war &&
  981. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  982. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  983. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  984. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  985. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  986. /*
  987. * Number of nbuf's must not exceed the size of the frags
  988. * array in seg_info.
  989. */
  990. if (i >= DP_TX_MAX_NUM_FRAGS) {
  991. dp_err_rl("nbuf cnt exceeds the max number of segs");
  992. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  993. goto error;
  994. }
  995. if (QDF_STATUS_SUCCESS !=
  996. qdf_nbuf_map_nbytes_single(vdev->osdev,
  997. curr_nbuf,
  998. QDF_DMA_TO_DEVICE,
  999. curr_nbuf->len)) {
  1000. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1001. "%s dma map error ", __func__);
  1002. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1003. goto error;
  1004. }
  1005. /* Update the count of mapped nbuf's */
  1006. mapped_buf_num++;
  1007. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1008. seg_info->frags[i].paddr_lo = paddr;
  1009. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1010. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1011. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1012. total_len += qdf_nbuf_len(curr_nbuf);
  1013. }
  1014. seg_info->frag_cnt = i;
  1015. seg_info->total_len = total_len;
  1016. seg_info->next = NULL;
  1017. sg_info->curr_seg = seg_info;
  1018. msdu_info->frm_type = dp_tx_frm_raw;
  1019. msdu_info->num_seg = 1;
  1020. return nbuf;
  1021. error:
  1022. i = 0;
  1023. while (nbuf) {
  1024. curr_nbuf = nbuf;
  1025. if (i < mapped_buf_num) {
  1026. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1027. QDF_DMA_TO_DEVICE,
  1028. curr_nbuf->len);
  1029. i++;
  1030. }
  1031. nbuf = qdf_nbuf_next(nbuf);
  1032. qdf_nbuf_free(curr_nbuf);
  1033. }
  1034. return NULL;
  1035. }
  1036. /**
  1037. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1038. * @soc: DP soc handle
  1039. * @nbuf: Buffer pointer
  1040. *
  1041. * unmap the chain of nbufs that belong to this RAW frame.
  1042. *
  1043. * Return: None
  1044. */
  1045. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1046. qdf_nbuf_t nbuf)
  1047. {
  1048. qdf_nbuf_t cur_nbuf = nbuf;
  1049. do {
  1050. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1051. QDF_DMA_TO_DEVICE,
  1052. cur_nbuf->len);
  1053. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1054. } while (cur_nbuf);
  1055. }
  1056. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1057. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, nbuf) \
  1058. { \
  1059. qdf_nbuf_t nbuf_local; \
  1060. struct dp_vdev *vdev_local = vdev_hdl; \
  1061. do { \
  1062. if (qdf_likely(!((vdev_local)->peer_protocol_count_track))) \
  1063. break; \
  1064. nbuf_local = nbuf; \
  1065. if (qdf_unlikely(((vdev_local)->tx_encap_type) == \
  1066. htt_cmn_pkt_type_raw)) \
  1067. break; \
  1068. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local)))) \
  1069. break; \
  1070. else if (qdf_nbuf_is_tso((nbuf_local))) \
  1071. break; \
  1072. dp_vdev_peer_stats_update_protocol_cnt((vdev_local), \
  1073. (nbuf_local), \
  1074. NULL, 1, 0); \
  1075. } while (0); \
  1076. }
  1077. #else
  1078. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, skb)
  1079. #endif
  1080. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1081. /**
  1082. * dp_tx_update_stats() - Update soc level tx stats
  1083. * @soc: DP soc handle
  1084. * @nbuf: packet being transmitted
  1085. *
  1086. * Returns: none
  1087. */
  1088. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1089. qdf_nbuf_t nbuf)
  1090. {
  1091. DP_STATS_INC_PKT(soc, tx.egress, 1, qdf_nbuf_len(nbuf));
  1092. }
  1093. /**
  1094. * dp_tx_attempt_coalescing() - Check and attempt TCL register write coalescing
  1095. * @soc: Datapath soc handle
  1096. * @tx_desc: tx packet descriptor
  1097. * @tid: TID for pkt transmission
  1098. *
  1099. * Returns: 1, if coalescing is to be done
  1100. * 0, if coalescing is not to be done
  1101. */
  1102. static inline int
  1103. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1104. struct dp_tx_desc_s *tx_desc,
  1105. uint8_t tid)
  1106. {
  1107. struct dp_swlm *swlm = &soc->swlm;
  1108. union swlm_data swlm_query_data;
  1109. struct dp_swlm_tcl_data tcl_data;
  1110. QDF_STATUS status;
  1111. int ret;
  1112. if (qdf_unlikely(!swlm->is_enabled))
  1113. return 0;
  1114. tcl_data.nbuf = tx_desc->nbuf;
  1115. tcl_data.tid = tid;
  1116. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1117. swlm_query_data.tcl_data = &tcl_data;
  1118. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1119. if (QDF_IS_STATUS_ERROR(status)) {
  1120. dp_swlm_tcl_reset_session_data(soc);
  1121. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1122. return 0;
  1123. }
  1124. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1125. if (ret) {
  1126. DP_STATS_INC(swlm, tcl.coalesce_success, 1);
  1127. } else {
  1128. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1129. }
  1130. return ret;
  1131. }
  1132. /**
  1133. * dp_tx_ring_access_end() - HAL ring access end for data transmission
  1134. * @soc: Datapath soc handle
  1135. * @hal_ring_hdl: HAL ring handle
  1136. * @coalesce: Coalesce the current write or not
  1137. *
  1138. * Returns: none
  1139. */
  1140. static inline void
  1141. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1142. int coalesce)
  1143. {
  1144. if (coalesce)
  1145. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1146. else
  1147. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1148. }
  1149. #else
  1150. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1151. qdf_nbuf_t nbuf)
  1152. {
  1153. }
  1154. static inline int
  1155. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1156. struct dp_tx_desc_s *tx_desc,
  1157. uint8_t tid)
  1158. {
  1159. return 0;
  1160. }
  1161. static inline void
  1162. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1163. int coalesce)
  1164. {
  1165. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1166. }
  1167. #endif
  1168. /**
  1169. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  1170. * @soc: DP Soc Handle
  1171. * @vdev: DP vdev handle
  1172. * @tx_desc: Tx Descriptor Handle
  1173. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1174. * @fw_metadata: Metadata to send to Target Firmware along with frame
  1175. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  1176. * @tx_exc_metadata: Handle that holds exception path meta data
  1177. *
  1178. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  1179. * from software Tx descriptor
  1180. *
  1181. * Return: QDF_STATUS_SUCCESS: success
  1182. * QDF_STATUS_E_RESOURCES: Error return
  1183. */
  1184. static QDF_STATUS
  1185. dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  1186. struct dp_tx_desc_s *tx_desc, uint16_t fw_metadata,
  1187. struct cdp_tx_exception_metadata *tx_exc_metadata,
  1188. struct dp_tx_msdu_info_s *msdu_info)
  1189. {
  1190. void *hal_tx_desc;
  1191. uint32_t *hal_tx_desc_cached;
  1192. int coalesce = 0;
  1193. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1194. uint8_t ring_id = tx_q->ring_id & DP_TX_QUEUE_MASK;
  1195. uint8_t tid = msdu_info->tid;
  1196. /*
  1197. * Setting it initialization statically here to avoid
  1198. * a memset call jump with qdf_mem_set call
  1199. */
  1200. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1201. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  1202. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  1203. tx_exc_metadata->sec_type : vdev->sec_type);
  1204. /* Return Buffer Manager ID */
  1205. uint8_t bm_id = dp_tx_get_rbm_id(soc, ring_id);
  1206. hal_ring_handle_t hal_ring_hdl = NULL;
  1207. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1208. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  1209. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1210. return QDF_STATUS_E_RESOURCES;
  1211. }
  1212. hal_tx_desc_cached = (void *) cached_desc;
  1213. hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
  1214. tx_desc->dma_addr, bm_id, tx_desc->id,
  1215. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG));
  1216. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  1217. vdev->lmac_id);
  1218. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  1219. msdu_info->search_type);
  1220. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  1221. msdu_info->ast_idx);
  1222. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  1223. vdev->dscp_tid_map_id);
  1224. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  1225. sec_type_map[sec_type]);
  1226. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1227. (msdu_info->ast_hash & 0xF));
  1228. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1229. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  1230. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1231. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  1232. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  1233. vdev->hal_desc_addr_search_flags);
  1234. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1235. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1236. /* verify checksum offload configuration*/
  1237. if (vdev->csum_enabled &&
  1238. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  1239. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  1240. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1241. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1242. }
  1243. if (tid != HTT_TX_EXT_TID_INVALID)
  1244. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1245. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  1246. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  1247. if (qdf_unlikely(vdev->pdev->delay_stats_flag) ||
  1248. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  1249. soc->wlan_cfg_ctx)))
  1250. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  1251. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  1252. tx_desc->length,
  1253. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG),
  1254. (uint64_t)tx_desc->dma_addr, tx_desc->pkt_offset,
  1255. tx_desc->id);
  1256. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  1257. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1258. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1259. "%s %d : HAL RING Access Failed -- %pK",
  1260. __func__, __LINE__, hal_ring_hdl);
  1261. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1262. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1263. return status;
  1264. }
  1265. /* Sync cached descriptor with HW */
  1266. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1267. if (qdf_unlikely(!hal_tx_desc)) {
  1268. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1269. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1270. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1271. goto ring_access_fail;
  1272. }
  1273. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1274. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1275. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  1276. coalesce = dp_tx_attempt_coalescing(soc, vdev, tx_desc, tid);
  1277. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
  1278. dp_tx_update_stats(soc, tx_desc->nbuf);
  1279. status = QDF_STATUS_SUCCESS;
  1280. ring_access_fail:
  1281. if (hif_pm_runtime_get(soc->hif_handle,
  1282. RTPM_ID_DW_TX_HW_ENQUEUE) == 0) {
  1283. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1284. hif_pm_runtime_put(soc->hif_handle,
  1285. RTPM_ID_DW_TX_HW_ENQUEUE);
  1286. } else {
  1287. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1288. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1289. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1290. }
  1291. return status;
  1292. }
  1293. /**
  1294. * dp_cce_classify() - Classify the frame based on CCE rules
  1295. * @vdev: DP vdev handle
  1296. * @nbuf: skb
  1297. *
  1298. * Classify frames based on CCE rules
  1299. * Return: bool( true if classified,
  1300. * else false)
  1301. */
  1302. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1303. {
  1304. qdf_ether_header_t *eh = NULL;
  1305. uint16_t ether_type;
  1306. qdf_llc_t *llcHdr;
  1307. qdf_nbuf_t nbuf_clone = NULL;
  1308. qdf_dot3_qosframe_t *qos_wh = NULL;
  1309. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1310. /*
  1311. * In case of mesh packets or hlos tid override enabled,
  1312. * don't do any classification
  1313. */
  1314. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1315. & DP_TX_SKIP_CCE_CLASSIFY))
  1316. return false;
  1317. }
  1318. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1319. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1320. ether_type = eh->ether_type;
  1321. llcHdr = (qdf_llc_t *)(nbuf->data +
  1322. sizeof(qdf_ether_header_t));
  1323. } else {
  1324. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1325. /* For encrypted packets don't do any classification */
  1326. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1327. return false;
  1328. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1329. if (qdf_unlikely(
  1330. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1331. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1332. ether_type = *(uint16_t *)(nbuf->data
  1333. + QDF_IEEE80211_4ADDR_HDR_LEN
  1334. + sizeof(qdf_llc_t)
  1335. - sizeof(ether_type));
  1336. llcHdr = (qdf_llc_t *)(nbuf->data +
  1337. QDF_IEEE80211_4ADDR_HDR_LEN);
  1338. } else {
  1339. ether_type = *(uint16_t *)(nbuf->data
  1340. + QDF_IEEE80211_3ADDR_HDR_LEN
  1341. + sizeof(qdf_llc_t)
  1342. - sizeof(ether_type));
  1343. llcHdr = (qdf_llc_t *)(nbuf->data +
  1344. QDF_IEEE80211_3ADDR_HDR_LEN);
  1345. }
  1346. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1347. && (ether_type ==
  1348. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1349. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1350. return true;
  1351. }
  1352. }
  1353. return false;
  1354. }
  1355. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1356. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1357. sizeof(*llcHdr));
  1358. nbuf_clone = qdf_nbuf_clone(nbuf);
  1359. if (qdf_unlikely(nbuf_clone)) {
  1360. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1361. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1362. qdf_nbuf_pull_head(nbuf_clone,
  1363. sizeof(qdf_net_vlanhdr_t));
  1364. }
  1365. }
  1366. } else {
  1367. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1368. nbuf_clone = qdf_nbuf_clone(nbuf);
  1369. if (qdf_unlikely(nbuf_clone)) {
  1370. qdf_nbuf_pull_head(nbuf_clone,
  1371. sizeof(qdf_net_vlanhdr_t));
  1372. }
  1373. }
  1374. }
  1375. if (qdf_unlikely(nbuf_clone))
  1376. nbuf = nbuf_clone;
  1377. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1378. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1379. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1380. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1381. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1382. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1383. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1384. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1385. if (qdf_unlikely(nbuf_clone))
  1386. qdf_nbuf_free(nbuf_clone);
  1387. return true;
  1388. }
  1389. if (qdf_unlikely(nbuf_clone))
  1390. qdf_nbuf_free(nbuf_clone);
  1391. return false;
  1392. }
  1393. /**
  1394. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1395. * @vdev: DP vdev handle
  1396. * @nbuf: skb
  1397. *
  1398. * Extract the DSCP or PCP information from frame and map into TID value.
  1399. *
  1400. * Return: void
  1401. */
  1402. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1403. struct dp_tx_msdu_info_s *msdu_info)
  1404. {
  1405. uint8_t tos = 0, dscp_tid_override = 0;
  1406. uint8_t *hdr_ptr, *L3datap;
  1407. uint8_t is_mcast = 0;
  1408. qdf_ether_header_t *eh = NULL;
  1409. qdf_ethervlan_header_t *evh = NULL;
  1410. uint16_t ether_type;
  1411. qdf_llc_t *llcHdr;
  1412. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1413. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1414. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1415. eh = (qdf_ether_header_t *)nbuf->data;
  1416. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1417. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1418. } else {
  1419. qdf_dot3_qosframe_t *qos_wh =
  1420. (qdf_dot3_qosframe_t *) nbuf->data;
  1421. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1422. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1423. return;
  1424. }
  1425. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1426. ether_type = eh->ether_type;
  1427. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1428. /*
  1429. * Check if packet is dot3 or eth2 type.
  1430. */
  1431. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1432. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1433. sizeof(*llcHdr));
  1434. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1435. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1436. sizeof(*llcHdr);
  1437. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1438. + sizeof(*llcHdr) +
  1439. sizeof(qdf_net_vlanhdr_t));
  1440. } else {
  1441. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1442. sizeof(*llcHdr);
  1443. }
  1444. } else {
  1445. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1446. evh = (qdf_ethervlan_header_t *) eh;
  1447. ether_type = evh->ether_type;
  1448. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1449. }
  1450. }
  1451. /*
  1452. * Find priority from IP TOS DSCP field
  1453. */
  1454. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1455. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1456. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1457. /* Only for unicast frames */
  1458. if (!is_mcast) {
  1459. /* send it on VO queue */
  1460. msdu_info->tid = DP_VO_TID;
  1461. }
  1462. } else {
  1463. /*
  1464. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1465. * from TOS byte.
  1466. */
  1467. tos = ip->ip_tos;
  1468. dscp_tid_override = 1;
  1469. }
  1470. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1471. /* TODO
  1472. * use flowlabel
  1473. *igmpmld cases to be handled in phase 2
  1474. */
  1475. unsigned long ver_pri_flowlabel;
  1476. unsigned long pri;
  1477. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1478. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1479. DP_IPV6_PRIORITY_SHIFT;
  1480. tos = pri;
  1481. dscp_tid_override = 1;
  1482. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1483. msdu_info->tid = DP_VO_TID;
  1484. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1485. /* Only for unicast frames */
  1486. if (!is_mcast) {
  1487. /* send ucast arp on VO queue */
  1488. msdu_info->tid = DP_VO_TID;
  1489. }
  1490. }
  1491. /*
  1492. * Assign all MCAST packets to BE
  1493. */
  1494. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1495. if (is_mcast) {
  1496. tos = 0;
  1497. dscp_tid_override = 1;
  1498. }
  1499. }
  1500. if (dscp_tid_override == 1) {
  1501. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1502. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1503. }
  1504. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1505. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1506. return;
  1507. }
  1508. /**
  1509. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1510. * @vdev: DP vdev handle
  1511. * @nbuf: skb
  1512. *
  1513. * Software based TID classification is required when more than 2 DSCP-TID
  1514. * mapping tables are needed.
  1515. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1516. *
  1517. * Return: void
  1518. */
  1519. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1520. struct dp_tx_msdu_info_s *msdu_info)
  1521. {
  1522. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1523. /*
  1524. * skip_sw_tid_classification flag will set in below cases-
  1525. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1526. * 2. hlos_tid_override enabled for vdev
  1527. * 3. mesh mode enabled for vdev
  1528. */
  1529. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1530. /* Update tid in msdu_info from skb priority */
  1531. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1532. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1533. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1534. return;
  1535. }
  1536. return;
  1537. }
  1538. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1539. }
  1540. #ifdef FEATURE_WLAN_TDLS
  1541. /**
  1542. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1543. * @soc: datapath SOC
  1544. * @vdev: datapath vdev
  1545. * @tx_desc: TX descriptor
  1546. *
  1547. * Return: None
  1548. */
  1549. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1550. struct dp_vdev *vdev,
  1551. struct dp_tx_desc_s *tx_desc)
  1552. {
  1553. if (vdev) {
  1554. if (vdev->is_tdls_frame) {
  1555. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1556. vdev->is_tdls_frame = false;
  1557. }
  1558. }
  1559. }
  1560. /**
  1561. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1562. * @soc: dp_soc handle
  1563. * @tx_desc: TX descriptor
  1564. * @vdev: datapath vdev handle
  1565. *
  1566. * Return: None
  1567. */
  1568. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1569. struct dp_tx_desc_s *tx_desc)
  1570. {
  1571. struct hal_tx_completion_status ts = {0};
  1572. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1573. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1574. DP_MOD_ID_TDLS);
  1575. if (qdf_unlikely(!vdev)) {
  1576. dp_err_rl("vdev is null!");
  1577. goto error;
  1578. }
  1579. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1580. if (vdev->tx_non_std_data_callback.func) {
  1581. qdf_nbuf_set_next(nbuf, NULL);
  1582. vdev->tx_non_std_data_callback.func(
  1583. vdev->tx_non_std_data_callback.ctxt,
  1584. nbuf, ts.status);
  1585. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1586. return;
  1587. } else {
  1588. dp_err_rl("callback func is null");
  1589. }
  1590. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1591. error:
  1592. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1593. qdf_nbuf_free(nbuf);
  1594. }
  1595. /**
  1596. * dp_tx_msdu_single_map() - do nbuf map
  1597. * @vdev: DP vdev handle
  1598. * @tx_desc: DP TX descriptor pointer
  1599. * @nbuf: skb pointer
  1600. *
  1601. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1602. * operation done in other component.
  1603. *
  1604. * Return: QDF_STATUS
  1605. */
  1606. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1607. struct dp_tx_desc_s *tx_desc,
  1608. qdf_nbuf_t nbuf)
  1609. {
  1610. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1611. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1612. nbuf,
  1613. QDF_DMA_TO_DEVICE,
  1614. nbuf->len);
  1615. else
  1616. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1617. QDF_DMA_TO_DEVICE);
  1618. }
  1619. #else
  1620. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1621. struct dp_vdev *vdev,
  1622. struct dp_tx_desc_s *tx_desc)
  1623. {
  1624. }
  1625. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1626. struct dp_tx_desc_s *tx_desc)
  1627. {
  1628. }
  1629. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1630. struct dp_tx_desc_s *tx_desc,
  1631. qdf_nbuf_t nbuf)
  1632. {
  1633. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1634. nbuf,
  1635. QDF_DMA_TO_DEVICE,
  1636. nbuf->len);
  1637. }
  1638. #endif
  1639. #ifdef MESH_MODE_SUPPORT
  1640. /**
  1641. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1642. * @soc: datapath SOC
  1643. * @vdev: datapath vdev
  1644. * @tx_desc: TX descriptor
  1645. *
  1646. * Return: None
  1647. */
  1648. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1649. struct dp_vdev *vdev,
  1650. struct dp_tx_desc_s *tx_desc)
  1651. {
  1652. if (qdf_unlikely(vdev->mesh_vdev))
  1653. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1654. }
  1655. /**
  1656. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1657. * @soc: dp_soc handle
  1658. * @tx_desc: TX descriptor
  1659. * @vdev: datapath vdev handle
  1660. *
  1661. * Return: None
  1662. */
  1663. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1664. struct dp_tx_desc_s *tx_desc)
  1665. {
  1666. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1667. struct dp_vdev *vdev = NULL;
  1668. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1669. qdf_nbuf_free(nbuf);
  1670. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1671. } else {
  1672. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1673. DP_MOD_ID_MESH);
  1674. if (vdev && vdev->osif_tx_free_ext)
  1675. vdev->osif_tx_free_ext((nbuf));
  1676. else
  1677. qdf_nbuf_free(nbuf);
  1678. if (vdev)
  1679. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1680. }
  1681. }
  1682. #else
  1683. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1684. struct dp_vdev *vdev,
  1685. struct dp_tx_desc_s *tx_desc)
  1686. {
  1687. }
  1688. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1689. struct dp_tx_desc_s *tx_desc)
  1690. {
  1691. }
  1692. #endif
  1693. /**
  1694. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1695. * @vdev: DP vdev handle
  1696. * @nbuf: skb
  1697. *
  1698. * Return: 1 if frame needs to be dropped else 0
  1699. */
  1700. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1701. {
  1702. struct dp_pdev *pdev = NULL;
  1703. struct dp_ast_entry *src_ast_entry = NULL;
  1704. struct dp_ast_entry *dst_ast_entry = NULL;
  1705. struct dp_soc *soc = NULL;
  1706. qdf_assert(vdev);
  1707. pdev = vdev->pdev;
  1708. qdf_assert(pdev);
  1709. soc = pdev->soc;
  1710. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1711. (soc, dstmac, vdev->pdev->pdev_id);
  1712. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1713. (soc, srcmac, vdev->pdev->pdev_id);
  1714. if (dst_ast_entry && src_ast_entry) {
  1715. if (dst_ast_entry->peer_id ==
  1716. src_ast_entry->peer_id)
  1717. return 1;
  1718. }
  1719. return 0;
  1720. }
  1721. /**
  1722. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1723. * @vdev: DP vdev handle
  1724. * @nbuf: skb
  1725. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1726. * @meta_data: Metadata to the fw
  1727. * @tx_q: Tx queue to be used for this Tx frame
  1728. * @peer_id: peer_id of the peer in case of NAWDS frames
  1729. * @tx_exc_metadata: Handle that holds exception path metadata
  1730. *
  1731. * Return: NULL on success,
  1732. * nbuf when it fails to send
  1733. */
  1734. qdf_nbuf_t
  1735. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1736. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1737. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1738. {
  1739. struct dp_pdev *pdev = vdev->pdev;
  1740. struct dp_soc *soc = pdev->soc;
  1741. struct dp_tx_desc_s *tx_desc;
  1742. QDF_STATUS status;
  1743. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1744. uint16_t htt_tcl_metadata = 0;
  1745. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1746. uint8_t tid = msdu_info->tid;
  1747. struct cdp_tid_tx_stats *tid_stats = NULL;
  1748. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1749. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1750. msdu_info, tx_exc_metadata);
  1751. if (!tx_desc) {
  1752. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1753. vdev, tx_q->desc_pool_id);
  1754. drop_code = TX_DESC_ERR;
  1755. goto fail_return;
  1756. }
  1757. if (qdf_unlikely(soc->cce_disable)) {
  1758. if (dp_cce_classify(vdev, nbuf) == true) {
  1759. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1760. tid = DP_VO_TID;
  1761. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1762. }
  1763. }
  1764. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1765. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1766. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1767. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1768. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1769. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1770. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1771. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1772. peer_id);
  1773. } else
  1774. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1775. if (msdu_info->exception_fw)
  1776. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1777. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1778. !pdev->enhanced_stats_en);
  1779. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1780. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1781. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1782. /* Handle failure */
  1783. dp_err("qdf_nbuf_map failed");
  1784. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1785. drop_code = TX_DMA_MAP_ERR;
  1786. goto release_desc;
  1787. }
  1788. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1789. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1790. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, htt_tcl_metadata,
  1791. tx_exc_metadata, msdu_info);
  1792. if (status != QDF_STATUS_SUCCESS) {
  1793. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1794. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1795. __func__, tx_desc, tx_q->ring_id);
  1796. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1797. QDF_DMA_TO_DEVICE,
  1798. nbuf->len);
  1799. drop_code = TX_HW_ENQUEUE;
  1800. goto release_desc;
  1801. }
  1802. return NULL;
  1803. release_desc:
  1804. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1805. fail_return:
  1806. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1807. tid_stats = &pdev->stats.tid_stats.
  1808. tid_tx_stats[tx_q->ring_id][tid];
  1809. tid_stats->swdrop_cnt[drop_code]++;
  1810. return nbuf;
  1811. }
  1812. /**
  1813. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1814. * @soc: Soc handle
  1815. * @desc: software Tx descriptor to be processed
  1816. *
  1817. * Return: none
  1818. */
  1819. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1820. struct dp_tx_desc_s *desc)
  1821. {
  1822. qdf_nbuf_t nbuf = desc->nbuf;
  1823. /* nbuf already freed in vdev detach path */
  1824. if (!nbuf)
  1825. return;
  1826. /* If it is TDLS mgmt, don't unmap or free the frame */
  1827. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1828. return dp_non_std_tx_comp_free_buff(soc, desc);
  1829. /* 0 : MSDU buffer, 1 : MLE */
  1830. if (desc->msdu_ext_desc) {
  1831. /* TSO free */
  1832. if (hal_tx_ext_desc_get_tso_enable(
  1833. desc->msdu_ext_desc->vaddr)) {
  1834. /* unmap eash TSO seg before free the nbuf */
  1835. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  1836. desc->tso_num_desc);
  1837. qdf_nbuf_free(nbuf);
  1838. return;
  1839. }
  1840. }
  1841. /* If it's ME frame, dont unmap the cloned nbuf's */
  1842. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  1843. goto nbuf_free;
  1844. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  1845. QDF_DMA_TO_DEVICE, nbuf->len);
  1846. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  1847. return dp_mesh_tx_comp_free_buff(soc, desc);
  1848. nbuf_free:
  1849. qdf_nbuf_free(nbuf);
  1850. }
  1851. /**
  1852. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1853. * @vdev: DP vdev handle
  1854. * @nbuf: skb
  1855. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1856. *
  1857. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1858. *
  1859. * Return: NULL on success,
  1860. * nbuf when it fails to send
  1861. */
  1862. #if QDF_LOCK_STATS
  1863. noinline
  1864. #else
  1865. #endif
  1866. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1867. struct dp_tx_msdu_info_s *msdu_info)
  1868. {
  1869. uint32_t i;
  1870. struct dp_pdev *pdev = vdev->pdev;
  1871. struct dp_soc *soc = pdev->soc;
  1872. struct dp_tx_desc_s *tx_desc;
  1873. bool is_cce_classified = false;
  1874. QDF_STATUS status;
  1875. uint16_t htt_tcl_metadata = 0;
  1876. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1877. struct cdp_tid_tx_stats *tid_stats = NULL;
  1878. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  1879. if (qdf_unlikely(soc->cce_disable)) {
  1880. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1881. if (is_cce_classified) {
  1882. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1883. msdu_info->tid = DP_VO_TID;
  1884. }
  1885. }
  1886. if (msdu_info->frm_type == dp_tx_frm_me)
  1887. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1888. i = 0;
  1889. /* Print statement to track i and num_seg */
  1890. /*
  1891. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1892. * descriptors using information in msdu_info
  1893. */
  1894. while (i < msdu_info->num_seg) {
  1895. /*
  1896. * Setup Tx descriptor for an MSDU, and MSDU extension
  1897. * descriptor
  1898. */
  1899. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1900. tx_q->desc_pool_id);
  1901. if (!tx_desc) {
  1902. if (msdu_info->frm_type == dp_tx_frm_me) {
  1903. prep_desc_fail++;
  1904. dp_tx_me_free_buf(pdev,
  1905. (void *)(msdu_info->u.sg_info
  1906. .curr_seg->frags[0].vaddr));
  1907. if (prep_desc_fail == msdu_info->num_seg) {
  1908. /*
  1909. * Unmap is needed only if descriptor
  1910. * preparation failed for all segments.
  1911. */
  1912. qdf_nbuf_unmap(soc->osdev,
  1913. msdu_info->u.sg_info.
  1914. curr_seg->nbuf,
  1915. QDF_DMA_TO_DEVICE);
  1916. }
  1917. /*
  1918. * Free the nbuf for the current segment
  1919. * and make it point to the next in the list.
  1920. * For me, there are as many segments as there
  1921. * are no of clients.
  1922. */
  1923. qdf_nbuf_free(msdu_info->u.sg_info
  1924. .curr_seg->nbuf);
  1925. if (msdu_info->u.sg_info.curr_seg->next) {
  1926. msdu_info->u.sg_info.curr_seg =
  1927. msdu_info->u.sg_info
  1928. .curr_seg->next;
  1929. nbuf = msdu_info->u.sg_info
  1930. .curr_seg->nbuf;
  1931. }
  1932. i++;
  1933. continue;
  1934. }
  1935. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1936. dp_tx_tso_unmap_segment(soc,
  1937. msdu_info->u.tso_info.
  1938. curr_seg,
  1939. msdu_info->u.tso_info.
  1940. tso_num_seg_list);
  1941. if (msdu_info->u.tso_info.curr_seg->next) {
  1942. msdu_info->u.tso_info.curr_seg =
  1943. msdu_info->u.tso_info.curr_seg->next;
  1944. i++;
  1945. continue;
  1946. }
  1947. }
  1948. goto done;
  1949. }
  1950. if (msdu_info->frm_type == dp_tx_frm_me) {
  1951. tx_desc->me_buffer =
  1952. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1953. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1954. }
  1955. if (is_cce_classified)
  1956. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1957. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1958. if (msdu_info->exception_fw) {
  1959. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1960. }
  1961. /*
  1962. * For frames with multiple segments (TSO, ME), jump to next
  1963. * segment.
  1964. */
  1965. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1966. if (msdu_info->u.tso_info.curr_seg->next) {
  1967. msdu_info->u.tso_info.curr_seg =
  1968. msdu_info->u.tso_info.curr_seg->next;
  1969. /*
  1970. * If this is a jumbo nbuf, then increment the
  1971. * number of nbuf users for each additional
  1972. * segment of the msdu. This will ensure that
  1973. * the skb is freed only after receiving tx
  1974. * completion for all segments of an nbuf
  1975. */
  1976. qdf_nbuf_inc_users(nbuf);
  1977. /* Check with MCL if this is needed */
  1978. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  1979. */
  1980. }
  1981. }
  1982. /*
  1983. * Enqueue the Tx MSDU descriptor to HW for transmit
  1984. */
  1985. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, htt_tcl_metadata,
  1986. NULL, msdu_info);
  1987. if (status != QDF_STATUS_SUCCESS) {
  1988. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1989. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1990. __func__, tx_desc, tx_q->ring_id);
  1991. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1992. tid_stats = &pdev->stats.tid_stats.
  1993. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1994. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1995. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1996. if (msdu_info->frm_type == dp_tx_frm_me) {
  1997. hw_enq_fail++;
  1998. if (hw_enq_fail == msdu_info->num_seg) {
  1999. /*
  2000. * Unmap is needed only if enqueue
  2001. * failed for all segments.
  2002. */
  2003. qdf_nbuf_unmap(soc->osdev,
  2004. msdu_info->u.sg_info.
  2005. curr_seg->nbuf,
  2006. QDF_DMA_TO_DEVICE);
  2007. }
  2008. /*
  2009. * Free the nbuf for the current segment
  2010. * and make it point to the next in the list.
  2011. * For me, there are as many segments as there
  2012. * are no of clients.
  2013. */
  2014. qdf_nbuf_free(msdu_info->u.sg_info
  2015. .curr_seg->nbuf);
  2016. if (msdu_info->u.sg_info.curr_seg->next) {
  2017. msdu_info->u.sg_info.curr_seg =
  2018. msdu_info->u.sg_info
  2019. .curr_seg->next;
  2020. nbuf = msdu_info->u.sg_info
  2021. .curr_seg->nbuf;
  2022. }
  2023. i++;
  2024. continue;
  2025. }
  2026. /*
  2027. * For TSO frames, the nbuf users increment done for
  2028. * the current segment has to be reverted, since the
  2029. * hw enqueue for this segment failed
  2030. */
  2031. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2032. msdu_info->u.tso_info.curr_seg) {
  2033. /*
  2034. * unmap and free current,
  2035. * retransmit remaining segments
  2036. */
  2037. dp_tx_comp_free_buf(soc, tx_desc);
  2038. i++;
  2039. continue;
  2040. }
  2041. goto done;
  2042. }
  2043. /*
  2044. * TODO
  2045. * if tso_info structure can be modified to have curr_seg
  2046. * as first element, following 2 blocks of code (for TSO and SG)
  2047. * can be combined into 1
  2048. */
  2049. /*
  2050. * For Multicast-Unicast converted packets,
  2051. * each converted frame (for a client) is represented as
  2052. * 1 segment
  2053. */
  2054. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2055. (msdu_info->frm_type == dp_tx_frm_me)) {
  2056. if (msdu_info->u.sg_info.curr_seg->next) {
  2057. msdu_info->u.sg_info.curr_seg =
  2058. msdu_info->u.sg_info.curr_seg->next;
  2059. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2060. }
  2061. }
  2062. i++;
  2063. }
  2064. nbuf = NULL;
  2065. done:
  2066. return nbuf;
  2067. }
  2068. /**
  2069. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2070. * for SG frames
  2071. * @vdev: DP vdev handle
  2072. * @nbuf: skb
  2073. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2074. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2075. *
  2076. * Return: NULL on success,
  2077. * nbuf when it fails to send
  2078. */
  2079. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2080. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2081. {
  2082. uint32_t cur_frag, nr_frags, i;
  2083. qdf_dma_addr_t paddr;
  2084. struct dp_tx_sg_info_s *sg_info;
  2085. sg_info = &msdu_info->u.sg_info;
  2086. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2087. if (QDF_STATUS_SUCCESS !=
  2088. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2089. QDF_DMA_TO_DEVICE,
  2090. qdf_nbuf_headlen(nbuf))) {
  2091. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2092. "dma map error");
  2093. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2094. qdf_nbuf_free(nbuf);
  2095. return NULL;
  2096. }
  2097. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2098. seg_info->frags[0].paddr_lo = paddr;
  2099. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2100. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2101. seg_info->frags[0].vaddr = (void *) nbuf;
  2102. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2103. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  2104. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  2105. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2106. "frag dma map error");
  2107. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2108. goto map_err;
  2109. }
  2110. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2111. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2112. seg_info->frags[cur_frag + 1].paddr_hi =
  2113. ((uint64_t) paddr) >> 32;
  2114. seg_info->frags[cur_frag + 1].len =
  2115. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2116. }
  2117. seg_info->frag_cnt = (cur_frag + 1);
  2118. seg_info->total_len = qdf_nbuf_len(nbuf);
  2119. seg_info->next = NULL;
  2120. sg_info->curr_seg = seg_info;
  2121. msdu_info->frm_type = dp_tx_frm_sg;
  2122. msdu_info->num_seg = 1;
  2123. return nbuf;
  2124. map_err:
  2125. /* restore paddr into nbuf before calling unmap */
  2126. qdf_nbuf_mapped_paddr_set(nbuf,
  2127. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2128. ((uint64_t)
  2129. seg_info->frags[0].paddr_hi) << 32));
  2130. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2131. QDF_DMA_TO_DEVICE,
  2132. seg_info->frags[0].len);
  2133. for (i = 1; i <= cur_frag; i++) {
  2134. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2135. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2136. seg_info->frags[i].paddr_hi) << 32),
  2137. seg_info->frags[i].len,
  2138. QDF_DMA_TO_DEVICE);
  2139. }
  2140. qdf_nbuf_free(nbuf);
  2141. return NULL;
  2142. }
  2143. /**
  2144. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2145. * @vdev: DP vdev handle
  2146. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2147. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2148. *
  2149. * Return: NULL on failure,
  2150. * nbuf when extracted successfully
  2151. */
  2152. static
  2153. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2154. struct dp_tx_msdu_info_s *msdu_info,
  2155. uint16_t ppdu_cookie)
  2156. {
  2157. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2158. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2159. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2160. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2161. (msdu_info->meta_data[5], 1);
  2162. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2163. (msdu_info->meta_data[5], 1);
  2164. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2165. (msdu_info->meta_data[6], ppdu_cookie);
  2166. msdu_info->exception_fw = 1;
  2167. msdu_info->is_tx_sniffer = 1;
  2168. }
  2169. #ifdef MESH_MODE_SUPPORT
  2170. /**
  2171. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2172. and prepare msdu_info for mesh frames.
  2173. * @vdev: DP vdev handle
  2174. * @nbuf: skb
  2175. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2176. *
  2177. * Return: NULL on failure,
  2178. * nbuf when extracted successfully
  2179. */
  2180. static
  2181. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2182. struct dp_tx_msdu_info_s *msdu_info)
  2183. {
  2184. struct meta_hdr_s *mhdr;
  2185. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2186. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2187. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2188. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2189. msdu_info->exception_fw = 0;
  2190. goto remove_meta_hdr;
  2191. }
  2192. msdu_info->exception_fw = 1;
  2193. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2194. meta_data->host_tx_desc_pool = 1;
  2195. meta_data->update_peer_cache = 1;
  2196. meta_data->learning_frame = 1;
  2197. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2198. meta_data->power = mhdr->power;
  2199. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2200. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2201. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2202. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2203. meta_data->dyn_bw = 1;
  2204. meta_data->valid_pwr = 1;
  2205. meta_data->valid_mcs_mask = 1;
  2206. meta_data->valid_nss_mask = 1;
  2207. meta_data->valid_preamble_type = 1;
  2208. meta_data->valid_retries = 1;
  2209. meta_data->valid_bw_info = 1;
  2210. }
  2211. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2212. meta_data->encrypt_type = 0;
  2213. meta_data->valid_encrypt_type = 1;
  2214. meta_data->learning_frame = 0;
  2215. }
  2216. meta_data->valid_key_flags = 1;
  2217. meta_data->key_flags = (mhdr->keyix & 0x3);
  2218. remove_meta_hdr:
  2219. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2220. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2221. "qdf_nbuf_pull_head failed");
  2222. qdf_nbuf_free(nbuf);
  2223. return NULL;
  2224. }
  2225. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2226. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2227. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  2228. " tid %d to_fw %d",
  2229. __func__, msdu_info->meta_data[0],
  2230. msdu_info->meta_data[1],
  2231. msdu_info->meta_data[2],
  2232. msdu_info->meta_data[3],
  2233. msdu_info->meta_data[4],
  2234. msdu_info->meta_data[5],
  2235. msdu_info->tid, msdu_info->exception_fw);
  2236. return nbuf;
  2237. }
  2238. #else
  2239. static
  2240. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2241. struct dp_tx_msdu_info_s *msdu_info)
  2242. {
  2243. return nbuf;
  2244. }
  2245. #endif
  2246. /**
  2247. * dp_check_exc_metadata() - Checks if parameters are valid
  2248. * @tx_exc - holds all exception path parameters
  2249. *
  2250. * Returns true when all the parameters are valid else false
  2251. *
  2252. */
  2253. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2254. {
  2255. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  2256. HTT_INVALID_TID);
  2257. bool invalid_encap_type =
  2258. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2259. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2260. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2261. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2262. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2263. tx_exc->ppdu_cookie == 0);
  2264. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2265. invalid_cookie) {
  2266. return false;
  2267. }
  2268. return true;
  2269. }
  2270. #ifdef ATH_SUPPORT_IQUE
  2271. /**
  2272. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2273. * @vdev: vdev handle
  2274. * @nbuf: skb
  2275. *
  2276. * Return: true on success,
  2277. * false on failure
  2278. */
  2279. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2280. {
  2281. qdf_ether_header_t *eh;
  2282. /* Mcast to Ucast Conversion*/
  2283. if (qdf_likely(!vdev->mcast_enhancement_en))
  2284. return true;
  2285. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2286. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2287. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2288. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2289. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2290. qdf_nbuf_len(nbuf));
  2291. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2292. QDF_STATUS_SUCCESS) {
  2293. return false;
  2294. }
  2295. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2296. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2297. QDF_STATUS_SUCCESS) {
  2298. return false;
  2299. }
  2300. }
  2301. }
  2302. return true;
  2303. }
  2304. #else
  2305. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2306. {
  2307. return true;
  2308. }
  2309. #endif
  2310. /**
  2311. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2312. * @nbuf: qdf_nbuf_t
  2313. * @vdev: struct dp_vdev *
  2314. *
  2315. * Allow packet for processing only if it is for peer client which is
  2316. * connected with same vap. Drop packet if client is connected to
  2317. * different vap.
  2318. *
  2319. * Return: QDF_STATUS
  2320. */
  2321. static inline QDF_STATUS
  2322. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2323. {
  2324. struct dp_ast_entry *dst_ast_entry = NULL;
  2325. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2326. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2327. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2328. return QDF_STATUS_SUCCESS;
  2329. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2330. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2331. eh->ether_dhost,
  2332. vdev->vdev_id);
  2333. /* If there is no ast entry, return failure */
  2334. if (qdf_unlikely(!dst_ast_entry)) {
  2335. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2336. return QDF_STATUS_E_FAILURE;
  2337. }
  2338. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2339. return QDF_STATUS_SUCCESS;
  2340. }
  2341. /**
  2342. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2343. * @soc: DP soc handle
  2344. * @vdev_id: id of DP vdev handle
  2345. * @nbuf: skb
  2346. * @tx_exc_metadata: Handle that holds exception path meta data
  2347. *
  2348. * Entry point for Core Tx layer (DP_TX) invoked from
  2349. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2350. *
  2351. * Return: NULL on success,
  2352. * nbuf when it fails to send
  2353. */
  2354. qdf_nbuf_t
  2355. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2356. qdf_nbuf_t nbuf,
  2357. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2358. {
  2359. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2360. qdf_ether_header_t *eh = NULL;
  2361. struct dp_tx_msdu_info_s msdu_info;
  2362. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2363. DP_MOD_ID_TX_EXCEPTION);
  2364. if (qdf_unlikely(!vdev))
  2365. goto fail;
  2366. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2367. if (!tx_exc_metadata)
  2368. goto fail;
  2369. msdu_info.tid = tx_exc_metadata->tid;
  2370. dp_tx_wds_ext(soc, vdev, tx_exc_metadata->peer_id, &msdu_info);
  2371. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2372. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2373. QDF_MAC_ADDR_REF(nbuf->data));
  2374. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2375. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2376. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2377. "Invalid parameters in exception path");
  2378. goto fail;
  2379. }
  2380. /* Basic sanity checks for unsupported packets */
  2381. /* MESH mode */
  2382. if (qdf_unlikely(vdev->mesh_vdev)) {
  2383. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2384. "Mesh mode is not supported in exception path");
  2385. goto fail;
  2386. }
  2387. /*
  2388. * Classify the frame and call corresponding
  2389. * "prepare" function which extracts the segment (TSO)
  2390. * and fragmentation information (for TSO , SG, ME, or Raw)
  2391. * into MSDU_INFO structure which is later used to fill
  2392. * SW and HW descriptors.
  2393. */
  2394. if (qdf_nbuf_is_tso(nbuf)) {
  2395. dp_verbose_debug("TSO frame %pK", vdev);
  2396. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2397. qdf_nbuf_len(nbuf));
  2398. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2399. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2400. qdf_nbuf_len(nbuf));
  2401. return nbuf;
  2402. }
  2403. goto send_multiple;
  2404. }
  2405. /* SG */
  2406. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2407. struct dp_tx_seg_info_s seg_info = {0};
  2408. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2409. if (!nbuf)
  2410. return NULL;
  2411. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2412. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2413. qdf_nbuf_len(nbuf));
  2414. goto send_multiple;
  2415. }
  2416. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  2417. return NULL;
  2418. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2419. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2420. qdf_nbuf_len(nbuf));
  2421. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2422. tx_exc_metadata->ppdu_cookie);
  2423. }
  2424. /*
  2425. * Get HW Queue to use for this frame.
  2426. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2427. * dedicated for data and 1 for command.
  2428. * "queue_id" maps to one hardware ring.
  2429. * With each ring, we also associate a unique Tx descriptor pool
  2430. * to minimize lock contention for these resources.
  2431. */
  2432. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2433. /*
  2434. * Check exception descriptors
  2435. */
  2436. if (dp_tx_exception_limit_check(vdev))
  2437. goto fail;
  2438. /* Single linear frame */
  2439. /*
  2440. * If nbuf is a simple linear frame, use send_single function to
  2441. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2442. * SRNG. There is no need to setup a MSDU extension descriptor.
  2443. */
  2444. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2445. tx_exc_metadata->peer_id, tx_exc_metadata);
  2446. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2447. return nbuf;
  2448. send_multiple:
  2449. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2450. fail:
  2451. if (vdev)
  2452. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2453. dp_verbose_debug("pkt send failed");
  2454. return nbuf;
  2455. }
  2456. /**
  2457. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2458. * in exception path in special case to avoid regular exception path chk.
  2459. * @soc: DP soc handle
  2460. * @vdev_id: id of DP vdev handle
  2461. * @nbuf: skb
  2462. * @tx_exc_metadata: Handle that holds exception path meta data
  2463. *
  2464. * Entry point for Core Tx layer (DP_TX) invoked from
  2465. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2466. *
  2467. * Return: NULL on success,
  2468. * nbuf when it fails to send
  2469. */
  2470. qdf_nbuf_t
  2471. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2472. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2473. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2474. {
  2475. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2476. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2477. DP_MOD_ID_TX_EXCEPTION);
  2478. if (qdf_unlikely(!vdev))
  2479. goto fail;
  2480. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2481. == QDF_STATUS_E_FAILURE)) {
  2482. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2483. goto fail;
  2484. }
  2485. /* Unref count as it will agin be taken inside dp_tx_exception */
  2486. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2487. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2488. fail:
  2489. if (vdev)
  2490. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2491. dp_verbose_debug("pkt send failed");
  2492. return nbuf;
  2493. }
  2494. /**
  2495. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2496. * @soc: DP soc handle
  2497. * @vdev_id: DP vdev handle
  2498. * @nbuf: skb
  2499. *
  2500. * Entry point for Core Tx layer (DP_TX) invoked from
  2501. * hard_start_xmit in OSIF/HDD
  2502. *
  2503. * Return: NULL on success,
  2504. * nbuf when it fails to send
  2505. */
  2506. #ifdef MESH_MODE_SUPPORT
  2507. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2508. qdf_nbuf_t nbuf)
  2509. {
  2510. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2511. struct meta_hdr_s *mhdr;
  2512. qdf_nbuf_t nbuf_mesh = NULL;
  2513. qdf_nbuf_t nbuf_clone = NULL;
  2514. struct dp_vdev *vdev;
  2515. uint8_t no_enc_frame = 0;
  2516. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2517. if (!nbuf_mesh) {
  2518. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2519. "qdf_nbuf_unshare failed");
  2520. return nbuf;
  2521. }
  2522. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2523. if (!vdev) {
  2524. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2525. "vdev is NULL for vdev_id %d", vdev_id);
  2526. return nbuf;
  2527. }
  2528. nbuf = nbuf_mesh;
  2529. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2530. if ((vdev->sec_type != cdp_sec_type_none) &&
  2531. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2532. no_enc_frame = 1;
  2533. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2534. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2535. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2536. !no_enc_frame) {
  2537. nbuf_clone = qdf_nbuf_clone(nbuf);
  2538. if (!nbuf_clone) {
  2539. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2540. "qdf_nbuf_clone failed");
  2541. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2542. return nbuf;
  2543. }
  2544. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2545. }
  2546. if (nbuf_clone) {
  2547. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2548. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2549. } else {
  2550. qdf_nbuf_free(nbuf_clone);
  2551. }
  2552. }
  2553. if (no_enc_frame)
  2554. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2555. else
  2556. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2557. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2558. if ((!nbuf) && no_enc_frame) {
  2559. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2560. }
  2561. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2562. return nbuf;
  2563. }
  2564. #else
  2565. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2566. qdf_nbuf_t nbuf)
  2567. {
  2568. return dp_tx_send(soc, vdev_id, nbuf);
  2569. }
  2570. #endif
  2571. /**
  2572. * dp_tx_nawds_handler() - NAWDS handler
  2573. *
  2574. * @soc: DP soc handle
  2575. * @vdev_id: id of DP vdev handle
  2576. * @msdu_info: msdu_info required to create HTT metadata
  2577. * @nbuf: skb
  2578. *
  2579. * This API transfers the multicast frames with the peer id
  2580. * on NAWDS enabled peer.
  2581. * Return: none
  2582. */
  2583. static inline
  2584. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2585. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2586. {
  2587. struct dp_peer *peer = NULL;
  2588. qdf_nbuf_t nbuf_clone = NULL;
  2589. uint16_t peer_id = DP_INVALID_PEER;
  2590. uint16_t sa_peer_id = DP_INVALID_PEER;
  2591. struct dp_ast_entry *ast_entry = NULL;
  2592. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2593. qdf_spin_lock_bh(&soc->ast_lock);
  2594. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2595. (soc,
  2596. (uint8_t *)(eh->ether_shost),
  2597. vdev->pdev->pdev_id);
  2598. if (ast_entry)
  2599. sa_peer_id = ast_entry->peer_id;
  2600. qdf_spin_unlock_bh(&soc->ast_lock);
  2601. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2602. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2603. if (!peer->bss_peer && peer->nawds_enabled) {
  2604. peer_id = peer->peer_id;
  2605. /* Multicast packets needs to be
  2606. * dropped in case of intra bss forwarding
  2607. */
  2608. if (sa_peer_id == peer->peer_id) {
  2609. QDF_TRACE(QDF_MODULE_ID_DP,
  2610. QDF_TRACE_LEVEL_DEBUG,
  2611. " %s: multicast packet", __func__);
  2612. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  2613. continue;
  2614. }
  2615. nbuf_clone = qdf_nbuf_clone(nbuf);
  2616. if (!nbuf_clone) {
  2617. QDF_TRACE(QDF_MODULE_ID_DP,
  2618. QDF_TRACE_LEVEL_ERROR,
  2619. FL("nbuf clone failed"));
  2620. break;
  2621. }
  2622. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2623. msdu_info, peer_id,
  2624. NULL);
  2625. if (nbuf_clone) {
  2626. QDF_TRACE(QDF_MODULE_ID_DP,
  2627. QDF_TRACE_LEVEL_DEBUG,
  2628. FL("pkt send failed"));
  2629. qdf_nbuf_free(nbuf_clone);
  2630. } else {
  2631. if (peer_id != DP_INVALID_PEER)
  2632. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2633. 1, qdf_nbuf_len(nbuf));
  2634. }
  2635. }
  2636. }
  2637. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2638. }
  2639. /**
  2640. * dp_tx_send() - Transmit a frame on a given VAP
  2641. * @soc: DP soc handle
  2642. * @vdev_id: id of DP vdev handle
  2643. * @nbuf: skb
  2644. *
  2645. * Entry point for Core Tx layer (DP_TX) invoked from
  2646. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2647. * cases
  2648. *
  2649. * Return: NULL on success,
  2650. * nbuf when it fails to send
  2651. */
  2652. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2653. qdf_nbuf_t nbuf)
  2654. {
  2655. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2656. uint16_t peer_id = HTT_INVALID_PEER;
  2657. /*
  2658. * doing a memzero is causing additional function call overhead
  2659. * so doing static stack clearing
  2660. */
  2661. struct dp_tx_msdu_info_s msdu_info = {0};
  2662. struct dp_vdev *vdev = NULL;
  2663. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2664. return nbuf;
  2665. /*
  2666. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2667. * this in per packet path.
  2668. *
  2669. * As in this path vdev memory is already protected with netdev
  2670. * tx lock
  2671. */
  2672. vdev = soc->vdev_id_map[vdev_id];
  2673. if (qdf_unlikely(!vdev))
  2674. return nbuf;
  2675. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2676. QDF_MAC_ADDR_REF(nbuf->data));
  2677. /*
  2678. * Set Default Host TID value to invalid TID
  2679. * (TID override disabled)
  2680. */
  2681. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2682. dp_tx_wds_ext(soc, vdev, peer_id, &msdu_info);
  2683. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2684. if (qdf_unlikely(vdev->mesh_vdev)) {
  2685. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2686. &msdu_info);
  2687. if (!nbuf_mesh) {
  2688. dp_verbose_debug("Extracting mesh metadata failed");
  2689. return nbuf;
  2690. }
  2691. nbuf = nbuf_mesh;
  2692. }
  2693. /*
  2694. * Get HW Queue to use for this frame.
  2695. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2696. * dedicated for data and 1 for command.
  2697. * "queue_id" maps to one hardware ring.
  2698. * With each ring, we also associate a unique Tx descriptor pool
  2699. * to minimize lock contention for these resources.
  2700. */
  2701. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2702. /*
  2703. * TCL H/W supports 2 DSCP-TID mapping tables.
  2704. * Table 1 - Default DSCP-TID mapping table
  2705. * Table 2 - 1 DSCP-TID override table
  2706. *
  2707. * If we need a different DSCP-TID mapping for this vap,
  2708. * call tid_classify to extract DSCP/ToS from frame and
  2709. * map to a TID and store in msdu_info. This is later used
  2710. * to fill in TCL Input descriptor (per-packet TID override).
  2711. */
  2712. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2713. /*
  2714. * Classify the frame and call corresponding
  2715. * "prepare" function which extracts the segment (TSO)
  2716. * and fragmentation information (for TSO , SG, ME, or Raw)
  2717. * into MSDU_INFO structure which is later used to fill
  2718. * SW and HW descriptors.
  2719. */
  2720. if (qdf_nbuf_is_tso(nbuf)) {
  2721. dp_verbose_debug("TSO frame %pK", vdev);
  2722. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2723. qdf_nbuf_len(nbuf));
  2724. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2725. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2726. qdf_nbuf_len(nbuf));
  2727. return nbuf;
  2728. }
  2729. goto send_multiple;
  2730. }
  2731. /* SG */
  2732. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2733. struct dp_tx_seg_info_s seg_info = {0};
  2734. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2735. if (!nbuf)
  2736. return NULL;
  2737. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2738. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2739. qdf_nbuf_len(nbuf));
  2740. goto send_multiple;
  2741. }
  2742. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  2743. return NULL;
  2744. /* RAW */
  2745. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2746. struct dp_tx_seg_info_s seg_info = {0};
  2747. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2748. if (!nbuf)
  2749. return NULL;
  2750. dp_verbose_debug("Raw frame %pK", vdev);
  2751. goto send_multiple;
  2752. }
  2753. if (qdf_unlikely(vdev->nawds_enabled)) {
  2754. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2755. qdf_nbuf_data(nbuf);
  2756. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2757. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2758. peer_id = DP_INVALID_PEER;
  2759. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2760. 1, qdf_nbuf_len(nbuf));
  2761. }
  2762. /* Single linear frame */
  2763. /*
  2764. * If nbuf is a simple linear frame, use send_single function to
  2765. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2766. * SRNG. There is no need to setup a MSDU extension descriptor.
  2767. */
  2768. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2769. return nbuf;
  2770. send_multiple:
  2771. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2772. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2773. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2774. return nbuf;
  2775. }
  2776. /**
  2777. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  2778. * case to vaoid check in perpkt path.
  2779. * @soc: DP soc handle
  2780. * @vdev_id: id of DP vdev handle
  2781. * @nbuf: skb
  2782. *
  2783. * Entry point for Core Tx layer (DP_TX) invoked from
  2784. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  2785. * with special condition to avoid per pkt check in dp_tx_send
  2786. *
  2787. * Return: NULL on success,
  2788. * nbuf when it fails to send
  2789. */
  2790. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2791. uint8_t vdev_id, qdf_nbuf_t nbuf)
  2792. {
  2793. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2794. struct dp_vdev *vdev = NULL;
  2795. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2796. return nbuf;
  2797. /*
  2798. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2799. * this in per packet path.
  2800. *
  2801. * As in this path vdev memory is already protected with netdev
  2802. * tx lock
  2803. */
  2804. vdev = soc->vdev_id_map[vdev_id];
  2805. if (qdf_unlikely(!vdev))
  2806. return nbuf;
  2807. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2808. == QDF_STATUS_E_FAILURE)) {
  2809. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2810. return nbuf;
  2811. }
  2812. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  2813. }
  2814. /**
  2815. * dp_tx_reinject_handler() - Tx Reinject Handler
  2816. * @soc: datapath soc handle
  2817. * @vdev: datapath vdev handle
  2818. * @tx_desc: software descriptor head pointer
  2819. * @status : Tx completion status from HTT descriptor
  2820. *
  2821. * This function reinjects frames back to Target.
  2822. * Todo - Host queue needs to be added
  2823. *
  2824. * Return: none
  2825. */
  2826. static
  2827. void dp_tx_reinject_handler(struct dp_soc *soc,
  2828. struct dp_vdev *vdev,
  2829. struct dp_tx_desc_s *tx_desc,
  2830. uint8_t *status)
  2831. {
  2832. struct dp_peer *peer = NULL;
  2833. uint32_t peer_id = HTT_INVALID_PEER;
  2834. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2835. qdf_nbuf_t nbuf_copy = NULL;
  2836. struct dp_tx_msdu_info_s msdu_info;
  2837. #ifdef WDS_VENDOR_EXTENSION
  2838. int is_mcast = 0, is_ucast = 0;
  2839. int num_peers_3addr = 0;
  2840. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2841. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2842. #endif
  2843. qdf_assert(vdev);
  2844. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2845. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2846. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2847. "%s Tx reinject path", __func__);
  2848. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2849. qdf_nbuf_len(tx_desc->nbuf));
  2850. #ifdef WDS_VENDOR_EXTENSION
  2851. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2852. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2853. } else {
  2854. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2855. }
  2856. is_ucast = !is_mcast;
  2857. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2858. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2859. if (peer->bss_peer)
  2860. continue;
  2861. /* Detect wds peers that use 3-addr framing for mcast.
  2862. * if there are any, the bss_peer is used to send the
  2863. * the mcast frame using 3-addr format. all wds enabled
  2864. * peers that use 4-addr framing for mcast frames will
  2865. * be duplicated and sent as 4-addr frames below.
  2866. */
  2867. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2868. num_peers_3addr = 1;
  2869. break;
  2870. }
  2871. }
  2872. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2873. #endif
  2874. if (qdf_unlikely(vdev->mesh_vdev)) {
  2875. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2876. } else {
  2877. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2878. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2879. if ((peer->peer_id != HTT_INVALID_PEER) &&
  2880. #ifdef WDS_VENDOR_EXTENSION
  2881. /*
  2882. * . if 3-addr STA, then send on BSS Peer
  2883. * . if Peer WDS enabled and accept 4-addr mcast,
  2884. * send mcast on that peer only
  2885. * . if Peer WDS enabled and accept 4-addr ucast,
  2886. * send ucast on that peer only
  2887. */
  2888. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2889. (peer->wds_enabled &&
  2890. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2891. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2892. #else
  2893. ((peer->bss_peer &&
  2894. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))))) {
  2895. #endif
  2896. peer_id = DP_INVALID_PEER;
  2897. nbuf_copy = qdf_nbuf_copy(nbuf);
  2898. if (!nbuf_copy) {
  2899. QDF_TRACE(QDF_MODULE_ID_DP,
  2900. QDF_TRACE_LEVEL_DEBUG,
  2901. FL("nbuf copy failed"));
  2902. break;
  2903. }
  2904. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2905. nbuf_copy,
  2906. &msdu_info,
  2907. peer_id,
  2908. NULL);
  2909. if (nbuf_copy) {
  2910. QDF_TRACE(QDF_MODULE_ID_DP,
  2911. QDF_TRACE_LEVEL_DEBUG,
  2912. FL("pkt send failed"));
  2913. qdf_nbuf_free(nbuf_copy);
  2914. }
  2915. }
  2916. }
  2917. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2918. }
  2919. qdf_nbuf_free(nbuf);
  2920. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2921. }
  2922. /**
  2923. * dp_tx_inspect_handler() - Tx Inspect Handler
  2924. * @soc: datapath soc handle
  2925. * @vdev: datapath vdev handle
  2926. * @tx_desc: software descriptor head pointer
  2927. * @status : Tx completion status from HTT descriptor
  2928. *
  2929. * Handles Tx frames sent back to Host for inspection
  2930. * (ProxyARP)
  2931. *
  2932. * Return: none
  2933. */
  2934. static void dp_tx_inspect_handler(struct dp_soc *soc,
  2935. struct dp_vdev *vdev,
  2936. struct dp_tx_desc_s *tx_desc,
  2937. uint8_t *status)
  2938. {
  2939. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2940. "%s Tx inspect path",
  2941. __func__);
  2942. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  2943. qdf_nbuf_len(tx_desc->nbuf));
  2944. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2945. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2946. }
  2947. #ifdef FEATURE_PERPKT_INFO
  2948. /**
  2949. * dp_get_completion_indication_for_stack() - send completion to stack
  2950. * @soc : dp_soc handle
  2951. * @pdev: dp_pdev handle
  2952. * @peer: dp peer handle
  2953. * @ts: transmit completion status structure
  2954. * @netbuf: Buffer pointer for free
  2955. *
  2956. * This function is used for indication whether buffer needs to be
  2957. * sent to stack for freeing or not
  2958. */
  2959. QDF_STATUS
  2960. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2961. struct dp_pdev *pdev,
  2962. struct dp_peer *peer,
  2963. struct hal_tx_completion_status *ts,
  2964. qdf_nbuf_t netbuf,
  2965. uint64_t time_latency)
  2966. {
  2967. struct tx_capture_hdr *ppdu_hdr;
  2968. uint16_t peer_id = ts->peer_id;
  2969. uint32_t ppdu_id = ts->ppdu_id;
  2970. uint8_t first_msdu = ts->first_msdu;
  2971. uint8_t last_msdu = ts->last_msdu;
  2972. uint32_t txcap_hdr_size = sizeof(struct tx_capture_hdr);
  2973. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2974. !pdev->latency_capture_enable))
  2975. return QDF_STATUS_E_NOSUPPORT;
  2976. if (!peer) {
  2977. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2978. FL("Peer Invalid"));
  2979. return QDF_STATUS_E_INVAL;
  2980. }
  2981. if (pdev->mcopy_mode) {
  2982. /* If mcopy is enabled and mcopy_mode is M_COPY deliver 1st MSDU
  2983. * per PPDU. If mcopy_mode is M_COPY_EXTENDED deliver 1st MSDU
  2984. * for each MPDU
  2985. */
  2986. if (pdev->mcopy_mode == M_COPY) {
  2987. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2988. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2989. return QDF_STATUS_E_INVAL;
  2990. }
  2991. }
  2992. if (!first_msdu)
  2993. return QDF_STATUS_E_INVAL;
  2994. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2995. pdev->m_copy_id.tx_peer_id = peer_id;
  2996. }
  2997. if (qdf_unlikely(qdf_nbuf_headroom(netbuf) < txcap_hdr_size)) {
  2998. netbuf = qdf_nbuf_realloc_headroom(netbuf, txcap_hdr_size);
  2999. if (!netbuf) {
  3000. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3001. FL("No headroom"));
  3002. return QDF_STATUS_E_NOMEM;
  3003. }
  3004. }
  3005. if (!qdf_nbuf_push_head(netbuf, txcap_hdr_size)) {
  3006. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3007. FL("No headroom"));
  3008. return QDF_STATUS_E_NOMEM;
  3009. }
  3010. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  3011. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  3012. QDF_MAC_ADDR_SIZE);
  3013. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  3014. QDF_MAC_ADDR_SIZE);
  3015. ppdu_hdr->ppdu_id = ppdu_id;
  3016. ppdu_hdr->peer_id = peer_id;
  3017. ppdu_hdr->first_msdu = first_msdu;
  3018. ppdu_hdr->last_msdu = last_msdu;
  3019. if (qdf_unlikely(pdev->latency_capture_enable)) {
  3020. ppdu_hdr->tsf = ts->tsf;
  3021. ppdu_hdr->time_latency = time_latency;
  3022. }
  3023. return QDF_STATUS_SUCCESS;
  3024. }
  3025. /**
  3026. * dp_send_completion_to_stack() - send completion to stack
  3027. * @soc : dp_soc handle
  3028. * @pdev: dp_pdev handle
  3029. * @peer_id: peer_id of the peer for which completion came
  3030. * @ppdu_id: ppdu_id
  3031. * @netbuf: Buffer pointer for free
  3032. *
  3033. * This function is used to send completion to stack
  3034. * to free buffer
  3035. */
  3036. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  3037. uint16_t peer_id, uint32_t ppdu_id,
  3038. qdf_nbuf_t netbuf)
  3039. {
  3040. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  3041. netbuf, peer_id,
  3042. WDI_NO_VAL, pdev->pdev_id);
  3043. }
  3044. #else
  3045. static QDF_STATUS
  3046. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  3047. struct dp_pdev *pdev,
  3048. struct dp_peer *peer,
  3049. struct hal_tx_completion_status *ts,
  3050. qdf_nbuf_t netbuf,
  3051. uint64_t time_latency)
  3052. {
  3053. return QDF_STATUS_E_NOSUPPORT;
  3054. }
  3055. static void
  3056. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  3057. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  3058. {
  3059. }
  3060. #endif
  3061. #ifdef MESH_MODE_SUPPORT
  3062. /**
  3063. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3064. * in mesh meta header
  3065. * @tx_desc: software descriptor head pointer
  3066. * @ts: pointer to tx completion stats
  3067. * Return: none
  3068. */
  3069. static
  3070. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3071. struct hal_tx_completion_status *ts)
  3072. {
  3073. struct meta_hdr_s *mhdr;
  3074. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3075. if (!tx_desc->msdu_ext_desc) {
  3076. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3077. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3078. "netbuf %pK offset %d",
  3079. netbuf, tx_desc->pkt_offset);
  3080. return;
  3081. }
  3082. }
  3083. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  3084. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3085. "netbuf %pK offset %lu", netbuf,
  3086. sizeof(struct meta_hdr_s));
  3087. return;
  3088. }
  3089. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  3090. mhdr->rssi = ts->ack_frame_rssi;
  3091. mhdr->band = tx_desc->pdev->operating_channel.band;
  3092. mhdr->channel = tx_desc->pdev->operating_channel.num;
  3093. }
  3094. #else
  3095. static
  3096. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3097. struct hal_tx_completion_status *ts)
  3098. {
  3099. }
  3100. #endif
  3101. #ifdef QCA_PEER_EXT_STATS
  3102. /*
  3103. * dp_tx_compute_tid_delay() - Compute per TID delay
  3104. * @stats: Per TID delay stats
  3105. * @tx_desc: Software Tx descriptor
  3106. *
  3107. * Compute the software enqueue and hw enqueue delays and
  3108. * update the respective histograms
  3109. *
  3110. * Return: void
  3111. */
  3112. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3113. struct dp_tx_desc_s *tx_desc)
  3114. {
  3115. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3116. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3117. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3118. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3119. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3120. timestamp_hw_enqueue = tx_desc->timestamp;
  3121. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3122. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3123. timestamp_hw_enqueue);
  3124. /*
  3125. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3126. */
  3127. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3128. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3129. }
  3130. /*
  3131. * dp_tx_update_peer_ext_stats() - Update the peer extended stats
  3132. * @peer: DP peer context
  3133. * @tx_desc: Tx software descriptor
  3134. * @tid: Transmission ID
  3135. * @ring_id: Rx CPU context ID/CPU_ID
  3136. *
  3137. * Update the peer extended stats. These are enhanced other
  3138. * delay stats per msdu level.
  3139. *
  3140. * Return: void
  3141. */
  3142. static void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3143. struct dp_tx_desc_s *tx_desc,
  3144. uint8_t tid, uint8_t ring_id)
  3145. {
  3146. struct dp_pdev *pdev = peer->vdev->pdev;
  3147. struct dp_soc *soc = NULL;
  3148. struct cdp_peer_ext_stats *pext_stats = NULL;
  3149. soc = pdev->soc;
  3150. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3151. return;
  3152. pext_stats = peer->pext_stats;
  3153. qdf_assert(pext_stats);
  3154. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3155. /*
  3156. * For non-TID packets use the TID 9
  3157. */
  3158. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3159. tid = CDP_MAX_DATA_TIDS - 1;
  3160. dp_tx_compute_tid_delay(&pext_stats->delay_stats[tid][ring_id],
  3161. tx_desc);
  3162. }
  3163. #else
  3164. static inline void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3165. struct dp_tx_desc_s *tx_desc,
  3166. uint8_t tid, uint8_t ring_id)
  3167. {
  3168. }
  3169. #endif
  3170. /**
  3171. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3172. * to pass in correct fields
  3173. *
  3174. * @vdev: pdev handle
  3175. * @tx_desc: tx descriptor
  3176. * @tid: tid value
  3177. * @ring_id: TCL or WBM ring number for transmit path
  3178. * Return: none
  3179. */
  3180. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  3181. struct dp_tx_desc_s *tx_desc,
  3182. uint8_t tid, uint8_t ring_id)
  3183. {
  3184. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3185. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3186. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  3187. return;
  3188. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3189. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3190. timestamp_hw_enqueue = tx_desc->timestamp;
  3191. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3192. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3193. timestamp_hw_enqueue);
  3194. interframe_delay = (uint32_t)(timestamp_ingress -
  3195. vdev->prev_tx_enq_tstamp);
  3196. /*
  3197. * Delay in software enqueue
  3198. */
  3199. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  3200. CDP_DELAY_STATS_SW_ENQ, ring_id);
  3201. /*
  3202. * Delay between packet enqueued to HW and Tx completion
  3203. */
  3204. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  3205. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  3206. /*
  3207. * Update interframe delay stats calculated at hardstart receive point.
  3208. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3209. * interframe delay will not be calculate correctly for 1st frame.
  3210. * On the other side, this will help in avoiding extra per packet check
  3211. * of !vdev->prev_tx_enq_tstamp.
  3212. */
  3213. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  3214. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  3215. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3216. }
  3217. #ifdef DISABLE_DP_STATS
  3218. static
  3219. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3220. {
  3221. }
  3222. #else
  3223. static
  3224. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3225. {
  3226. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3227. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3228. if (subtype != QDF_PROTO_INVALID)
  3229. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  3230. }
  3231. #endif
  3232. /**
  3233. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3234. * per wbm ring
  3235. *
  3236. * @tx_desc: software descriptor head pointer
  3237. * @ts: Tx completion status
  3238. * @peer: peer handle
  3239. * @ring_id: ring number
  3240. *
  3241. * Return: None
  3242. */
  3243. static inline void
  3244. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3245. struct hal_tx_completion_status *ts,
  3246. struct dp_peer *peer, uint8_t ring_id)
  3247. {
  3248. struct dp_pdev *pdev = peer->vdev->pdev;
  3249. struct dp_soc *soc = NULL;
  3250. uint8_t mcs, pkt_type;
  3251. uint8_t tid = ts->tid;
  3252. uint32_t length;
  3253. struct cdp_tid_tx_stats *tid_stats;
  3254. if (!pdev)
  3255. return;
  3256. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3257. tid = CDP_MAX_DATA_TIDS - 1;
  3258. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3259. soc = pdev->soc;
  3260. mcs = ts->mcs;
  3261. pkt_type = ts->pkt_type;
  3262. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3263. dp_err("Release source is not from TQM");
  3264. return;
  3265. }
  3266. length = qdf_nbuf_len(tx_desc->nbuf);
  3267. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  3268. if (qdf_unlikely(pdev->delay_stats_flag))
  3269. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  3270. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  3271. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  3272. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  3273. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3274. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  3275. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  3276. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  3277. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  3278. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  3279. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  3280. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  3281. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  3282. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  3283. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  3284. /*
  3285. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  3286. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  3287. * are no completions for failed cases. Hence updating tx_failed from
  3288. * data path. Please note that if tx_failed is fixed to be from ppdu,
  3289. * then this has to be removed
  3290. */
  3291. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  3292. peer->stats.tx.dropped.fw_rem_notx +
  3293. peer->stats.tx.dropped.fw_rem_tx +
  3294. peer->stats.tx.dropped.age_out +
  3295. peer->stats.tx.dropped.fw_reason1 +
  3296. peer->stats.tx.dropped.fw_reason2 +
  3297. peer->stats.tx.dropped.fw_reason3;
  3298. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3299. tid_stats->tqm_status_cnt[ts->status]++;
  3300. }
  3301. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3302. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  3303. return;
  3304. }
  3305. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  3306. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  3307. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  3308. /*
  3309. * Following Rate Statistics are updated from HTT PPDU events from FW.
  3310. * Return from here if HTT PPDU events are enabled.
  3311. */
  3312. if (!(soc->process_tx_status))
  3313. return;
  3314. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3315. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  3316. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3317. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  3318. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3319. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3320. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3321. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3322. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3323. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3324. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3325. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3326. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3327. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3328. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3329. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3330. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3331. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3332. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3333. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3334. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  3335. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  3336. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3337. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3338. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  3339. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  3340. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  3341. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  3342. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  3343. &peer->stats, ts->peer_id,
  3344. UPDATE_PEER_STATS, pdev->pdev_id);
  3345. #endif
  3346. }
  3347. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3348. /**
  3349. * dp_tx_flow_pool_lock() - take flow pool lock
  3350. * @soc: core txrx main context
  3351. * @tx_desc: tx desc
  3352. *
  3353. * Return: None
  3354. */
  3355. static inline
  3356. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3357. struct dp_tx_desc_s *tx_desc)
  3358. {
  3359. struct dp_tx_desc_pool_s *pool;
  3360. uint8_t desc_pool_id;
  3361. desc_pool_id = tx_desc->pool_id;
  3362. pool = &soc->tx_desc[desc_pool_id];
  3363. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3364. }
  3365. /**
  3366. * dp_tx_flow_pool_unlock() - release flow pool lock
  3367. * @soc: core txrx main context
  3368. * @tx_desc: tx desc
  3369. *
  3370. * Return: None
  3371. */
  3372. static inline
  3373. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3374. struct dp_tx_desc_s *tx_desc)
  3375. {
  3376. struct dp_tx_desc_pool_s *pool;
  3377. uint8_t desc_pool_id;
  3378. desc_pool_id = tx_desc->pool_id;
  3379. pool = &soc->tx_desc[desc_pool_id];
  3380. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3381. }
  3382. #else
  3383. static inline
  3384. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3385. {
  3386. }
  3387. static inline
  3388. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3389. {
  3390. }
  3391. #endif
  3392. /**
  3393. * dp_tx_notify_completion() - Notify tx completion for this desc
  3394. * @soc: core txrx main context
  3395. * @vdev: datapath vdev handle
  3396. * @tx_desc: tx desc
  3397. * @netbuf: buffer
  3398. * @status: tx status
  3399. *
  3400. * Return: none
  3401. */
  3402. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3403. struct dp_vdev *vdev,
  3404. struct dp_tx_desc_s *tx_desc,
  3405. qdf_nbuf_t netbuf,
  3406. uint8_t status)
  3407. {
  3408. void *osif_dev;
  3409. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3410. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3411. qdf_assert(tx_desc);
  3412. dp_tx_flow_pool_lock(soc, tx_desc);
  3413. if (!vdev ||
  3414. !vdev->osif_vdev) {
  3415. dp_tx_flow_pool_unlock(soc, tx_desc);
  3416. return;
  3417. }
  3418. osif_dev = vdev->osif_vdev;
  3419. tx_compl_cbk = vdev->tx_comp;
  3420. dp_tx_flow_pool_unlock(soc, tx_desc);
  3421. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3422. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3423. if (tx_compl_cbk)
  3424. tx_compl_cbk(netbuf, osif_dev, flag);
  3425. }
  3426. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3427. * @pdev: pdev handle
  3428. * @tid: tid value
  3429. * @txdesc_ts: timestamp from txdesc
  3430. * @ppdu_id: ppdu id
  3431. *
  3432. * Return: none
  3433. */
  3434. #ifdef FEATURE_PERPKT_INFO
  3435. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3436. struct dp_peer *peer,
  3437. uint8_t tid,
  3438. uint64_t txdesc_ts,
  3439. uint32_t ppdu_id)
  3440. {
  3441. uint64_t delta_ms;
  3442. struct cdp_tx_sojourn_stats *sojourn_stats;
  3443. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  3444. return;
  3445. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3446. tid >= CDP_DATA_TID_MAX))
  3447. return;
  3448. if (qdf_unlikely(!pdev->sojourn_buf))
  3449. return;
  3450. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3451. qdf_nbuf_data(pdev->sojourn_buf);
  3452. sojourn_stats->cookie = (void *)peer->rdkstats_ctx;
  3453. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  3454. txdesc_ts;
  3455. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  3456. delta_ms);
  3457. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3458. sojourn_stats->num_msdus[tid] = 1;
  3459. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3460. peer->avg_sojourn_msdu[tid].internal;
  3461. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3462. pdev->sojourn_buf, HTT_INVALID_PEER,
  3463. WDI_NO_VAL, pdev->pdev_id);
  3464. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3465. sojourn_stats->num_msdus[tid] = 0;
  3466. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3467. }
  3468. #else
  3469. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3470. struct dp_peer *peer,
  3471. uint8_t tid,
  3472. uint64_t txdesc_ts,
  3473. uint32_t ppdu_id)
  3474. {
  3475. }
  3476. #endif
  3477. /**
  3478. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3479. * @soc: DP Soc handle
  3480. * @tx_desc: software Tx descriptor
  3481. * @ts : Tx completion status from HAL/HTT descriptor
  3482. *
  3483. * Return: none
  3484. */
  3485. static inline void
  3486. dp_tx_comp_process_desc(struct dp_soc *soc,
  3487. struct dp_tx_desc_s *desc,
  3488. struct hal_tx_completion_status *ts,
  3489. struct dp_peer *peer)
  3490. {
  3491. uint64_t time_latency = 0;
  3492. /*
  3493. * m_copy/tx_capture modes are not supported for
  3494. * scatter gather packets
  3495. */
  3496. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3497. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3498. desc->timestamp);
  3499. }
  3500. if (!(desc->msdu_ext_desc)) {
  3501. if (QDF_STATUS_SUCCESS ==
  3502. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  3503. return;
  3504. }
  3505. if (QDF_STATUS_SUCCESS ==
  3506. dp_get_completion_indication_for_stack(soc,
  3507. desc->pdev,
  3508. peer, ts,
  3509. desc->nbuf,
  3510. time_latency)) {
  3511. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  3512. QDF_DMA_TO_DEVICE,
  3513. desc->nbuf->len);
  3514. dp_send_completion_to_stack(soc,
  3515. desc->pdev,
  3516. ts->peer_id,
  3517. ts->ppdu_id,
  3518. desc->nbuf);
  3519. return;
  3520. }
  3521. }
  3522. dp_tx_comp_free_buf(soc, desc);
  3523. }
  3524. #ifdef DISABLE_DP_STATS
  3525. /**
  3526. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3527. * @soc: core txrx main context
  3528. * @tx_desc: tx desc
  3529. * @status: tx status
  3530. *
  3531. * Return: none
  3532. */
  3533. static inline
  3534. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3535. struct dp_vdev *vdev,
  3536. struct dp_tx_desc_s *tx_desc,
  3537. uint8_t status)
  3538. {
  3539. }
  3540. #else
  3541. static inline
  3542. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3543. struct dp_vdev *vdev,
  3544. struct dp_tx_desc_s *tx_desc,
  3545. uint8_t status)
  3546. {
  3547. void *osif_dev;
  3548. ol_txrx_stats_rx_fp stats_cbk;
  3549. uint8_t pkt_type;
  3550. qdf_assert(tx_desc);
  3551. if (!vdev ||
  3552. !vdev->osif_vdev ||
  3553. !vdev->stats_cb)
  3554. return;
  3555. osif_dev = vdev->osif_vdev;
  3556. stats_cbk = vdev->stats_cb;
  3557. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3558. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3559. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3560. &pkt_type);
  3561. }
  3562. #endif
  3563. /**
  3564. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3565. * @soc: DP soc handle
  3566. * @tx_desc: software descriptor head pointer
  3567. * @ts: Tx completion status
  3568. * @peer: peer handle
  3569. * @ring_id: ring number
  3570. *
  3571. * Return: none
  3572. */
  3573. static inline
  3574. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3575. struct dp_tx_desc_s *tx_desc,
  3576. struct hal_tx_completion_status *ts,
  3577. struct dp_peer *peer, uint8_t ring_id)
  3578. {
  3579. uint32_t length;
  3580. qdf_ether_header_t *eh;
  3581. struct dp_vdev *vdev = NULL;
  3582. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3583. uint8_t dp_status;
  3584. if (!nbuf) {
  3585. dp_info_rl("invalid tx descriptor. nbuf NULL");
  3586. goto out;
  3587. }
  3588. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3589. length = qdf_nbuf_len(nbuf);
  3590. dp_status = qdf_dp_get_status_from_htt(ts->status);
  3591. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3592. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3593. QDF_TRACE_DEFAULT_PDEV_ID,
  3594. qdf_nbuf_data_addr(nbuf),
  3595. sizeof(qdf_nbuf_data(nbuf)),
  3596. tx_desc->id,
  3597. dp_status));
  3598. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3599. "-------------------- \n"
  3600. "Tx Completion Stats: \n"
  3601. "-------------------- \n"
  3602. "ack_frame_rssi = %d \n"
  3603. "first_msdu = %d \n"
  3604. "last_msdu = %d \n"
  3605. "msdu_part_of_amsdu = %d \n"
  3606. "rate_stats valid = %d \n"
  3607. "bw = %d \n"
  3608. "pkt_type = %d \n"
  3609. "stbc = %d \n"
  3610. "ldpc = %d \n"
  3611. "sgi = %d \n"
  3612. "mcs = %d \n"
  3613. "ofdma = %d \n"
  3614. "tones_in_ru = %d \n"
  3615. "tsf = %d \n"
  3616. "ppdu_id = %d \n"
  3617. "transmit_cnt = %d \n"
  3618. "tid = %d \n"
  3619. "peer_id = %d\n",
  3620. ts->ack_frame_rssi, ts->first_msdu,
  3621. ts->last_msdu, ts->msdu_part_of_amsdu,
  3622. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3623. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3624. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3625. ts->transmit_cnt, ts->tid, ts->peer_id);
  3626. /* Update SoC level stats */
  3627. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3628. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3629. if (!peer) {
  3630. dp_info_rl("peer is null or deletion in progress");
  3631. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3632. goto out;
  3633. }
  3634. vdev = peer->vdev;
  3635. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  3636. /* Update per-packet stats for mesh mode */
  3637. if (qdf_unlikely(vdev->mesh_vdev) &&
  3638. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3639. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3640. /* Update peer level stats */
  3641. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  3642. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3643. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  3644. if ((peer->vdev->tx_encap_type ==
  3645. htt_cmn_pkt_type_ethernet) &&
  3646. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3647. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  3648. }
  3649. }
  3650. } else {
  3651. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3652. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3653. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3654. if (qdf_unlikely(peer->in_twt)) {
  3655. DP_STATS_INC_PKT(peer,
  3656. tx.tx_success_twt,
  3657. 1, length);
  3658. }
  3659. }
  3660. }
  3661. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3662. dp_tx_update_peer_ext_stats(peer, tx_desc, ts->tid, ring_id);
  3663. #ifdef QCA_SUPPORT_RDK_STATS
  3664. if (soc->rdkstats_enabled)
  3665. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3666. tx_desc->timestamp,
  3667. ts->ppdu_id);
  3668. #endif
  3669. out:
  3670. return;
  3671. }
  3672. /**
  3673. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3674. * @soc: core txrx main context
  3675. * @comp_head: software descriptor head pointer
  3676. * @ring_id: ring number
  3677. *
  3678. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3679. * and release the software descriptors after processing is complete
  3680. *
  3681. * Return: none
  3682. */
  3683. static void
  3684. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3685. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3686. {
  3687. struct dp_tx_desc_s *desc;
  3688. struct dp_tx_desc_s *next;
  3689. struct hal_tx_completion_status ts;
  3690. struct dp_peer *peer = NULL;
  3691. uint16_t peer_id = DP_INVALID_PEER;
  3692. qdf_nbuf_t netbuf;
  3693. desc = comp_head;
  3694. while (desc) {
  3695. if (peer_id != desc->peer_id) {
  3696. if (peer)
  3697. dp_peer_unref_delete(peer,
  3698. DP_MOD_ID_TX_COMP);
  3699. peer_id = desc->peer_id;
  3700. peer = dp_peer_get_ref_by_id(soc, peer_id,
  3701. DP_MOD_ID_TX_COMP);
  3702. }
  3703. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3704. struct dp_pdev *pdev = desc->pdev;
  3705. if (qdf_likely(peer)) {
  3706. /*
  3707. * Increment peer statistics
  3708. * Minimal statistics update done here
  3709. */
  3710. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1,
  3711. desc->length);
  3712. if (desc->tx_status !=
  3713. HAL_TX_TQM_RR_FRAME_ACKED)
  3714. DP_STATS_INC(peer, tx.tx_failed, 1);
  3715. }
  3716. qdf_assert(pdev);
  3717. dp_tx_outstanding_dec(pdev);
  3718. /*
  3719. * Calling a QDF WRAPPER here is creating signifcant
  3720. * performance impact so avoided the wrapper call here
  3721. */
  3722. next = desc->next;
  3723. qdf_mem_unmap_nbytes_single(soc->osdev,
  3724. desc->dma_addr,
  3725. QDF_DMA_TO_DEVICE,
  3726. desc->length);
  3727. qdf_nbuf_free(desc->nbuf);
  3728. dp_tx_desc_free(soc, desc, desc->pool_id);
  3729. desc = next;
  3730. continue;
  3731. }
  3732. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3733. dp_tx_comp_process_tx_status(soc, desc, &ts, peer, ring_id);
  3734. netbuf = desc->nbuf;
  3735. /* check tx complete notification */
  3736. if (peer &&
  3737. QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  3738. dp_tx_notify_completion(soc, peer->vdev, desc,
  3739. netbuf, ts.status);
  3740. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3741. next = desc->next;
  3742. dp_tx_desc_release(desc, desc->pool_id);
  3743. desc = next;
  3744. }
  3745. if (peer)
  3746. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3747. }
  3748. /**
  3749. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  3750. * @soc: Handle to DP soc structure
  3751. * @tx_desc: software descriptor head pointer
  3752. * @status : Tx completion status from HTT descriptor
  3753. * @ring_id: ring number
  3754. *
  3755. * This function will process HTT Tx indication messages from Target
  3756. *
  3757. * Return: none
  3758. */
  3759. static
  3760. void dp_tx_process_htt_completion(struct dp_soc *soc,
  3761. struct dp_tx_desc_s *tx_desc, uint8_t *status,
  3762. uint8_t ring_id)
  3763. {
  3764. uint8_t tx_status;
  3765. struct dp_pdev *pdev;
  3766. struct dp_vdev *vdev;
  3767. struct hal_tx_completion_status ts = {0};
  3768. uint32_t *htt_desc = (uint32_t *)status;
  3769. struct dp_peer *peer;
  3770. struct cdp_tid_tx_stats *tid_stats = NULL;
  3771. struct htt_soc *htt_handle;
  3772. uint8_t vdev_id;
  3773. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3774. htt_handle = (struct htt_soc *)soc->htt_handle;
  3775. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3776. /*
  3777. * There can be scenario where WBM consuming descriptor enqueued
  3778. * from TQM2WBM first and TQM completion can happen before MEC
  3779. * notification comes from FW2WBM. Avoid access any field of tx
  3780. * descriptor in case of MEC notify.
  3781. */
  3782. if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY) {
  3783. /*
  3784. * Get vdev id from HTT status word in case of MEC
  3785. * notification
  3786. */
  3787. vdev_id = HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(htt_desc[3]);
  3788. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3789. return;
  3790. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3791. DP_MOD_ID_HTT_COMP);
  3792. if (!vdev)
  3793. return;
  3794. dp_tx_mec_handler(vdev, status);
  3795. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3796. return;
  3797. }
  3798. /*
  3799. * If the descriptor is already freed in vdev_detach,
  3800. * continue to next descriptor
  3801. */
  3802. if ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) && !tx_desc->flags) {
  3803. QDF_TRACE(QDF_MODULE_ID_DP,
  3804. QDF_TRACE_LEVEL_INFO,
  3805. "Descriptor freed in vdev_detach %d",
  3806. tx_desc->id);
  3807. return;
  3808. }
  3809. pdev = tx_desc->pdev;
  3810. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3811. QDF_TRACE(QDF_MODULE_ID_DP,
  3812. QDF_TRACE_LEVEL_INFO,
  3813. "pdev in down state %d",
  3814. tx_desc->id);
  3815. dp_tx_comp_free_buf(soc, tx_desc);
  3816. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3817. return;
  3818. }
  3819. qdf_assert(tx_desc->pdev);
  3820. vdev_id = tx_desc->vdev_id;
  3821. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3822. DP_MOD_ID_HTT_COMP);
  3823. if (!vdev)
  3824. return;
  3825. switch (tx_status) {
  3826. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3827. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3828. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3829. {
  3830. uint8_t tid;
  3831. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3832. ts.peer_id =
  3833. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3834. htt_desc[2]);
  3835. ts.tid =
  3836. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3837. htt_desc[2]);
  3838. } else {
  3839. ts.peer_id = HTT_INVALID_PEER;
  3840. ts.tid = HTT_INVALID_TID;
  3841. }
  3842. ts.ppdu_id =
  3843. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3844. htt_desc[1]);
  3845. ts.ack_frame_rssi =
  3846. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3847. htt_desc[1]);
  3848. ts.tsf = htt_desc[3];
  3849. ts.first_msdu = 1;
  3850. ts.last_msdu = 1;
  3851. tid = ts.tid;
  3852. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3853. tid = CDP_MAX_DATA_TIDS - 1;
  3854. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3855. if (qdf_unlikely(pdev->delay_stats_flag))
  3856. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3857. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3858. tid_stats->htt_status_cnt[tx_status]++;
  3859. }
  3860. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3861. DP_MOD_ID_HTT_COMP);
  3862. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, peer, ring_id);
  3863. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3864. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3865. if (qdf_likely(peer))
  3866. dp_peer_unref_delete(peer, DP_MOD_ID_HTT_COMP);
  3867. break;
  3868. }
  3869. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3870. {
  3871. dp_tx_reinject_handler(soc, vdev, tx_desc, status);
  3872. break;
  3873. }
  3874. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3875. {
  3876. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  3877. break;
  3878. }
  3879. default:
  3880. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3881. "%s Invalid HTT tx_status %d\n",
  3882. __func__, tx_status);
  3883. break;
  3884. }
  3885. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3886. }
  3887. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3888. static inline
  3889. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3890. {
  3891. bool limit_hit = false;
  3892. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3893. limit_hit =
  3894. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  3895. if (limit_hit)
  3896. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3897. return limit_hit;
  3898. }
  3899. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3900. {
  3901. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3902. }
  3903. #else
  3904. static inline
  3905. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3906. {
  3907. return false;
  3908. }
  3909. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3910. {
  3911. return false;
  3912. }
  3913. #endif
  3914. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3915. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3916. uint32_t quota)
  3917. {
  3918. void *tx_comp_hal_desc;
  3919. uint8_t buffer_src;
  3920. uint8_t pool_id;
  3921. uint32_t tx_desc_id;
  3922. struct dp_tx_desc_s *tx_desc = NULL;
  3923. struct dp_tx_desc_s *head_desc = NULL;
  3924. struct dp_tx_desc_s *tail_desc = NULL;
  3925. uint32_t num_processed = 0;
  3926. uint32_t count;
  3927. uint32_t num_avail_for_reap = 0;
  3928. bool force_break = false;
  3929. DP_HIST_INIT();
  3930. more_data:
  3931. /* Re-initialize local variables to be re-used */
  3932. head_desc = NULL;
  3933. tail_desc = NULL;
  3934. count = 0;
  3935. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  3936. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  3937. return 0;
  3938. }
  3939. num_avail_for_reap = hal_srng_dst_num_valid(soc->hal_soc, hal_ring_hdl, 0);
  3940. if (num_avail_for_reap >= quota)
  3941. num_avail_for_reap = quota;
  3942. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  3943. /* Find head descriptor from completion ring */
  3944. while (qdf_likely(num_avail_for_reap)) {
  3945. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  3946. if (qdf_unlikely(!tx_comp_hal_desc))
  3947. break;
  3948. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  3949. /* If this buffer was not released by TQM or FW, then it is not
  3950. * Tx completion indication, assert */
  3951. if (qdf_unlikely(buffer_src !=
  3952. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  3953. (qdf_unlikely(buffer_src !=
  3954. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  3955. uint8_t wbm_internal_error;
  3956. dp_err_rl(
  3957. "Tx comp release_src != TQM | FW but from %d",
  3958. buffer_src);
  3959. hal_dump_comp_desc(tx_comp_hal_desc);
  3960. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  3961. /* When WBM sees NULL buffer_addr_info in any of
  3962. * ingress rings it sends an error indication,
  3963. * with wbm_internal_error=1, to a specific ring.
  3964. * The WBM2SW ring used to indicate these errors is
  3965. * fixed in HW, and that ring is being used as Tx
  3966. * completion ring. These errors are not related to
  3967. * Tx completions, and should just be ignored
  3968. */
  3969. wbm_internal_error = hal_get_wbm_internal_error(
  3970. soc->hal_soc,
  3971. tx_comp_hal_desc);
  3972. if (wbm_internal_error) {
  3973. dp_err_rl("Tx comp wbm_internal_error!!");
  3974. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  3975. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  3976. buffer_src)
  3977. dp_handle_wbm_internal_error(
  3978. soc,
  3979. tx_comp_hal_desc,
  3980. hal_tx_comp_get_buffer_type(
  3981. tx_comp_hal_desc));
  3982. } else {
  3983. dp_err_rl("Tx comp wbm_internal_error false");
  3984. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  3985. }
  3986. continue;
  3987. }
  3988. /* Get descriptor id */
  3989. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  3990. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3991. DP_TX_DESC_ID_POOL_OS;
  3992. /* Find Tx descriptor */
  3993. tx_desc = dp_tx_desc_find(soc, pool_id,
  3994. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3995. DP_TX_DESC_ID_PAGE_OS,
  3996. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3997. DP_TX_DESC_ID_OFFSET_OS);
  3998. /*
  3999. * If the release source is FW, process the HTT status
  4000. */
  4001. if (qdf_unlikely(buffer_src ==
  4002. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  4003. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  4004. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  4005. htt_tx_status);
  4006. dp_tx_process_htt_completion(soc, tx_desc,
  4007. htt_tx_status, ring_id);
  4008. } else {
  4009. tx_desc->peer_id =
  4010. hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  4011. tx_desc->tx_status =
  4012. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  4013. /*
  4014. * If the fast completion mode is enabled extended
  4015. * metadata from descriptor is not copied
  4016. */
  4017. if (qdf_likely(tx_desc->flags &
  4018. DP_TX_DESC_FLAG_SIMPLE))
  4019. goto add_to_pool;
  4020. /*
  4021. * If the descriptor is already freed in vdev_detach,
  4022. * continue to next descriptor
  4023. */
  4024. if (qdf_unlikely
  4025. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  4026. !tx_desc->flags)) {
  4027. QDF_TRACE(QDF_MODULE_ID_DP,
  4028. QDF_TRACE_LEVEL_INFO,
  4029. "Descriptor freed in vdev_detach %d",
  4030. tx_desc_id);
  4031. continue;
  4032. }
  4033. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  4034. QDF_TRACE(QDF_MODULE_ID_DP,
  4035. QDF_TRACE_LEVEL_INFO,
  4036. "pdev in down state %d",
  4037. tx_desc_id);
  4038. dp_tx_comp_free_buf(soc, tx_desc);
  4039. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  4040. goto next_desc;
  4041. }
  4042. /* Pool id is not matching. Error */
  4043. if (tx_desc->pool_id != pool_id) {
  4044. QDF_TRACE(QDF_MODULE_ID_DP,
  4045. QDF_TRACE_LEVEL_FATAL,
  4046. "Tx Comp pool id %d not matched %d",
  4047. pool_id, tx_desc->pool_id);
  4048. qdf_assert_always(0);
  4049. }
  4050. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  4051. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  4052. QDF_TRACE(QDF_MODULE_ID_DP,
  4053. QDF_TRACE_LEVEL_FATAL,
  4054. "Txdesc invalid, flgs = %x,id = %d",
  4055. tx_desc->flags, tx_desc_id);
  4056. qdf_assert_always(0);
  4057. }
  4058. /* Collect hw completion contents */
  4059. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4060. &tx_desc->comp, 1);
  4061. add_to_pool:
  4062. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  4063. /* First ring descriptor on the cycle */
  4064. if (!head_desc) {
  4065. head_desc = tx_desc;
  4066. tail_desc = tx_desc;
  4067. }
  4068. tail_desc->next = tx_desc;
  4069. tx_desc->next = NULL;
  4070. tail_desc = tx_desc;
  4071. }
  4072. next_desc:
  4073. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  4074. /*
  4075. * Processed packet count is more than given quota
  4076. * stop to processing
  4077. */
  4078. count++;
  4079. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  4080. break;
  4081. }
  4082. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  4083. /* Process the reaped descriptors */
  4084. if (head_desc)
  4085. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  4086. if (dp_tx_comp_enable_eol_data_check(soc)) {
  4087. if (num_processed >= quota)
  4088. force_break = true;
  4089. if (!force_break &&
  4090. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  4091. hal_ring_hdl)) {
  4092. DP_STATS_INC(soc, tx.hp_oos2, 1);
  4093. if (!hif_exec_should_yield(soc->hif_handle,
  4094. int_ctx->dp_intr_id))
  4095. goto more_data;
  4096. }
  4097. }
  4098. DP_TX_HIST_STATS_PER_PDEV();
  4099. return num_processed;
  4100. }
  4101. #ifdef FEATURE_WLAN_TDLS
  4102. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4103. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  4104. {
  4105. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4106. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4107. DP_MOD_ID_TDLS);
  4108. if (!vdev) {
  4109. dp_err("vdev handle for id %d is NULL", vdev_id);
  4110. return NULL;
  4111. }
  4112. if (tx_spec & OL_TX_SPEC_NO_FREE)
  4113. vdev->is_tdls_frame = true;
  4114. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  4115. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  4116. }
  4117. #endif
  4118. static void dp_tx_vdev_update_feature_flags(struct dp_vdev *vdev)
  4119. {
  4120. struct wlan_cfg_dp_soc_ctxt *cfg;
  4121. struct dp_soc *soc;
  4122. soc = vdev->pdev->soc;
  4123. if (!soc)
  4124. return;
  4125. cfg = soc->wlan_cfg_ctx;
  4126. if (!cfg)
  4127. return;
  4128. if (vdev->opmode == wlan_op_mode_ndi)
  4129. vdev->csum_enabled = wlan_cfg_get_nan_checksum_offload(cfg);
  4130. else if ((vdev->subtype == wlan_op_subtype_p2p_device) ||
  4131. (vdev->subtype == wlan_op_subtype_p2p_cli) ||
  4132. (vdev->subtype == wlan_op_subtype_p2p_go))
  4133. vdev->csum_enabled = wlan_cfg_get_p2p_checksum_offload(cfg);
  4134. else
  4135. vdev->csum_enabled = wlan_cfg_get_checksum_offload(cfg);
  4136. }
  4137. /**
  4138. * dp_tx_vdev_attach() - attach vdev to dp tx
  4139. * @vdev: virtual device instance
  4140. *
  4141. * Return: QDF_STATUS_SUCCESS: success
  4142. * QDF_STATUS_E_RESOURCES: Error return
  4143. */
  4144. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4145. {
  4146. int pdev_id;
  4147. /*
  4148. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4149. */
  4150. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4151. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  4152. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4153. vdev->vdev_id);
  4154. pdev_id =
  4155. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4156. vdev->pdev->pdev_id);
  4157. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4158. /*
  4159. * Set HTT Extension Valid bit to 0 by default
  4160. */
  4161. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4162. dp_tx_vdev_update_search_flags(vdev);
  4163. dp_tx_vdev_update_feature_flags(vdev);
  4164. return QDF_STATUS_SUCCESS;
  4165. }
  4166. #ifndef FEATURE_WDS
  4167. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4168. {
  4169. return false;
  4170. }
  4171. #endif
  4172. /**
  4173. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4174. * @vdev: virtual device instance
  4175. *
  4176. * Return: void
  4177. *
  4178. */
  4179. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4180. {
  4181. struct dp_soc *soc = vdev->pdev->soc;
  4182. /*
  4183. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4184. * for TDLS link
  4185. *
  4186. * Enable AddrY (SA based search) only for non-WDS STA and
  4187. * ProxySTA VAP (in HKv1) modes.
  4188. *
  4189. * In all other VAP modes, only DA based search should be
  4190. * enabled
  4191. */
  4192. if (vdev->opmode == wlan_op_mode_sta &&
  4193. vdev->tdls_link_connected)
  4194. vdev->hal_desc_addr_search_flags =
  4195. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4196. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4197. !dp_tx_da_search_override(vdev))
  4198. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4199. else
  4200. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4201. /* Set search type only when peer map v2 messaging is enabled
  4202. * as we will have the search index (AST hash) only when v2 is
  4203. * enabled
  4204. */
  4205. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  4206. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  4207. else
  4208. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4209. }
  4210. static inline bool
  4211. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4212. struct dp_vdev *vdev,
  4213. struct dp_tx_desc_s *tx_desc)
  4214. {
  4215. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4216. return false;
  4217. /*
  4218. * if vdev is given, then only check whether desc
  4219. * vdev match. if vdev is NULL, then check whether
  4220. * desc pdev match.
  4221. */
  4222. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4223. (tx_desc->pdev == pdev);
  4224. }
  4225. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4226. /**
  4227. * dp_tx_desc_flush() - release resources associated
  4228. * to TX Desc
  4229. *
  4230. * @dp_pdev: Handle to DP pdev structure
  4231. * @vdev: virtual device instance
  4232. * NULL: no specific Vdev is required and check all allcated TX desc
  4233. * on this pdev.
  4234. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4235. *
  4236. * @force_free:
  4237. * true: flush the TX desc.
  4238. * false: only reset the Vdev in each allocated TX desc
  4239. * that associated to current Vdev.
  4240. *
  4241. * This function will go through the TX desc pool to flush
  4242. * the outstanding TX data or reset Vdev to NULL in associated TX
  4243. * Desc.
  4244. */
  4245. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4246. bool force_free)
  4247. {
  4248. uint8_t i;
  4249. uint32_t j;
  4250. uint32_t num_desc, page_id, offset;
  4251. uint16_t num_desc_per_page;
  4252. struct dp_soc *soc = pdev->soc;
  4253. struct dp_tx_desc_s *tx_desc = NULL;
  4254. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4255. if (!vdev && !force_free) {
  4256. dp_err("Reset TX desc vdev, Vdev param is required!");
  4257. return;
  4258. }
  4259. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4260. tx_desc_pool = &soc->tx_desc[i];
  4261. if (!(tx_desc_pool->pool_size) ||
  4262. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4263. !(tx_desc_pool->desc_pages.cacheable_pages))
  4264. continue;
  4265. /*
  4266. * Add flow pool lock protection in case pool is freed
  4267. * due to all tx_desc is recycled when handle TX completion.
  4268. * this is not necessary when do force flush as:
  4269. * a. double lock will happen if dp_tx_desc_release is
  4270. * also trying to acquire it.
  4271. * b. dp interrupt has been disabled before do force TX desc
  4272. * flush in dp_pdev_deinit().
  4273. */
  4274. if (!force_free)
  4275. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4276. num_desc = tx_desc_pool->pool_size;
  4277. num_desc_per_page =
  4278. tx_desc_pool->desc_pages.num_element_per_page;
  4279. for (j = 0; j < num_desc; j++) {
  4280. page_id = j / num_desc_per_page;
  4281. offset = j % num_desc_per_page;
  4282. if (qdf_unlikely(!(tx_desc_pool->
  4283. desc_pages.cacheable_pages)))
  4284. break;
  4285. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4286. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4287. /*
  4288. * Free TX desc if force free is
  4289. * required, otherwise only reset vdev
  4290. * in this TX desc.
  4291. */
  4292. if (force_free) {
  4293. dp_tx_comp_free_buf(soc, tx_desc);
  4294. dp_tx_desc_release(tx_desc, i);
  4295. } else {
  4296. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4297. }
  4298. }
  4299. }
  4300. if (!force_free)
  4301. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4302. }
  4303. }
  4304. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4305. /**
  4306. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4307. *
  4308. * @soc: Handle to DP soc structure
  4309. * @tx_desc: pointer of one TX desc
  4310. * @desc_pool_id: TX Desc pool id
  4311. */
  4312. static inline void
  4313. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4314. uint8_t desc_pool_id)
  4315. {
  4316. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4317. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4318. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4319. }
  4320. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4321. bool force_free)
  4322. {
  4323. uint8_t i, num_pool;
  4324. uint32_t j;
  4325. uint32_t num_desc, page_id, offset;
  4326. uint16_t num_desc_per_page;
  4327. struct dp_soc *soc = pdev->soc;
  4328. struct dp_tx_desc_s *tx_desc = NULL;
  4329. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4330. if (!vdev && !force_free) {
  4331. dp_err("Reset TX desc vdev, Vdev param is required!");
  4332. return;
  4333. }
  4334. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4335. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4336. for (i = 0; i < num_pool; i++) {
  4337. tx_desc_pool = &soc->tx_desc[i];
  4338. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4339. continue;
  4340. num_desc_per_page =
  4341. tx_desc_pool->desc_pages.num_element_per_page;
  4342. for (j = 0; j < num_desc; j++) {
  4343. page_id = j / num_desc_per_page;
  4344. offset = j % num_desc_per_page;
  4345. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4346. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4347. if (force_free) {
  4348. dp_tx_comp_free_buf(soc, tx_desc);
  4349. dp_tx_desc_release(tx_desc, i);
  4350. } else {
  4351. dp_tx_desc_reset_vdev(soc, tx_desc,
  4352. i);
  4353. }
  4354. }
  4355. }
  4356. }
  4357. }
  4358. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4359. /**
  4360. * dp_tx_vdev_detach() - detach vdev from dp tx
  4361. * @vdev: virtual device instance
  4362. *
  4363. * Return: QDF_STATUS_SUCCESS: success
  4364. * QDF_STATUS_E_RESOURCES: Error return
  4365. */
  4366. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4367. {
  4368. struct dp_pdev *pdev = vdev->pdev;
  4369. /* Reset TX desc associated to this Vdev as NULL */
  4370. dp_tx_desc_flush(pdev, vdev, false);
  4371. dp_tx_vdev_multipass_deinit(vdev);
  4372. return QDF_STATUS_SUCCESS;
  4373. }
  4374. /**
  4375. * dp_tx_pdev_attach() - attach pdev to dp tx
  4376. * @pdev: physical device instance
  4377. *
  4378. * Return: QDF_STATUS_SUCCESS: success
  4379. * QDF_STATUS_E_RESOURCES: Error return
  4380. */
  4381. QDF_STATUS dp_tx_pdev_init(struct dp_pdev *pdev)
  4382. {
  4383. struct dp_soc *soc = pdev->soc;
  4384. /* Initialize Flow control counters */
  4385. qdf_atomic_init(&pdev->num_tx_outstanding);
  4386. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  4387. /* Initialize descriptors in TCL Ring */
  4388. hal_tx_init_data_ring(soc->hal_soc,
  4389. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  4390. }
  4391. return QDF_STATUS_SUCCESS;
  4392. }
  4393. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4394. /* Pools will be allocated dynamically */
  4395. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4396. int num_desc)
  4397. {
  4398. uint8_t i;
  4399. for (i = 0; i < num_pool; i++) {
  4400. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4401. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4402. }
  4403. return QDF_STATUS_SUCCESS;
  4404. }
  4405. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4406. int num_desc)
  4407. {
  4408. return QDF_STATUS_SUCCESS;
  4409. }
  4410. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4411. {
  4412. }
  4413. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4414. {
  4415. uint8_t i;
  4416. for (i = 0; i < num_pool; i++)
  4417. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4418. }
  4419. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4420. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4421. int num_desc)
  4422. {
  4423. uint8_t i, count;
  4424. /* Allocate software Tx descriptor pools */
  4425. for (i = 0; i < num_pool; i++) {
  4426. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4427. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4428. FL("Tx Desc Pool alloc %d failed %pK"),
  4429. i, soc);
  4430. goto fail;
  4431. }
  4432. }
  4433. return QDF_STATUS_SUCCESS;
  4434. fail:
  4435. for (count = 0; count < i; count++)
  4436. dp_tx_desc_pool_free(soc, count);
  4437. return QDF_STATUS_E_NOMEM;
  4438. }
  4439. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4440. int num_desc)
  4441. {
  4442. uint8_t i;
  4443. for (i = 0; i < num_pool; i++) {
  4444. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4445. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4446. FL("Tx Desc Pool init %d failed %pK"),
  4447. i, soc);
  4448. return QDF_STATUS_E_NOMEM;
  4449. }
  4450. }
  4451. return QDF_STATUS_SUCCESS;
  4452. }
  4453. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4454. {
  4455. uint8_t i;
  4456. for (i = 0; i < num_pool; i++)
  4457. dp_tx_desc_pool_deinit(soc, i);
  4458. }
  4459. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4460. {
  4461. uint8_t i;
  4462. for (i = 0; i < num_pool; i++)
  4463. dp_tx_desc_pool_free(soc, i);
  4464. }
  4465. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4466. /**
  4467. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4468. * @soc: core txrx main context
  4469. * @num_pool: number of pools
  4470. *
  4471. */
  4472. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4473. {
  4474. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4475. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4476. }
  4477. /**
  4478. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4479. * @soc: core txrx main context
  4480. * @num_pool: number of pools
  4481. *
  4482. */
  4483. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4484. {
  4485. dp_tx_tso_desc_pool_free(soc, num_pool);
  4486. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4487. }
  4488. /**
  4489. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4490. * @soc: core txrx main context
  4491. *
  4492. * This function frees all tx related descriptors as below
  4493. * 1. Regular TX descriptors (static pools)
  4494. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4495. * 3. TSO descriptors
  4496. *
  4497. */
  4498. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4499. {
  4500. uint8_t num_pool;
  4501. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4502. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4503. dp_tx_ext_desc_pool_free(soc, num_pool);
  4504. dp_tx_delete_static_pools(soc, num_pool);
  4505. }
  4506. /**
  4507. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4508. * @soc: core txrx main context
  4509. *
  4510. * This function de-initializes all tx related descriptors as below
  4511. * 1. Regular TX descriptors (static pools)
  4512. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4513. * 3. TSO descriptors
  4514. *
  4515. */
  4516. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4517. {
  4518. uint8_t num_pool;
  4519. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4520. dp_tx_flow_control_deinit(soc);
  4521. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4522. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4523. dp_tx_deinit_static_pools(soc, num_pool);
  4524. }
  4525. /**
  4526. * dp_tso_attach() - TSO attach handler
  4527. * @txrx_soc: Opaque Dp handle
  4528. *
  4529. * Reserve TSO descriptor buffers
  4530. *
  4531. * Return: QDF_STATUS_E_FAILURE on failure or
  4532. * QDF_STATUS_SUCCESS on success
  4533. */
  4534. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4535. uint8_t num_pool,
  4536. uint16_t num_desc)
  4537. {
  4538. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4539. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4540. return QDF_STATUS_E_FAILURE;
  4541. }
  4542. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4543. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4544. num_pool, soc);
  4545. return QDF_STATUS_E_FAILURE;
  4546. }
  4547. return QDF_STATUS_SUCCESS;
  4548. }
  4549. /**
  4550. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4551. * @soc: DP soc handle
  4552. * @num_pool: Number of pools
  4553. * @num_desc: Number of descriptors
  4554. *
  4555. * Initialize TSO descriptor pools
  4556. *
  4557. * Return: QDF_STATUS_E_FAILURE on failure or
  4558. * QDF_STATUS_SUCCESS on success
  4559. */
  4560. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4561. uint8_t num_pool,
  4562. uint16_t num_desc)
  4563. {
  4564. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4565. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4566. return QDF_STATUS_E_FAILURE;
  4567. }
  4568. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4569. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4570. num_pool, soc);
  4571. return QDF_STATUS_E_FAILURE;
  4572. }
  4573. return QDF_STATUS_SUCCESS;
  4574. }
  4575. /**
  4576. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4577. * @soc: core txrx main context
  4578. *
  4579. * This function allocates memory for following descriptor pools
  4580. * 1. regular sw tx descriptor pools (static pools)
  4581. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4582. * 3. TSO descriptor pools
  4583. *
  4584. * Return: QDF_STATUS_SUCCESS: success
  4585. * QDF_STATUS_E_RESOURCES: Error return
  4586. */
  4587. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4588. {
  4589. uint8_t num_pool;
  4590. uint32_t num_desc;
  4591. uint32_t num_ext_desc;
  4592. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4593. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4594. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4595. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4596. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4597. __func__, num_pool, num_desc);
  4598. if ((num_pool > MAX_TXDESC_POOLS) ||
  4599. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4600. goto fail1;
  4601. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4602. goto fail1;
  4603. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4604. goto fail2;
  4605. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4606. return QDF_STATUS_SUCCESS;
  4607. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4608. goto fail3;
  4609. return QDF_STATUS_SUCCESS;
  4610. fail3:
  4611. dp_tx_ext_desc_pool_free(soc, num_pool);
  4612. fail2:
  4613. dp_tx_delete_static_pools(soc, num_pool);
  4614. fail1:
  4615. return QDF_STATUS_E_RESOURCES;
  4616. }
  4617. /**
  4618. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4619. * @soc: core txrx main context
  4620. *
  4621. * This function initializes the following TX descriptor pools
  4622. * 1. regular sw tx descriptor pools (static pools)
  4623. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4624. * 3. TSO descriptor pools
  4625. *
  4626. * Return: QDF_STATUS_SUCCESS: success
  4627. * QDF_STATUS_E_RESOURCES: Error return
  4628. */
  4629. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4630. {
  4631. uint8_t num_pool;
  4632. uint32_t num_desc;
  4633. uint32_t num_ext_desc;
  4634. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4635. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4636. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4637. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4638. goto fail1;
  4639. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4640. goto fail2;
  4641. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4642. return QDF_STATUS_SUCCESS;
  4643. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4644. goto fail3;
  4645. dp_tx_flow_control_init(soc);
  4646. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4647. return QDF_STATUS_SUCCESS;
  4648. fail3:
  4649. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4650. fail2:
  4651. dp_tx_deinit_static_pools(soc, num_pool);
  4652. fail1:
  4653. return QDF_STATUS_E_RESOURCES;
  4654. }
  4655. /**
  4656. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4657. * @txrx_soc: dp soc handle
  4658. *
  4659. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4660. * QDF_STATUS_E_FAILURE
  4661. */
  4662. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4663. {
  4664. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4665. uint8_t num_pool;
  4666. uint32_t num_desc;
  4667. uint32_t num_ext_desc;
  4668. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4669. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4670. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4671. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4672. return QDF_STATUS_E_FAILURE;
  4673. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4674. return QDF_STATUS_E_FAILURE;
  4675. return QDF_STATUS_SUCCESS;
  4676. }
  4677. /**
  4678. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4679. * @txrx_soc: dp soc handle
  4680. *
  4681. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4682. */
  4683. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4684. {
  4685. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4686. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4687. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4688. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4689. return QDF_STATUS_SUCCESS;
  4690. }