wcd937x.c 83 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <linux/regmap.h>
  13. #include <linux/pm_runtime.h>
  14. #include <sound/soc.h>
  15. #include <sound/tlv.h>
  16. #include <soc/soundwire.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include "internal.h"
  20. #include "wcd937x.h"
  21. #include <asoc/wcdcal-hwdep.h>
  22. #include "wcd937x-registers.h"
  23. #include <asoc/msm-cdc-pinctrl.h>
  24. #include <dt-bindings/sound/audio-codec-port-types.h>
  25. #include <asoc/msm-cdc-supply.h>
  26. #define DRV_NAME "wcd937x_codec"
  27. #define WCD9370_VARIANT 0
  28. #define WCD9375_VARIANT 5
  29. #define WCD937X_VARIANT_ENTRY_SIZE 32
  30. #define NUM_SWRS_DT_PARAMS 5
  31. #define WCD937X_VERSION_1_0 1
  32. #define WCD937X_VERSION_ENTRY_SIZE 32
  33. #define EAR_RX_PATH_AUX 1
  34. enum {
  35. CODEC_TX = 0,
  36. CODEC_RX,
  37. };
  38. enum {
  39. ALLOW_BUCK_DISABLE,
  40. HPH_COMP_DELAY,
  41. HPH_PA_DELAY,
  42. };
  43. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  44. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  45. static int wcd937x_handle_post_irq(void *data);
  46. static int wcd937x_reset(struct device *dev);
  47. static int wcd937x_reset_low(struct device *dev);
  48. static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = {
  49. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  50. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  51. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  52. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  53. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, 0x10),
  54. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, 0x20),
  55. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, 0x40),
  56. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, 0x80),
  57. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, 0x01),
  58. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, 0x02),
  59. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, 0x04),
  60. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, 0x08),
  61. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, 0x10),
  62. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  63. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  64. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  65. REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, 0x01),
  66. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  67. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  68. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  69. };
  70. static struct regmap_irq_chip wcd937x_regmap_irq_chip = {
  71. .name = "wcd937x",
  72. .irqs = wcd937x_irqs,
  73. .num_irqs = ARRAY_SIZE(wcd937x_irqs),
  74. .num_regs = 3,
  75. .status_base = WCD937X_DIGITAL_INTR_STATUS_0,
  76. .mask_base = WCD937X_DIGITAL_INTR_MASK_0,
  77. .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0,
  78. .use_ack = 1,
  79. .type_base = WCD937X_DIGITAL_INTR_LEVEL_0,
  80. .runtime_pm = false,
  81. .handle_post_irq = wcd937x_handle_post_irq,
  82. .irq_drv_data = NULL,
  83. };
  84. static int wcd937x_handle_post_irq(void *data)
  85. {
  86. struct wcd937x_priv *wcd937x = data;
  87. u32 status1 = 0, status2 = 0, status3 = 0;
  88. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_0, &status1);
  89. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_1, &status2);
  90. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_2, &status3);
  91. wcd937x->tx_swr_dev->slave_irq_pending =
  92. ((status1 || status2 || status3) ? true : false);
  93. return IRQ_HANDLED;
  94. }
  95. static int wcd937x_init_reg(struct snd_soc_component *component)
  96. {
  97. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  98. 0x0E, 0x0E);
  99. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  100. 0x80, 0x80);
  101. usleep_range(1000, 1010);
  102. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  103. 0x40, 0x40);
  104. usleep_range(1000, 1010);
  105. snd_soc_component_update_bits(component, WCD937X_LDORXTX_CONFIG,
  106. 0x10, 0x00);
  107. snd_soc_component_update_bits(component, WCD937X_BIAS_VBG_FINE_ADJ,
  108. 0xF0, 0x80);
  109. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  110. 0x80, 0x80);
  111. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  112. 0x40, 0x40);
  113. usleep_range(10000, 10010);
  114. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  115. 0x40, 0x00);
  116. snd_soc_component_update_bits(component,
  117. WCD937X_HPH_SURGE_HPHLR_SURGE_EN,
  118. 0xFF, 0xD9);
  119. snd_soc_component_update_bits(component, WCD937X_MICB1_TEST_CTL_1,
  120. 0xFF, 0xFA);
  121. snd_soc_component_update_bits(component, WCD937X_MICB2_TEST_CTL_1,
  122. 0xFF, 0xFA);
  123. snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_1,
  124. 0xFF, 0xFA);
  125. return 0;
  126. }
  127. static int wcd937x_set_port_params(struct snd_soc_component *component,
  128. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  129. u8 *ch_mask, u32 *ch_rate,
  130. u8 *port_type, u8 path)
  131. {
  132. int i, j;
  133. u8 num_ports = 0;
  134. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  135. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  136. switch (path) {
  137. case CODEC_RX:
  138. map = &wcd937x->rx_port_mapping;
  139. num_ports = wcd937x->num_rx_ports;
  140. break;
  141. case CODEC_TX:
  142. map = &wcd937x->tx_port_mapping;
  143. num_ports = wcd937x->num_tx_ports;
  144. break;
  145. }
  146. for (i = 0; i <= num_ports; i++) {
  147. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  148. if ((*map)[i][j].slave_port_type == slv_prt_type)
  149. goto found;
  150. }
  151. }
  152. found:
  153. if (i > num_ports || j == MAX_CH_PER_PORT) {
  154. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  155. __func__, slv_prt_type);
  156. return -EINVAL;
  157. }
  158. *port_id = i;
  159. *num_ch = (*map)[i][j].num_ch;
  160. *ch_mask = (*map)[i][j].ch_mask;
  161. *ch_rate = (*map)[i][j].ch_rate;
  162. *port_type = (*map)[i][j].master_port_type;
  163. return 0;
  164. }
  165. static int wcd937x_parse_port_mapping(struct device *dev,
  166. char *prop, u8 path)
  167. {
  168. u32 *dt_array, map_size, map_length;
  169. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  170. u32 slave_port_type, master_port_type;
  171. u32 i, ch_iter = 0;
  172. int ret = 0;
  173. u8 *num_ports = NULL;
  174. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  175. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  176. switch (path) {
  177. case CODEC_RX:
  178. map = &wcd937x->rx_port_mapping;
  179. num_ports = &wcd937x->num_rx_ports;
  180. break;
  181. case CODEC_TX:
  182. map = &wcd937x->tx_port_mapping;
  183. num_ports = &wcd937x->num_tx_ports;
  184. break;
  185. }
  186. if (!of_find_property(dev->of_node, prop,
  187. &map_size)) {
  188. dev_err(dev, "missing port mapping prop %s\n", prop);
  189. ret = -EINVAL;
  190. goto err;
  191. }
  192. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  193. dt_array = kzalloc(map_size, GFP_KERNEL);
  194. if (!dt_array) {
  195. ret = -ENOMEM;
  196. goto err;
  197. }
  198. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  199. NUM_SWRS_DT_PARAMS * map_length);
  200. if (ret) {
  201. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  202. __func__, prop);
  203. ret = -EINVAL;
  204. goto err_pdata_fail;
  205. }
  206. for (i = 0; i < map_length; i++) {
  207. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  208. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  209. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  210. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  211. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  212. if (port_num != old_port_num)
  213. ch_iter = 0;
  214. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  215. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  216. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  217. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  218. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  219. old_port_num = port_num;
  220. }
  221. *num_ports = port_num;
  222. kfree(dt_array);
  223. return 0;
  224. err_pdata_fail:
  225. kfree(dt_array);
  226. err:
  227. return ret;
  228. }
  229. static int wcd937x_tx_connect_port(struct snd_soc_component *component,
  230. u8 slv_port_type, u8 enable)
  231. {
  232. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  233. u8 port_id;
  234. u8 num_ch;
  235. u8 ch_mask;
  236. u32 ch_rate;
  237. u8 port_type;
  238. u8 num_port = 1;
  239. int ret = 0;
  240. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  241. &num_ch, &ch_mask, &ch_rate,
  242. &port_type, CODEC_TX);
  243. if (ret)
  244. return ret;
  245. if (enable)
  246. ret = swr_connect_port(wcd937x->tx_swr_dev, &port_id,
  247. num_port, &ch_mask, &ch_rate,
  248. &num_ch, &port_type);
  249. else
  250. ret = swr_disconnect_port(wcd937x->tx_swr_dev, &port_id,
  251. num_port, &ch_mask, &port_type);
  252. return ret;
  253. }
  254. static int wcd937x_rx_connect_port(struct snd_soc_component *component,
  255. u8 slv_port_type, u8 enable)
  256. {
  257. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  258. u8 port_id;
  259. u8 num_ch;
  260. u8 ch_mask;
  261. u32 ch_rate;
  262. u8 port_type;
  263. u8 num_port = 1;
  264. int ret = 0;
  265. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  266. &num_ch, &ch_mask, &ch_rate,
  267. &port_type, CODEC_RX);
  268. if (ret)
  269. return ret;
  270. if (enable)
  271. ret = swr_connect_port(wcd937x->rx_swr_dev, &port_id,
  272. num_port, &ch_mask, &ch_rate,
  273. &num_ch, &port_type);
  274. else
  275. ret = swr_disconnect_port(wcd937x->rx_swr_dev, &port_id,
  276. num_port, &ch_mask, &port_type);
  277. return ret;
  278. }
  279. static int wcd937x_rx_clk_enable(struct snd_soc_component *component)
  280. {
  281. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  282. if (wcd937x->rx_clk_cnt == 0) {
  283. snd_soc_component_update_bits(component,
  284. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x08, 0x08);
  285. snd_soc_component_update_bits(component,
  286. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  287. snd_soc_component_update_bits(component,
  288. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x01);
  289. snd_soc_component_update_bits(component,
  290. WCD937X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  291. snd_soc_component_update_bits(component,
  292. WCD937X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  293. snd_soc_component_update_bits(component,
  294. WCD937X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  295. snd_soc_component_update_bits(component,
  296. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  297. }
  298. wcd937x->rx_clk_cnt++;
  299. return 0;
  300. }
  301. static int wcd937x_rx_clk_disable(struct snd_soc_component *component)
  302. {
  303. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  304. if (wcd937x->rx_clk_cnt == 0) {
  305. dev_dbg(wcd937x->dev, "%s:clk already disabled\n", __func__);
  306. return 0;
  307. }
  308. wcd937x->rx_clk_cnt--;
  309. if (wcd937x->rx_clk_cnt == 0) {
  310. snd_soc_component_update_bits(component,
  311. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x00);
  312. snd_soc_component_update_bits(component,
  313. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  314. 0x02, 0x00);
  315. snd_soc_component_update_bits(component,
  316. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  317. 0x01, 0x00);
  318. }
  319. return 0;
  320. }
  321. /*
  322. * wcd937x_soc_get_mbhc: get wcd937x_mbhc handle of corresponding component
  323. * @component: handle to snd_soc_component *
  324. *
  325. * return wcd937x_mbhc handle or error code in case of failure
  326. */
  327. struct wcd937x_mbhc *wcd937x_soc_get_mbhc(struct snd_soc_component *component)
  328. {
  329. struct wcd937x_priv *wcd937x;
  330. if (!component) {
  331. pr_err("%s: Invalid params, NULL component\n", __func__);
  332. return NULL;
  333. }
  334. wcd937x = snd_soc_component_get_drvdata(component);
  335. if (!wcd937x) {
  336. pr_err("%s: Invalid params, NULL tavil\n", __func__);
  337. return NULL;
  338. }
  339. return wcd937x->mbhc;
  340. }
  341. EXPORT_SYMBOL(wcd937x_soc_get_mbhc);
  342. static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  343. struct snd_kcontrol *kcontrol,
  344. int event)
  345. {
  346. struct snd_soc_component *component =
  347. snd_soc_dapm_to_component(w->dapm);
  348. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  349. int hph_mode = wcd937x->hph_mode;
  350. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  351. w->name, event);
  352. switch (event) {
  353. case SND_SOC_DAPM_PRE_PMU:
  354. wcd937x_rx_clk_enable(component);
  355. snd_soc_component_update_bits(component,
  356. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  357. 0x01, 0x01);
  358. snd_soc_component_update_bits(component,
  359. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  360. 0x04, 0x04);
  361. snd_soc_component_update_bits(component,
  362. WCD937X_HPH_RDAC_CLK_CTL1,
  363. 0x80, 0x00);
  364. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  365. break;
  366. case SND_SOC_DAPM_POST_PMU:
  367. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  368. snd_soc_component_update_bits(component,
  369. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  370. 0x0F, 0x02);
  371. else if (hph_mode == CLS_H_LOHIFI)
  372. snd_soc_component_update_bits(component,
  373. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  374. 0x0F, 0x06);
  375. if (wcd937x->comp1_enable) {
  376. snd_soc_component_update_bits(component,
  377. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  378. 0x02, 0x02);
  379. snd_soc_component_update_bits(component,
  380. WCD937X_HPH_L_EN, 0x20, 0x00);
  381. if (wcd937x->comp2_enable) {
  382. snd_soc_component_update_bits(component,
  383. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  384. 0x01, 0x01);
  385. snd_soc_component_update_bits(component,
  386. WCD937X_HPH_R_EN, 0x20, 0x00);
  387. }
  388. /*
  389. * 5ms sleep is required after COMP is enabled as per
  390. * HW requirement
  391. */
  392. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  393. usleep_range(5000, 5100);
  394. clear_bit(HPH_COMP_DELAY,
  395. &wcd937x->status_mask);
  396. }
  397. } else {
  398. snd_soc_component_update_bits(component,
  399. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  400. 0x02, 0x00);
  401. snd_soc_component_update_bits(component,
  402. WCD937X_HPH_L_EN, 0x20, 0x20);
  403. }
  404. snd_soc_component_update_bits(component,
  405. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  406. break;
  407. case SND_SOC_DAPM_POST_PMD:
  408. snd_soc_component_update_bits(component,
  409. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  410. 0x0F, 0x01);
  411. break;
  412. }
  413. return 0;
  414. }
  415. static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  416. struct snd_kcontrol *kcontrol,
  417. int event)
  418. {
  419. struct snd_soc_component *component =
  420. snd_soc_dapm_to_component(w->dapm);
  421. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  422. int hph_mode = wcd937x->hph_mode;
  423. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  424. w->name, event);
  425. switch (event) {
  426. case SND_SOC_DAPM_PRE_PMU:
  427. wcd937x_rx_clk_enable(component);
  428. snd_soc_component_update_bits(component,
  429. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  430. snd_soc_component_update_bits(component,
  431. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  432. snd_soc_component_update_bits(component,
  433. WCD937X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  434. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  435. break;
  436. case SND_SOC_DAPM_POST_PMU:
  437. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  438. snd_soc_component_update_bits(component,
  439. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  440. 0x0F, 0x02);
  441. else if (hph_mode == CLS_H_LOHIFI)
  442. snd_soc_component_update_bits(component,
  443. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  444. 0x0F, 0x06);
  445. if (wcd937x->comp2_enable) {
  446. snd_soc_component_update_bits(component,
  447. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  448. 0x01, 0x01);
  449. snd_soc_component_update_bits(component,
  450. WCD937X_HPH_R_EN, 0x20, 0x00);
  451. if (wcd937x->comp1_enable) {
  452. snd_soc_component_update_bits(component,
  453. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  454. 0x02, 0x02);
  455. snd_soc_component_update_bits(component,
  456. WCD937X_HPH_L_EN, 0x20, 0x00);
  457. }
  458. /*
  459. * 5ms sleep is required after COMP is enabled as per
  460. * HW requirement
  461. */
  462. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  463. usleep_range(5000, 5100);
  464. clear_bit(HPH_COMP_DELAY,
  465. &wcd937x->status_mask);
  466. }
  467. } else {
  468. snd_soc_component_update_bits(component,
  469. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  470. 0x01, 0x00);
  471. snd_soc_component_update_bits(component,
  472. WCD937X_HPH_R_EN, 0x20, 0x20);
  473. }
  474. snd_soc_component_update_bits(component,
  475. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  476. break;
  477. case SND_SOC_DAPM_POST_PMD:
  478. snd_soc_component_update_bits(component,
  479. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  480. 0x0F, 0x01);
  481. break;
  482. }
  483. return 0;
  484. }
  485. static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  486. struct snd_kcontrol *kcontrol,
  487. int event)
  488. {
  489. struct snd_soc_component *component =
  490. snd_soc_dapm_to_component(w->dapm);
  491. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  492. int hph_mode = wcd937x->hph_mode;
  493. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  494. w->name, event);
  495. switch (event) {
  496. case SND_SOC_DAPM_PRE_PMU:
  497. wcd937x_rx_clk_enable(component);
  498. snd_soc_component_update_bits(component,
  499. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  500. 0x04, 0x04);
  501. snd_soc_component_update_bits(component,
  502. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  503. 0x01, 0x01);
  504. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  505. snd_soc_component_update_bits(component,
  506. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  507. 0x0F, 0x02);
  508. else if (hph_mode == CLS_H_LOHIFI)
  509. snd_soc_component_update_bits(component,
  510. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  511. 0x0F, 0x06);
  512. snd_soc_component_update_bits(component,
  513. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  514. 0x02, 0x02);
  515. usleep_range(5000, 5010);
  516. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  517. 0x04, 0x00);
  518. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  519. WCD_CLSH_EVENT_PRE_DAC,
  520. WCD_CLSH_STATE_EAR,
  521. hph_mode);
  522. break;
  523. case SND_SOC_DAPM_POST_PMD:
  524. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI ||
  525. hph_mode == CLS_H_HIFI)
  526. snd_soc_component_update_bits(component,
  527. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  528. 0x0F, 0x01);
  529. break;
  530. };
  531. return 0;
  532. }
  533. static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  534. struct snd_kcontrol *kcontrol,
  535. int event)
  536. {
  537. struct snd_soc_component *component =
  538. snd_soc_dapm_to_component(w->dapm);
  539. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  540. int hph_mode = wcd937x->hph_mode;
  541. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  542. w->name, event);
  543. switch (event) {
  544. case SND_SOC_DAPM_PRE_PMU:
  545. wcd937x_rx_clk_enable(component);
  546. snd_soc_component_update_bits(component,
  547. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  548. 0x04, 0x04);
  549. snd_soc_component_update_bits(component,
  550. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  551. 0x04, 0x04);
  552. snd_soc_component_update_bits(component,
  553. WCD937X_DIGITAL_CDC_AUX_GAIN_CTL,
  554. 0x01, 0x01);
  555. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  556. WCD_CLSH_EVENT_PRE_DAC,
  557. WCD_CLSH_STATE_AUX,
  558. hph_mode);
  559. break;
  560. case SND_SOC_DAPM_POST_PMD:
  561. wcd937x_rx_clk_disable(component);
  562. snd_soc_component_update_bits(component,
  563. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  564. 0x04, 0x00);
  565. break;
  566. };
  567. return 0;
  568. }
  569. static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  570. struct snd_kcontrol *kcontrol,
  571. int event)
  572. {
  573. struct snd_soc_component *component =
  574. snd_soc_dapm_to_component(w->dapm);
  575. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  576. int ret = 0;
  577. int hph_mode = wcd937x->hph_mode;
  578. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  579. w->name, event);
  580. switch (event) {
  581. case SND_SOC_DAPM_PRE_PMU:
  582. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  583. wcd937x->rx_swr_dev->dev_num,
  584. true);
  585. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  586. WCD_CLSH_EVENT_PRE_DAC,
  587. WCD_CLSH_STATE_HPHR,
  588. hph_mode);
  589. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  590. 0x10, 0x10);
  591. usleep_range(100, 110);
  592. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  593. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  594. wcd937x->rx_swr_dev->dev_num,
  595. true);
  596. snd_soc_component_update_bits(component,
  597. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  598. break;
  599. case SND_SOC_DAPM_POST_PMU:
  600. /*
  601. * 7ms sleep is required after PA is enabled as per
  602. * HW requirement. If compander is disabled, then
  603. * 20ms delay is required.
  604. */
  605. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  606. if (!wcd937x->comp2_enable)
  607. usleep_range(20000, 20100);
  608. else
  609. usleep_range(7000, 7100);
  610. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  611. }
  612. snd_soc_component_update_bits(component,
  613. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  614. 0x02, 0x02);
  615. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  616. snd_soc_component_update_bits(component,
  617. WCD937X_ANA_RX_SUPPLIES,
  618. 0x02, 0x02);
  619. if (wcd937x->update_wcd_event)
  620. wcd937x->update_wcd_event(wcd937x->handle,
  621. WCD_BOLERO_EVT_RX_MUTE,
  622. (WCD_RX2 << 0x10));
  623. break;
  624. case SND_SOC_DAPM_PRE_PMD:
  625. if (wcd937x->update_wcd_event)
  626. wcd937x->update_wcd_event(wcd937x->handle,
  627. WCD_BOLERO_EVT_RX_MUTE,
  628. (WCD_RX2 << 0x10 | 0x1));
  629. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  630. WCD_EVENT_PRE_HPHR_PA_OFF,
  631. &wcd937x->mbhc->wcd_mbhc);
  632. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  633. break;
  634. case SND_SOC_DAPM_POST_PMD:
  635. /*
  636. * 7ms sleep is required after PA is disabled as per
  637. * HW requirement. If compander is disabled, then
  638. * 20ms delay is required.
  639. */
  640. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  641. if (!wcd937x->comp2_enable)
  642. usleep_range(20000, 20100);
  643. else
  644. usleep_range(7000, 7100);
  645. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  646. }
  647. snd_soc_component_update_bits(component,
  648. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  649. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  650. WCD_EVENT_POST_HPHR_PA_OFF,
  651. &wcd937x->mbhc->wcd_mbhc);
  652. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  653. 0x10, 0x00);
  654. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  655. WCD_CLSH_EVENT_POST_PA,
  656. WCD_CLSH_STATE_HPHR,
  657. hph_mode);
  658. break;
  659. };
  660. return ret;
  661. }
  662. static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  663. struct snd_kcontrol *kcontrol,
  664. int event)
  665. {
  666. struct snd_soc_component *component =
  667. snd_soc_dapm_to_component(w->dapm);
  668. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  669. int ret = 0;
  670. int hph_mode = wcd937x->hph_mode;
  671. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  672. w->name, event);
  673. switch (event) {
  674. case SND_SOC_DAPM_PRE_PMU:
  675. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  676. wcd937x->rx_swr_dev->dev_num,
  677. true);
  678. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  679. WCD_CLSH_EVENT_PRE_DAC,
  680. WCD_CLSH_STATE_HPHL,
  681. hph_mode);
  682. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  683. 0x20, 0x20);
  684. usleep_range(100, 110);
  685. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  686. snd_soc_component_update_bits(component,
  687. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  688. break;
  689. case SND_SOC_DAPM_POST_PMU:
  690. /*
  691. * 7ms sleep is required after PA is enabled as per
  692. * HW requirement. If compander is disabled, then
  693. * 20ms delay is required.
  694. */
  695. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  696. if (!wcd937x->comp1_enable)
  697. usleep_range(20000, 20100);
  698. else
  699. usleep_range(7000, 7100);
  700. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  701. }
  702. snd_soc_component_update_bits(component,
  703. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  704. 0x02, 0x02);
  705. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  706. snd_soc_component_update_bits(component,
  707. WCD937X_ANA_RX_SUPPLIES,
  708. 0x02, 0x02);
  709. if (wcd937x->update_wcd_event)
  710. wcd937x->update_wcd_event(wcd937x->handle,
  711. WCD_BOLERO_EVT_RX_MUTE,
  712. (WCD_RX1 << 0x10));
  713. break;
  714. case SND_SOC_DAPM_PRE_PMD:
  715. if (wcd937x->update_wcd_event)
  716. wcd937x->update_wcd_event(wcd937x->handle,
  717. WCD_BOLERO_EVT_RX_MUTE,
  718. (WCD_RX1 << 0x10 | 0x1));
  719. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  720. WCD_EVENT_PRE_HPHL_PA_OFF,
  721. &wcd937x->mbhc->wcd_mbhc);
  722. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  723. break;
  724. case SND_SOC_DAPM_POST_PMD:
  725. /*
  726. * 7ms sleep is required after PA is disabled as per
  727. * HW requirement. If compander is disabled, then
  728. * 20ms delay is required.
  729. */
  730. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  731. if (!wcd937x->comp1_enable)
  732. usleep_range(20000, 20100);
  733. else
  734. usleep_range(7000, 7100);
  735. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  736. }
  737. snd_soc_component_update_bits(component,
  738. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  739. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  740. WCD_EVENT_POST_HPHL_PA_OFF,
  741. &wcd937x->mbhc->wcd_mbhc);
  742. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  743. 0x20, 0x00);
  744. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  745. WCD_CLSH_EVENT_POST_PA,
  746. WCD_CLSH_STATE_HPHL,
  747. hph_mode);
  748. break;
  749. };
  750. return ret;
  751. }
  752. static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  753. struct snd_kcontrol *kcontrol,
  754. int event)
  755. {
  756. struct snd_soc_component *component =
  757. snd_soc_dapm_to_component(w->dapm);
  758. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  759. int hph_mode = wcd937x->hph_mode;
  760. int ret = 0;
  761. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  762. w->name, event);
  763. switch (event) {
  764. case SND_SOC_DAPM_PRE_PMU:
  765. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  766. wcd937x->rx_swr_dev->dev_num,
  767. true);
  768. snd_soc_component_update_bits(component,
  769. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  770. break;
  771. case SND_SOC_DAPM_POST_PMU:
  772. usleep_range(1000, 1010);
  773. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  774. snd_soc_component_update_bits(component,
  775. WCD937X_ANA_RX_SUPPLIES,
  776. 0x02, 0x02);
  777. if (wcd937x->update_wcd_event)
  778. wcd937x->update_wcd_event(wcd937x->handle,
  779. WCD_BOLERO_EVT_RX_MUTE,
  780. (WCD_RX3 << 0x10));
  781. break;
  782. case SND_SOC_DAPM_PRE_PMD:
  783. if (wcd937x->update_wcd_event)
  784. wcd937x->update_wcd_event(wcd937x->handle,
  785. WCD_BOLERO_EVT_RX_MUTE,
  786. (WCD_RX3 << 0x10 | 0x1));
  787. break;
  788. case SND_SOC_DAPM_POST_PMD:
  789. /* Add delay as per hw requirement */
  790. usleep_range(2000, 2010);
  791. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  792. WCD_CLSH_EVENT_POST_PA,
  793. WCD_CLSH_STATE_AUX,
  794. hph_mode);
  795. snd_soc_component_update_bits(component,
  796. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  797. break;
  798. };
  799. return ret;
  800. }
  801. static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  802. struct snd_kcontrol *kcontrol,
  803. int event)
  804. {
  805. struct snd_soc_component *component =
  806. snd_soc_dapm_to_component(w->dapm);
  807. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  808. int hph_mode = wcd937x->hph_mode;
  809. int ret = 0;
  810. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  811. w->name, event);
  812. switch (event) {
  813. case SND_SOC_DAPM_PRE_PMU:
  814. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  815. wcd937x->rx_swr_dev->dev_num,
  816. true);
  817. /*
  818. * Enable watchdog interrupt for HPHL or AUX
  819. * depending on mux value
  820. */
  821. wcd937x->ear_rx_path =
  822. snd_soc_component_read32(
  823. component, WCD937X_DIGITAL_CDC_EAR_PATH_CTL);
  824. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  825. snd_soc_component_update_bits(component,
  826. WCD937X_DIGITAL_PDM_WD_CTL2,
  827. 0x05, 0x05);
  828. else
  829. snd_soc_component_update_bits(component,
  830. WCD937X_DIGITAL_PDM_WD_CTL0,
  831. 0x17, 0x13);
  832. if (!wcd937x->comp1_enable)
  833. snd_soc_component_update_bits(component,
  834. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  835. break;
  836. case SND_SOC_DAPM_POST_PMU:
  837. usleep_range(6000, 6010);
  838. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  839. snd_soc_component_update_bits(component,
  840. WCD937X_ANA_RX_SUPPLIES,
  841. 0x02, 0x02);
  842. if (wcd937x->update_wcd_event)
  843. wcd937x->update_wcd_event(wcd937x->handle,
  844. WCD_BOLERO_EVT_RX_MUTE,
  845. (WCD_RX1 << 0x10));
  846. break;
  847. case SND_SOC_DAPM_PRE_PMD:
  848. if (wcd937x->update_wcd_event)
  849. wcd937x->update_wcd_event(wcd937x->handle,
  850. WCD_BOLERO_EVT_RX_MUTE,
  851. (WCD_RX1 << 0x10 | 0x1));
  852. break;
  853. case SND_SOC_DAPM_POST_PMD:
  854. if (!wcd937x->comp1_enable)
  855. snd_soc_component_update_bits(component,
  856. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  857. usleep_range(7000, 7010);
  858. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  859. WCD_CLSH_EVENT_POST_PA,
  860. WCD_CLSH_STATE_EAR,
  861. hph_mode);
  862. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  863. 0x04, 0x04);
  864. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  865. snd_soc_component_update_bits(component,
  866. WCD937X_DIGITAL_PDM_WD_CTL2,
  867. 0x05, 0x00);
  868. else
  869. snd_soc_component_update_bits(component,
  870. WCD937X_DIGITAL_PDM_WD_CTL0,
  871. 0x17, 0x00);
  872. break;
  873. };
  874. return ret;
  875. }
  876. static int wcd937x_enable_clsh(struct snd_soc_dapm_widget *w,
  877. struct snd_kcontrol *kcontrol,
  878. int event)
  879. {
  880. struct snd_soc_component *component =
  881. snd_soc_dapm_to_component(w->dapm);
  882. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  883. int mode = wcd937x->hph_mode;
  884. int ret = 0;
  885. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  886. w->name, event);
  887. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  888. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  889. wcd937x_rx_connect_port(component, CLSH,
  890. SND_SOC_DAPM_EVENT_ON(event));
  891. }
  892. if (SND_SOC_DAPM_EVENT_OFF(event))
  893. ret = swr_slvdev_datapath_control(
  894. wcd937x->rx_swr_dev,
  895. wcd937x->rx_swr_dev->dev_num,
  896. false);
  897. return ret;
  898. }
  899. static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w,
  900. struct snd_kcontrol *kcontrol,
  901. int event)
  902. {
  903. struct snd_soc_component *component =
  904. snd_soc_dapm_to_component(w->dapm);
  905. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  906. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  907. w->name, event);
  908. switch (event) {
  909. case SND_SOC_DAPM_PRE_PMU:
  910. wcd937x_rx_connect_port(component, HPH_L, true);
  911. if (wcd937x->comp1_enable)
  912. wcd937x_rx_connect_port(component, COMP_L, true);
  913. break;
  914. case SND_SOC_DAPM_POST_PMD:
  915. wcd937x_rx_connect_port(component, HPH_L, false);
  916. if (wcd937x->comp1_enable)
  917. wcd937x_rx_connect_port(component, COMP_L, false);
  918. wcd937x_rx_clk_disable(component);
  919. snd_soc_component_update_bits(component,
  920. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  921. 0x01, 0x00);
  922. break;
  923. };
  924. return 0;
  925. }
  926. static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w,
  927. struct snd_kcontrol *kcontrol, int event)
  928. {
  929. struct snd_soc_component *component =
  930. snd_soc_dapm_to_component(w->dapm);
  931. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  932. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  933. w->name, event);
  934. switch (event) {
  935. case SND_SOC_DAPM_PRE_PMU:
  936. wcd937x_rx_connect_port(component, HPH_R, true);
  937. if (wcd937x->comp2_enable)
  938. wcd937x_rx_connect_port(component, COMP_R, true);
  939. break;
  940. case SND_SOC_DAPM_POST_PMD:
  941. wcd937x_rx_connect_port(component, HPH_R, false);
  942. if (wcd937x->comp2_enable)
  943. wcd937x_rx_connect_port(component, COMP_R, false);
  944. wcd937x_rx_clk_disable(component);
  945. snd_soc_component_update_bits(component,
  946. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  947. 0x02, 0x00);
  948. break;
  949. };
  950. return 0;
  951. }
  952. static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w,
  953. struct snd_kcontrol *kcontrol,
  954. int event)
  955. {
  956. struct snd_soc_component *component =
  957. snd_soc_dapm_to_component(w->dapm);
  958. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  959. w->name, event);
  960. switch (event) {
  961. case SND_SOC_DAPM_PRE_PMU:
  962. wcd937x_rx_connect_port(component, LO, true);
  963. break;
  964. case SND_SOC_DAPM_POST_PMD:
  965. wcd937x_rx_connect_port(component, LO, false);
  966. usleep_range(6000, 6010);
  967. wcd937x_rx_clk_disable(component);
  968. snd_soc_component_update_bits(component,
  969. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  970. break;
  971. }
  972. return 0;
  973. }
  974. static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  975. struct snd_kcontrol *kcontrol,
  976. int event)
  977. {
  978. struct snd_soc_component *component =
  979. snd_soc_dapm_to_component(w->dapm);
  980. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  981. u16 dmic_clk_reg;
  982. s32 *dmic_clk_cnt;
  983. unsigned int dmic;
  984. char *wname;
  985. int ret = 0;
  986. wname = strpbrk(w->name, "012345");
  987. if (!wname) {
  988. dev_err(component->dev, "%s: widget not found\n", __func__);
  989. return -EINVAL;
  990. }
  991. ret = kstrtouint(wname, 10, &dmic);
  992. if (ret < 0) {
  993. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  994. __func__);
  995. return -EINVAL;
  996. }
  997. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  998. w->name, event);
  999. switch (dmic) {
  1000. case 0:
  1001. case 1:
  1002. dmic_clk_cnt = &(wcd937x->dmic_0_1_clk_cnt);
  1003. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL;
  1004. break;
  1005. case 2:
  1006. case 3:
  1007. dmic_clk_cnt = &(wcd937x->dmic_2_3_clk_cnt);
  1008. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL;
  1009. break;
  1010. case 4:
  1011. case 5:
  1012. dmic_clk_cnt = &(wcd937x->dmic_4_5_clk_cnt);
  1013. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL;
  1014. break;
  1015. default:
  1016. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1017. __func__);
  1018. return -EINVAL;
  1019. };
  1020. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1021. __func__, event, dmic, *dmic_clk_cnt);
  1022. switch (event) {
  1023. case SND_SOC_DAPM_PRE_PMU:
  1024. snd_soc_component_update_bits(component,
  1025. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1026. snd_soc_component_update_bits(component,
  1027. dmic_clk_reg, 0x07, 0x02);
  1028. snd_soc_component_update_bits(component,
  1029. dmic_clk_reg, 0x08, 0x08);
  1030. snd_soc_component_update_bits(component,
  1031. dmic_clk_reg, 0x70, 0x20);
  1032. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1033. break;
  1034. case SND_SOC_DAPM_POST_PMD:
  1035. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1036. break;
  1037. };
  1038. return 0;
  1039. }
  1040. /*
  1041. * wcd937x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1042. * @micb_mv: micbias in mv
  1043. *
  1044. * return register value converted
  1045. */
  1046. int wcd937x_get_micb_vout_ctl_val(u32 micb_mv)
  1047. {
  1048. /* min micbias voltage is 1V and maximum is 2.85V */
  1049. if (micb_mv < 1000 || micb_mv > 2850) {
  1050. pr_err("%s: unsupported micbias voltage\n", __func__);
  1051. return -EINVAL;
  1052. }
  1053. return (micb_mv - 1000) / 50;
  1054. }
  1055. EXPORT_SYMBOL(wcd937x_get_micb_vout_ctl_val);
  1056. /*
  1057. * wcd937x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1058. * @component: handle to snd_soc_component *
  1059. * @req_volt: micbias voltage to be set
  1060. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1061. *
  1062. * return 0 if adjustment is success or error code in case of failure
  1063. */
  1064. int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1065. int req_volt, int micb_num)
  1066. {
  1067. struct wcd937x_priv *wcd937x =
  1068. snd_soc_component_get_drvdata(component);
  1069. int cur_vout_ctl, req_vout_ctl;
  1070. int micb_reg, micb_val, micb_en;
  1071. int ret = 0;
  1072. switch (micb_num) {
  1073. case MIC_BIAS_1:
  1074. micb_reg = WCD937X_ANA_MICB1;
  1075. break;
  1076. case MIC_BIAS_2:
  1077. micb_reg = WCD937X_ANA_MICB2;
  1078. break;
  1079. case MIC_BIAS_3:
  1080. micb_reg = WCD937X_ANA_MICB3;
  1081. break;
  1082. default:
  1083. return -EINVAL;
  1084. }
  1085. mutex_lock(&wcd937x->micb_lock);
  1086. /*
  1087. * If requested micbias voltage is same as current micbias
  1088. * voltage, then just return. Otherwise, adjust voltage as
  1089. * per requested value. If micbias is already enabled, then
  1090. * to avoid slow micbias ramp-up or down enable pull-up
  1091. * momentarily, change the micbias value and then re-enable
  1092. * micbias.
  1093. */
  1094. micb_val = snd_soc_component_read32(component, micb_reg);
  1095. micb_en = (micb_val & 0xC0) >> 6;
  1096. cur_vout_ctl = micb_val & 0x3F;
  1097. req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt);
  1098. if (req_vout_ctl < 0) {
  1099. ret = -EINVAL;
  1100. goto exit;
  1101. }
  1102. if (cur_vout_ctl == req_vout_ctl) {
  1103. ret = 0;
  1104. goto exit;
  1105. }
  1106. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1107. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1108. req_volt, micb_en);
  1109. if (micb_en == 0x1)
  1110. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1111. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1112. if (micb_en == 0x1) {
  1113. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1114. /*
  1115. * Add 2ms delay as per HW requirement after enabling
  1116. * micbias
  1117. */
  1118. usleep_range(2000, 2100);
  1119. }
  1120. exit:
  1121. mutex_unlock(&wcd937x->micb_lock);
  1122. return ret;
  1123. }
  1124. EXPORT_SYMBOL(wcd937x_mbhc_micb_adjust_voltage);
  1125. static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1126. struct snd_kcontrol *kcontrol,
  1127. int event)
  1128. {
  1129. struct snd_soc_component *component =
  1130. snd_soc_dapm_to_component(w->dapm);
  1131. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1132. int ret = 0;
  1133. switch (event) {
  1134. case SND_SOC_DAPM_PRE_PMU:
  1135. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1136. wcd937x->tx_swr_dev->dev_num,
  1137. true);
  1138. break;
  1139. case SND_SOC_DAPM_POST_PMD:
  1140. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1141. wcd937x->tx_swr_dev->dev_num,
  1142. false);
  1143. break;
  1144. };
  1145. return ret;
  1146. }
  1147. static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1148. struct snd_kcontrol *kcontrol,
  1149. int event){
  1150. struct snd_soc_component *component =
  1151. snd_soc_dapm_to_component(w->dapm);
  1152. struct wcd937x_priv *wcd937x =
  1153. snd_soc_component_get_drvdata(component);
  1154. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1155. w->name, event);
  1156. switch (event) {
  1157. case SND_SOC_DAPM_PRE_PMU:
  1158. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1159. wcd937x->ana_clk_count++;
  1160. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1161. snd_soc_component_update_bits(component,
  1162. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1163. snd_soc_component_update_bits(component,
  1164. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1165. snd_soc_component_update_bits(component,
  1166. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1167. wcd937x_tx_connect_port(component, ADC1 + (w->shift), true);
  1168. break;
  1169. case SND_SOC_DAPM_POST_PMD:
  1170. wcd937x_tx_connect_port(component, ADC1 + (w->shift), false);
  1171. snd_soc_component_update_bits(component,
  1172. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1173. break;
  1174. };
  1175. return 0;
  1176. }
  1177. static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
  1178. struct snd_kcontrol *kcontrol, int event)
  1179. {
  1180. struct snd_soc_component *component =
  1181. snd_soc_dapm_to_component(w->dapm);
  1182. struct wcd937x_priv *wcd937x =
  1183. snd_soc_component_get_drvdata(component);
  1184. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1185. w->name, event);
  1186. switch (event) {
  1187. case SND_SOC_DAPM_PRE_PMU:
  1188. snd_soc_component_update_bits(component,
  1189. WCD937X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1190. snd_soc_component_update_bits(component,
  1191. WCD937X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1192. snd_soc_component_update_bits(component,
  1193. WCD937X_ANA_TX_CH2, 0x40, 0x40);
  1194. snd_soc_component_update_bits(component,
  1195. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x30, 0x30);
  1196. snd_soc_component_update_bits(component,
  1197. WCD937X_ANA_TX_CH1, 0x80, 0x80);
  1198. snd_soc_component_update_bits(component,
  1199. WCD937X_ANA_TX_CH2, 0x40, 0x00);
  1200. snd_soc_component_update_bits(component,
  1201. WCD937X_ANA_TX_CH2, 0x80, 0x80);
  1202. break;
  1203. case SND_SOC_DAPM_POST_PMD:
  1204. snd_soc_component_update_bits(component,
  1205. WCD937X_ANA_TX_CH1, 0x80, 0x00);
  1206. snd_soc_component_update_bits(component,
  1207. WCD937X_ANA_TX_CH2, 0x80, 0x00);
  1208. snd_soc_component_update_bits(component,
  1209. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1210. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1211. wcd937x->ana_clk_count--;
  1212. if (wcd937x->ana_clk_count <= 0) {
  1213. snd_soc_component_update_bits(component,
  1214. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1215. wcd937x->ana_clk_count = 0;
  1216. }
  1217. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1218. snd_soc_component_update_bits(component,
  1219. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1220. break;
  1221. };
  1222. return 0;
  1223. }
  1224. int wcd937x_micbias_control(struct snd_soc_component *component,
  1225. int micb_num, int req, bool is_dapm)
  1226. {
  1227. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1228. int micb_index = micb_num - 1;
  1229. u16 micb_reg;
  1230. int pre_off_event = 0, post_off_event = 0;
  1231. int post_on_event = 0, post_dapm_off = 0;
  1232. int post_dapm_on = 0;
  1233. if ((micb_index < 0) || (micb_index > WCD937X_MAX_MICBIAS - 1)) {
  1234. dev_err(component->dev, "%s: Invalid micbias index, micb_ind:%d\n",
  1235. __func__, micb_index);
  1236. return -EINVAL;
  1237. }
  1238. switch (micb_num) {
  1239. case MIC_BIAS_1:
  1240. micb_reg = WCD937X_ANA_MICB1;
  1241. break;
  1242. case MIC_BIAS_2:
  1243. micb_reg = WCD937X_ANA_MICB2;
  1244. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1245. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1246. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1247. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1248. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1249. break;
  1250. case MIC_BIAS_3:
  1251. micb_reg = WCD937X_ANA_MICB3;
  1252. break;
  1253. default:
  1254. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1255. __func__, micb_num);
  1256. return -EINVAL;
  1257. };
  1258. mutex_lock(&wcd937x->micb_lock);
  1259. switch (req) {
  1260. case MICB_PULLUP_ENABLE:
  1261. wcd937x->pullup_ref[micb_index]++;
  1262. if ((wcd937x->pullup_ref[micb_index] == 1) &&
  1263. (wcd937x->micb_ref[micb_index] == 0))
  1264. snd_soc_component_update_bits(component, micb_reg,
  1265. 0xC0, 0x80);
  1266. break;
  1267. case MICB_PULLUP_DISABLE:
  1268. if (wcd937x->pullup_ref[micb_index] > 0)
  1269. wcd937x->pullup_ref[micb_index]--;
  1270. if ((wcd937x->pullup_ref[micb_index] == 0) &&
  1271. (wcd937x->micb_ref[micb_index] == 0))
  1272. snd_soc_component_update_bits(component, micb_reg,
  1273. 0xC0, 0x00);
  1274. break;
  1275. case MICB_ENABLE:
  1276. wcd937x->micb_ref[micb_index]++;
  1277. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1278. wcd937x->ana_clk_count++;
  1279. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1280. if (wcd937x->micb_ref[micb_index] == 1) {
  1281. snd_soc_component_update_bits(component,
  1282. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1283. snd_soc_component_update_bits(component,
  1284. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1285. snd_soc_component_update_bits(component,
  1286. WCD937X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1287. snd_soc_component_update_bits(component,
  1288. WCD937X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1289. snd_soc_component_update_bits(component,
  1290. WCD937X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1291. snd_soc_component_update_bits(component,
  1292. micb_reg, 0xC0, 0x40);
  1293. if (post_on_event)
  1294. blocking_notifier_call_chain(
  1295. &wcd937x->mbhc->notifier, post_on_event,
  1296. &wcd937x->mbhc->wcd_mbhc);
  1297. }
  1298. if (is_dapm && post_dapm_on && wcd937x->mbhc)
  1299. blocking_notifier_call_chain(
  1300. &wcd937x->mbhc->notifier, post_dapm_on,
  1301. &wcd937x->mbhc->wcd_mbhc);
  1302. break;
  1303. case MICB_DISABLE:
  1304. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1305. wcd937x->ana_clk_count--;
  1306. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1307. if (wcd937x->micb_ref[micb_index] > 0)
  1308. wcd937x->micb_ref[micb_index]--;
  1309. if ((wcd937x->micb_ref[micb_index] == 0) &&
  1310. (wcd937x->pullup_ref[micb_index] > 0))
  1311. snd_soc_component_update_bits(component, micb_reg,
  1312. 0xC0, 0x80);
  1313. else if ((wcd937x->micb_ref[micb_index] == 0) &&
  1314. (wcd937x->pullup_ref[micb_index] == 0)) {
  1315. if (pre_off_event && wcd937x->mbhc)
  1316. blocking_notifier_call_chain(
  1317. &wcd937x->mbhc->notifier, pre_off_event,
  1318. &wcd937x->mbhc->wcd_mbhc);
  1319. snd_soc_component_update_bits(component, micb_reg,
  1320. 0xC0, 0x00);
  1321. if (post_off_event && wcd937x->mbhc)
  1322. blocking_notifier_call_chain(
  1323. &wcd937x->mbhc->notifier,
  1324. post_off_event,
  1325. &wcd937x->mbhc->wcd_mbhc);
  1326. }
  1327. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1328. if (wcd937x->ana_clk_count <= 0) {
  1329. snd_soc_component_update_bits(component,
  1330. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  1331. 0x10, 0x00);
  1332. wcd937x->ana_clk_count = 0;
  1333. }
  1334. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1335. if (is_dapm && post_dapm_off && wcd937x->mbhc)
  1336. blocking_notifier_call_chain(
  1337. &wcd937x->mbhc->notifier, post_dapm_off,
  1338. &wcd937x->mbhc->wcd_mbhc);
  1339. break;
  1340. };
  1341. dev_dbg(component->dev, "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1342. __func__, micb_num, wcd937x->micb_ref[micb_index],
  1343. wcd937x->pullup_ref[micb_index]);
  1344. mutex_unlock(&wcd937x->micb_lock);
  1345. return 0;
  1346. }
  1347. EXPORT_SYMBOL(wcd937x_micbias_control);
  1348. static int wcd937x_get_logical_addr(struct swr_device *swr_dev)
  1349. {
  1350. int ret = 0;
  1351. uint8_t devnum = 0;
  1352. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1353. if (ret) {
  1354. dev_err(&swr_dev->dev,
  1355. "%s get devnum %d for dev addr %lx failed\n",
  1356. __func__, devnum, swr_dev->addr);
  1357. return ret;
  1358. }
  1359. swr_dev->dev_num = devnum;
  1360. return 0;
  1361. }
  1362. static int wcd937x_event_notify(struct notifier_block *block,
  1363. unsigned long val,
  1364. void *data)
  1365. {
  1366. u16 event = (val & 0xffff);
  1367. u16 amic = (val >> 0x10);
  1368. u16 mask = 0x40, reg = 0x0;
  1369. int ret = 0;
  1370. struct wcd937x_priv *wcd937x = dev_get_drvdata((struct device *)data);
  1371. struct snd_soc_component *component = wcd937x->component;
  1372. struct wcd_mbhc *mbhc;
  1373. switch (event) {
  1374. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1375. if (amic == 0x1 || amic == 0x2)
  1376. reg = WCD937X_ANA_TX_CH2;
  1377. else if (amic == 0x3)
  1378. reg = WCD937X_ANA_TX_CH3_HPF;
  1379. else
  1380. return 0;
  1381. if (amic == 0x2)
  1382. mask = 0x20;
  1383. snd_soc_component_update_bits(component, reg, mask, 0x00);
  1384. break;
  1385. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1386. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  1387. 0xC0, 0x00);
  1388. snd_soc_component_update_bits(component, WCD937X_ANA_EAR,
  1389. 0x80, 0x00);
  1390. snd_soc_component_update_bits(component, WCD937X_AUX_AUXPA,
  1391. 0x80, 0x00);
  1392. break;
  1393. case BOLERO_WCD_EVT_SSR_DOWN:
  1394. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1395. wcd937x_mbhc_ssr_down(wcd937x->mbhc, component);
  1396. wcd937x_reset_low(wcd937x->dev);
  1397. break;
  1398. case BOLERO_WCD_EVT_SSR_UP:
  1399. wcd937x_reset(wcd937x->dev);
  1400. wcd937x_get_logical_addr(wcd937x->tx_swr_dev);
  1401. wcd937x_get_logical_addr(wcd937x->rx_swr_dev);
  1402. regcache_mark_dirty(wcd937x->regmap);
  1403. regcache_sync(wcd937x->regmap);
  1404. /* Enable surge protection */
  1405. snd_soc_component_update_bits(component,
  1406. WCD937X_HPH_SURGE_HPHLR_SURGE_EN,
  1407. 0xFF, 0xD9);
  1408. /* Initialize MBHC module */
  1409. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1410. ret = wcd937x_mbhc_post_ssr_init(wcd937x->mbhc, component);
  1411. if (ret) {
  1412. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1413. __func__);
  1414. } else {
  1415. wcd937x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1416. }
  1417. break;
  1418. default:
  1419. dev_err(component->dev, "%s: invalid event %d\n", __func__,
  1420. event);
  1421. break;
  1422. }
  1423. return 0;
  1424. }
  1425. static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1426. int event)
  1427. {
  1428. struct snd_soc_component *component =
  1429. snd_soc_dapm_to_component(w->dapm);
  1430. int micb_num;
  1431. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1432. __func__, w->name, event);
  1433. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1434. micb_num = MIC_BIAS_1;
  1435. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1436. micb_num = MIC_BIAS_2;
  1437. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1438. micb_num = MIC_BIAS_3;
  1439. else
  1440. return -EINVAL;
  1441. switch (event) {
  1442. case SND_SOC_DAPM_PRE_PMU:
  1443. wcd937x_micbias_control(component, micb_num,
  1444. MICB_ENABLE, true);
  1445. break;
  1446. case SND_SOC_DAPM_POST_PMU:
  1447. usleep_range(1000, 1100);
  1448. break;
  1449. case SND_SOC_DAPM_POST_PMD:
  1450. wcd937x_micbias_control(component, micb_num,
  1451. MICB_DISABLE, true);
  1452. break;
  1453. };
  1454. return 0;
  1455. }
  1456. static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1457. struct snd_kcontrol *kcontrol,
  1458. int event)
  1459. {
  1460. return __wcd937x_codec_enable_micbias(w, event);
  1461. }
  1462. static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1463. struct snd_ctl_elem_value *ucontrol)
  1464. {
  1465. struct snd_soc_component *component =
  1466. snd_soc_kcontrol_component(kcontrol);
  1467. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1468. ucontrol->value.integer.value[0] = wcd937x->hph_mode;
  1469. return 0;
  1470. }
  1471. static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1472. struct snd_ctl_elem_value *ucontrol)
  1473. {
  1474. struct snd_soc_component *component =
  1475. snd_soc_kcontrol_component(kcontrol);
  1476. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1477. u32 mode_val;
  1478. mode_val = ucontrol->value.enumerated.item[0];
  1479. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1480. if (mode_val == 0) {
  1481. dev_warn(component->dev, "%s:Invalid HPH Mode, default to class_AB\n",
  1482. __func__);
  1483. mode_val = 3; /* enum will be updated later */
  1484. }
  1485. wcd937x->hph_mode = mode_val;
  1486. return 0;
  1487. }
  1488. static int wcd937x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  1489. struct snd_ctl_elem_value *ucontrol)
  1490. {
  1491. u8 ear_pa_gain = 0;
  1492. struct snd_soc_component *component =
  1493. snd_soc_kcontrol_component(kcontrol);
  1494. ear_pa_gain = snd_soc_component_read32(component,
  1495. WCD937X_ANA_EAR_COMPANDER_CTL);
  1496. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  1497. ucontrol->value.integer.value[0] = ear_pa_gain;
  1498. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  1499. ear_pa_gain);
  1500. return 0;
  1501. }
  1502. static int wcd937x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  1503. struct snd_ctl_elem_value *ucontrol)
  1504. {
  1505. u8 ear_pa_gain = 0;
  1506. struct snd_soc_component *component =
  1507. snd_soc_kcontrol_component(kcontrol);
  1508. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1509. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1510. __func__, ucontrol->value.integer.value[0]);
  1511. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  1512. if (!wcd937x->comp1_enable) {
  1513. snd_soc_component_update_bits(component,
  1514. WCD937X_ANA_EAR_COMPANDER_CTL,
  1515. 0x7C, ear_pa_gain);
  1516. }
  1517. return 0;
  1518. }
  1519. static int wcd937x_get_compander(struct snd_kcontrol *kcontrol,
  1520. struct snd_ctl_elem_value *ucontrol)
  1521. {
  1522. struct snd_soc_component *component =
  1523. snd_soc_kcontrol_component(kcontrol);
  1524. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1525. bool hphr;
  1526. struct soc_multi_mixer_control *mc;
  1527. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1528. hphr = mc->shift;
  1529. ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable :
  1530. wcd937x->comp1_enable;
  1531. return 0;
  1532. }
  1533. static int wcd937x_set_compander(struct snd_kcontrol *kcontrol,
  1534. struct snd_ctl_elem_value *ucontrol)
  1535. {
  1536. struct snd_soc_component *component =
  1537. snd_soc_kcontrol_component(kcontrol);
  1538. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1539. int value = ucontrol->value.integer.value[0];
  1540. bool hphr;
  1541. struct soc_multi_mixer_control *mc;
  1542. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1543. hphr = mc->shift;
  1544. if (hphr)
  1545. wcd937x->comp2_enable = value;
  1546. else
  1547. wcd937x->comp1_enable = value;
  1548. return 0;
  1549. }
  1550. static int wcd937x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  1551. struct snd_kcontrol *kcontrol,
  1552. int event)
  1553. {
  1554. struct snd_soc_component *component =
  1555. snd_soc_dapm_to_component(w->dapm);
  1556. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1557. struct wcd937x_pdata *pdata = NULL;
  1558. int ret = 0;
  1559. pdata = dev_get_platdata(wcd937x->dev);
  1560. if (!pdata) {
  1561. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  1562. return -EINVAL;
  1563. }
  1564. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1565. w->name, event);
  1566. switch (event) {
  1567. case SND_SOC_DAPM_PRE_PMU:
  1568. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  1569. dev_dbg(component->dev,
  1570. "%s: buck already in enabled state\n",
  1571. __func__);
  1572. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1573. return 0;
  1574. }
  1575. ret = msm_cdc_enable_ondemand_supply(wcd937x->dev,
  1576. wcd937x->supplies,
  1577. pdata->regulator,
  1578. pdata->num_supplies,
  1579. "cdc-vdd-buck");
  1580. if (ret == -EINVAL) {
  1581. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  1582. __func__);
  1583. return ret;
  1584. }
  1585. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1586. /*
  1587. * 200us sleep is required after LDO15 is enabled as per
  1588. * HW requirement
  1589. */
  1590. usleep_range(200, 250);
  1591. break;
  1592. case SND_SOC_DAPM_POST_PMD:
  1593. set_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1594. break;
  1595. }
  1596. return 0;
  1597. }
  1598. static const char * const rx_hph_mode_mux_text[] = {
  1599. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1600. "CLS_H_ULP", "CLS_AB_HIFI",
  1601. };
  1602. static const char * const wcd937x_ear_pa_gain_text[] = {
  1603. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  1604. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  1605. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  1606. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  1607. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  1608. };
  1609. static const struct soc_enum rx_hph_mode_mux_enum =
  1610. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1611. rx_hph_mode_mux_text);
  1612. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_ear_pa_gain_enum,
  1613. wcd937x_ear_pa_gain_text);
  1614. static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
  1615. SOC_ENUM_EXT("EAR PA GAIN", wcd937x_ear_pa_gain_enum,
  1616. wcd937x_ear_pa_gain_get, wcd937x_ear_pa_gain_put),
  1617. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1618. wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put),
  1619. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1620. wcd937x_get_compander, wcd937x_set_compander),
  1621. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1622. wcd937x_get_compander, wcd937x_set_compander),
  1623. SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain),
  1624. SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain),
  1625. SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0,
  1626. analog_gain),
  1627. SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0,
  1628. analog_gain),
  1629. SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0,
  1630. analog_gain),
  1631. };
  1632. static const struct snd_kcontrol_new adc1_switch[] = {
  1633. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1634. };
  1635. static const struct snd_kcontrol_new adc2_switch[] = {
  1636. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1637. };
  1638. static const struct snd_kcontrol_new adc3_switch[] = {
  1639. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1640. };
  1641. static const struct snd_kcontrol_new dmic1_switch[] = {
  1642. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1643. };
  1644. static const struct snd_kcontrol_new dmic2_switch[] = {
  1645. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1646. };
  1647. static const struct snd_kcontrol_new dmic3_switch[] = {
  1648. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1649. };
  1650. static const struct snd_kcontrol_new dmic4_switch[] = {
  1651. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1652. };
  1653. static const struct snd_kcontrol_new dmic5_switch[] = {
  1654. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1655. };
  1656. static const struct snd_kcontrol_new dmic6_switch[] = {
  1657. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1658. };
  1659. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  1660. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1661. };
  1662. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  1663. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1664. };
  1665. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  1666. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1667. };
  1668. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  1669. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1670. };
  1671. static const char * const adc2_mux_text[] = {
  1672. "INP2", "INP3"
  1673. };
  1674. static const char * const rdac3_mux_text[] = {
  1675. "RX1", "RX3"
  1676. };
  1677. static const struct soc_enum adc2_enum =
  1678. SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7,
  1679. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  1680. static const struct soc_enum rdac3_enum =
  1681. SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  1682. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  1683. static const struct snd_kcontrol_new tx_adc2_mux =
  1684. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  1685. static const struct snd_kcontrol_new rx_rdac3_mux =
  1686. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  1687. static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = {
  1688. /*input widgets*/
  1689. SND_SOC_DAPM_INPUT("AMIC1"),
  1690. SND_SOC_DAPM_INPUT("AMIC2"),
  1691. SND_SOC_DAPM_INPUT("AMIC3"),
  1692. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  1693. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  1694. SND_SOC_DAPM_INPUT("IN3_AUX"),
  1695. /*tx widgets*/
  1696. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  1697. wcd937x_codec_enable_adc,
  1698. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1699. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  1700. wcd937x_codec_enable_adc,
  1701. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1702. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  1703. NULL, 0, wcd937x_enable_req,
  1704. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1705. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
  1706. NULL, 0, wcd937x_enable_req,
  1707. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1708. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  1709. &tx_adc2_mux),
  1710. /*tx mixers*/
  1711. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  1712. adc1_switch, ARRAY_SIZE(adc1_switch),
  1713. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1714. SND_SOC_DAPM_POST_PMD),
  1715. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  1716. adc2_switch, ARRAY_SIZE(adc2_switch),
  1717. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1718. SND_SOC_DAPM_POST_PMD),
  1719. /* micbias widgets*/
  1720. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  1721. wcd937x_codec_enable_micbias,
  1722. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1723. SND_SOC_DAPM_POST_PMD),
  1724. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  1725. wcd937x_codec_enable_micbias,
  1726. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1727. SND_SOC_DAPM_POST_PMD),
  1728. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  1729. wcd937x_codec_enable_micbias,
  1730. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1731. SND_SOC_DAPM_POST_PMD),
  1732. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  1733. wcd937x_codec_enable_vdd_buck,
  1734. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1735. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  1736. wcd937x_enable_clsh,
  1737. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1738. /*rx widgets*/
  1739. SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0,
  1740. wcd937x_codec_enable_ear_pa,
  1741. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1742. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1743. SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0,
  1744. wcd937x_codec_enable_aux_pa,
  1745. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1746. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1747. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0,
  1748. wcd937x_codec_enable_hphl_pa,
  1749. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1750. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1751. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0,
  1752. wcd937x_codec_enable_hphr_pa,
  1753. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1754. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1755. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  1756. wcd937x_codec_hphl_dac_event,
  1757. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1758. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1759. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  1760. wcd937x_codec_hphr_dac_event,
  1761. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1762. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1763. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  1764. wcd937x_codec_ear_dac_event,
  1765. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1766. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1767. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  1768. wcd937x_codec_aux_dac_event,
  1769. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1770. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1771. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  1772. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  1773. wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  1774. SND_SOC_DAPM_POST_PMD),
  1775. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  1776. wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  1777. SND_SOC_DAPM_POST_PMD),
  1778. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  1779. wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  1780. SND_SOC_DAPM_POST_PMD),
  1781. /* rx mixer widgets*/
  1782. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  1783. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  1784. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  1785. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  1786. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  1787. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  1788. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  1789. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  1790. /*output widgets tx*/
  1791. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  1792. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  1793. /*output widgets rx*/
  1794. SND_SOC_DAPM_OUTPUT("EAR"),
  1795. SND_SOC_DAPM_OUTPUT("AUX"),
  1796. SND_SOC_DAPM_OUTPUT("HPHL"),
  1797. SND_SOC_DAPM_OUTPUT("HPHR"),
  1798. };
  1799. static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = {
  1800. /*input widgets*/
  1801. SND_SOC_DAPM_INPUT("AMIC4"),
  1802. /*tx widgets*/
  1803. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  1804. wcd937x_codec_enable_adc,
  1805. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1806. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
  1807. NULL, 0, wcd937x_enable_req,
  1808. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1809. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  1810. wcd937x_codec_enable_dmic,
  1811. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1812. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  1813. wcd937x_codec_enable_dmic,
  1814. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1815. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  1816. wcd937x_codec_enable_dmic,
  1817. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1818. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  1819. wcd937x_codec_enable_dmic,
  1820. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1821. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  1822. wcd937x_codec_enable_dmic,
  1823. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1824. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  1825. wcd937x_codec_enable_dmic,
  1826. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1827. /*tx mixer widgets*/
  1828. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  1829. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  1830. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1831. SND_SOC_DAPM_POST_PMD),
  1832. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  1833. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  1834. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1835. SND_SOC_DAPM_POST_PMD),
  1836. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  1837. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  1838. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1839. SND_SOC_DAPM_POST_PMD),
  1840. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  1841. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  1842. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1843. SND_SOC_DAPM_POST_PMD),
  1844. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  1845. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  1846. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1847. SND_SOC_DAPM_POST_PMD),
  1848. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  1849. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  1850. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1851. SND_SOC_DAPM_POST_PMD),
  1852. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  1853. ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl,
  1854. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1855. /*output widgets*/
  1856. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  1857. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  1858. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  1859. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  1860. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  1861. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  1862. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  1863. };
  1864. static const struct snd_soc_dapm_route wcd937x_audio_map[] = {
  1865. {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
  1866. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  1867. {"ADC1 REQ", NULL, "ADC1"},
  1868. {"ADC1", NULL, "AMIC1"},
  1869. {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
  1870. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  1871. {"ADC2 REQ", NULL, "ADC2"},
  1872. {"ADC2", NULL, "ADC2 MUX"},
  1873. {"ADC2 MUX", "INP3", "AMIC3"},
  1874. {"ADC2 MUX", "INP2", "AMIC2"},
  1875. {"IN1_HPHL", NULL, "VDD_BUCK"},
  1876. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  1877. {"RX1", NULL, "IN1_HPHL"},
  1878. {"RDAC1", NULL, "RX1"},
  1879. {"HPHL_RDAC", "Switch", "RDAC1"},
  1880. {"HPHL PGA", NULL, "HPHL_RDAC"},
  1881. {"HPHL", NULL, "HPHL PGA"},
  1882. {"IN2_HPHR", NULL, "VDD_BUCK"},
  1883. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  1884. {"RX2", NULL, "IN2_HPHR"},
  1885. {"RDAC2", NULL, "RX2"},
  1886. {"HPHR_RDAC", "Switch", "RDAC2"},
  1887. {"HPHR PGA", NULL, "HPHR_RDAC"},
  1888. {"HPHR", NULL, "HPHR PGA"},
  1889. {"IN3_AUX", NULL, "VDD_BUCK"},
  1890. {"IN3_AUX", NULL, "CLS_H_PORT"},
  1891. {"RX3", NULL, "IN3_AUX"},
  1892. {"RDAC4", NULL, "RX3"},
  1893. {"AUX_RDAC", "Switch", "RDAC4"},
  1894. {"AUX PGA", NULL, "AUX_RDAC"},
  1895. {"AUX", NULL, "AUX PGA"},
  1896. {"RDAC3_MUX", "RX3", "RX3"},
  1897. {"RDAC3_MUX", "RX1", "RX1"},
  1898. {"RDAC3", NULL, "RDAC3_MUX"},
  1899. {"EAR_RDAC", "Switch", "RDAC3"},
  1900. {"EAR PGA", NULL, "EAR_RDAC"},
  1901. {"EAR", NULL, "EAR PGA"},
  1902. };
  1903. static const struct snd_soc_dapm_route wcd9375_audio_map[] = {
  1904. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  1905. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  1906. {"ADC3 REQ", NULL, "ADC3"},
  1907. {"ADC3", NULL, "AMIC4"},
  1908. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  1909. {"DMIC1_MIXER", "Switch", "DMIC1"},
  1910. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  1911. {"DMIC2_MIXER", "Switch", "DMIC2"},
  1912. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  1913. {"DMIC3_MIXER", "Switch", "DMIC3"},
  1914. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  1915. {"DMIC4_MIXER", "Switch", "DMIC4"},
  1916. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  1917. {"DMIC5_MIXER", "Switch", "DMIC5"},
  1918. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  1919. {"DMIC6_MIXER", "Switch", "DMIC6"},
  1920. };
  1921. static ssize_t wcd937x_version_read(struct snd_info_entry *entry,
  1922. void *file_private_data,
  1923. struct file *file,
  1924. char __user *buf, size_t count,
  1925. loff_t pos)
  1926. {
  1927. struct wcd937x_priv *priv;
  1928. char buffer[WCD937X_VERSION_ENTRY_SIZE];
  1929. int len = 0;
  1930. priv = (struct wcd937x_priv *) entry->private_data;
  1931. if (!priv) {
  1932. pr_err("%s: wcd937x priv is null\n", __func__);
  1933. return -EINVAL;
  1934. }
  1935. switch (priv->version) {
  1936. case WCD937X_VERSION_1_0:
  1937. len = snprintf(buffer, sizeof(buffer), "WCD937X_1_0\n");
  1938. break;
  1939. default:
  1940. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  1941. }
  1942. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  1943. }
  1944. static struct snd_info_entry_ops wcd937x_info_ops = {
  1945. .read = wcd937x_version_read,
  1946. };
  1947. static ssize_t wcd937x_variant_read(struct snd_info_entry *entry,
  1948. void *file_private_data,
  1949. struct file *file,
  1950. char __user *buf, size_t count,
  1951. loff_t pos)
  1952. {
  1953. struct wcd937x_priv *priv;
  1954. char buffer[WCD937X_VARIANT_ENTRY_SIZE];
  1955. int len = 0;
  1956. priv = (struct wcd937x_priv *) entry->private_data;
  1957. if (!priv) {
  1958. pr_err("%s: wcd937x priv is null\n", __func__);
  1959. return -EINVAL;
  1960. }
  1961. switch (priv->variant) {
  1962. case WCD9370_VARIANT:
  1963. len = snprintf(buffer, sizeof(buffer), "WCD9370\n");
  1964. break;
  1965. case WCD9375_VARIANT:
  1966. len = snprintf(buffer, sizeof(buffer), "WCD9375\n");
  1967. break;
  1968. default:
  1969. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  1970. }
  1971. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  1972. }
  1973. static struct snd_info_entry_ops wcd937x_variant_ops = {
  1974. .read = wcd937x_variant_read,
  1975. };
  1976. /*
  1977. * wcd937x_info_create_codec_entry - creates wcd937x module
  1978. * @codec_root: The parent directory
  1979. * @component: component instance
  1980. *
  1981. * Creates wcd937x module, variant and version entry under the given
  1982. * parent directory.
  1983. *
  1984. * Return: 0 on success or negative error code on failure.
  1985. */
  1986. int wcd937x_info_create_codec_entry(struct snd_info_entry *codec_root,
  1987. struct snd_soc_component *component)
  1988. {
  1989. struct snd_info_entry *version_entry;
  1990. struct snd_info_entry *variant_entry;
  1991. struct wcd937x_priv *priv;
  1992. struct snd_soc_card *card;
  1993. if (!codec_root || !component)
  1994. return -EINVAL;
  1995. priv = snd_soc_component_get_drvdata(component);
  1996. if (priv->entry) {
  1997. dev_dbg(priv->dev,
  1998. "%s:wcd937x module already created\n", __func__);
  1999. return 0;
  2000. }
  2001. card = component->card;
  2002. priv->entry = snd_info_create_subdir(codec_root->module,
  2003. "wcd937x", codec_root);
  2004. if (!priv->entry) {
  2005. dev_dbg(component->dev, "%s: failed to create wcd937x entry\n",
  2006. __func__);
  2007. return -ENOMEM;
  2008. }
  2009. version_entry = snd_info_create_card_entry(card->snd_card,
  2010. "version",
  2011. priv->entry);
  2012. if (!version_entry) {
  2013. dev_dbg(component->dev, "%s: failed to create wcd937x version entry\n",
  2014. __func__);
  2015. return -ENOMEM;
  2016. }
  2017. version_entry->private_data = priv;
  2018. version_entry->size = WCD937X_VERSION_ENTRY_SIZE;
  2019. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2020. version_entry->c.ops = &wcd937x_info_ops;
  2021. if (snd_info_register(version_entry) < 0) {
  2022. snd_info_free_entry(version_entry);
  2023. return -ENOMEM;
  2024. }
  2025. priv->version_entry = version_entry;
  2026. variant_entry = snd_info_create_card_entry(card->snd_card,
  2027. "variant",
  2028. priv->entry);
  2029. if (!variant_entry) {
  2030. dev_dbg(codec->dev, "%s: failed to create wcd937x variant entry\n",
  2031. __func__);
  2032. return -ENOMEM;
  2033. }
  2034. variant_entry->private_data = priv;
  2035. variant_entry->size = WCD937X_VARIANT_ENTRY_SIZE;
  2036. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2037. variant_entry->c.ops = &wcd937x_variant_ops;
  2038. if (snd_info_register(variant_entry) < 0) {
  2039. snd_info_free_entry(variant_entry);
  2040. return -ENOMEM;
  2041. }
  2042. priv->variant_entry = variant_entry;
  2043. return 0;
  2044. }
  2045. EXPORT_SYMBOL(wcd937x_info_create_codec_entry);
  2046. static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x,
  2047. struct wcd937x_pdata *pdata)
  2048. {
  2049. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0;
  2050. int rc = 0;
  2051. if (!pdata) {
  2052. dev_err(wcd937x->dev, "%s: NULL pdata\n", __func__);
  2053. return -ENODEV;
  2054. }
  2055. /* set micbias voltage */
  2056. vout_ctl_1 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  2057. vout_ctl_2 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  2058. vout_ctl_3 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  2059. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0) {
  2060. rc = -EINVAL;
  2061. goto done;
  2062. }
  2063. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, 0x3F,
  2064. vout_ctl_1);
  2065. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, 0x3F,
  2066. vout_ctl_2);
  2067. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, 0x3F,
  2068. vout_ctl_3);
  2069. done:
  2070. return rc;
  2071. }
  2072. static int wcd937x_soc_codec_probe(struct snd_soc_component *component)
  2073. {
  2074. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2075. struct snd_soc_dapm_context *dapm =
  2076. snd_soc_component_get_dapm(component);
  2077. int variant;
  2078. int ret = -EINVAL;
  2079. dev_info(component->dev, "%s()\n", __func__);
  2080. wcd937x = snd_soc_component_get_drvdata(component);
  2081. if (!wcd937x)
  2082. return -EINVAL;
  2083. wcd937x->component = component;
  2084. variant = (snd_soc_component_read32(
  2085. component, WCD937X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2086. wcd937x->variant = variant;
  2087. wcd937x->fw_data = devm_kzalloc(component->dev,
  2088. sizeof(*(wcd937x->fw_data)),
  2089. GFP_KERNEL);
  2090. if (!wcd937x->fw_data) {
  2091. dev_err(component->dev, "Failed to allocate fw_data\n");
  2092. ret = -ENOMEM;
  2093. goto err;
  2094. }
  2095. set_bit(WCD9XXX_MBHC_CAL, wcd937x->fw_data->cal_bit);
  2096. ret = wcd_cal_create_hwdep(wcd937x->fw_data,
  2097. WCD9XXX_CODEC_HWDEP_NODE, component);
  2098. if (ret < 0) {
  2099. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2100. goto err_hwdep;
  2101. }
  2102. ret = wcd937x_mbhc_init(&wcd937x->mbhc, component, wcd937x->fw_data);
  2103. if (ret) {
  2104. pr_err("%s: mbhc initialization failed\n", __func__);
  2105. goto err_hwdep;
  2106. }
  2107. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2108. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2109. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2110. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2111. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2112. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2113. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2114. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2115. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2116. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2117. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2118. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2119. snd_soc_dapm_sync(dapm);
  2120. wcd_cls_h_init(&wcd937x->clsh_info);
  2121. wcd937x_init_reg(component);
  2122. if (wcd937x->variant == WCD9375_VARIANT) {
  2123. ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets,
  2124. ARRAY_SIZE(wcd9375_dapm_widgets));
  2125. if (ret < 0) {
  2126. dev_err(component->dev, "%s: Failed to add snd_ctls\n",
  2127. __func__);
  2128. goto err_hwdep;
  2129. }
  2130. ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map,
  2131. ARRAY_SIZE(wcd9375_audio_map));
  2132. if (ret < 0) {
  2133. dev_err(component->dev, "%s: Failed to add routes\n",
  2134. __func__);
  2135. goto err_hwdep;
  2136. }
  2137. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2138. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2139. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2140. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2141. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2142. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2143. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2144. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2145. snd_soc_dapm_sync(dapm);
  2146. }
  2147. wcd937x->version = WCD937X_VERSION_1_0;
  2148. /* Register event notifier */
  2149. wcd937x->nblock.notifier_call = wcd937x_event_notify;
  2150. if (wcd937x->register_notifier) {
  2151. ret = wcd937x->register_notifier(wcd937x->handle,
  2152. &wcd937x->nblock,
  2153. true);
  2154. if (ret) {
  2155. dev_err(component->dev,
  2156. "%s: Failed to register notifier %d\n",
  2157. __func__, ret);
  2158. return ret;
  2159. }
  2160. }
  2161. return ret;
  2162. err_hwdep:
  2163. wcd937x->fw_data = NULL;
  2164. err:
  2165. return ret;
  2166. }
  2167. static void wcd937x_soc_codec_remove(struct snd_soc_component *component)
  2168. {
  2169. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2170. if (!wcd937x)
  2171. return;
  2172. if (wcd937x->register_notifier)
  2173. wcd937x->register_notifier(wcd937x->handle,
  2174. &wcd937x->nblock,
  2175. false);
  2176. return;
  2177. }
  2178. static const struct snd_soc_component_driver soc_codec_dev_wcd937x = {
  2179. .name = DRV_NAME,
  2180. .probe = wcd937x_soc_codec_probe,
  2181. .remove = wcd937x_soc_codec_remove,
  2182. .controls = wcd937x_snd_controls,
  2183. .num_controls = ARRAY_SIZE(wcd937x_snd_controls),
  2184. .dapm_widgets = wcd937x_dapm_widgets,
  2185. .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets),
  2186. .dapm_routes = wcd937x_audio_map,
  2187. .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map),
  2188. };
  2189. #ifdef CONFIG_PM_SLEEP
  2190. static int wcd937x_suspend(struct device *dev)
  2191. {
  2192. struct wcd937x_priv *wcd937x = NULL;
  2193. int ret = 0;
  2194. struct wcd937x_pdata *pdata = NULL;
  2195. if (!dev)
  2196. return -ENODEV;
  2197. wcd937x = dev_get_drvdata(dev);
  2198. if (!wcd937x)
  2199. return -EINVAL;
  2200. pdata = dev_get_platdata(wcd937x->dev);
  2201. if (!pdata) {
  2202. dev_err(dev, "%s: pdata is NULL\n", __func__);
  2203. return -EINVAL;
  2204. }
  2205. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  2206. ret = msm_cdc_disable_ondemand_supply(wcd937x->dev,
  2207. wcd937x->supplies,
  2208. pdata->regulator,
  2209. pdata->num_supplies,
  2210. "cdc-vdd-buck");
  2211. if (ret == -EINVAL) {
  2212. dev_err(dev, "%s: vdd buck is not disabled\n",
  2213. __func__);
  2214. return 0;
  2215. }
  2216. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  2217. }
  2218. return 0;
  2219. }
  2220. static int wcd937x_resume(struct device *dev)
  2221. {
  2222. return 0;
  2223. }
  2224. #endif
  2225. static int wcd937x_reset(struct device *dev)
  2226. {
  2227. struct wcd937x_priv *wcd937x = NULL;
  2228. int rc = 0;
  2229. int value = 0;
  2230. if (!dev)
  2231. return -ENODEV;
  2232. wcd937x = dev_get_drvdata(dev);
  2233. if (!wcd937x)
  2234. return -EINVAL;
  2235. if (!wcd937x->rst_np) {
  2236. dev_err(dev, "%s: reset gpio device node not specified\n",
  2237. __func__);
  2238. return -EINVAL;
  2239. }
  2240. value = msm_cdc_pinctrl_get_state(wcd937x->rst_np);
  2241. if (value > 0)
  2242. return 0;
  2243. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2244. if (rc) {
  2245. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2246. __func__);
  2247. return rc;
  2248. }
  2249. /* 20ms sleep required after pulling the reset gpio to LOW */
  2250. usleep_range(20, 30);
  2251. rc = msm_cdc_pinctrl_select_active_state(wcd937x->rst_np);
  2252. if (rc) {
  2253. dev_err(dev, "%s: wcd active state request fail!\n",
  2254. __func__);
  2255. return rc;
  2256. }
  2257. /* 20ms sleep required after pulling the reset gpio to HIGH */
  2258. usleep_range(20, 30);
  2259. return rc;
  2260. }
  2261. static int wcd937x_read_of_property_u32(struct device *dev, const char *name,
  2262. u32 *val)
  2263. {
  2264. int rc = 0;
  2265. rc = of_property_read_u32(dev->of_node, name, val);
  2266. if (rc)
  2267. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2268. __func__, name, dev->of_node->full_name);
  2269. return rc;
  2270. }
  2271. static void wcd937x_dt_parse_micbias_info(struct device *dev,
  2272. struct wcd937x_micbias_setting *mb)
  2273. {
  2274. u32 prop_val = 0;
  2275. int rc = 0;
  2276. /* MB1 */
  2277. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2278. NULL)) {
  2279. rc = wcd937x_read_of_property_u32(dev,
  2280. "qcom,cdc-micbias1-mv",
  2281. &prop_val);
  2282. if (!rc)
  2283. mb->micb1_mv = prop_val;
  2284. } else {
  2285. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2286. __func__);
  2287. }
  2288. /* MB2 */
  2289. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2290. NULL)) {
  2291. rc = wcd937x_read_of_property_u32(dev,
  2292. "qcom,cdc-micbias2-mv",
  2293. &prop_val);
  2294. if (!rc)
  2295. mb->micb2_mv = prop_val;
  2296. } else {
  2297. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2298. __func__);
  2299. }
  2300. /* MB3 */
  2301. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2302. NULL)) {
  2303. rc = wcd937x_read_of_property_u32(dev,
  2304. "qcom,cdc-micbias3-mv",
  2305. &prop_val);
  2306. if (!rc)
  2307. mb->micb3_mv = prop_val;
  2308. } else {
  2309. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2310. __func__);
  2311. }
  2312. }
  2313. static int wcd937x_reset_low(struct device *dev)
  2314. {
  2315. struct wcd937x_priv *wcd937x = NULL;
  2316. int rc = 0;
  2317. if (!dev)
  2318. return -ENODEV;
  2319. wcd937x = dev_get_drvdata(dev);
  2320. if (!wcd937x)
  2321. return -EINVAL;
  2322. if (!wcd937x->rst_np) {
  2323. dev_err(dev, "%s: reset gpio device node not specified\n",
  2324. __func__);
  2325. return -EINVAL;
  2326. }
  2327. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2328. if (rc) {
  2329. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2330. __func__);
  2331. return rc;
  2332. }
  2333. /* 20ms sleep required after pulling the reset gpio to LOW */
  2334. usleep_range(20, 30);
  2335. return rc;
  2336. }
  2337. struct wcd937x_pdata *wcd937x_populate_dt_data(struct device *dev)
  2338. {
  2339. struct wcd937x_pdata *pdata = NULL;
  2340. pdata = kzalloc(sizeof(struct wcd937x_pdata),
  2341. GFP_KERNEL);
  2342. if (!pdata)
  2343. return NULL;
  2344. pdata->rst_np = of_parse_phandle(dev->of_node,
  2345. "qcom,wcd-rst-gpio-node", 0);
  2346. if (!pdata->rst_np) {
  2347. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2348. __func__, "qcom,wcd-rst-gpio-node",
  2349. dev->of_node->full_name);
  2350. return NULL;
  2351. }
  2352. /* Parse power supplies */
  2353. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2354. &pdata->num_supplies);
  2355. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2356. dev_err(dev, "%s: no power supplies defined for codec\n",
  2357. __func__);
  2358. return NULL;
  2359. }
  2360. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2361. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2362. wcd937x_dt_parse_micbias_info(dev, &pdata->micbias);
  2363. return pdata;
  2364. }
  2365. static int wcd937x_wakeup(void *handle, bool enable)
  2366. {
  2367. struct wcd937x_priv *priv;
  2368. if (!handle) {
  2369. pr_err("%s: NULL handle\n", __func__);
  2370. return -EINVAL;
  2371. }
  2372. priv = (struct wcd937x_priv *)handle;
  2373. if (!priv->tx_swr_dev) {
  2374. pr_err("%s: tx swr dev is NULL\n", __func__);
  2375. return -EINVAL;
  2376. }
  2377. if (enable)
  2378. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2379. else
  2380. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2381. }
  2382. static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data)
  2383. {
  2384. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2385. __func__, irq);
  2386. return IRQ_HANDLED;
  2387. }
  2388. static int wcd937x_bind(struct device *dev)
  2389. {
  2390. int ret = 0, i = 0;
  2391. struct wcd937x_priv *wcd937x = NULL;
  2392. struct wcd937x_pdata *pdata = NULL;
  2393. struct wcd_ctrl_platform_data *plat_data = NULL;
  2394. wcd937x = kzalloc(sizeof(struct wcd937x_priv), GFP_KERNEL);
  2395. if (!wcd937x)
  2396. return -ENOMEM;
  2397. dev_set_drvdata(dev, wcd937x);
  2398. pdata = wcd937x_populate_dt_data(dev);
  2399. if (!pdata) {
  2400. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2401. return -EINVAL;
  2402. }
  2403. wcd937x->dev = dev;
  2404. wcd937x->dev->platform_data = pdata;
  2405. wcd937x->rst_np = pdata->rst_np;
  2406. ret = msm_cdc_init_supplies(dev, &wcd937x->supplies,
  2407. pdata->regulator, pdata->num_supplies);
  2408. if (!wcd937x->supplies) {
  2409. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2410. __func__);
  2411. goto err_bind_all;
  2412. }
  2413. plat_data = dev_get_platdata(dev->parent);
  2414. if (!plat_data) {
  2415. dev_err(dev, "%s: platform data from parent is NULL\n",
  2416. __func__);
  2417. ret = -EINVAL;
  2418. goto err_bind_all;
  2419. }
  2420. wcd937x->handle = (void *)plat_data->handle;
  2421. if (!wcd937x->handle) {
  2422. dev_err(dev, "%s: handle is NULL\n", __func__);
  2423. ret = -EINVAL;
  2424. goto err_bind_all;
  2425. }
  2426. wcd937x->update_wcd_event = plat_data->update_wcd_event;
  2427. if (!wcd937x->update_wcd_event) {
  2428. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2429. __func__);
  2430. ret = -EINVAL;
  2431. goto err_bind_all;
  2432. }
  2433. wcd937x->register_notifier = plat_data->register_notifier;
  2434. if (!wcd937x->register_notifier) {
  2435. dev_err(dev, "%s: register_notifier api is null!\n",
  2436. __func__);
  2437. ret = -EINVAL;
  2438. goto err_bind_all;
  2439. }
  2440. ret = msm_cdc_enable_static_supplies(dev, wcd937x->supplies,
  2441. pdata->regulator,
  2442. pdata->num_supplies);
  2443. if (ret) {
  2444. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2445. __func__);
  2446. goto err_bind_all;
  2447. }
  2448. wcd937x_reset(dev);
  2449. /*
  2450. * Add 5msec delay to provide sufficient time for
  2451. * soundwire auto enumeration of slave devices as
  2452. * as per HW requirement.
  2453. */
  2454. usleep_range(5000, 5010);
  2455. wcd937x->wakeup = wcd937x_wakeup;
  2456. ret = component_bind_all(dev, wcd937x);
  2457. if (ret) {
  2458. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2459. __func__, ret);
  2460. goto err_bind_all;
  2461. }
  2462. ret = wcd937x_parse_port_mapping(dev, "qcom,rx_swr_ch_map", CODEC_RX);
  2463. ret |= wcd937x_parse_port_mapping(dev, "qcom,tx_swr_ch_map", CODEC_TX);
  2464. if (ret) {
  2465. dev_err(dev, "Failed to read port mapping\n");
  2466. goto err;
  2467. }
  2468. wcd937x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2469. if (!wcd937x->rx_swr_dev) {
  2470. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2471. __func__);
  2472. ret = -ENODEV;
  2473. goto err;
  2474. }
  2475. wcd937x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2476. if (!wcd937x->tx_swr_dev) {
  2477. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2478. __func__);
  2479. ret = -ENODEV;
  2480. goto err;
  2481. }
  2482. wcd937x->regmap = devm_regmap_init_swr(wcd937x->tx_swr_dev,
  2483. &wcd937x_regmap_config);
  2484. if (!wcd937x->regmap) {
  2485. dev_err(dev, "%s: Regmap init failed\n",
  2486. __func__);
  2487. goto err;
  2488. }
  2489. /* Set all interupts as edge triggered */
  2490. for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++)
  2491. regmap_write(wcd937x->regmap,
  2492. (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2493. wcd937x_regmap_irq_chip.irq_drv_data = wcd937x;
  2494. wcd937x->irq_info.wcd_regmap_irq_chip = &wcd937x_regmap_irq_chip;
  2495. wcd937x->irq_info.codec_name = "WCD937X";
  2496. wcd937x->irq_info.regmap = wcd937x->regmap;
  2497. wcd937x->irq_info.dev = dev;
  2498. ret = wcd_irq_init(&wcd937x->irq_info, &wcd937x->virq);
  2499. if (ret) {
  2500. dev_err(dev, "%s: IRQ init failed: %d\n",
  2501. __func__, ret);
  2502. goto err;
  2503. }
  2504. wcd937x->tx_swr_dev->slave_irq = wcd937x->virq;
  2505. ret = wcd937x_set_micbias_data(wcd937x, pdata);
  2506. if (ret < 0) {
  2507. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  2508. goto err_irq;
  2509. }
  2510. mutex_init(&wcd937x->micb_lock);
  2511. mutex_init(&wcd937x->ana_tx_clk_lock);
  2512. /* Request for watchdog interrupt */
  2513. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT,
  2514. "HPHR PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2515. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT,
  2516. "HPHL PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2517. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT,
  2518. "AUX PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2519. /* Enable watchdog interrupt for HPH and AUX */
  2520. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT);
  2521. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT);
  2522. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  2523. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x,
  2524. NULL, 0);
  2525. if (ret) {
  2526. dev_err(dev, "%s: Codec registration failed\n",
  2527. __func__);
  2528. goto err_irq;
  2529. }
  2530. return ret;
  2531. err_irq:
  2532. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2533. err:
  2534. component_unbind_all(dev, wcd937x);
  2535. err_bind_all:
  2536. dev_set_drvdata(dev, NULL);
  2537. kfree(pdata);
  2538. kfree(wcd937x);
  2539. return ret;
  2540. }
  2541. static void wcd937x_unbind(struct device *dev)
  2542. {
  2543. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  2544. struct wcd937x_pdata *pdata = dev_get_platdata(wcd937x->dev);
  2545. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2546. snd_soc_unregister_component(dev);
  2547. component_unbind_all(dev, wcd937x);
  2548. mutex_destroy(&wcd937x->micb_lock);
  2549. mutex_destroy(&wcd937x->ana_tx_clk_lock);
  2550. dev_set_drvdata(dev, NULL);
  2551. kfree(pdata);
  2552. kfree(wcd937x);
  2553. }
  2554. static const struct of_device_id wcd937x_dt_match[] = {
  2555. { .compatible = "qcom,wcd937x-codec" },
  2556. {}
  2557. };
  2558. static const struct component_master_ops wcd937x_comp_ops = {
  2559. .bind = wcd937x_bind,
  2560. .unbind = wcd937x_unbind,
  2561. };
  2562. static int wcd937x_compare_of(struct device *dev, void *data)
  2563. {
  2564. return dev->of_node == data;
  2565. }
  2566. static void wcd937x_release_of(struct device *dev, void *data)
  2567. {
  2568. of_node_put(data);
  2569. }
  2570. static int wcd937x_add_slave_components(struct device *dev,
  2571. struct component_match **matchptr)
  2572. {
  2573. struct device_node *np, *rx_node, *tx_node;
  2574. np = dev->of_node;
  2575. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  2576. if (!rx_node) {
  2577. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  2578. return -ENODEV;
  2579. }
  2580. of_node_get(rx_node);
  2581. component_match_add_release(dev, matchptr,
  2582. wcd937x_release_of,
  2583. wcd937x_compare_of,
  2584. rx_node);
  2585. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  2586. if (!tx_node) {
  2587. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  2588. return -ENODEV;
  2589. }
  2590. of_node_get(tx_node);
  2591. component_match_add_release(dev, matchptr,
  2592. wcd937x_release_of,
  2593. wcd937x_compare_of,
  2594. tx_node);
  2595. return 0;
  2596. }
  2597. static int wcd937x_probe(struct platform_device *pdev)
  2598. {
  2599. struct component_match *match = NULL;
  2600. int ret;
  2601. ret = wcd937x_add_slave_components(&pdev->dev, &match);
  2602. if (ret)
  2603. return ret;
  2604. return component_master_add_with_match(&pdev->dev,
  2605. &wcd937x_comp_ops, match);
  2606. }
  2607. static int wcd937x_remove(struct platform_device *pdev)
  2608. {
  2609. component_master_del(&pdev->dev, &wcd937x_comp_ops);
  2610. dev_set_drvdata(&pdev->dev, NULL);
  2611. return 0;
  2612. }
  2613. #ifdef CONFIG_PM_SLEEP
  2614. static const struct dev_pm_ops wcd937x_dev_pm_ops = {
  2615. SET_SYSTEM_SLEEP_PM_OPS(
  2616. wcd937x_suspend,
  2617. wcd937x_resume
  2618. )
  2619. };
  2620. #endif
  2621. static struct platform_driver wcd937x_codec_driver = {
  2622. .probe = wcd937x_probe,
  2623. .remove = wcd937x_remove,
  2624. .driver = {
  2625. .name = "wcd937x_codec",
  2626. .owner = THIS_MODULE,
  2627. .of_match_table = of_match_ptr(wcd937x_dt_match),
  2628. #ifdef CONFIG_PM_SLEEP
  2629. .pm = &wcd937x_dev_pm_ops,
  2630. #endif
  2631. .suppress_bind_attrs = true,
  2632. },
  2633. };
  2634. module_platform_driver(wcd937x_codec_driver);
  2635. MODULE_DESCRIPTION("WCD937X Codec driver");
  2636. MODULE_LICENSE("GPL v2");