sde_crtc.c 167 KB

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  1. /*
  2. * Copyright (c) 2014-2020 The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/sort.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/ktime.h>
  22. #include <drm/sde_drm.h>
  23. #include <drm/drm_mode.h>
  24. #include <drm/drm_crtc.h>
  25. #include <drm/drm_probe_helper.h>
  26. #include <drm/drm_flip_work.h>
  27. #include "sde_kms.h"
  28. #include "sde_hw_lm.h"
  29. #include "sde_hw_ctl.h"
  30. #include "sde_crtc.h"
  31. #include "sde_plane.h"
  32. #include "sde_hw_util.h"
  33. #include "sde_hw_catalog.h"
  34. #include "sde_color_processing.h"
  35. #include "sde_encoder.h"
  36. #include "sde_connector.h"
  37. #include "sde_vbif.h"
  38. #include "sde_power_handle.h"
  39. #include "sde_core_perf.h"
  40. #include "sde_trace.h"
  41. #define SDE_PSTATES_MAX (SDE_STAGE_MAX * 4)
  42. #define SDE_MULTIRECT_PLANE_MAX (SDE_STAGE_MAX * 2)
  43. struct sde_crtc_custom_events {
  44. u32 event;
  45. int (*func)(struct drm_crtc *crtc, bool en,
  46. struct sde_irq_callback *irq);
  47. };
  48. static int sde_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
  49. bool en, struct sde_irq_callback *ad_irq);
  50. static int sde_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
  51. bool en, struct sde_irq_callback *idle_irq);
  52. static int sde_crtc_pm_event_handler(struct drm_crtc *crtc, bool en,
  53. struct sde_irq_callback *noirq);
  54. static struct sde_crtc_custom_events custom_events[] = {
  55. {DRM_EVENT_AD_BACKLIGHT, sde_cp_ad_interrupt},
  56. {DRM_EVENT_CRTC_POWER, sde_crtc_power_interrupt_handler},
  57. {DRM_EVENT_IDLE_NOTIFY, sde_crtc_idle_interrupt_handler},
  58. {DRM_EVENT_HISTOGRAM, sde_cp_hist_interrupt},
  59. {DRM_EVENT_SDE_POWER, sde_crtc_pm_event_handler},
  60. {DRM_EVENT_LTM_HIST, sde_cp_ltm_hist_interrupt},
  61. {DRM_EVENT_LTM_WB_PB, sde_cp_ltm_wb_pb_interrupt},
  62. {DRM_EVENT_LTM_OFF, sde_cp_ltm_off_event_handler},
  63. };
  64. /* default input fence timeout, in ms */
  65. #define SDE_CRTC_INPUT_FENCE_TIMEOUT 10000
  66. /*
  67. * The default input fence timeout is 2 seconds while max allowed
  68. * range is 10 seconds. Any value above 10 seconds adds glitches beyond
  69. * tolerance limit.
  70. */
  71. #define SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT 10000
  72. /* layer mixer index on sde_crtc */
  73. #define LEFT_MIXER 0
  74. #define RIGHT_MIXER 1
  75. #define MISR_BUFF_SIZE 256
  76. /*
  77. * Time period for fps calculation in micro seconds.
  78. * Default value is set to 1 sec.
  79. */
  80. #define DEFAULT_FPS_PERIOD_1_SEC 1000000
  81. #define MAX_FPS_PERIOD_5_SECONDS 5000000
  82. #define MAX_FRAME_COUNT 1000
  83. #define MILI_TO_MICRO 1000
  84. static inline struct sde_kms *_sde_crtc_get_kms(struct drm_crtc *crtc)
  85. {
  86. struct msm_drm_private *priv;
  87. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  88. SDE_ERROR("invalid crtc\n");
  89. return NULL;
  90. }
  91. priv = crtc->dev->dev_private;
  92. if (!priv || !priv->kms) {
  93. SDE_ERROR("invalid kms\n");
  94. return NULL;
  95. }
  96. return to_sde_kms(priv->kms);
  97. }
  98. /**
  99. * sde_crtc_calc_fps() - Calculates fps value.
  100. * @sde_crtc : CRTC structure
  101. *
  102. * This function is called at frame done. It counts the number
  103. * of frames done for every 1 sec. Stores the value in measured_fps.
  104. * measured_fps value is 10 times the calculated fps value.
  105. * For example, measured_fps= 594 for calculated fps of 59.4
  106. */
  107. static void sde_crtc_calc_fps(struct sde_crtc *sde_crtc)
  108. {
  109. ktime_t current_time_us;
  110. u64 fps, diff_us;
  111. current_time_us = ktime_get();
  112. diff_us = (u64)ktime_us_delta(current_time_us,
  113. sde_crtc->fps_info.last_sampled_time_us);
  114. sde_crtc->fps_info.frame_count++;
  115. if (diff_us >= DEFAULT_FPS_PERIOD_1_SEC) {
  116. /* Multiplying with 10 to get fps in floating point */
  117. fps = ((u64)sde_crtc->fps_info.frame_count)
  118. * DEFAULT_FPS_PERIOD_1_SEC * 10;
  119. do_div(fps, diff_us);
  120. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  121. SDE_DEBUG(" FPS for crtc%d is %d.%d\n",
  122. sde_crtc->base.base.id, (unsigned int)fps/10,
  123. (unsigned int)fps%10);
  124. sde_crtc->fps_info.last_sampled_time_us = current_time_us;
  125. sde_crtc->fps_info.frame_count = 0;
  126. }
  127. if (!sde_crtc->fps_info.time_buf)
  128. return;
  129. /**
  130. * Array indexing is based on sliding window algorithm.
  131. * sde_crtc->time_buf has a maximum capacity of MAX_FRAME_COUNT
  132. * time slots. As the count increases to MAX_FRAME_COUNT + 1, the
  133. * counter loops around and comes back to the first index to store
  134. * the next ktime.
  135. */
  136. sde_crtc->fps_info.time_buf[sde_crtc->fps_info.next_time_index++] =
  137. ktime_get();
  138. sde_crtc->fps_info.next_time_index %= MAX_FRAME_COUNT;
  139. }
  140. static void _sde_crtc_deinit_events(struct sde_crtc *sde_crtc)
  141. {
  142. if (!sde_crtc)
  143. return;
  144. }
  145. static int _sde_debugfs_fps_status_show(struct seq_file *s, void *data)
  146. {
  147. struct sde_crtc *sde_crtc;
  148. u64 fps_int, fps_float;
  149. ktime_t current_time_us;
  150. u64 fps, diff_us;
  151. if (!s || !s->private) {
  152. SDE_ERROR("invalid input param(s)\n");
  153. return -EAGAIN;
  154. }
  155. sde_crtc = s->private;
  156. current_time_us = ktime_get();
  157. diff_us = (u64)ktime_us_delta(current_time_us,
  158. sde_crtc->fps_info.last_sampled_time_us);
  159. if (diff_us >= DEFAULT_FPS_PERIOD_1_SEC) {
  160. /* Multiplying with 10 to get fps in floating point */
  161. fps = ((u64)sde_crtc->fps_info.frame_count)
  162. * DEFAULT_FPS_PERIOD_1_SEC * 10;
  163. do_div(fps, diff_us);
  164. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  165. sde_crtc->fps_info.last_sampled_time_us = current_time_us;
  166. sde_crtc->fps_info.frame_count = 0;
  167. SDE_DEBUG("Measured FPS for crtc%d is %d.%d\n",
  168. sde_crtc->base.base.id, (unsigned int)fps/10,
  169. (unsigned int)fps%10);
  170. }
  171. fps_int = (unsigned int) sde_crtc->fps_info.measured_fps;
  172. fps_float = do_div(fps_int, 10);
  173. seq_printf(s, "fps: %llu.%llu\n", fps_int, fps_float);
  174. return 0;
  175. }
  176. static int _sde_debugfs_fps_status(struct inode *inode, struct file *file)
  177. {
  178. return single_open(file, _sde_debugfs_fps_status_show,
  179. inode->i_private);
  180. }
  181. static ssize_t fps_periodicity_ms_store(struct device *device,
  182. struct device_attribute *attr, const char *buf, size_t count)
  183. {
  184. struct drm_crtc *crtc;
  185. struct sde_crtc *sde_crtc;
  186. int res;
  187. /* Base of the input */
  188. int cnt = 10;
  189. if (!device || !buf) {
  190. SDE_ERROR("invalid input param(s)\n");
  191. return -EAGAIN;
  192. }
  193. crtc = dev_get_drvdata(device);
  194. if (!crtc)
  195. return -EINVAL;
  196. sde_crtc = to_sde_crtc(crtc);
  197. res = kstrtou32(buf, cnt, &sde_crtc->fps_info.fps_periodic_duration);
  198. if (res < 0)
  199. return res;
  200. if (sde_crtc->fps_info.fps_periodic_duration <= 0)
  201. sde_crtc->fps_info.fps_periodic_duration =
  202. DEFAULT_FPS_PERIOD_1_SEC;
  203. else if ((sde_crtc->fps_info.fps_periodic_duration) * MILI_TO_MICRO >
  204. MAX_FPS_PERIOD_5_SECONDS)
  205. sde_crtc->fps_info.fps_periodic_duration =
  206. MAX_FPS_PERIOD_5_SECONDS;
  207. else
  208. sde_crtc->fps_info.fps_periodic_duration *= MILI_TO_MICRO;
  209. return count;
  210. }
  211. static ssize_t fps_periodicity_ms_show(struct device *device,
  212. struct device_attribute *attr, char *buf)
  213. {
  214. struct drm_crtc *crtc;
  215. struct sde_crtc *sde_crtc;
  216. if (!device || !buf) {
  217. SDE_ERROR("invalid input param(s)\n");
  218. return -EAGAIN;
  219. }
  220. crtc = dev_get_drvdata(device);
  221. if (!crtc)
  222. return -EINVAL;
  223. sde_crtc = to_sde_crtc(crtc);
  224. return scnprintf(buf, PAGE_SIZE, "%d\n",
  225. (sde_crtc->fps_info.fps_periodic_duration)/MILI_TO_MICRO);
  226. }
  227. static ssize_t measured_fps_show(struct device *device,
  228. struct device_attribute *attr, char *buf)
  229. {
  230. struct drm_crtc *crtc;
  231. struct sde_crtc *sde_crtc;
  232. uint64_t fps_int, fps_decimal;
  233. u64 fps = 0, frame_count = 0;
  234. ktime_t current_time;
  235. int i = 0, current_time_index;
  236. u64 diff_us;
  237. if (!device || !buf) {
  238. SDE_ERROR("invalid input param(s)\n");
  239. return -EAGAIN;
  240. }
  241. crtc = dev_get_drvdata(device);
  242. if (!crtc) {
  243. scnprintf(buf, PAGE_SIZE, "fps information not available");
  244. return -EINVAL;
  245. }
  246. sde_crtc = to_sde_crtc(crtc);
  247. if (!sde_crtc->fps_info.time_buf) {
  248. scnprintf(buf, PAGE_SIZE,
  249. "timebuf null - fps information not available");
  250. return -EINVAL;
  251. }
  252. /**
  253. * Whenever the time_index counter comes to zero upon decrementing,
  254. * it is set to the last index since it is the next index that we
  255. * should check for calculating the buftime.
  256. */
  257. current_time_index = (sde_crtc->fps_info.next_time_index == 0) ?
  258. MAX_FRAME_COUNT - 1 : (sde_crtc->fps_info.next_time_index - 1);
  259. current_time = ktime_get();
  260. for (i = 0; i < MAX_FRAME_COUNT; i++) {
  261. u64 ptime = (u64)ktime_to_us(current_time);
  262. u64 buftime = (u64)ktime_to_us(
  263. sde_crtc->fps_info.time_buf[current_time_index]);
  264. diff_us = (u64)ktime_us_delta(current_time,
  265. sde_crtc->fps_info.time_buf[current_time_index]);
  266. if (ptime > buftime && diff_us >= (u64)
  267. sde_crtc->fps_info.fps_periodic_duration) {
  268. /* Multiplying with 10 to get fps in floating point */
  269. fps = frame_count * DEFAULT_FPS_PERIOD_1_SEC * 10;
  270. do_div(fps, diff_us);
  271. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  272. SDE_DEBUG("measured fps: %d\n",
  273. sde_crtc->fps_info.measured_fps);
  274. break;
  275. }
  276. current_time_index = (current_time_index == 0) ?
  277. (MAX_FRAME_COUNT - 1) : (current_time_index - 1);
  278. SDE_DEBUG("current time index: %d\n", current_time_index);
  279. frame_count++;
  280. }
  281. if (i == MAX_FRAME_COUNT) {
  282. current_time_index = (sde_crtc->fps_info.next_time_index == 0) ?
  283. MAX_FRAME_COUNT - 1 : (sde_crtc->fps_info.next_time_index - 1);
  284. diff_us = (u64)ktime_us_delta(current_time,
  285. sde_crtc->fps_info.time_buf[current_time_index]);
  286. if (diff_us >= sde_crtc->fps_info.fps_periodic_duration) {
  287. /* Multiplying with 10 to get fps in floating point */
  288. fps = (frame_count) * DEFAULT_FPS_PERIOD_1_SEC * 10;
  289. do_div(fps, diff_us);
  290. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  291. }
  292. }
  293. fps_int = (uint64_t) sde_crtc->fps_info.measured_fps;
  294. fps_decimal = do_div(fps_int, 10);
  295. return scnprintf(buf, PAGE_SIZE,
  296. "fps: %d.%d duration:%d frame_count:%lld\n", fps_int, fps_decimal,
  297. sde_crtc->fps_info.fps_periodic_duration, frame_count);
  298. }
  299. static ssize_t vsync_event_show(struct device *device,
  300. struct device_attribute *attr, char *buf)
  301. {
  302. struct drm_crtc *crtc;
  303. struct sde_crtc *sde_crtc;
  304. if (!device || !buf) {
  305. SDE_ERROR("invalid input param(s)\n");
  306. return -EAGAIN;
  307. }
  308. crtc = dev_get_drvdata(device);
  309. sde_crtc = to_sde_crtc(crtc);
  310. return scnprintf(buf, PAGE_SIZE, "VSYNC=%llu\n",
  311. ktime_to_ns(sde_crtc->vblank_last_cb_time));
  312. }
  313. static DEVICE_ATTR_RO(vsync_event);
  314. static DEVICE_ATTR_RO(measured_fps);
  315. static DEVICE_ATTR_RW(fps_periodicity_ms);
  316. static struct attribute *sde_crtc_dev_attrs[] = {
  317. &dev_attr_vsync_event.attr,
  318. &dev_attr_measured_fps.attr,
  319. &dev_attr_fps_periodicity_ms.attr,
  320. NULL
  321. };
  322. static const struct attribute_group sde_crtc_attr_group = {
  323. .attrs = sde_crtc_dev_attrs,
  324. };
  325. static const struct attribute_group *sde_crtc_attr_groups[] = {
  326. &sde_crtc_attr_group,
  327. NULL,
  328. };
  329. static void sde_crtc_destroy(struct drm_crtc *crtc)
  330. {
  331. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  332. SDE_DEBUG("\n");
  333. if (!crtc)
  334. return;
  335. if (sde_crtc->vsync_event_sf)
  336. sysfs_put(sde_crtc->vsync_event_sf);
  337. if (sde_crtc->sysfs_dev)
  338. device_unregister(sde_crtc->sysfs_dev);
  339. if (sde_crtc->blob_info)
  340. drm_property_blob_put(sde_crtc->blob_info);
  341. msm_property_destroy(&sde_crtc->property_info);
  342. sde_cp_crtc_destroy_properties(crtc);
  343. sde_fence_deinit(sde_crtc->output_fence);
  344. _sde_crtc_deinit_events(sde_crtc);
  345. drm_crtc_cleanup(crtc);
  346. mutex_destroy(&sde_crtc->crtc_lock);
  347. kfree(sde_crtc);
  348. }
  349. static bool sde_crtc_mode_fixup(struct drm_crtc *crtc,
  350. const struct drm_display_mode *mode,
  351. struct drm_display_mode *adjusted_mode)
  352. {
  353. SDE_DEBUG("\n");
  354. if ((msm_is_mode_seamless(adjusted_mode) ||
  355. (msm_is_mode_seamless_vrr(adjusted_mode) ||
  356. msm_is_mode_seamless_dyn_clk(adjusted_mode))) &&
  357. (!crtc->enabled)) {
  358. SDE_ERROR("crtc state prevents seamless transition\n");
  359. return false;
  360. }
  361. return true;
  362. }
  363. static void _sde_crtc_setup_blend_cfg(struct sde_crtc_mixer *mixer,
  364. struct sde_plane_state *pstate, struct sde_format *format)
  365. {
  366. uint32_t blend_op, fg_alpha, bg_alpha;
  367. uint32_t blend_type;
  368. struct sde_hw_mixer *lm = mixer->hw_lm;
  369. /* default to opaque blending */
  370. fg_alpha = sde_plane_get_property(pstate, PLANE_PROP_ALPHA);
  371. bg_alpha = 0xFF - fg_alpha;
  372. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST | SDE_BLEND_BG_ALPHA_BG_CONST;
  373. blend_type = sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP);
  374. SDE_DEBUG("blend type:0x%x blend alpha:0x%x\n", blend_type, fg_alpha);
  375. switch (blend_type) {
  376. case SDE_DRM_BLEND_OP_OPAQUE:
  377. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST |
  378. SDE_BLEND_BG_ALPHA_BG_CONST;
  379. break;
  380. case SDE_DRM_BLEND_OP_PREMULTIPLIED:
  381. if (format->alpha_enable) {
  382. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST |
  383. SDE_BLEND_BG_ALPHA_FG_PIXEL;
  384. if (fg_alpha != 0xff) {
  385. bg_alpha = fg_alpha;
  386. blend_op |= SDE_BLEND_BG_MOD_ALPHA |
  387. SDE_BLEND_BG_INV_MOD_ALPHA;
  388. } else {
  389. blend_op |= SDE_BLEND_BG_INV_ALPHA;
  390. }
  391. }
  392. break;
  393. case SDE_DRM_BLEND_OP_COVERAGE:
  394. if (format->alpha_enable) {
  395. blend_op = SDE_BLEND_FG_ALPHA_FG_PIXEL |
  396. SDE_BLEND_BG_ALPHA_FG_PIXEL;
  397. if (fg_alpha != 0xff) {
  398. bg_alpha = fg_alpha;
  399. blend_op |= SDE_BLEND_FG_MOD_ALPHA |
  400. SDE_BLEND_BG_MOD_ALPHA |
  401. SDE_BLEND_BG_INV_MOD_ALPHA;
  402. } else {
  403. blend_op |= SDE_BLEND_BG_INV_ALPHA;
  404. }
  405. }
  406. break;
  407. default:
  408. /* do nothing */
  409. break;
  410. }
  411. lm->ops.setup_blend_config(lm, pstate->stage, fg_alpha,
  412. bg_alpha, blend_op);
  413. SDE_DEBUG(
  414. "format: %4.4s, alpha_enable %u fg alpha:0x%x bg alpha:0x%x blend_op:0x%x\n",
  415. (char *) &format->base.pixel_format,
  416. format->alpha_enable, fg_alpha, bg_alpha, blend_op);
  417. }
  418. static void _sde_crtc_setup_dim_layer_cfg(struct drm_crtc *crtc,
  419. struct sde_crtc *sde_crtc, struct sde_crtc_mixer *mixer,
  420. struct sde_hw_dim_layer *dim_layer)
  421. {
  422. struct sde_crtc_state *cstate;
  423. struct sde_hw_mixer *lm;
  424. struct sde_hw_dim_layer split_dim_layer;
  425. int i;
  426. if (!dim_layer->rect.w || !dim_layer->rect.h) {
  427. SDE_DEBUG("empty dim_layer\n");
  428. return;
  429. }
  430. cstate = to_sde_crtc_state(crtc->state);
  431. SDE_DEBUG("dim_layer - flags:%d, stage:%d\n",
  432. dim_layer->flags, dim_layer->stage);
  433. split_dim_layer.stage = dim_layer->stage;
  434. split_dim_layer.color_fill = dim_layer->color_fill;
  435. /*
  436. * traverse through the layer mixers attached to crtc and find the
  437. * intersecting dim layer rect in each LM and program accordingly.
  438. */
  439. for (i = 0; i < sde_crtc->num_mixers; i++) {
  440. split_dim_layer.flags = dim_layer->flags;
  441. sde_kms_rect_intersect(&cstate->lm_roi[i], &dim_layer->rect,
  442. &split_dim_layer.rect);
  443. if (sde_kms_rect_is_null(&split_dim_layer.rect)) {
  444. /*
  445. * no extra programming required for non-intersecting
  446. * layer mixers with INCLUSIVE dim layer
  447. */
  448. if (split_dim_layer.flags & SDE_DRM_DIM_LAYER_INCLUSIVE)
  449. continue;
  450. /*
  451. * program the other non-intersecting layer mixers with
  452. * INCLUSIVE dim layer of full size for uniformity
  453. * with EXCLUSIVE dim layer config.
  454. */
  455. split_dim_layer.flags &= ~SDE_DRM_DIM_LAYER_EXCLUSIVE;
  456. split_dim_layer.flags |= SDE_DRM_DIM_LAYER_INCLUSIVE;
  457. memcpy(&split_dim_layer.rect, &cstate->lm_bounds[i],
  458. sizeof(split_dim_layer.rect));
  459. } else {
  460. split_dim_layer.rect.x =
  461. split_dim_layer.rect.x -
  462. cstate->lm_roi[i].x;
  463. split_dim_layer.rect.y =
  464. split_dim_layer.rect.y -
  465. cstate->lm_roi[i].y;
  466. }
  467. SDE_EVT32_VERBOSE(DRMID(crtc),
  468. cstate->lm_roi[i].x,
  469. cstate->lm_roi[i].y,
  470. cstate->lm_roi[i].w,
  471. cstate->lm_roi[i].h,
  472. dim_layer->rect.x,
  473. dim_layer->rect.y,
  474. dim_layer->rect.w,
  475. dim_layer->rect.h,
  476. split_dim_layer.rect.x,
  477. split_dim_layer.rect.y,
  478. split_dim_layer.rect.w,
  479. split_dim_layer.rect.h);
  480. SDE_DEBUG("split_dim_layer - LM:%d, rect:{%d,%d,%d,%d}}\n",
  481. i, split_dim_layer.rect.x, split_dim_layer.rect.y,
  482. split_dim_layer.rect.w, split_dim_layer.rect.h);
  483. lm = mixer[i].hw_lm;
  484. mixer[i].mixer_op_mode |= 1 << split_dim_layer.stage;
  485. lm->ops.setup_dim_layer(lm, &split_dim_layer);
  486. }
  487. }
  488. void sde_crtc_get_crtc_roi(struct drm_crtc_state *state,
  489. const struct sde_rect **crtc_roi)
  490. {
  491. struct sde_crtc_state *crtc_state;
  492. if (!state || !crtc_roi)
  493. return;
  494. crtc_state = to_sde_crtc_state(state);
  495. *crtc_roi = &crtc_state->crtc_roi;
  496. }
  497. bool sde_crtc_is_crtc_roi_dirty(struct drm_crtc_state *state)
  498. {
  499. struct sde_crtc_state *cstate;
  500. struct sde_crtc *sde_crtc;
  501. if (!state || !state->crtc)
  502. return false;
  503. sde_crtc = to_sde_crtc(state->crtc);
  504. cstate = to_sde_crtc_state(state);
  505. return msm_property_is_dirty(&sde_crtc->property_info,
  506. &cstate->property_state, CRTC_PROP_ROI_V1);
  507. }
  508. static int _sde_crtc_set_roi_v1(struct drm_crtc_state *state,
  509. void __user *usr_ptr)
  510. {
  511. struct drm_crtc *crtc;
  512. struct sde_crtc_state *cstate;
  513. struct sde_drm_roi_v1 roi_v1;
  514. int i;
  515. if (!state) {
  516. SDE_ERROR("invalid args\n");
  517. return -EINVAL;
  518. }
  519. cstate = to_sde_crtc_state(state);
  520. crtc = cstate->base.crtc;
  521. memset(&cstate->user_roi_list, 0, sizeof(cstate->user_roi_list));
  522. if (!usr_ptr) {
  523. SDE_DEBUG("crtc%d: rois cleared\n", DRMID(crtc));
  524. return 0;
  525. }
  526. if (copy_from_user(&roi_v1, usr_ptr, sizeof(roi_v1))) {
  527. SDE_ERROR("crtc%d: failed to copy roi_v1 data\n", DRMID(crtc));
  528. return -EINVAL;
  529. }
  530. SDE_DEBUG("crtc%d: num_rects %d\n", DRMID(crtc), roi_v1.num_rects);
  531. if (roi_v1.num_rects == 0) {
  532. SDE_DEBUG("crtc%d: rois cleared\n", DRMID(crtc));
  533. return 0;
  534. }
  535. if (roi_v1.num_rects > SDE_MAX_ROI_V1) {
  536. SDE_ERROR("crtc%d: too many rects specified: %d\n", DRMID(crtc),
  537. roi_v1.num_rects);
  538. return -EINVAL;
  539. }
  540. cstate->user_roi_list.num_rects = roi_v1.num_rects;
  541. for (i = 0; i < roi_v1.num_rects; ++i) {
  542. cstate->user_roi_list.roi[i] = roi_v1.roi[i];
  543. SDE_DEBUG("crtc%d: roi%d: roi (%d,%d) (%d,%d)\n",
  544. DRMID(crtc), i,
  545. cstate->user_roi_list.roi[i].x1,
  546. cstate->user_roi_list.roi[i].y1,
  547. cstate->user_roi_list.roi[i].x2,
  548. cstate->user_roi_list.roi[i].y2);
  549. SDE_EVT32_VERBOSE(DRMID(crtc),
  550. cstate->user_roi_list.roi[i].x1,
  551. cstate->user_roi_list.roi[i].y1,
  552. cstate->user_roi_list.roi[i].x2,
  553. cstate->user_roi_list.roi[i].y2);
  554. }
  555. return 0;
  556. }
  557. static bool _sde_crtc_setup_is_3dmux_dsc(struct drm_crtc_state *state)
  558. {
  559. int i;
  560. struct sde_crtc_state *cstate;
  561. bool is_3dmux_dsc = false;
  562. cstate = to_sde_crtc_state(state);
  563. for (i = 0; i < cstate->num_connectors; i++) {
  564. struct drm_connector *conn = cstate->connectors[i];
  565. if (sde_connector_get_topology_name(conn) ==
  566. SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC)
  567. is_3dmux_dsc = true;
  568. }
  569. return is_3dmux_dsc;
  570. }
  571. static int _sde_crtc_set_crtc_roi(struct drm_crtc *crtc,
  572. struct drm_crtc_state *state)
  573. {
  574. struct drm_connector *conn;
  575. struct drm_connector_state *conn_state;
  576. struct sde_crtc *sde_crtc;
  577. struct sde_crtc_state *crtc_state;
  578. struct sde_rect *crtc_roi;
  579. struct msm_mode_info mode_info;
  580. int i = 0;
  581. int rc;
  582. bool is_crtc_roi_dirty;
  583. bool is_any_conn_roi_dirty;
  584. if (!crtc || !state)
  585. return -EINVAL;
  586. sde_crtc = to_sde_crtc(crtc);
  587. crtc_state = to_sde_crtc_state(state);
  588. crtc_roi = &crtc_state->crtc_roi;
  589. is_crtc_roi_dirty = sde_crtc_is_crtc_roi_dirty(state);
  590. is_any_conn_roi_dirty = false;
  591. for_each_new_connector_in_state(state->state, conn, conn_state, i) {
  592. struct sde_connector *sde_conn;
  593. struct sde_connector_state *sde_conn_state;
  594. struct sde_rect conn_roi;
  595. if (!conn_state || conn_state->crtc != crtc)
  596. continue;
  597. rc = sde_connector_state_get_mode_info(conn_state, &mode_info);
  598. if (rc) {
  599. SDE_ERROR("failed to get mode info\n");
  600. return -EINVAL;
  601. }
  602. sde_conn = to_sde_connector(conn_state->connector);
  603. sde_conn_state = to_sde_connector_state(conn_state);
  604. is_any_conn_roi_dirty = is_any_conn_roi_dirty ||
  605. msm_property_is_dirty(
  606. &sde_conn->property_info,
  607. &sde_conn_state->property_state,
  608. CONNECTOR_PROP_ROI_V1);
  609. if (!mode_info.roi_caps.enabled)
  610. continue;
  611. /*
  612. * current driver only supports same connector and crtc size,
  613. * but if support for different sizes is added, driver needs
  614. * to check the connector roi here to make sure is full screen
  615. * for dsc 3d-mux topology that doesn't support partial update.
  616. */
  617. if (memcmp(&sde_conn_state->rois, &crtc_state->user_roi_list,
  618. sizeof(crtc_state->user_roi_list))) {
  619. SDE_ERROR("%s: crtc -> conn roi scaling unsupported\n",
  620. sde_crtc->name);
  621. return -EINVAL;
  622. }
  623. sde_kms_rect_merge_rectangles(&sde_conn_state->rois, &conn_roi);
  624. SDE_EVT32_VERBOSE(DRMID(crtc), DRMID(conn),
  625. conn_roi.x, conn_roi.y,
  626. conn_roi.w, conn_roi.h);
  627. }
  628. /*
  629. * Check against CRTC ROI and Connector ROI not being updated together.
  630. * This restriction should be relaxed when Connector ROI scaling is
  631. * supported.
  632. */
  633. if (is_any_conn_roi_dirty != is_crtc_roi_dirty) {
  634. SDE_ERROR("connector/crtc rois not updated together\n");
  635. return -EINVAL;
  636. }
  637. sde_kms_rect_merge_rectangles(&crtc_state->user_roi_list, crtc_roi);
  638. /* clear the ROI to null if it matches full screen anyways */
  639. if (crtc_roi->x == 0 && crtc_roi->y == 0 &&
  640. crtc_roi->w == state->adjusted_mode.hdisplay &&
  641. crtc_roi->h == state->adjusted_mode.vdisplay)
  642. memset(crtc_roi, 0, sizeof(*crtc_roi));
  643. SDE_DEBUG("%s: crtc roi (%d,%d,%d,%d)\n", sde_crtc->name,
  644. crtc_roi->x, crtc_roi->y, crtc_roi->w, crtc_roi->h);
  645. SDE_EVT32_VERBOSE(DRMID(crtc), crtc_roi->x, crtc_roi->y, crtc_roi->w,
  646. crtc_roi->h);
  647. return 0;
  648. }
  649. static int _sde_crtc_check_autorefresh(struct drm_crtc *crtc,
  650. struct drm_crtc_state *state)
  651. {
  652. struct sde_crtc *sde_crtc;
  653. struct sde_crtc_state *crtc_state;
  654. struct drm_connector *conn;
  655. struct drm_connector_state *conn_state;
  656. int i;
  657. if (!crtc || !state)
  658. return -EINVAL;
  659. sde_crtc = to_sde_crtc(crtc);
  660. crtc_state = to_sde_crtc_state(state);
  661. if (sde_kms_rect_is_null(&crtc_state->crtc_roi))
  662. return 0;
  663. /* partial update active, check if autorefresh is also requested */
  664. for_each_new_connector_in_state(state->state, conn, conn_state, i) {
  665. uint64_t autorefresh;
  666. if (!conn_state || conn_state->crtc != crtc)
  667. continue;
  668. autorefresh = sde_connector_get_property(conn_state,
  669. CONNECTOR_PROP_AUTOREFRESH);
  670. if (autorefresh) {
  671. SDE_ERROR(
  672. "%s: autorefresh & partial crtc roi incompatible %llu\n",
  673. sde_crtc->name, autorefresh);
  674. return -EINVAL;
  675. }
  676. }
  677. return 0;
  678. }
  679. static int _sde_crtc_set_lm_roi(struct drm_crtc *crtc,
  680. struct drm_crtc_state *state, int lm_idx)
  681. {
  682. struct sde_crtc *sde_crtc;
  683. struct sde_crtc_state *crtc_state;
  684. const struct sde_rect *crtc_roi;
  685. const struct sde_rect *lm_bounds;
  686. struct sde_rect *lm_roi;
  687. if (!crtc || !state || lm_idx >= ARRAY_SIZE(crtc_state->lm_bounds))
  688. return -EINVAL;
  689. sde_crtc = to_sde_crtc(crtc);
  690. crtc_state = to_sde_crtc_state(state);
  691. crtc_roi = &crtc_state->crtc_roi;
  692. lm_bounds = &crtc_state->lm_bounds[lm_idx];
  693. lm_roi = &crtc_state->lm_roi[lm_idx];
  694. if (sde_kms_rect_is_null(crtc_roi))
  695. memcpy(lm_roi, lm_bounds, sizeof(*lm_roi));
  696. else
  697. sde_kms_rect_intersect(crtc_roi, lm_bounds, lm_roi);
  698. SDE_DEBUG("%s: lm%d roi (%d,%d,%d,%d)\n", sde_crtc->name, lm_idx,
  699. lm_roi->x, lm_roi->y, lm_roi->w, lm_roi->h);
  700. /*
  701. * partial update is not supported with 3dmux dsc or dest scaler.
  702. * hence, crtc roi must match the mixer dimensions.
  703. */
  704. if (crtc_state->num_ds_enabled ||
  705. _sde_crtc_setup_is_3dmux_dsc(state)) {
  706. if (memcmp(lm_roi, lm_bounds, sizeof(struct sde_rect))) {
  707. SDE_ERROR("Unsupported: Dest scaler/3d mux DSC + PU\n");
  708. return -EINVAL;
  709. }
  710. }
  711. /* if any dimension is zero, clear all dimensions for clarity */
  712. if (sde_kms_rect_is_null(lm_roi))
  713. memset(lm_roi, 0, sizeof(*lm_roi));
  714. return 0;
  715. }
  716. static u32 _sde_crtc_get_displays_affected(struct drm_crtc *crtc,
  717. struct drm_crtc_state *state)
  718. {
  719. struct sde_crtc *sde_crtc;
  720. struct sde_crtc_state *crtc_state;
  721. u32 disp_bitmask = 0;
  722. int i;
  723. if (!crtc || !state) {
  724. pr_err("Invalid crtc or state\n");
  725. return 0;
  726. }
  727. sde_crtc = to_sde_crtc(crtc);
  728. crtc_state = to_sde_crtc_state(state);
  729. /* pingpong split: one ROI, one LM, two physical displays */
  730. if (crtc_state->is_ppsplit) {
  731. u32 lm_split_width = crtc_state->lm_bounds[0].w / 2;
  732. struct sde_rect *roi = &crtc_state->lm_roi[0];
  733. if (sde_kms_rect_is_null(roi))
  734. disp_bitmask = 0;
  735. else if ((u32)roi->x + (u32)roi->w <= lm_split_width)
  736. disp_bitmask = BIT(0); /* left only */
  737. else if (roi->x >= lm_split_width)
  738. disp_bitmask = BIT(1); /* right only */
  739. else
  740. disp_bitmask = BIT(0) | BIT(1); /* left and right */
  741. } else {
  742. for (i = 0; i < sde_crtc->num_mixers; i++) {
  743. if (!sde_kms_rect_is_null(&crtc_state->lm_roi[i]))
  744. disp_bitmask |= BIT(i);
  745. }
  746. }
  747. SDE_DEBUG("affected displays 0x%x\n", disp_bitmask);
  748. return disp_bitmask;
  749. }
  750. static int _sde_crtc_check_rois_centered_and_symmetric(struct drm_crtc *crtc,
  751. struct drm_crtc_state *state)
  752. {
  753. struct sde_crtc *sde_crtc;
  754. struct sde_crtc_state *crtc_state;
  755. const struct sde_rect *roi[CRTC_DUAL_MIXERS];
  756. if (!crtc || !state)
  757. return -EINVAL;
  758. sde_crtc = to_sde_crtc(crtc);
  759. crtc_state = to_sde_crtc_state(state);
  760. if (sde_crtc->num_mixers > CRTC_DUAL_MIXERS) {
  761. SDE_ERROR("%s: unsupported number of mixers: %d\n",
  762. sde_crtc->name, sde_crtc->num_mixers);
  763. return -EINVAL;
  764. }
  765. /*
  766. * If using pingpong split: one ROI, one LM, two physical displays
  767. * then the ROI must be centered on the panel split boundary and
  768. * be of equal width across the split.
  769. */
  770. if (crtc_state->is_ppsplit) {
  771. u16 panel_split_width;
  772. u32 display_mask;
  773. roi[0] = &crtc_state->lm_roi[0];
  774. if (sde_kms_rect_is_null(roi[0]))
  775. return 0;
  776. display_mask = _sde_crtc_get_displays_affected(crtc, state);
  777. if (display_mask != (BIT(0) | BIT(1)))
  778. return 0;
  779. panel_split_width = crtc_state->lm_bounds[0].w / 2;
  780. if (roi[0]->x + roi[0]->w / 2 != panel_split_width) {
  781. SDE_ERROR("%s: roi x %d w %d split %d\n",
  782. sde_crtc->name, roi[0]->x, roi[0]->w,
  783. panel_split_width);
  784. return -EINVAL;
  785. }
  786. return 0;
  787. }
  788. /*
  789. * On certain HW, if using 2 LM, ROIs must be split evenly between the
  790. * LMs and be of equal width.
  791. */
  792. if (sde_crtc->num_mixers < 2)
  793. return 0;
  794. roi[0] = &crtc_state->lm_roi[0];
  795. roi[1] = &crtc_state->lm_roi[1];
  796. /* if one of the roi is null it's a left/right-only update */
  797. if (sde_kms_rect_is_null(roi[0]) || sde_kms_rect_is_null(roi[1]))
  798. return 0;
  799. /* check lm rois are equal width & first roi ends at 2nd roi */
  800. if (roi[0]->x + roi[0]->w != roi[1]->x || roi[0]->w != roi[1]->w) {
  801. SDE_ERROR(
  802. "%s: rois not centered and symmetric: roi0 x %d w %d roi1 x %d w %d\n",
  803. sde_crtc->name, roi[0]->x, roi[0]->w,
  804. roi[1]->x, roi[1]->w);
  805. return -EINVAL;
  806. }
  807. return 0;
  808. }
  809. static int _sde_crtc_check_planes_within_crtc_roi(struct drm_crtc *crtc,
  810. struct drm_crtc_state *state)
  811. {
  812. struct sde_crtc *sde_crtc;
  813. struct sde_crtc_state *crtc_state;
  814. const struct sde_rect *crtc_roi;
  815. const struct drm_plane_state *pstate;
  816. struct drm_plane *plane;
  817. if (!crtc || !state)
  818. return -EINVAL;
  819. /*
  820. * Reject commit if a Plane CRTC destination coordinates fall outside
  821. * the partial CRTC ROI. LM output is determined via connector ROIs,
  822. * if they are specified, not Plane CRTC ROIs.
  823. */
  824. sde_crtc = to_sde_crtc(crtc);
  825. crtc_state = to_sde_crtc_state(state);
  826. crtc_roi = &crtc_state->crtc_roi;
  827. if (sde_kms_rect_is_null(crtc_roi))
  828. return 0;
  829. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  830. struct sde_rect plane_roi, intersection;
  831. if (IS_ERR_OR_NULL(pstate)) {
  832. int rc = PTR_ERR(pstate);
  833. SDE_ERROR("%s: failed to get plane%d state, %d\n",
  834. sde_crtc->name, plane->base.id, rc);
  835. return rc;
  836. }
  837. plane_roi.x = pstate->crtc_x;
  838. plane_roi.y = pstate->crtc_y;
  839. plane_roi.w = pstate->crtc_w;
  840. plane_roi.h = pstate->crtc_h;
  841. sde_kms_rect_intersect(crtc_roi, &plane_roi, &intersection);
  842. if (!sde_kms_rect_is_equal(&plane_roi, &intersection)) {
  843. SDE_ERROR(
  844. "%s: plane%d crtc roi (%d,%d,%d,%d) outside crtc roi (%d,%d,%d,%d)\n",
  845. sde_crtc->name, plane->base.id,
  846. plane_roi.x, plane_roi.y,
  847. plane_roi.w, plane_roi.h,
  848. crtc_roi->x, crtc_roi->y,
  849. crtc_roi->w, crtc_roi->h);
  850. return -E2BIG;
  851. }
  852. }
  853. return 0;
  854. }
  855. static int _sde_crtc_check_rois(struct drm_crtc *crtc,
  856. struct drm_crtc_state *state)
  857. {
  858. struct sde_crtc *sde_crtc;
  859. struct sde_crtc_state *sde_crtc_state;
  860. struct msm_mode_info mode_info;
  861. int rc, lm_idx, i;
  862. if (!crtc || !state)
  863. return -EINVAL;
  864. memset(&mode_info, 0, sizeof(mode_info));
  865. sde_crtc = to_sde_crtc(crtc);
  866. sde_crtc_state = to_sde_crtc_state(state);
  867. /*
  868. * check connector array cached at modeset time since incoming atomic
  869. * state may not include any connectors if they aren't modified
  870. */
  871. for (i = 0; i < sde_crtc_state->num_connectors; i++) {
  872. struct drm_connector *conn = sde_crtc_state->connectors[i];
  873. if (!conn || !conn->state)
  874. continue;
  875. rc = sde_connector_state_get_mode_info(conn->state, &mode_info);
  876. if (rc) {
  877. SDE_ERROR("failed to get mode info\n");
  878. return -EINVAL;
  879. }
  880. if (!mode_info.roi_caps.enabled)
  881. continue;
  882. if (sde_crtc_state->user_roi_list.num_rects >
  883. mode_info.roi_caps.num_roi) {
  884. SDE_ERROR("roi count is exceeding limit, %d > %d\n",
  885. sde_crtc_state->user_roi_list.num_rects,
  886. mode_info.roi_caps.num_roi);
  887. return -E2BIG;
  888. }
  889. rc = _sde_crtc_set_crtc_roi(crtc, state);
  890. if (rc)
  891. return rc;
  892. rc = _sde_crtc_check_autorefresh(crtc, state);
  893. if (rc)
  894. return rc;
  895. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) {
  896. rc = _sde_crtc_set_lm_roi(crtc, state, lm_idx);
  897. if (rc)
  898. return rc;
  899. }
  900. rc = _sde_crtc_check_rois_centered_and_symmetric(crtc, state);
  901. if (rc)
  902. return rc;
  903. rc = _sde_crtc_check_planes_within_crtc_roi(crtc, state);
  904. if (rc)
  905. return rc;
  906. }
  907. return 0;
  908. }
  909. static void _sde_crtc_program_lm_output_roi(struct drm_crtc *crtc)
  910. {
  911. struct sde_crtc *sde_crtc;
  912. struct sde_crtc_state *crtc_state;
  913. const struct sde_rect *lm_roi;
  914. struct sde_hw_mixer *hw_lm;
  915. int lm_idx, lm_horiz_position;
  916. if (!crtc)
  917. return;
  918. sde_crtc = to_sde_crtc(crtc);
  919. crtc_state = to_sde_crtc_state(crtc->state);
  920. lm_horiz_position = 0;
  921. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) {
  922. struct sde_hw_mixer_cfg cfg;
  923. lm_roi = &crtc_state->lm_roi[lm_idx];
  924. hw_lm = sde_crtc->mixers[lm_idx].hw_lm;
  925. SDE_EVT32(DRMID(crtc_state->base.crtc), lm_idx,
  926. lm_roi->x, lm_roi->y, lm_roi->w, lm_roi->h);
  927. if (sde_kms_rect_is_null(lm_roi))
  928. continue;
  929. hw_lm->cfg.out_width = lm_roi->w;
  930. hw_lm->cfg.out_height = lm_roi->h;
  931. hw_lm->cfg.right_mixer = lm_horiz_position;
  932. cfg.out_width = lm_roi->w;
  933. cfg.out_height = lm_roi->h;
  934. cfg.right_mixer = lm_horiz_position++;
  935. cfg.flags = 0;
  936. hw_lm->ops.setup_mixer_out(hw_lm, &cfg);
  937. }
  938. }
  939. struct plane_state {
  940. struct sde_plane_state *sde_pstate;
  941. const struct drm_plane_state *drm_pstate;
  942. int stage;
  943. u32 pipe_id;
  944. };
  945. static int pstate_cmp(const void *a, const void *b)
  946. {
  947. struct plane_state *pa = (struct plane_state *)a;
  948. struct plane_state *pb = (struct plane_state *)b;
  949. int rc = 0;
  950. int pa_zpos, pb_zpos;
  951. pa_zpos = sde_plane_get_property(pa->sde_pstate, PLANE_PROP_ZPOS);
  952. pb_zpos = sde_plane_get_property(pb->sde_pstate, PLANE_PROP_ZPOS);
  953. if (pa_zpos != pb_zpos)
  954. rc = pa_zpos - pb_zpos;
  955. else
  956. rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x;
  957. return rc;
  958. }
  959. /*
  960. * validate and set source split:
  961. * use pstates sorted by stage to check planes on same stage
  962. * we assume that all pipes are in source split so its valid to compare
  963. * without taking into account left/right mixer placement
  964. */
  965. static int _sde_crtc_validate_src_split_order(struct drm_crtc *crtc,
  966. struct plane_state *pstates, int cnt)
  967. {
  968. struct plane_state *prv_pstate, *cur_pstate;
  969. struct sde_rect left_rect, right_rect;
  970. struct sde_kms *sde_kms;
  971. int32_t left_pid, right_pid;
  972. int32_t stage;
  973. int i, rc = 0;
  974. sde_kms = _sde_crtc_get_kms(crtc);
  975. if (!sde_kms || !sde_kms->catalog) {
  976. SDE_ERROR("invalid parameters\n");
  977. return -EINVAL;
  978. }
  979. for (i = 1; i < cnt; i++) {
  980. prv_pstate = &pstates[i - 1];
  981. cur_pstate = &pstates[i];
  982. if (prv_pstate->stage != cur_pstate->stage)
  983. continue;
  984. stage = cur_pstate->stage;
  985. left_pid = prv_pstate->sde_pstate->base.plane->base.id;
  986. POPULATE_RECT(&left_rect, prv_pstate->drm_pstate->crtc_x,
  987. prv_pstate->drm_pstate->crtc_y,
  988. prv_pstate->drm_pstate->crtc_w,
  989. prv_pstate->drm_pstate->crtc_h, false);
  990. right_pid = cur_pstate->sde_pstate->base.plane->base.id;
  991. POPULATE_RECT(&right_rect, cur_pstate->drm_pstate->crtc_x,
  992. cur_pstate->drm_pstate->crtc_y,
  993. cur_pstate->drm_pstate->crtc_w,
  994. cur_pstate->drm_pstate->crtc_h, false);
  995. if (right_rect.x < left_rect.x) {
  996. swap(left_pid, right_pid);
  997. swap(left_rect, right_rect);
  998. swap(prv_pstate, cur_pstate);
  999. }
  1000. /*
  1001. * - planes are enumerated in pipe-priority order such that
  1002. * planes with lower drm_id must be left-most in a shared
  1003. * blend-stage when using source split.
  1004. * - planes in source split must be contiguous in width
  1005. * - planes in source split must have same dest yoff and height
  1006. */
  1007. if ((right_pid < left_pid) &&
  1008. !sde_kms->catalog->pipe_order_type) {
  1009. SDE_ERROR(
  1010. "invalid src split cfg, stage:%d left:%d right:%d\n",
  1011. stage, left_pid, right_pid);
  1012. return -EINVAL;
  1013. } else if (right_rect.x != (left_rect.x + left_rect.w)) {
  1014. SDE_ERROR(
  1015. "invalid coordinates, stage:%d l:%d-%d r:%d-%d\n",
  1016. stage, left_rect.x, left_rect.w,
  1017. right_rect.x, right_rect.w);
  1018. return -EINVAL;
  1019. } else if ((left_rect.y != right_rect.y) ||
  1020. (left_rect.h != right_rect.h)) {
  1021. SDE_ERROR(
  1022. "stage:%d invalid yoff/ht: l_yxh:%dx%d r_yxh:%dx%d\n",
  1023. stage, left_rect.y, left_rect.h,
  1024. right_rect.y, right_rect.h);
  1025. return -EINVAL;
  1026. }
  1027. }
  1028. return rc;
  1029. }
  1030. static void _sde_crtc_set_src_split_order(struct drm_crtc *crtc,
  1031. struct plane_state *pstates, int cnt)
  1032. {
  1033. struct plane_state *prv_pstate, *cur_pstate, *nxt_pstate;
  1034. struct sde_kms *sde_kms;
  1035. struct sde_rect left_rect, right_rect;
  1036. int32_t left_pid, right_pid;
  1037. int32_t stage;
  1038. int i;
  1039. sde_kms = _sde_crtc_get_kms(crtc);
  1040. if (!sde_kms || !sde_kms->catalog) {
  1041. SDE_ERROR("invalid parameters\n");
  1042. return;
  1043. }
  1044. if (!sde_kms->catalog->pipe_order_type)
  1045. return;
  1046. for (i = 0; i < cnt; i++) {
  1047. prv_pstate = (i > 0) ? &pstates[i - 1] : NULL;
  1048. cur_pstate = &pstates[i];
  1049. nxt_pstate = ((i + 1) < cnt) ? &pstates[i + 1] : NULL;
  1050. if ((!prv_pstate) || (prv_pstate->stage != cur_pstate->stage)) {
  1051. /*
  1052. * reset if prv or nxt pipes are not in the same stage
  1053. * as the cur pipe
  1054. */
  1055. if ((!nxt_pstate)
  1056. || (nxt_pstate->stage != cur_pstate->stage))
  1057. cur_pstate->sde_pstate->pipe_order_flags = 0;
  1058. continue;
  1059. }
  1060. stage = cur_pstate->stage;
  1061. left_pid = prv_pstate->sde_pstate->base.plane->base.id;
  1062. POPULATE_RECT(&left_rect, prv_pstate->drm_pstate->crtc_x,
  1063. prv_pstate->drm_pstate->crtc_y,
  1064. prv_pstate->drm_pstate->crtc_w,
  1065. prv_pstate->drm_pstate->crtc_h, false);
  1066. right_pid = cur_pstate->sde_pstate->base.plane->base.id;
  1067. POPULATE_RECT(&right_rect, cur_pstate->drm_pstate->crtc_x,
  1068. cur_pstate->drm_pstate->crtc_y,
  1069. cur_pstate->drm_pstate->crtc_w,
  1070. cur_pstate->drm_pstate->crtc_h, false);
  1071. if (right_rect.x < left_rect.x) {
  1072. swap(left_pid, right_pid);
  1073. swap(left_rect, right_rect);
  1074. swap(prv_pstate, cur_pstate);
  1075. }
  1076. cur_pstate->sde_pstate->pipe_order_flags = SDE_SSPP_RIGHT;
  1077. prv_pstate->sde_pstate->pipe_order_flags = 0;
  1078. }
  1079. for (i = 0; i < cnt; i++) {
  1080. cur_pstate = &pstates[i];
  1081. sde_plane_setup_src_split_order(
  1082. cur_pstate->drm_pstate->plane,
  1083. cur_pstate->sde_pstate->multirect_index,
  1084. cur_pstate->sde_pstate->pipe_order_flags);
  1085. }
  1086. }
  1087. static void _sde_crtc_blend_setup_mixer(struct drm_crtc *crtc,
  1088. struct drm_crtc_state *old_state, struct sde_crtc *sde_crtc,
  1089. struct sde_crtc_mixer *mixer)
  1090. {
  1091. struct drm_plane *plane;
  1092. struct drm_framebuffer *fb;
  1093. struct drm_plane_state *state;
  1094. struct sde_crtc_state *cstate;
  1095. struct sde_plane_state *pstate = NULL;
  1096. struct plane_state *pstates = NULL;
  1097. struct sde_format *format;
  1098. struct sde_hw_ctl *ctl;
  1099. struct sde_hw_mixer *lm;
  1100. struct sde_hw_stage_cfg *stage_cfg;
  1101. struct sde_rect plane_crtc_roi;
  1102. uint32_t stage_idx, lm_idx;
  1103. int zpos_cnt[SDE_STAGE_MAX + 1] = { 0 };
  1104. int i, cnt = 0;
  1105. bool bg_alpha_enable = false;
  1106. if (!sde_crtc || !crtc->state || !mixer) {
  1107. SDE_ERROR("invalid sde_crtc or mixer\n");
  1108. return;
  1109. }
  1110. ctl = mixer->hw_ctl;
  1111. lm = mixer->hw_lm;
  1112. stage_cfg = &sde_crtc->stage_cfg;
  1113. cstate = to_sde_crtc_state(crtc->state);
  1114. pstates = kcalloc(SDE_PSTATES_MAX,
  1115. sizeof(struct plane_state), GFP_KERNEL);
  1116. if (!pstates)
  1117. return;
  1118. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1119. state = plane->state;
  1120. if (!state)
  1121. continue;
  1122. plane_crtc_roi.x = state->crtc_x;
  1123. plane_crtc_roi.y = state->crtc_y;
  1124. plane_crtc_roi.w = state->crtc_w;
  1125. plane_crtc_roi.h = state->crtc_h;
  1126. pstate = to_sde_plane_state(state);
  1127. fb = state->fb;
  1128. sde_plane_ctl_flush(plane, ctl, true);
  1129. SDE_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n",
  1130. crtc->base.id,
  1131. pstate->stage,
  1132. plane->base.id,
  1133. sde_plane_pipe(plane) - SSPP_VIG0,
  1134. state->fb ? state->fb->base.id : -1);
  1135. format = to_sde_format(msm_framebuffer_format(pstate->base.fb));
  1136. if (!format) {
  1137. SDE_ERROR("invalid format\n");
  1138. goto end;
  1139. }
  1140. if (pstate->stage == SDE_STAGE_BASE && format->alpha_enable)
  1141. bg_alpha_enable = true;
  1142. SDE_EVT32(DRMID(crtc), DRMID(plane),
  1143. state->fb ? state->fb->base.id : -1,
  1144. state->src_x >> 16, state->src_y >> 16,
  1145. state->src_w >> 16, state->src_h >> 16,
  1146. state->crtc_x, state->crtc_y,
  1147. state->crtc_w, state->crtc_h,
  1148. pstate->rotation);
  1149. stage_idx = zpos_cnt[pstate->stage]++;
  1150. stage_cfg->stage[pstate->stage][stage_idx] =
  1151. sde_plane_pipe(plane);
  1152. stage_cfg->multirect_index[pstate->stage][stage_idx] =
  1153. pstate->multirect_index;
  1154. SDE_EVT32(DRMID(crtc), DRMID(plane), stage_idx,
  1155. sde_plane_pipe(plane) - SSPP_VIG0, pstate->stage,
  1156. pstate->multirect_index, pstate->multirect_mode,
  1157. format->base.pixel_format, fb ? fb->modifier : 0);
  1158. /* blend config update */
  1159. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) {
  1160. _sde_crtc_setup_blend_cfg(mixer + lm_idx, pstate,
  1161. format);
  1162. if (bg_alpha_enable && !format->alpha_enable)
  1163. mixer[lm_idx].mixer_op_mode = 0;
  1164. else
  1165. mixer[lm_idx].mixer_op_mode |=
  1166. 1 << pstate->stage;
  1167. }
  1168. if (cnt >= SDE_PSTATES_MAX)
  1169. continue;
  1170. pstates[cnt].sde_pstate = pstate;
  1171. pstates[cnt].drm_pstate = state;
  1172. pstates[cnt].stage = sde_plane_get_property(
  1173. pstates[cnt].sde_pstate, PLANE_PROP_ZPOS);
  1174. pstates[cnt].pipe_id = sde_plane_pipe(plane);
  1175. cnt++;
  1176. }
  1177. sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
  1178. _sde_crtc_set_src_split_order(crtc, pstates, cnt);
  1179. if (lm && lm->ops.setup_dim_layer) {
  1180. cstate = to_sde_crtc_state(crtc->state);
  1181. for (i = 0; i < cstate->num_dim_layers; i++)
  1182. _sde_crtc_setup_dim_layer_cfg(crtc, sde_crtc,
  1183. mixer, &cstate->dim_layer[i]);
  1184. }
  1185. _sde_crtc_program_lm_output_roi(crtc);
  1186. end:
  1187. kfree(pstates);
  1188. }
  1189. static void _sde_crtc_swap_mixers_for_right_partial_update(
  1190. struct drm_crtc *crtc)
  1191. {
  1192. struct sde_crtc *sde_crtc;
  1193. struct sde_crtc_state *cstate;
  1194. struct drm_encoder *drm_enc;
  1195. bool is_right_only;
  1196. bool encoder_in_dsc_merge = false;
  1197. if (!crtc || !crtc->state)
  1198. return;
  1199. sde_crtc = to_sde_crtc(crtc);
  1200. cstate = to_sde_crtc_state(crtc->state);
  1201. if (sde_crtc->num_mixers != CRTC_DUAL_MIXERS)
  1202. return;
  1203. drm_for_each_encoder_mask(drm_enc, crtc->dev,
  1204. crtc->state->encoder_mask) {
  1205. if (sde_encoder_is_dsc_merge(drm_enc)) {
  1206. encoder_in_dsc_merge = true;
  1207. break;
  1208. }
  1209. }
  1210. /**
  1211. * For right-only partial update with DSC merge, we swap LM0 & LM1.
  1212. * This is due to two reasons:
  1213. * - On 8996, there is a DSC HW requirement that in DSC Merge Mode,
  1214. * the left DSC must be used, right DSC cannot be used alone.
  1215. * For right-only partial update, this means swap layer mixers to map
  1216. * Left LM to Right INTF. On later HW this was relaxed.
  1217. * - In DSC Merge mode, the physical encoder has already registered
  1218. * PP0 as the master, to switch to right-only we would have to
  1219. * reprogram to be driven by PP1 instead.
  1220. * To support both cases, we prefer to support the mixer swap solution.
  1221. */
  1222. if (!encoder_in_dsc_merge)
  1223. return;
  1224. is_right_only = sde_kms_rect_is_null(&cstate->lm_roi[0]) &&
  1225. !sde_kms_rect_is_null(&cstate->lm_roi[1]);
  1226. if (is_right_only && !sde_crtc->mixers_swapped) {
  1227. /* right-only update swap mixers */
  1228. swap(sde_crtc->mixers[0], sde_crtc->mixers[1]);
  1229. sde_crtc->mixers_swapped = true;
  1230. } else if (!is_right_only && sde_crtc->mixers_swapped) {
  1231. /* left-only or full update, swap back */
  1232. swap(sde_crtc->mixers[0], sde_crtc->mixers[1]);
  1233. sde_crtc->mixers_swapped = false;
  1234. }
  1235. SDE_DEBUG("%s: right_only %d swapped %d, mix0->lm%d, mix1->lm%d\n",
  1236. sde_crtc->name, is_right_only, sde_crtc->mixers_swapped,
  1237. sde_crtc->mixers[0].hw_lm->idx - LM_0,
  1238. sde_crtc->mixers[1].hw_lm->idx - LM_0);
  1239. SDE_EVT32(DRMID(crtc), is_right_only, sde_crtc->mixers_swapped,
  1240. sde_crtc->mixers[0].hw_lm->idx - LM_0,
  1241. sde_crtc->mixers[1].hw_lm->idx - LM_0);
  1242. }
  1243. /**
  1244. * _sde_crtc_blend_setup - configure crtc mixers
  1245. * @crtc: Pointer to drm crtc structure
  1246. * @old_state: Pointer to old crtc state
  1247. * @add_planes: Whether or not to add planes to mixers
  1248. */
  1249. static void _sde_crtc_blend_setup(struct drm_crtc *crtc,
  1250. struct drm_crtc_state *old_state, bool add_planes)
  1251. {
  1252. struct sde_crtc *sde_crtc;
  1253. struct sde_crtc_state *sde_crtc_state;
  1254. struct sde_crtc_mixer *mixer;
  1255. struct sde_hw_ctl *ctl;
  1256. struct sde_hw_mixer *lm;
  1257. struct sde_ctl_flush_cfg cfg = {0,};
  1258. int i;
  1259. if (!crtc)
  1260. return;
  1261. sde_crtc = to_sde_crtc(crtc);
  1262. sde_crtc_state = to_sde_crtc_state(crtc->state);
  1263. mixer = sde_crtc->mixers;
  1264. SDE_DEBUG("%s\n", sde_crtc->name);
  1265. if (sde_crtc->num_mixers > CRTC_DUAL_MIXERS) {
  1266. SDE_ERROR("invalid number mixers: %d\n", sde_crtc->num_mixers);
  1267. return;
  1268. }
  1269. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1270. if (!mixer[i].hw_lm || !mixer[i].hw_ctl) {
  1271. SDE_ERROR("invalid lm or ctl assigned to mixer\n");
  1272. return;
  1273. }
  1274. mixer[i].mixer_op_mode = 0;
  1275. if (mixer[i].hw_ctl->ops.clear_all_blendstages)
  1276. mixer[i].hw_ctl->ops.clear_all_blendstages(
  1277. mixer[i].hw_ctl);
  1278. /* clear dim_layer settings */
  1279. lm = mixer[i].hw_lm;
  1280. if (lm->ops.clear_dim_layer)
  1281. lm->ops.clear_dim_layer(lm);
  1282. }
  1283. _sde_crtc_swap_mixers_for_right_partial_update(crtc);
  1284. /* initialize stage cfg */
  1285. memset(&sde_crtc->stage_cfg, 0, sizeof(struct sde_hw_stage_cfg));
  1286. if (add_planes)
  1287. _sde_crtc_blend_setup_mixer(crtc, old_state, sde_crtc, mixer);
  1288. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1289. const struct sde_rect *lm_roi = &sde_crtc_state->lm_roi[i];
  1290. ctl = mixer[i].hw_ctl;
  1291. lm = mixer[i].hw_lm;
  1292. if (sde_kms_rect_is_null(lm_roi)) {
  1293. SDE_DEBUG(
  1294. "%s: lm%d leave ctl%d mask 0 since null roi\n",
  1295. sde_crtc->name, lm->idx - LM_0,
  1296. ctl->idx - CTL_0);
  1297. continue;
  1298. }
  1299. lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode);
  1300. /* stage config flush mask */
  1301. ctl->ops.update_bitmask_mixer(ctl, mixer[i].hw_lm->idx, 1);
  1302. ctl->ops.get_pending_flush(ctl, &cfg);
  1303. SDE_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n",
  1304. mixer[i].hw_lm->idx - LM_0,
  1305. mixer[i].mixer_op_mode,
  1306. ctl->idx - CTL_0,
  1307. cfg.pending_flush_mask);
  1308. ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
  1309. &sde_crtc->stage_cfg);
  1310. }
  1311. _sde_crtc_program_lm_output_roi(crtc);
  1312. }
  1313. int sde_crtc_find_plane_fb_modes(struct drm_crtc *crtc,
  1314. uint32_t *fb_ns, uint32_t *fb_sec, uint32_t *fb_sec_dir)
  1315. {
  1316. struct drm_plane *plane;
  1317. struct sde_plane_state *sde_pstate;
  1318. uint32_t mode = 0;
  1319. int rc;
  1320. if (!crtc) {
  1321. SDE_ERROR("invalid state\n");
  1322. return -EINVAL;
  1323. }
  1324. *fb_ns = 0;
  1325. *fb_sec = 0;
  1326. *fb_sec_dir = 0;
  1327. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1328. if (IS_ERR_OR_NULL(plane) || IS_ERR_OR_NULL(plane->state)) {
  1329. rc = PTR_ERR(plane);
  1330. SDE_ERROR("crtc%d failed to get plane%d state%d\n",
  1331. DRMID(crtc), DRMID(plane), rc);
  1332. return rc;
  1333. }
  1334. sde_pstate = to_sde_plane_state(plane->state);
  1335. mode = sde_plane_get_property(sde_pstate,
  1336. PLANE_PROP_FB_TRANSLATION_MODE);
  1337. switch (mode) {
  1338. case SDE_DRM_FB_NON_SEC:
  1339. (*fb_ns)++;
  1340. break;
  1341. case SDE_DRM_FB_SEC:
  1342. (*fb_sec)++;
  1343. break;
  1344. case SDE_DRM_FB_SEC_DIR_TRANS:
  1345. (*fb_sec_dir)++;
  1346. break;
  1347. default:
  1348. SDE_ERROR("Error: Plane[%d], fb_trans_mode:%d",
  1349. DRMID(plane), mode);
  1350. return -EINVAL;
  1351. }
  1352. }
  1353. return 0;
  1354. }
  1355. int sde_crtc_state_find_plane_fb_modes(struct drm_crtc_state *state,
  1356. uint32_t *fb_ns, uint32_t *fb_sec, uint32_t *fb_sec_dir)
  1357. {
  1358. struct drm_plane *plane;
  1359. const struct drm_plane_state *pstate;
  1360. struct sde_plane_state *sde_pstate;
  1361. uint32_t mode = 0;
  1362. int rc;
  1363. if (!state) {
  1364. SDE_ERROR("invalid state\n");
  1365. return -EINVAL;
  1366. }
  1367. *fb_ns = 0;
  1368. *fb_sec = 0;
  1369. *fb_sec_dir = 0;
  1370. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  1371. if (IS_ERR_OR_NULL(pstate)) {
  1372. rc = PTR_ERR(pstate);
  1373. SDE_ERROR("crtc%d failed to get plane%d state%d\n",
  1374. DRMID(state->crtc), DRMID(plane), rc);
  1375. return rc;
  1376. }
  1377. sde_pstate = to_sde_plane_state(pstate);
  1378. mode = sde_plane_get_property(sde_pstate,
  1379. PLANE_PROP_FB_TRANSLATION_MODE);
  1380. switch (mode) {
  1381. case SDE_DRM_FB_NON_SEC:
  1382. (*fb_ns)++;
  1383. break;
  1384. case SDE_DRM_FB_SEC:
  1385. (*fb_sec)++;
  1386. break;
  1387. case SDE_DRM_FB_SEC_DIR_TRANS:
  1388. (*fb_sec_dir)++;
  1389. break;
  1390. default:
  1391. SDE_ERROR("Error: Plane[%d], fb_trans_mode:%d",
  1392. DRMID(plane), mode);
  1393. return -EINVAL;
  1394. }
  1395. }
  1396. return 0;
  1397. }
  1398. static void _sde_drm_fb_sec_dir_trans(
  1399. struct sde_kms_smmu_state_data *smmu_state, uint32_t secure_level,
  1400. struct sde_mdss_cfg *catalog, bool old_valid_fb, int *ops)
  1401. {
  1402. /* secure display usecase */
  1403. if ((smmu_state->state == ATTACHED)
  1404. && (secure_level == SDE_DRM_SEC_ONLY)) {
  1405. smmu_state->state = catalog->sui_ns_allowed ?
  1406. DETACH_SEC_REQ : DETACH_ALL_REQ;
  1407. smmu_state->secure_level = secure_level;
  1408. smmu_state->transition_type = PRE_COMMIT;
  1409. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1410. if (old_valid_fb)
  1411. *ops |= (SDE_KMS_OPS_WAIT_FOR_TX_DONE |
  1412. SDE_KMS_OPS_CLEANUP_PLANE_FB);
  1413. if (catalog->sui_misr_supported)
  1414. smmu_state->sui_misr_state =
  1415. SUI_MISR_ENABLE_REQ;
  1416. /* secure camera usecase */
  1417. } else if (smmu_state->state == ATTACHED) {
  1418. smmu_state->state = DETACH_SEC_REQ;
  1419. smmu_state->secure_level = secure_level;
  1420. smmu_state->transition_type = PRE_COMMIT;
  1421. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1422. }
  1423. }
  1424. static void _sde_drm_fb_transactions(
  1425. struct sde_kms_smmu_state_data *smmu_state,
  1426. struct sde_mdss_cfg *catalog, bool old_valid_fb, bool post_commit,
  1427. int *ops)
  1428. {
  1429. if (((smmu_state->state == DETACHED)
  1430. || (smmu_state->state == DETACH_ALL_REQ))
  1431. || ((smmu_state->secure_level == SDE_DRM_SEC_ONLY)
  1432. && ((smmu_state->state == DETACHED_SEC)
  1433. || (smmu_state->state == DETACH_SEC_REQ)))) {
  1434. smmu_state->state = catalog->sui_ns_allowed ?
  1435. ATTACH_SEC_REQ : ATTACH_ALL_REQ;
  1436. smmu_state->transition_type = post_commit ?
  1437. POST_COMMIT : PRE_COMMIT;
  1438. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1439. if (old_valid_fb)
  1440. *ops |= SDE_KMS_OPS_WAIT_FOR_TX_DONE;
  1441. if (catalog->sui_misr_supported)
  1442. smmu_state->sui_misr_state =
  1443. SUI_MISR_DISABLE_REQ;
  1444. } else if ((smmu_state->state == DETACHED_SEC)
  1445. || (smmu_state->state == DETACH_SEC_REQ)) {
  1446. smmu_state->state = ATTACH_SEC_REQ;
  1447. smmu_state->transition_type = post_commit ?
  1448. POST_COMMIT : PRE_COMMIT;
  1449. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1450. if (old_valid_fb)
  1451. *ops |= SDE_KMS_OPS_WAIT_FOR_TX_DONE;
  1452. }
  1453. }
  1454. /**
  1455. * sde_crtc_get_secure_transition_ops - determines the operations that
  1456. * need to be performed before transitioning to secure state
  1457. * This function should be called after swapping the new state
  1458. * @crtc: Pointer to drm crtc structure
  1459. * Returns the bitmask of operations need to be performed, -Error in
  1460. * case of error cases
  1461. */
  1462. int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc,
  1463. struct drm_crtc_state *old_crtc_state,
  1464. bool old_valid_fb)
  1465. {
  1466. struct drm_plane *plane;
  1467. struct drm_encoder *encoder;
  1468. struct sde_crtc *sde_crtc;
  1469. struct sde_kms *sde_kms;
  1470. struct sde_mdss_cfg *catalog;
  1471. struct sde_kms_smmu_state_data *smmu_state;
  1472. uint32_t translation_mode = 0, secure_level;
  1473. int ops = 0;
  1474. bool post_commit = false;
  1475. if (!crtc || !crtc->state) {
  1476. SDE_ERROR("invalid crtc\n");
  1477. return -EINVAL;
  1478. }
  1479. sde_kms = _sde_crtc_get_kms(crtc);
  1480. if (!sde_kms)
  1481. return -EINVAL;
  1482. smmu_state = &sde_kms->smmu_state;
  1483. smmu_state->prev_state = smmu_state->state;
  1484. smmu_state->prev_secure_level = smmu_state->secure_level;
  1485. sde_crtc = to_sde_crtc(crtc);
  1486. secure_level = sde_crtc_get_secure_level(crtc, crtc->state);
  1487. catalog = sde_kms->catalog;
  1488. /*
  1489. * SMMU operations need to be delayed in case of video mode panels
  1490. * when switching back to non_secure mode
  1491. */
  1492. drm_for_each_encoder_mask(encoder, crtc->dev,
  1493. crtc->state->encoder_mask) {
  1494. if (sde_encoder_is_dsi_display(encoder))
  1495. post_commit |= sde_encoder_check_curr_mode(encoder,
  1496. MSM_DISPLAY_VIDEO_MODE);
  1497. }
  1498. SDE_DEBUG("crtc%d: secure_level %d old_valid_fb %d post_commit %d\n",
  1499. DRMID(crtc), secure_level, old_valid_fb, post_commit);
  1500. SDE_EVT32_VERBOSE(DRMID(crtc), secure_level, smmu_state->state,
  1501. old_valid_fb, post_commit, SDE_EVTLOG_FUNC_ENTRY);
  1502. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1503. if (!plane->state)
  1504. continue;
  1505. translation_mode = sde_plane_get_property(
  1506. to_sde_plane_state(plane->state),
  1507. PLANE_PROP_FB_TRANSLATION_MODE);
  1508. if (translation_mode > SDE_DRM_FB_SEC_DIR_TRANS) {
  1509. SDE_ERROR("crtc%d: invalid translation_mode %d\n",
  1510. DRMID(crtc), translation_mode);
  1511. return -EINVAL;
  1512. }
  1513. /* we can break if we find sec_dir plane */
  1514. if (translation_mode == SDE_DRM_FB_SEC_DIR_TRANS)
  1515. break;
  1516. }
  1517. mutex_lock(&sde_kms->secure_transition_lock);
  1518. switch (translation_mode) {
  1519. case SDE_DRM_FB_SEC_DIR_TRANS:
  1520. _sde_drm_fb_sec_dir_trans(smmu_state, secure_level,
  1521. catalog, old_valid_fb, &ops);
  1522. break;
  1523. case SDE_DRM_FB_SEC:
  1524. case SDE_DRM_FB_NON_SEC:
  1525. _sde_drm_fb_transactions(smmu_state, catalog,
  1526. old_valid_fb, post_commit, &ops);
  1527. break;
  1528. default:
  1529. SDE_ERROR("crtc%d: invalid plane fb_mode %d\n",
  1530. DRMID(crtc), translation_mode);
  1531. ops = -EINVAL;
  1532. }
  1533. /* log only during actual transition times */
  1534. if (ops) {
  1535. SDE_DEBUG("crtc%d: state%d sec%d sec_lvl%d type%d ops%x\n",
  1536. DRMID(crtc), smmu_state->state,
  1537. secure_level, smmu_state->secure_level,
  1538. smmu_state->transition_type, ops);
  1539. SDE_EVT32(DRMID(crtc), secure_level, translation_mode,
  1540. smmu_state->state, smmu_state->transition_type,
  1541. smmu_state->secure_level, old_valid_fb,
  1542. post_commit, ops, SDE_EVTLOG_FUNC_EXIT);
  1543. }
  1544. mutex_unlock(&sde_kms->secure_transition_lock);
  1545. return ops;
  1546. }
  1547. /**
  1548. * _sde_crtc_setup_scaler3_lut - Set up scaler lut
  1549. * LUTs are configured only once during boot
  1550. * @sde_crtc: Pointer to sde crtc
  1551. * @cstate: Pointer to sde crtc state
  1552. */
  1553. static int _sde_crtc_set_dest_scaler_lut(struct sde_crtc *sde_crtc,
  1554. struct sde_crtc_state *cstate, uint32_t lut_idx)
  1555. {
  1556. struct sde_hw_scaler3_lut_cfg *cfg;
  1557. struct sde_kms *sde_kms;
  1558. u32 *lut_data = NULL;
  1559. size_t len = 0;
  1560. int ret = 0;
  1561. if (!sde_crtc || !cstate) {
  1562. SDE_ERROR("invalid args\n");
  1563. return -EINVAL;
  1564. }
  1565. sde_kms = _sde_crtc_get_kms(&sde_crtc->base);
  1566. if (!sde_kms)
  1567. return -EINVAL;
  1568. if (is_qseed3_rev_qseed3lite(sde_kms->catalog))
  1569. return 0;
  1570. lut_data = msm_property_get_blob(&sde_crtc->property_info,
  1571. &cstate->property_state, &len, lut_idx);
  1572. if (!lut_data || !len) {
  1573. SDE_DEBUG("%s: lut(%d): cleared: %pK, %zu\n", sde_crtc->name,
  1574. lut_idx, lut_data, len);
  1575. lut_data = NULL;
  1576. len = 0;
  1577. }
  1578. cfg = &cstate->scl3_lut_cfg;
  1579. switch (lut_idx) {
  1580. case CRTC_PROP_DEST_SCALER_LUT_ED:
  1581. cfg->dir_lut = lut_data;
  1582. cfg->dir_len = len;
  1583. break;
  1584. case CRTC_PROP_DEST_SCALER_LUT_CIR:
  1585. cfg->cir_lut = lut_data;
  1586. cfg->cir_len = len;
  1587. break;
  1588. case CRTC_PROP_DEST_SCALER_LUT_SEP:
  1589. cfg->sep_lut = lut_data;
  1590. cfg->sep_len = len;
  1591. break;
  1592. default:
  1593. ret = -EINVAL;
  1594. SDE_ERROR("%s:invalid LUT idx(%d)\n", sde_crtc->name, lut_idx);
  1595. SDE_EVT32(DRMID(&sde_crtc->base), lut_idx, SDE_EVTLOG_ERROR);
  1596. break;
  1597. }
  1598. cfg->is_configured = cfg->dir_lut && cfg->cir_lut && cfg->sep_lut;
  1599. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), ret, lut_idx, len,
  1600. cfg->is_configured);
  1601. return ret;
  1602. }
  1603. void sde_crtc_timeline_status(struct drm_crtc *crtc)
  1604. {
  1605. struct sde_crtc *sde_crtc;
  1606. if (!crtc) {
  1607. SDE_ERROR("invalid crtc\n");
  1608. return;
  1609. }
  1610. sde_crtc = to_sde_crtc(crtc);
  1611. sde_fence_timeline_status(sde_crtc->output_fence, &crtc->base);
  1612. }
  1613. static int _sde_validate_hw_resources(struct sde_crtc *sde_crtc)
  1614. {
  1615. int i;
  1616. /**
  1617. * Check if sufficient hw resources are
  1618. * available as per target caps & topology
  1619. */
  1620. if (!sde_crtc) {
  1621. SDE_ERROR("invalid argument\n");
  1622. return -EINVAL;
  1623. }
  1624. if (!sde_crtc->num_mixers ||
  1625. sde_crtc->num_mixers > CRTC_DUAL_MIXERS) {
  1626. SDE_ERROR("%s: invalid number mixers: %d\n",
  1627. sde_crtc->name, sde_crtc->num_mixers);
  1628. SDE_EVT32(DRMID(&sde_crtc->base), sde_crtc->num_mixers,
  1629. SDE_EVTLOG_ERROR);
  1630. return -EINVAL;
  1631. }
  1632. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1633. if (!sde_crtc->mixers[i].hw_lm || !sde_crtc->mixers[i].hw_ctl
  1634. || !sde_crtc->mixers[i].hw_ds) {
  1635. SDE_ERROR("%s:insufficient resources for mixer(%d)\n",
  1636. sde_crtc->name, i);
  1637. SDE_EVT32(DRMID(&sde_crtc->base), sde_crtc->num_mixers,
  1638. i, sde_crtc->mixers[i].hw_lm,
  1639. sde_crtc->mixers[i].hw_ctl,
  1640. sde_crtc->mixers[i].hw_ds, SDE_EVTLOG_ERROR);
  1641. return -EINVAL;
  1642. }
  1643. }
  1644. return 0;
  1645. }
  1646. /**
  1647. * _sde_crtc_dest_scaler_setup - Set up dest scaler block
  1648. * @crtc: Pointer to drm crtc
  1649. */
  1650. static void _sde_crtc_dest_scaler_setup(struct drm_crtc *crtc)
  1651. {
  1652. struct sde_crtc *sde_crtc;
  1653. struct sde_crtc_state *cstate;
  1654. struct sde_hw_mixer *hw_lm;
  1655. struct sde_hw_ctl *hw_ctl;
  1656. struct sde_hw_ds *hw_ds;
  1657. struct sde_hw_ds_cfg *cfg;
  1658. struct sde_kms *kms;
  1659. u32 op_mode = 0;
  1660. u32 lm_idx = 0, num_mixers = 0;
  1661. int i, count = 0;
  1662. bool ds_dirty = false;
  1663. if (!crtc)
  1664. return;
  1665. sde_crtc = to_sde_crtc(crtc);
  1666. cstate = to_sde_crtc_state(crtc->state);
  1667. kms = _sde_crtc_get_kms(crtc);
  1668. num_mixers = sde_crtc->num_mixers;
  1669. count = cstate->num_ds;
  1670. SDE_DEBUG("crtc%d\n", crtc->base.id);
  1671. SDE_EVT32(DRMID(crtc), num_mixers, count, cstate->ds_dirty,
  1672. sde_crtc->ds_reconfig, cstate->num_ds_enabled);
  1673. /**
  1674. * destination scaler configuration will be done either
  1675. * or on set property or on power collapse (idle/suspend)
  1676. */
  1677. ds_dirty = (cstate->ds_dirty || sde_crtc->ds_reconfig);
  1678. if (sde_crtc->ds_reconfig) {
  1679. SDE_DEBUG("reconfigure dest scaler block\n");
  1680. sde_crtc->ds_reconfig = false;
  1681. }
  1682. if (!ds_dirty) {
  1683. SDE_DEBUG("no change in settings, skip commit\n");
  1684. } else if (!kms || !kms->catalog) {
  1685. SDE_ERROR("crtc%d:invalid parameters\n", crtc->base.id);
  1686. } else if (!kms->catalog->mdp[0].has_dest_scaler) {
  1687. SDE_DEBUG("dest scaler feature not supported\n");
  1688. } else if (_sde_validate_hw_resources(sde_crtc)) {
  1689. //do nothing
  1690. } else if ((!cstate->scl3_lut_cfg.is_configured) &&
  1691. (!is_qseed3_rev_qseed3lite(kms->catalog))) {
  1692. SDE_ERROR("crtc%d:no LUT data available\n", crtc->base.id);
  1693. } else {
  1694. for (i = 0; i < count; i++) {
  1695. cfg = &cstate->ds_cfg[i];
  1696. if (!cfg->flags)
  1697. continue;
  1698. lm_idx = cfg->idx;
  1699. hw_lm = sde_crtc->mixers[lm_idx].hw_lm;
  1700. hw_ctl = sde_crtc->mixers[lm_idx].hw_ctl;
  1701. hw_ds = sde_crtc->mixers[lm_idx].hw_ds;
  1702. /* Setup op mode - Dual/single */
  1703. if (cfg->flags & SDE_DRM_DESTSCALER_ENABLE)
  1704. op_mode |= BIT(hw_ds->idx - DS_0);
  1705. if ((i == count-1) && hw_ds->ops.setup_opmode) {
  1706. op_mode |= (cstate->num_ds_enabled ==
  1707. CRTC_DUAL_MIXERS) ?
  1708. SDE_DS_OP_MODE_DUAL : 0;
  1709. hw_ds->ops.setup_opmode(hw_ds, op_mode);
  1710. SDE_EVT32_VERBOSE(DRMID(crtc), op_mode);
  1711. }
  1712. /* Setup scaler */
  1713. if ((cfg->flags & SDE_DRM_DESTSCALER_SCALE_UPDATE) ||
  1714. (cfg->flags &
  1715. SDE_DRM_DESTSCALER_ENHANCER_UPDATE)) {
  1716. if (hw_ds->ops.setup_scaler)
  1717. hw_ds->ops.setup_scaler(hw_ds,
  1718. &cfg->scl3_cfg,
  1719. &cstate->scl3_lut_cfg);
  1720. }
  1721. /*
  1722. * Dest scaler shares the flush bit of the LM in control
  1723. */
  1724. if (hw_ctl && hw_ctl->ops.update_bitmask_mixer)
  1725. hw_ctl->ops.update_bitmask_mixer(
  1726. hw_ctl, hw_lm->idx, 1);
  1727. }
  1728. }
  1729. }
  1730. static void sde_crtc_frame_event_cb(void *data, u32 event)
  1731. {
  1732. struct drm_crtc *crtc = (struct drm_crtc *)data;
  1733. struct sde_crtc *sde_crtc;
  1734. struct msm_drm_private *priv;
  1735. struct sde_crtc_frame_event *fevent;
  1736. struct sde_crtc_frame_event_cb_data *cb_data;
  1737. struct drm_plane *plane;
  1738. u32 ubwc_error;
  1739. unsigned long flags;
  1740. u32 crtc_id;
  1741. cb_data = (struct sde_crtc_frame_event_cb_data *)data;
  1742. if (!data) {
  1743. SDE_ERROR("invalid parameters\n");
  1744. return;
  1745. }
  1746. crtc = cb_data->crtc;
  1747. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  1748. SDE_ERROR("invalid parameters\n");
  1749. return;
  1750. }
  1751. sde_crtc = to_sde_crtc(crtc);
  1752. priv = crtc->dev->dev_private;
  1753. crtc_id = drm_crtc_index(crtc);
  1754. SDE_DEBUG("crtc%d\n", crtc->base.id);
  1755. SDE_EVT32_VERBOSE(DRMID(crtc), event);
  1756. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  1757. fevent = list_first_entry_or_null(&sde_crtc->frame_event_list,
  1758. struct sde_crtc_frame_event, list);
  1759. if (fevent)
  1760. list_del_init(&fevent->list);
  1761. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  1762. if (!fevent) {
  1763. SDE_ERROR("crtc%d event %d overflow\n",
  1764. crtc->base.id, event);
  1765. SDE_EVT32(DRMID(crtc), event);
  1766. return;
  1767. }
  1768. /* log and clear plane ubwc errors if any */
  1769. if (event & (SDE_ENCODER_FRAME_EVENT_ERROR
  1770. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD
  1771. | SDE_ENCODER_FRAME_EVENT_DONE)) {
  1772. drm_for_each_plane_mask(plane, crtc->dev,
  1773. sde_crtc->plane_mask_old) {
  1774. ubwc_error = sde_plane_get_ubwc_error(plane);
  1775. if (ubwc_error) {
  1776. SDE_EVT32(DRMID(crtc), DRMID(plane),
  1777. ubwc_error, SDE_EVTLOG_ERROR);
  1778. SDE_DEBUG("crtc%d plane %d ubwc_error %d\n",
  1779. DRMID(crtc), DRMID(plane),
  1780. ubwc_error);
  1781. sde_plane_clear_ubwc_error(plane);
  1782. }
  1783. }
  1784. }
  1785. fevent->event = event;
  1786. fevent->crtc = crtc;
  1787. fevent->connector = cb_data->connector;
  1788. fevent->ts = ktime_get();
  1789. kthread_queue_work(&priv->event_thread[crtc_id].worker, &fevent->work);
  1790. }
  1791. void sde_crtc_prepare_commit(struct drm_crtc *crtc,
  1792. struct drm_crtc_state *old_state)
  1793. {
  1794. struct drm_device *dev;
  1795. struct sde_crtc *sde_crtc;
  1796. struct sde_crtc_state *cstate;
  1797. struct drm_connector *conn;
  1798. struct drm_encoder *encoder;
  1799. struct drm_connector_list_iter conn_iter;
  1800. if (!crtc || !crtc->state) {
  1801. SDE_ERROR("invalid crtc\n");
  1802. return;
  1803. }
  1804. dev = crtc->dev;
  1805. sde_crtc = to_sde_crtc(crtc);
  1806. cstate = to_sde_crtc_state(crtc->state);
  1807. SDE_EVT32_VERBOSE(DRMID(crtc));
  1808. SDE_ATRACE_BEGIN("sde_crtc_prepare_commit");
  1809. /* identify connectors attached to this crtc */
  1810. cstate->num_connectors = 0;
  1811. drm_connector_list_iter_begin(dev, &conn_iter);
  1812. drm_for_each_connector_iter(conn, &conn_iter)
  1813. if (conn->state && conn->state->crtc == crtc &&
  1814. cstate->num_connectors < MAX_CONNECTORS) {
  1815. encoder = conn->state->best_encoder;
  1816. if (encoder)
  1817. sde_encoder_register_frame_event_callback(
  1818. encoder,
  1819. sde_crtc_frame_event_cb,
  1820. crtc);
  1821. cstate->connectors[cstate->num_connectors++] = conn;
  1822. sde_connector_prepare_fence(conn);
  1823. }
  1824. drm_connector_list_iter_end(&conn_iter);
  1825. /* prepare main output fence */
  1826. sde_fence_prepare(sde_crtc->output_fence);
  1827. SDE_ATRACE_END("sde_crtc_prepare_commit");
  1828. }
  1829. /**
  1830. * sde_crtc_complete_flip - signal pending page_flip events
  1831. * Any pending vblank events are added to the vblank_event_list
  1832. * so that the next vblank interrupt shall signal them.
  1833. * However PAGE_FLIP events are not handled through the vblank_event_list.
  1834. * This API signals any pending PAGE_FLIP events requested through
  1835. * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the sde_crtc->event.
  1836. * if file!=NULL, this is preclose potential cancel-flip path
  1837. * @crtc: Pointer to drm crtc structure
  1838. * @file: Pointer to drm file
  1839. */
  1840. void sde_crtc_complete_flip(struct drm_crtc *crtc,
  1841. struct drm_file *file)
  1842. {
  1843. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  1844. struct drm_device *dev = crtc->dev;
  1845. struct drm_pending_vblank_event *event;
  1846. unsigned long flags;
  1847. spin_lock_irqsave(&dev->event_lock, flags);
  1848. event = sde_crtc->event;
  1849. if (!event)
  1850. goto end;
  1851. /*
  1852. * if regular vblank case (!file) or if cancel-flip from
  1853. * preclose on file that requested flip, then send the
  1854. * event:
  1855. */
  1856. if (!file || (event->base.file_priv == file)) {
  1857. sde_crtc->event = NULL;
  1858. DRM_DEBUG_VBL("%s: send event: %pK\n",
  1859. sde_crtc->name, event);
  1860. SDE_EVT32_VERBOSE(DRMID(crtc));
  1861. drm_crtc_send_vblank_event(crtc, event);
  1862. }
  1863. end:
  1864. spin_unlock_irqrestore(&dev->event_lock, flags);
  1865. }
  1866. enum sde_intf_mode sde_crtc_get_intf_mode(struct drm_crtc *crtc,
  1867. struct drm_crtc_state *cstate)
  1868. {
  1869. struct drm_encoder *encoder;
  1870. if (!crtc || !crtc->dev || !cstate) {
  1871. SDE_ERROR("invalid crtc\n");
  1872. return INTF_MODE_NONE;
  1873. }
  1874. drm_for_each_encoder_mask(encoder, crtc->dev,
  1875. cstate->encoder_mask) {
  1876. /* continue if copy encoder is encountered */
  1877. if (sde_encoder_in_clone_mode(encoder))
  1878. continue;
  1879. return sde_encoder_get_intf_mode(encoder);
  1880. }
  1881. return INTF_MODE_NONE;
  1882. }
  1883. u32 sde_crtc_get_fps_mode(struct drm_crtc *crtc)
  1884. {
  1885. struct drm_encoder *encoder;
  1886. if (!crtc || !crtc->dev) {
  1887. SDE_ERROR("invalid crtc\n");
  1888. return INTF_MODE_NONE;
  1889. }
  1890. drm_for_each_encoder(encoder, crtc->dev)
  1891. if ((encoder->crtc == crtc)
  1892. && !sde_encoder_in_cont_splash(encoder))
  1893. return sde_encoder_get_fps(encoder);
  1894. return 0;
  1895. }
  1896. static void sde_crtc_vblank_cb(void *data)
  1897. {
  1898. struct drm_crtc *crtc = (struct drm_crtc *)data;
  1899. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  1900. /* keep statistics on vblank callback - with auto reset via debugfs */
  1901. if (ktime_compare(sde_crtc->vblank_cb_time, ktime_set(0, 0)) == 0)
  1902. sde_crtc->vblank_cb_time = ktime_get();
  1903. else
  1904. sde_crtc->vblank_cb_count++;
  1905. sde_crtc->vblank_last_cb_time = ktime_get();
  1906. sysfs_notify_dirent(sde_crtc->vsync_event_sf);
  1907. drm_crtc_handle_vblank(crtc);
  1908. DRM_DEBUG_VBL("crtc%d\n", crtc->base.id);
  1909. SDE_EVT32_VERBOSE(DRMID(crtc));
  1910. }
  1911. static void _sde_crtc_retire_event(struct drm_connector *connector,
  1912. ktime_t ts, enum sde_fence_event fence_event)
  1913. {
  1914. if (!connector) {
  1915. SDE_ERROR("invalid param\n");
  1916. return;
  1917. }
  1918. SDE_ATRACE_BEGIN("signal_retire_fence");
  1919. sde_connector_complete_commit(connector, ts, fence_event);
  1920. SDE_ATRACE_END("signal_retire_fence");
  1921. }
  1922. static void sde_crtc_frame_event_work(struct kthread_work *work)
  1923. {
  1924. struct msm_drm_private *priv;
  1925. struct sde_crtc_frame_event *fevent;
  1926. struct drm_crtc *crtc;
  1927. struct sde_crtc *sde_crtc;
  1928. struct sde_kms *sde_kms;
  1929. unsigned long flags;
  1930. bool in_clone_mode = false;
  1931. if (!work) {
  1932. SDE_ERROR("invalid work handle\n");
  1933. return;
  1934. }
  1935. fevent = container_of(work, struct sde_crtc_frame_event, work);
  1936. if (!fevent->crtc || !fevent->crtc->state) {
  1937. SDE_ERROR("invalid crtc\n");
  1938. return;
  1939. }
  1940. crtc = fevent->crtc;
  1941. sde_crtc = to_sde_crtc(crtc);
  1942. sde_kms = _sde_crtc_get_kms(crtc);
  1943. if (!sde_kms) {
  1944. SDE_ERROR("invalid kms handle\n");
  1945. return;
  1946. }
  1947. priv = sde_kms->dev->dev_private;
  1948. SDE_ATRACE_BEGIN("crtc_frame_event");
  1949. SDE_DEBUG("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
  1950. ktime_to_ns(fevent->ts));
  1951. SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event, SDE_EVTLOG_FUNC_ENTRY);
  1952. in_clone_mode = sde_encoder_in_clone_mode(fevent->connector->encoder);
  1953. if (!in_clone_mode && (fevent->event & (SDE_ENCODER_FRAME_EVENT_ERROR
  1954. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD
  1955. | SDE_ENCODER_FRAME_EVENT_DONE))) {
  1956. if (atomic_read(&sde_crtc->frame_pending) < 1) {
  1957. /* this should not happen */
  1958. SDE_ERROR("crtc%d ts:%lld invalid frame_pending:%d\n",
  1959. crtc->base.id,
  1960. ktime_to_ns(fevent->ts),
  1961. atomic_read(&sde_crtc->frame_pending));
  1962. SDE_EVT32(DRMID(crtc), fevent->event,
  1963. SDE_EVTLOG_FUNC_CASE1);
  1964. } else if (atomic_dec_return(&sde_crtc->frame_pending) == 0) {
  1965. /* release bandwidth and other resources */
  1966. SDE_DEBUG("crtc%d ts:%lld last pending\n",
  1967. crtc->base.id,
  1968. ktime_to_ns(fevent->ts));
  1969. SDE_EVT32(DRMID(crtc), fevent->event,
  1970. SDE_EVTLOG_FUNC_CASE2);
  1971. sde_core_perf_crtc_release_bw(crtc);
  1972. } else {
  1973. SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event,
  1974. SDE_EVTLOG_FUNC_CASE3);
  1975. }
  1976. }
  1977. if (fevent->event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE) {
  1978. SDE_ATRACE_BEGIN("signal_release_fence");
  1979. sde_fence_signal(sde_crtc->output_fence, fevent->ts,
  1980. (fevent->event & SDE_ENCODER_FRAME_EVENT_ERROR)
  1981. ? SDE_FENCE_SIGNAL_ERROR : SDE_FENCE_SIGNAL);
  1982. SDE_ATRACE_END("signal_release_fence");
  1983. }
  1984. if (fevent->event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE)
  1985. /* this api should be called without spin_lock */
  1986. _sde_crtc_retire_event(fevent->connector, fevent->ts,
  1987. (fevent->event & SDE_ENCODER_FRAME_EVENT_ERROR)
  1988. ? SDE_FENCE_SIGNAL_ERROR : SDE_FENCE_SIGNAL);
  1989. if (fevent->event & SDE_ENCODER_FRAME_EVENT_PANEL_DEAD)
  1990. SDE_ERROR("crtc%d ts:%lld received panel dead event\n",
  1991. crtc->base.id, ktime_to_ns(fevent->ts));
  1992. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  1993. list_add_tail(&fevent->list, &sde_crtc->frame_event_list);
  1994. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  1995. SDE_ATRACE_END("crtc_frame_event");
  1996. }
  1997. void sde_crtc_complete_commit(struct drm_crtc *crtc,
  1998. struct drm_crtc_state *old_state)
  1999. {
  2000. struct sde_crtc *sde_crtc;
  2001. if (!crtc || !crtc->state) {
  2002. SDE_ERROR("invalid crtc\n");
  2003. return;
  2004. }
  2005. sde_crtc = to_sde_crtc(crtc);
  2006. SDE_EVT32_VERBOSE(DRMID(crtc));
  2007. sde_core_perf_crtc_update(crtc, 0, false);
  2008. }
  2009. /**
  2010. * _sde_crtc_set_input_fence_timeout - update ns version of in fence timeout
  2011. * @cstate: Pointer to sde crtc state
  2012. */
  2013. static void _sde_crtc_set_input_fence_timeout(struct sde_crtc_state *cstate)
  2014. {
  2015. if (!cstate) {
  2016. SDE_ERROR("invalid cstate\n");
  2017. return;
  2018. }
  2019. cstate->input_fence_timeout_ns =
  2020. sde_crtc_get_property(cstate, CRTC_PROP_INPUT_FENCE_TIMEOUT);
  2021. cstate->input_fence_timeout_ns *= NSEC_PER_MSEC;
  2022. }
  2023. /**
  2024. * _sde_crtc_clear_dim_layers_v1 - clear all dim layer settings
  2025. * @cstate: Pointer to sde crtc state
  2026. */
  2027. static void _sde_crtc_clear_dim_layers_v1(struct sde_crtc_state *cstate)
  2028. {
  2029. u32 i;
  2030. if (!cstate)
  2031. return;
  2032. for (i = 0; i < cstate->num_dim_layers; i++)
  2033. memset(&cstate->dim_layer[i], 0, sizeof(cstate->dim_layer[i]));
  2034. cstate->num_dim_layers = 0;
  2035. }
  2036. /**
  2037. * _sde_crtc_set_dim_layer_v1 - copy dim layer settings from userspace
  2038. * @cstate: Pointer to sde crtc state
  2039. * @user_ptr: User ptr for sde_drm_dim_layer_v1 struct
  2040. */
  2041. static void _sde_crtc_set_dim_layer_v1(struct sde_crtc_state *cstate,
  2042. void __user *usr_ptr)
  2043. {
  2044. struct sde_drm_dim_layer_v1 dim_layer_v1;
  2045. struct sde_drm_dim_layer_cfg *user_cfg;
  2046. struct sde_hw_dim_layer *dim_layer;
  2047. u32 count, i;
  2048. if (!cstate) {
  2049. SDE_ERROR("invalid cstate\n");
  2050. return;
  2051. }
  2052. dim_layer = cstate->dim_layer;
  2053. if (!usr_ptr) {
  2054. /* usr_ptr is null when setting the default property value */
  2055. _sde_crtc_clear_dim_layers_v1(cstate);
  2056. SDE_DEBUG("dim_layer data removed\n");
  2057. return;
  2058. }
  2059. if (copy_from_user(&dim_layer_v1, usr_ptr, sizeof(dim_layer_v1))) {
  2060. SDE_ERROR("failed to copy dim_layer data\n");
  2061. return;
  2062. }
  2063. count = dim_layer_v1.num_layers;
  2064. if (count > SDE_MAX_DIM_LAYERS) {
  2065. SDE_ERROR("invalid number of dim_layers:%d", count);
  2066. return;
  2067. }
  2068. /* populate from user space */
  2069. cstate->num_dim_layers = count;
  2070. for (i = 0; i < count; i++) {
  2071. user_cfg = &dim_layer_v1.layer_cfg[i];
  2072. dim_layer[i].flags = user_cfg->flags;
  2073. dim_layer[i].stage = user_cfg->stage + SDE_STAGE_0;
  2074. dim_layer[i].rect.x = user_cfg->rect.x1;
  2075. dim_layer[i].rect.y = user_cfg->rect.y1;
  2076. dim_layer[i].rect.w = user_cfg->rect.x2 - user_cfg->rect.x1;
  2077. dim_layer[i].rect.h = user_cfg->rect.y2 - user_cfg->rect.y1;
  2078. dim_layer[i].color_fill = (struct sde_mdss_color) {
  2079. user_cfg->color_fill.color_0,
  2080. user_cfg->color_fill.color_1,
  2081. user_cfg->color_fill.color_2,
  2082. user_cfg->color_fill.color_3,
  2083. };
  2084. SDE_DEBUG("dim_layer[%d] - flags:%d, stage:%d\n",
  2085. i, dim_layer[i].flags, dim_layer[i].stage);
  2086. SDE_DEBUG(" rect:{%d,%d,%d,%d}, color:{%d,%d,%d,%d}\n",
  2087. dim_layer[i].rect.x, dim_layer[i].rect.y,
  2088. dim_layer[i].rect.w, dim_layer[i].rect.h,
  2089. dim_layer[i].color_fill.color_0,
  2090. dim_layer[i].color_fill.color_1,
  2091. dim_layer[i].color_fill.color_2,
  2092. dim_layer[i].color_fill.color_3);
  2093. }
  2094. }
  2095. /**
  2096. * _sde_crtc_set_dest_scaler - copy dest scaler settings from userspace
  2097. * @sde_crtc : Pointer to sde crtc
  2098. * @cstate : Pointer to sde crtc state
  2099. * @usr_ptr: User ptr for sde_drm_dest_scaler_data struct
  2100. */
  2101. static int _sde_crtc_set_dest_scaler(struct sde_crtc *sde_crtc,
  2102. struct sde_crtc_state *cstate,
  2103. void __user *usr_ptr)
  2104. {
  2105. struct sde_drm_dest_scaler_data ds_data;
  2106. struct sde_drm_dest_scaler_cfg *ds_cfg_usr;
  2107. struct sde_drm_scaler_v2 scaler_v2;
  2108. void __user *scaler_v2_usr;
  2109. int i, count;
  2110. if (!sde_crtc || !cstate) {
  2111. SDE_ERROR("invalid sde_crtc/state\n");
  2112. return -EINVAL;
  2113. }
  2114. SDE_DEBUG("crtc %s\n", sde_crtc->name);
  2115. if (!usr_ptr) {
  2116. SDE_DEBUG("ds data removed\n");
  2117. return 0;
  2118. }
  2119. if (copy_from_user(&ds_data, usr_ptr, sizeof(ds_data))) {
  2120. SDE_ERROR("%s:failed to copy dest scaler data from user\n",
  2121. sde_crtc->name);
  2122. return -EINVAL;
  2123. }
  2124. count = ds_data.num_dest_scaler;
  2125. if (!count) {
  2126. SDE_DEBUG("no ds data available\n");
  2127. return 0;
  2128. }
  2129. if (count > SDE_MAX_DS_COUNT) {
  2130. SDE_ERROR("%s: invalid config: num_ds(%d) max(%d)\n",
  2131. sde_crtc->name, count, SDE_MAX_DS_COUNT);
  2132. SDE_EVT32(DRMID(&sde_crtc->base), count, SDE_EVTLOG_ERROR);
  2133. return -EINVAL;
  2134. }
  2135. /* Populate from user space */
  2136. for (i = 0; i < count; i++) {
  2137. ds_cfg_usr = &ds_data.ds_cfg[i];
  2138. cstate->ds_cfg[i].idx = ds_cfg_usr->index;
  2139. cstate->ds_cfg[i].flags = ds_cfg_usr->flags;
  2140. cstate->ds_cfg[i].lm_width = ds_cfg_usr->lm_width;
  2141. cstate->ds_cfg[i].lm_height = ds_cfg_usr->lm_height;
  2142. memset(&scaler_v2, 0, sizeof(scaler_v2));
  2143. if (ds_cfg_usr->scaler_cfg) {
  2144. scaler_v2_usr =
  2145. (void __user *)((uintptr_t)ds_cfg_usr->scaler_cfg);
  2146. if (copy_from_user(&scaler_v2, scaler_v2_usr,
  2147. sizeof(scaler_v2))) {
  2148. SDE_ERROR("%s:scaler: copy from user failed\n",
  2149. sde_crtc->name);
  2150. return -EINVAL;
  2151. }
  2152. }
  2153. sde_set_scaler_v2(&cstate->ds_cfg[i].scl3_cfg, &scaler_v2);
  2154. SDE_DEBUG("en(%d)dir(%d)de(%d) src(%dx%d) dst(%dx%d)\n",
  2155. scaler_v2.enable, scaler_v2.dir_en, scaler_v2.de.enable,
  2156. scaler_v2.src_width[0], scaler_v2.src_height[0],
  2157. scaler_v2.dst_width, scaler_v2.dst_height);
  2158. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base),
  2159. scaler_v2.enable, scaler_v2.dir_en, scaler_v2.de.enable,
  2160. scaler_v2.src_width[0], scaler_v2.src_height[0],
  2161. scaler_v2.dst_width, scaler_v2.dst_height);
  2162. SDE_DEBUG("ds cfg[%d]-ndx(%d) flags(%d) lm(%dx%d)\n",
  2163. i, ds_cfg_usr->index, ds_cfg_usr->flags,
  2164. ds_cfg_usr->lm_width, ds_cfg_usr->lm_height);
  2165. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), i, ds_cfg_usr->index,
  2166. ds_cfg_usr->flags, ds_cfg_usr->lm_width,
  2167. ds_cfg_usr->lm_height);
  2168. }
  2169. cstate->num_ds = count;
  2170. cstate->ds_dirty = true;
  2171. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), count, cstate->ds_dirty);
  2172. return 0;
  2173. }
  2174. static int _sde_crtc_check_dest_scaler_lm(struct drm_crtc *crtc,
  2175. struct drm_display_mode *mode, struct sde_hw_ds_cfg *cfg, u32 hdisplay,
  2176. u32 prev_lm_width, u32 prev_lm_height)
  2177. {
  2178. if (cfg->lm_width > hdisplay || cfg->lm_height > mode->vdisplay
  2179. || !cfg->lm_width || !cfg->lm_height) {
  2180. SDE_ERROR("crtc%d: lm size[%d,%d] display [%d,%d]\n",
  2181. crtc->base.id, cfg->lm_width, cfg->lm_height,
  2182. hdisplay, mode->vdisplay);
  2183. SDE_EVT32(DRMID(crtc), cfg->lm_width, cfg->lm_height,
  2184. hdisplay, mode->vdisplay, SDE_EVTLOG_ERROR);
  2185. return -E2BIG;
  2186. }
  2187. if (!prev_lm_width && !prev_lm_height) {
  2188. prev_lm_width = cfg->lm_width;
  2189. prev_lm_height = cfg->lm_height;
  2190. } else {
  2191. if (cfg->lm_width != prev_lm_width ||
  2192. cfg->lm_height != prev_lm_height) {
  2193. SDE_ERROR("crtc%d:lm left[%d,%d]right[%d %d]\n",
  2194. crtc->base.id, cfg->lm_width,
  2195. cfg->lm_height, prev_lm_width,
  2196. prev_lm_height);
  2197. SDE_EVT32(DRMID(crtc), cfg->lm_width,
  2198. cfg->lm_height, prev_lm_width,
  2199. prev_lm_height, SDE_EVTLOG_ERROR);
  2200. return -EINVAL;
  2201. }
  2202. }
  2203. return 0;
  2204. }
  2205. static int _sde_crtc_check_dest_scaler_cfg(struct drm_crtc *crtc,
  2206. struct sde_crtc *sde_crtc, struct drm_display_mode *mode,
  2207. struct sde_hw_ds *hw_ds, struct sde_hw_ds_cfg *cfg, u32 hdisplay,
  2208. u32 max_in_width, u32 max_out_width)
  2209. {
  2210. if (cfg->flags & SDE_DRM_DESTSCALER_SCALE_UPDATE ||
  2211. cfg->flags & SDE_DRM_DESTSCALER_ENHANCER_UPDATE) {
  2212. /**
  2213. * Scaler src and dst width shouldn't exceed the maximum
  2214. * width limitation. Also, if there is no partial update
  2215. * dst width and height must match display resolution.
  2216. */
  2217. if (cfg->scl3_cfg.src_width[0] > max_in_width ||
  2218. cfg->scl3_cfg.dst_width > max_out_width ||
  2219. !cfg->scl3_cfg.src_width[0] ||
  2220. !cfg->scl3_cfg.dst_width ||
  2221. (!(cfg->flags & SDE_DRM_DESTSCALER_PU_ENABLE)
  2222. && (cfg->scl3_cfg.dst_width != hdisplay ||
  2223. cfg->scl3_cfg.dst_height != mode->vdisplay))) {
  2224. SDE_ERROR("crtc%d: ", crtc->base.id);
  2225. SDE_ERROR("src_w(%d) dst(%dx%d) display(%dx%d)",
  2226. cfg->scl3_cfg.src_width[0],
  2227. cfg->scl3_cfg.dst_width,
  2228. cfg->scl3_cfg.dst_height,
  2229. hdisplay, mode->vdisplay);
  2230. SDE_ERROR("num_mixers(%d) flags(%d) ds-%d:\n",
  2231. sde_crtc->num_mixers, cfg->flags,
  2232. hw_ds->idx - DS_0);
  2233. SDE_ERROR("scale_en = %d, DE_en =%d\n",
  2234. cfg->scl3_cfg.enable,
  2235. cfg->scl3_cfg.de.enable);
  2236. SDE_EVT32(DRMID(crtc), cfg->scl3_cfg.enable,
  2237. cfg->scl3_cfg.de.enable, cfg->flags,
  2238. max_in_width, max_out_width,
  2239. cfg->scl3_cfg.src_width[0],
  2240. cfg->scl3_cfg.dst_width,
  2241. cfg->scl3_cfg.dst_height, hdisplay,
  2242. mode->vdisplay, sde_crtc->num_mixers,
  2243. SDE_EVTLOG_ERROR);
  2244. cfg->flags &=
  2245. ~SDE_DRM_DESTSCALER_SCALE_UPDATE;
  2246. cfg->flags &=
  2247. ~SDE_DRM_DESTSCALER_ENHANCER_UPDATE;
  2248. return -EINVAL;
  2249. }
  2250. }
  2251. return 0;
  2252. }
  2253. static int _sde_crtc_check_dest_scaler_validate_ds(struct drm_crtc *crtc,
  2254. struct sde_crtc *sde_crtc, struct sde_crtc_state *cstate,
  2255. struct drm_display_mode *mode, struct sde_hw_ds *hw_ds,
  2256. struct sde_hw_ds_cfg *cfg, u32 hdisplay, u32 *num_ds_enable,
  2257. u32 prev_lm_width, u32 prev_lm_height, u32 max_in_width,
  2258. u32 max_out_width)
  2259. {
  2260. int i, ret;
  2261. u32 lm_idx;
  2262. for (i = 0; i < cstate->num_ds; i++) {
  2263. cfg = &cstate->ds_cfg[i];
  2264. lm_idx = cfg->idx;
  2265. /**
  2266. * Validate against topology
  2267. * No of dest scalers should match the num of mixers
  2268. * unless it is partial update left only/right only use case
  2269. */
  2270. if (lm_idx >= sde_crtc->num_mixers || (i != lm_idx &&
  2271. !(cfg->flags & SDE_DRM_DESTSCALER_PU_ENABLE))) {
  2272. SDE_ERROR("crtc%d: ds_cfg id(%d):idx(%d), flags(%d)\n",
  2273. crtc->base.id, i, lm_idx, cfg->flags);
  2274. SDE_EVT32(DRMID(crtc), i, lm_idx, cfg->flags,
  2275. SDE_EVTLOG_ERROR);
  2276. return -EINVAL;
  2277. }
  2278. hw_ds = sde_crtc->mixers[lm_idx].hw_ds;
  2279. if (!max_in_width && !max_out_width) {
  2280. max_in_width = hw_ds->scl->top->maxinputwidth;
  2281. max_out_width = hw_ds->scl->top->maxoutputwidth;
  2282. if (cstate->num_ds == CRTC_DUAL_MIXERS)
  2283. max_in_width -= SDE_DS_OVERFETCH_SIZE;
  2284. SDE_DEBUG("max DS width [%d,%d] for num_ds = %d\n",
  2285. max_in_width, max_out_width, cstate->num_ds);
  2286. }
  2287. /* Check LM width and height */
  2288. ret = _sde_crtc_check_dest_scaler_lm(crtc, mode, cfg, hdisplay,
  2289. prev_lm_width, prev_lm_height);
  2290. if (ret)
  2291. return ret;
  2292. /* Check scaler data */
  2293. ret = _sde_crtc_check_dest_scaler_cfg(crtc, sde_crtc, mode,
  2294. hw_ds, cfg, hdisplay,
  2295. max_in_width, max_out_width);
  2296. if (ret)
  2297. return ret;
  2298. if (cfg->flags & SDE_DRM_DESTSCALER_ENABLE)
  2299. (*num_ds_enable)++;
  2300. SDE_DEBUG("ds[%d]: flags[0x%X]\n",
  2301. hw_ds->idx - DS_0, cfg->flags);
  2302. SDE_EVT32_VERBOSE(DRMID(crtc), hw_ds->idx - DS_0, cfg->flags);
  2303. }
  2304. return 0;
  2305. }
  2306. static void _sde_crtc_check_dest_scaler_data_disable(struct drm_crtc *crtc,
  2307. struct sde_crtc_state *cstate, struct sde_hw_ds_cfg *cfg,
  2308. u32 num_ds_enable)
  2309. {
  2310. int i;
  2311. SDE_DEBUG("dest scaler status : %d -> %d\n",
  2312. cstate->num_ds_enabled, num_ds_enable);
  2313. SDE_EVT32_VERBOSE(DRMID(crtc), cstate->num_ds_enabled, num_ds_enable,
  2314. cstate->num_ds, cstate->ds_dirty);
  2315. if (cstate->num_ds_enabled != num_ds_enable) {
  2316. /* Disabling destination scaler */
  2317. if (!num_ds_enable) {
  2318. for (i = 0; i < cstate->num_ds; i++) {
  2319. cfg = &cstate->ds_cfg[i];
  2320. cfg->idx = i;
  2321. /* Update scaler settings in disable case */
  2322. cfg->flags = SDE_DRM_DESTSCALER_SCALE_UPDATE;
  2323. cfg->scl3_cfg.enable = 0;
  2324. cfg->scl3_cfg.de.enable = 0;
  2325. }
  2326. }
  2327. cstate->num_ds_enabled = num_ds_enable;
  2328. cstate->ds_dirty = true;
  2329. } else {
  2330. if (!cstate->num_ds_enabled)
  2331. cstate->ds_dirty = false;
  2332. }
  2333. }
  2334. /**
  2335. * _sde_crtc_check_dest_scaler_data - validate the dest scaler data
  2336. * @crtc : Pointer to drm crtc
  2337. * @state : Pointer to drm crtc state
  2338. */
  2339. static int _sde_crtc_check_dest_scaler_data(struct drm_crtc *crtc,
  2340. struct drm_crtc_state *state)
  2341. {
  2342. struct sde_crtc *sde_crtc;
  2343. struct sde_crtc_state *cstate;
  2344. struct drm_display_mode *mode;
  2345. struct sde_kms *kms;
  2346. struct sde_hw_ds *hw_ds = NULL;
  2347. struct sde_hw_ds_cfg *cfg = NULL;
  2348. u32 ret = 0;
  2349. u32 num_ds_enable = 0, hdisplay = 0;
  2350. u32 max_in_width = 0, max_out_width = 0;
  2351. u32 prev_lm_width = 0, prev_lm_height = 0;
  2352. if (!crtc || !state)
  2353. return -EINVAL;
  2354. sde_crtc = to_sde_crtc(crtc);
  2355. cstate = to_sde_crtc_state(state);
  2356. kms = _sde_crtc_get_kms(crtc);
  2357. mode = &state->adjusted_mode;
  2358. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2359. if (!cstate->ds_dirty) {
  2360. SDE_DEBUG("dest scaler property not set, skip validation\n");
  2361. return 0;
  2362. }
  2363. if (!kms || !kms->catalog) {
  2364. SDE_ERROR("crtc%d: invalid parameters\n", crtc->base.id);
  2365. return -EINVAL;
  2366. }
  2367. if (!kms->catalog->mdp[0].has_dest_scaler) {
  2368. SDE_DEBUG("dest scaler feature not supported\n");
  2369. return 0;
  2370. }
  2371. if (!sde_crtc->num_mixers) {
  2372. SDE_DEBUG("mixers not allocated\n");
  2373. return 0;
  2374. }
  2375. ret = _sde_validate_hw_resources(sde_crtc);
  2376. if (ret)
  2377. goto err;
  2378. /**
  2379. * No of dest scalers shouldn't exceed hw ds block count and
  2380. * also, match the num of mixers unless it is partial update
  2381. * left only/right only use case - currently PU + DS is not supported
  2382. */
  2383. if (cstate->num_ds > kms->catalog->ds_count ||
  2384. ((cstate->num_ds != sde_crtc->num_mixers) &&
  2385. !(cstate->ds_cfg[0].flags & SDE_DRM_DESTSCALER_PU_ENABLE))) {
  2386. SDE_ERROR("crtc%d: num_ds(%d), hw_ds_cnt(%d) flags(%d)\n",
  2387. crtc->base.id, cstate->num_ds, kms->catalog->ds_count,
  2388. cstate->ds_cfg[0].flags);
  2389. ret = -EINVAL;
  2390. goto err;
  2391. }
  2392. /**
  2393. * Check if DS needs to be enabled or disabled
  2394. * In case of enable, validate the data
  2395. */
  2396. if (!(cstate->ds_cfg[0].flags & SDE_DRM_DESTSCALER_ENABLE)) {
  2397. SDE_DEBUG("disable dest scaler, num(%d) flags(%d)\n",
  2398. cstate->num_ds, cstate->ds_cfg[0].flags);
  2399. goto disable;
  2400. }
  2401. /* Display resolution */
  2402. hdisplay = mode->hdisplay/sde_crtc->num_mixers;
  2403. /* Validate the DS data */
  2404. ret = _sde_crtc_check_dest_scaler_validate_ds(crtc, sde_crtc, cstate,
  2405. mode, hw_ds, cfg, hdisplay, &num_ds_enable,
  2406. prev_lm_width, prev_lm_height,
  2407. max_in_width, max_out_width);
  2408. if (ret)
  2409. goto err;
  2410. disable:
  2411. _sde_crtc_check_dest_scaler_data_disable(crtc, cstate, cfg,
  2412. num_ds_enable);
  2413. return 0;
  2414. err:
  2415. cstate->ds_dirty = false;
  2416. return ret;
  2417. }
  2418. /**
  2419. * _sde_crtc_wait_for_fences - wait for incoming framebuffer sync fences
  2420. * @crtc: Pointer to CRTC object
  2421. */
  2422. static void _sde_crtc_wait_for_fences(struct drm_crtc *crtc)
  2423. {
  2424. struct drm_plane *plane = NULL;
  2425. uint32_t wait_ms = 1;
  2426. ktime_t kt_end, kt_wait;
  2427. int rc = 0;
  2428. SDE_DEBUG("\n");
  2429. if (!crtc || !crtc->state) {
  2430. SDE_ERROR("invalid crtc/state %pK\n", crtc);
  2431. return;
  2432. }
  2433. /* use monotonic timer to limit total fence wait time */
  2434. kt_end = ktime_add_ns(ktime_get(),
  2435. to_sde_crtc_state(crtc->state)->input_fence_timeout_ns);
  2436. /*
  2437. * Wait for fences sequentially, as all of them need to be signalled
  2438. * before we can proceed.
  2439. *
  2440. * Limit total wait time to INPUT_FENCE_TIMEOUT, but still call
  2441. * sde_plane_wait_input_fence with wait_ms == 0 after the timeout so
  2442. * that each plane can check its fence status and react appropriately
  2443. * if its fence has timed out. Call input fence wait multiple times if
  2444. * fence wait is interrupted due to interrupt call.
  2445. */
  2446. SDE_ATRACE_BEGIN("plane_wait_input_fence");
  2447. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2448. do {
  2449. kt_wait = ktime_sub(kt_end, ktime_get());
  2450. if (ktime_compare(kt_wait, ktime_set(0, 0)) >= 0)
  2451. wait_ms = ktime_to_ms(kt_wait);
  2452. else
  2453. wait_ms = 0;
  2454. rc = sde_plane_wait_input_fence(plane, wait_ms);
  2455. } while (wait_ms && rc == -ERESTARTSYS);
  2456. }
  2457. SDE_ATRACE_END("plane_wait_input_fence");
  2458. }
  2459. static void _sde_crtc_setup_mixer_for_encoder(
  2460. struct drm_crtc *crtc,
  2461. struct drm_encoder *enc)
  2462. {
  2463. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2464. struct sde_kms *sde_kms = _sde_crtc_get_kms(crtc);
  2465. struct sde_rm *rm = &sde_kms->rm;
  2466. struct sde_crtc_mixer *mixer;
  2467. struct sde_hw_ctl *last_valid_ctl = NULL;
  2468. int i;
  2469. struct sde_rm_hw_iter lm_iter, ctl_iter, dspp_iter, ds_iter;
  2470. sde_rm_init_hw_iter(&lm_iter, enc->base.id, SDE_HW_BLK_LM);
  2471. sde_rm_init_hw_iter(&ctl_iter, enc->base.id, SDE_HW_BLK_CTL);
  2472. sde_rm_init_hw_iter(&dspp_iter, enc->base.id, SDE_HW_BLK_DSPP);
  2473. sde_rm_init_hw_iter(&ds_iter, enc->base.id, SDE_HW_BLK_DS);
  2474. /* Set up all the mixers and ctls reserved by this encoder */
  2475. for (i = sde_crtc->num_mixers; i < ARRAY_SIZE(sde_crtc->mixers); i++) {
  2476. mixer = &sde_crtc->mixers[i];
  2477. if (!sde_rm_get_hw(rm, &lm_iter))
  2478. break;
  2479. mixer->hw_lm = (struct sde_hw_mixer *)lm_iter.hw;
  2480. /* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */
  2481. if (!sde_rm_get_hw(rm, &ctl_iter)) {
  2482. SDE_DEBUG("no ctl assigned to lm %d, using previous\n",
  2483. mixer->hw_lm->idx - LM_0);
  2484. mixer->hw_ctl = last_valid_ctl;
  2485. } else {
  2486. mixer->hw_ctl = (struct sde_hw_ctl *)ctl_iter.hw;
  2487. last_valid_ctl = mixer->hw_ctl;
  2488. sde_crtc->num_ctls++;
  2489. }
  2490. /* Shouldn't happen, mixers are always >= ctls */
  2491. if (!mixer->hw_ctl) {
  2492. SDE_ERROR("no valid ctls found for lm %d\n",
  2493. mixer->hw_lm->idx - LM_0);
  2494. return;
  2495. }
  2496. /* Dspp may be null */
  2497. (void) sde_rm_get_hw(rm, &dspp_iter);
  2498. mixer->hw_dspp = (struct sde_hw_dspp *)dspp_iter.hw;
  2499. /* DS may be null */
  2500. (void) sde_rm_get_hw(rm, &ds_iter);
  2501. mixer->hw_ds = (struct sde_hw_ds *)ds_iter.hw;
  2502. mixer->encoder = enc;
  2503. sde_crtc->num_mixers++;
  2504. SDE_DEBUG("setup mixer %d: lm %d\n",
  2505. i, mixer->hw_lm->idx - LM_0);
  2506. SDE_DEBUG("setup mixer %d: ctl %d\n",
  2507. i, mixer->hw_ctl->idx - CTL_0);
  2508. if (mixer->hw_ds)
  2509. SDE_DEBUG("setup mixer %d: ds %d\n",
  2510. i, mixer->hw_ds->idx - DS_0);
  2511. }
  2512. }
  2513. static void _sde_crtc_setup_mixers(struct drm_crtc *crtc)
  2514. {
  2515. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2516. struct drm_encoder *enc;
  2517. sde_crtc->num_ctls = 0;
  2518. sde_crtc->num_mixers = 0;
  2519. sde_crtc->mixers_swapped = false;
  2520. memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers));
  2521. mutex_lock(&sde_crtc->crtc_lock);
  2522. /* Check for mixers on all encoders attached to this crtc */
  2523. list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) {
  2524. if (enc->crtc != crtc)
  2525. continue;
  2526. /* avoid overwriting mixers info from a copy encoder */
  2527. if (sde_encoder_in_clone_mode(enc))
  2528. continue;
  2529. _sde_crtc_setup_mixer_for_encoder(crtc, enc);
  2530. }
  2531. mutex_unlock(&sde_crtc->crtc_lock);
  2532. _sde_crtc_check_dest_scaler_data(crtc, crtc->state);
  2533. }
  2534. static void _sde_crtc_setup_is_ppsplit(struct drm_crtc_state *state)
  2535. {
  2536. int i;
  2537. struct sde_crtc_state *cstate;
  2538. cstate = to_sde_crtc_state(state);
  2539. cstate->is_ppsplit = false;
  2540. for (i = 0; i < cstate->num_connectors; i++) {
  2541. struct drm_connector *conn = cstate->connectors[i];
  2542. if (sde_connector_get_topology_name(conn) ==
  2543. SDE_RM_TOPOLOGY_PPSPLIT)
  2544. cstate->is_ppsplit = true;
  2545. }
  2546. }
  2547. static void _sde_crtc_setup_lm_bounds(struct drm_crtc *crtc,
  2548. struct drm_crtc_state *state)
  2549. {
  2550. struct sde_crtc *sde_crtc;
  2551. struct sde_crtc_state *cstate;
  2552. struct drm_display_mode *adj_mode;
  2553. u32 crtc_split_width;
  2554. int i;
  2555. if (!crtc || !state) {
  2556. SDE_ERROR("invalid args\n");
  2557. return;
  2558. }
  2559. sde_crtc = to_sde_crtc(crtc);
  2560. cstate = to_sde_crtc_state(state);
  2561. adj_mode = &state->adjusted_mode;
  2562. crtc_split_width = sde_crtc_get_mixer_width(sde_crtc, cstate, adj_mode);
  2563. for (i = 0; i < sde_crtc->num_mixers; i++) {
  2564. cstate->lm_bounds[i].x = crtc_split_width * i;
  2565. cstate->lm_bounds[i].y = 0;
  2566. cstate->lm_bounds[i].w = crtc_split_width;
  2567. cstate->lm_bounds[i].h =
  2568. sde_crtc_get_mixer_height(sde_crtc, cstate, adj_mode);
  2569. memcpy(&cstate->lm_roi[i], &cstate->lm_bounds[i],
  2570. sizeof(cstate->lm_roi[i]));
  2571. SDE_EVT32_VERBOSE(DRMID(crtc), i,
  2572. cstate->lm_bounds[i].x, cstate->lm_bounds[i].y,
  2573. cstate->lm_bounds[i].w, cstate->lm_bounds[i].h);
  2574. SDE_DEBUG("%s: lm%d bnd&roi (%d,%d,%d,%d)\n", sde_crtc->name, i,
  2575. cstate->lm_roi[i].x, cstate->lm_roi[i].y,
  2576. cstate->lm_roi[i].w, cstate->lm_roi[i].h);
  2577. }
  2578. drm_mode_debug_printmodeline(adj_mode);
  2579. }
  2580. static void sde_crtc_atomic_begin(struct drm_crtc *crtc,
  2581. struct drm_crtc_state *old_state)
  2582. {
  2583. struct sde_crtc *sde_crtc;
  2584. struct drm_encoder *encoder;
  2585. struct drm_device *dev;
  2586. struct sde_kms *sde_kms;
  2587. struct sde_splash_display *splash_display;
  2588. bool cont_splash_enabled = false;
  2589. size_t i;
  2590. if (!crtc) {
  2591. SDE_ERROR("invalid crtc\n");
  2592. return;
  2593. }
  2594. if (!crtc->state->enable) {
  2595. SDE_DEBUG("crtc%d -> enable %d, skip atomic_begin\n",
  2596. crtc->base.id, crtc->state->enable);
  2597. return;
  2598. }
  2599. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  2600. SDE_ERROR("power resource is not enabled\n");
  2601. return;
  2602. }
  2603. sde_kms = _sde_crtc_get_kms(crtc);
  2604. if (!sde_kms)
  2605. return;
  2606. SDE_ATRACE_BEGIN("crtc_atomic_begin");
  2607. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2608. sde_crtc = to_sde_crtc(crtc);
  2609. dev = crtc->dev;
  2610. if (!sde_crtc->num_mixers) {
  2611. _sde_crtc_setup_mixers(crtc);
  2612. _sde_crtc_setup_is_ppsplit(crtc->state);
  2613. _sde_crtc_setup_lm_bounds(crtc, crtc->state);
  2614. }
  2615. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  2616. if (encoder->crtc != crtc)
  2617. continue;
  2618. /* encoder will trigger pending mask now */
  2619. sde_encoder_trigger_kickoff_pending(encoder);
  2620. }
  2621. /*
  2622. * If no mixers have been allocated in sde_crtc_atomic_check(),
  2623. * it means we are trying to flush a CRTC whose state is disabled:
  2624. * nothing else needs to be done.
  2625. */
  2626. if (unlikely(!sde_crtc->num_mixers))
  2627. goto end;
  2628. _sde_crtc_blend_setup(crtc, old_state, true);
  2629. _sde_crtc_dest_scaler_setup(crtc);
  2630. /* cancel the idle notify delayed work */
  2631. if (sde_encoder_check_curr_mode(sde_crtc->mixers[0].encoder,
  2632. MSM_DISPLAY_VIDEO_MODE) &&
  2633. kthread_cancel_delayed_work_sync(&sde_crtc->idle_notify_work))
  2634. SDE_DEBUG("idle notify work cancelled\n");
  2635. /*
  2636. * Since CP properties use AXI buffer to program the
  2637. * HW, check if context bank is in attached state,
  2638. * apply color processing properties only if
  2639. * smmu state is attached,
  2640. */
  2641. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2642. splash_display = &sde_kms->splash_data.splash_display[i];
  2643. if (splash_display->cont_splash_enabled &&
  2644. splash_display->encoder &&
  2645. crtc == splash_display->encoder->crtc)
  2646. cont_splash_enabled = true;
  2647. }
  2648. if (sde_kms_is_cp_operation_allowed(sde_kms) &&
  2649. (cont_splash_enabled || sde_crtc->enabled))
  2650. sde_cp_crtc_apply_properties(crtc);
  2651. /*
  2652. * PP_DONE irq is only used by command mode for now.
  2653. * It is better to request pending before FLUSH and START trigger
  2654. * to make sure no pp_done irq missed.
  2655. * This is safe because no pp_done will happen before SW trigger
  2656. * in command mode.
  2657. */
  2658. end:
  2659. SDE_ATRACE_END("crtc_atomic_begin");
  2660. }
  2661. static void sde_crtc_atomic_flush(struct drm_crtc *crtc,
  2662. struct drm_crtc_state *old_crtc_state)
  2663. {
  2664. struct drm_encoder *encoder;
  2665. struct sde_crtc *sde_crtc;
  2666. struct drm_device *dev;
  2667. struct drm_plane *plane;
  2668. struct msm_drm_private *priv;
  2669. struct msm_drm_thread *event_thread;
  2670. struct sde_crtc_state *cstate;
  2671. struct sde_kms *sde_kms;
  2672. int idle_time = 0;
  2673. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  2674. SDE_ERROR("invalid crtc\n");
  2675. return;
  2676. }
  2677. if (!crtc->state->enable) {
  2678. SDE_DEBUG("crtc%d -> enable %d, skip atomic_flush\n",
  2679. crtc->base.id, crtc->state->enable);
  2680. return;
  2681. }
  2682. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  2683. SDE_ERROR("power resource is not enabled\n");
  2684. return;
  2685. }
  2686. sde_kms = _sde_crtc_get_kms(crtc);
  2687. if (!sde_kms) {
  2688. SDE_ERROR("invalid kms\n");
  2689. return;
  2690. }
  2691. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2692. sde_crtc = to_sde_crtc(crtc);
  2693. cstate = to_sde_crtc_state(crtc->state);
  2694. dev = crtc->dev;
  2695. priv = dev->dev_private;
  2696. if (crtc->index >= ARRAY_SIZE(priv->event_thread)) {
  2697. SDE_ERROR("invalid crtc index[%d]\n", crtc->index);
  2698. return;
  2699. }
  2700. event_thread = &priv->event_thread[crtc->index];
  2701. idle_time = sde_crtc_get_property(cstate, CRTC_PROP_IDLE_TIMEOUT);
  2702. /*
  2703. * If no mixers has been allocated in sde_crtc_atomic_check(),
  2704. * it means we are trying to flush a CRTC whose state is disabled:
  2705. * nothing else needs to be done.
  2706. */
  2707. if (unlikely(!sde_crtc->num_mixers))
  2708. return;
  2709. SDE_ATRACE_BEGIN("sde_crtc_atomic_flush");
  2710. /*
  2711. * For planes without commit update, drm framework will not add
  2712. * those planes to current state since hardware update is not
  2713. * required. However, if those planes were power collapsed since
  2714. * last commit cycle, driver has to restore the hardware state
  2715. * of those planes explicitly here prior to plane flush.
  2716. * Also use this iteration to see if any plane requires cache,
  2717. * so during the perf update driver can activate/deactivate
  2718. * the cache accordingly.
  2719. */
  2720. sde_crtc->new_perf.llcc_active = false;
  2721. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2722. sde_plane_restore(plane);
  2723. if (sde_plane_is_cache_required(plane))
  2724. sde_crtc->new_perf.llcc_active = true;
  2725. }
  2726. /* wait for acquire fences before anything else is done */
  2727. _sde_crtc_wait_for_fences(crtc);
  2728. /* schedule the idle notify delayed work */
  2729. if (idle_time && sde_encoder_check_curr_mode(
  2730. sde_crtc->mixers[0].encoder,
  2731. MSM_DISPLAY_VIDEO_MODE)) {
  2732. kthread_queue_delayed_work(&event_thread->worker,
  2733. &sde_crtc->idle_notify_work,
  2734. msecs_to_jiffies(idle_time));
  2735. SDE_DEBUG("schedule idle notify work in %dms\n", idle_time);
  2736. }
  2737. if (!cstate->rsc_update) {
  2738. drm_for_each_encoder_mask(encoder, dev,
  2739. crtc->state->encoder_mask) {
  2740. cstate->rsc_client =
  2741. sde_encoder_get_rsc_client(encoder);
  2742. }
  2743. cstate->rsc_update = true;
  2744. }
  2745. /* update performance setting before crtc kickoff */
  2746. sde_core_perf_crtc_update(crtc, 1, false);
  2747. /*
  2748. * Final plane updates: Give each plane a chance to complete all
  2749. * required writes/flushing before crtc's "flush
  2750. * everything" call below.
  2751. */
  2752. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2753. if (sde_kms->smmu_state.transition_error)
  2754. sde_plane_set_error(plane, true);
  2755. sde_plane_flush(plane);
  2756. }
  2757. /* Kickoff will be scheduled by outer layer */
  2758. SDE_ATRACE_END("sde_crtc_atomic_flush");
  2759. }
  2760. /**
  2761. * sde_crtc_destroy_state - state destroy hook
  2762. * @crtc: drm CRTC
  2763. * @state: CRTC state object to release
  2764. */
  2765. static void sde_crtc_destroy_state(struct drm_crtc *crtc,
  2766. struct drm_crtc_state *state)
  2767. {
  2768. struct sde_crtc *sde_crtc;
  2769. struct sde_crtc_state *cstate;
  2770. struct drm_encoder *enc;
  2771. struct sde_kms *sde_kms;
  2772. if (!crtc || !state) {
  2773. SDE_ERROR("invalid argument(s)\n");
  2774. return;
  2775. }
  2776. sde_crtc = to_sde_crtc(crtc);
  2777. cstate = to_sde_crtc_state(state);
  2778. sde_kms = _sde_crtc_get_kms(crtc);
  2779. if (!sde_kms) {
  2780. SDE_ERROR("invalid sde_kms\n");
  2781. return;
  2782. }
  2783. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2784. drm_for_each_encoder_mask(enc, crtc->dev, state->encoder_mask)
  2785. sde_rm_release(&sde_kms->rm, enc, true);
  2786. __drm_atomic_helper_crtc_destroy_state(state);
  2787. /* destroy value helper */
  2788. msm_property_destroy_state(&sde_crtc->property_info, cstate,
  2789. &cstate->property_state);
  2790. }
  2791. static int _sde_crtc_flush_event_thread(struct drm_crtc *crtc)
  2792. {
  2793. struct sde_crtc *sde_crtc;
  2794. int i;
  2795. if (!crtc) {
  2796. SDE_ERROR("invalid argument\n");
  2797. return -EINVAL;
  2798. }
  2799. sde_crtc = to_sde_crtc(crtc);
  2800. if (!atomic_read(&sde_crtc->frame_pending)) {
  2801. SDE_DEBUG("no frames pending\n");
  2802. return 0;
  2803. }
  2804. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_ENTRY);
  2805. /*
  2806. * flush all the event thread work to make sure all the
  2807. * FRAME_EVENTS from encoder are propagated to crtc
  2808. */
  2809. for (i = 0; i < ARRAY_SIZE(sde_crtc->frame_events); i++) {
  2810. if (list_empty(&sde_crtc->frame_events[i].list))
  2811. kthread_flush_work(&sde_crtc->frame_events[i].work);
  2812. }
  2813. SDE_EVT32_VERBOSE(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  2814. return 0;
  2815. }
  2816. /**
  2817. * _sde_crtc_remove_pipe_flush - remove staged pipes from flush mask
  2818. * @crtc: Pointer to crtc structure
  2819. */
  2820. static void _sde_crtc_remove_pipe_flush(struct drm_crtc *crtc)
  2821. {
  2822. struct drm_plane *plane;
  2823. struct drm_plane_state *state;
  2824. struct sde_crtc *sde_crtc;
  2825. struct sde_crtc_mixer *mixer;
  2826. struct sde_hw_ctl *ctl;
  2827. if (!crtc)
  2828. return;
  2829. sde_crtc = to_sde_crtc(crtc);
  2830. mixer = sde_crtc->mixers;
  2831. if (!mixer)
  2832. return;
  2833. ctl = mixer->hw_ctl;
  2834. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2835. state = plane->state;
  2836. if (!state)
  2837. continue;
  2838. /* clear plane flush bitmask */
  2839. sde_plane_ctl_flush(plane, ctl, false);
  2840. }
  2841. }
  2842. /**
  2843. * sde_crtc_reset_hw - attempt hardware reset on errors
  2844. * @crtc: Pointer to DRM crtc instance
  2845. * @old_state: Pointer to crtc state for previous commit
  2846. * @recovery_events: Whether or not recovery events are enabled
  2847. * Returns: Zero if current commit should still be attempted
  2848. */
  2849. int sde_crtc_reset_hw(struct drm_crtc *crtc, struct drm_crtc_state *old_state,
  2850. bool recovery_events)
  2851. {
  2852. struct drm_plane *plane_halt[MAX_PLANES];
  2853. struct drm_plane *plane;
  2854. struct drm_encoder *encoder;
  2855. struct sde_crtc *sde_crtc;
  2856. struct sde_crtc_state *cstate;
  2857. struct sde_hw_ctl *ctl;
  2858. signed int i, plane_count;
  2859. int rc;
  2860. if (!crtc || !crtc->dev || !old_state || !crtc->state)
  2861. return -EINVAL;
  2862. sde_crtc = to_sde_crtc(crtc);
  2863. cstate = to_sde_crtc_state(crtc->state);
  2864. SDE_EVT32(DRMID(crtc), recovery_events, SDE_EVTLOG_FUNC_ENTRY);
  2865. /* optionally generate a panic instead of performing a h/w reset */
  2866. SDE_DBG_CTRL("stop_ftrace", "reset_hw_panic");
  2867. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  2868. ctl = sde_crtc->mixers[i].hw_ctl;
  2869. if (!ctl || !ctl->ops.reset)
  2870. continue;
  2871. rc = ctl->ops.reset(ctl);
  2872. if (rc) {
  2873. SDE_DEBUG("crtc%d: ctl%d reset failure\n",
  2874. crtc->base.id, ctl->idx - CTL_0);
  2875. SDE_EVT32(DRMID(crtc), ctl->idx - CTL_0,
  2876. SDE_EVTLOG_ERROR);
  2877. break;
  2878. }
  2879. }
  2880. /* Early out if simple ctl reset succeeded */
  2881. if (i == sde_crtc->num_ctls)
  2882. return 0;
  2883. SDE_DEBUG("crtc%d: issuing hard reset\n", DRMID(crtc));
  2884. /* force all components in the system into reset at the same time */
  2885. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  2886. ctl = sde_crtc->mixers[i].hw_ctl;
  2887. if (!ctl || !ctl->ops.hard_reset)
  2888. continue;
  2889. SDE_EVT32(DRMID(crtc), ctl->idx - CTL_0);
  2890. ctl->ops.hard_reset(ctl, true);
  2891. }
  2892. plane_count = 0;
  2893. drm_atomic_crtc_state_for_each_plane(plane, old_state) {
  2894. if (plane_count >= ARRAY_SIZE(plane_halt))
  2895. break;
  2896. plane_halt[plane_count++] = plane;
  2897. sde_plane_halt_requests(plane, true);
  2898. sde_plane_set_revalidate(plane, true);
  2899. }
  2900. /* provide safe "border color only" commit configuration for later */
  2901. _sde_crtc_remove_pipe_flush(crtc);
  2902. _sde_crtc_blend_setup(crtc, old_state, false);
  2903. /* take h/w components out of reset */
  2904. for (i = plane_count - 1; i >= 0; --i)
  2905. sde_plane_halt_requests(plane_halt[i], false);
  2906. /* attempt to poll for start of frame cycle before reset release */
  2907. list_for_each_entry(encoder,
  2908. &crtc->dev->mode_config.encoder_list, head) {
  2909. if (encoder->crtc != crtc)
  2910. continue;
  2911. if (sde_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
  2912. sde_encoder_poll_line_counts(encoder);
  2913. }
  2914. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  2915. ctl = sde_crtc->mixers[i].hw_ctl;
  2916. if (!ctl || !ctl->ops.hard_reset)
  2917. continue;
  2918. ctl->ops.hard_reset(ctl, false);
  2919. }
  2920. list_for_each_entry(encoder,
  2921. &crtc->dev->mode_config.encoder_list, head) {
  2922. if (encoder->crtc != crtc)
  2923. continue;
  2924. if (sde_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
  2925. sde_encoder_kickoff(encoder, false);
  2926. }
  2927. /* panic the device if VBIF is not in good state */
  2928. return !recovery_events ? 0 : -EAGAIN;
  2929. }
  2930. void sde_crtc_commit_kickoff(struct drm_crtc *crtc,
  2931. struct drm_crtc_state *old_state)
  2932. {
  2933. struct drm_encoder *encoder;
  2934. struct drm_device *dev;
  2935. struct sde_crtc *sde_crtc;
  2936. struct msm_drm_private *priv;
  2937. struct sde_kms *sde_kms;
  2938. struct sde_crtc_state *cstate;
  2939. bool is_error = false, reset_req;
  2940. unsigned long flags;
  2941. enum sde_crtc_idle_pc_state idle_pc_state;
  2942. struct sde_encoder_kickoff_params params = { 0 };
  2943. if (!crtc) {
  2944. SDE_ERROR("invalid argument\n");
  2945. return;
  2946. }
  2947. dev = crtc->dev;
  2948. sde_crtc = to_sde_crtc(crtc);
  2949. sde_kms = _sde_crtc_get_kms(crtc);
  2950. reset_req = false;
  2951. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) {
  2952. SDE_ERROR("invalid argument\n");
  2953. return;
  2954. }
  2955. priv = sde_kms->dev->dev_private;
  2956. cstate = to_sde_crtc_state(crtc->state);
  2957. /*
  2958. * If no mixers has been allocated in sde_crtc_atomic_check(),
  2959. * it means we are trying to start a CRTC whose state is disabled:
  2960. * nothing else needs to be done.
  2961. */
  2962. if (unlikely(!sde_crtc->num_mixers))
  2963. return;
  2964. SDE_ATRACE_BEGIN("crtc_commit");
  2965. idle_pc_state = sde_crtc_get_property(cstate, CRTC_PROP_IDLE_PC_STATE);
  2966. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  2967. if (encoder->crtc != crtc)
  2968. continue;
  2969. /*
  2970. * Encoder will flush/start now, unless it has a tx pending.
  2971. * If so, it may delay and flush at an irq event (e.g. ppdone)
  2972. */
  2973. params.affected_displays = _sde_crtc_get_displays_affected(crtc,
  2974. crtc->state);
  2975. if (sde_encoder_prepare_for_kickoff(encoder, &params))
  2976. reset_req = true;
  2977. if (idle_pc_state != IDLE_PC_NONE)
  2978. sde_encoder_control_idle_pc(encoder,
  2979. (idle_pc_state == IDLE_PC_ENABLE) ? true : false);
  2980. }
  2981. /*
  2982. * Optionally attempt h/w recovery if any errors were detected while
  2983. * preparing for the kickoff
  2984. */
  2985. if (reset_req) {
  2986. sde_crtc->frame_trigger_mode = params.frame_trigger_mode;
  2987. if (sde_crtc->frame_trigger_mode
  2988. != FRAME_DONE_WAIT_POSTED_START &&
  2989. sde_crtc_reset_hw(crtc, old_state,
  2990. params.recovery_events_enabled))
  2991. is_error = true;
  2992. }
  2993. sde_crtc_calc_fps(sde_crtc);
  2994. SDE_ATRACE_BEGIN("flush_event_thread");
  2995. _sde_crtc_flush_event_thread(crtc);
  2996. SDE_ATRACE_END("flush_event_thread");
  2997. sde_crtc->plane_mask_old = crtc->state->plane_mask;
  2998. if (atomic_inc_return(&sde_crtc->frame_pending) == 1) {
  2999. /* acquire bandwidth and other resources */
  3000. SDE_DEBUG("crtc%d first commit\n", crtc->base.id);
  3001. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_CASE1);
  3002. } else {
  3003. SDE_DEBUG("crtc%d commit\n", crtc->base.id);
  3004. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_CASE2);
  3005. }
  3006. sde_crtc->play_count++;
  3007. sde_vbif_clear_errors(sde_kms);
  3008. if (is_error) {
  3009. _sde_crtc_remove_pipe_flush(crtc);
  3010. _sde_crtc_blend_setup(crtc, old_state, false);
  3011. }
  3012. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  3013. if (encoder->crtc != crtc)
  3014. continue;
  3015. sde_encoder_kickoff(encoder, false);
  3016. }
  3017. /* store the event after frame trigger */
  3018. if (sde_crtc->event) {
  3019. WARN_ON(sde_crtc->event);
  3020. } else {
  3021. spin_lock_irqsave(&dev->event_lock, flags);
  3022. sde_crtc->event = crtc->state->event;
  3023. spin_unlock_irqrestore(&dev->event_lock, flags);
  3024. }
  3025. SDE_ATRACE_END("crtc_commit");
  3026. }
  3027. /**
  3028. * _sde_crtc_vblank_enable_no_lock - update power resource and vblank request
  3029. * @sde_crtc: Pointer to sde crtc structure
  3030. * @enable: Whether to enable/disable vblanks
  3031. *
  3032. * @Return: error code
  3033. */
  3034. static int _sde_crtc_vblank_enable_no_lock(
  3035. struct sde_crtc *sde_crtc, bool enable)
  3036. {
  3037. struct drm_crtc *crtc;
  3038. struct drm_encoder *enc;
  3039. if (!sde_crtc) {
  3040. SDE_ERROR("invalid crtc\n");
  3041. return -EINVAL;
  3042. }
  3043. crtc = &sde_crtc->base;
  3044. if (enable) {
  3045. int ret;
  3046. /* drop lock since power crtc cb may try to re-acquire lock */
  3047. mutex_unlock(&sde_crtc->crtc_lock);
  3048. ret = pm_runtime_get_sync(crtc->dev->dev);
  3049. mutex_lock(&sde_crtc->crtc_lock);
  3050. if (ret < 0)
  3051. return ret;
  3052. drm_for_each_encoder_mask(enc, crtc->dev,
  3053. crtc->state->encoder_mask) {
  3054. if (enc->crtc != crtc)
  3055. continue;
  3056. SDE_EVT32(DRMID(&sde_crtc->base), DRMID(enc), enable,
  3057. sde_crtc->enabled);
  3058. sde_encoder_register_vblank_callback(enc,
  3059. sde_crtc_vblank_cb, (void *)crtc);
  3060. }
  3061. } else {
  3062. drm_for_each_encoder_mask(enc, crtc->dev,
  3063. crtc->state->encoder_mask) {
  3064. if (enc->crtc != crtc)
  3065. continue;
  3066. SDE_EVT32(DRMID(&sde_crtc->base), DRMID(enc), enable,
  3067. sde_crtc->enabled);
  3068. sde_encoder_register_vblank_callback(enc, NULL, NULL);
  3069. }
  3070. /* drop lock since power crtc cb may try to re-acquire lock */
  3071. mutex_unlock(&sde_crtc->crtc_lock);
  3072. pm_runtime_put_sync(crtc->dev->dev);
  3073. mutex_lock(&sde_crtc->crtc_lock);
  3074. }
  3075. return 0;
  3076. }
  3077. /**
  3078. * sde_crtc_duplicate_state - state duplicate hook
  3079. * @crtc: Pointer to drm crtc structure
  3080. * @Returns: Pointer to new drm_crtc_state structure
  3081. */
  3082. static struct drm_crtc_state *sde_crtc_duplicate_state(struct drm_crtc *crtc)
  3083. {
  3084. struct sde_crtc *sde_crtc;
  3085. struct sde_crtc_state *cstate, *old_cstate;
  3086. if (!crtc || !crtc->state) {
  3087. SDE_ERROR("invalid argument(s)\n");
  3088. return NULL;
  3089. }
  3090. sde_crtc = to_sde_crtc(crtc);
  3091. old_cstate = to_sde_crtc_state(crtc->state);
  3092. cstate = msm_property_alloc_state(&sde_crtc->property_info);
  3093. if (!cstate) {
  3094. SDE_ERROR("failed to allocate state\n");
  3095. return NULL;
  3096. }
  3097. /* duplicate value helper */
  3098. msm_property_duplicate_state(&sde_crtc->property_info,
  3099. old_cstate, cstate,
  3100. &cstate->property_state, cstate->property_values);
  3101. /* clear destination scaler dirty bit */
  3102. cstate->ds_dirty = false;
  3103. /* duplicate base helper */
  3104. __drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base);
  3105. return &cstate->base;
  3106. }
  3107. /**
  3108. * sde_crtc_reset - reset hook for CRTCs
  3109. * Resets the atomic state for @crtc by freeing the state pointer (which might
  3110. * be NULL, e.g. at driver load time) and allocating a new empty state object.
  3111. * @crtc: Pointer to drm crtc structure
  3112. */
  3113. static void sde_crtc_reset(struct drm_crtc *crtc)
  3114. {
  3115. struct sde_crtc *sde_crtc;
  3116. struct sde_crtc_state *cstate;
  3117. if (!crtc) {
  3118. SDE_ERROR("invalid crtc\n");
  3119. return;
  3120. }
  3121. /* revert suspend actions, if necessary */
  3122. if (!sde_crtc_is_reset_required(crtc)) {
  3123. SDE_DEBUG("avoiding reset for crtc:%d\n", crtc->base.id);
  3124. return;
  3125. }
  3126. /* remove previous state, if present */
  3127. if (crtc->state) {
  3128. sde_crtc_destroy_state(crtc, crtc->state);
  3129. crtc->state = 0;
  3130. }
  3131. sde_crtc = to_sde_crtc(crtc);
  3132. cstate = msm_property_alloc_state(&sde_crtc->property_info);
  3133. if (!cstate) {
  3134. SDE_ERROR("failed to allocate state\n");
  3135. return;
  3136. }
  3137. /* reset value helper */
  3138. msm_property_reset_state(&sde_crtc->property_info, cstate,
  3139. &cstate->property_state,
  3140. cstate->property_values);
  3141. _sde_crtc_set_input_fence_timeout(cstate);
  3142. cstate->base.crtc = crtc;
  3143. crtc->state = &cstate->base;
  3144. }
  3145. static void sde_crtc_handle_power_event(u32 event_type, void *arg)
  3146. {
  3147. struct drm_crtc *crtc = arg;
  3148. struct sde_crtc *sde_crtc;
  3149. struct sde_crtc_state *cstate;
  3150. struct drm_plane *plane;
  3151. struct drm_encoder *encoder;
  3152. u32 power_on;
  3153. unsigned long flags;
  3154. struct sde_crtc_irq_info *node = NULL;
  3155. int ret = 0;
  3156. struct drm_event event;
  3157. if (!crtc) {
  3158. SDE_ERROR("invalid crtc\n");
  3159. return;
  3160. }
  3161. sde_crtc = to_sde_crtc(crtc);
  3162. cstate = to_sde_crtc_state(crtc->state);
  3163. mutex_lock(&sde_crtc->crtc_lock);
  3164. SDE_EVT32(DRMID(crtc), event_type);
  3165. switch (event_type) {
  3166. case SDE_POWER_EVENT_POST_ENABLE:
  3167. /* restore encoder; crtc will be programmed during commit */
  3168. drm_for_each_encoder_mask(encoder, crtc->dev,
  3169. crtc->state->encoder_mask) {
  3170. sde_encoder_virt_restore(encoder);
  3171. }
  3172. /* restore UIDLE */
  3173. sde_core_perf_crtc_update_uidle(crtc, true);
  3174. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3175. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3176. ret = 0;
  3177. if (node->func)
  3178. ret = node->func(crtc, true, &node->irq);
  3179. if (ret)
  3180. SDE_ERROR("%s failed to enable event %x\n",
  3181. sde_crtc->name, node->event);
  3182. }
  3183. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3184. sde_cp_crtc_post_ipc(crtc);
  3185. break;
  3186. case SDE_POWER_EVENT_PRE_DISABLE:
  3187. drm_for_each_encoder_mask(encoder, crtc->dev,
  3188. crtc->state->encoder_mask) {
  3189. /*
  3190. * disable the vsync source after updating the
  3191. * rsc state. rsc state update might have vsync wait
  3192. * and vsync source must be disabled after it.
  3193. * It will avoid generating any vsync from this point
  3194. * till mode-2 entry. It is SW workaround for HW
  3195. * limitation and should not be removed without
  3196. * checking the updated design.
  3197. */
  3198. sde_encoder_control_te(encoder, false);
  3199. }
  3200. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3201. node = NULL;
  3202. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3203. ret = 0;
  3204. if (node->func)
  3205. ret = node->func(crtc, false, &node->irq);
  3206. if (ret)
  3207. SDE_ERROR("%s failed to disable event %x\n",
  3208. sde_crtc->name, node->event);
  3209. }
  3210. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3211. sde_cp_crtc_pre_ipc(crtc);
  3212. break;
  3213. case SDE_POWER_EVENT_POST_DISABLE:
  3214. /*
  3215. * set revalidate flag in planes, so it will be re-programmed
  3216. * in the next frame update
  3217. */
  3218. drm_atomic_crtc_for_each_plane(plane, crtc)
  3219. sde_plane_set_revalidate(plane, true);
  3220. sde_cp_crtc_suspend(crtc);
  3221. /**
  3222. * destination scaler if enabled should be reconfigured
  3223. * in the next frame update
  3224. */
  3225. if (cstate->num_ds_enabled)
  3226. sde_crtc->ds_reconfig = true;
  3227. event.type = DRM_EVENT_SDE_POWER;
  3228. event.length = sizeof(power_on);
  3229. power_on = 0;
  3230. msm_mode_object_event_notify(&crtc->base, crtc->dev, &event,
  3231. (u8 *)&power_on);
  3232. break;
  3233. default:
  3234. SDE_DEBUG("event:%d not handled\n", event_type);
  3235. break;
  3236. }
  3237. mutex_unlock(&sde_crtc->crtc_lock);
  3238. }
  3239. static void sde_crtc_disable(struct drm_crtc *crtc)
  3240. {
  3241. struct sde_kms *sde_kms;
  3242. struct sde_crtc *sde_crtc;
  3243. struct sde_crtc_state *cstate;
  3244. struct drm_encoder *encoder;
  3245. struct msm_drm_private *priv;
  3246. unsigned long flags;
  3247. struct sde_crtc_irq_info *node = NULL;
  3248. struct drm_event event;
  3249. u32 power_on;
  3250. bool in_cont_splash = false;
  3251. int ret, i;
  3252. if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) {
  3253. SDE_ERROR("invalid crtc\n");
  3254. return;
  3255. }
  3256. sde_kms = _sde_crtc_get_kms(crtc);
  3257. if (!sde_kms) {
  3258. SDE_ERROR("invalid kms\n");
  3259. return;
  3260. }
  3261. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  3262. SDE_ERROR("power resource is not enabled\n");
  3263. return;
  3264. }
  3265. sde_crtc = to_sde_crtc(crtc);
  3266. cstate = to_sde_crtc_state(crtc->state);
  3267. priv = crtc->dev->dev_private;
  3268. SDE_DEBUG("crtc%d\n", crtc->base.id);
  3269. drm_crtc_vblank_off(crtc);
  3270. mutex_lock(&sde_crtc->crtc_lock);
  3271. SDE_EVT32_VERBOSE(DRMID(crtc));
  3272. /* update color processing on suspend */
  3273. event.type = DRM_EVENT_CRTC_POWER;
  3274. event.length = sizeof(u32);
  3275. sde_cp_crtc_suspend(crtc);
  3276. power_on = 0;
  3277. msm_mode_object_event_notify(&crtc->base, crtc->dev, &event,
  3278. (u8 *)&power_on);
  3279. /* destination scaler if enabled should be reconfigured on resume */
  3280. if (cstate->num_ds_enabled)
  3281. sde_crtc->ds_reconfig = true;
  3282. _sde_crtc_flush_event_thread(crtc);
  3283. SDE_EVT32(DRMID(crtc), sde_crtc->enabled,
  3284. crtc->state->active, crtc->state->enable);
  3285. sde_crtc->enabled = false;
  3286. /* Try to disable uidle */
  3287. sde_core_perf_crtc_update_uidle(crtc, false);
  3288. if (atomic_read(&sde_crtc->frame_pending)) {
  3289. SDE_ERROR("crtc%d frame_pending%d\n", crtc->base.id,
  3290. atomic_read(&sde_crtc->frame_pending));
  3291. SDE_EVT32(DRMID(crtc), atomic_read(&sde_crtc->frame_pending),
  3292. SDE_EVTLOG_FUNC_CASE2);
  3293. sde_core_perf_crtc_release_bw(crtc);
  3294. atomic_set(&sde_crtc->frame_pending, 0);
  3295. }
  3296. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3297. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3298. ret = 0;
  3299. if (node->func)
  3300. ret = node->func(crtc, false, &node->irq);
  3301. if (ret)
  3302. SDE_ERROR("%s failed to disable event %x\n",
  3303. sde_crtc->name, node->event);
  3304. }
  3305. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3306. drm_for_each_encoder_mask(encoder, crtc->dev,
  3307. crtc->state->encoder_mask) {
  3308. if (sde_encoder_in_cont_splash(encoder)) {
  3309. in_cont_splash = true;
  3310. break;
  3311. }
  3312. }
  3313. /* avoid clk/bw downvote if cont-splash is enabled */
  3314. if (!in_cont_splash)
  3315. sde_core_perf_crtc_update(crtc, 0, true);
  3316. drm_for_each_encoder_mask(encoder, crtc->dev,
  3317. crtc->state->encoder_mask) {
  3318. sde_encoder_register_frame_event_callback(encoder, NULL, NULL);
  3319. cstate->rsc_client = NULL;
  3320. cstate->rsc_update = false;
  3321. /*
  3322. * reset idle power-collapse to original state during suspend;
  3323. * user-mode will change the state on resume, if required
  3324. */
  3325. if (sde_kms->catalog->has_idle_pc)
  3326. sde_encoder_control_idle_pc(encoder, true);
  3327. }
  3328. if (sde_crtc->power_event)
  3329. sde_power_handle_unregister_event(&priv->phandle,
  3330. sde_crtc->power_event);
  3331. /**
  3332. * All callbacks are unregistered and frame done waits are complete
  3333. * at this point. No buffers are accessed by hardware.
  3334. * reset the fence timeline if crtc will not be enabled for this commit
  3335. */
  3336. if (!crtc->state->active || !crtc->state->enable) {
  3337. sde_fence_signal(sde_crtc->output_fence,
  3338. ktime_get(), SDE_FENCE_RESET_TIMELINE);
  3339. for (i = 0; i < cstate->num_connectors; ++i)
  3340. sde_connector_commit_reset(cstate->connectors[i],
  3341. ktime_get());
  3342. }
  3343. memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers));
  3344. sde_crtc->num_mixers = 0;
  3345. sde_crtc->mixers_swapped = false;
  3346. /* disable clk & bw control until clk & bw properties are set */
  3347. cstate->bw_control = false;
  3348. cstate->bw_split_vote = false;
  3349. mutex_unlock(&sde_crtc->crtc_lock);
  3350. }
  3351. static void sde_crtc_enable(struct drm_crtc *crtc,
  3352. struct drm_crtc_state *old_crtc_state)
  3353. {
  3354. struct sde_crtc *sde_crtc;
  3355. struct drm_encoder *encoder;
  3356. struct msm_drm_private *priv;
  3357. unsigned long flags;
  3358. struct sde_crtc_irq_info *node = NULL;
  3359. struct drm_event event;
  3360. u32 power_on;
  3361. int ret, i;
  3362. struct sde_crtc_state *cstate;
  3363. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  3364. SDE_ERROR("invalid crtc\n");
  3365. return;
  3366. }
  3367. priv = crtc->dev->dev_private;
  3368. cstate = to_sde_crtc_state(crtc->state);
  3369. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  3370. SDE_ERROR("power resource is not enabled\n");
  3371. return;
  3372. }
  3373. SDE_DEBUG("crtc%d\n", crtc->base.id);
  3374. SDE_EVT32_VERBOSE(DRMID(crtc));
  3375. sde_crtc = to_sde_crtc(crtc);
  3376. drm_crtc_vblank_on(crtc);
  3377. mutex_lock(&sde_crtc->crtc_lock);
  3378. SDE_EVT32(DRMID(crtc), sde_crtc->enabled);
  3379. /*
  3380. * Try to enable uidle (if possible), we do this before the call
  3381. * to return early during seamless dms mode, so any fps
  3382. * change is also consider to enable/disable UIDLE
  3383. */
  3384. sde_core_perf_crtc_update_uidle(crtc, true);
  3385. /* return early if crtc is already enabled, do this after UIDLE check */
  3386. if (sde_crtc->enabled) {
  3387. if (msm_is_mode_seamless_dms(&crtc->state->adjusted_mode) ||
  3388. msm_is_mode_seamless_dyn_clk(&crtc->state->adjusted_mode))
  3389. SDE_DEBUG("%s extra crtc enable expected during DMS\n",
  3390. sde_crtc->name);
  3391. else
  3392. WARN(1, "%s unexpected crtc enable\n", sde_crtc->name);
  3393. mutex_unlock(&sde_crtc->crtc_lock);
  3394. return;
  3395. }
  3396. drm_for_each_encoder_mask(encoder, crtc->dev,
  3397. crtc->state->encoder_mask) {
  3398. sde_encoder_register_frame_event_callback(encoder,
  3399. sde_crtc_frame_event_cb, crtc);
  3400. }
  3401. sde_crtc->enabled = true;
  3402. /* update color processing on resume */
  3403. event.type = DRM_EVENT_CRTC_POWER;
  3404. event.length = sizeof(u32);
  3405. sde_cp_crtc_resume(crtc);
  3406. power_on = 1;
  3407. msm_mode_object_event_notify(&crtc->base, crtc->dev, &event,
  3408. (u8 *)&power_on);
  3409. mutex_unlock(&sde_crtc->crtc_lock);
  3410. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3411. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3412. ret = 0;
  3413. if (node->func)
  3414. ret = node->func(crtc, true, &node->irq);
  3415. if (ret)
  3416. SDE_ERROR("%s failed to enable event %x\n",
  3417. sde_crtc->name, node->event);
  3418. }
  3419. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3420. sde_crtc->power_event = sde_power_handle_register_event(
  3421. &priv->phandle,
  3422. SDE_POWER_EVENT_POST_ENABLE | SDE_POWER_EVENT_POST_DISABLE |
  3423. SDE_POWER_EVENT_PRE_DISABLE,
  3424. sde_crtc_handle_power_event, crtc, sde_crtc->name);
  3425. /* Enable ESD thread */
  3426. for (i = 0; i < cstate->num_connectors; i++)
  3427. sde_connector_schedule_status_work(cstate->connectors[i], true);
  3428. }
  3429. /* no input validation - caller API has all the checks */
  3430. static int _sde_crtc_excl_dim_layer_check(struct drm_crtc_state *state,
  3431. struct plane_state pstates[], int cnt)
  3432. {
  3433. struct sde_crtc_state *cstate = to_sde_crtc_state(state);
  3434. struct drm_display_mode *mode = &state->adjusted_mode;
  3435. const struct drm_plane_state *pstate;
  3436. struct sde_plane_state *sde_pstate;
  3437. int rc = 0, i;
  3438. /* Check dim layer rect bounds and stage */
  3439. for (i = 0; i < cstate->num_dim_layers; i++) {
  3440. if ((CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.y,
  3441. cstate->dim_layer[i].rect.h, mode->vdisplay)) ||
  3442. (CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.x,
  3443. cstate->dim_layer[i].rect.w, mode->hdisplay)) ||
  3444. (cstate->dim_layer[i].stage >= SDE_STAGE_MAX) ||
  3445. (!cstate->dim_layer[i].rect.w) ||
  3446. (!cstate->dim_layer[i].rect.h)) {
  3447. SDE_ERROR("invalid dim_layer:{%d,%d,%d,%d}, stage:%d\n",
  3448. cstate->dim_layer[i].rect.x,
  3449. cstate->dim_layer[i].rect.y,
  3450. cstate->dim_layer[i].rect.w,
  3451. cstate->dim_layer[i].rect.h,
  3452. cstate->dim_layer[i].stage);
  3453. SDE_ERROR("display: %dx%d\n", mode->hdisplay,
  3454. mode->vdisplay);
  3455. rc = -E2BIG;
  3456. goto end;
  3457. }
  3458. }
  3459. /* log all src and excl_rect, useful for debugging */
  3460. for (i = 0; i < cnt; i++) {
  3461. pstate = pstates[i].drm_pstate;
  3462. sde_pstate = to_sde_plane_state(pstate);
  3463. SDE_DEBUG("p %d z %d src{%d,%d,%d,%d} excl_rect{%d,%d,%d,%d}\n",
  3464. pstate->plane->base.id, pstates[i].stage,
  3465. pstate->crtc_x, pstate->crtc_y,
  3466. pstate->crtc_w, pstate->crtc_h,
  3467. sde_pstate->excl_rect.x, sde_pstate->excl_rect.y,
  3468. sde_pstate->excl_rect.w, sde_pstate->excl_rect.h);
  3469. }
  3470. end:
  3471. return rc;
  3472. }
  3473. static int _sde_crtc_check_secure_blend_config(struct drm_crtc *crtc,
  3474. struct drm_crtc_state *state, struct plane_state pstates[],
  3475. struct sde_crtc_state *cstate, struct sde_kms *sde_kms,
  3476. int cnt, int secure, int fb_ns, int fb_sec, int fb_sec_dir)
  3477. {
  3478. struct drm_plane *plane;
  3479. int i;
  3480. if (secure == SDE_DRM_SEC_ONLY) {
  3481. /*
  3482. * validate planes - only fb_sec_dir is allowed during sec_crtc
  3483. * - fb_sec_dir is for secure camera preview and
  3484. * secure display use case
  3485. * - fb_sec is for secure video playback
  3486. * - fb_ns is for normal non secure use cases
  3487. */
  3488. if (fb_ns || fb_sec) {
  3489. SDE_ERROR(
  3490. "crtc%d: invalid fb_modes Sec:%d, NS:%d, Sec_Dir:%d\n",
  3491. DRMID(crtc), fb_sec, fb_ns, fb_sec_dir);
  3492. return -EINVAL;
  3493. }
  3494. /*
  3495. * - only one blending stage is allowed in sec_crtc
  3496. * - validate if pipe is allowed for sec-ui updates
  3497. */
  3498. for (i = 1; i < cnt; i++) {
  3499. if (!pstates[i].drm_pstate
  3500. || !pstates[i].drm_pstate->plane) {
  3501. SDE_ERROR("crtc%d: invalid pstate at i:%d\n",
  3502. DRMID(crtc), i);
  3503. return -EINVAL;
  3504. }
  3505. plane = pstates[i].drm_pstate->plane;
  3506. if (!sde_plane_is_sec_ui_allowed(plane)) {
  3507. SDE_ERROR("crtc%d: sec-ui not allowed in p%d\n",
  3508. DRMID(crtc), plane->base.id);
  3509. return -EINVAL;
  3510. } else if (pstates[i].stage != pstates[i-1].stage) {
  3511. SDE_ERROR(
  3512. "crtc%d: invalid blend stages %d:%d, %d:%d\n",
  3513. DRMID(crtc), i, pstates[i].stage,
  3514. i-1, pstates[i-1].stage);
  3515. return -EINVAL;
  3516. }
  3517. }
  3518. /* check if all the dim_layers are in the same stage */
  3519. for (i = 1; i < cstate->num_dim_layers; i++) {
  3520. if (cstate->dim_layer[i].stage !=
  3521. cstate->dim_layer[i-1].stage) {
  3522. SDE_ERROR(
  3523. "crtc%d: invalid dimlayer stage %d:%d, %d:%d\n",
  3524. DRMID(crtc),
  3525. i, cstate->dim_layer[i].stage,
  3526. i-1, cstate->dim_layer[i-1].stage);
  3527. return -EINVAL;
  3528. }
  3529. }
  3530. /*
  3531. * if secure-ui supported blendstage is specified,
  3532. * - fail empty commit
  3533. * - validate dim_layer or plane is staged in the supported
  3534. * blendstage
  3535. */
  3536. if (sde_kms->catalog->sui_supported_blendstage) {
  3537. int sec_stage = cnt ? pstates[0].sde_pstate->stage :
  3538. cstate->dim_layer[0].stage;
  3539. if ((!cnt && !cstate->num_dim_layers) ||
  3540. (sde_kms->catalog->sui_supported_blendstage
  3541. != (sec_stage - SDE_STAGE_0))) {
  3542. SDE_ERROR(
  3543. "crtc%d: empty cnt%d/dim%d or bad stage%d\n",
  3544. DRMID(crtc), cnt,
  3545. cstate->num_dim_layers, sec_stage);
  3546. return -EINVAL;
  3547. }
  3548. }
  3549. }
  3550. return 0;
  3551. }
  3552. static int _sde_crtc_check_secure_single_encoder(struct drm_crtc *crtc,
  3553. struct drm_crtc_state *state, int fb_sec_dir)
  3554. {
  3555. struct drm_encoder *encoder;
  3556. int encoder_cnt = 0;
  3557. if (fb_sec_dir) {
  3558. drm_for_each_encoder_mask(encoder, crtc->dev,
  3559. state->encoder_mask)
  3560. encoder_cnt++;
  3561. if (encoder_cnt > MAX_ALLOWED_ENCODER_CNT_PER_SECURE_CRTC) {
  3562. SDE_ERROR("crtc:%d invalid number of encoders:%d\n",
  3563. DRMID(crtc), encoder_cnt);
  3564. return -EINVAL;
  3565. }
  3566. }
  3567. return 0;
  3568. }
  3569. static int _sde_crtc_check_secure_state_smmu_translation(struct drm_crtc *crtc,
  3570. struct drm_crtc_state *state, struct sde_kms *sde_kms, int secure,
  3571. int fb_ns, int fb_sec, int fb_sec_dir)
  3572. {
  3573. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  3574. struct drm_encoder *encoder;
  3575. int is_video_mode = false;
  3576. drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) {
  3577. if (sde_encoder_is_dsi_display(encoder))
  3578. is_video_mode |= sde_encoder_check_curr_mode(encoder,
  3579. MSM_DISPLAY_VIDEO_MODE);
  3580. }
  3581. /*
  3582. * In video mode check for null commit before transition
  3583. * from secure to non secure and vice versa
  3584. */
  3585. if (is_video_mode && smmu_state &&
  3586. state->plane_mask && crtc->state->plane_mask &&
  3587. ((fb_sec_dir && ((smmu_state->state == ATTACHED) &&
  3588. (secure == SDE_DRM_SEC_ONLY))) ||
  3589. (fb_ns && ((smmu_state->state == DETACHED) ||
  3590. (smmu_state->state == DETACH_ALL_REQ))) ||
  3591. (fb_ns && ((smmu_state->state == DETACHED_SEC) ||
  3592. (smmu_state->state == DETACH_SEC_REQ)) &&
  3593. (smmu_state->secure_level == SDE_DRM_SEC_ONLY)))) {
  3594. SDE_EVT32(DRMID(crtc), fb_ns, fb_sec_dir,
  3595. smmu_state->state, smmu_state->secure_level,
  3596. secure, crtc->state->plane_mask, state->plane_mask);
  3597. SDE_ERROR(
  3598. "crtc%d Invalid transition;sec%d state%d slvl%d ns%d sdir%d\n",
  3599. DRMID(crtc), secure, smmu_state->state,
  3600. smmu_state->secure_level, fb_ns, fb_sec_dir);
  3601. return -EINVAL;
  3602. }
  3603. return 0;
  3604. }
  3605. static int _sde_crtc_check_secure_state(struct drm_crtc *crtc,
  3606. struct drm_crtc_state *state, struct plane_state pstates[],
  3607. int cnt)
  3608. {
  3609. struct sde_crtc_state *cstate;
  3610. struct sde_kms *sde_kms;
  3611. uint32_t secure;
  3612. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  3613. int rc;
  3614. if (!crtc || !state) {
  3615. SDE_ERROR("invalid arguments\n");
  3616. return -EINVAL;
  3617. }
  3618. sde_kms = _sde_crtc_get_kms(crtc);
  3619. if (!sde_kms || !sde_kms->catalog) {
  3620. SDE_ERROR("invalid kms\n");
  3621. return -EINVAL;
  3622. }
  3623. cstate = to_sde_crtc_state(state);
  3624. secure = sde_crtc_get_property(cstate, CRTC_PROP_SECURITY_LEVEL);
  3625. rc = sde_crtc_state_find_plane_fb_modes(state, &fb_ns,
  3626. &fb_sec, &fb_sec_dir);
  3627. if (rc)
  3628. return rc;
  3629. rc = _sde_crtc_check_secure_blend_config(crtc, state, pstates, cstate,
  3630. sde_kms, cnt, secure, fb_ns, fb_sec, fb_sec_dir);
  3631. if (rc)
  3632. return rc;
  3633. /*
  3634. * secure_crtc is not allowed in a shared toppolgy
  3635. * across different encoders.
  3636. */
  3637. rc = _sde_crtc_check_secure_single_encoder(crtc, state, fb_sec_dir);
  3638. if (rc)
  3639. return rc;
  3640. rc = _sde_crtc_check_secure_state_smmu_translation(crtc, state, sde_kms,
  3641. secure, fb_ns, fb_sec, fb_sec_dir);
  3642. if (rc)
  3643. return rc;
  3644. SDE_DEBUG("crtc:%d Secure validation successful\n", DRMID(crtc));
  3645. return 0;
  3646. }
  3647. static int _sde_crtc_check_get_pstates(struct drm_crtc *crtc,
  3648. struct drm_crtc_state *state,
  3649. struct drm_display_mode *mode,
  3650. struct plane_state *pstates,
  3651. struct drm_plane *plane,
  3652. struct sde_multirect_plane_states *multirect_plane,
  3653. int *cnt)
  3654. {
  3655. struct sde_crtc *sde_crtc;
  3656. struct sde_crtc_state *cstate;
  3657. const struct drm_plane_state *pstate;
  3658. const struct drm_plane_state *pipe_staged[SSPP_MAX];
  3659. int rc = 0, multirect_count = 0, i, mixer_width, mixer_height;
  3660. sde_crtc = to_sde_crtc(crtc);
  3661. cstate = to_sde_crtc_state(state);
  3662. memset(pipe_staged, 0, sizeof(pipe_staged));
  3663. mixer_width = sde_crtc_get_mixer_width(sde_crtc, cstate, mode);
  3664. mixer_height = sde_crtc_get_mixer_height(sde_crtc, cstate, mode);
  3665. if (cstate->num_ds_enabled)
  3666. mixer_width = mixer_width * cstate->num_ds_enabled;
  3667. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  3668. if (IS_ERR_OR_NULL(pstate)) {
  3669. rc = PTR_ERR(pstate);
  3670. SDE_ERROR("%s: failed to get plane%d state, %d\n",
  3671. sde_crtc->name, plane->base.id, rc);
  3672. return rc;
  3673. }
  3674. if (*cnt >= SDE_PSTATES_MAX)
  3675. continue;
  3676. pstates[*cnt].sde_pstate = to_sde_plane_state(pstate);
  3677. pstates[*cnt].drm_pstate = pstate;
  3678. pstates[*cnt].stage = sde_plane_get_property(
  3679. pstates[*cnt].sde_pstate, PLANE_PROP_ZPOS);
  3680. pstates[*cnt].pipe_id = sde_plane_pipe(plane);
  3681. /* check dim layer stage with every plane */
  3682. for (i = 0; i < cstate->num_dim_layers; i++) {
  3683. if (cstate->dim_layer[i].stage ==
  3684. (pstates[*cnt].stage + SDE_STAGE_0)) {
  3685. SDE_ERROR(
  3686. "plane:%d/dim_layer:%i-same stage:%d\n",
  3687. plane->base.id, i,
  3688. cstate->dim_layer[i].stage);
  3689. return -EINVAL;
  3690. }
  3691. }
  3692. if (pipe_staged[pstates[*cnt].pipe_id]) {
  3693. multirect_plane[multirect_count].r0 =
  3694. pipe_staged[pstates[*cnt].pipe_id];
  3695. multirect_plane[multirect_count].r1 = pstate;
  3696. multirect_count++;
  3697. pipe_staged[pstates[*cnt].pipe_id] = NULL;
  3698. } else {
  3699. pipe_staged[pstates[*cnt].pipe_id] = pstate;
  3700. }
  3701. (*cnt)++;
  3702. if (CHECK_LAYER_BOUNDS(pstate->crtc_y, pstate->crtc_h,
  3703. mode->vdisplay) ||
  3704. CHECK_LAYER_BOUNDS(pstate->crtc_x, pstate->crtc_w,
  3705. mode->hdisplay)) {
  3706. SDE_ERROR("invalid vertical/horizontal destination\n");
  3707. SDE_ERROR("y:%d h:%d vdisp:%d x:%d w:%d hdisp:%d\n",
  3708. pstate->crtc_y, pstate->crtc_h, mode->vdisplay,
  3709. pstate->crtc_x, pstate->crtc_w, mode->hdisplay);
  3710. return -E2BIG;
  3711. }
  3712. if (cstate->num_ds_enabled &&
  3713. ((pstate->crtc_h > mixer_height) ||
  3714. (pstate->crtc_w > mixer_width))) {
  3715. SDE_ERROR("plane w/h:%x*%x > mixer w/h:%x*%x\n",
  3716. pstate->crtc_w, pstate->crtc_h,
  3717. mixer_width, mixer_height);
  3718. return -E2BIG;
  3719. }
  3720. }
  3721. for (i = 1; i < SSPP_MAX; i++) {
  3722. if (pipe_staged[i]) {
  3723. if (is_sde_plane_virtual(pipe_staged[i]->plane)) {
  3724. SDE_ERROR(
  3725. "r1 only virt plane:%d not supported\n",
  3726. pipe_staged[i]->plane->base.id);
  3727. return -EINVAL;
  3728. }
  3729. sde_plane_clear_multirect(pipe_staged[i]);
  3730. }
  3731. }
  3732. for (i = 0; i < multirect_count; i++) {
  3733. if (sde_plane_validate_multirect_v2(&multirect_plane[i])) {
  3734. SDE_ERROR(
  3735. "multirect validation failed for planes (%d - %d)\n",
  3736. multirect_plane[i].r0->plane->base.id,
  3737. multirect_plane[i].r1->plane->base.id);
  3738. return -EINVAL;
  3739. }
  3740. }
  3741. return rc;
  3742. }
  3743. static int _sde_crtc_check_zpos(struct drm_crtc_state *state,
  3744. struct sde_crtc *sde_crtc,
  3745. struct plane_state *pstates,
  3746. struct sde_crtc_state *cstate,
  3747. struct drm_display_mode *mode,
  3748. int cnt)
  3749. {
  3750. int rc = 0, i, z_pos;
  3751. u32 zpos_cnt = 0;
  3752. sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
  3753. rc = _sde_crtc_excl_dim_layer_check(state, pstates, cnt);
  3754. if (rc)
  3755. return rc;
  3756. if (!sde_is_custom_client()) {
  3757. int stage_old = pstates[0].stage;
  3758. z_pos = 0;
  3759. for (i = 0; i < cnt; i++) {
  3760. if (stage_old != pstates[i].stage)
  3761. ++z_pos;
  3762. stage_old = pstates[i].stage;
  3763. pstates[i].stage = z_pos;
  3764. }
  3765. }
  3766. z_pos = -1;
  3767. for (i = 0; i < cnt; i++) {
  3768. /* reset counts at every new blend stage */
  3769. if (pstates[i].stage != z_pos) {
  3770. zpos_cnt = 0;
  3771. z_pos = pstates[i].stage;
  3772. }
  3773. /* verify z_pos setting before using it */
  3774. if (z_pos >= SDE_STAGE_MAX - SDE_STAGE_0) {
  3775. SDE_ERROR("> %d plane stages assigned\n",
  3776. SDE_STAGE_MAX - SDE_STAGE_0);
  3777. return -EINVAL;
  3778. } else if (zpos_cnt == 2) {
  3779. SDE_ERROR("> 2 planes @ stage %d\n", z_pos);
  3780. return -EINVAL;
  3781. } else {
  3782. zpos_cnt++;
  3783. }
  3784. pstates[i].sde_pstate->stage = z_pos + SDE_STAGE_0;
  3785. SDE_DEBUG("%s: zpos %d", sde_crtc->name, z_pos);
  3786. }
  3787. return rc;
  3788. }
  3789. static int _sde_crtc_atomic_check_pstates(struct drm_crtc *crtc,
  3790. struct drm_crtc_state *state,
  3791. struct plane_state *pstates,
  3792. struct sde_multirect_plane_states *multirect_plane)
  3793. {
  3794. struct sde_crtc *sde_crtc;
  3795. struct sde_crtc_state *cstate;
  3796. struct sde_kms *kms;
  3797. struct drm_plane *plane = NULL;
  3798. struct drm_display_mode *mode;
  3799. int rc = 0, cnt = 0;
  3800. kms = _sde_crtc_get_kms(crtc);
  3801. if (!kms || !kms->catalog) {
  3802. SDE_ERROR("invalid parameters\n");
  3803. return -EINVAL;
  3804. }
  3805. sde_crtc = to_sde_crtc(crtc);
  3806. cstate = to_sde_crtc_state(state);
  3807. mode = &state->adjusted_mode;
  3808. /* get plane state for all drm planes associated with crtc state */
  3809. rc = _sde_crtc_check_get_pstates(crtc, state, mode, pstates,
  3810. plane, multirect_plane, &cnt);
  3811. if (rc)
  3812. return rc;
  3813. /* assign mixer stages based on sorted zpos property */
  3814. rc = _sde_crtc_check_zpos(state, sde_crtc, pstates, cstate, mode, cnt);
  3815. if (rc)
  3816. return rc;
  3817. rc = _sde_crtc_check_secure_state(crtc, state, pstates, cnt);
  3818. if (rc)
  3819. return rc;
  3820. /*
  3821. * validate and set source split:
  3822. * use pstates sorted by stage to check planes on same stage
  3823. * we assume that all pipes are in source split so its valid to compare
  3824. * without taking into account left/right mixer placement
  3825. */
  3826. rc = _sde_crtc_validate_src_split_order(crtc, pstates, cnt);
  3827. if (rc)
  3828. return rc;
  3829. return 0;
  3830. }
  3831. static int sde_crtc_atomic_check(struct drm_crtc *crtc,
  3832. struct drm_crtc_state *state)
  3833. {
  3834. struct drm_device *dev;
  3835. struct sde_crtc *sde_crtc;
  3836. struct plane_state *pstates = NULL;
  3837. struct sde_crtc_state *cstate;
  3838. struct drm_display_mode *mode;
  3839. int rc = 0;
  3840. struct sde_multirect_plane_states *multirect_plane = NULL;
  3841. struct drm_connector *conn;
  3842. struct drm_connector_list_iter conn_iter;
  3843. if (!crtc) {
  3844. SDE_ERROR("invalid crtc\n");
  3845. return -EINVAL;
  3846. }
  3847. dev = crtc->dev;
  3848. sde_crtc = to_sde_crtc(crtc);
  3849. cstate = to_sde_crtc_state(state);
  3850. if (!state->enable || !state->active) {
  3851. SDE_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n",
  3852. crtc->base.id, state->enable, state->active);
  3853. goto end;
  3854. }
  3855. pstates = kcalloc(SDE_PSTATES_MAX,
  3856. sizeof(struct plane_state), GFP_KERNEL);
  3857. multirect_plane = kcalloc(SDE_MULTIRECT_PLANE_MAX,
  3858. sizeof(struct sde_multirect_plane_states),
  3859. GFP_KERNEL);
  3860. if (!pstates || !multirect_plane) {
  3861. rc = -ENOMEM;
  3862. goto end;
  3863. }
  3864. mode = &state->adjusted_mode;
  3865. SDE_DEBUG("%s: check", sde_crtc->name);
  3866. /* force a full mode set if active state changed */
  3867. if (state->active_changed)
  3868. state->mode_changed = true;
  3869. rc = _sde_crtc_check_dest_scaler_data(crtc, state);
  3870. if (rc) {
  3871. SDE_ERROR("crtc%d failed dest scaler check %d\n",
  3872. crtc->base.id, rc);
  3873. goto end;
  3874. }
  3875. /* identify connectors attached to this crtc */
  3876. cstate->num_connectors = 0;
  3877. drm_connector_list_iter_begin(dev, &conn_iter);
  3878. drm_for_each_connector_iter(conn, &conn_iter)
  3879. if (conn->state && conn->state->crtc == crtc &&
  3880. cstate->num_connectors < MAX_CONNECTORS) {
  3881. cstate->connectors[cstate->num_connectors++] = conn;
  3882. }
  3883. drm_connector_list_iter_end(&conn_iter);
  3884. _sde_crtc_setup_is_ppsplit(state);
  3885. _sde_crtc_setup_lm_bounds(crtc, state);
  3886. rc = _sde_crtc_atomic_check_pstates(crtc, state, pstates,
  3887. multirect_plane);
  3888. if (rc) {
  3889. SDE_ERROR("crtc%d failed pstate check %d\n", crtc->base.id, rc);
  3890. goto end;
  3891. }
  3892. rc = sde_core_perf_crtc_check(crtc, state);
  3893. if (rc) {
  3894. SDE_ERROR("crtc%d failed performance check %d\n",
  3895. crtc->base.id, rc);
  3896. goto end;
  3897. }
  3898. rc = _sde_crtc_check_rois(crtc, state);
  3899. if (rc) {
  3900. SDE_ERROR("crtc%d failed roi check %d\n", crtc->base.id, rc);
  3901. goto end;
  3902. }
  3903. end:
  3904. kfree(pstates);
  3905. kfree(multirect_plane);
  3906. return rc;
  3907. }
  3908. int sde_crtc_vblank(struct drm_crtc *crtc, bool en)
  3909. {
  3910. struct sde_crtc *sde_crtc;
  3911. int ret;
  3912. if (!crtc) {
  3913. SDE_ERROR("invalid crtc\n");
  3914. return -EINVAL;
  3915. }
  3916. sde_crtc = to_sde_crtc(crtc);
  3917. mutex_lock(&sde_crtc->crtc_lock);
  3918. SDE_EVT32(DRMID(&sde_crtc->base), en, sde_crtc->enabled);
  3919. ret = _sde_crtc_vblank_enable_no_lock(sde_crtc, en);
  3920. if (ret)
  3921. SDE_ERROR("%s vblank enable failed: %d\n",
  3922. sde_crtc->name, ret);
  3923. mutex_unlock(&sde_crtc->crtc_lock);
  3924. return 0;
  3925. }
  3926. /**
  3927. * sde_crtc_install_properties - install all drm properties for crtc
  3928. * @crtc: Pointer to drm crtc structure
  3929. */
  3930. static void sde_crtc_install_properties(struct drm_crtc *crtc,
  3931. struct sde_mdss_cfg *catalog)
  3932. {
  3933. struct sde_crtc *sde_crtc;
  3934. struct drm_device *dev;
  3935. struct sde_kms_info *info;
  3936. struct sde_kms *sde_kms;
  3937. int i, j;
  3938. static const struct drm_prop_enum_list e_secure_level[] = {
  3939. {SDE_DRM_SEC_NON_SEC, "sec_and_non_sec"},
  3940. {SDE_DRM_SEC_ONLY, "sec_only"},
  3941. };
  3942. static const struct drm_prop_enum_list e_cwb_data_points[] = {
  3943. {CAPTURE_MIXER_OUT, "capture_mixer_out"},
  3944. {CAPTURE_DSPP_OUT, "capture_pp_out"},
  3945. };
  3946. static const struct drm_prop_enum_list e_idle_pc_state[] = {
  3947. {IDLE_PC_NONE, "idle_pc_none"},
  3948. {IDLE_PC_ENABLE, "idle_pc_enable"},
  3949. {IDLE_PC_DISABLE, "idle_pc_disable"},
  3950. };
  3951. SDE_DEBUG("\n");
  3952. if (!crtc || !catalog) {
  3953. SDE_ERROR("invalid crtc or catalog\n");
  3954. return;
  3955. }
  3956. sde_crtc = to_sde_crtc(crtc);
  3957. dev = crtc->dev;
  3958. sde_kms = _sde_crtc_get_kms(crtc);
  3959. if (!sde_kms) {
  3960. SDE_ERROR("invalid argument\n");
  3961. return;
  3962. }
  3963. info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
  3964. if (!info) {
  3965. SDE_ERROR("failed to allocate info memory\n");
  3966. return;
  3967. }
  3968. /* range properties */
  3969. msm_property_install_range(&sde_crtc->property_info,
  3970. "input_fence_timeout", 0x0, 0, SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT,
  3971. SDE_CRTC_INPUT_FENCE_TIMEOUT, CRTC_PROP_INPUT_FENCE_TIMEOUT);
  3972. msm_property_install_volatile_range(&sde_crtc->property_info,
  3973. "output_fence", 0x0, 0, ~0, 0, CRTC_PROP_OUTPUT_FENCE);
  3974. msm_property_install_range(&sde_crtc->property_info,
  3975. "output_fence_offset", 0x0, 0, 1, 0,
  3976. CRTC_PROP_OUTPUT_FENCE_OFFSET);
  3977. msm_property_install_range(&sde_crtc->property_info,
  3978. "core_clk", 0x0, 0, U64_MAX,
  3979. sde_kms->perf.max_core_clk_rate,
  3980. CRTC_PROP_CORE_CLK);
  3981. msm_property_install_range(&sde_crtc->property_info,
  3982. "core_ab", 0x0, 0, U64_MAX,
  3983. catalog->perf.max_bw_high * 1000ULL,
  3984. CRTC_PROP_CORE_AB);
  3985. msm_property_install_range(&sde_crtc->property_info,
  3986. "core_ib", 0x0, 0, U64_MAX,
  3987. catalog->perf.max_bw_high * 1000ULL,
  3988. CRTC_PROP_CORE_IB);
  3989. msm_property_install_range(&sde_crtc->property_info,
  3990. "llcc_ab", 0x0, 0, U64_MAX,
  3991. catalog->perf.max_bw_high * 1000ULL,
  3992. CRTC_PROP_LLCC_AB);
  3993. msm_property_install_range(&sde_crtc->property_info,
  3994. "llcc_ib", 0x0, 0, U64_MAX,
  3995. catalog->perf.max_bw_high * 1000ULL,
  3996. CRTC_PROP_LLCC_IB);
  3997. msm_property_install_range(&sde_crtc->property_info,
  3998. "dram_ab", 0x0, 0, U64_MAX,
  3999. catalog->perf.max_bw_high * 1000ULL,
  4000. CRTC_PROP_DRAM_AB);
  4001. msm_property_install_range(&sde_crtc->property_info,
  4002. "dram_ib", 0x0, 0, U64_MAX,
  4003. catalog->perf.max_bw_high * 1000ULL,
  4004. CRTC_PROP_DRAM_IB);
  4005. msm_property_install_range(&sde_crtc->property_info,
  4006. "rot_prefill_bw", 0, 0, U64_MAX,
  4007. catalog->perf.max_bw_high * 1000ULL,
  4008. CRTC_PROP_ROT_PREFILL_BW);
  4009. msm_property_install_range(&sde_crtc->property_info,
  4010. "rot_clk", 0, 0, U64_MAX,
  4011. sde_kms->perf.max_core_clk_rate,
  4012. CRTC_PROP_ROT_CLK);
  4013. msm_property_install_range(&sde_crtc->property_info,
  4014. "idle_time", 0, 0, U64_MAX, 0,
  4015. CRTC_PROP_IDLE_TIMEOUT);
  4016. if (catalog->has_idle_pc)
  4017. msm_property_install_enum(&sde_crtc->property_info,
  4018. "idle_pc_state", 0x0, 0, e_idle_pc_state,
  4019. ARRAY_SIZE(e_idle_pc_state),
  4020. CRTC_PROP_IDLE_PC_STATE);
  4021. if (catalog->has_cwb_support)
  4022. msm_property_install_enum(&sde_crtc->property_info,
  4023. "capture_mode", 0, 0, e_cwb_data_points,
  4024. ARRAY_SIZE(e_cwb_data_points),
  4025. CRTC_PROP_CAPTURE_OUTPUT);
  4026. msm_property_install_blob(&sde_crtc->property_info, "capabilities",
  4027. DRM_MODE_PROP_IMMUTABLE, CRTC_PROP_INFO);
  4028. msm_property_install_volatile_range(&sde_crtc->property_info,
  4029. "sde_drm_roi_v1", 0x0, 0, ~0, 0, CRTC_PROP_ROI_V1);
  4030. msm_property_install_enum(&sde_crtc->property_info, "security_level",
  4031. 0x0, 0, e_secure_level,
  4032. ARRAY_SIZE(e_secure_level),
  4033. CRTC_PROP_SECURITY_LEVEL);
  4034. sde_kms_info_reset(info);
  4035. if (catalog->has_dim_layer) {
  4036. msm_property_install_volatile_range(&sde_crtc->property_info,
  4037. "dim_layer_v1", 0x0, 0, ~0, 0, CRTC_PROP_DIM_LAYER_V1);
  4038. sde_kms_info_add_keyint(info, "dim_layer_v1_max_layers",
  4039. SDE_MAX_DIM_LAYERS);
  4040. }
  4041. sde_kms_info_add_keyint(info, "hw_version", catalog->hwversion);
  4042. sde_kms_info_add_keyint(info, "max_linewidth",
  4043. catalog->max_mixer_width);
  4044. sde_kms_info_add_keyint(info, "max_blendstages",
  4045. catalog->max_mixer_blendstages);
  4046. if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED2)
  4047. sde_kms_info_add_keystr(info, "qseed_type", "qseed2");
  4048. if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED3)
  4049. sde_kms_info_add_keystr(info, "qseed_type", "qseed3");
  4050. if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED3LITE)
  4051. sde_kms_info_add_keystr(info, "qseed_type", "qseed3lite");
  4052. sde_kms_info_add_keyint(info, "UBWC version", catalog->ubwc_version);
  4053. sde_kms_info_add_keyint(info, "UBWC macrotile_mode",
  4054. catalog->macrotile_mode);
  4055. sde_kms_info_add_keyint(info, "UBWC highest banking bit",
  4056. catalog->mdp[0].highest_bank_bit);
  4057. sde_kms_info_add_keyint(info, "UBWC swizzle",
  4058. catalog->mdp[0].ubwc_swizzle);
  4059. if (of_fdt_get_ddrtype() == LP_DDR4_TYPE)
  4060. sde_kms_info_add_keystr(info, "DDR version", "DDR4");
  4061. else
  4062. sde_kms_info_add_keystr(info, "DDR version", "DDR5");
  4063. if (sde_is_custom_client()) {
  4064. /* No support for SMART_DMA_V1 yet */
  4065. if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V2)
  4066. sde_kms_info_add_keystr(info,
  4067. "smart_dma_rev", "smart_dma_v2");
  4068. else if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V2p5)
  4069. sde_kms_info_add_keystr(info,
  4070. "smart_dma_rev", "smart_dma_v2p5");
  4071. }
  4072. if (catalog->mdp[0].has_dest_scaler) {
  4073. sde_kms_info_add_keyint(info, "has_dest_scaler",
  4074. catalog->mdp[0].has_dest_scaler);
  4075. sde_kms_info_add_keyint(info, "dest_scaler_count",
  4076. catalog->ds_count);
  4077. if (catalog->ds[0].top) {
  4078. sde_kms_info_add_keyint(info,
  4079. "max_dest_scaler_input_width",
  4080. catalog->ds[0].top->maxinputwidth);
  4081. sde_kms_info_add_keyint(info,
  4082. "max_dest_scaler_output_width",
  4083. catalog->ds[0].top->maxinputwidth);
  4084. sde_kms_info_add_keyint(info, "max_dest_scale_up",
  4085. catalog->ds[0].top->maxupscale);
  4086. }
  4087. if (catalog->ds[0].features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  4088. msm_property_install_volatile_range(
  4089. &sde_crtc->property_info, "dest_scaler",
  4090. 0x0, 0, ~0, 0, CRTC_PROP_DEST_SCALER);
  4091. msm_property_install_blob(&sde_crtc->property_info,
  4092. "ds_lut_ed", 0,
  4093. CRTC_PROP_DEST_SCALER_LUT_ED);
  4094. msm_property_install_blob(&sde_crtc->property_info,
  4095. "ds_lut_cir", 0,
  4096. CRTC_PROP_DEST_SCALER_LUT_CIR);
  4097. msm_property_install_blob(&sde_crtc->property_info,
  4098. "ds_lut_sep", 0,
  4099. CRTC_PROP_DEST_SCALER_LUT_SEP);
  4100. } else if (catalog->ds[0].features
  4101. & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  4102. msm_property_install_volatile_range(
  4103. &sde_crtc->property_info, "dest_scaler",
  4104. 0x0, 0, ~0, 0, CRTC_PROP_DEST_SCALER);
  4105. }
  4106. }
  4107. sde_kms_info_add_keyint(info, "has_src_split", catalog->has_src_split);
  4108. sde_kms_info_add_keyint(info, "has_hdr", catalog->has_hdr);
  4109. sde_kms_info_add_keyint(info, "has_hdr_plus", catalog->has_hdr_plus);
  4110. if (catalog->perf.max_bw_low)
  4111. sde_kms_info_add_keyint(info, "max_bandwidth_low",
  4112. catalog->perf.max_bw_low * 1000LL);
  4113. if (catalog->perf.max_bw_high)
  4114. sde_kms_info_add_keyint(info, "max_bandwidth_high",
  4115. catalog->perf.max_bw_high * 1000LL);
  4116. if (catalog->perf.min_core_ib)
  4117. sde_kms_info_add_keyint(info, "min_core_ib",
  4118. catalog->perf.min_core_ib * 1000LL);
  4119. if (catalog->perf.min_llcc_ib)
  4120. sde_kms_info_add_keyint(info, "min_llcc_ib",
  4121. catalog->perf.min_llcc_ib * 1000LL);
  4122. if (catalog->perf.min_dram_ib)
  4123. sde_kms_info_add_keyint(info, "min_dram_ib",
  4124. catalog->perf.min_dram_ib * 1000LL);
  4125. if (sde_kms->perf.max_core_clk_rate)
  4126. sde_kms_info_add_keyint(info, "max_mdp_clk",
  4127. sde_kms->perf.max_core_clk_rate);
  4128. for (i = 0; i < catalog->limit_count; i++) {
  4129. sde_kms_info_add_keyint(info,
  4130. catalog->limit_cfg[i].name,
  4131. catalog->limit_cfg[i].lmt_case_cnt);
  4132. for (j = 0; j < catalog->limit_cfg[i].lmt_case_cnt; j++) {
  4133. sde_kms_info_add_keyint(info,
  4134. catalog->limit_cfg[i].vector_cfg[j].usecase,
  4135. catalog->limit_cfg[i].vector_cfg[j].value);
  4136. }
  4137. if (!strcmp(catalog->limit_cfg[i].name,
  4138. "sspp_linewidth_usecases"))
  4139. sde_kms_info_add_keyint(info,
  4140. "sspp_linewidth_values",
  4141. catalog->limit_cfg[i].lmt_vec_cnt);
  4142. else if (!strcmp(catalog->limit_cfg[i].name,
  4143. "sde_bwlimit_usecases"))
  4144. sde_kms_info_add_keyint(info,
  4145. "sde_bwlimit_values",
  4146. catalog->limit_cfg[i].lmt_vec_cnt);
  4147. for (j = 0; j < catalog->limit_cfg[i].lmt_vec_cnt; j++) {
  4148. sde_kms_info_add_keyint(info, "limit_usecase",
  4149. catalog->limit_cfg[i].value_cfg[j].use_concur);
  4150. sde_kms_info_add_keyint(info, "limit_value",
  4151. catalog->limit_cfg[i].value_cfg[j].value);
  4152. }
  4153. }
  4154. sde_kms_info_add_keystr(info, "core_ib_ff",
  4155. catalog->perf.core_ib_ff);
  4156. sde_kms_info_add_keystr(info, "core_clk_ff",
  4157. catalog->perf.core_clk_ff);
  4158. sde_kms_info_add_keystr(info, "comp_ratio_rt",
  4159. catalog->perf.comp_ratio_rt);
  4160. sde_kms_info_add_keystr(info, "comp_ratio_nrt",
  4161. catalog->perf.comp_ratio_nrt);
  4162. sde_kms_info_add_keyint(info, "dest_scale_prefill_lines",
  4163. catalog->perf.dest_scale_prefill_lines);
  4164. sde_kms_info_add_keyint(info, "undersized_prefill_lines",
  4165. catalog->perf.undersized_prefill_lines);
  4166. sde_kms_info_add_keyint(info, "macrotile_prefill_lines",
  4167. catalog->perf.macrotile_prefill_lines);
  4168. sde_kms_info_add_keyint(info, "yuv_nv12_prefill_lines",
  4169. catalog->perf.yuv_nv12_prefill_lines);
  4170. sde_kms_info_add_keyint(info, "linear_prefill_lines",
  4171. catalog->perf.linear_prefill_lines);
  4172. sde_kms_info_add_keyint(info, "downscaling_prefill_lines",
  4173. catalog->perf.downscaling_prefill_lines);
  4174. sde_kms_info_add_keyint(info, "xtra_prefill_lines",
  4175. catalog->perf.xtra_prefill_lines);
  4176. sde_kms_info_add_keyint(info, "amortizable_threshold",
  4177. catalog->perf.amortizable_threshold);
  4178. sde_kms_info_add_keyint(info, "min_prefill_lines",
  4179. catalog->perf.min_prefill_lines);
  4180. sde_kms_info_add_keyint(info, "num_mnoc_ports",
  4181. catalog->perf.num_mnoc_ports);
  4182. sde_kms_info_add_keyint(info, "axi_bus_width",
  4183. catalog->perf.axi_bus_width);
  4184. sde_kms_info_add_keyint(info, "sec_ui_blendstage",
  4185. catalog->sui_supported_blendstage);
  4186. if (catalog->ubwc_bw_calc_version)
  4187. sde_kms_info_add_keyint(info, "ubwc_bw_calc_ver",
  4188. catalog->ubwc_bw_calc_version);
  4189. msm_property_set_blob(&sde_crtc->property_info, &sde_crtc->blob_info,
  4190. info->data, SDE_KMS_INFO_DATALEN(info), CRTC_PROP_INFO);
  4191. kfree(info);
  4192. }
  4193. static int _sde_crtc_get_output_fence(struct drm_crtc *crtc,
  4194. const struct drm_crtc_state *state, uint64_t *val)
  4195. {
  4196. struct sde_crtc *sde_crtc;
  4197. struct sde_crtc_state *cstate;
  4198. uint32_t offset;
  4199. bool is_vid = false;
  4200. struct drm_encoder *encoder;
  4201. sde_crtc = to_sde_crtc(crtc);
  4202. cstate = to_sde_crtc_state(state);
  4203. drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) {
  4204. if (sde_encoder_check_curr_mode(encoder,
  4205. MSM_DISPLAY_VIDEO_MODE))
  4206. is_vid = true;
  4207. if (is_vid)
  4208. break;
  4209. }
  4210. offset = sde_crtc_get_property(cstate, CRTC_PROP_OUTPUT_FENCE_OFFSET);
  4211. /*
  4212. * Increment trigger offset for vidoe mode alone as its release fence
  4213. * can be triggered only after the next frame-update. For cmd mode &
  4214. * virtual displays the release fence for the current frame can be
  4215. * triggered right after PP_DONE/WB_DONE interrupt
  4216. */
  4217. if (is_vid)
  4218. offset++;
  4219. /*
  4220. * Hwcomposer now queries the fences using the commit list in atomic
  4221. * commit ioctl. The offset should be set to next timeline
  4222. * which will be incremented during the prepare commit phase
  4223. */
  4224. offset++;
  4225. return sde_fence_create(sde_crtc->output_fence, val, offset);
  4226. }
  4227. /**
  4228. * sde_crtc_atomic_set_property - atomically set a crtc drm property
  4229. * @crtc: Pointer to drm crtc structure
  4230. * @state: Pointer to drm crtc state structure
  4231. * @property: Pointer to targeted drm property
  4232. * @val: Updated property value
  4233. * @Returns: Zero on success
  4234. */
  4235. static int sde_crtc_atomic_set_property(struct drm_crtc *crtc,
  4236. struct drm_crtc_state *state,
  4237. struct drm_property *property,
  4238. uint64_t val)
  4239. {
  4240. struct sde_crtc *sde_crtc;
  4241. struct sde_crtc_state *cstate;
  4242. int idx, ret;
  4243. uint64_t fence_user_fd;
  4244. uint64_t __user prev_user_fd;
  4245. if (!crtc || !state || !property) {
  4246. SDE_ERROR("invalid argument(s)\n");
  4247. return -EINVAL;
  4248. }
  4249. sde_crtc = to_sde_crtc(crtc);
  4250. cstate = to_sde_crtc_state(state);
  4251. SDE_ATRACE_BEGIN("sde_crtc_atomic_set_property");
  4252. /* check with cp property system first */
  4253. ret = sde_cp_crtc_set_property(crtc, property, val);
  4254. if (ret != -ENOENT)
  4255. goto exit;
  4256. /* if not handled by cp, check msm_property system */
  4257. ret = msm_property_atomic_set(&sde_crtc->property_info,
  4258. &cstate->property_state, property, val);
  4259. if (ret)
  4260. goto exit;
  4261. idx = msm_property_index(&sde_crtc->property_info, property);
  4262. switch (idx) {
  4263. case CRTC_PROP_INPUT_FENCE_TIMEOUT:
  4264. _sde_crtc_set_input_fence_timeout(cstate);
  4265. break;
  4266. case CRTC_PROP_DIM_LAYER_V1:
  4267. _sde_crtc_set_dim_layer_v1(cstate,
  4268. (void __user *)(uintptr_t)val);
  4269. break;
  4270. case CRTC_PROP_ROI_V1:
  4271. ret = _sde_crtc_set_roi_v1(state,
  4272. (void __user *)(uintptr_t)val);
  4273. break;
  4274. case CRTC_PROP_DEST_SCALER:
  4275. ret = _sde_crtc_set_dest_scaler(sde_crtc, cstate,
  4276. (void __user *)(uintptr_t)val);
  4277. break;
  4278. case CRTC_PROP_DEST_SCALER_LUT_ED:
  4279. case CRTC_PROP_DEST_SCALER_LUT_CIR:
  4280. case CRTC_PROP_DEST_SCALER_LUT_SEP:
  4281. ret = _sde_crtc_set_dest_scaler_lut(sde_crtc, cstate, idx);
  4282. break;
  4283. case CRTC_PROP_CORE_CLK:
  4284. case CRTC_PROP_CORE_AB:
  4285. case CRTC_PROP_CORE_IB:
  4286. cstate->bw_control = true;
  4287. break;
  4288. case CRTC_PROP_LLCC_AB:
  4289. case CRTC_PROP_LLCC_IB:
  4290. case CRTC_PROP_DRAM_AB:
  4291. case CRTC_PROP_DRAM_IB:
  4292. cstate->bw_control = true;
  4293. cstate->bw_split_vote = true;
  4294. break;
  4295. case CRTC_PROP_OUTPUT_FENCE:
  4296. if (!val)
  4297. goto exit;
  4298. ret = copy_from_user(&prev_user_fd, (void __user *)val,
  4299. sizeof(uint64_t));
  4300. if (ret) {
  4301. SDE_ERROR("copy from user failed rc:%d\n", ret);
  4302. ret = -EFAULT;
  4303. goto exit;
  4304. }
  4305. /*
  4306. * client is expected to reset the property to -1 before
  4307. * requesting for the release fence
  4308. */
  4309. if (prev_user_fd == -1) {
  4310. ret = _sde_crtc_get_output_fence(crtc, state,
  4311. &fence_user_fd);
  4312. if (ret) {
  4313. SDE_ERROR("fence create failed rc:%d\n", ret);
  4314. goto exit;
  4315. }
  4316. ret = copy_to_user((uint64_t __user *)(uintptr_t)val,
  4317. &fence_user_fd, sizeof(uint64_t));
  4318. if (ret) {
  4319. SDE_ERROR("copy to user failed rc:%d\n", ret);
  4320. put_unused_fd(fence_user_fd);
  4321. ret = -EFAULT;
  4322. goto exit;
  4323. }
  4324. }
  4325. break;
  4326. default:
  4327. /* nothing to do */
  4328. break;
  4329. }
  4330. exit:
  4331. if (ret) {
  4332. if (ret != -EPERM)
  4333. SDE_ERROR("%s: failed to set property%d %s: %d\n",
  4334. crtc->name, DRMID(property),
  4335. property->name, ret);
  4336. else
  4337. SDE_DEBUG("%s: failed to set property%d %s: %d\n",
  4338. crtc->name, DRMID(property),
  4339. property->name, ret);
  4340. } else {
  4341. SDE_DEBUG("%s: %s[%d] <= 0x%llx\n", crtc->name, property->name,
  4342. property->base.id, val);
  4343. }
  4344. SDE_ATRACE_END("sde_crtc_atomic_set_property");
  4345. return ret;
  4346. }
  4347. /**
  4348. * sde_crtc_atomic_get_property - retrieve a crtc drm property
  4349. * @crtc: Pointer to drm crtc structure
  4350. * @state: Pointer to drm crtc state structure
  4351. * @property: Pointer to targeted drm property
  4352. * @val: Pointer to variable for receiving property value
  4353. * @Returns: Zero on success
  4354. */
  4355. static int sde_crtc_atomic_get_property(struct drm_crtc *crtc,
  4356. const struct drm_crtc_state *state,
  4357. struct drm_property *property,
  4358. uint64_t *val)
  4359. {
  4360. struct sde_crtc *sde_crtc;
  4361. struct sde_crtc_state *cstate;
  4362. int ret = -EINVAL, i;
  4363. if (!crtc || !state) {
  4364. SDE_ERROR("invalid argument(s)\n");
  4365. goto end;
  4366. }
  4367. sde_crtc = to_sde_crtc(crtc);
  4368. cstate = to_sde_crtc_state(state);
  4369. i = msm_property_index(&sde_crtc->property_info, property);
  4370. if (i == CRTC_PROP_OUTPUT_FENCE) {
  4371. *val = ~0;
  4372. ret = 0;
  4373. } else {
  4374. ret = msm_property_atomic_get(&sde_crtc->property_info,
  4375. &cstate->property_state, property, val);
  4376. if (ret)
  4377. ret = sde_cp_crtc_get_property(crtc, property, val);
  4378. }
  4379. if (ret)
  4380. DRM_ERROR("get property failed\n");
  4381. end:
  4382. return ret;
  4383. }
  4384. int sde_crtc_helper_reset_custom_properties(struct drm_crtc *crtc,
  4385. struct drm_crtc_state *crtc_state)
  4386. {
  4387. struct sde_crtc *sde_crtc;
  4388. struct sde_crtc_state *cstate;
  4389. struct drm_property *drm_prop;
  4390. enum msm_mdp_crtc_property prop_idx;
  4391. if (!crtc || !crtc_state) {
  4392. SDE_ERROR("invalid params\n");
  4393. return -EINVAL;
  4394. }
  4395. sde_crtc = to_sde_crtc(crtc);
  4396. cstate = to_sde_crtc_state(crtc_state);
  4397. sde_cp_crtc_clear(crtc);
  4398. for (prop_idx = 0; prop_idx < CRTC_PROP_COUNT; prop_idx++) {
  4399. uint64_t val = cstate->property_values[prop_idx].value;
  4400. uint64_t def;
  4401. int ret;
  4402. drm_prop = msm_property_index_to_drm_property(
  4403. &sde_crtc->property_info, prop_idx);
  4404. if (!drm_prop) {
  4405. /* not all props will be installed, based on caps */
  4406. SDE_DEBUG("%s: invalid property index %d\n",
  4407. sde_crtc->name, prop_idx);
  4408. continue;
  4409. }
  4410. def = msm_property_get_default(&sde_crtc->property_info,
  4411. prop_idx);
  4412. if (val == def)
  4413. continue;
  4414. SDE_DEBUG("%s: set prop %s idx %d from %llu to %llu\n",
  4415. sde_crtc->name, drm_prop->name, prop_idx, val,
  4416. def);
  4417. ret = sde_crtc_atomic_set_property(crtc, crtc_state, drm_prop,
  4418. def);
  4419. if (ret) {
  4420. SDE_ERROR("%s: set property failed, idx %d ret %d\n",
  4421. sde_crtc->name, prop_idx, ret);
  4422. continue;
  4423. }
  4424. }
  4425. return 0;
  4426. }
  4427. void sde_crtc_misr_setup(struct drm_crtc *crtc, bool enable, u32 frame_count)
  4428. {
  4429. struct sde_crtc *sde_crtc;
  4430. struct sde_crtc_mixer *m;
  4431. int i;
  4432. if (!crtc) {
  4433. SDE_ERROR("invalid argument\n");
  4434. return;
  4435. }
  4436. sde_crtc = to_sde_crtc(crtc);
  4437. sde_crtc->misr_enable_sui = enable;
  4438. sde_crtc->misr_frame_count = frame_count;
  4439. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  4440. m = &sde_crtc->mixers[i];
  4441. if (!m->hw_lm || !m->hw_lm->ops.setup_misr)
  4442. continue;
  4443. m->hw_lm->ops.setup_misr(m->hw_lm, enable, frame_count);
  4444. }
  4445. }
  4446. void sde_crtc_get_misr_info(struct drm_crtc *crtc,
  4447. struct sde_crtc_misr_info *crtc_misr_info)
  4448. {
  4449. struct sde_crtc *sde_crtc;
  4450. struct sde_kms *sde_kms;
  4451. if (!crtc_misr_info) {
  4452. SDE_ERROR("invalid misr info\n");
  4453. return;
  4454. }
  4455. crtc_misr_info->misr_enable = false;
  4456. crtc_misr_info->misr_frame_count = 0;
  4457. if (!crtc) {
  4458. SDE_ERROR("invalid crtc\n");
  4459. return;
  4460. }
  4461. sde_kms = _sde_crtc_get_kms(crtc);
  4462. if (!sde_kms) {
  4463. SDE_ERROR("invalid sde_kms\n");
  4464. return;
  4465. }
  4466. if (sde_kms_is_secure_session_inprogress(sde_kms))
  4467. return;
  4468. sde_crtc = to_sde_crtc(crtc);
  4469. crtc_misr_info->misr_enable =
  4470. sde_crtc->misr_enable_debugfs ? true : false;
  4471. crtc_misr_info->misr_frame_count = sde_crtc->misr_frame_count;
  4472. }
  4473. #ifdef CONFIG_DEBUG_FS
  4474. static int _sde_debugfs_status_show(struct seq_file *s, void *data)
  4475. {
  4476. struct sde_crtc *sde_crtc;
  4477. struct sde_plane_state *pstate = NULL;
  4478. struct sde_crtc_mixer *m;
  4479. struct drm_crtc *crtc;
  4480. struct drm_plane *plane;
  4481. struct drm_display_mode *mode;
  4482. struct drm_framebuffer *fb;
  4483. struct drm_plane_state *state;
  4484. struct sde_crtc_state *cstate;
  4485. int i, out_width, out_height;
  4486. if (!s || !s->private)
  4487. return -EINVAL;
  4488. sde_crtc = s->private;
  4489. crtc = &sde_crtc->base;
  4490. cstate = to_sde_crtc_state(crtc->state);
  4491. mutex_lock(&sde_crtc->crtc_lock);
  4492. mode = &crtc->state->adjusted_mode;
  4493. out_width = sde_crtc_get_mixer_width(sde_crtc, cstate, mode);
  4494. out_height = sde_crtc_get_mixer_height(sde_crtc, cstate, mode);
  4495. seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id,
  4496. mode->hdisplay, mode->vdisplay);
  4497. seq_puts(s, "\n");
  4498. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  4499. m = &sde_crtc->mixers[i];
  4500. if (!m->hw_lm)
  4501. seq_printf(s, "\tmixer[%d] has no lm\n", i);
  4502. else if (!m->hw_ctl)
  4503. seq_printf(s, "\tmixer[%d] has no ctl\n", i);
  4504. else
  4505. seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n",
  4506. m->hw_lm->idx - LM_0, m->hw_ctl->idx - CTL_0,
  4507. out_width, out_height);
  4508. }
  4509. seq_puts(s, "\n");
  4510. for (i = 0; i < cstate->num_dim_layers; i++) {
  4511. struct sde_hw_dim_layer *dim_layer = &cstate->dim_layer[i];
  4512. seq_printf(s, "\tdim_layer:%d] stage:%d flags:%d\n",
  4513. i, dim_layer->stage, dim_layer->flags);
  4514. seq_printf(s, "\tdst_x:%d dst_y:%d dst_w:%d dst_h:%d\n",
  4515. dim_layer->rect.x, dim_layer->rect.y,
  4516. dim_layer->rect.w, dim_layer->rect.h);
  4517. seq_printf(s,
  4518. "\tcolor_0:%d color_1:%d color_2:%d color_3:%d\n",
  4519. dim_layer->color_fill.color_0,
  4520. dim_layer->color_fill.color_1,
  4521. dim_layer->color_fill.color_2,
  4522. dim_layer->color_fill.color_3);
  4523. seq_puts(s, "\n");
  4524. }
  4525. drm_atomic_crtc_for_each_plane(plane, crtc) {
  4526. pstate = to_sde_plane_state(plane->state);
  4527. state = plane->state;
  4528. if (!pstate || !state)
  4529. continue;
  4530. seq_printf(s, "\tplane:%u stage:%d rotation:%d\n",
  4531. plane->base.id, pstate->stage, pstate->rotation);
  4532. if (plane->state->fb) {
  4533. fb = plane->state->fb;
  4534. seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u ",
  4535. fb->base.id, (char *) &fb->format->format,
  4536. fb->width, fb->height);
  4537. for (i = 0; i < ARRAY_SIZE(fb->format->cpp); ++i)
  4538. seq_printf(s, "cpp[%d]:%u ",
  4539. i, fb->format->cpp[i]);
  4540. seq_puts(s, "\n\t");
  4541. seq_printf(s, "modifier:%8llu ", fb->modifier);
  4542. seq_puts(s, "\n");
  4543. seq_puts(s, "\t");
  4544. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++)
  4545. seq_printf(s, "pitches[%d]:%8u ", i,
  4546. fb->pitches[i]);
  4547. seq_puts(s, "\n");
  4548. seq_puts(s, "\t");
  4549. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++)
  4550. seq_printf(s, "offsets[%d]:%8u ", i,
  4551. fb->offsets[i]);
  4552. seq_puts(s, "\n");
  4553. }
  4554. seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n",
  4555. state->src_x >> 16, state->src_y >> 16,
  4556. state->src_w >> 16, state->src_h >> 16);
  4557. seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n",
  4558. state->crtc_x, state->crtc_y, state->crtc_w,
  4559. state->crtc_h);
  4560. seq_printf(s, "\tmultirect: mode: %d index: %d\n",
  4561. pstate->multirect_mode, pstate->multirect_index);
  4562. seq_printf(s, "\texcl_rect: x:%4d y:%4d w:%4d h:%4d\n",
  4563. pstate->excl_rect.x, pstate->excl_rect.y,
  4564. pstate->excl_rect.w, pstate->excl_rect.h);
  4565. seq_puts(s, "\n");
  4566. }
  4567. if (sde_crtc->vblank_cb_count) {
  4568. ktime_t diff = ktime_sub(ktime_get(), sde_crtc->vblank_cb_time);
  4569. u32 diff_ms = ktime_to_ms(diff);
  4570. u64 fps = diff_ms ? DIV_ROUND_CLOSEST(
  4571. sde_crtc->vblank_cb_count * 1000, diff_ms) : 0;
  4572. seq_printf(s,
  4573. "vblank fps:%lld count:%u total:%llums total_framecount:%llu\n",
  4574. fps, sde_crtc->vblank_cb_count,
  4575. ktime_to_ms(diff), sde_crtc->play_count);
  4576. /* reset time & count for next measurement */
  4577. sde_crtc->vblank_cb_count = 0;
  4578. sde_crtc->vblank_cb_time = ktime_set(0, 0);
  4579. }
  4580. mutex_unlock(&sde_crtc->crtc_lock);
  4581. return 0;
  4582. }
  4583. static int _sde_debugfs_status_open(struct inode *inode, struct file *file)
  4584. {
  4585. return single_open(file, _sde_debugfs_status_show, inode->i_private);
  4586. }
  4587. static ssize_t _sde_crtc_misr_setup(struct file *file,
  4588. const char __user *user_buf, size_t count, loff_t *ppos)
  4589. {
  4590. struct drm_crtc *crtc;
  4591. struct sde_crtc *sde_crtc;
  4592. int rc;
  4593. char buf[MISR_BUFF_SIZE + 1];
  4594. u32 frame_count, enable;
  4595. size_t buff_copy;
  4596. struct sde_kms *sde_kms;
  4597. if (!file || !file->private_data)
  4598. return -EINVAL;
  4599. sde_crtc = file->private_data;
  4600. crtc = &sde_crtc->base;
  4601. sde_kms = _sde_crtc_get_kms(crtc);
  4602. if (!sde_kms) {
  4603. SDE_ERROR("invalid sde_kms\n");
  4604. return -EINVAL;
  4605. }
  4606. buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
  4607. if (copy_from_user(buf, user_buf, buff_copy)) {
  4608. SDE_ERROR("buffer copy failed\n");
  4609. return -EINVAL;
  4610. }
  4611. buf[buff_copy] = 0; /* end of string */
  4612. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
  4613. return -EINVAL;
  4614. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  4615. SDE_DEBUG("crtc:%d misr enable/disable not allowed\n",
  4616. DRMID(crtc));
  4617. return -EINVAL;
  4618. }
  4619. rc = pm_runtime_get_sync(crtc->dev->dev);
  4620. if (rc < 0)
  4621. return rc;
  4622. sde_crtc->misr_enable_debugfs = enable;
  4623. sde_crtc_misr_setup(crtc, enable, frame_count);
  4624. pm_runtime_put_sync(crtc->dev->dev);
  4625. return count;
  4626. }
  4627. static ssize_t _sde_crtc_misr_read(struct file *file,
  4628. char __user *user_buff, size_t count, loff_t *ppos)
  4629. {
  4630. struct drm_crtc *crtc;
  4631. struct sde_crtc *sde_crtc;
  4632. struct sde_kms *sde_kms;
  4633. struct sde_crtc_mixer *m;
  4634. int i = 0, rc;
  4635. ssize_t len = 0;
  4636. char buf[MISR_BUFF_SIZE + 1] = {'\0'};
  4637. if (*ppos)
  4638. return 0;
  4639. if (!file || !file->private_data)
  4640. return -EINVAL;
  4641. sde_crtc = file->private_data;
  4642. crtc = &sde_crtc->base;
  4643. sde_kms = _sde_crtc_get_kms(crtc);
  4644. if (!sde_kms)
  4645. return -EINVAL;
  4646. rc = pm_runtime_get_sync(crtc->dev->dev);
  4647. if (rc < 0)
  4648. return rc;
  4649. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  4650. SDE_DEBUG("crtc:%d misr read not allowed\n", DRMID(crtc));
  4651. goto end;
  4652. }
  4653. if (!sde_crtc->misr_enable_debugfs) {
  4654. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4655. "disabled\n");
  4656. goto buff_check;
  4657. }
  4658. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  4659. u32 misr_value = 0;
  4660. m = &sde_crtc->mixers[i];
  4661. if (!m->hw_lm || !m->hw_lm->ops.collect_misr) {
  4662. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4663. "invalid\n");
  4664. SDE_ERROR("crtc:%d invalid misr ops\n", DRMID(crtc));
  4665. continue;
  4666. }
  4667. rc = m->hw_lm->ops.collect_misr(m->hw_lm, false, &misr_value);
  4668. if (rc) {
  4669. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4670. "invalid\n");
  4671. SDE_ERROR("crtc:%d failed to collect misr %d\n",
  4672. DRMID(crtc), rc);
  4673. continue;
  4674. } else {
  4675. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4676. "lm idx:%d\n", m->hw_lm->idx - LM_0);
  4677. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4678. "0x%x\n", misr_value);
  4679. }
  4680. }
  4681. buff_check:
  4682. if (count <= len) {
  4683. len = 0;
  4684. goto end;
  4685. }
  4686. if (copy_to_user(user_buff, buf, len)) {
  4687. len = -EFAULT;
  4688. goto end;
  4689. }
  4690. *ppos += len; /* increase offset */
  4691. end:
  4692. pm_runtime_put_sync(crtc->dev->dev);
  4693. return len;
  4694. }
  4695. #define DEFINE_SDE_DEBUGFS_SEQ_FOPS(__prefix) \
  4696. static int __prefix ## _open(struct inode *inode, struct file *file) \
  4697. { \
  4698. return single_open(file, __prefix ## _show, inode->i_private); \
  4699. } \
  4700. static const struct file_operations __prefix ## _fops = { \
  4701. .owner = THIS_MODULE, \
  4702. .open = __prefix ## _open, \
  4703. .release = single_release, \
  4704. .read = seq_read, \
  4705. .llseek = seq_lseek, \
  4706. }
  4707. static int sde_crtc_debugfs_state_show(struct seq_file *s, void *v)
  4708. {
  4709. struct drm_crtc *crtc = (struct drm_crtc *) s->private;
  4710. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  4711. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
  4712. int i;
  4713. seq_printf(s, "num_connectors: %d\n", cstate->num_connectors);
  4714. seq_printf(s, "client type: %d\n", sde_crtc_get_client_type(crtc));
  4715. seq_printf(s, "intf_mode: %d\n", sde_crtc_get_intf_mode(crtc,
  4716. crtc->state));
  4717. seq_printf(s, "core_clk_rate: %llu\n",
  4718. sde_crtc->cur_perf.core_clk_rate);
  4719. for (i = SDE_POWER_HANDLE_DBUS_ID_MNOC;
  4720. i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++) {
  4721. seq_printf(s, "bw_ctl[%s]: %llu\n",
  4722. sde_power_handle_get_dbus_name(i),
  4723. sde_crtc->cur_perf.bw_ctl[i]);
  4724. seq_printf(s, "max_per_pipe_ib[%s]: %llu\n",
  4725. sde_power_handle_get_dbus_name(i),
  4726. sde_crtc->cur_perf.max_per_pipe_ib[i]);
  4727. }
  4728. return 0;
  4729. }
  4730. DEFINE_SDE_DEBUGFS_SEQ_FOPS(sde_crtc_debugfs_state);
  4731. static int _sde_debugfs_fence_status_show(struct seq_file *s, void *data)
  4732. {
  4733. struct drm_crtc *crtc;
  4734. struct drm_plane *plane;
  4735. struct drm_connector *conn;
  4736. struct drm_mode_object *drm_obj;
  4737. struct sde_crtc *sde_crtc;
  4738. struct sde_crtc_state *cstate;
  4739. struct sde_fence_context *ctx;
  4740. struct drm_connector_list_iter conn_iter;
  4741. struct drm_device *dev;
  4742. if (!s || !s->private)
  4743. return -EINVAL;
  4744. sde_crtc = s->private;
  4745. crtc = &sde_crtc->base;
  4746. dev = crtc->dev;
  4747. cstate = to_sde_crtc_state(crtc->state);
  4748. /* Dump input fence info */
  4749. seq_puts(s, "===Input fence===\n");
  4750. drm_atomic_crtc_for_each_plane(plane, crtc) {
  4751. struct sde_plane_state *pstate;
  4752. struct dma_fence *fence;
  4753. pstate = to_sde_plane_state(plane->state);
  4754. if (!pstate)
  4755. continue;
  4756. seq_printf(s, "plane:%u stage:%d\n", plane->base.id,
  4757. pstate->stage);
  4758. fence = pstate->input_fence;
  4759. if (fence)
  4760. sde_fence_list_dump(fence, &s);
  4761. }
  4762. /* Dump release fence info */
  4763. seq_puts(s, "\n");
  4764. seq_puts(s, "===Release fence===\n");
  4765. ctx = sde_crtc->output_fence;
  4766. drm_obj = &crtc->base;
  4767. sde_debugfs_timeline_dump(ctx, drm_obj, &s);
  4768. seq_puts(s, "\n");
  4769. /* Dump retire fence info */
  4770. seq_puts(s, "===Retire fence===\n");
  4771. drm_connector_list_iter_begin(dev, &conn_iter);
  4772. drm_for_each_connector_iter(conn, &conn_iter)
  4773. if (conn->state && conn->state->crtc == crtc &&
  4774. cstate->num_connectors < MAX_CONNECTORS) {
  4775. struct sde_connector *c_conn;
  4776. c_conn = to_sde_connector(conn);
  4777. ctx = c_conn->retire_fence;
  4778. drm_obj = &conn->base;
  4779. sde_debugfs_timeline_dump(ctx, drm_obj, &s);
  4780. }
  4781. drm_connector_list_iter_end(&conn_iter);
  4782. seq_puts(s, "\n");
  4783. return 0;
  4784. }
  4785. static int _sde_debugfs_fence_status(struct inode *inode, struct file *file)
  4786. {
  4787. return single_open(file, _sde_debugfs_fence_status_show,
  4788. inode->i_private);
  4789. }
  4790. static int _sde_crtc_init_debugfs(struct drm_crtc *crtc)
  4791. {
  4792. struct sde_crtc *sde_crtc;
  4793. struct sde_kms *sde_kms;
  4794. static const struct file_operations debugfs_status_fops = {
  4795. .open = _sde_debugfs_status_open,
  4796. .read = seq_read,
  4797. .llseek = seq_lseek,
  4798. .release = single_release,
  4799. };
  4800. static const struct file_operations debugfs_misr_fops = {
  4801. .open = simple_open,
  4802. .read = _sde_crtc_misr_read,
  4803. .write = _sde_crtc_misr_setup,
  4804. };
  4805. static const struct file_operations debugfs_fps_fops = {
  4806. .open = _sde_debugfs_fps_status,
  4807. .read = seq_read,
  4808. };
  4809. static const struct file_operations debugfs_fence_fops = {
  4810. .open = _sde_debugfs_fence_status,
  4811. .read = seq_read,
  4812. };
  4813. if (!crtc)
  4814. return -EINVAL;
  4815. sde_crtc = to_sde_crtc(crtc);
  4816. sde_kms = _sde_crtc_get_kms(crtc);
  4817. if (!sde_kms)
  4818. return -EINVAL;
  4819. sde_crtc->debugfs_root = debugfs_create_dir(sde_crtc->name,
  4820. crtc->dev->primary->debugfs_root);
  4821. if (!sde_crtc->debugfs_root)
  4822. return -ENOMEM;
  4823. /* don't error check these */
  4824. debugfs_create_file("status", 0400,
  4825. sde_crtc->debugfs_root,
  4826. sde_crtc, &debugfs_status_fops);
  4827. debugfs_create_file("state", 0400,
  4828. sde_crtc->debugfs_root,
  4829. &sde_crtc->base,
  4830. &sde_crtc_debugfs_state_fops);
  4831. debugfs_create_file("misr_data", 0600, sde_crtc->debugfs_root,
  4832. sde_crtc, &debugfs_misr_fops);
  4833. debugfs_create_file("fps", 0400, sde_crtc->debugfs_root,
  4834. sde_crtc, &debugfs_fps_fops);
  4835. debugfs_create_file("fence_status", 0400, sde_crtc->debugfs_root,
  4836. sde_crtc, &debugfs_fence_fops);
  4837. return 0;
  4838. }
  4839. static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc)
  4840. {
  4841. struct sde_crtc *sde_crtc;
  4842. if (!crtc)
  4843. return;
  4844. sde_crtc = to_sde_crtc(crtc);
  4845. debugfs_remove_recursive(sde_crtc->debugfs_root);
  4846. }
  4847. #else
  4848. static int _sde_crtc_init_debugfs(struct drm_crtc *crtc)
  4849. {
  4850. return 0;
  4851. }
  4852. static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc)
  4853. {
  4854. }
  4855. #endif /* CONFIG_DEBUG_FS */
  4856. static int sde_crtc_late_register(struct drm_crtc *crtc)
  4857. {
  4858. return _sde_crtc_init_debugfs(crtc);
  4859. }
  4860. static void sde_crtc_early_unregister(struct drm_crtc *crtc)
  4861. {
  4862. _sde_crtc_destroy_debugfs(crtc);
  4863. }
  4864. static const struct drm_crtc_funcs sde_crtc_funcs = {
  4865. .set_config = drm_atomic_helper_set_config,
  4866. .destroy = sde_crtc_destroy,
  4867. .page_flip = drm_atomic_helper_page_flip,
  4868. .atomic_set_property = sde_crtc_atomic_set_property,
  4869. .atomic_get_property = sde_crtc_atomic_get_property,
  4870. .reset = sde_crtc_reset,
  4871. .atomic_duplicate_state = sde_crtc_duplicate_state,
  4872. .atomic_destroy_state = sde_crtc_destroy_state,
  4873. .late_register = sde_crtc_late_register,
  4874. .early_unregister = sde_crtc_early_unregister,
  4875. };
  4876. static const struct drm_crtc_helper_funcs sde_crtc_helper_funcs = {
  4877. .mode_fixup = sde_crtc_mode_fixup,
  4878. .disable = sde_crtc_disable,
  4879. .atomic_enable = sde_crtc_enable,
  4880. .atomic_check = sde_crtc_atomic_check,
  4881. .atomic_begin = sde_crtc_atomic_begin,
  4882. .atomic_flush = sde_crtc_atomic_flush,
  4883. };
  4884. static void _sde_crtc_event_cb(struct kthread_work *work)
  4885. {
  4886. struct sde_crtc_event *event;
  4887. struct sde_crtc *sde_crtc;
  4888. unsigned long irq_flags;
  4889. if (!work) {
  4890. SDE_ERROR("invalid work item\n");
  4891. return;
  4892. }
  4893. event = container_of(work, struct sde_crtc_event, kt_work);
  4894. /* set sde_crtc to NULL for static work structures */
  4895. sde_crtc = event->sde_crtc;
  4896. if (!sde_crtc)
  4897. return;
  4898. if (event->cb_func)
  4899. event->cb_func(&sde_crtc->base, event->usr);
  4900. spin_lock_irqsave(&sde_crtc->event_lock, irq_flags);
  4901. list_add_tail(&event->list, &sde_crtc->event_free_list);
  4902. spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags);
  4903. }
  4904. int sde_crtc_event_queue(struct drm_crtc *crtc,
  4905. void (*func)(struct drm_crtc *crtc, void *usr),
  4906. void *usr, bool color_processing_event)
  4907. {
  4908. unsigned long irq_flags;
  4909. struct sde_crtc *sde_crtc;
  4910. struct msm_drm_private *priv;
  4911. struct sde_crtc_event *event = NULL;
  4912. u32 crtc_id;
  4913. if (!crtc || !crtc->dev || !crtc->dev->dev_private || !func) {
  4914. SDE_ERROR("invalid parameters\n");
  4915. return -EINVAL;
  4916. }
  4917. sde_crtc = to_sde_crtc(crtc);
  4918. priv = crtc->dev->dev_private;
  4919. crtc_id = drm_crtc_index(crtc);
  4920. /*
  4921. * Obtain an event struct from the private cache. This event
  4922. * queue may be called from ISR contexts, so use a private
  4923. * cache to avoid calling any memory allocation functions.
  4924. */
  4925. spin_lock_irqsave(&sde_crtc->event_lock, irq_flags);
  4926. if (!list_empty(&sde_crtc->event_free_list)) {
  4927. event = list_first_entry(&sde_crtc->event_free_list,
  4928. struct sde_crtc_event, list);
  4929. list_del_init(&event->list);
  4930. }
  4931. spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags);
  4932. if (!event)
  4933. return -ENOMEM;
  4934. /* populate event node */
  4935. event->sde_crtc = sde_crtc;
  4936. event->cb_func = func;
  4937. event->usr = usr;
  4938. /* queue new event request */
  4939. kthread_init_work(&event->kt_work, _sde_crtc_event_cb);
  4940. if (color_processing_event)
  4941. kthread_queue_work(&priv->pp_event_worker,
  4942. &event->kt_work);
  4943. else
  4944. kthread_queue_work(&priv->event_thread[crtc_id].worker,
  4945. &event->kt_work);
  4946. return 0;
  4947. }
  4948. static int _sde_crtc_init_events(struct sde_crtc *sde_crtc)
  4949. {
  4950. int i, rc = 0;
  4951. if (!sde_crtc) {
  4952. SDE_ERROR("invalid crtc\n");
  4953. return -EINVAL;
  4954. }
  4955. spin_lock_init(&sde_crtc->event_lock);
  4956. INIT_LIST_HEAD(&sde_crtc->event_free_list);
  4957. for (i = 0; i < SDE_CRTC_MAX_EVENT_COUNT; ++i)
  4958. list_add_tail(&sde_crtc->event_cache[i].list,
  4959. &sde_crtc->event_free_list);
  4960. return rc;
  4961. }
  4962. /*
  4963. * __sde_crtc_idle_notify_work - signal idle timeout to user space
  4964. */
  4965. static void __sde_crtc_idle_notify_work(struct kthread_work *work)
  4966. {
  4967. struct sde_crtc *sde_crtc = container_of(work, struct sde_crtc,
  4968. idle_notify_work.work);
  4969. struct drm_crtc *crtc;
  4970. struct drm_event event;
  4971. int ret = 0;
  4972. if (!sde_crtc) {
  4973. SDE_ERROR("invalid sde crtc\n");
  4974. } else {
  4975. crtc = &sde_crtc->base;
  4976. event.type = DRM_EVENT_IDLE_NOTIFY;
  4977. event.length = sizeof(u32);
  4978. msm_mode_object_event_notify(&crtc->base, crtc->dev,
  4979. &event, (u8 *)&ret);
  4980. SDE_DEBUG("crtc[%d]: idle timeout notified\n", crtc->base.id);
  4981. }
  4982. }
  4983. /* initialize crtc */
  4984. struct drm_crtc *sde_crtc_init(struct drm_device *dev, struct drm_plane *plane)
  4985. {
  4986. struct drm_crtc *crtc = NULL;
  4987. struct sde_crtc *sde_crtc = NULL;
  4988. struct msm_drm_private *priv = NULL;
  4989. struct sde_kms *kms = NULL;
  4990. int i, rc;
  4991. priv = dev->dev_private;
  4992. kms = to_sde_kms(priv->kms);
  4993. sde_crtc = kzalloc(sizeof(*sde_crtc), GFP_KERNEL);
  4994. if (!sde_crtc)
  4995. return ERR_PTR(-ENOMEM);
  4996. crtc = &sde_crtc->base;
  4997. crtc->dev = dev;
  4998. mutex_init(&sde_crtc->crtc_lock);
  4999. spin_lock_init(&sde_crtc->spin_lock);
  5000. atomic_set(&sde_crtc->frame_pending, 0);
  5001. sde_crtc->enabled = false;
  5002. /* Below parameters are for fps calculation for sysfs node */
  5003. sde_crtc->fps_info.fps_periodic_duration = DEFAULT_FPS_PERIOD_1_SEC;
  5004. sde_crtc->fps_info.time_buf = kmalloc_array(MAX_FRAME_COUNT,
  5005. sizeof(ktime_t), GFP_KERNEL);
  5006. if (!sde_crtc->fps_info.time_buf)
  5007. SDE_ERROR("invalid buffer\n");
  5008. else
  5009. memset(sde_crtc->fps_info.time_buf, 0,
  5010. sizeof(*(sde_crtc->fps_info.time_buf)));
  5011. INIT_LIST_HEAD(&sde_crtc->frame_event_list);
  5012. INIT_LIST_HEAD(&sde_crtc->user_event_list);
  5013. for (i = 0; i < ARRAY_SIZE(sde_crtc->frame_events); i++) {
  5014. INIT_LIST_HEAD(&sde_crtc->frame_events[i].list);
  5015. list_add(&sde_crtc->frame_events[i].list,
  5016. &sde_crtc->frame_event_list);
  5017. kthread_init_work(&sde_crtc->frame_events[i].work,
  5018. sde_crtc_frame_event_work);
  5019. }
  5020. drm_crtc_init_with_planes(dev, crtc, plane, NULL, &sde_crtc_funcs,
  5021. NULL);
  5022. drm_crtc_helper_add(crtc, &sde_crtc_helper_funcs);
  5023. /* save user friendly CRTC name for later */
  5024. snprintf(sde_crtc->name, SDE_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
  5025. /* initialize event handling */
  5026. rc = _sde_crtc_init_events(sde_crtc);
  5027. if (rc) {
  5028. drm_crtc_cleanup(crtc);
  5029. kfree(sde_crtc);
  5030. return ERR_PTR(rc);
  5031. }
  5032. /* initialize output fence support */
  5033. sde_crtc->output_fence = sde_fence_init(sde_crtc->name, crtc->base.id);
  5034. if (IS_ERR(sde_crtc->output_fence)) {
  5035. rc = PTR_ERR(sde_crtc->output_fence);
  5036. SDE_ERROR("failed to init fence, %d\n", rc);
  5037. drm_crtc_cleanup(crtc);
  5038. kfree(sde_crtc);
  5039. return ERR_PTR(rc);
  5040. }
  5041. /* create CRTC properties */
  5042. msm_property_init(&sde_crtc->property_info, &crtc->base, dev,
  5043. priv->crtc_property, sde_crtc->property_data,
  5044. CRTC_PROP_COUNT, CRTC_PROP_BLOBCOUNT,
  5045. sizeof(struct sde_crtc_state));
  5046. sde_crtc_install_properties(crtc, kms->catalog);
  5047. /* Install color processing properties */
  5048. sde_cp_crtc_init(crtc);
  5049. sde_cp_crtc_install_properties(crtc);
  5050. sde_crtc->cur_perf.llcc_active = false;
  5051. sde_crtc->new_perf.llcc_active = false;
  5052. kthread_init_delayed_work(&sde_crtc->idle_notify_work,
  5053. __sde_crtc_idle_notify_work);
  5054. SDE_DEBUG("crtc=%d new_llcc=%d, old_llcc=%d\n",
  5055. crtc->base.id,
  5056. sde_crtc->new_perf.llcc_active,
  5057. sde_crtc->cur_perf.llcc_active);
  5058. SDE_DEBUG("%s: successfully initialized crtc\n", sde_crtc->name);
  5059. return crtc;
  5060. }
  5061. int sde_crtc_post_init(struct drm_device *dev, struct drm_crtc *crtc)
  5062. {
  5063. struct sde_crtc *sde_crtc;
  5064. int rc = 0;
  5065. if (!dev || !dev->primary || !dev->primary->kdev || !crtc) {
  5066. SDE_ERROR("invalid input param(s)\n");
  5067. rc = -EINVAL;
  5068. goto end;
  5069. }
  5070. sde_crtc = to_sde_crtc(crtc);
  5071. sde_crtc->sysfs_dev = device_create_with_groups(
  5072. dev->primary->kdev->class, dev->primary->kdev, 0, crtc,
  5073. sde_crtc_attr_groups, "sde-crtc-%d", crtc->index);
  5074. if (IS_ERR_OR_NULL(sde_crtc->sysfs_dev)) {
  5075. SDE_ERROR("crtc:%d sysfs create failed rc:%ld\n", crtc->index,
  5076. PTR_ERR(sde_crtc->sysfs_dev));
  5077. if (!sde_crtc->sysfs_dev)
  5078. rc = -EINVAL;
  5079. else
  5080. rc = PTR_ERR(sde_crtc->sysfs_dev);
  5081. goto end;
  5082. }
  5083. sde_crtc->vsync_event_sf = sysfs_get_dirent(
  5084. sde_crtc->sysfs_dev->kobj.sd, "vsync_event");
  5085. if (!sde_crtc->vsync_event_sf)
  5086. SDE_ERROR("crtc:%d vsync_event sysfs create failed\n",
  5087. crtc->base.id);
  5088. end:
  5089. return rc;
  5090. }
  5091. static int _sde_crtc_event_enable(struct sde_kms *kms,
  5092. struct drm_crtc *crtc_drm, u32 event)
  5093. {
  5094. struct sde_crtc *crtc = NULL;
  5095. struct sde_crtc_irq_info *node;
  5096. unsigned long flags;
  5097. bool found = false;
  5098. int ret, i = 0;
  5099. bool add_event = false;
  5100. crtc = to_sde_crtc(crtc_drm);
  5101. spin_lock_irqsave(&crtc->spin_lock, flags);
  5102. list_for_each_entry(node, &crtc->user_event_list, list) {
  5103. if (node->event == event) {
  5104. found = true;
  5105. break;
  5106. }
  5107. }
  5108. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5109. /* event already enabled */
  5110. if (found)
  5111. return 0;
  5112. node = NULL;
  5113. for (i = 0; i < ARRAY_SIZE(custom_events); i++) {
  5114. if (custom_events[i].event == event &&
  5115. custom_events[i].func) {
  5116. node = kzalloc(sizeof(*node), GFP_KERNEL);
  5117. if (!node)
  5118. return -ENOMEM;
  5119. INIT_LIST_HEAD(&node->list);
  5120. node->func = custom_events[i].func;
  5121. node->event = event;
  5122. node->state = IRQ_NOINIT;
  5123. spin_lock_init(&node->state_lock);
  5124. break;
  5125. }
  5126. }
  5127. if (!node) {
  5128. SDE_ERROR("unsupported event %x\n", event);
  5129. return -EINVAL;
  5130. }
  5131. ret = 0;
  5132. if (crtc_drm->enabled) {
  5133. ret = pm_runtime_get_sync(crtc_drm->dev->dev);
  5134. if (ret < 0) {
  5135. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  5136. kfree(node);
  5137. return ret;
  5138. }
  5139. INIT_LIST_HEAD(&node->irq.list);
  5140. mutex_lock(&crtc->crtc_lock);
  5141. ret = node->func(crtc_drm, true, &node->irq);
  5142. if (!ret) {
  5143. spin_lock_irqsave(&crtc->spin_lock, flags);
  5144. list_add_tail(&node->list, &crtc->user_event_list);
  5145. add_event = true;
  5146. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5147. }
  5148. mutex_unlock(&crtc->crtc_lock);
  5149. pm_runtime_put_sync(crtc_drm->dev->dev);
  5150. }
  5151. if (add_event)
  5152. return 0;
  5153. if (!ret) {
  5154. spin_lock_irqsave(&crtc->spin_lock, flags);
  5155. list_add_tail(&node->list, &crtc->user_event_list);
  5156. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5157. } else {
  5158. kfree(node);
  5159. }
  5160. return ret;
  5161. }
  5162. static int _sde_crtc_event_disable(struct sde_kms *kms,
  5163. struct drm_crtc *crtc_drm, u32 event)
  5164. {
  5165. struct sde_crtc *crtc = NULL;
  5166. struct sde_crtc_irq_info *node = NULL;
  5167. unsigned long flags;
  5168. bool found = false;
  5169. int ret;
  5170. crtc = to_sde_crtc(crtc_drm);
  5171. spin_lock_irqsave(&crtc->spin_lock, flags);
  5172. list_for_each_entry(node, &crtc->user_event_list, list) {
  5173. if (node->event == event) {
  5174. list_del(&node->list);
  5175. found = true;
  5176. break;
  5177. }
  5178. }
  5179. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5180. /* event already disabled */
  5181. if (!found)
  5182. return 0;
  5183. /**
  5184. * crtc is disabled interrupts are cleared remove from the list,
  5185. * no need to disable/de-register.
  5186. */
  5187. if (!crtc_drm->enabled) {
  5188. kfree(node);
  5189. return 0;
  5190. }
  5191. ret = pm_runtime_get_sync(crtc_drm->dev->dev);
  5192. if (ret < 0) {
  5193. SDE_ERROR("failed to enable power resource %d\n", ret);
  5194. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  5195. kfree(node);
  5196. return ret;
  5197. }
  5198. ret = node->func(crtc_drm, false, &node->irq);
  5199. kfree(node);
  5200. pm_runtime_put_sync(crtc_drm->dev->dev);
  5201. return ret;
  5202. }
  5203. int sde_crtc_register_custom_event(struct sde_kms *kms,
  5204. struct drm_crtc *crtc_drm, u32 event, bool en)
  5205. {
  5206. struct sde_crtc *crtc = NULL;
  5207. int ret;
  5208. crtc = to_sde_crtc(crtc_drm);
  5209. if (!crtc || !kms || !kms->dev) {
  5210. DRM_ERROR("invalid sde_crtc %pK kms %pK dev %pK\n", crtc,
  5211. kms, ((kms) ? (kms->dev) : NULL));
  5212. return -EINVAL;
  5213. }
  5214. if (en)
  5215. ret = _sde_crtc_event_enable(kms, crtc_drm, event);
  5216. else
  5217. ret = _sde_crtc_event_disable(kms, crtc_drm, event);
  5218. return ret;
  5219. }
  5220. static int sde_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
  5221. bool en, struct sde_irq_callback *irq)
  5222. {
  5223. return 0;
  5224. }
  5225. static int sde_crtc_pm_event_handler(struct drm_crtc *crtc, bool en,
  5226. struct sde_irq_callback *noirq)
  5227. {
  5228. /*
  5229. * IRQ object noirq is not being used here since there is
  5230. * no crtc irq from pm event.
  5231. */
  5232. return 0;
  5233. }
  5234. static int sde_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
  5235. bool en, struct sde_irq_callback *irq)
  5236. {
  5237. return 0;
  5238. }
  5239. /**
  5240. * sde_crtc_update_cont_splash_settings - update mixer settings
  5241. * and initial clk during device bootup for cont_splash use case
  5242. * @crtc: Pointer to drm crtc structure
  5243. */
  5244. void sde_crtc_update_cont_splash_settings(struct drm_crtc *crtc)
  5245. {
  5246. struct sde_kms *kms = NULL;
  5247. struct msm_drm_private *priv;
  5248. struct sde_crtc *sde_crtc;
  5249. u64 rate;
  5250. if (!crtc || !crtc->state || !crtc->dev || !crtc->dev->dev_private) {
  5251. SDE_ERROR("invalid crtc\n");
  5252. return;
  5253. }
  5254. priv = crtc->dev->dev_private;
  5255. kms = to_sde_kms(priv->kms);
  5256. if (!kms || !kms->catalog) {
  5257. SDE_ERROR("invalid parameters\n");
  5258. return;
  5259. }
  5260. _sde_crtc_setup_mixers(crtc);
  5261. crtc->enabled = true;
  5262. /* update core clk value for initial state with cont-splash */
  5263. sde_crtc = to_sde_crtc(crtc);
  5264. rate = sde_power_clk_get_rate(&priv->phandle, kms->perf.clk_name);
  5265. sde_crtc->cur_perf.core_clk_rate = (rate > 0) ?
  5266. rate : kms->perf.max_core_clk_rate;
  5267. sde_crtc->cur_perf.core_clk_rate = kms->perf.max_core_clk_rate;
  5268. }