dp_tx.c 108 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065
  1. /*
  2. * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "hal_hw_headers.h"
  20. #include "dp_tx.h"
  21. #include "dp_tx_desc.h"
  22. #include "dp_peer.h"
  23. #include "dp_types.h"
  24. #include "hal_tx.h"
  25. #include "qdf_mem.h"
  26. #include "qdf_nbuf.h"
  27. #include "qdf_net_types.h"
  28. #include <wlan_cfg.h>
  29. #ifdef MESH_MODE_SUPPORT
  30. #include "if_meta_hdr.h"
  31. #endif
  32. #define DP_TX_QUEUE_MASK 0x3
  33. /* TODO Add support in TSO */
  34. #define DP_DESC_NUM_FRAG(x) 0
  35. /* disable TQM_BYPASS */
  36. #define TQM_BYPASS_WAR 0
  37. /* invalid peer id for reinject*/
  38. #define DP_INVALID_PEER 0XFFFE
  39. /*mapping between hal encrypt type and cdp_sec_type*/
  40. #define MAX_CDP_SEC_TYPE 12
  41. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  42. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  43. HAL_TX_ENCRYPT_TYPE_WEP_128,
  44. HAL_TX_ENCRYPT_TYPE_WEP_104,
  45. HAL_TX_ENCRYPT_TYPE_WEP_40,
  46. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  47. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  48. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  49. HAL_TX_ENCRYPT_TYPE_WAPI,
  50. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  51. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  52. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  53. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  54. /**
  55. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  56. * @vdev: DP Virtual device handle
  57. * @nbuf: Buffer pointer
  58. * @queue: queue ids container for nbuf
  59. *
  60. * TX packet queue has 2 instances, software descriptors id and dma ring id
  61. * Based on tx feature and hardware configuration queue id combination could be
  62. * different.
  63. * For example -
  64. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  65. * With no XPS,lock based resource protection, Descriptor pool ids are different
  66. * for each vdev, dma ring id will be same as single pdev id
  67. *
  68. * Return: None
  69. */
  70. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  71. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  72. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  73. {
  74. uint16_t queue_offset = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  75. queue->desc_pool_id = queue_offset;
  76. queue->ring_id = vdev->pdev->soc->tx_ring_map[queue_offset];
  77. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  78. "%s, pool_id:%d ring_id: %d",
  79. __func__, queue->desc_pool_id, queue->ring_id);
  80. return;
  81. }
  82. #else /* QCA_OL_TX_MULTIQ_SUPPORT */
  83. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  84. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  85. {
  86. /* get flow id */
  87. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  88. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  89. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  90. "%s, pool_id:%d ring_id: %d",
  91. __func__, queue->desc_pool_id, queue->ring_id);
  92. return;
  93. }
  94. #endif
  95. #if defined(FEATURE_TSO)
  96. /**
  97. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  98. *
  99. * @soc - core txrx main context
  100. * @seg_desc - tso segment descriptor
  101. * @num_seg_desc - tso number segment descriptor
  102. */
  103. static void dp_tx_tso_unmap_segment(
  104. struct dp_soc *soc,
  105. struct qdf_tso_seg_elem_t *seg_desc,
  106. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  107. {
  108. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  109. if (qdf_unlikely(!seg_desc)) {
  110. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  111. __func__, __LINE__);
  112. qdf_assert(0);
  113. } else if (qdf_unlikely(!num_seg_desc)) {
  114. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  115. __func__, __LINE__);
  116. qdf_assert(0);
  117. } else {
  118. bool is_last_seg;
  119. /* no tso segment left to do dma unmap */
  120. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  121. return;
  122. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  123. true : false;
  124. qdf_nbuf_unmap_tso_segment(soc->osdev,
  125. seg_desc, is_last_seg);
  126. num_seg_desc->num_seg.tso_cmn_num_seg--;
  127. }
  128. }
  129. /**
  130. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  131. * back to the freelist
  132. *
  133. * @soc - soc device handle
  134. * @tx_desc - Tx software descriptor
  135. */
  136. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  137. struct dp_tx_desc_s *tx_desc)
  138. {
  139. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  140. if (qdf_unlikely(!tx_desc->tso_desc)) {
  141. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  142. "%s %d TSO desc is NULL!",
  143. __func__, __LINE__);
  144. qdf_assert(0);
  145. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  146. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  147. "%s %d TSO num desc is NULL!",
  148. __func__, __LINE__);
  149. qdf_assert(0);
  150. } else {
  151. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  152. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  153. /* Add the tso num segment into the free list */
  154. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  155. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  156. tx_desc->tso_num_desc);
  157. tx_desc->tso_num_desc = NULL;
  158. }
  159. /* Add the tso segment into the free list*/
  160. dp_tx_tso_desc_free(soc,
  161. tx_desc->pool_id, tx_desc->tso_desc);
  162. tx_desc->tso_desc = NULL;
  163. }
  164. }
  165. #else
  166. static void dp_tx_tso_unmap_segment(
  167. struct dp_soc *soc,
  168. struct qdf_tso_seg_elem_t *seg_desc,
  169. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  170. {
  171. }
  172. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  173. struct dp_tx_desc_s *tx_desc)
  174. {
  175. }
  176. #endif
  177. /**
  178. * dp_tx_desc_release() - Release Tx Descriptor
  179. * @tx_desc : Tx Descriptor
  180. * @desc_pool_id: Descriptor Pool ID
  181. *
  182. * Deallocate all resources attached to Tx descriptor and free the Tx
  183. * descriptor.
  184. *
  185. * Return:
  186. */
  187. static void
  188. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  189. {
  190. struct dp_pdev *pdev = tx_desc->pdev;
  191. struct dp_soc *soc;
  192. uint8_t comp_status = 0;
  193. qdf_assert(pdev);
  194. soc = pdev->soc;
  195. if (tx_desc->frm_type == dp_tx_frm_tso)
  196. dp_tx_tso_desc_release(soc, tx_desc);
  197. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  198. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  199. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  200. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  201. qdf_atomic_dec(&pdev->num_tx_outstanding);
  202. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  203. qdf_atomic_dec(&pdev->num_tx_exception);
  204. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  205. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  206. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  207. soc->hal_soc);
  208. else
  209. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  210. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  211. "Tx Completion Release desc %d status %d outstanding %d",
  212. tx_desc->id, comp_status,
  213. qdf_atomic_read(&pdev->num_tx_outstanding));
  214. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  215. return;
  216. }
  217. /**
  218. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  219. * @vdev: DP vdev Handle
  220. * @nbuf: skb
  221. *
  222. * Prepares and fills HTT metadata in the frame pre-header for special frames
  223. * that should be transmitted using varying transmit parameters.
  224. * There are 2 VDEV modes that currently needs this special metadata -
  225. * 1) Mesh Mode
  226. * 2) DSRC Mode
  227. *
  228. * Return: HTT metadata size
  229. *
  230. */
  231. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  232. uint32_t *meta_data)
  233. {
  234. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  235. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  236. uint8_t htt_desc_size;
  237. /* Size rounded of multiple of 8 bytes */
  238. uint8_t htt_desc_size_aligned;
  239. uint8_t *hdr = NULL;
  240. /*
  241. * Metadata - HTT MSDU Extension header
  242. */
  243. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  244. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  245. if (vdev->mesh_vdev) {
  246. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  247. htt_desc_size_aligned)) {
  248. DP_STATS_INC(vdev,
  249. tx_i.dropped.headroom_insufficient, 1);
  250. return 0;
  251. }
  252. /* Fill and add HTT metaheader */
  253. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  254. if (hdr == NULL) {
  255. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  256. "Error in filling HTT metadata");
  257. return 0;
  258. }
  259. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  260. } else if (vdev->opmode == wlan_op_mode_ocb) {
  261. /* Todo - Add support for DSRC */
  262. }
  263. return htt_desc_size_aligned;
  264. }
  265. /**
  266. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  267. * @tso_seg: TSO segment to process
  268. * @ext_desc: Pointer to MSDU extension descriptor
  269. *
  270. * Return: void
  271. */
  272. #if defined(FEATURE_TSO)
  273. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  274. void *ext_desc)
  275. {
  276. uint8_t num_frag;
  277. uint32_t tso_flags;
  278. /*
  279. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  280. * tcp_flag_mask
  281. *
  282. * Checksum enable flags are set in TCL descriptor and not in Extension
  283. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  284. */
  285. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  286. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  287. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  288. tso_seg->tso_flags.ip_len);
  289. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  290. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  291. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  292. uint32_t lo = 0;
  293. uint32_t hi = 0;
  294. qdf_dmaaddr_to_32s(
  295. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  296. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  297. tso_seg->tso_frags[num_frag].length);
  298. }
  299. return;
  300. }
  301. #else
  302. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  303. void *ext_desc)
  304. {
  305. return;
  306. }
  307. #endif
  308. #if defined(FEATURE_TSO)
  309. /**
  310. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  311. * allocated and free them
  312. *
  313. * @soc: soc handle
  314. * @free_seg: list of tso segments
  315. * @msdu_info: msdu descriptor
  316. *
  317. * Return - void
  318. */
  319. static void dp_tx_free_tso_seg_list(
  320. struct dp_soc *soc,
  321. struct qdf_tso_seg_elem_t *free_seg,
  322. struct dp_tx_msdu_info_s *msdu_info)
  323. {
  324. struct qdf_tso_seg_elem_t *next_seg;
  325. while (free_seg) {
  326. next_seg = free_seg->next;
  327. dp_tx_tso_desc_free(soc,
  328. msdu_info->tx_queue.desc_pool_id,
  329. free_seg);
  330. free_seg = next_seg;
  331. }
  332. }
  333. /**
  334. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  335. * allocated and free them
  336. *
  337. * @soc: soc handle
  338. * @free_num_seg: list of tso number segments
  339. * @msdu_info: msdu descriptor
  340. * Return - void
  341. */
  342. static void dp_tx_free_tso_num_seg_list(
  343. struct dp_soc *soc,
  344. struct qdf_tso_num_seg_elem_t *free_num_seg,
  345. struct dp_tx_msdu_info_s *msdu_info)
  346. {
  347. struct qdf_tso_num_seg_elem_t *next_num_seg;
  348. while (free_num_seg) {
  349. next_num_seg = free_num_seg->next;
  350. dp_tso_num_seg_free(soc,
  351. msdu_info->tx_queue.desc_pool_id,
  352. free_num_seg);
  353. free_num_seg = next_num_seg;
  354. }
  355. }
  356. /**
  357. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  358. * do dma unmap for each segment
  359. *
  360. * @soc: soc handle
  361. * @free_seg: list of tso segments
  362. * @num_seg_desc: tso number segment descriptor
  363. *
  364. * Return - void
  365. */
  366. static void dp_tx_unmap_tso_seg_list(
  367. struct dp_soc *soc,
  368. struct qdf_tso_seg_elem_t *free_seg,
  369. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  370. {
  371. struct qdf_tso_seg_elem_t *next_seg;
  372. if (qdf_unlikely(!num_seg_desc)) {
  373. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  374. return;
  375. }
  376. while (free_seg) {
  377. next_seg = free_seg->next;
  378. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  379. free_seg = next_seg;
  380. }
  381. }
  382. /**
  383. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  384. * free the tso segments descriptor and
  385. * tso num segments descriptor
  386. *
  387. * @soc: soc handle
  388. * @msdu_info: msdu descriptor
  389. * @tso_seg_unmap: flag to show if dma unmap is necessary
  390. *
  391. * Return - void
  392. */
  393. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  394. struct dp_tx_msdu_info_s *msdu_info,
  395. bool tso_seg_unmap)
  396. {
  397. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  398. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  399. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  400. tso_info->tso_num_seg_list;
  401. /* do dma unmap for each segment */
  402. if (tso_seg_unmap)
  403. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  404. /* free all tso number segment descriptor though looks only have 1 */
  405. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  406. /* free all tso segment descriptor */
  407. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  408. }
  409. /**
  410. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  411. * @vdev: virtual device handle
  412. * @msdu: network buffer
  413. * @msdu_info: meta data associated with the msdu
  414. *
  415. * Return: QDF_STATUS_SUCCESS success
  416. */
  417. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  418. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  419. {
  420. struct qdf_tso_seg_elem_t *tso_seg;
  421. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  422. struct dp_soc *soc = vdev->pdev->soc;
  423. struct qdf_tso_info_t *tso_info;
  424. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  425. tso_info = &msdu_info->u.tso_info;
  426. tso_info->curr_seg = NULL;
  427. tso_info->tso_seg_list = NULL;
  428. tso_info->num_segs = num_seg;
  429. msdu_info->frm_type = dp_tx_frm_tso;
  430. tso_info->tso_num_seg_list = NULL;
  431. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  432. while (num_seg) {
  433. tso_seg = dp_tx_tso_desc_alloc(
  434. soc, msdu_info->tx_queue.desc_pool_id);
  435. if (tso_seg) {
  436. tso_seg->next = tso_info->tso_seg_list;
  437. tso_info->tso_seg_list = tso_seg;
  438. num_seg--;
  439. } else {
  440. DP_TRACE(ERROR, "%s: Failed to alloc tso seg desc",
  441. __func__);
  442. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  443. return QDF_STATUS_E_NOMEM;
  444. }
  445. }
  446. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  447. tso_num_seg = dp_tso_num_seg_alloc(soc,
  448. msdu_info->tx_queue.desc_pool_id);
  449. if (tso_num_seg) {
  450. tso_num_seg->next = tso_info->tso_num_seg_list;
  451. tso_info->tso_num_seg_list = tso_num_seg;
  452. } else {
  453. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  454. __func__);
  455. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  456. return QDF_STATUS_E_NOMEM;
  457. }
  458. msdu_info->num_seg =
  459. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  460. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  461. msdu_info->num_seg);
  462. if (!(msdu_info->num_seg)) {
  463. /*
  464. * Free allocated TSO seg desc and number seg desc,
  465. * do unmap for segments if dma map has done.
  466. */
  467. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  468. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  469. return QDF_STATUS_E_INVAL;
  470. }
  471. tso_info->curr_seg = tso_info->tso_seg_list;
  472. return QDF_STATUS_SUCCESS;
  473. }
  474. #else
  475. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  476. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  477. {
  478. return QDF_STATUS_E_NOMEM;
  479. }
  480. #endif
  481. /**
  482. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  483. * @vdev: DP Vdev handle
  484. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  485. * @desc_pool_id: Descriptor Pool ID
  486. *
  487. * Return:
  488. */
  489. static
  490. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  491. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  492. {
  493. uint8_t i;
  494. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  495. struct dp_tx_seg_info_s *seg_info;
  496. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  497. struct dp_soc *soc = vdev->pdev->soc;
  498. /* Allocate an extension descriptor */
  499. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  500. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  501. if (!msdu_ext_desc) {
  502. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  503. return NULL;
  504. }
  505. if (msdu_info->exception_fw &&
  506. qdf_unlikely(vdev->mesh_vdev)) {
  507. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  508. &msdu_info->meta_data[0],
  509. sizeof(struct htt_tx_msdu_desc_ext2_t));
  510. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  511. }
  512. switch (msdu_info->frm_type) {
  513. case dp_tx_frm_sg:
  514. case dp_tx_frm_me:
  515. case dp_tx_frm_raw:
  516. seg_info = msdu_info->u.sg_info.curr_seg;
  517. /* Update the buffer pointers in MSDU Extension Descriptor */
  518. for (i = 0; i < seg_info->frag_cnt; i++) {
  519. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  520. seg_info->frags[i].paddr_lo,
  521. seg_info->frags[i].paddr_hi,
  522. seg_info->frags[i].len);
  523. }
  524. break;
  525. case dp_tx_frm_tso:
  526. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  527. &cached_ext_desc[0]);
  528. break;
  529. default:
  530. break;
  531. }
  532. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  533. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  534. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  535. msdu_ext_desc->vaddr);
  536. return msdu_ext_desc;
  537. }
  538. /**
  539. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  540. *
  541. * @skb: skb to be traced
  542. * @msdu_id: msdu_id of the packet
  543. * @vdev_id: vdev_id of the packet
  544. *
  545. * Return: None
  546. */
  547. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  548. uint8_t vdev_id)
  549. {
  550. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  551. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  552. DPTRACE(qdf_dp_trace_ptr(skb,
  553. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  554. QDF_TRACE_DEFAULT_PDEV_ID,
  555. qdf_nbuf_data_addr(skb),
  556. sizeof(qdf_nbuf_data(skb)),
  557. msdu_id, vdev_id));
  558. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  559. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  560. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  561. msdu_id, QDF_TX));
  562. }
  563. /**
  564. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  565. * @vdev: DP vdev handle
  566. * @nbuf: skb
  567. * @desc_pool_id: Descriptor pool ID
  568. * @meta_data: Metadata to the fw
  569. * @tx_exc_metadata: Handle that holds exception path metadata
  570. * Allocate and prepare Tx descriptor with msdu information.
  571. *
  572. * Return: Pointer to Tx Descriptor on success,
  573. * NULL on failure
  574. */
  575. static
  576. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  577. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  578. struct dp_tx_msdu_info_s *msdu_info,
  579. struct cdp_tx_exception_metadata *tx_exc_metadata)
  580. {
  581. uint8_t align_pad;
  582. uint8_t is_exception = 0;
  583. uint8_t htt_hdr_size;
  584. struct ether_header *eh;
  585. struct dp_tx_desc_s *tx_desc;
  586. struct dp_pdev *pdev = vdev->pdev;
  587. struct dp_soc *soc = pdev->soc;
  588. /* Allocate software Tx descriptor */
  589. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  590. if (qdf_unlikely(!tx_desc)) {
  591. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  592. return NULL;
  593. }
  594. /* Flow control/Congestion Control counters */
  595. qdf_atomic_inc(&pdev->num_tx_outstanding);
  596. /* Initialize the SW tx descriptor */
  597. tx_desc->nbuf = nbuf;
  598. tx_desc->frm_type = dp_tx_frm_std;
  599. tx_desc->tx_encap_type = (tx_exc_metadata ?
  600. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  601. tx_desc->vdev = vdev;
  602. tx_desc->pdev = pdev;
  603. tx_desc->msdu_ext_desc = NULL;
  604. tx_desc->pkt_offset = 0;
  605. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  606. /*
  607. * For special modes (vdev_type == ocb or mesh), data frames should be
  608. * transmitted using varying transmit parameters (tx spec) which include
  609. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  610. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  611. * These frames are sent as exception packets to firmware.
  612. *
  613. * HW requirement is that metadata should always point to a
  614. * 8-byte aligned address. So we add alignment pad to start of buffer.
  615. * HTT Metadata should be ensured to be multiple of 8-bytes,
  616. * to get 8-byte aligned start address along with align_pad added
  617. *
  618. * |-----------------------------|
  619. * | |
  620. * |-----------------------------| <-----Buffer Pointer Address given
  621. * | | ^ in HW descriptor (aligned)
  622. * | HTT Metadata | |
  623. * | | |
  624. * | | | Packet Offset given in descriptor
  625. * | | |
  626. * |-----------------------------| |
  627. * | Alignment Pad | v
  628. * |-----------------------------| <----- Actual buffer start address
  629. * | SKB Data | (Unaligned)
  630. * | |
  631. * | |
  632. * | |
  633. * | |
  634. * | |
  635. * |-----------------------------|
  636. */
  637. if (qdf_unlikely((msdu_info->exception_fw)) ||
  638. (vdev->opmode == wlan_op_mode_ocb)) {
  639. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  640. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  641. DP_STATS_INC(vdev,
  642. tx_i.dropped.headroom_insufficient, 1);
  643. goto failure;
  644. }
  645. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  646. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  647. "qdf_nbuf_push_head failed");
  648. goto failure;
  649. }
  650. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  651. msdu_info->meta_data);
  652. if (htt_hdr_size == 0)
  653. goto failure;
  654. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  655. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  656. is_exception = 1;
  657. }
  658. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  659. qdf_nbuf_map(soc->osdev, nbuf,
  660. QDF_DMA_TO_DEVICE))) {
  661. /* Handle failure */
  662. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  663. "qdf_nbuf_map failed");
  664. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  665. goto failure;
  666. }
  667. if (qdf_unlikely(vdev->nawds_enabled)) {
  668. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  669. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  670. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  671. is_exception = 1;
  672. }
  673. }
  674. #if !TQM_BYPASS_WAR
  675. if (is_exception || tx_exc_metadata)
  676. #endif
  677. {
  678. /* Temporary WAR due to TQM VP issues */
  679. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  680. qdf_atomic_inc(&pdev->num_tx_exception);
  681. }
  682. return tx_desc;
  683. failure:
  684. dp_tx_desc_release(tx_desc, desc_pool_id);
  685. return NULL;
  686. }
  687. /**
  688. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  689. * @vdev: DP vdev handle
  690. * @nbuf: skb
  691. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  692. * @desc_pool_id : Descriptor Pool ID
  693. *
  694. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  695. * information. For frames wth fragments, allocate and prepare
  696. * an MSDU extension descriptor
  697. *
  698. * Return: Pointer to Tx Descriptor on success,
  699. * NULL on failure
  700. */
  701. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  702. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  703. uint8_t desc_pool_id)
  704. {
  705. struct dp_tx_desc_s *tx_desc;
  706. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  707. struct dp_pdev *pdev = vdev->pdev;
  708. struct dp_soc *soc = pdev->soc;
  709. /* Allocate software Tx descriptor */
  710. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  711. if (!tx_desc) {
  712. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  713. return NULL;
  714. }
  715. /* Flow control/Congestion Control counters */
  716. qdf_atomic_inc(&pdev->num_tx_outstanding);
  717. /* Initialize the SW tx descriptor */
  718. tx_desc->nbuf = nbuf;
  719. tx_desc->frm_type = msdu_info->frm_type;
  720. tx_desc->tx_encap_type = vdev->tx_encap_type;
  721. tx_desc->vdev = vdev;
  722. tx_desc->pdev = pdev;
  723. tx_desc->pkt_offset = 0;
  724. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  725. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  726. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  727. /* Handle scattered frames - TSO/SG/ME */
  728. /* Allocate and prepare an extension descriptor for scattered frames */
  729. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  730. if (!msdu_ext_desc) {
  731. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  732. "%s Tx Extension Descriptor Alloc Fail",
  733. __func__);
  734. goto failure;
  735. }
  736. #if TQM_BYPASS_WAR
  737. /* Temporary WAR due to TQM VP issues */
  738. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  739. qdf_atomic_inc(&pdev->num_tx_exception);
  740. #endif
  741. if (qdf_unlikely(msdu_info->exception_fw))
  742. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  743. tx_desc->msdu_ext_desc = msdu_ext_desc;
  744. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  745. return tx_desc;
  746. failure:
  747. dp_tx_desc_release(tx_desc, desc_pool_id);
  748. return NULL;
  749. }
  750. /**
  751. * dp_tx_prepare_raw() - Prepare RAW packet TX
  752. * @vdev: DP vdev handle
  753. * @nbuf: buffer pointer
  754. * @seg_info: Pointer to Segment info Descriptor to be prepared
  755. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  756. * descriptor
  757. *
  758. * Return:
  759. */
  760. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  761. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  762. {
  763. qdf_nbuf_t curr_nbuf = NULL;
  764. uint16_t total_len = 0;
  765. qdf_dma_addr_t paddr;
  766. int32_t i;
  767. int32_t mapped_buf_num = 0;
  768. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  769. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  770. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  771. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  772. if (vdev->raw_mode_war &&
  773. (qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS))
  774. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  775. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  776. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  777. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  778. QDF_DMA_TO_DEVICE)) {
  779. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  780. "%s dma map error ", __func__);
  781. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  782. mapped_buf_num = i;
  783. goto error;
  784. }
  785. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  786. seg_info->frags[i].paddr_lo = paddr;
  787. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  788. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  789. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  790. total_len += qdf_nbuf_len(curr_nbuf);
  791. }
  792. seg_info->frag_cnt = i;
  793. seg_info->total_len = total_len;
  794. seg_info->next = NULL;
  795. sg_info->curr_seg = seg_info;
  796. msdu_info->frm_type = dp_tx_frm_raw;
  797. msdu_info->num_seg = 1;
  798. return nbuf;
  799. error:
  800. i = 0;
  801. while (nbuf) {
  802. curr_nbuf = nbuf;
  803. if (i < mapped_buf_num) {
  804. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  805. i++;
  806. }
  807. nbuf = qdf_nbuf_next(nbuf);
  808. qdf_nbuf_free(curr_nbuf);
  809. }
  810. return NULL;
  811. }
  812. /**
  813. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  814. * @soc: DP Soc Handle
  815. * @vdev: DP vdev handle
  816. * @tx_desc: Tx Descriptor Handle
  817. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  818. * @fw_metadata: Metadata to send to Target Firmware along with frame
  819. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  820. * @tx_exc_metadata: Handle that holds exception path meta data
  821. *
  822. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  823. * from software Tx descriptor
  824. *
  825. * Return:
  826. */
  827. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  828. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  829. uint16_t fw_metadata, uint8_t ring_id,
  830. struct cdp_tx_exception_metadata
  831. *tx_exc_metadata)
  832. {
  833. uint8_t type;
  834. uint16_t length;
  835. void *hal_tx_desc, *hal_tx_desc_cached;
  836. qdf_dma_addr_t dma_addr;
  837. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  838. enum cdp_sec_type sec_type = (tx_exc_metadata ?
  839. tx_exc_metadata->sec_type : vdev->sec_type);
  840. /* Return Buffer Manager ID */
  841. uint8_t bm_id = ring_id;
  842. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  843. hal_tx_desc_cached = (void *) cached_desc;
  844. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  845. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  846. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  847. type = HAL_TX_BUF_TYPE_EXT_DESC;
  848. dma_addr = tx_desc->msdu_ext_desc->paddr;
  849. } else {
  850. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  851. type = HAL_TX_BUF_TYPE_BUFFER;
  852. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  853. }
  854. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  855. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  856. dma_addr, bm_id, tx_desc->id,
  857. type, soc->hal_soc);
  858. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  859. return QDF_STATUS_E_RESOURCES;
  860. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  861. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  862. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  863. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  864. vdev->pdev->lmac_id);
  865. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  866. vdev->search_type);
  867. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  868. vdev->bss_ast_hash);
  869. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  870. vdev->dscp_tid_map_id);
  871. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  872. sec_type_map[sec_type]);
  873. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  874. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  875. __func__, length, type, (uint64_t)dma_addr,
  876. tx_desc->pkt_offset, tx_desc->id);
  877. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  878. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  879. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  880. vdev->hal_desc_addr_search_flags);
  881. /* verify checksum offload configuration*/
  882. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  883. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  884. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  885. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  886. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  887. }
  888. if (tid != HTT_TX_EXT_TID_INVALID)
  889. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  890. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  891. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  892. /* Sync cached descriptor with HW */
  893. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  894. if (!hal_tx_desc) {
  895. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  896. "%s TCL ring full ring_id:%d", __func__, ring_id);
  897. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  898. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  899. return QDF_STATUS_E_RESOURCES;
  900. }
  901. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  902. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  903. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  904. return QDF_STATUS_SUCCESS;
  905. }
  906. /**
  907. * dp_cce_classify() - Classify the frame based on CCE rules
  908. * @vdev: DP vdev handle
  909. * @nbuf: skb
  910. *
  911. * Classify frames based on CCE rules
  912. * Return: bool( true if classified,
  913. * else false)
  914. */
  915. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  916. {
  917. struct ether_header *eh = NULL;
  918. uint16_t ether_type;
  919. qdf_llc_t *llcHdr;
  920. qdf_nbuf_t nbuf_clone = NULL;
  921. qdf_dot3_qosframe_t *qos_wh = NULL;
  922. /* for mesh packets don't do any classification */
  923. if (qdf_unlikely(vdev->mesh_vdev))
  924. return false;
  925. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  926. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  927. ether_type = eh->ether_type;
  928. llcHdr = (qdf_llc_t *)(nbuf->data +
  929. sizeof(struct ether_header));
  930. } else {
  931. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  932. /* For encrypted packets don't do any classification */
  933. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  934. return false;
  935. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  936. if (qdf_unlikely(
  937. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  938. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  939. ether_type = *(uint16_t *)(nbuf->data
  940. + QDF_IEEE80211_4ADDR_HDR_LEN
  941. + sizeof(qdf_llc_t)
  942. - sizeof(ether_type));
  943. llcHdr = (qdf_llc_t *)(nbuf->data +
  944. QDF_IEEE80211_4ADDR_HDR_LEN);
  945. } else {
  946. ether_type = *(uint16_t *)(nbuf->data
  947. + QDF_IEEE80211_3ADDR_HDR_LEN
  948. + sizeof(qdf_llc_t)
  949. - sizeof(ether_type));
  950. llcHdr = (qdf_llc_t *)(nbuf->data +
  951. QDF_IEEE80211_3ADDR_HDR_LEN);
  952. }
  953. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  954. && (ether_type ==
  955. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  956. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  957. return true;
  958. }
  959. }
  960. return false;
  961. }
  962. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  963. ether_type = *(uint16_t *)(nbuf->data + 2*ETHER_ADDR_LEN +
  964. sizeof(*llcHdr));
  965. nbuf_clone = qdf_nbuf_clone(nbuf);
  966. if (qdf_unlikely(nbuf_clone)) {
  967. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  968. if (ether_type == htons(ETHERTYPE_8021Q)) {
  969. qdf_nbuf_pull_head(nbuf_clone,
  970. sizeof(qdf_net_vlanhdr_t));
  971. }
  972. }
  973. } else {
  974. if (ether_type == htons(ETHERTYPE_8021Q)) {
  975. nbuf_clone = qdf_nbuf_clone(nbuf);
  976. if (qdf_unlikely(nbuf_clone)) {
  977. qdf_nbuf_pull_head(nbuf_clone,
  978. sizeof(qdf_net_vlanhdr_t));
  979. }
  980. }
  981. }
  982. if (qdf_unlikely(nbuf_clone))
  983. nbuf = nbuf_clone;
  984. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  985. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  986. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  987. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  988. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  989. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  990. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  991. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  992. if (qdf_unlikely(nbuf_clone != NULL))
  993. qdf_nbuf_free(nbuf_clone);
  994. return true;
  995. }
  996. if (qdf_unlikely(nbuf_clone != NULL))
  997. qdf_nbuf_free(nbuf_clone);
  998. return false;
  999. }
  1000. /**
  1001. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1002. * @vdev: DP vdev handle
  1003. * @nbuf: skb
  1004. *
  1005. * Extract the DSCP or PCP information from frame and map into TID value.
  1006. * Software based TID classification is required when more than 2 DSCP-TID
  1007. * mapping tables are needed.
  1008. * Hardware supports 2 DSCP-TID mapping tables
  1009. *
  1010. * Return: void
  1011. */
  1012. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1013. struct dp_tx_msdu_info_s *msdu_info)
  1014. {
  1015. uint8_t tos = 0, dscp_tid_override = 0;
  1016. uint8_t *hdr_ptr, *L3datap;
  1017. uint8_t is_mcast = 0;
  1018. struct ether_header *eh = NULL;
  1019. qdf_ethervlan_header_t *evh = NULL;
  1020. uint16_t ether_type;
  1021. qdf_llc_t *llcHdr;
  1022. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1023. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1024. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1025. return;
  1026. /* for mesh packets don't do any classification */
  1027. if (qdf_unlikely(vdev->mesh_vdev))
  1028. return;
  1029. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1030. eh = (struct ether_header *) nbuf->data;
  1031. hdr_ptr = eh->ether_dhost;
  1032. L3datap = hdr_ptr + sizeof(struct ether_header);
  1033. } else {
  1034. qdf_dot3_qosframe_t *qos_wh =
  1035. (qdf_dot3_qosframe_t *) nbuf->data;
  1036. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1037. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1038. return;
  1039. }
  1040. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1041. ether_type = eh->ether_type;
  1042. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(struct ether_header));
  1043. /*
  1044. * Check if packet is dot3 or eth2 type.
  1045. */
  1046. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1047. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  1048. sizeof(*llcHdr));
  1049. if (ether_type == htons(ETHERTYPE_8021Q)) {
  1050. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1051. sizeof(*llcHdr);
  1052. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  1053. + sizeof(*llcHdr) +
  1054. sizeof(qdf_net_vlanhdr_t));
  1055. } else {
  1056. L3datap = hdr_ptr + sizeof(struct ether_header) +
  1057. sizeof(*llcHdr);
  1058. }
  1059. } else {
  1060. if (ether_type == htons(ETHERTYPE_8021Q)) {
  1061. evh = (qdf_ethervlan_header_t *) eh;
  1062. ether_type = evh->ether_type;
  1063. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1064. }
  1065. }
  1066. /*
  1067. * Find priority from IP TOS DSCP field
  1068. */
  1069. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1070. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1071. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1072. /* Only for unicast frames */
  1073. if (!is_mcast) {
  1074. /* send it on VO queue */
  1075. msdu_info->tid = DP_VO_TID;
  1076. }
  1077. } else {
  1078. /*
  1079. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1080. * from TOS byte.
  1081. */
  1082. tos = ip->ip_tos;
  1083. dscp_tid_override = 1;
  1084. }
  1085. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1086. /* TODO
  1087. * use flowlabel
  1088. *igmpmld cases to be handled in phase 2
  1089. */
  1090. unsigned long ver_pri_flowlabel;
  1091. unsigned long pri;
  1092. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1093. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1094. DP_IPV6_PRIORITY_SHIFT;
  1095. tos = pri;
  1096. dscp_tid_override = 1;
  1097. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1098. msdu_info->tid = DP_VO_TID;
  1099. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1100. /* Only for unicast frames */
  1101. if (!is_mcast) {
  1102. /* send ucast arp on VO queue */
  1103. msdu_info->tid = DP_VO_TID;
  1104. }
  1105. }
  1106. /*
  1107. * Assign all MCAST packets to BE
  1108. */
  1109. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1110. if (is_mcast) {
  1111. tos = 0;
  1112. dscp_tid_override = 1;
  1113. }
  1114. }
  1115. if (dscp_tid_override == 1) {
  1116. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1117. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1118. }
  1119. return;
  1120. }
  1121. #ifdef CONVERGED_TDLS_ENABLE
  1122. /**
  1123. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1124. * @tx_desc: TX descriptor
  1125. *
  1126. * Return: None
  1127. */
  1128. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1129. {
  1130. if (tx_desc->vdev) {
  1131. if (tx_desc->vdev->is_tdls_frame) {
  1132. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1133. tx_desc->vdev->is_tdls_frame = false;
  1134. }
  1135. }
  1136. }
  1137. /**
  1138. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1139. * @tx_desc: TX descriptor
  1140. * @vdev: datapath vdev handle
  1141. *
  1142. * Return: None
  1143. */
  1144. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1145. struct dp_vdev *vdev)
  1146. {
  1147. struct hal_tx_completion_status ts = {0};
  1148. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1149. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1150. if (vdev->tx_non_std_data_callback.func) {
  1151. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1152. vdev->tx_non_std_data_callback.func(
  1153. vdev->tx_non_std_data_callback.ctxt,
  1154. nbuf, ts.status);
  1155. return;
  1156. }
  1157. }
  1158. #endif
  1159. /**
  1160. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1161. * @vdev: DP vdev handle
  1162. * @nbuf: skb
  1163. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1164. * @meta_data: Metadata to the fw
  1165. * @tx_q: Tx queue to be used for this Tx frame
  1166. * @peer_id: peer_id of the peer in case of NAWDS frames
  1167. * @tx_exc_metadata: Handle that holds exception path metadata
  1168. *
  1169. * Return: NULL on success,
  1170. * nbuf when it fails to send
  1171. */
  1172. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1173. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1174. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1175. {
  1176. struct dp_pdev *pdev = vdev->pdev;
  1177. struct dp_soc *soc = pdev->soc;
  1178. struct dp_tx_desc_s *tx_desc;
  1179. QDF_STATUS status;
  1180. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1181. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1182. uint16_t htt_tcl_metadata = 0;
  1183. uint8_t tid = msdu_info->tid;
  1184. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1185. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1186. msdu_info, tx_exc_metadata);
  1187. if (!tx_desc) {
  1188. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1189. "%s Tx_desc prepare Fail vdev %pK queue %d",
  1190. __func__, vdev, tx_q->desc_pool_id);
  1191. return nbuf;
  1192. }
  1193. if (qdf_unlikely(soc->cce_disable)) {
  1194. if (dp_cce_classify(vdev, nbuf) == true) {
  1195. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1196. tid = DP_VO_TID;
  1197. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1198. }
  1199. }
  1200. dp_tx_update_tdls_flags(tx_desc);
  1201. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1202. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1203. "%s %d : HAL RING Access Failed -- %pK",
  1204. __func__, __LINE__, hal_srng);
  1205. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1206. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1207. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1208. goto fail_return;
  1209. }
  1210. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1211. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1212. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1213. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1214. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1215. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1216. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1217. peer_id);
  1218. } else
  1219. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1220. if (msdu_info->exception_fw) {
  1221. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1222. }
  1223. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1224. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1225. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1226. if (status != QDF_STATUS_SUCCESS) {
  1227. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1228. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1229. __func__, tx_desc, tx_q->ring_id);
  1230. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1231. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1232. goto fail_return;
  1233. }
  1234. nbuf = NULL;
  1235. fail_return:
  1236. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1237. hal_srng_access_end(soc->hal_soc, hal_srng);
  1238. hif_pm_runtime_put(soc->hif_handle);
  1239. } else {
  1240. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1241. }
  1242. return nbuf;
  1243. }
  1244. /**
  1245. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1246. * @vdev: DP vdev handle
  1247. * @nbuf: skb
  1248. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1249. *
  1250. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1251. *
  1252. * Return: NULL on success,
  1253. * nbuf when it fails to send
  1254. */
  1255. #if QDF_LOCK_STATS
  1256. static noinline
  1257. #else
  1258. static
  1259. #endif
  1260. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1261. struct dp_tx_msdu_info_s *msdu_info)
  1262. {
  1263. uint8_t i;
  1264. struct dp_pdev *pdev = vdev->pdev;
  1265. struct dp_soc *soc = pdev->soc;
  1266. struct dp_tx_desc_s *tx_desc;
  1267. bool is_cce_classified = false;
  1268. QDF_STATUS status;
  1269. uint16_t htt_tcl_metadata = 0;
  1270. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1271. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1272. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1273. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1274. "%s %d : HAL RING Access Failed -- %pK",
  1275. __func__, __LINE__, hal_srng);
  1276. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1277. return nbuf;
  1278. }
  1279. if (qdf_unlikely(soc->cce_disable)) {
  1280. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1281. if (is_cce_classified) {
  1282. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1283. msdu_info->tid = DP_VO_TID;
  1284. }
  1285. }
  1286. if (msdu_info->frm_type == dp_tx_frm_me)
  1287. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1288. i = 0;
  1289. /* Print statement to track i and num_seg */
  1290. /*
  1291. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1292. * descriptors using information in msdu_info
  1293. */
  1294. while (i < msdu_info->num_seg) {
  1295. /*
  1296. * Setup Tx descriptor for an MSDU, and MSDU extension
  1297. * descriptor
  1298. */
  1299. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1300. tx_q->desc_pool_id);
  1301. if (!tx_desc) {
  1302. if (msdu_info->frm_type == dp_tx_frm_me) {
  1303. dp_tx_me_free_buf(pdev,
  1304. (void *)(msdu_info->u.sg_info
  1305. .curr_seg->frags[0].vaddr));
  1306. }
  1307. goto done;
  1308. }
  1309. if (msdu_info->frm_type == dp_tx_frm_me) {
  1310. tx_desc->me_buffer =
  1311. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1312. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1313. }
  1314. if (is_cce_classified)
  1315. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1316. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1317. if (msdu_info->exception_fw) {
  1318. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1319. }
  1320. /*
  1321. * Enqueue the Tx MSDU descriptor to HW for transmit
  1322. */
  1323. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1324. htt_tcl_metadata, tx_q->ring_id, NULL);
  1325. if (status != QDF_STATUS_SUCCESS) {
  1326. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1327. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1328. __func__, tx_desc, tx_q->ring_id);
  1329. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1330. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1331. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1332. goto done;
  1333. }
  1334. /*
  1335. * TODO
  1336. * if tso_info structure can be modified to have curr_seg
  1337. * as first element, following 2 blocks of code (for TSO and SG)
  1338. * can be combined into 1
  1339. */
  1340. /*
  1341. * For frames with multiple segments (TSO, ME), jump to next
  1342. * segment.
  1343. */
  1344. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1345. if (msdu_info->u.tso_info.curr_seg->next) {
  1346. msdu_info->u.tso_info.curr_seg =
  1347. msdu_info->u.tso_info.curr_seg->next;
  1348. /*
  1349. * If this is a jumbo nbuf, then increment the number of
  1350. * nbuf users for each additional segment of the msdu.
  1351. * This will ensure that the skb is freed only after
  1352. * receiving tx completion for all segments of an nbuf
  1353. */
  1354. qdf_nbuf_inc_users(nbuf);
  1355. /* Check with MCL if this is needed */
  1356. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1357. }
  1358. }
  1359. /*
  1360. * For Multicast-Unicast converted packets,
  1361. * each converted frame (for a client) is represented as
  1362. * 1 segment
  1363. */
  1364. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1365. (msdu_info->frm_type == dp_tx_frm_me)) {
  1366. if (msdu_info->u.sg_info.curr_seg->next) {
  1367. msdu_info->u.sg_info.curr_seg =
  1368. msdu_info->u.sg_info.curr_seg->next;
  1369. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1370. }
  1371. }
  1372. i++;
  1373. }
  1374. nbuf = NULL;
  1375. done:
  1376. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1377. hal_srng_access_end(soc->hal_soc, hal_srng);
  1378. hif_pm_runtime_put(soc->hif_handle);
  1379. } else {
  1380. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1381. }
  1382. return nbuf;
  1383. }
  1384. /**
  1385. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1386. * for SG frames
  1387. * @vdev: DP vdev handle
  1388. * @nbuf: skb
  1389. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1390. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1391. *
  1392. * Return: NULL on success,
  1393. * nbuf when it fails to send
  1394. */
  1395. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1396. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1397. {
  1398. uint32_t cur_frag, nr_frags;
  1399. qdf_dma_addr_t paddr;
  1400. struct dp_tx_sg_info_s *sg_info;
  1401. sg_info = &msdu_info->u.sg_info;
  1402. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1403. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1404. QDF_DMA_TO_DEVICE)) {
  1405. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1406. "dma map error");
  1407. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1408. qdf_nbuf_free(nbuf);
  1409. return NULL;
  1410. }
  1411. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1412. seg_info->frags[0].paddr_lo = paddr;
  1413. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1414. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1415. seg_info->frags[0].vaddr = (void *) nbuf;
  1416. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1417. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1418. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1419. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1420. "frag dma map error");
  1421. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1422. qdf_nbuf_free(nbuf);
  1423. return NULL;
  1424. }
  1425. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1426. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1427. seg_info->frags[cur_frag + 1].paddr_hi =
  1428. ((uint64_t) paddr) >> 32;
  1429. seg_info->frags[cur_frag + 1].len =
  1430. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1431. }
  1432. seg_info->frag_cnt = (cur_frag + 1);
  1433. seg_info->total_len = qdf_nbuf_len(nbuf);
  1434. seg_info->next = NULL;
  1435. sg_info->curr_seg = seg_info;
  1436. msdu_info->frm_type = dp_tx_frm_sg;
  1437. msdu_info->num_seg = 1;
  1438. return nbuf;
  1439. }
  1440. #ifdef MESH_MODE_SUPPORT
  1441. /**
  1442. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1443. and prepare msdu_info for mesh frames.
  1444. * @vdev: DP vdev handle
  1445. * @nbuf: skb
  1446. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1447. *
  1448. * Return: NULL on failure,
  1449. * nbuf when extracted successfully
  1450. */
  1451. static
  1452. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1453. struct dp_tx_msdu_info_s *msdu_info)
  1454. {
  1455. struct meta_hdr_s *mhdr;
  1456. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1457. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1458. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1459. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1460. msdu_info->exception_fw = 0;
  1461. goto remove_meta_hdr;
  1462. }
  1463. msdu_info->exception_fw = 1;
  1464. qdf_mem_set(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t), 0);
  1465. meta_data->host_tx_desc_pool = 1;
  1466. meta_data->update_peer_cache = 1;
  1467. meta_data->learning_frame = 1;
  1468. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1469. meta_data->power = mhdr->power;
  1470. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1471. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1472. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1473. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1474. meta_data->dyn_bw = 1;
  1475. meta_data->valid_pwr = 1;
  1476. meta_data->valid_mcs_mask = 1;
  1477. meta_data->valid_nss_mask = 1;
  1478. meta_data->valid_preamble_type = 1;
  1479. meta_data->valid_retries = 1;
  1480. meta_data->valid_bw_info = 1;
  1481. }
  1482. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1483. meta_data->encrypt_type = 0;
  1484. meta_data->valid_encrypt_type = 1;
  1485. meta_data->learning_frame = 0;
  1486. }
  1487. meta_data->valid_key_flags = 1;
  1488. meta_data->key_flags = (mhdr->keyix & 0x3);
  1489. remove_meta_hdr:
  1490. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1491. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1492. "qdf_nbuf_pull_head failed");
  1493. qdf_nbuf_free(nbuf);
  1494. return NULL;
  1495. }
  1496. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1497. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1498. else
  1499. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1500. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1501. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1502. " tid %d to_fw %d",
  1503. __func__, msdu_info->meta_data[0],
  1504. msdu_info->meta_data[1],
  1505. msdu_info->meta_data[2],
  1506. msdu_info->meta_data[3],
  1507. msdu_info->meta_data[4],
  1508. msdu_info->meta_data[5],
  1509. msdu_info->tid, msdu_info->exception_fw);
  1510. return nbuf;
  1511. }
  1512. #else
  1513. static
  1514. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1515. struct dp_tx_msdu_info_s *msdu_info)
  1516. {
  1517. return nbuf;
  1518. }
  1519. #endif
  1520. #ifdef DP_FEATURE_NAWDS_TX
  1521. /**
  1522. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1523. * @vdev: dp_vdev handle
  1524. * @nbuf: skb
  1525. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1526. * @tx_q: Tx queue to be used for this Tx frame
  1527. * @meta_data: Meta date for mesh
  1528. * @peer_id: peer_id of the peer in case of NAWDS frames
  1529. *
  1530. * return: NULL on success nbuf on failure
  1531. */
  1532. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1533. struct dp_tx_msdu_info_s *msdu_info)
  1534. {
  1535. struct dp_peer *peer = NULL;
  1536. struct dp_soc *soc = vdev->pdev->soc;
  1537. struct dp_ast_entry *ast_entry = NULL;
  1538. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1539. uint16_t peer_id = HTT_INVALID_PEER;
  1540. struct dp_peer *sa_peer = NULL;
  1541. qdf_nbuf_t nbuf_copy;
  1542. qdf_spin_lock_bh(&(soc->ast_lock));
  1543. ast_entry = dp_peer_ast_hash_find_by_pdevid
  1544. (soc,
  1545. (uint8_t *)(eh->ether_shost),
  1546. vdev->pdev->pdev_id);
  1547. if (ast_entry)
  1548. sa_peer = ast_entry->peer;
  1549. qdf_spin_unlock_bh(&(soc->ast_lock));
  1550. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1551. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1552. (peer->nawds_enabled)) {
  1553. if (sa_peer == peer) {
  1554. QDF_TRACE(QDF_MODULE_ID_DP,
  1555. QDF_TRACE_LEVEL_DEBUG,
  1556. " %s: broadcast multicast packet",
  1557. __func__);
  1558. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  1559. continue;
  1560. }
  1561. nbuf_copy = qdf_nbuf_copy(nbuf);
  1562. if (!nbuf_copy) {
  1563. QDF_TRACE(QDF_MODULE_ID_DP,
  1564. QDF_TRACE_LEVEL_ERROR,
  1565. "nbuf copy failed");
  1566. }
  1567. peer_id = peer->peer_ids[0];
  1568. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy,
  1569. msdu_info, peer_id, NULL);
  1570. if (nbuf_copy != NULL) {
  1571. qdf_nbuf_free(nbuf_copy);
  1572. continue;
  1573. }
  1574. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  1575. 1, qdf_nbuf_len(nbuf));
  1576. }
  1577. }
  1578. if (peer_id == HTT_INVALID_PEER)
  1579. return nbuf;
  1580. return NULL;
  1581. }
  1582. #endif
  1583. /**
  1584. * dp_check_exc_metadata() - Checks if parameters are valid
  1585. * @tx_exc - holds all exception path parameters
  1586. *
  1587. * Returns true when all the parameters are valid else false
  1588. *
  1589. */
  1590. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1591. {
  1592. if ((tx_exc->tid > DP_MAX_TIDS && tx_exc->tid != HTT_INVALID_TID) ||
  1593. tx_exc->tx_encap_type > htt_cmn_pkt_num_types ||
  1594. tx_exc->sec_type > cdp_num_sec_types) {
  1595. return false;
  1596. }
  1597. return true;
  1598. }
  1599. /**
  1600. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1601. * @vap_dev: DP vdev handle
  1602. * @nbuf: skb
  1603. * @tx_exc_metadata: Handle that holds exception path meta data
  1604. *
  1605. * Entry point for Core Tx layer (DP_TX) invoked from
  1606. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1607. *
  1608. * Return: NULL on success,
  1609. * nbuf when it fails to send
  1610. */
  1611. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1612. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1613. {
  1614. struct ether_header *eh = NULL;
  1615. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1616. struct dp_tx_msdu_info_s msdu_info;
  1617. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1618. msdu_info.tid = tx_exc_metadata->tid;
  1619. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1620. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1621. "%s , skb %pM",
  1622. __func__, nbuf->data);
  1623. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1624. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1625. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1626. "Invalid parameters in exception path");
  1627. goto fail;
  1628. }
  1629. /* Basic sanity checks for unsupported packets */
  1630. /* MESH mode */
  1631. if (qdf_unlikely(vdev->mesh_vdev)) {
  1632. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1633. "Mesh mode is not supported in exception path");
  1634. goto fail;
  1635. }
  1636. /* TSO or SG */
  1637. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1638. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1639. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1640. "TSO and SG are not supported in exception path");
  1641. goto fail;
  1642. }
  1643. /* RAW */
  1644. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1645. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1646. "Raw frame is not supported in exception path");
  1647. goto fail;
  1648. }
  1649. /* Mcast enhancement*/
  1650. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1651. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1652. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1653. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1654. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1655. }
  1656. }
  1657. /*
  1658. * Get HW Queue to use for this frame.
  1659. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1660. * dedicated for data and 1 for command.
  1661. * "queue_id" maps to one hardware ring.
  1662. * With each ring, we also associate a unique Tx descriptor pool
  1663. * to minimize lock contention for these resources.
  1664. */
  1665. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1666. /* Single linear frame */
  1667. /*
  1668. * If nbuf is a simple linear frame, use send_single function to
  1669. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1670. * SRNG. There is no need to setup a MSDU extension descriptor.
  1671. */
  1672. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1673. tx_exc_metadata->peer_id, tx_exc_metadata);
  1674. return nbuf;
  1675. fail:
  1676. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1677. "pkt send failed");
  1678. return nbuf;
  1679. }
  1680. /**
  1681. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1682. * @vap_dev: DP vdev handle
  1683. * @nbuf: skb
  1684. *
  1685. * Entry point for Core Tx layer (DP_TX) invoked from
  1686. * hard_start_xmit in OSIF/HDD
  1687. *
  1688. * Return: NULL on success,
  1689. * nbuf when it fails to send
  1690. */
  1691. #ifdef MESH_MODE_SUPPORT
  1692. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1693. {
  1694. struct meta_hdr_s *mhdr;
  1695. qdf_nbuf_t nbuf_mesh = NULL;
  1696. qdf_nbuf_t nbuf_clone = NULL;
  1697. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1698. uint8_t no_enc_frame = 0;
  1699. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1700. if (nbuf_mesh == NULL) {
  1701. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1702. "qdf_nbuf_unshare failed");
  1703. return nbuf;
  1704. }
  1705. nbuf = nbuf_mesh;
  1706. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1707. if ((vdev->sec_type != cdp_sec_type_none) &&
  1708. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1709. no_enc_frame = 1;
  1710. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1711. !no_enc_frame) {
  1712. nbuf_clone = qdf_nbuf_clone(nbuf);
  1713. if (nbuf_clone == NULL) {
  1714. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1715. "qdf_nbuf_clone failed");
  1716. return nbuf;
  1717. }
  1718. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1719. }
  1720. if (nbuf_clone) {
  1721. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1722. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1723. } else {
  1724. qdf_nbuf_free(nbuf_clone);
  1725. }
  1726. }
  1727. if (no_enc_frame)
  1728. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1729. else
  1730. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1731. nbuf = dp_tx_send(vap_dev, nbuf);
  1732. if ((nbuf == NULL) && no_enc_frame) {
  1733. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1734. }
  1735. return nbuf;
  1736. }
  1737. #else
  1738. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1739. {
  1740. return dp_tx_send(vap_dev, nbuf);
  1741. }
  1742. #endif
  1743. /**
  1744. * dp_tx_send() - Transmit a frame on a given VAP
  1745. * @vap_dev: DP vdev handle
  1746. * @nbuf: skb
  1747. *
  1748. * Entry point for Core Tx layer (DP_TX) invoked from
  1749. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1750. * cases
  1751. *
  1752. * Return: NULL on success,
  1753. * nbuf when it fails to send
  1754. */
  1755. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1756. {
  1757. struct ether_header *eh = NULL;
  1758. struct dp_tx_msdu_info_s msdu_info;
  1759. struct dp_tx_seg_info_s seg_info;
  1760. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1761. uint16_t peer_id = HTT_INVALID_PEER;
  1762. qdf_nbuf_t nbuf_mesh = NULL;
  1763. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1764. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1765. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1766. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1767. "%s , skb %pM",
  1768. __func__, nbuf->data);
  1769. /*
  1770. * Set Default Host TID value to invalid TID
  1771. * (TID override disabled)
  1772. */
  1773. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1774. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1775. if (qdf_unlikely(vdev->mesh_vdev)) {
  1776. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1777. &msdu_info);
  1778. if (nbuf_mesh == NULL) {
  1779. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1780. "Extracting mesh metadata failed");
  1781. return nbuf;
  1782. }
  1783. nbuf = nbuf_mesh;
  1784. }
  1785. /*
  1786. * Get HW Queue to use for this frame.
  1787. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1788. * dedicated for data and 1 for command.
  1789. * "queue_id" maps to one hardware ring.
  1790. * With each ring, we also associate a unique Tx descriptor pool
  1791. * to minimize lock contention for these resources.
  1792. */
  1793. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1794. /*
  1795. * TCL H/W supports 2 DSCP-TID mapping tables.
  1796. * Table 1 - Default DSCP-TID mapping table
  1797. * Table 2 - 1 DSCP-TID override table
  1798. *
  1799. * If we need a different DSCP-TID mapping for this vap,
  1800. * call tid_classify to extract DSCP/ToS from frame and
  1801. * map to a TID and store in msdu_info. This is later used
  1802. * to fill in TCL Input descriptor (per-packet TID override).
  1803. */
  1804. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1805. /*
  1806. * Classify the frame and call corresponding
  1807. * "prepare" function which extracts the segment (TSO)
  1808. * and fragmentation information (for TSO , SG, ME, or Raw)
  1809. * into MSDU_INFO structure which is later used to fill
  1810. * SW and HW descriptors.
  1811. */
  1812. if (qdf_nbuf_is_tso(nbuf)) {
  1813. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1814. "%s TSO frame %pK", __func__, vdev);
  1815. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1816. qdf_nbuf_len(nbuf));
  1817. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1818. DP_STATS_INC_PKT(vdev, tx_i.tso.dropped_host, 1,
  1819. qdf_nbuf_len(nbuf));
  1820. return nbuf;
  1821. }
  1822. goto send_multiple;
  1823. }
  1824. /* SG */
  1825. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1826. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1827. if (!nbuf)
  1828. return NULL;
  1829. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1830. "%s non-TSO SG frame %pK", __func__, vdev);
  1831. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1832. qdf_nbuf_len(nbuf));
  1833. goto send_multiple;
  1834. }
  1835. #ifdef ATH_SUPPORT_IQUE
  1836. /* Mcast to Ucast Conversion*/
  1837. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1838. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1839. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1840. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1841. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1842. "%s Mcast frm for ME %pK", __func__, vdev);
  1843. DP_STATS_INC_PKT(vdev,
  1844. tx_i.mcast_en.mcast_pkt, 1,
  1845. qdf_nbuf_len(nbuf));
  1846. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1847. QDF_STATUS_SUCCESS) {
  1848. return NULL;
  1849. }
  1850. }
  1851. }
  1852. #endif
  1853. /* RAW */
  1854. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1855. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1856. if (nbuf == NULL)
  1857. return NULL;
  1858. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1859. "%s Raw frame %pK", __func__, vdev);
  1860. goto send_multiple;
  1861. }
  1862. /* Single linear frame */
  1863. /*
  1864. * If nbuf is a simple linear frame, use send_single function to
  1865. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1866. * SRNG. There is no need to setup a MSDU extension descriptor.
  1867. */
  1868. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1869. return nbuf;
  1870. send_multiple:
  1871. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1872. return nbuf;
  1873. }
  1874. /**
  1875. * dp_tx_reinject_handler() - Tx Reinject Handler
  1876. * @tx_desc: software descriptor head pointer
  1877. * @status : Tx completion status from HTT descriptor
  1878. *
  1879. * This function reinjects frames back to Target.
  1880. * Todo - Host queue needs to be added
  1881. *
  1882. * Return: none
  1883. */
  1884. static
  1885. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1886. {
  1887. struct dp_vdev *vdev;
  1888. struct dp_peer *peer = NULL;
  1889. uint32_t peer_id = HTT_INVALID_PEER;
  1890. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1891. qdf_nbuf_t nbuf_copy = NULL;
  1892. struct dp_tx_msdu_info_s msdu_info;
  1893. struct dp_peer *sa_peer = NULL;
  1894. struct dp_ast_entry *ast_entry = NULL;
  1895. struct dp_soc *soc = NULL;
  1896. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1897. #ifdef WDS_VENDOR_EXTENSION
  1898. int is_mcast = 0, is_ucast = 0;
  1899. int num_peers_3addr = 0;
  1900. struct ether_header *eth_hdr = (struct ether_header *)(qdf_nbuf_data(nbuf));
  1901. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1902. #endif
  1903. vdev = tx_desc->vdev;
  1904. soc = vdev->pdev->soc;
  1905. qdf_assert(vdev);
  1906. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1907. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1908. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1909. "%s Tx reinject path", __func__);
  1910. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1911. qdf_nbuf_len(tx_desc->nbuf));
  1912. qdf_spin_lock_bh(&(soc->ast_lock));
  1913. ast_entry = dp_peer_ast_hash_find_by_pdevid
  1914. (soc,
  1915. (uint8_t *)(eh->ether_shost),
  1916. vdev->pdev->pdev_id);
  1917. if (ast_entry)
  1918. sa_peer = ast_entry->peer;
  1919. qdf_spin_unlock_bh(&(soc->ast_lock));
  1920. #ifdef WDS_VENDOR_EXTENSION
  1921. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1922. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1923. } else {
  1924. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1925. }
  1926. is_ucast = !is_mcast;
  1927. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1928. if (peer->bss_peer)
  1929. continue;
  1930. /* Detect wds peers that use 3-addr framing for mcast.
  1931. * if there are any, the bss_peer is used to send the
  1932. * the mcast frame using 3-addr format. all wds enabled
  1933. * peers that use 4-addr framing for mcast frames will
  1934. * be duplicated and sent as 4-addr frames below.
  1935. */
  1936. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1937. num_peers_3addr = 1;
  1938. break;
  1939. }
  1940. }
  1941. #endif
  1942. if (qdf_unlikely(vdev->mesh_vdev)) {
  1943. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1944. } else {
  1945. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1946. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1947. #ifdef WDS_VENDOR_EXTENSION
  1948. /*
  1949. * . if 3-addr STA, then send on BSS Peer
  1950. * . if Peer WDS enabled and accept 4-addr mcast,
  1951. * send mcast on that peer only
  1952. * . if Peer WDS enabled and accept 4-addr ucast,
  1953. * send ucast on that peer only
  1954. */
  1955. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1956. (peer->wds_enabled &&
  1957. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1958. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1959. #else
  1960. ((peer->bss_peer &&
  1961. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1962. peer->nawds_enabled)) {
  1963. #endif
  1964. peer_id = DP_INVALID_PEER;
  1965. if (peer->nawds_enabled) {
  1966. peer_id = peer->peer_ids[0];
  1967. if (sa_peer == peer) {
  1968. QDF_TRACE(
  1969. QDF_MODULE_ID_DP,
  1970. QDF_TRACE_LEVEL_DEBUG,
  1971. " %s: multicast packet",
  1972. __func__);
  1973. DP_STATS_INC(peer,
  1974. tx.nawds_mcast_drop, 1);
  1975. continue;
  1976. }
  1977. }
  1978. nbuf_copy = qdf_nbuf_copy(nbuf);
  1979. if (!nbuf_copy) {
  1980. QDF_TRACE(QDF_MODULE_ID_DP,
  1981. QDF_TRACE_LEVEL_DEBUG,
  1982. FL("nbuf copy failed"));
  1983. break;
  1984. }
  1985. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1986. nbuf_copy,
  1987. &msdu_info,
  1988. peer_id,
  1989. NULL);
  1990. if (nbuf_copy) {
  1991. QDF_TRACE(QDF_MODULE_ID_DP,
  1992. QDF_TRACE_LEVEL_DEBUG,
  1993. FL("pkt send failed"));
  1994. qdf_nbuf_free(nbuf_copy);
  1995. } else {
  1996. if (peer_id != DP_INVALID_PEER)
  1997. DP_STATS_INC_PKT(peer,
  1998. tx.nawds_mcast,
  1999. 1, qdf_nbuf_len(nbuf));
  2000. }
  2001. }
  2002. }
  2003. }
  2004. if (vdev->nawds_enabled) {
  2005. peer_id = DP_INVALID_PEER;
  2006. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2007. 1, qdf_nbuf_len(nbuf));
  2008. nbuf = dp_tx_send_msdu_single(vdev,
  2009. nbuf,
  2010. &msdu_info,
  2011. peer_id, NULL);
  2012. if (nbuf) {
  2013. QDF_TRACE(QDF_MODULE_ID_DP,
  2014. QDF_TRACE_LEVEL_DEBUG,
  2015. FL("pkt send failed"));
  2016. qdf_nbuf_free(nbuf);
  2017. }
  2018. } else
  2019. qdf_nbuf_free(nbuf);
  2020. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2021. }
  2022. /**
  2023. * dp_tx_inspect_handler() - Tx Inspect Handler
  2024. * @tx_desc: software descriptor head pointer
  2025. * @status : Tx completion status from HTT descriptor
  2026. *
  2027. * Handles Tx frames sent back to Host for inspection
  2028. * (ProxyARP)
  2029. *
  2030. * Return: none
  2031. */
  2032. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2033. {
  2034. struct dp_soc *soc;
  2035. struct dp_pdev *pdev = tx_desc->pdev;
  2036. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2037. "%s Tx inspect path",
  2038. __func__);
  2039. qdf_assert(pdev);
  2040. soc = pdev->soc;
  2041. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2042. qdf_nbuf_len(tx_desc->nbuf));
  2043. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2044. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2045. }
  2046. #ifdef FEATURE_PERPKT_INFO
  2047. /**
  2048. * dp_get_completion_indication_for_stack() - send completion to stack
  2049. * @soc : dp_soc handle
  2050. * @pdev: dp_pdev handle
  2051. * @peer: dp peer handle
  2052. * @ts: transmit completion status structure
  2053. * @netbuf: Buffer pointer for free
  2054. *
  2055. * This function is used for indication whether buffer needs to be
  2056. * sent to stack for freeing or not
  2057. */
  2058. QDF_STATUS
  2059. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2060. struct dp_pdev *pdev,
  2061. struct dp_peer *peer,
  2062. struct hal_tx_completion_status *ts,
  2063. qdf_nbuf_t netbuf)
  2064. {
  2065. struct tx_capture_hdr *ppdu_hdr;
  2066. uint16_t peer_id = ts->peer_id;
  2067. uint32_t ppdu_id = ts->ppdu_id;
  2068. uint8_t first_msdu = ts->first_msdu;
  2069. uint8_t last_msdu = ts->last_msdu;
  2070. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode))
  2071. return QDF_STATUS_E_NOSUPPORT;
  2072. if (!peer) {
  2073. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2074. FL("Peer Invalid"));
  2075. return QDF_STATUS_E_INVAL;
  2076. }
  2077. if (pdev->mcopy_mode) {
  2078. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2079. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2080. return QDF_STATUS_E_INVAL;
  2081. }
  2082. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2083. pdev->m_copy_id.tx_peer_id = peer_id;
  2084. }
  2085. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2086. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2087. FL("No headroom"));
  2088. return QDF_STATUS_E_NOMEM;
  2089. }
  2090. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2091. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2092. IEEE80211_ADDR_LEN);
  2093. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2094. IEEE80211_ADDR_LEN);
  2095. ppdu_hdr->ppdu_id = ppdu_id;
  2096. ppdu_hdr->peer_id = peer_id;
  2097. ppdu_hdr->first_msdu = first_msdu;
  2098. ppdu_hdr->last_msdu = last_msdu;
  2099. return QDF_STATUS_SUCCESS;
  2100. }
  2101. /**
  2102. * dp_send_completion_to_stack() - send completion to stack
  2103. * @soc : dp_soc handle
  2104. * @pdev: dp_pdev handle
  2105. * @peer_id: peer_id of the peer for which completion came
  2106. * @ppdu_id: ppdu_id
  2107. * @netbuf: Buffer pointer for free
  2108. *
  2109. * This function is used to send completion to stack
  2110. * to free buffer
  2111. */
  2112. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2113. uint16_t peer_id, uint32_t ppdu_id,
  2114. qdf_nbuf_t netbuf)
  2115. {
  2116. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2117. netbuf, peer_id,
  2118. WDI_NO_VAL, pdev->pdev_id);
  2119. }
  2120. #else
  2121. static QDF_STATUS
  2122. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2123. struct dp_pdev *pdev,
  2124. struct dp_peer *peer,
  2125. struct hal_tx_completion_status *ts,
  2126. qdf_nbuf_t netbuf)
  2127. {
  2128. return QDF_STATUS_E_NOSUPPORT;
  2129. }
  2130. static void
  2131. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2132. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2133. {
  2134. }
  2135. #endif
  2136. /**
  2137. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2138. * @soc: Soc handle
  2139. * @desc: software Tx descriptor to be processed
  2140. *
  2141. * Return: none
  2142. */
  2143. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2144. struct dp_tx_desc_s *desc)
  2145. {
  2146. struct dp_vdev *vdev = desc->vdev;
  2147. qdf_nbuf_t nbuf = desc->nbuf;
  2148. /* If it is TDLS mgmt, don't unmap or free the frame */
  2149. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2150. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2151. /* 0 : MSDU buffer, 1 : MLE */
  2152. if (desc->msdu_ext_desc) {
  2153. /* TSO free */
  2154. if (hal_tx_ext_desc_get_tso_enable(
  2155. desc->msdu_ext_desc->vaddr)) {
  2156. /* unmap eash TSO seg before free the nbuf */
  2157. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2158. desc->tso_num_desc);
  2159. qdf_nbuf_free(nbuf);
  2160. return;
  2161. }
  2162. }
  2163. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2164. if (qdf_likely(!vdev->mesh_vdev))
  2165. qdf_nbuf_free(nbuf);
  2166. else {
  2167. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2168. qdf_nbuf_free(nbuf);
  2169. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2170. } else
  2171. vdev->osif_tx_free_ext((nbuf));
  2172. }
  2173. }
  2174. /**
  2175. * dp_tx_mec_handler() - Tx MEC Notify Handler
  2176. * @vdev: pointer to dp dev handler
  2177. * @status : Tx completion status from HTT descriptor
  2178. *
  2179. * Handles MEC notify event sent from fw to Host
  2180. *
  2181. * Return: none
  2182. */
  2183. #ifdef FEATURE_WDS
  2184. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  2185. {
  2186. struct dp_soc *soc;
  2187. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  2188. struct dp_peer *peer;
  2189. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  2190. if (!vdev->mec_enabled)
  2191. return;
  2192. /* MEC required only in STA mode */
  2193. if (vdev->opmode != wlan_op_mode_sta)
  2194. return;
  2195. soc = vdev->pdev->soc;
  2196. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2197. peer = TAILQ_FIRST(&vdev->peer_list);
  2198. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2199. if (!peer) {
  2200. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2201. FL("peer is NULL"));
  2202. return;
  2203. }
  2204. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2205. "%s Tx MEC Handler",
  2206. __func__);
  2207. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  2208. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  2209. status[(DP_MAC_ADDR_LEN - 2) + i];
  2210. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, DP_MAC_ADDR_LEN))
  2211. dp_peer_add_ast(soc,
  2212. peer,
  2213. mac_addr,
  2214. CDP_TXRX_AST_TYPE_MEC,
  2215. flags);
  2216. }
  2217. #endif
  2218. #ifdef MESH_MODE_SUPPORT
  2219. /**
  2220. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2221. * in mesh meta header
  2222. * @tx_desc: software descriptor head pointer
  2223. * @ts: pointer to tx completion stats
  2224. * Return: none
  2225. */
  2226. static
  2227. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2228. struct hal_tx_completion_status *ts)
  2229. {
  2230. struct meta_hdr_s *mhdr;
  2231. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2232. if (!tx_desc->msdu_ext_desc) {
  2233. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2234. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2235. "netbuf %pK offset %d",
  2236. netbuf, tx_desc->pkt_offset);
  2237. return;
  2238. }
  2239. }
  2240. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2241. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2242. "netbuf %pK offset %d", netbuf,
  2243. sizeof(struct meta_hdr_s));
  2244. return;
  2245. }
  2246. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2247. mhdr->rssi = ts->ack_frame_rssi;
  2248. mhdr->channel = tx_desc->pdev->operating_channel;
  2249. }
  2250. #else
  2251. static
  2252. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2253. struct hal_tx_completion_status *ts)
  2254. {
  2255. }
  2256. #endif
  2257. /**
  2258. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2259. * @peer: Handle to DP peer
  2260. * @ts: pointer to HAL Tx completion stats
  2261. *
  2262. * Return: None
  2263. */
  2264. static inline void
  2265. dp_tx_update_peer_stats(struct dp_peer *peer,
  2266. struct hal_tx_completion_status *ts, uint32_t length)
  2267. {
  2268. struct dp_pdev *pdev = peer->vdev->pdev;
  2269. struct dp_soc *soc = NULL;
  2270. uint8_t mcs, pkt_type;
  2271. if (!pdev)
  2272. return;
  2273. soc = pdev->soc;
  2274. mcs = ts->mcs;
  2275. pkt_type = ts->pkt_type;
  2276. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2277. dp_err("Release source is not from TQM");
  2278. return;
  2279. }
  2280. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2281. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2282. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2283. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2284. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2285. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2286. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2287. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2288. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2289. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2290. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2291. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2292. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2293. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2294. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2295. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2296. return;
  2297. }
  2298. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2299. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2300. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2301. /*
  2302. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2303. * Return from here if HTT PPDU events are enabled.
  2304. */
  2305. if (!(soc->process_tx_status))
  2306. return;
  2307. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2308. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2309. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2310. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2311. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2312. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2313. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2314. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2315. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2316. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2317. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2318. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2319. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2320. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2321. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2322. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2323. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2324. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2325. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2326. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2327. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2328. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2329. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2330. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2331. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2332. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2333. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2334. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2335. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2336. &peer->stats, ts->peer_id,
  2337. UPDATE_PEER_STATS, pdev->pdev_id);
  2338. #endif
  2339. }
  2340. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2341. /**
  2342. * dp_tx_flow_pool_lock() - take flow pool lock
  2343. * @soc: core txrx main context
  2344. * @tx_desc: tx desc
  2345. *
  2346. * Return: None
  2347. */
  2348. static inline
  2349. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2350. struct dp_tx_desc_s *tx_desc)
  2351. {
  2352. struct dp_tx_desc_pool_s *pool;
  2353. uint8_t desc_pool_id;
  2354. desc_pool_id = tx_desc->pool_id;
  2355. pool = &soc->tx_desc[desc_pool_id];
  2356. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2357. }
  2358. /**
  2359. * dp_tx_flow_pool_unlock() - release flow pool lock
  2360. * @soc: core txrx main context
  2361. * @tx_desc: tx desc
  2362. *
  2363. * Return: None
  2364. */
  2365. static inline
  2366. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2367. struct dp_tx_desc_s *tx_desc)
  2368. {
  2369. struct dp_tx_desc_pool_s *pool;
  2370. uint8_t desc_pool_id;
  2371. desc_pool_id = tx_desc->pool_id;
  2372. pool = &soc->tx_desc[desc_pool_id];
  2373. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2374. }
  2375. #else
  2376. static inline
  2377. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2378. {
  2379. }
  2380. static inline
  2381. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2382. {
  2383. }
  2384. #endif
  2385. /**
  2386. * dp_tx_notify_completion() - Notify tx completion for this desc
  2387. * @soc: core txrx main context
  2388. * @tx_desc: tx desc
  2389. * @netbuf: buffer
  2390. *
  2391. * Return: none
  2392. */
  2393. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2394. struct dp_tx_desc_s *tx_desc,
  2395. qdf_nbuf_t netbuf)
  2396. {
  2397. void *osif_dev;
  2398. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2399. qdf_assert(tx_desc);
  2400. dp_tx_flow_pool_lock(soc, tx_desc);
  2401. if (!tx_desc->vdev ||
  2402. !tx_desc->vdev->osif_vdev) {
  2403. dp_tx_flow_pool_unlock(soc, tx_desc);
  2404. return;
  2405. }
  2406. osif_dev = tx_desc->vdev->osif_vdev;
  2407. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2408. dp_tx_flow_pool_unlock(soc, tx_desc);
  2409. if (tx_compl_cbk)
  2410. tx_compl_cbk(netbuf, osif_dev);
  2411. }
  2412. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2413. * @pdev: pdev handle
  2414. * @tid: tid value
  2415. * @txdesc_ts: timestamp from txdesc
  2416. * @ppdu_id: ppdu id
  2417. *
  2418. * Return: none
  2419. */
  2420. #ifdef FEATURE_PERPKT_INFO
  2421. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2422. uint8_t tid,
  2423. uint64_t txdesc_ts,
  2424. uint32_t ppdu_id)
  2425. {
  2426. uint64_t delta_ms;
  2427. struct cdp_tx_sojourn_stats *sojourn_stats;
  2428. if (pdev->enhanced_stats_en == 0)
  2429. return;
  2430. if (pdev->sojourn_stats.ppdu_seq_id == 0)
  2431. pdev->sojourn_stats.ppdu_seq_id = ppdu_id;
  2432. if (ppdu_id != pdev->sojourn_stats.ppdu_seq_id) {
  2433. if (!pdev->sojourn_buf)
  2434. return;
  2435. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2436. qdf_nbuf_data(pdev->sojourn_buf);
  2437. qdf_mem_copy(sojourn_stats, &pdev->sojourn_stats,
  2438. sizeof(struct cdp_tx_sojourn_stats));
  2439. qdf_mem_zero(&pdev->sojourn_stats,
  2440. sizeof(struct cdp_tx_sojourn_stats));
  2441. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2442. pdev->sojourn_buf, HTT_INVALID_PEER,
  2443. WDI_NO_VAL, pdev->pdev_id);
  2444. pdev->sojourn_stats.ppdu_seq_id = ppdu_id;
  2445. }
  2446. if (tid == HTT_INVALID_TID)
  2447. return;
  2448. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2449. txdesc_ts;
  2450. qdf_ewma_tx_lag_add(&pdev->sojourn_stats.avg_sojourn_msdu[tid],
  2451. delta_ms);
  2452. pdev->sojourn_stats.sum_sojourn_msdu[tid] += delta_ms;
  2453. pdev->sojourn_stats.num_msdus[tid]++;
  2454. }
  2455. #else
  2456. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2457. uint8_t tid,
  2458. uint64_t txdesc_ts,
  2459. uint32_t ppdu_id)
  2460. {
  2461. }
  2462. #endif
  2463. /**
  2464. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2465. * @soc: DP Soc handle
  2466. * @tx_desc: software Tx descriptor
  2467. * @ts : Tx completion status from HAL/HTT descriptor
  2468. *
  2469. * Return: none
  2470. */
  2471. static inline void
  2472. dp_tx_comp_process_desc(struct dp_soc *soc,
  2473. struct dp_tx_desc_s *desc,
  2474. struct hal_tx_completion_status *ts,
  2475. struct dp_peer *peer)
  2476. {
  2477. /*
  2478. * m_copy/tx_capture modes are not supported for
  2479. * scatter gather packets
  2480. */
  2481. if (!(desc->msdu_ext_desc) &&
  2482. (dp_get_completion_indication_for_stack(soc, desc->pdev,
  2483. peer, ts, desc->nbuf)
  2484. == QDF_STATUS_SUCCESS)) {
  2485. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2486. QDF_DMA_TO_DEVICE);
  2487. dp_send_completion_to_stack(soc, desc->pdev, ts->peer_id,
  2488. ts->ppdu_id, desc->nbuf);
  2489. } else {
  2490. dp_tx_comp_free_buf(soc, desc);
  2491. }
  2492. }
  2493. /**
  2494. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2495. * @tx_desc: software descriptor head pointer
  2496. * @ts: Tx completion status
  2497. * @peer: peer handle
  2498. *
  2499. * Return: none
  2500. */
  2501. static inline
  2502. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2503. struct hal_tx_completion_status *ts,
  2504. struct dp_peer *peer)
  2505. {
  2506. uint32_t length;
  2507. struct dp_soc *soc = NULL;
  2508. struct dp_vdev *vdev = tx_desc->vdev;
  2509. struct ether_header *eh =
  2510. (struct ether_header *)qdf_nbuf_data(tx_desc->nbuf);
  2511. if (!vdev) {
  2512. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2513. "invalid vdev");
  2514. goto out;
  2515. }
  2516. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2517. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2518. QDF_TRACE_DEFAULT_PDEV_ID,
  2519. qdf_nbuf_data_addr(tx_desc->nbuf),
  2520. sizeof(qdf_nbuf_data(tx_desc->nbuf)),
  2521. tx_desc->id,
  2522. ts->status));
  2523. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2524. "-------------------- \n"
  2525. "Tx Completion Stats: \n"
  2526. "-------------------- \n"
  2527. "ack_frame_rssi = %d \n"
  2528. "first_msdu = %d \n"
  2529. "last_msdu = %d \n"
  2530. "msdu_part_of_amsdu = %d \n"
  2531. "rate_stats valid = %d \n"
  2532. "bw = %d \n"
  2533. "pkt_type = %d \n"
  2534. "stbc = %d \n"
  2535. "ldpc = %d \n"
  2536. "sgi = %d \n"
  2537. "mcs = %d \n"
  2538. "ofdma = %d \n"
  2539. "tones_in_ru = %d \n"
  2540. "tsf = %d \n"
  2541. "ppdu_id = %d \n"
  2542. "transmit_cnt = %d \n"
  2543. "tid = %d \n"
  2544. "peer_id = %d\n",
  2545. ts->ack_frame_rssi, ts->first_msdu,
  2546. ts->last_msdu, ts->msdu_part_of_amsdu,
  2547. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2548. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2549. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2550. ts->transmit_cnt, ts->tid, ts->peer_id);
  2551. soc = vdev->pdev->soc;
  2552. /* Update SoC level stats */
  2553. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2554. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2555. /* Update per-packet stats for mesh mode */
  2556. if (qdf_unlikely(vdev->mesh_vdev) &&
  2557. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2558. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2559. length = qdf_nbuf_len(tx_desc->nbuf);
  2560. /* Update peer level stats */
  2561. if (!peer) {
  2562. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2563. "peer is null or deletion in progress");
  2564. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2565. goto out;
  2566. }
  2567. if (qdf_likely(!peer->bss_peer)) {
  2568. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2569. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2570. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2571. } else {
  2572. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2573. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2574. if ((peer->vdev->tx_encap_type ==
  2575. htt_cmn_pkt_type_ethernet) &&
  2576. IEEE80211_IS_BROADCAST(eh->ether_dhost)) {
  2577. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2578. }
  2579. }
  2580. }
  2581. dp_tx_update_peer_stats(peer, ts, length);
  2582. out:
  2583. return;
  2584. }
  2585. /**
  2586. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2587. * @soc: core txrx main context
  2588. * @comp_head: software descriptor head pointer
  2589. *
  2590. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2591. * and release the software descriptors after processing is complete
  2592. *
  2593. * Return: none
  2594. */
  2595. static void
  2596. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2597. struct dp_tx_desc_s *comp_head)
  2598. {
  2599. struct dp_tx_desc_s *desc;
  2600. struct dp_tx_desc_s *next;
  2601. struct hal_tx_completion_status ts = {0};
  2602. struct dp_peer *peer;
  2603. DP_HIST_INIT();
  2604. desc = comp_head;
  2605. while (desc) {
  2606. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2607. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2608. dp_tx_comp_process_tx_status(desc, &ts, peer);
  2609. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2610. if (peer)
  2611. dp_peer_unref_del_find_by_id(peer);
  2612. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  2613. next = desc->next;
  2614. dp_tx_desc_release(desc, desc->pool_id);
  2615. desc = next;
  2616. }
  2617. DP_TX_HIST_STATS_PER_PDEV();
  2618. }
  2619. /**
  2620. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2621. * @tx_desc: software descriptor head pointer
  2622. * @status : Tx completion status from HTT descriptor
  2623. *
  2624. * This function will process HTT Tx indication messages from Target
  2625. *
  2626. * Return: none
  2627. */
  2628. static
  2629. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2630. {
  2631. uint8_t tx_status;
  2632. struct dp_pdev *pdev;
  2633. struct dp_vdev *vdev;
  2634. struct dp_soc *soc;
  2635. struct hal_tx_completion_status ts = {0};
  2636. uint32_t *htt_desc = (uint32_t *)status;
  2637. struct dp_peer *peer;
  2638. qdf_assert(tx_desc->pdev);
  2639. pdev = tx_desc->pdev;
  2640. vdev = tx_desc->vdev;
  2641. soc = pdev->soc;
  2642. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2643. switch (tx_status) {
  2644. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2645. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2646. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2647. {
  2648. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2649. ts.peer_id =
  2650. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2651. htt_desc[2]);
  2652. ts.tid =
  2653. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2654. htt_desc[2]);
  2655. } else {
  2656. ts.peer_id = HTT_INVALID_PEER;
  2657. ts.tid = HTT_INVALID_TID;
  2658. }
  2659. ts.ppdu_id =
  2660. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2661. htt_desc[1]);
  2662. ts.ack_frame_rssi =
  2663. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2664. htt_desc[1]);
  2665. ts.first_msdu = 1;
  2666. ts.last_msdu = 1;
  2667. if (tx_status != HTT_TX_FW2WBM_TX_STATUS_OK)
  2668. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  2669. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2670. if (qdf_likely(peer))
  2671. dp_peer_unref_del_find_by_id(peer);
  2672. dp_tx_comp_process_tx_status(tx_desc, &ts, peer);
  2673. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2674. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2675. break;
  2676. }
  2677. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2678. {
  2679. dp_tx_reinject_handler(tx_desc, status);
  2680. break;
  2681. }
  2682. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2683. {
  2684. dp_tx_inspect_handler(tx_desc, status);
  2685. break;
  2686. }
  2687. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2688. {
  2689. dp_tx_mec_handler(vdev, status);
  2690. break;
  2691. }
  2692. default:
  2693. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2694. "%s Invalid HTT tx_status %d\n",
  2695. __func__, tx_status);
  2696. break;
  2697. }
  2698. }
  2699. /**
  2700. * dp_tx_comp_handler() - Tx completion handler
  2701. * @soc: core txrx main context
  2702. * @ring_id: completion ring id
  2703. * @quota: No. of packets/descriptors that can be serviced in one loop
  2704. *
  2705. * This function will collect hardware release ring element contents and
  2706. * handle descriptor contents. Based on contents, free packet or handle error
  2707. * conditions
  2708. *
  2709. * Return: none
  2710. */
  2711. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  2712. {
  2713. void *tx_comp_hal_desc;
  2714. uint8_t buffer_src;
  2715. uint8_t pool_id;
  2716. uint32_t tx_desc_id;
  2717. struct dp_tx_desc_s *tx_desc = NULL;
  2718. struct dp_tx_desc_s *head_desc = NULL;
  2719. struct dp_tx_desc_s *tail_desc = NULL;
  2720. uint32_t num_processed;
  2721. uint32_t count;
  2722. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2723. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2724. "%s %d : HAL RING Access Failed -- %pK",
  2725. __func__, __LINE__, hal_srng);
  2726. return 0;
  2727. }
  2728. num_processed = 0;
  2729. count = 0;
  2730. /* Find head descriptor from completion ring */
  2731. while (qdf_likely(tx_comp_hal_desc =
  2732. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2733. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2734. /* If this buffer was not released by TQM or FW, then it is not
  2735. * Tx completion indication, assert */
  2736. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2737. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2738. QDF_TRACE(QDF_MODULE_ID_DP,
  2739. QDF_TRACE_LEVEL_FATAL,
  2740. "Tx comp release_src != TQM | FW");
  2741. qdf_assert_always(0);
  2742. }
  2743. /* Get descriptor id */
  2744. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2745. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2746. DP_TX_DESC_ID_POOL_OS;
  2747. if (!dp_tx_is_desc_id_valid(soc, tx_desc_id))
  2748. continue;
  2749. /* Find Tx descriptor */
  2750. tx_desc = dp_tx_desc_find(soc, pool_id,
  2751. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2752. DP_TX_DESC_ID_PAGE_OS,
  2753. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2754. DP_TX_DESC_ID_OFFSET_OS);
  2755. /*
  2756. * If the descriptor is already freed in vdev_detach,
  2757. * continue to next descriptor
  2758. */
  2759. if (!tx_desc->vdev) {
  2760. QDF_TRACE(QDF_MODULE_ID_DP,
  2761. QDF_TRACE_LEVEL_INFO,
  2762. "Descriptor freed in vdev_detach %d",
  2763. tx_desc_id);
  2764. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2765. count++;
  2766. continue;
  2767. }
  2768. /*
  2769. * If the release source is FW, process the HTT status
  2770. */
  2771. if (qdf_unlikely(buffer_src ==
  2772. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2773. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2774. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2775. htt_tx_status);
  2776. dp_tx_process_htt_completion(tx_desc,
  2777. htt_tx_status);
  2778. } else {
  2779. /* Pool id is not matching. Error */
  2780. if (tx_desc->pool_id != pool_id) {
  2781. QDF_TRACE(QDF_MODULE_ID_DP,
  2782. QDF_TRACE_LEVEL_FATAL,
  2783. "Tx Comp pool id %d not matched %d",
  2784. pool_id, tx_desc->pool_id);
  2785. qdf_assert_always(0);
  2786. }
  2787. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2788. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2789. QDF_TRACE(QDF_MODULE_ID_DP,
  2790. QDF_TRACE_LEVEL_FATAL,
  2791. "Txdesc invalid, flgs = %x,id = %d",
  2792. tx_desc->flags, tx_desc_id);
  2793. qdf_assert_always(0);
  2794. }
  2795. /* First ring descriptor on the cycle */
  2796. if (!head_desc) {
  2797. head_desc = tx_desc;
  2798. tail_desc = tx_desc;
  2799. }
  2800. tail_desc->next = tx_desc;
  2801. tx_desc->next = NULL;
  2802. tail_desc = tx_desc;
  2803. /* Collect hw completion contents */
  2804. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2805. &tx_desc->comp, 1);
  2806. }
  2807. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2808. /*
  2809. * Processed packet count is more than given quota
  2810. * stop to processing
  2811. */
  2812. if ((num_processed >= quota))
  2813. break;
  2814. count++;
  2815. }
  2816. hal_srng_access_end(soc->hal_soc, hal_srng);
  2817. /* Process the reaped descriptors */
  2818. if (head_desc)
  2819. dp_tx_comp_process_desc_list(soc, head_desc);
  2820. return num_processed;
  2821. }
  2822. #ifdef CONVERGED_TDLS_ENABLE
  2823. /**
  2824. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2825. *
  2826. * @data_vdev - which vdev should transmit the tx data frames
  2827. * @tx_spec - what non-standard handling to apply to the tx data frames
  2828. * @msdu_list - NULL-terminated list of tx MSDUs
  2829. *
  2830. * Return: NULL on success,
  2831. * nbuf when it fails to send
  2832. */
  2833. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2834. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2835. {
  2836. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2837. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2838. vdev->is_tdls_frame = true;
  2839. return dp_tx_send(vdev_handle, msdu_list);
  2840. }
  2841. #endif
  2842. /**
  2843. * dp_tx_vdev_attach() - attach vdev to dp tx
  2844. * @vdev: virtual device instance
  2845. *
  2846. * Return: QDF_STATUS_SUCCESS: success
  2847. * QDF_STATUS_E_RESOURCES: Error return
  2848. */
  2849. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2850. {
  2851. /*
  2852. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2853. */
  2854. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2855. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2856. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2857. vdev->vdev_id);
  2858. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2859. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2860. /*
  2861. * Set HTT Extension Valid bit to 0 by default
  2862. */
  2863. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2864. dp_tx_vdev_update_search_flags(vdev);
  2865. return QDF_STATUS_SUCCESS;
  2866. }
  2867. #ifdef FEATURE_WDS
  2868. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  2869. {
  2870. struct dp_soc *soc = vdev->pdev->soc;
  2871. /*
  2872. * If AST index override support is available (HKv2 etc),
  2873. * DA search flag be enabled always
  2874. *
  2875. * If AST index override support is not available (HKv1),
  2876. * DA search flag should be used for all modes except QWRAP
  2877. */
  2878. if (soc->ast_override_support || !vdev->proxysta_vdev)
  2879. return true;
  2880. return false;
  2881. }
  2882. #else
  2883. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  2884. {
  2885. return false;
  2886. }
  2887. #endif
  2888. /**
  2889. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2890. * @vdev: virtual device instance
  2891. *
  2892. * Return: void
  2893. *
  2894. */
  2895. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2896. {
  2897. struct dp_soc *soc = vdev->pdev->soc;
  2898. /*
  2899. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2900. * for TDLS link
  2901. *
  2902. * Enable AddrY (SA based search) only for non-WDS STA and
  2903. * ProxySTA VAP (in HKv1) modes.
  2904. *
  2905. * In all other VAP modes, only DA based search should be
  2906. * enabled
  2907. */
  2908. if (vdev->opmode == wlan_op_mode_sta &&
  2909. vdev->tdls_link_connected)
  2910. vdev->hal_desc_addr_search_flags =
  2911. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2912. else if ((vdev->opmode == wlan_op_mode_sta) &&
  2913. !dp_tx_da_search_override(vdev))
  2914. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2915. else
  2916. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2917. /* Set search type only when peer map v2 messaging is enabled
  2918. * as we will have the search index (AST hash) only when v2 is
  2919. * enabled
  2920. */
  2921. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  2922. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  2923. else
  2924. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  2925. }
  2926. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2927. /* dp_tx_desc_flush() - release resources associated
  2928. * to tx_desc
  2929. * @vdev: virtual device instance
  2930. *
  2931. * This function will free all outstanding Tx buffers,
  2932. * including ME buffer for which either free during
  2933. * completion didn't happened or completion is not
  2934. * received.
  2935. */
  2936. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2937. {
  2938. uint8_t i;
  2939. uint32_t j;
  2940. uint32_t num_desc, page_id, offset;
  2941. uint16_t num_desc_per_page;
  2942. struct dp_soc *soc = vdev->pdev->soc;
  2943. struct dp_tx_desc_s *tx_desc = NULL;
  2944. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  2945. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  2946. tx_desc_pool = &soc->tx_desc[i];
  2947. if (!(tx_desc_pool->pool_size) ||
  2948. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  2949. !(tx_desc_pool->desc_pages.cacheable_pages))
  2950. continue;
  2951. num_desc = tx_desc_pool->pool_size;
  2952. num_desc_per_page =
  2953. tx_desc_pool->desc_pages.num_element_per_page;
  2954. for (j = 0; j < num_desc; j++) {
  2955. page_id = j / num_desc_per_page;
  2956. offset = j % num_desc_per_page;
  2957. if (qdf_unlikely(!(tx_desc_pool->
  2958. desc_pages.cacheable_pages)))
  2959. break;
  2960. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  2961. if (tx_desc && (tx_desc->vdev == vdev) &&
  2962. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  2963. dp_tx_comp_free_buf(soc, tx_desc);
  2964. dp_tx_desc_release(tx_desc, i);
  2965. }
  2966. }
  2967. }
  2968. }
  2969. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2970. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2971. {
  2972. uint8_t i, num_pool;
  2973. uint32_t j;
  2974. uint32_t num_desc, page_id, offset;
  2975. uint16_t num_desc_per_page;
  2976. struct dp_soc *soc = vdev->pdev->soc;
  2977. struct dp_tx_desc_s *tx_desc = NULL;
  2978. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  2979. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2980. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2981. for (i = 0; i < num_pool; i++) {
  2982. tx_desc_pool = &soc->tx_desc[i];
  2983. if (!tx_desc_pool->desc_pages.cacheable_pages)
  2984. continue;
  2985. num_desc_per_page =
  2986. tx_desc_pool->desc_pages.num_element_per_page;
  2987. for (j = 0; j < num_desc; j++) {
  2988. page_id = j / num_desc_per_page;
  2989. offset = j % num_desc_per_page;
  2990. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  2991. if (tx_desc && (tx_desc->vdev == vdev) &&
  2992. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  2993. dp_tx_comp_free_buf(soc, tx_desc);
  2994. dp_tx_desc_release(tx_desc, i);
  2995. }
  2996. }
  2997. }
  2998. }
  2999. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3000. /**
  3001. * dp_tx_vdev_detach() - detach vdev from dp tx
  3002. * @vdev: virtual device instance
  3003. *
  3004. * Return: QDF_STATUS_SUCCESS: success
  3005. * QDF_STATUS_E_RESOURCES: Error return
  3006. */
  3007. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3008. {
  3009. dp_tx_desc_flush(vdev);
  3010. return QDF_STATUS_SUCCESS;
  3011. }
  3012. /**
  3013. * dp_tx_pdev_attach() - attach pdev to dp tx
  3014. * @pdev: physical device instance
  3015. *
  3016. * Return: QDF_STATUS_SUCCESS: success
  3017. * QDF_STATUS_E_RESOURCES: Error return
  3018. */
  3019. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3020. {
  3021. struct dp_soc *soc = pdev->soc;
  3022. /* Initialize Flow control counters */
  3023. qdf_atomic_init(&pdev->num_tx_exception);
  3024. qdf_atomic_init(&pdev->num_tx_outstanding);
  3025. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3026. /* Initialize descriptors in TCL Ring */
  3027. hal_tx_init_data_ring(soc->hal_soc,
  3028. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3029. }
  3030. return QDF_STATUS_SUCCESS;
  3031. }
  3032. /**
  3033. * dp_tx_pdev_detach() - detach pdev from dp tx
  3034. * @pdev: physical device instance
  3035. *
  3036. * Return: QDF_STATUS_SUCCESS: success
  3037. * QDF_STATUS_E_RESOURCES: Error return
  3038. */
  3039. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3040. {
  3041. dp_tx_me_exit(pdev);
  3042. return QDF_STATUS_SUCCESS;
  3043. }
  3044. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3045. /* Pools will be allocated dynamically */
  3046. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3047. int num_desc)
  3048. {
  3049. uint8_t i;
  3050. for (i = 0; i < num_pool; i++) {
  3051. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3052. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3053. }
  3054. return 0;
  3055. }
  3056. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3057. {
  3058. uint8_t i;
  3059. for (i = 0; i < num_pool; i++)
  3060. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3061. }
  3062. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3063. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3064. int num_desc)
  3065. {
  3066. uint8_t i;
  3067. /* Allocate software Tx descriptor pools */
  3068. for (i = 0; i < num_pool; i++) {
  3069. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3070. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3071. "%s Tx Desc Pool alloc %d failed %pK",
  3072. __func__, i, soc);
  3073. return ENOMEM;
  3074. }
  3075. }
  3076. return 0;
  3077. }
  3078. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3079. {
  3080. uint8_t i;
  3081. for (i = 0; i < num_pool; i++) {
  3082. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3083. if (dp_tx_desc_pool_free(soc, i)) {
  3084. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3085. "%s Tx Desc Pool Free failed", __func__);
  3086. }
  3087. }
  3088. }
  3089. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3090. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3091. /**
  3092. * dp_tso_attach_wifi3() - TSO attach handler
  3093. * @txrx_soc: Opaque Dp handle
  3094. *
  3095. * Reserve TSO descriptor buffers
  3096. *
  3097. * Return: QDF_STATUS_E_FAILURE on failure or
  3098. * QDF_STATUS_SUCCESS on success
  3099. */
  3100. static
  3101. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3102. {
  3103. return dp_tso_soc_attach(txrx_soc);
  3104. }
  3105. /**
  3106. * dp_tso_detach_wifi3() - TSO Detach handler
  3107. * @txrx_soc: Opaque Dp handle
  3108. *
  3109. * Deallocate TSO descriptor buffers
  3110. *
  3111. * Return: QDF_STATUS_E_FAILURE on failure or
  3112. * QDF_STATUS_SUCCESS on success
  3113. */
  3114. static
  3115. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3116. {
  3117. return dp_tso_soc_detach(txrx_soc);
  3118. }
  3119. #else
  3120. static
  3121. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3122. {
  3123. return QDF_STATUS_SUCCESS;
  3124. }
  3125. static
  3126. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3127. {
  3128. return QDF_STATUS_SUCCESS;
  3129. }
  3130. #endif
  3131. QDF_STATUS dp_tso_soc_detach(void *txrx_soc)
  3132. {
  3133. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3134. uint8_t i;
  3135. uint8_t num_pool;
  3136. uint32_t num_desc;
  3137. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3138. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3139. for (i = 0; i < num_pool; i++)
  3140. dp_tx_tso_desc_pool_free(soc, i);
  3141. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3142. __func__, num_pool, num_desc);
  3143. for (i = 0; i < num_pool; i++)
  3144. dp_tx_tso_num_seg_pool_free(soc, i);
  3145. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3146. __func__, num_pool, num_desc);
  3147. return QDF_STATUS_SUCCESS;
  3148. }
  3149. /**
  3150. * dp_tso_attach() - TSO attach handler
  3151. * @txrx_soc: Opaque Dp handle
  3152. *
  3153. * Reserve TSO descriptor buffers
  3154. *
  3155. * Return: QDF_STATUS_E_FAILURE on failure or
  3156. * QDF_STATUS_SUCCESS on success
  3157. */
  3158. QDF_STATUS dp_tso_soc_attach(void *txrx_soc)
  3159. {
  3160. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3161. uint8_t i;
  3162. uint8_t num_pool;
  3163. uint32_t num_desc;
  3164. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3165. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3166. for (i = 0; i < num_pool; i++) {
  3167. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3168. dp_err("TSO Desc Pool alloc %d failed %pK",
  3169. i, soc);
  3170. return QDF_STATUS_E_FAILURE;
  3171. }
  3172. }
  3173. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3174. __func__, num_pool, num_desc);
  3175. for (i = 0; i < num_pool; i++) {
  3176. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3177. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3178. i, soc);
  3179. return QDF_STATUS_E_FAILURE;
  3180. }
  3181. }
  3182. return QDF_STATUS_SUCCESS;
  3183. }
  3184. /**
  3185. * dp_tx_soc_detach() - detach soc from dp tx
  3186. * @soc: core txrx main context
  3187. *
  3188. * This function will detach dp tx into main device context
  3189. * will free dp tx resource and initialize resources
  3190. *
  3191. * Return: QDF_STATUS_SUCCESS: success
  3192. * QDF_STATUS_E_RESOURCES: Error return
  3193. */
  3194. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3195. {
  3196. uint8_t num_pool;
  3197. uint16_t num_desc;
  3198. uint16_t num_ext_desc;
  3199. uint8_t i;
  3200. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3201. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3202. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3203. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3204. dp_tx_flow_control_deinit(soc);
  3205. dp_tx_delete_static_pools(soc, num_pool);
  3206. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3207. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3208. __func__, num_pool, num_desc);
  3209. for (i = 0; i < num_pool; i++) {
  3210. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3211. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3212. "%s Tx Ext Desc Pool Free failed",
  3213. __func__);
  3214. return QDF_STATUS_E_RESOURCES;
  3215. }
  3216. }
  3217. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3218. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3219. __func__, num_pool, num_ext_desc);
  3220. status = dp_tso_detach_wifi3(soc);
  3221. if (status != QDF_STATUS_SUCCESS)
  3222. return status;
  3223. return QDF_STATUS_SUCCESS;
  3224. }
  3225. /**
  3226. * dp_tx_soc_attach() - attach soc to dp tx
  3227. * @soc: core txrx main context
  3228. *
  3229. * This function will attach dp tx into main device context
  3230. * will allocate dp tx resource and initialize resources
  3231. *
  3232. * Return: QDF_STATUS_SUCCESS: success
  3233. * QDF_STATUS_E_RESOURCES: Error return
  3234. */
  3235. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3236. {
  3237. uint8_t i;
  3238. uint8_t num_pool;
  3239. uint32_t num_desc;
  3240. uint32_t num_ext_desc;
  3241. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3242. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3243. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3244. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3245. if (num_pool > MAX_TXDESC_POOLS)
  3246. goto fail;
  3247. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3248. goto fail;
  3249. dp_tx_flow_control_init(soc);
  3250. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3251. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3252. __func__, num_pool, num_desc);
  3253. /* Allocate extension tx descriptor pools */
  3254. for (i = 0; i < num_pool; i++) {
  3255. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3256. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3257. "MSDU Ext Desc Pool alloc %d failed %pK",
  3258. i, soc);
  3259. goto fail;
  3260. }
  3261. }
  3262. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3263. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3264. __func__, num_pool, num_ext_desc);
  3265. status = dp_tso_attach_wifi3((void *)soc);
  3266. if (status != QDF_STATUS_SUCCESS)
  3267. goto fail;
  3268. /* Initialize descriptors in TCL Rings */
  3269. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3270. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3271. hal_tx_init_data_ring(soc->hal_soc,
  3272. soc->tcl_data_ring[i].hal_srng);
  3273. }
  3274. }
  3275. /*
  3276. * todo - Add a runtime config option to enable this.
  3277. */
  3278. /*
  3279. * Due to multiple issues on NPR EMU, enable it selectively
  3280. * only for NPR EMU, should be removed, once NPR platforms
  3281. * are stable.
  3282. */
  3283. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3284. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3285. "%s HAL Tx init Success", __func__);
  3286. return QDF_STATUS_SUCCESS;
  3287. fail:
  3288. /* Detach will take care of freeing only allocated resources */
  3289. dp_tx_soc_detach(soc);
  3290. return QDF_STATUS_E_RESOURCES;
  3291. }
  3292. /*
  3293. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  3294. * pdev: pointer to DP PDEV structure
  3295. * seg_info_head: Pointer to the head of list
  3296. *
  3297. * return: void
  3298. */
  3299. static void dp_tx_me_mem_free(struct dp_pdev *pdev,
  3300. struct dp_tx_seg_info_s *seg_info_head)
  3301. {
  3302. struct dp_tx_me_buf_t *mc_uc_buf;
  3303. struct dp_tx_seg_info_s *seg_info_new = NULL;
  3304. qdf_nbuf_t nbuf = NULL;
  3305. uint64_t phy_addr;
  3306. while (seg_info_head) {
  3307. nbuf = seg_info_head->nbuf;
  3308. mc_uc_buf = (struct dp_tx_me_buf_t *)
  3309. seg_info_head->frags[0].vaddr;
  3310. phy_addr = seg_info_head->frags[0].paddr_hi;
  3311. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  3312. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  3313. phy_addr,
  3314. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  3315. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3316. qdf_nbuf_free(nbuf);
  3317. seg_info_new = seg_info_head;
  3318. seg_info_head = seg_info_head->next;
  3319. qdf_mem_free(seg_info_new);
  3320. }
  3321. }
  3322. /**
  3323. * dp_tx_me_send_convert_ucast(): function to convert multicast to unicast
  3324. * @vdev: DP VDEV handle
  3325. * @nbuf: Multicast nbuf
  3326. * @newmac: Table of the clients to which packets have to be sent
  3327. * @new_mac_cnt: No of clients
  3328. *
  3329. * return: no of converted packets
  3330. */
  3331. uint16_t
  3332. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  3333. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  3334. {
  3335. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3336. struct dp_pdev *pdev = vdev->pdev;
  3337. struct ether_header *eh;
  3338. uint8_t *data;
  3339. uint16_t len;
  3340. /* reference to frame dst addr */
  3341. uint8_t *dstmac;
  3342. /* copy of original frame src addr */
  3343. uint8_t srcmac[DP_MAC_ADDR_LEN];
  3344. /* local index into newmac */
  3345. uint8_t new_mac_idx = 0;
  3346. struct dp_tx_me_buf_t *mc_uc_buf;
  3347. qdf_nbuf_t nbuf_clone;
  3348. struct dp_tx_msdu_info_s msdu_info;
  3349. struct dp_tx_seg_info_s *seg_info_head = NULL;
  3350. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  3351. struct dp_tx_seg_info_s *seg_info_new;
  3352. struct dp_tx_frag_info_s data_frag;
  3353. qdf_dma_addr_t paddr_data;
  3354. qdf_dma_addr_t paddr_mcbuf = 0;
  3355. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  3356. QDF_STATUS status;
  3357. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  3358. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3359. eh = (struct ether_header *) nbuf;
  3360. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  3361. len = qdf_nbuf_len(nbuf);
  3362. data = qdf_nbuf_data(nbuf);
  3363. status = qdf_nbuf_map(vdev->osdev, nbuf,
  3364. QDF_DMA_TO_DEVICE);
  3365. if (status) {
  3366. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3367. "Mapping failure Error:%d", status);
  3368. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3369. qdf_nbuf_free(nbuf);
  3370. return 1;
  3371. }
  3372. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  3373. /*preparing data fragment*/
  3374. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  3375. data_frag.paddr_lo = (uint32_t)paddr_data;
  3376. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  3377. data_frag.len = len - DP_MAC_ADDR_LEN;
  3378. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  3379. dstmac = newmac[new_mac_idx];
  3380. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3381. "added mac addr (%pM)", dstmac);
  3382. /* Check for NULL Mac Address */
  3383. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  3384. continue;
  3385. /* frame to self mac. skip */
  3386. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  3387. continue;
  3388. /*
  3389. * TODO: optimize to avoid malloc in per-packet path
  3390. * For eg. seg_pool can be made part of vdev structure
  3391. */
  3392. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  3393. if (!seg_info_new) {
  3394. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3395. "alloc failed");
  3396. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  3397. goto fail_seg_alloc;
  3398. }
  3399. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  3400. if (mc_uc_buf == NULL)
  3401. goto fail_buf_alloc;
  3402. /*
  3403. * TODO: Check if we need to clone the nbuf
  3404. * Or can we just use the reference for all cases
  3405. */
  3406. if (new_mac_idx < (new_mac_cnt - 1)) {
  3407. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  3408. if (nbuf_clone == NULL) {
  3409. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  3410. goto fail_clone;
  3411. }
  3412. } else {
  3413. /*
  3414. * Update the ref
  3415. * to account for frame sent without cloning
  3416. */
  3417. qdf_nbuf_ref(nbuf);
  3418. nbuf_clone = nbuf;
  3419. }
  3420. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  3421. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  3422. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  3423. &paddr_mcbuf);
  3424. if (status) {
  3425. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3426. "Mapping failure Error:%d", status);
  3427. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3428. goto fail_map;
  3429. }
  3430. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  3431. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  3432. seg_info_new->frags[0].paddr_hi =
  3433. ((uint64_t) paddr_mcbuf >> 32);
  3434. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  3435. seg_info_new->frags[1] = data_frag;
  3436. seg_info_new->nbuf = nbuf_clone;
  3437. seg_info_new->frag_cnt = 2;
  3438. seg_info_new->total_len = len;
  3439. seg_info_new->next = NULL;
  3440. if (seg_info_head == NULL)
  3441. seg_info_head = seg_info_new;
  3442. else
  3443. seg_info_tail->next = seg_info_new;
  3444. seg_info_tail = seg_info_new;
  3445. }
  3446. if (!seg_info_head) {
  3447. goto free_return;
  3448. }
  3449. msdu_info.u.sg_info.curr_seg = seg_info_head;
  3450. msdu_info.num_seg = new_mac_cnt;
  3451. msdu_info.frm_type = dp_tx_frm_me;
  3452. if (qdf_unlikely(vdev->mcast_enhancement_en > 0) &&
  3453. qdf_unlikely(pdev->hmmc_tid_override_en))
  3454. msdu_info.tid = pdev->hmmc_tid;
  3455. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  3456. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3457. while (seg_info_head->next) {
  3458. seg_info_new = seg_info_head;
  3459. seg_info_head = seg_info_head->next;
  3460. qdf_mem_free(seg_info_new);
  3461. }
  3462. qdf_mem_free(seg_info_head);
  3463. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3464. qdf_nbuf_free(nbuf);
  3465. return new_mac_cnt;
  3466. fail_map:
  3467. qdf_nbuf_free(nbuf_clone);
  3468. fail_clone:
  3469. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3470. fail_buf_alloc:
  3471. qdf_mem_free(seg_info_new);
  3472. fail_seg_alloc:
  3473. dp_tx_me_mem_free(pdev, seg_info_head);
  3474. free_return:
  3475. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3476. qdf_nbuf_free(nbuf);
  3477. return 1;
  3478. }