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wsa884x
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wsa884x-reg-masks.h

wsa884x-reg-masks.h 16 KB
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  1. /* SPDX-License-Identifier: GPL-2.0-only */
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
    4. 

  4.  */
    5. 

  5. 

  6. #ifndef WSA884X_REG_MASKS_H
    7. 

  7. #define WSA884X_REG_MASKS_H
    8. 

  8. #include <linux/regmap.h>
    9. 

  9. #include <linux/device.h>
    10. 

  10. #include "wsa884x-registers.h"
    11. 

  11. 

  12. /*
    13. 

  13.  * Use in conjunction with wsa884x-reg-shifts.c for field values.
    14. 

  14.  * field_value = (register_value & field_mask) >> field_shift
    15. 

  15.  */
    16. 

  16. 

  17. #define FIELD_MASK(register_name, field_name) \
    18. 

  18. 	WSA884X_##register_name##_##field_name##_MASK
    19. 

  19. 

  20. /* WSA884X_BOP2_PROG Fields: */
    21. 

  21. #define WSA884X_BOP2_PROG_BOP2_VTH_MASK                                  0xf0
    22. 

  22. #define WSA884X_BOP2_PROG_BOP2_HYST_MASK                                 0x0f
    23. 

  23. /* WSA884X_VSENSE1 Fields: */
    24. 

  24. #define WSA884X_VSENSE1_GAIN_VSENSE_FE_MASK                              0xe0
    25. 

  25. #define WSA884X_VSENSE1_VSENSE_AMP_IQ_CTL_1_MASK                         0x10
    26. 

  26. #define WSA884X_VSENSE1_IDLE_MODE_CTL_MASK                               0x0c
    27. 

  27. #define WSA884X_VSENSE1_VOCM_AMP_CTL_MASK                                0x03
    28. 

  28. /* WSA884X_ISENSE2 Fields: */
    29. 

  29. #define WSA884X_ISENSE2_ISENSE_GAIN_CTL_MASK                             0xe0
    30. 

  30. #define WSA884X_ISENSE2_SUMAMP_IQ_CTL_MASK                               0x10
    31. 

  31. #define WSA884X_ISENSE2_SPARE_BITS_3_0_MASK                              0x0f
    32. 

  32. /* WSA884X_ADC_2 Fields: */
    33. 

  33. #define WSA884X_ADC_2_ATEST_SEL_CAL_REF_MASK                             0x80
    34. 

  34. #define WSA884X_ADC_2_ISNS_LOAD_STORED_MASK                              0x40
    35. 

  35. #define WSA884X_ADC_2_EN_DET_MASK                                        0x20
    36. 

  36. #define WSA884X_ADC_2_EN_ATEST_REF_MASK                                  0x10
    37. 

  37. #define WSA884X_ADC_2_EN_ATEST_INT_MASK                                  0x0e
    38. 

  38. #define WSA884X_ADC_2_D_ADC_REG_EN_MASK                                  0x01
    39. 

  39. /* WSA884X_ADC_7 Fields: */
    40. 

  40. #define WSA884X_ADC_7_CLAMPON_MASK                                       0x80
    41. 

  41. #define WSA884X_ADC_7_CAL_LOOP_TRIM_MASK                                 0x70
    42. 

  42. #define WSA884X_ADC_7_REG_TRIM_EN_MASK                                   0x08
    43. 

  43. #define WSA884X_ADC_7_EN_AZ_REG_MASK                                     0x04
    44. 

  44. #define WSA884X_ADC_7_EN_SAR_REG_MASK                                    0x02
    45. 

  45. #define WSA884X_ADC_7_EN_SW_CURRENT_REG_MASK                             0x01
    46. 

  46. /* WSA884X_TOP_CTRL1 Fields: */
    47. 

  47. #define WSA884X_TOP_CTRL1_IDLE_PWRSAV_OVERRIDE_MASK                      0x80
    48. 

  48. #define WSA884X_TOP_CTRL1_DAC_LDO_PROG_MASK                              0x60
    49. 

  49. #define WSA884X_TOP_CTRL1_DATA_INV_MASK                                  0x10
    50. 

  50. #define WSA884X_TOP_CTRL1_DATA_RESET_MASK                                0x08
    51. 

  51. #define WSA884X_TOP_CTRL1_CLK_DIV2_MASK                                  0x04
    52. 

  52. #define WSA884X_TOP_CTRL1_CLK_INV_MASK                                   0x02
    53. 

  53. #define WSA884X_TOP_CTRL1_OCP_LOWVBAT_ITH_SEL_EN_MASK                    0x01
    54. 

  54. /* WSA884X_BOP_DEGLITCH_CTL Fields: */
    55. 

  55. #define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_SETTING_MASK               0x1e
    56. 

  56. #define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_EN_MASK                    0x01
    57. 

  57. /* WSA884X_CDC_SPK_DSM_A2_0 Fields: */
    58. 

  58. #define WSA884X_CDC_SPK_DSM_A2_0_COEF_A2_MASK                            0xff
    59. 

  59. /* WSA884X_CDC_SPK_DSM_A2_1 Fields: */
    60. 

  60. #define WSA884X_CDC_SPK_DSM_A2_1_COEF_A2_MASK                            0x0f
    61. 

  61. /* WSA884X_CDC_SPK_DSM_A3_0 Fields: */
    62. 

  62. #define WSA884X_CDC_SPK_DSM_A3_0_COEF_A3_MASK                            0xff
    63. 

  63. /* WSA884X_CDC_SPK_DSM_A3_1 Fields: */
    64. 

  64. #define WSA884X_CDC_SPK_DSM_A3_1_COEF_A3_MASK                            0x07
    65. 

  65. /* WSA884X_CDC_SPK_DSM_A4_0 Fields: */
    66. 

  66. #define WSA884X_CDC_SPK_DSM_A4_0_COEF_A4_MASK                            0xff
    67. 

  67. /* WSA884X_CDC_SPK_DSM_A5_0 Fields: */
    68. 

  68. #define WSA884X_CDC_SPK_DSM_A5_0_COEF_A5_MASK                            0xff
    69. 

  69. /* WSA884X_CDC_SPK_DSM_A6_0 Fields: */
    70. 

  70. #define WSA884X_CDC_SPK_DSM_A6_0_COEF_A6_MASK                            0xff
    71. 

  71. /* WSA884X_CDC_SPK_DSM_A7_0 Fields: */
    72. 

  72. #define WSA884X_CDC_SPK_DSM_A7_0_COEF_A7_MASK                            0xff
    73. 

  73. /* WSA884X_CDC_SPK_DSM_C_0 Fields: */
    74. 

  74. #define WSA884X_CDC_SPK_DSM_C_0_COEF_C3_MASK                             0xf0
    75. 

  75. #define WSA884X_CDC_SPK_DSM_C_0_COEF_C2_MASK                             0x0f
    76. 

  76. /* WSA884X_CDC_SPK_DSM_C_2 Fields: */
    77. 

  77. #define WSA884X_CDC_SPK_DSM_C_2_COEF_C7_MASK                             0xf0
    78. 

  78. #define WSA884X_CDC_SPK_DSM_C_2_COEF_C6_MASK                             0x0f
    79. 

  79. /* WSA884X_CDC_SPK_DSM_C_3 Fields: */
    80. 

  80. #define WSA884X_CDC_SPK_DSM_C_3_COEF_C7_MASK                             0x3f
    81. 

  81. /* WSA884X_CDC_SPK_DSM_R1 Fields: */
    82. 

  82. #define WSA884X_CDC_SPK_DSM_R1_SAT_LIMIT_R1_MASK                         0xff
    83. 

  83. /* WSA884X_CDC_SPK_DSM_R2 Fields: */
    84. 

  84. #define WSA884X_CDC_SPK_DSM_R2_SAT_LIMIT_R2_MASK                         0xff
    85. 

  85. /* WSA884X_CDC_SPK_DSM_R3 Fields: */
    86. 

  86. #define WSA884X_CDC_SPK_DSM_R3_SAT_LIMIT_R3_MASK                         0xff
    87. 

  87. /* WSA884X_CDC_SPK_DSM_R4 Fields: */
    88. 

  88. #define WSA884X_CDC_SPK_DSM_R4_SAT_LIMIT_R4_MASK                         0xff
    89. 

  89. /* WSA884X_CDC_SPK_DSM_R5 Fields: */
    90. 

  90. #define WSA884X_CDC_SPK_DSM_R5_SAT_LIMIT_R5_MASK                         0xff
    91. 

  91. /* WSA884X_CDC_SPK_DSM_R6 Fields: */
    92. 

  92. #define WSA884X_CDC_SPK_DSM_R6_SAT_LIMIT_R6_MASK                         0xff
    93. 

  93. /* WSA884X_CDC_SPK_DSM_R7 Fields: */
    94. 

  94. #define WSA884X_CDC_SPK_DSM_R7_SAT_LIMIT_R7_MASK                         0xff
    95. 

  95. /* WSA884X_DRE_CTL_0 Fields: */
    96. 

  96. #define WSA884X_DRE_CTL_0_PROG_DELAY_MASK                                0xf0
    97. 

  97. #define WSA884X_DRE_CTL_0_OFFSET_MASK                                    0x07
    98. 

  98. /* WSA884X_GAIN_RAMPING_MIN Fields: */
    99. 

  99. #define WSA884X_GAIN_RAMPING_MIN_MIN_GAIN_MASK                           0x1f
    100. 

  100. /* WSA884X_CLSH_SOFT_MAX Fields: */
    101. 

  101. #define WSA884X_CLSH_SOFT_MAX_SOFT_MAX_MASK                              0xff
    102. 

  102. /* WSA884X_CLSH_VTH1 Fields: */
    103. 

  103. #define WSA884X_CLSH_VTH1_CLSH_VTH1_MASK                                 0xff
    104. 

  104. /* WSA884X_CLSH_VTH10 Fields: */
    105. 

  105. #define WSA884X_CLSH_VTH10_CLSH_VTH10_MASK                               0xff
    106. 

  106. /* WSA884X_CLSH_VTH11 Fields: */
    107. 

  107. #define WSA884X_CLSH_VTH11_CLSH_VTH11_MASK                               0xff
    108. 

  108. /* WSA884X_CLSH_VTH12 Fields: */
    109. 

  109. #define WSA884X_CLSH_VTH12_CLSH_VTH12_MASK                               0xff
    110. 

  110. /* WSA884X_CLSH_VTH13 Fields: */
    111. 

  111. #define WSA884X_CLSH_VTH13_CLSH_VTH13_MASK                               0xff
    112. 

  112. /* WSA884X_CLSH_VTH14 Fields: */
    113. 

  113. #define WSA884X_CLSH_VTH14_CLSH_VTH14_MASK                               0xff
    114. 

  114. /* WSA884X_CLSH_VTH15 Fields: */
    115. 

  115. #define WSA884X_CLSH_VTH15_CLSH_VTH15_MASK                               0xff
    116. 

  116. /* WSA884X_ANA_WO_CTL_0 Fields: */
    117. 

  117. #define WSA884X_ANA_WO_CTL_0_VPHX_SYS_EN_MASK                            0xc0
    118. 

  118. #define WSA884X_ANA_WO_CTL_0_PA_AUX_GAIN_MASK                            0x3c
    119. 

  119. #define WSA884X_ANA_WO_CTL_0_PA_MIN_GAIN_BYP_MASK                        0x02
    120. 

  120. #define WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_MASK                        0x01
    121. 

  121. /* WSA884X_ANA_WO_CTL_1 Fields: */
    122. 

  122. #define WSA884X_ANA_WO_CTL_1_BOOST_SHARE_EN_MASK                         0x08
    123. 

  123. #define WSA884X_ANA_WO_CTL_1_EXT_VDDSPK_EN_MASK                          0x07
    124. 

  124. /* WSA884X_DRE_CTL_1 Fields: */
    125. 

  125. #define WSA884X_DRE_CTL_1_CSR_GAIN_MASK                                  0x3e
    126. 

  126. #define WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK                               0x01
    127. 

  127. /* WSA884X_VBAT_THRM_FLT_CTL Fields: */
    128. 

  128. #define WSA884X_VBAT_THRM_FLT_CTL_THRM_COEF_SEL_MASK                     0xe0
    129. 

  129. #define WSA884X_VBAT_THRM_FLT_CTL_THRM_FLT_EN_MASK                       0x10
    130. 

  130. #define WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_MASK                     0x0e
    131. 

  131. #define WSA884X_VBAT_THRM_FLT_CTL_VBAT_FLT_EN_MASK                       0x01
    132. 

  132. /* WSA884X_PDM_WD_CTL Fields: */
    133. 

  133. #define WSA884X_PDM_WD_CTL_HOLD_OFF_MASK                                 0x04
    134. 

  134. #define WSA884X_PDM_WD_CTL_TIME_OUT_SEL_MASK                             0x02
    135. 

  135. #define WSA884X_PDM_WD_CTL_PDM_WD_EN_MASK                                0x01
    136. 

  136. /* WSA884X_PA_FSM_BYP_CTL Fields: */
    137. 

  137. #define WSA884X_PA_FSM_BYP_CTL_PA_FSM_BYP_MASK                           0x01
    138. 

  138. /* WSA884X_TADC_VALUE_CTL Fields: */
    139. 

  139. #define WSA884X_TADC_VALUE_CTL_VBAT_VALUE_RD_EN_MASK                     0x02
    140. 

  140. #define WSA884X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_MASK                     0x01
    141. 

  141. /* WSA884X_CDC_PATH_MODE Fields: */
    142. 

  142. #define WSA884X_CDC_PATH_MODE_RXD_MODE_MASK                              0x02
    143. 

  143. #define WSA884X_CDC_PATH_MODE_TXD_MODE_MASK                              0x01
    144. 

  144. /* WSA884X_PA_FSM_BYP0 Fields: */
    145. 

  145. #define WSA884X_PA_FSM_BYP0_TSADC_EN_MASK                                0x80
    146. 

  146. #define WSA884X_PA_FSM_BYP0_SPKR_PROT_EN_MASK                            0x40
    147. 

  147. #define WSA884X_PA_FSM_BYP0_D_UNMUTE_MASK                                0x20
    148. 

  148. #define WSA884X_PA_FSM_BYP0_PA_EN_MASK                                   0x10
    149. 

  149. #define WSA884X_PA_FSM_BYP0_BOOST_EN_MASK                                0x08
    150. 

  150. #define WSA884X_PA_FSM_BYP0_BG_EN_MASK                                   0x04
    151. 

  151. #define WSA884X_PA_FSM_BYP0_CLK_WD_EN_MASK                               0x02
    152. 

  152. #define WSA884X_PA_FSM_BYP0_DC_CAL_EN_MASK                               0x01
    153. 

  153. /* WSA884X_PA_FSM_BYP1 Fields: */
    154. 

  154. #define WSA884X_PA_FSM_BYP1_NG_MODE_MASK                                 0xc0
    155. 

  155. #define WSA884X_PA_FSM_BYP1_PWRSAV_CTL_MASK                              0x20
    156. 

  156. #define WSA884X_PA_FSM_BYP1_RAMP_DOWN_MASK                               0x10
    157. 

  157. #define WSA884X_PA_FSM_BYP1_RAMP_UP_MASK                                 0x08
    158. 

  158. #define WSA884X_PA_FSM_BYP1_BLEEDER_EN_MASK                              0x04
    159. 

  159. #define WSA884X_PA_FSM_BYP1_PA_MAIN_EN_MASK                              0x02
    160. 

  160. #define WSA884X_PA_FSM_BYP1_PA_AUX_EN_MASK                               0x01
    161. 

  161. /* WSA884X_PA_FSM_EN Fields: */
    162. 

  162. #define WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK                              0x01
    163. 

  163. /* WSA884X_OTP_REG_0 Fields: */
    164. 

  164. #define WSA884X_OTP_REG_0_WSA884X_ID_MASK                                0x0f
    165. 

  165. /* WSA884X_CHIP_ID0 Fields: */
    166. 

  166. #define WSA884X_CHIP_ID0_BYTE_0_MASK                                     0xff
    167. 

  167. /* WSA884X_CHIP_ID1 Fields: */
    168. 

  168. #define WSA884X_CHIP_ID1_BYTE_1_MASK                                     0xff
    169. 

  169. /* WSA884X_CHIP_ID2 Fields: */
    170. 

  170. #define WSA884X_CHIP_ID2_BYTE_2_MASK                                     0xff
    171. 

  171. /* WSA884X_CHIP_ID3 Fields: */
    172. 

  172. #define WSA884X_CHIP_ID3_BYTE_3_MASK                                     0xff
    173. 

  173. /* WSA884X_OCP_CTL Fields: */
    174. 

  174. #define WSA884X_OCP_CTL_OCP_EN_MASK                                      0x80
    175. 

  175. #define WSA884X_OCP_CTL_OCP_CURR_LIMIT_MASK                              0x70
    176. 

  176. #define WSA884X_OCP_CTL_GLITCH_FILTER_MASK                               0x0c
    177. 

  177. #define WSA884X_OCP_CTL_OCP_P_HS_DLY_CTL_MASK                            0x03
    178. 

  178. /* WSA884X_ILIM_CTRL1 Fields: */
    179. 

  179. #define WSA884X_ILIM_CTRL1_EN_AUTO_MAXD_SEL_MASK                         0x80
    180. 

  180. #define WSA884X_ILIM_CTRL1_EN_ILIM_SW_CLH_MASK                           0x40
    181. 

  181. #define WSA884X_ILIM_CTRL1_ILIM_OFFSET_CLH_MASK                          0x38
    182. 

  182. #define WSA884X_ILIM_CTRL1_ILIM_OFFSET_PB_MASK                           0x07
    183. 

  183. /* WSA884X_CLSH_CTL_0 Fields: */
    184. 

  184. #define WSA884X_CLSH_CTL_0_CSR_GAIN_EN_MASK                              0x80
    185. 

  185. #define WSA884X_CLSH_CTL_0_DLY_CODE_MASK                                 0x70
    186. 

  186. #define WSA884X_CLSH_CTL_0_DLY_RST_MASK                                  0x08
    187. 

  187. #define WSA884X_CLSH_CTL_0_DLY_EN_MASK                                   0x04
    188. 

  188. #define WSA884X_CLSH_CTL_0_INPUT_EN_MASK                                 0x02
    189. 

  189. #define WSA884X_CLSH_CTL_0_CLSH_EN_MASK                                  0x01
    190. 

  190. /* WSA884X_CLSH_CTL_1 Fields: */
    191. 

  191. #define WSA884X_CLSH_CTL_1_SLR_MAX_MASK                                  0xf0
    192. 

  192. #define WSA884X_CLSH_CTL_1_VERF_OVRD_EN_MASK                             0x08
    193. 

  193. #define WSA884X_CLSH_CTL_1_DECAY_RATE_MASK                               0x07
    194. 

  194. /* WSA884X_CLSH_V_HD_PA Fields: */
    195. 

  195. #define WSA884X_CLSH_V_HD_PA_V_HD_PA_MASK                                0x1f
    196. 

  196. /* WSA884X_UVLO_PROG Fields: */
    197. 

  197. #define WSA884X_UVLO_PROG_UVLO1_HYST_MASK                                0xf0
    198. 

  198. #define WSA884X_UVLO_PROG_UVLO1_VTH_MASK                                 0x0f
    199. 

  199. /* WSA884X_DAC_VCM_CTRL_REG2 Fields: */
    200. 

  200. #define WSA884X_DAC_VCM_CTRL_REG2_DAC_VCM_SHIFT_MASK                     0xff
    201. 

  201. /* WSA884X_DAC_VCM_CTRL_REG3 Fields: */
    202. 

  202. #define WSA884X_DAC_VCM_CTRL_REG3_DAC_VCM_SHIFT_MASK                     0xff
    203. 

  203. /* WSA884X_DAC_VCM_CTRL_REG4 Fields: */
    204. 

  204. #define WSA884X_DAC_VCM_CTRL_REG4_DAC_VCM_SHIFT_MASK                     0xff
    205. 

  205. /* WSA884X_DAC_VCM_CTRL_REG5 Fields: */
    206. 

  206. #define WSA884X_DAC_VCM_CTRL_REG5_DAC_VCM_SHIFT_MASK                     0xff
    207. 

  207. /* WSA884X_DAC_VCM_CTRL_REG6 Fields: */
    208. 

  208. #define WSA884X_DAC_VCM_CTRL_REG6_DAC_VCM_SHIFT_MASK                     0xff
    209. 

  209. /* WSA884X_DAC_VCM_CTRL_REG7 Fields: */
    210. 

  210. #define WSA884X_DAC_VCM_CTRL_REG7_SPARE_BITS_7_2_MASK                    0xfc
    211. 

  211. #define WSA884X_DAC_VCM_CTRL_REG7_DAC_VCM_SHIFT_FINAL_OVERRIDE_MASK      0x02
    212. 

  212. #define WSA884X_DAC_VCM_CTRL_REG7_DAC_VCM_SHIFT_ZONE_OVERRIDE_MASK       0x01
    213. 

  213. /* WSA884X_STB_CTRL1 Fields: */
    214. 

  214. #define WSA884X_STB_CTRL1_SLOPE_COMP_CURRENT_MASK                        0xf8
    215. 

  215. #define WSA884X_STB_CTRL1_VOUT_FS_MASK                                   0x07
    216. 

  216. /* WSA884X_OTP_REG_38 Fields: */
    217. 

  217. #define WSA884X_OTP_REG_38_RESERVER_MASK                                 0xf0
    218. 

  218. #define WSA884X_OTP_REG_38_BST_CFG_SEL_MASK                              0x08
    219. 

  219. #define WSA884X_OTP_REG_38_BOOST_ILIM_TUNE_MASK                          0x07
    220. 

  220. /* WSA884X_OTP_REG_40 Fields: */
    221. 

  221. #define WSA884X_OTP_REG_40_SPARE_TYPE2_MASK                              0xc0
    222. 

  222. #define WSA884X_OTP_REG_40_ISENSE_RESCAL_MASK                            0x3c
    223. 

  223. #define WSA884X_OTP_REG_40_ATE_BOOST_RDSON_TEST_MASK                     0x02
    224. 

  224. #define WSA884X_OTP_REG_40_ATE_CLASSD_RDSON_TEST_MASK                    0x01
    225. 

  225. /* WSA884X_CURRENT_LIMIT Fields: */
    226. 

  226. #define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_OVRD_EN_MASK                 0x80
    227. 

  227. #define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_MASK                         0x7c
    228. 

  228. #define WSA884X_CURRENT_LIMIT_CLK_PHASE_MASK                             0x03
    229. 

  229. /* WSA884X_PWM_CLK_CTL Fields: */
    230. 

  230. #define WSA884X_PWM_CLK_CTL_VCMO_INT1_IDLE_MODE_OVRT_MASK                0x80
    231. 

  231. #define WSA884X_PWM_CLK_CTL_REG_MCLK_DIV_RATIO_MASK                      0x40
    232. 

  232. #define WSA884X_PWM_CLK_CTL_PWM_DEGLITCH_CLK_DELAY_CTRL_MASK             0x30
    233. 

  233. #define WSA884X_PWM_CLK_CTL_PWM_CLK_FREQ_SEL_MASK                        0x08
    234. 

  234. #define WSA884X_PWM_CLK_CTL_PWM_CLK_DIV_RATIO_MASK                       0x06
    235. 

  235. #define WSA884X_PWM_CLK_CTL_PWM_CLK_DIV_BYPASS_MASK                      0x01
    236. 

  236. /* WSA884X_CKWD_CTL_1 Fields: */
    237. 

  237. #define WSA884X_CKWD_CTL_1_SPARE_BITS_7_6_MASK                           0xc0
    238. 

  238. #define WSA884X_CKWD_CTL_1_VPP_SW_CTL_MASK                               0x20
    239. 

  239. #define WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_MASK                      0x1f
    240. 

  240. /* WSA884X_VBAT_CAL_CTL Fields: */
    241. 

  241. #define WSA884X_VBAT_CAL_CTL_RESERVE_MASK                                0x0e
    242. 

  242. #define WSA884X_VBAT_CAL_CTL_VBAT_CAL_EN_MASK                            0x01
    243. 

  243. /* WSA884X_REF_CTRL Fields: */
    244. 

  244. #define WSA884X_REF_CTRL_DC_STARTUP_EN_MASK                              0x80
    245. 

  245. #define WSA884X_REF_CTRL_DC_STARTUP_HOLD_MASK                            0x40
    246. 

  246. #define WSA884X_REF_CTRL_TRAN_STARTUP_EN_CORE_MASK                       0x20
    247. 

  247. #define WSA884X_REF_CTRL_TRAN_STARTUP_EN_PTAT_MASK                       0x10
    248. 

  248. #define WSA884X_REF_CTRL_BG_EN_MASK                                      0x08
    249. 

  249. #define WSA884X_REF_CTRL_BG_READY_FORCE_MASK                             0x04
    250. 

  250. #define WSA884X_REF_CTRL_BG_RDY_SEL_MASK                                 0x03
    251. 

  251. /* WSA884X_ZX_CTRL1 Fields: */
    252. 

  252. #define WSA884X_ZX_CTRL1_ZX_DET_EN_MASK                                  0x80
    253. 

  253. #define WSA884X_ZX_CTRL1_ZX_DET_SW_EN_MASK                               0x40
    254. 

  254. #define WSA884X_ZX_CTRL1_ZX_DET_STAGE_DEFAULT_MASK                       0x20
    255. 

  255. #define WSA884X_ZX_CTRL1_ZX_DET_SW_SEL_MASK                              0x18
    256. 

  256. #define WSA884X_ZX_CTRL1_ZX_BYP_MASK_IGNORE_MASK                         0x04
    257. 

  257. #define WSA884X_ZX_CTRL1_ZX_BYP_MASK_DEL_MASK                            0x02
    258. 

  258. #define WSA884X_ZX_CTRL1_BOOTCAP_REFRESH_DIS_MASK                        0x01
    259. 

  259. #endif /* WSA884X_REG_MASKS_H */
    260.