lpass-cdc.c 42 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #include <linux/of_platform.h>
  6. #include <linux/module.h>
  7. #include <linux/io.h>
  8. #include <linux/init.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/printk.h>
  11. #include <linux/delay.h>
  12. #include <linux/kernel.h>
  13. #include <linux/clk.h>
  14. #include <soc/snd_event.h>
  15. #include <linux/pm_runtime.h>
  16. #include <soc/swr-common.h>
  17. #include <dsp/digital-cdc-rsc-mgr.h>
  18. #include "lpass-cdc.h"
  19. #include "internal.h"
  20. #include "lpass-cdc-clk-rsc.h"
  21. #include <linux/qti-regmap-debugfs.h>
  22. #define DRV_NAME "lpass-cdc"
  23. #define LPASS_CDC_VERSION_ENTRY_SIZE 32
  24. #define LPASS_CDC_STRING_LEN 80
  25. static const struct snd_soc_component_driver lpass_cdc;
  26. /* pm runtime auto suspend timer in msecs */
  27. #define LPASS_CDC_AUTO_SUSPEND_DELAY 100 /* delay in msec */
  28. /* MCLK_MUX table for all macros */
  29. static u16 lpass_cdc_mclk_mux_tbl[MAX_MACRO][MCLK_MUX_MAX] = {
  30. {TX_MACRO, VA_MACRO},
  31. {TX_MACRO, RX_MACRO},
  32. {TX_MACRO, WSA_MACRO},
  33. {TX_MACRO, VA_MACRO},
  34. };
  35. static bool lpass_cdc_is_valid_codec_dev(struct device *dev);
  36. int lpass_cdc_set_port_map(struct snd_soc_component *component,
  37. u32 size, void *data)
  38. {
  39. struct lpass_cdc_priv *priv = NULL;
  40. struct swr_mstr_port_map *map = NULL;
  41. u16 idx;
  42. if (!component || (size == 0) || !data)
  43. return -EINVAL;
  44. priv = snd_soc_component_get_drvdata(component);
  45. if (!priv)
  46. return -EINVAL;
  47. if (!lpass_cdc_is_valid_codec_dev(priv->dev)) {
  48. dev_err_ratelimited(priv->dev, "%s: invalid codec\n", __func__);
  49. return -EINVAL;
  50. }
  51. map = (struct swr_mstr_port_map *)data;
  52. for (idx = 0; idx < size; idx++) {
  53. if (priv->macro_params[map->id].set_port_map)
  54. priv->macro_params[map->id].set_port_map(component,
  55. map->uc,
  56. SWR_MSTR_PORT_LEN,
  57. map->swr_port_params);
  58. map += 1;
  59. }
  60. return 0;
  61. }
  62. EXPORT_SYMBOL(lpass_cdc_set_port_map);
  63. static void lpass_cdc_ahb_write_device(char __iomem *io_base,
  64. u16 reg, u8 value)
  65. {
  66. u32 temp = (u32)(value) & 0x000000FF;
  67. iowrite32(temp, io_base + reg);
  68. }
  69. static void lpass_cdc_ahb_read_device(char __iomem *io_base,
  70. u16 reg, u8 *value)
  71. {
  72. u32 temp;
  73. temp = ioread32(io_base + reg);
  74. *value = (u8)temp;
  75. }
  76. static int __lpass_cdc_reg_read(struct lpass_cdc_priv *priv,
  77. u16 macro_id, u16 reg, u8 *val)
  78. {
  79. int ret = 0;
  80. mutex_lock(&priv->clk_lock);
  81. if (!priv->dev_up) {
  82. dev_dbg_ratelimited(priv->dev,
  83. "%s: SSR in progress, exit\n", __func__);
  84. ret = -EINVAL;
  85. goto ssr_err;
  86. }
  87. if (priv->macro_params[VA_MACRO].dev) {
  88. pm_runtime_get_sync(priv->macro_params[VA_MACRO].dev);
  89. mutex_lock(&priv->vote_lock);
  90. if (((priv->lpass_core_hw_vote && !priv->core_hw_vote_count) ||
  91. (priv->lpass_audio_hw_vote && !priv->core_audio_vote_count))) {
  92. goto vote_err;
  93. }
  94. }
  95. lpass_cdc_ahb_read_device(
  96. priv->macro_params[macro_id].io_base, reg, val);
  97. vote_err:
  98. if (priv->macro_params[VA_MACRO].dev) {
  99. mutex_unlock(&priv->vote_lock);
  100. pm_runtime_mark_last_busy(priv->macro_params[VA_MACRO].dev);
  101. pm_runtime_put_autosuspend(priv->macro_params[VA_MACRO].dev);
  102. }
  103. ssr_err:
  104. mutex_unlock(&priv->clk_lock);
  105. return ret;
  106. }
  107. static int __lpass_cdc_reg_write(struct lpass_cdc_priv *priv,
  108. u16 macro_id, u16 reg, u8 val)
  109. {
  110. int ret = 0;
  111. mutex_lock(&priv->clk_lock);
  112. if (!priv->dev_up) {
  113. dev_dbg_ratelimited(priv->dev,
  114. "%s: SSR in progress, exit\n", __func__);
  115. ret = -EINVAL;
  116. goto ssr_err;
  117. }
  118. if (priv->macro_params[VA_MACRO].dev) {
  119. pm_runtime_get_sync(priv->macro_params[VA_MACRO].dev);
  120. mutex_lock(&priv->vote_lock);
  121. if (((priv->lpass_core_hw_vote && !priv->core_hw_vote_count) ||
  122. (priv->lpass_audio_hw_vote && !priv->core_audio_vote_count))) {
  123. goto vote_err;
  124. }
  125. }
  126. lpass_cdc_ahb_write_device(
  127. priv->macro_params[macro_id].io_base, reg, val);
  128. vote_err:
  129. if (priv->macro_params[VA_MACRO].dev) {
  130. mutex_unlock(&priv->vote_lock);
  131. pm_runtime_mark_last_busy(priv->macro_params[VA_MACRO].dev);
  132. pm_runtime_put_autosuspend(priv->macro_params[VA_MACRO].dev);
  133. }
  134. ssr_err:
  135. mutex_unlock(&priv->clk_lock);
  136. return ret;
  137. }
  138. static int lpass_cdc_update_wcd_event(void *handle, u16 event, u32 data)
  139. {
  140. struct lpass_cdc_priv *priv = (struct lpass_cdc_priv *)handle;
  141. if (!priv) {
  142. pr_err_ratelimited("%s:Invalid lpass_cdc priv handle\n", __func__);
  143. return -EINVAL;
  144. }
  145. switch (event) {
  146. case WCD_LPASS_CDC_EVT_RX_MUTE:
  147. if (priv->macro_params[RX_MACRO].event_handler)
  148. priv->macro_params[RX_MACRO].event_handler(
  149. priv->component,
  150. LPASS_CDC_MACRO_EVT_RX_MUTE, data);
  151. break;
  152. case WCD_LPASS_CDC_EVT_IMPED_TRUE:
  153. if (priv->macro_params[RX_MACRO].event_handler)
  154. priv->macro_params[RX_MACRO].event_handler(
  155. priv->component,
  156. LPASS_CDC_MACRO_EVT_IMPED_TRUE, data);
  157. break;
  158. case WCD_LPASS_CDC_EVT_IMPED_FALSE:
  159. if (priv->macro_params[RX_MACRO].event_handler)
  160. priv->macro_params[RX_MACRO].event_handler(
  161. priv->component,
  162. LPASS_CDC_MACRO_EVT_IMPED_FALSE, data);
  163. break;
  164. case WCD_LPASS_CDC_EVT_RX_COMPANDER_SOFT_RST:
  165. if (priv->macro_params[RX_MACRO].event_handler)
  166. priv->macro_params[RX_MACRO].event_handler(
  167. priv->component,
  168. LPASS_CDC_MACRO_EVT_RX_COMPANDER_SOFT_RST, data);
  169. break;
  170. case WCD_LPASS_CDC_EVT_BCS_CLK_OFF:
  171. if (priv->macro_params[TX_MACRO].event_handler)
  172. priv->macro_params[TX_MACRO].event_handler(
  173. priv->component,
  174. LPASS_CDC_MACRO_EVT_BCS_CLK_OFF, data);
  175. break;
  176. case WCD_LPASS_CDC_EVT_RX_PA_GAIN_UPDATE:
  177. if (priv->macro_params[RX_MACRO].event_handler)
  178. priv->macro_params[RX_MACRO].event_handler(
  179. priv->component,
  180. LPASS_CDC_MACRO_EVT_RX_PA_GAIN_UPDATE,
  181. data);
  182. break;
  183. case WCD_LPASS_CDC_EVT_HPHL_HD2_ENABLE:
  184. if (priv->macro_params[RX_MACRO].event_handler)
  185. priv->macro_params[RX_MACRO].event_handler(
  186. priv->component,
  187. LPASS_CDC_MACRO_EVT_HPHL_HD2_ENABLE, data);
  188. break;
  189. case WCD_LPASS_CDC_EVT_HPHR_HD2_ENABLE:
  190. if (priv->macro_params[RX_MACRO].event_handler)
  191. priv->macro_params[RX_MACRO].event_handler(
  192. priv->component,
  193. LPASS_CDC_MACRO_EVT_HPHR_HD2_ENABLE, data);
  194. break;
  195. default:
  196. dev_err_ratelimited(priv->dev, "%s: Invalid event %d trigger from wcd\n",
  197. __func__, event);
  198. return -EINVAL;
  199. }
  200. return 0;
  201. }
  202. static int lpass_cdc_register_notifier(void *handle,
  203. struct notifier_block *nblock,
  204. bool enable)
  205. {
  206. struct lpass_cdc_priv *priv = (struct lpass_cdc_priv *)handle;
  207. if (!priv || !nblock) {
  208. pr_err_ratelimited("%s: lpass_cdc priv or nblock is null\n", __func__);
  209. return -EINVAL;
  210. }
  211. if (enable)
  212. return blocking_notifier_chain_register(&priv->notifier,
  213. nblock);
  214. return blocking_notifier_chain_unregister(&priv->notifier,
  215. nblock);
  216. }
  217. static void lpass_cdc_notifier_call(struct lpass_cdc_priv *priv,
  218. u32 data)
  219. {
  220. dev_dbg(priv->dev, "%s: notifier call, data:%d\n", __func__, data);
  221. blocking_notifier_call_chain(&priv->notifier,
  222. data, (void *)priv->wcd_dev);
  223. }
  224. static bool lpass_cdc_is_valid_child_dev(struct device *dev)
  225. {
  226. if (of_device_is_compatible(dev->parent->of_node, "qcom,lpass-cdc"))
  227. return true;
  228. return false;
  229. }
  230. static bool lpass_cdc_is_valid_codec_dev(struct device *dev)
  231. {
  232. if (of_device_is_compatible(dev->of_node, "qcom,lpass-cdc"))
  233. return true;
  234. return false;
  235. }
  236. /**
  237. * lpass_cdc_clear_amic_tx_hold - clears AMIC register on analog codec
  238. *
  239. * @dev: lpass_cdc device ptr.
  240. *
  241. */
  242. void lpass_cdc_clear_amic_tx_hold(struct device *dev, u16 adc_n)
  243. {
  244. struct lpass_cdc_priv *priv;
  245. u16 event;
  246. u16 amic = 0;
  247. if (!dev) {
  248. pr_err("%s: dev is null\n", __func__);
  249. return;
  250. }
  251. if (!lpass_cdc_is_valid_codec_dev(dev)) {
  252. pr_err("%s: invalid codec\n", __func__);
  253. return;
  254. }
  255. priv = dev_get_drvdata(dev);
  256. if (!priv) {
  257. dev_err(dev, "%s: priv is null\n", __func__);
  258. return;
  259. }
  260. event = LPASS_CDC_WCD_EVT_TX_CH_HOLD_CLEAR;
  261. if (adc_n == LPASS_CDC_ADC0)
  262. amic = 0x1;
  263. else if (adc_n == LPASS_CDC_ADC1)
  264. amic = 0x2;
  265. else if (adc_n == LPASS_CDC_ADC2)
  266. amic = 0x2;
  267. else if (adc_n == LPASS_CDC_ADC3)
  268. amic = 0x3;
  269. else
  270. return;
  271. lpass_cdc_notifier_call(priv, (amic << 0x10 | event));
  272. }
  273. EXPORT_SYMBOL(lpass_cdc_clear_amic_tx_hold);
  274. /**
  275. * lpass_cdc_get_device_ptr - Get child or macro device ptr
  276. *
  277. * @dev: lpass_cdc device ptr.
  278. * @macro_id: ID of macro calling this API.
  279. *
  280. * Returns dev ptr on success or NULL on error.
  281. */
  282. struct device *lpass_cdc_get_device_ptr(struct device *dev, u16 macro_id)
  283. {
  284. struct lpass_cdc_priv *priv;
  285. if (!dev) {
  286. pr_err_ratelimited("%s: dev is null\n", __func__);
  287. return NULL;
  288. }
  289. if (!lpass_cdc_is_valid_codec_dev(dev)) {
  290. pr_err_ratelimited("%s: invalid codec\n", __func__);
  291. return NULL;
  292. }
  293. priv = dev_get_drvdata(dev);
  294. if (!priv || (macro_id >= MAX_MACRO)) {
  295. dev_err_ratelimited(dev, "%s: priv is null or invalid macro\n", __func__);
  296. return NULL;
  297. }
  298. return priv->macro_params[macro_id].dev;
  299. }
  300. EXPORT_SYMBOL(lpass_cdc_get_device_ptr);
  301. /**
  302. * lpass_cdc_get_rsc_clk_device_ptr - Get rsc clk device ptr
  303. *
  304. * @dev: lpass_cdc device ptr.
  305. *
  306. * Returns dev ptr on success or NULL on error.
  307. */
  308. struct device *lpass_cdc_get_rsc_clk_device_ptr(struct device *dev)
  309. {
  310. struct lpass_cdc_priv *priv;
  311. if (!dev) {
  312. pr_err_ratelimited("%s: dev is null\n", __func__);
  313. return NULL;
  314. }
  315. if (!lpass_cdc_is_valid_codec_dev(dev)) {
  316. pr_err_ratelimited("%s: invalid codec\n", __func__);
  317. return NULL;
  318. }
  319. priv = dev_get_drvdata(dev);
  320. if (!priv) {
  321. dev_err_ratelimited(dev, "%s: priv is null\n", __func__);
  322. return NULL;
  323. }
  324. return priv->clk_dev;
  325. }
  326. EXPORT_SYMBOL(lpass_cdc_get_rsc_clk_device_ptr);
  327. static int lpass_cdc_copy_dais_from_macro(struct lpass_cdc_priv *priv)
  328. {
  329. struct snd_soc_dai_driver *dai_ptr;
  330. u16 macro_idx;
  331. /* memcpy into lpass_cdc_dais all macro dais */
  332. if (!priv->lpass_cdc_dais)
  333. priv->lpass_cdc_dais = devm_kzalloc(priv->dev,
  334. priv->num_dais *
  335. sizeof(
  336. struct snd_soc_dai_driver),
  337. GFP_KERNEL);
  338. if (!priv->lpass_cdc_dais)
  339. return -ENOMEM;
  340. dai_ptr = priv->lpass_cdc_dais;
  341. for (macro_idx = START_MACRO; macro_idx < MAX_MACRO; macro_idx++) {
  342. if (priv->macro_params[macro_idx].dai_ptr) {
  343. memcpy(dai_ptr,
  344. priv->macro_params[macro_idx].dai_ptr,
  345. priv->macro_params[macro_idx].num_dais *
  346. sizeof(struct snd_soc_dai_driver));
  347. dai_ptr += priv->macro_params[macro_idx].num_dais;
  348. }
  349. }
  350. return 0;
  351. }
  352. /**
  353. * lpass_cdc_register_res_clk - Registers rsc clk driver to lpass_cdc
  354. *
  355. * @dev: rsc clk device ptr.
  356. * @rsc_clk_cb: event handler callback for notifications like SSR
  357. *
  358. * Returns 0 on success or -EINVAL on error.
  359. */
  360. int lpass_cdc_register_res_clk(struct device *dev, rsc_clk_cb_t rsc_clk_cb)
  361. {
  362. struct lpass_cdc_priv *priv;
  363. if (!dev || !rsc_clk_cb) {
  364. pr_err_ratelimited("%s: dev or rsc_clk_cb is null\n", __func__);
  365. return -EINVAL;
  366. }
  367. if (!lpass_cdc_is_valid_child_dev(dev)) {
  368. dev_err_ratelimited(dev, "%s: child device :%pK not added yet\n",
  369. __func__, dev);
  370. return -EINVAL;
  371. }
  372. priv = dev_get_drvdata(dev->parent);
  373. if (!priv) {
  374. dev_err_ratelimited(dev, "%s: priv is null\n", __func__);
  375. return -EINVAL;
  376. }
  377. priv->clk_dev = dev;
  378. priv->rsc_clk_cb = rsc_clk_cb;
  379. return 0;
  380. }
  381. EXPORT_SYMBOL(lpass_cdc_register_res_clk);
  382. /**
  383. * lpass_cdc_unregister_res_clk - Unregisters rsc clk driver from lpass_cdc
  384. *
  385. * @dev: resource clk device ptr.
  386. */
  387. void lpass_cdc_unregister_res_clk(struct device *dev)
  388. {
  389. struct lpass_cdc_priv *priv;
  390. if (!dev) {
  391. pr_err_ratelimited("%s: dev is NULL\n", __func__);
  392. return;
  393. }
  394. if (!lpass_cdc_is_valid_child_dev(dev)) {
  395. dev_err_ratelimited(dev, "%s: child device :%pK not added\n",
  396. __func__, dev);
  397. return;
  398. }
  399. priv = dev_get_drvdata(dev->parent);
  400. if (!priv) {
  401. dev_err_ratelimited(dev, "%s: priv is null\n", __func__);
  402. return;
  403. }
  404. priv->clk_dev = NULL;
  405. priv->rsc_clk_cb = NULL;
  406. }
  407. EXPORT_SYMBOL(lpass_cdc_unregister_res_clk);
  408. static u8 lpass_cdc_dmic_clk_div_get(struct snd_soc_component *component,
  409. u32 mode)
  410. {
  411. struct lpass_cdc_priv* priv = snd_soc_component_get_drvdata(component);
  412. int macro = (mode ? VA_MACRO : TX_MACRO);
  413. int ret = 0;
  414. if (priv->macro_params[macro].clk_div_get) {
  415. ret = priv->macro_params[macro].clk_div_get(component);
  416. if (ret >= 0)
  417. return ret;
  418. }
  419. return 1;
  420. }
  421. int lpass_cdc_dmic_clk_enable(struct snd_soc_component *component,
  422. u32 dmic, u32 tx_mode, bool enable)
  423. {
  424. struct lpass_cdc_priv* priv = snd_soc_component_get_drvdata(component);
  425. u8 dmic_clk_en = 0x01;
  426. u16 dmic_clk_reg = 0;
  427. s32 *dmic_clk_cnt = NULL;
  428. u8 *dmic_clk_div = NULL;
  429. u8 freq_change_mask = 0;
  430. u8 clk_div = 0;
  431. dev_dbg(component->dev, "%s: enable: %d, tx_mode:%d, dmic: %d\n",
  432. __func__, enable, tx_mode, dmic);
  433. switch (dmic) {
  434. case 0:
  435. case 1:
  436. dmic_clk_cnt = &(priv->dmic_0_1_clk_cnt);
  437. dmic_clk_div = &(priv->dmic_0_1_clk_div);
  438. dmic_clk_reg = LPASS_CDC_VA_TOP_CSR_DMIC0_CTL;
  439. freq_change_mask = 0x01;
  440. break;
  441. case 2:
  442. case 3:
  443. dmic_clk_cnt = &(priv->dmic_2_3_clk_cnt);
  444. dmic_clk_div = &(priv->dmic_2_3_clk_div);
  445. dmic_clk_reg = LPASS_CDC_VA_TOP_CSR_DMIC1_CTL;
  446. freq_change_mask = 0x02;
  447. break;
  448. case 4:
  449. case 5:
  450. dmic_clk_cnt = &(priv->dmic_4_5_clk_cnt);
  451. dmic_clk_div = &(priv->dmic_4_5_clk_div);
  452. dmic_clk_reg = LPASS_CDC_VA_TOP_CSR_DMIC2_CTL;
  453. freq_change_mask = 0x04;
  454. break;
  455. case 6:
  456. case 7:
  457. dmic_clk_cnt = &(priv->dmic_6_7_clk_cnt);
  458. dmic_clk_div = &(priv->dmic_6_7_clk_div);
  459. dmic_clk_reg = LPASS_CDC_VA_TOP_CSR_DMIC3_CTL;
  460. freq_change_mask = 0x08;
  461. break;
  462. default:
  463. dev_err_ratelimited(component->dev, "%s: Invalid DMIC Selection\n",
  464. __func__);
  465. return -EINVAL;
  466. }
  467. dev_dbg(component->dev, "%s: DMIC%d dmic_clk_cnt %d\n",
  468. __func__, dmic, *dmic_clk_cnt);
  469. if (enable) {
  470. clk_div = lpass_cdc_dmic_clk_div_get(component, tx_mode);
  471. (*dmic_clk_cnt)++;
  472. if (*dmic_clk_cnt == 1) {
  473. snd_soc_component_update_bits(component,
  474. LPASS_CDC_VA_TOP_CSR_DMIC_CFG,
  475. 0x80, 0x00);
  476. snd_soc_component_update_bits(component, dmic_clk_reg,
  477. 0x0E, clk_div << 0x1);
  478. snd_soc_component_update_bits(component, dmic_clk_reg,
  479. dmic_clk_en, dmic_clk_en);
  480. } else {
  481. if (*dmic_clk_div > clk_div) {
  482. snd_soc_component_update_bits(component,
  483. LPASS_CDC_VA_TOP_CSR_DMIC_CFG,
  484. freq_change_mask, freq_change_mask);
  485. snd_soc_component_update_bits(component, dmic_clk_reg,
  486. 0x0E, clk_div << 0x1);
  487. snd_soc_component_update_bits(component,
  488. LPASS_CDC_VA_TOP_CSR_DMIC_CFG,
  489. freq_change_mask, 0x00);
  490. } else {
  491. clk_div = *dmic_clk_div;
  492. }
  493. }
  494. *dmic_clk_div = clk_div;
  495. } else {
  496. (*dmic_clk_cnt)--;
  497. if (*dmic_clk_cnt == 0) {
  498. snd_soc_component_update_bits(component, dmic_clk_reg,
  499. dmic_clk_en, 0);
  500. clk_div = 0;
  501. snd_soc_component_update_bits(component, dmic_clk_reg,
  502. 0x0E, clk_div << 0x1);
  503. } else {
  504. clk_div = lpass_cdc_dmic_clk_div_get(component, tx_mode);
  505. if (*dmic_clk_div > clk_div) {
  506. clk_div = lpass_cdc_dmic_clk_div_get(component, !tx_mode);
  507. snd_soc_component_update_bits(component,
  508. LPASS_CDC_VA_TOP_CSR_DMIC_CFG,
  509. freq_change_mask, freq_change_mask);
  510. snd_soc_component_update_bits(component, dmic_clk_reg,
  511. 0x0E, clk_div << 0x1);
  512. snd_soc_component_update_bits(component,
  513. LPASS_CDC_VA_TOP_CSR_DMIC_CFG,
  514. freq_change_mask, 0x00);
  515. } else {
  516. clk_div = *dmic_clk_div;
  517. }
  518. }
  519. *dmic_clk_div = clk_div;
  520. }
  521. return 0;
  522. }
  523. EXPORT_SYMBOL(lpass_cdc_dmic_clk_enable);
  524. bool lpass_cdc_is_va_macro_registered(struct device *dev)
  525. {
  526. struct lpass_cdc_priv *priv;
  527. if (!dev) {
  528. pr_err_ratelimited("%s: dev is null\n", __func__);
  529. return false;
  530. }
  531. if (!lpass_cdc_is_valid_child_dev(dev)) {
  532. dev_err_ratelimited(dev, "%s: child device calling is not added yet\n",
  533. __func__);
  534. return false;
  535. }
  536. priv = dev_get_drvdata(dev->parent);
  537. if (!priv) {
  538. dev_err_ratelimited(dev, "%s: priv is null\n", __func__);
  539. return false;
  540. }
  541. return priv->macros_supported[VA_MACRO];
  542. }
  543. EXPORT_SYMBOL(lpass_cdc_is_va_macro_registered);
  544. /**
  545. * lpass_cdc_register_macro - Registers macro to lpass_cdc
  546. *
  547. * @dev: macro device ptr.
  548. * @macro_id: ID of macro calling this API.
  549. * @ops: macro params to register.
  550. *
  551. * Returns 0 on success or -EINVAL on error.
  552. */
  553. int lpass_cdc_register_macro(struct device *dev, u16 macro_id,
  554. struct macro_ops *ops)
  555. {
  556. struct lpass_cdc_priv *priv;
  557. int ret = -EINVAL;
  558. if (!dev || !ops) {
  559. pr_err("%s: dev or ops is null\n", __func__);
  560. return -EINVAL;
  561. }
  562. if (!lpass_cdc_is_valid_child_dev(dev)) {
  563. dev_err(dev, "%s: child device for macro:%d not added yet\n",
  564. __func__, macro_id);
  565. return -EINVAL;
  566. }
  567. priv = dev_get_drvdata(dev->parent);
  568. if (!priv || (macro_id >= MAX_MACRO)) {
  569. dev_err(dev, "%s: priv is null or invalid macro\n", __func__);
  570. return -EINVAL;
  571. }
  572. priv->macro_params[macro_id].clk_id_req = ops->clk_id_req;
  573. priv->macro_params[macro_id].default_clk_id = ops->default_clk_id;
  574. priv->macro_params[macro_id].init = ops->init;
  575. priv->macro_params[macro_id].exit = ops->exit;
  576. priv->macro_params[macro_id].io_base = ops->io_base;
  577. priv->macro_params[macro_id].num_dais = ops->num_dais;
  578. priv->macro_params[macro_id].dai_ptr = ops->dai_ptr;
  579. priv->macro_params[macro_id].event_handler = ops->event_handler;
  580. priv->macro_params[macro_id].set_port_map = ops->set_port_map;
  581. priv->macro_params[macro_id].dev = dev;
  582. priv->current_mclk_mux_macro[macro_id] =
  583. lpass_cdc_mclk_mux_tbl[macro_id][MCLK_MUX0];
  584. if (macro_id == TX_MACRO) {
  585. priv->macro_params[macro_id].reg_wake_irq = ops->reg_wake_irq;
  586. priv->macro_params[macro_id].reg_evt_listener =
  587. ops->reg_evt_listener;
  588. priv->macro_params[macro_id].clk_enable = ops->clk_enable;
  589. }
  590. if (macro_id == TX_MACRO || macro_id == VA_MACRO)
  591. priv->macro_params[macro_id].clk_div_get = ops->clk_div_get;
  592. if (macro_id == VA_MACRO)
  593. priv->macro_params[macro_id].reg_wake_irq =
  594. ops->reg_wake_irq;
  595. mutex_lock(&priv->macro_lock);
  596. priv->num_dais += ops->num_dais;
  597. priv->num_macros_registered++;
  598. priv->macros_supported[macro_id] = true;
  599. dev_info(dev, "%s: register macro successful:%d\n", __func__, macro_id);
  600. if (priv->num_macros_registered == priv->num_macros) {
  601. ret = lpass_cdc_copy_dais_from_macro(priv);
  602. if (ret < 0) {
  603. dev_err(dev, "%s: copy_dais failed\n", __func__);
  604. mutex_unlock(&priv->macro_lock);
  605. return ret;
  606. }
  607. if (priv->macros_supported[TX_MACRO] == false) {
  608. lpass_cdc_mclk_mux_tbl[WSA_MACRO][MCLK_MUX0] = WSA_MACRO;
  609. priv->current_mclk_mux_macro[WSA_MACRO] = WSA_MACRO;
  610. lpass_cdc_mclk_mux_tbl[VA_MACRO][MCLK_MUX0] = VA_MACRO;
  611. priv->current_mclk_mux_macro[VA_MACRO] = VA_MACRO;
  612. }
  613. ret = snd_soc_register_component(dev->parent, &lpass_cdc,
  614. priv->lpass_cdc_dais, priv->num_dais);
  615. if (ret < 0) {
  616. dev_err(dev, "%s: register codec failed\n", __func__);
  617. mutex_unlock(&priv->macro_lock);
  618. return ret;
  619. }
  620. }
  621. mutex_unlock(&priv->macro_lock);
  622. return 0;
  623. }
  624. EXPORT_SYMBOL(lpass_cdc_register_macro);
  625. /**
  626. * lpass_cdc_unregister_macro - De-Register macro from lpass_cdc
  627. *
  628. * @dev: macro device ptr.
  629. * @macro_id: ID of macro calling this API.
  630. *
  631. */
  632. void lpass_cdc_unregister_macro(struct device *dev, u16 macro_id)
  633. {
  634. struct lpass_cdc_priv *priv;
  635. if (!dev) {
  636. pr_err_ratelimited("%s: dev is null\n", __func__);
  637. return;
  638. }
  639. if (!lpass_cdc_is_valid_child_dev(dev)) {
  640. dev_err_ratelimited(dev, "%s: macro:%d not in valid registered macro-list\n",
  641. __func__, macro_id);
  642. return;
  643. }
  644. priv = dev_get_drvdata(dev->parent);
  645. if (!priv || (macro_id >= MAX_MACRO)) {
  646. dev_err_ratelimited(dev, "%s: priv is null or invalid macro\n", __func__);
  647. return;
  648. }
  649. priv->macro_params[macro_id].init = NULL;
  650. priv->macro_params[macro_id].num_dais = 0;
  651. priv->macro_params[macro_id].dai_ptr = NULL;
  652. priv->macro_params[macro_id].event_handler = NULL;
  653. priv->macro_params[macro_id].dev = NULL;
  654. if (macro_id == TX_MACRO) {
  655. priv->macro_params[macro_id].reg_wake_irq = NULL;
  656. priv->macro_params[macro_id].reg_evt_listener = NULL;
  657. priv->macro_params[macro_id].clk_enable = NULL;
  658. }
  659. if (macro_id == TX_MACRO || macro_id == VA_MACRO)
  660. priv->macro_params[macro_id].clk_div_get = NULL;
  661. priv->num_dais -= priv->macro_params[macro_id].num_dais;
  662. priv->num_macros_registered--;
  663. /* UNREGISTER CODEC HERE */
  664. if (priv->num_macros - 1 == priv->num_macros_registered)
  665. snd_soc_unregister_component(dev->parent);
  666. }
  667. EXPORT_SYMBOL(lpass_cdc_unregister_macro);
  668. void lpass_cdc_notify_wcd_rx_clk(struct device *dev, bool is_native_on)
  669. {
  670. struct lpass_cdc_priv *priv;
  671. u32 val;
  672. if (!dev) {
  673. pr_err_ratelimited("%s: dev is null\n", __func__);
  674. return;
  675. }
  676. if (!lpass_cdc_is_valid_child_dev(dev)) {
  677. dev_err_ratelimited(dev, "%s: not a valid child dev\n",
  678. __func__);
  679. return;
  680. }
  681. priv = dev_get_drvdata(dev->parent);
  682. if (!priv) {
  683. dev_err_ratelimited(dev, "%s: priv is null\n", __func__);
  684. return;
  685. }
  686. if (is_native_on)
  687. val = 0x2; /* 11.2896M */
  688. else
  689. val = 0x0; /* 9.6M */
  690. lpass_cdc_notifier_call(priv,
  691. ((val << 16) | LPASS_CDC_WCD_EVT_CLK_NOTIFY));
  692. }
  693. EXPORT_SYMBOL(lpass_cdc_notify_wcd_rx_clk);
  694. void lpass_cdc_wsa_pa_on(struct device *dev, bool adie_lb)
  695. {
  696. struct lpass_cdc_priv *priv;
  697. if (!dev) {
  698. pr_err_ratelimited("%s: dev is null\n", __func__);
  699. return;
  700. }
  701. if (!lpass_cdc_is_valid_child_dev(dev)) {
  702. dev_err_ratelimited(dev, "%s: not a valid child dev\n",
  703. __func__);
  704. return;
  705. }
  706. priv = dev_get_drvdata(dev->parent);
  707. if (!priv) {
  708. dev_err_ratelimited(dev, "%s: priv is null\n", __func__);
  709. return;
  710. }
  711. if (adie_lb)
  712. lpass_cdc_notifier_call(priv,
  713. LPASS_CDC_WCD_EVT_PA_ON_POST_FSCLK_ADIE_LB);
  714. else
  715. lpass_cdc_notifier_call(priv,
  716. LPASS_CDC_WCD_EVT_PA_ON_POST_FSCLK);
  717. }
  718. EXPORT_SYMBOL(lpass_cdc_wsa_pa_on);
  719. int lpass_cdc_get_version(struct device *dev)
  720. {
  721. struct lpass_cdc_priv *priv;
  722. if (!dev) {
  723. pr_err("%s: dev is null\n", __func__);
  724. return -EINVAL;
  725. }
  726. if (!lpass_cdc_is_valid_child_dev(dev)) {
  727. dev_err(dev, "%s: child device for macro not added yet\n",
  728. __func__);
  729. return -EINVAL;
  730. }
  731. priv = dev_get_drvdata(dev->parent);
  732. if (!priv) {
  733. dev_err(dev, "%s: priv is null\n", __func__);
  734. return -EINVAL;
  735. }
  736. return priv->version;
  737. }
  738. EXPORT_SYMBOL(lpass_cdc_get_version);
  739. static ssize_t lpass_cdc_version_read(struct snd_info_entry *entry,
  740. void *file_private_data,
  741. struct file *file,
  742. char __user *buf, size_t count,
  743. loff_t pos)
  744. {
  745. struct lpass_cdc_priv *priv;
  746. char buffer[LPASS_CDC_VERSION_ENTRY_SIZE];
  747. int len = 0;
  748. priv = (struct lpass_cdc_priv *) entry->private_data;
  749. if (!priv) {
  750. pr_err_ratelimited("%s: lpass_cdc priv is null\n", __func__);
  751. return -EINVAL;
  752. }
  753. switch (priv->version) {
  754. case LPASS_CDC_VERSION_1_0:
  755. len = snprintf(buffer, sizeof(buffer), "LPASS-CDC_1_0\n");
  756. break;
  757. case LPASS_CDC_VERSION_1_1:
  758. len = snprintf(buffer, sizeof(buffer), "LPASS-CDC_1_1\n");
  759. break;
  760. case LPASS_CDC_VERSION_1_2:
  761. len = snprintf(buffer, sizeof(buffer), "LPASS-CDC_1_2\n");
  762. break;
  763. case LPASS_CDC_VERSION_2_1:
  764. len = snprintf(buffer, sizeof(buffer), "LPASS-CDC_2_1\n");
  765. break;
  766. case LPASS_CDC_VERSION_2_5:
  767. len = snprintf(buffer, sizeof(buffer), "LPASS-CDC_2_5\n");
  768. break;
  769. case LPASS_CDC_VERSION_2_6:
  770. len = snprintf(buffer, sizeof(buffer), "LPASS-CDC_2_6\n");
  771. break;
  772. default:
  773. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  774. }
  775. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  776. }
  777. static int lpass_cdc_ssr_enable(struct device *dev, void *data)
  778. {
  779. struct lpass_cdc_priv *priv = data;
  780. int macro_idx;
  781. if (priv->initial_boot) {
  782. priv->initial_boot = false;
  783. return 0;
  784. }
  785. if (priv->rsc_clk_cb)
  786. priv->rsc_clk_cb(priv->clk_dev, LPASS_CDC_MACRO_EVT_SSR_UP);
  787. for (macro_idx = START_MACRO; macro_idx < MAX_MACRO; macro_idx++) {
  788. if (priv->macro_params[macro_idx].event_handler)
  789. priv->macro_params[macro_idx].event_handler(
  790. priv->component,
  791. LPASS_CDC_MACRO_EVT_CLK_RESET, 0x0);
  792. }
  793. mutex_lock(&priv->clk_lock);
  794. priv->pre_dev_up = true;
  795. mutex_unlock(&priv->clk_lock);
  796. if (priv->rsc_clk_cb)
  797. priv->rsc_clk_cb(priv->clk_dev, LPASS_CDC_MACRO_EVT_SSR_GFMUX_UP);
  798. for (macro_idx = START_MACRO; macro_idx < MAX_MACRO; macro_idx++) {
  799. if (!priv->macro_params[macro_idx].event_handler)
  800. continue;
  801. priv->macro_params[macro_idx].event_handler(
  802. priv->component,
  803. LPASS_CDC_MACRO_EVT_PRE_SSR_UP, 0x0);
  804. }
  805. regcache_cache_only(priv->regmap, false);
  806. mutex_lock(&priv->clk_lock);
  807. priv->dev_up = true;
  808. mutex_unlock(&priv->clk_lock);
  809. regcache_mark_dirty(priv->regmap);
  810. lpass_cdc_clk_rsc_enable_all_clocks(priv->clk_dev, true);
  811. regcache_sync(priv->regmap);
  812. /* Add a 100usec sleep to ensure last register write is done */
  813. usleep_range(100,110);
  814. lpass_cdc_clk_rsc_enable_all_clocks(priv->clk_dev, false);
  815. /* call ssr event for supported macros */
  816. for (macro_idx = START_MACRO; macro_idx < MAX_MACRO; macro_idx++) {
  817. if (!priv->macro_params[macro_idx].event_handler)
  818. continue;
  819. priv->macro_params[macro_idx].event_handler(
  820. priv->component,
  821. LPASS_CDC_MACRO_EVT_SSR_UP, 0x0);
  822. }
  823. lpass_cdc_notifier_call(priv, LPASS_CDC_WCD_EVT_SSR_UP);
  824. return 0;
  825. }
  826. static void lpass_cdc_ssr_disable(struct device *dev, void *data)
  827. {
  828. struct lpass_cdc_priv *priv = data;
  829. int macro_idx;
  830. if (!priv->dev_up) {
  831. dev_err_ratelimited(priv->dev,
  832. "%s: already disabled\n", __func__);
  833. return;
  834. }
  835. regcache_cache_only(priv->regmap, true);
  836. mutex_lock(&priv->clk_lock);
  837. priv->dev_up = false;
  838. priv->pre_dev_up = false;
  839. mutex_unlock(&priv->clk_lock);
  840. if (priv->rsc_clk_cb)
  841. priv->rsc_clk_cb(priv->clk_dev, LPASS_CDC_MACRO_EVT_SSR_DOWN);
  842. /* call ssr event for supported macros */
  843. for (macro_idx = START_MACRO; macro_idx < MAX_MACRO; macro_idx++) {
  844. if (!priv->macro_params[macro_idx].event_handler)
  845. continue;
  846. priv->macro_params[macro_idx].event_handler(
  847. priv->component,
  848. LPASS_CDC_MACRO_EVT_SSR_DOWN, 0x0);
  849. }
  850. lpass_cdc_notifier_call(priv, LPASS_CDC_WCD_EVT_SSR_DOWN);
  851. }
  852. static struct snd_info_entry_ops lpass_cdc_info_ops = {
  853. .read = lpass_cdc_version_read,
  854. };
  855. static const struct snd_event_ops lpass_cdc_ssr_ops = {
  856. .enable = lpass_cdc_ssr_enable,
  857. .disable = lpass_cdc_ssr_disable,
  858. };
  859. /*
  860. * lpass_cdc_info_create_codec_entry - creates lpass_cdc module
  861. * @codec_root: The parent directory
  862. * @component: Codec component instance
  863. *
  864. * Creates lpass_cdc module and version entry under the given
  865. * parent directory.
  866. *
  867. * Return: 0 on success or negative error code on failure.
  868. */
  869. int lpass_cdc_info_create_codec_entry(struct snd_info_entry *codec_root,
  870. struct snd_soc_component *component)
  871. {
  872. struct snd_info_entry *version_entry;
  873. struct lpass_cdc_priv *priv;
  874. struct snd_soc_card *card;
  875. if (!codec_root || !component)
  876. return -EINVAL;
  877. priv = snd_soc_component_get_drvdata(component);
  878. if (priv->entry) {
  879. dev_dbg(priv->dev,
  880. "%s:lpass_cdc module already created\n", __func__);
  881. return 0;
  882. }
  883. card = component->card;
  884. priv->entry = snd_info_create_module_entry(codec_root->module,
  885. "lpass-cdc", codec_root);
  886. if (!priv->entry) {
  887. dev_dbg(component->dev, "%s: failed to create lpass_cdc entry\n",
  888. __func__);
  889. return -ENOMEM;
  890. }
  891. priv->entry->mode = S_IFDIR | 0555;
  892. if (snd_info_register(priv->entry) < 0) {
  893. snd_info_free_entry(priv->entry);
  894. return -ENOMEM;
  895. }
  896. version_entry = snd_info_create_card_entry(card->snd_card,
  897. "version",
  898. priv->entry);
  899. if (!version_entry) {
  900. dev_err_ratelimited(component->dev, "%s: failed to create lpass_cdc version entry\n",
  901. __func__);
  902. snd_info_free_entry(priv->entry);
  903. return -ENOMEM;
  904. }
  905. version_entry->private_data = priv;
  906. version_entry->size = LPASS_CDC_VERSION_ENTRY_SIZE;
  907. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  908. version_entry->c.ops = &lpass_cdc_info_ops;
  909. if (snd_info_register(version_entry) < 0) {
  910. snd_info_free_entry(version_entry);
  911. snd_info_free_entry(priv->entry);
  912. return -ENOMEM;
  913. }
  914. priv->version_entry = version_entry;
  915. return 0;
  916. }
  917. EXPORT_SYMBOL(lpass_cdc_info_create_codec_entry);
  918. /**
  919. * lpass_cdc_register_wake_irq - Register wake irq of Tx macro
  920. *
  921. * @component: codec component ptr.
  922. * @ipc_wakeup: bool to identify ipc_wakeup to be used or HW interrupt line.
  923. *
  924. * Return: 0 on success or negative error code on failure.
  925. */
  926. int lpass_cdc_register_wake_irq(struct snd_soc_component *component,
  927. u32 ipc_wakeup)
  928. {
  929. struct lpass_cdc_priv *priv = NULL;
  930. if (!component)
  931. return -EINVAL;
  932. priv = snd_soc_component_get_drvdata(component);
  933. if (!priv)
  934. return -EINVAL;
  935. if (!lpass_cdc_is_valid_codec_dev(priv->dev)) {
  936. dev_err_ratelimited(component->dev, "%s: invalid codec\n", __func__);
  937. return -EINVAL;
  938. }
  939. if (priv->macro_params[VA_MACRO].reg_wake_irq)
  940. priv->macro_params[VA_MACRO].reg_wake_irq(
  941. component, ipc_wakeup);
  942. return 0;
  943. }
  944. EXPORT_SYMBOL(lpass_cdc_register_wake_irq);
  945. /**
  946. * lpass_cdc_tx_mclk_enable - Enable/Disable TX Macro mclk
  947. *
  948. * @component: pointer to codec component instance.
  949. * @enable: set true to enable, otherwise false.
  950. *
  951. * Returns 0 on success or -EINVAL on error.
  952. */
  953. int lpass_cdc_tx_mclk_enable(struct snd_soc_component *component,
  954. bool enable)
  955. {
  956. struct lpass_cdc_priv *priv = NULL;
  957. int ret = 0;
  958. if (!component)
  959. return -EINVAL;
  960. priv = snd_soc_component_get_drvdata(component);
  961. if (!priv)
  962. return -EINVAL;
  963. if (!lpass_cdc_is_valid_codec_dev(priv->dev)) {
  964. dev_err_ratelimited(component->dev, "%s: invalid codec\n", __func__);
  965. return -EINVAL;
  966. }
  967. if (priv->macro_params[TX_MACRO].clk_enable)
  968. ret = priv->macro_params[TX_MACRO].clk_enable(component,
  969. enable);
  970. return ret;
  971. }
  972. EXPORT_SYMBOL(lpass_cdc_tx_mclk_enable);
  973. /**
  974. * lpass_cdc_register_event_listener - Register/Deregister to event listener
  975. *
  976. * @component: pointer to codec component instance.
  977. * @enable: when set to 1 registers to event listener otherwise, derigisters
  978. * from the event listener
  979. *
  980. * Returns 0 on success or -EINVAL on error.
  981. */
  982. int lpass_cdc_register_event_listener(struct snd_soc_component *component,
  983. bool enable)
  984. {
  985. struct lpass_cdc_priv *priv = NULL;
  986. int ret = 0;
  987. if (!component)
  988. return -EINVAL;
  989. priv = snd_soc_component_get_drvdata(component);
  990. if (!priv)
  991. return -EINVAL;
  992. if (!lpass_cdc_is_valid_codec_dev(priv->dev)) {
  993. dev_err_ratelimited(component->dev, "%s: invalid codec\n", __func__);
  994. return -EINVAL;
  995. }
  996. if (priv->macro_params[TX_MACRO].reg_evt_listener)
  997. ret = priv->macro_params[TX_MACRO].reg_evt_listener(component,
  998. enable);
  999. return ret;
  1000. }
  1001. EXPORT_SYMBOL(lpass_cdc_register_event_listener);
  1002. static int lpass_cdc_soc_codec_probe(struct snd_soc_component *component)
  1003. {
  1004. struct lpass_cdc_priv *priv = dev_get_drvdata(component->dev);
  1005. int macro_idx, ret = 0;
  1006. u8 core_id_0 = 0, core_id_1 = 0, core_id_2 = 0;
  1007. snd_soc_component_init_regmap(component, priv->regmap);
  1008. if (!priv->version) {
  1009. /*
  1010. * In order for the ADIE RTC to differentiate between targets
  1011. * version info is used.
  1012. * Assign 1.0 for target with only one macro
  1013. * Assign 1.1 for target with two macros
  1014. * Assign 1.2 for target with more than two macros
  1015. */
  1016. if (priv->num_macros_registered == 1)
  1017. priv->version = LPASS_CDC_VERSION_1_0;
  1018. else if (priv->num_macros_registered == 2)
  1019. priv->version = LPASS_CDC_VERSION_1_1;
  1020. else if (priv->num_macros_registered > 2)
  1021. priv->version = LPASS_CDC_VERSION_1_2;
  1022. }
  1023. /* Assign lpass_cdc version */
  1024. core_id_0 = snd_soc_component_read(component,
  1025. LPASS_CDC_VA_TOP_CSR_CORE_ID_0);
  1026. core_id_1 = snd_soc_component_read(component,
  1027. LPASS_CDC_VA_TOP_CSR_CORE_ID_1);
  1028. core_id_2 = snd_soc_component_read(component,
  1029. LPASS_CDC_VA_TOP_CSR_CORE_ID_2);
  1030. if ((core_id_0 == 0x01) && (core_id_1 == 0x0F))
  1031. priv->version = LPASS_CDC_VERSION_2_0;
  1032. if ((core_id_0 == 0x02) && (core_id_1 == 0x0E))
  1033. priv->version = LPASS_CDC_VERSION_2_1;
  1034. if ((core_id_0 == 0x02) && (core_id_1 == 0x0F) && (core_id_2 == 0x50 || core_id_2 == 0x51))
  1035. priv->version = LPASS_CDC_VERSION_2_5;
  1036. if ((core_id_0 == 0x02) && (core_id_1 == 0x0F) && (core_id_2 == 0x60 || core_id_2 == 0x61))
  1037. priv->version = LPASS_CDC_VERSION_2_6;
  1038. if ((core_id_0 == 0x02) && (core_id_1 == 0x0F) && (core_id_2 == 0x70 || core_id_2 == 0x71))
  1039. priv->version = LPASS_CDC_VERSION_2_7;
  1040. if ((core_id_0 == 0x02) && (core_id_1 == 0x0F) && (core_id_2 == 0x80 || core_id_2 == 0x81))
  1041. priv->version = LPASS_CDC_VERSION_2_8;
  1042. /* call init for supported macros */
  1043. for (macro_idx = START_MACRO; macro_idx < MAX_MACRO; macro_idx++) {
  1044. if (priv->macro_params[macro_idx].init) {
  1045. ret = priv->macro_params[macro_idx].init(component);
  1046. if (ret < 0) {
  1047. dev_err(component->dev,
  1048. "%s: init for macro %d failed\n",
  1049. __func__, macro_idx);
  1050. goto err;
  1051. }
  1052. }
  1053. }
  1054. priv->component = component;
  1055. ret = snd_event_client_register(priv->dev, &lpass_cdc_ssr_ops, priv);
  1056. if (!ret) {
  1057. snd_event_notify(priv->dev, SND_EVENT_UP);
  1058. } else {
  1059. dev_err(component->dev,
  1060. "%s: Registration with SND event FWK failed ret = %d\n",
  1061. __func__, ret);
  1062. goto err;
  1063. }
  1064. dev_dbg(component->dev, "%s: lpass_cdc soc codec probe success\n",
  1065. __func__);
  1066. err:
  1067. return ret;
  1068. }
  1069. static void lpass_cdc_soc_codec_remove(struct snd_soc_component *component)
  1070. {
  1071. struct lpass_cdc_priv *priv = dev_get_drvdata(component->dev);
  1072. int macro_idx;
  1073. snd_event_client_deregister(priv->dev);
  1074. /* call exit for supported macros */
  1075. for (macro_idx = START_MACRO; macro_idx < MAX_MACRO; macro_idx++)
  1076. if (priv->macro_params[macro_idx].exit)
  1077. priv->macro_params[macro_idx].exit(component);
  1078. return;
  1079. }
  1080. static const struct snd_soc_component_driver lpass_cdc = {
  1081. .name = DRV_NAME,
  1082. .probe = lpass_cdc_soc_codec_probe,
  1083. .remove = lpass_cdc_soc_codec_remove,
  1084. };
  1085. static void lpass_cdc_add_child_devices(struct work_struct *work)
  1086. {
  1087. struct lpass_cdc_priv *priv;
  1088. bool split_codec = false;
  1089. struct platform_device *pdev;
  1090. struct device_node *node;
  1091. int ret = 0, count = 0;
  1092. struct wcd_ctrl_platform_data *platdata = NULL;
  1093. char plat_dev_name[LPASS_CDC_STRING_LEN] = "";
  1094. priv = container_of(work, struct lpass_cdc_priv,
  1095. lpass_cdc_add_child_devices_work);
  1096. if (!priv) {
  1097. pr_err("%s: Memory for lpass_cdc priv does not exist\n",
  1098. __func__);
  1099. return;
  1100. }
  1101. if (!priv->dev || !priv->dev->of_node) {
  1102. dev_err(priv->dev, "%s: DT node for lpass_cdc does not exist\n",
  1103. __func__);
  1104. return;
  1105. }
  1106. platdata = &priv->plat_data;
  1107. priv->child_count = 0;
  1108. for_each_available_child_of_node(priv->dev->of_node, node) {
  1109. split_codec = false;
  1110. if (of_find_property(node, "qcom,split-codec", NULL)) {
  1111. split_codec = true;
  1112. dev_dbg(priv->dev, "%s: split codec slave exists\n",
  1113. __func__);
  1114. }
  1115. strlcpy(plat_dev_name, node->name,
  1116. (LPASS_CDC_STRING_LEN - 1));
  1117. pdev = platform_device_alloc(plat_dev_name, -1);
  1118. if (!pdev) {
  1119. dev_err(priv->dev, "%s: pdev memory alloc failed\n",
  1120. __func__);
  1121. ret = -ENOMEM;
  1122. goto err;
  1123. }
  1124. pdev->dev.parent = priv->dev;
  1125. pdev->dev.of_node = node;
  1126. priv->dev->platform_data = platdata;
  1127. if (split_codec)
  1128. priv->wcd_dev = &pdev->dev;
  1129. ret = platform_device_add(pdev);
  1130. if (ret) {
  1131. dev_err(&pdev->dev,
  1132. "%s: Cannot add platform device\n",
  1133. __func__);
  1134. platform_device_put(pdev);
  1135. goto fail_pdev_add;
  1136. }
  1137. if (priv->child_count < LPASS_CDC_CHILD_DEVICES_MAX)
  1138. priv->pdev_child_devices[priv->child_count++] = pdev;
  1139. else
  1140. goto err;
  1141. }
  1142. return;
  1143. fail_pdev_add:
  1144. for (count = 0; count < priv->child_count; count++)
  1145. platform_device_put(priv->pdev_child_devices[count]);
  1146. err:
  1147. return;
  1148. }
  1149. static int lpass_cdc_probe(struct platform_device *pdev)
  1150. {
  1151. struct lpass_cdc_priv *priv;
  1152. u32 num_macros = 0;
  1153. int ret;
  1154. struct clk *lpass_core_hw_vote = NULL;
  1155. struct clk *lpass_audio_hw_vote = NULL;
  1156. priv = devm_kzalloc(&pdev->dev, sizeof(struct lpass_cdc_priv),
  1157. GFP_KERNEL);
  1158. if (!priv)
  1159. return -ENOMEM;
  1160. ret = of_property_read_u32(pdev->dev.of_node, "qcom,num-macros",
  1161. &num_macros);
  1162. if (ret) {
  1163. dev_err(&pdev->dev,
  1164. "%s:num-macros property not found\n",
  1165. __func__);
  1166. return ret;
  1167. }
  1168. priv->num_macros = num_macros;
  1169. if (priv->num_macros > MAX_MACRO) {
  1170. dev_err(&pdev->dev,
  1171. "%s:num_macros(%d) > MAX_MACRO(%d) than supported\n",
  1172. __func__, priv->num_macros, MAX_MACRO);
  1173. return -EINVAL;
  1174. }
  1175. ret = of_property_read_u32(pdev->dev.of_node,
  1176. "qcom,lpass-cdc-version", &priv->version);
  1177. if (ret) {
  1178. dev_dbg(&pdev->dev, "%s:lpass_cdc version not specified\n",
  1179. __func__);
  1180. ret = 0;
  1181. }
  1182. BLOCKING_INIT_NOTIFIER_HEAD(&priv->notifier);
  1183. priv->dev = &pdev->dev;
  1184. priv->dev_up = true;
  1185. priv->pre_dev_up = true;
  1186. priv->initial_boot = true;
  1187. priv->regmap = lpass_cdc_regmap_init(priv->dev,
  1188. &lpass_cdc_regmap_config);
  1189. if (IS_ERR_OR_NULL((void *)(priv->regmap))) {
  1190. dev_err(&pdev->dev, "%s:regmap init failed\n", __func__);
  1191. return -EINVAL;
  1192. }
  1193. devm_regmap_qti_debugfs_register(priv->dev, priv->regmap);
  1194. priv->read_dev = __lpass_cdc_reg_read;
  1195. priv->write_dev = __lpass_cdc_reg_write;
  1196. priv->plat_data.handle = (void *) priv;
  1197. priv->plat_data.update_wcd_event = lpass_cdc_update_wcd_event;
  1198. priv->plat_data.register_notifier = lpass_cdc_register_notifier;
  1199. priv->core_hw_vote_count = 0;
  1200. priv->core_audio_vote_count = 0;
  1201. dev_set_drvdata(&pdev->dev, priv);
  1202. mutex_init(&priv->macro_lock);
  1203. mutex_init(&priv->io_lock);
  1204. mutex_init(&priv->clk_lock);
  1205. mutex_init(&priv->vote_lock);
  1206. INIT_WORK(&priv->lpass_cdc_add_child_devices_work,
  1207. lpass_cdc_add_child_devices);
  1208. /* Register LPASS core hw vote */
  1209. lpass_core_hw_vote = devm_clk_get(&pdev->dev, "lpass_core_hw_vote");
  1210. if (IS_ERR(lpass_core_hw_vote)) {
  1211. ret = PTR_ERR(lpass_core_hw_vote);
  1212. dev_dbg(&pdev->dev, "%s: clk get %s failed %d\n",
  1213. __func__, "lpass_core_hw_vote", ret);
  1214. lpass_core_hw_vote = NULL;
  1215. ret = 0;
  1216. }
  1217. priv->lpass_core_hw_vote = lpass_core_hw_vote;
  1218. /* Register LPASS audio hw vote */
  1219. lpass_audio_hw_vote = devm_clk_get(&pdev->dev, "lpass_audio_hw_vote");
  1220. if (IS_ERR(lpass_audio_hw_vote)) {
  1221. ret = PTR_ERR(lpass_audio_hw_vote);
  1222. dev_dbg(&pdev->dev, "%s: clk get %s failed %d\n",
  1223. __func__, "lpass_audio_hw_vote", ret);
  1224. lpass_audio_hw_vote = NULL;
  1225. ret = 0;
  1226. }
  1227. priv->lpass_audio_hw_vote = lpass_audio_hw_vote;
  1228. schedule_work(&priv->lpass_cdc_add_child_devices_work);
  1229. return 0;
  1230. }
  1231. static int lpass_cdc_remove(struct platform_device *pdev)
  1232. {
  1233. struct lpass_cdc_priv *priv = dev_get_drvdata(&pdev->dev);
  1234. if (!priv)
  1235. return -EINVAL;
  1236. of_platform_depopulate(&pdev->dev);
  1237. mutex_destroy(&priv->macro_lock);
  1238. mutex_destroy(&priv->io_lock);
  1239. mutex_destroy(&priv->clk_lock);
  1240. mutex_destroy(&priv->vote_lock);
  1241. return 0;
  1242. }
  1243. #ifdef CONFIG_PM
  1244. int lpass_cdc_runtime_resume(struct device *dev)
  1245. {
  1246. struct lpass_cdc_priv *priv = dev_get_drvdata(dev->parent);
  1247. int ret = 0;
  1248. dev_dbg(dev,"%s, enter\n", __func__);
  1249. mutex_lock(&priv->vote_lock);
  1250. if (priv->lpass_core_hw_vote == NULL) {
  1251. dev_dbg(dev, "%s: Invalid lpass core hw node\n", __func__);
  1252. goto audio_vote;
  1253. }
  1254. if (priv->core_hw_vote_count == 0) {
  1255. ret = digital_cdc_rsc_mgr_hw_vote_enable(priv->lpass_core_hw_vote, dev);
  1256. if (ret < 0) {
  1257. dev_err_ratelimited(dev, "%s:lpass core hw enable failed\n",
  1258. __func__);
  1259. goto audio_vote;
  1260. }
  1261. }
  1262. priv->core_hw_vote_count++;
  1263. audio_vote:
  1264. if (priv->lpass_audio_hw_vote == NULL) {
  1265. dev_dbg(dev, "%s: Invalid lpass audio hw node\n", __func__);
  1266. goto done;
  1267. }
  1268. if (priv->core_audio_vote_count == 0) {
  1269. ret = digital_cdc_rsc_mgr_hw_vote_enable(priv->lpass_audio_hw_vote, dev);
  1270. if (ret < 0) {
  1271. dev_err_ratelimited(dev, "%s:lpass audio hw enable failed\n",
  1272. __func__);
  1273. goto core_clk_vote;
  1274. }
  1275. }
  1276. priv->core_audio_vote_count++;
  1277. core_clk_vote:
  1278. if (priv->core_clk_vote_count == 0) {
  1279. ret = lpass_cdc_clk_rsc_request_clock(dev, TX_CORE_CLK,
  1280. TX_CORE_CLK, true);
  1281. if (ret < 0) {
  1282. dev_err_ratelimited(dev, "%s:lpass Tx core clk enable failed\n",
  1283. __func__);
  1284. goto done;
  1285. }
  1286. }
  1287. priv->core_clk_vote_count++;
  1288. done:
  1289. mutex_unlock(&priv->vote_lock);
  1290. dev_dbg(dev, "%s, leave, hw_vote %d, audio_vote %d, core_clk_vote %d\n",
  1291. __func__, priv->core_hw_vote_count,
  1292. priv->core_audio_vote_count, priv->core_clk_vote_count);
  1293. pm_runtime_set_autosuspend_delay(priv->dev, LPASS_CDC_AUTO_SUSPEND_DELAY);
  1294. return 0;
  1295. }
  1296. EXPORT_SYMBOL(lpass_cdc_runtime_resume);
  1297. int lpass_cdc_runtime_suspend(struct device *dev)
  1298. {
  1299. struct lpass_cdc_priv *priv = dev_get_drvdata(dev->parent);
  1300. dev_dbg(dev,"%s, enter\n", __func__);
  1301. mutex_lock(&priv->vote_lock);
  1302. if (priv->lpass_core_hw_vote != NULL) {
  1303. if (--priv->core_hw_vote_count == 0)
  1304. digital_cdc_rsc_mgr_hw_vote_disable(
  1305. priv->lpass_core_hw_vote, dev);
  1306. if (priv->core_hw_vote_count < 0)
  1307. priv->core_hw_vote_count = 0;
  1308. } else {
  1309. dev_dbg(dev, "%s: Invalid lpass core hw node\n",
  1310. __func__);
  1311. }
  1312. if (priv->lpass_audio_hw_vote != NULL) {
  1313. if (--priv->core_audio_vote_count == 0)
  1314. digital_cdc_rsc_mgr_hw_vote_disable(
  1315. priv->lpass_audio_hw_vote, dev);
  1316. if (priv->core_audio_vote_count < 0)
  1317. priv->core_audio_vote_count = 0;
  1318. } else {
  1319. dev_dbg(dev, "%s: Invalid lpass audio hw node\n",
  1320. __func__);
  1321. }
  1322. if (--priv->core_clk_vote_count == 0) {
  1323. lpass_cdc_clk_rsc_request_clock(dev, TX_CORE_CLK,
  1324. TX_CORE_CLK, false);
  1325. }
  1326. if (priv->core_clk_vote_count < 0)
  1327. priv->core_clk_vote_count = 0;
  1328. mutex_unlock(&priv->vote_lock);
  1329. dev_dbg(dev, "%s, leave, hw_vote %d, audio_vote %d, core_clk_vote %d\n",
  1330. __func__, priv->core_hw_vote_count,
  1331. priv->core_audio_vote_count, priv->core_clk_vote_count);
  1332. return 0;
  1333. }
  1334. EXPORT_SYMBOL(lpass_cdc_runtime_suspend);
  1335. #endif /* CONFIG_PM */
  1336. bool lpass_cdc_check_core_votes(struct device *dev)
  1337. {
  1338. struct lpass_cdc_priv *priv = dev_get_drvdata(dev->parent);
  1339. bool ret = true;
  1340. mutex_lock(&priv->vote_lock);
  1341. if (!priv->pre_dev_up ||
  1342. (priv->lpass_core_hw_vote && !priv->core_hw_vote_count) ||
  1343. (priv->lpass_audio_hw_vote && !priv->core_audio_vote_count))
  1344. ret = false;
  1345. mutex_unlock(&priv->vote_lock);
  1346. return ret;
  1347. }
  1348. EXPORT_SYMBOL(lpass_cdc_check_core_votes);
  1349. static const struct of_device_id lpass_cdc_dt_match[] = {
  1350. {.compatible = "qcom,lpass-cdc"},
  1351. {}
  1352. };
  1353. MODULE_DEVICE_TABLE(of, lpass_cdc_dt_match);
  1354. static struct platform_driver lpass_cdc_drv = {
  1355. .driver = {
  1356. .name = "lpass-cdc",
  1357. .owner = THIS_MODULE,
  1358. .of_match_table = lpass_cdc_dt_match,
  1359. .suppress_bind_attrs = true,
  1360. },
  1361. .probe = lpass_cdc_probe,
  1362. .remove = lpass_cdc_remove,
  1363. };
  1364. static int lpass_cdc_drv_init(void)
  1365. {
  1366. return platform_driver_register(&lpass_cdc_drv);
  1367. }
  1368. static void lpass_cdc_drv_exit(void)
  1369. {
  1370. platform_driver_unregister(&lpass_cdc_drv);
  1371. }
  1372. static int __init lpass_cdc_init(void)
  1373. {
  1374. lpass_cdc_drv_init();
  1375. lpass_cdc_clk_rsc_mgr_init();
  1376. return 0;
  1377. }
  1378. module_init(lpass_cdc_init);
  1379. static void __exit lpass_cdc_exit(void)
  1380. {
  1381. lpass_cdc_clk_rsc_mgr_exit();
  1382. lpass_cdc_drv_exit();
  1383. }
  1384. module_exit(lpass_cdc_exit);
  1385. MODULE_DESCRIPTION("LPASS Codec driver");
  1386. MODULE_LICENSE("GPL v2");