wcd937x.c 77 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <linux/regmap.h>
  13. #include <linux/pm_runtime.h>
  14. #include <sound/soc.h>
  15. #include <sound/tlv.h>
  16. #include <soc/soundwire.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include "internal.h"
  20. #include "wcd937x.h"
  21. #include <asoc/wcdcal-hwdep.h>
  22. #include "wcd937x-registers.h"
  23. #include <asoc/msm-cdc-pinctrl.h>
  24. #include <dt-bindings/sound/audio-codec-port-types.h>
  25. #include <asoc/msm-cdc-supply.h>
  26. #define DRV_NAME "wcd937x_codec"
  27. #define WCD9370_VARIANT 0
  28. #define WCD9375_VARIANT 5
  29. #define NUM_SWRS_DT_PARAMS 5
  30. #define WCD937X_VERSION_1_0 1
  31. #define WCD937X_VERSION_ENTRY_SIZE 32
  32. #define EAR_RX_PATH_AUX 1
  33. enum {
  34. CODEC_TX = 0,
  35. CODEC_RX,
  36. };
  37. enum {
  38. ALLOW_BUCK_DISABLE,
  39. HPH_COMP_DELAY,
  40. HPH_PA_DELAY,
  41. };
  42. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  43. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  44. static int wcd937x_handle_post_irq(void *data);
  45. static int wcd937x_reset(struct device *dev);
  46. static int wcd937x_reset_low(struct device *dev);
  47. static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = {
  48. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  49. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  50. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  51. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  52. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, 0x10),
  53. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, 0x20),
  54. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, 0x40),
  55. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, 0x80),
  56. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, 0x01),
  57. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, 0x02),
  58. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, 0x04),
  59. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, 0x08),
  60. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, 0x10),
  61. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  62. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  63. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  64. REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, 0x01),
  65. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  66. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  67. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  68. };
  69. static struct regmap_irq_chip wcd937x_regmap_irq_chip = {
  70. .name = "wcd937x",
  71. .irqs = wcd937x_irqs,
  72. .num_irqs = ARRAY_SIZE(wcd937x_irqs),
  73. .num_regs = 3,
  74. .status_base = WCD937X_DIGITAL_INTR_STATUS_0,
  75. .mask_base = WCD937X_DIGITAL_INTR_MASK_0,
  76. .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0,
  77. .use_ack = 1,
  78. .type_base = WCD937X_DIGITAL_INTR_LEVEL_0,
  79. .runtime_pm = false,
  80. .handle_post_irq = wcd937x_handle_post_irq,
  81. .irq_drv_data = NULL,
  82. };
  83. static int wcd937x_handle_post_irq(void *data)
  84. {
  85. struct wcd937x_priv *wcd937x = data;
  86. u32 status1 = 0, status2 = 0, status3 = 0;
  87. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_0, &status1);
  88. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_1, &status2);
  89. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_2, &status3);
  90. wcd937x->tx_swr_dev->slave_irq_pending =
  91. ((status1 || status2 || status3) ? true : false);
  92. return IRQ_HANDLED;
  93. }
  94. static int wcd937x_init_reg(struct snd_soc_component *component)
  95. {
  96. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  97. 0x0E, 0x0E);
  98. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  99. 0x80, 0x80);
  100. usleep_range(1000, 1010);
  101. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  102. 0x40, 0x40);
  103. usleep_range(1000, 1010);
  104. snd_soc_component_update_bits(component, WCD937X_LDORXTX_CONFIG,
  105. 0x10, 0x00);
  106. snd_soc_component_update_bits(component, WCD937X_BIAS_VBG_FINE_ADJ,
  107. 0xF0, 0x80);
  108. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  109. 0x80, 0x80);
  110. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  111. 0x40, 0x40);
  112. usleep_range(10000, 10010);
  113. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  114. 0x40, 0x00);
  115. snd_soc_component_update_bits(component, WCD937X_HPH_OCP_CTL,
  116. 0xFF, 0x3A);
  117. snd_soc_component_update_bits(component, WCD937X_RX_OCP_CTL,
  118. 0x0F, 0x02);
  119. snd_soc_component_update_bits(component, WCD937X_HPH_R_TEST,
  120. 0x01, 0x01);
  121. snd_soc_component_update_bits(component, WCD937X_HPH_L_TEST,
  122. 0x01, 0x01);
  123. return 0;
  124. }
  125. static int wcd937x_set_port_params(struct snd_soc_component *component,
  126. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  127. u8 *ch_mask, u32 *ch_rate,
  128. u8 *port_type, u8 path)
  129. {
  130. int i, j;
  131. u8 num_ports = 0;
  132. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  133. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  134. switch (path) {
  135. case CODEC_RX:
  136. map = &wcd937x->rx_port_mapping;
  137. num_ports = wcd937x->num_rx_ports;
  138. break;
  139. case CODEC_TX:
  140. map = &wcd937x->tx_port_mapping;
  141. num_ports = wcd937x->num_tx_ports;
  142. break;
  143. }
  144. for (i = 0; i <= num_ports; i++) {
  145. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  146. if ((*map)[i][j].slave_port_type == slv_prt_type)
  147. goto found;
  148. }
  149. }
  150. found:
  151. if (i > num_ports || j == MAX_CH_PER_PORT) {
  152. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  153. __func__, slv_prt_type);
  154. return -EINVAL;
  155. }
  156. *port_id = i;
  157. *num_ch = (*map)[i][j].num_ch;
  158. *ch_mask = (*map)[i][j].ch_mask;
  159. *ch_rate = (*map)[i][j].ch_rate;
  160. *port_type = (*map)[i][j].master_port_type;
  161. return 0;
  162. }
  163. static int wcd937x_parse_port_mapping(struct device *dev,
  164. char *prop, u8 path)
  165. {
  166. u32 *dt_array, map_size, map_length;
  167. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  168. u32 slave_port_type, master_port_type;
  169. u32 i, ch_iter = 0;
  170. int ret = 0;
  171. u8 *num_ports = NULL;
  172. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  173. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  174. switch (path) {
  175. case CODEC_RX:
  176. map = &wcd937x->rx_port_mapping;
  177. num_ports = &wcd937x->num_rx_ports;
  178. break;
  179. case CODEC_TX:
  180. map = &wcd937x->tx_port_mapping;
  181. num_ports = &wcd937x->num_tx_ports;
  182. break;
  183. }
  184. if (!of_find_property(dev->of_node, prop,
  185. &map_size)) {
  186. dev_err(dev, "missing port mapping prop %s\n", prop);
  187. ret = -EINVAL;
  188. goto err;
  189. }
  190. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  191. dt_array = kzalloc(map_size, GFP_KERNEL);
  192. if (!dt_array) {
  193. ret = -ENOMEM;
  194. goto err;
  195. }
  196. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  197. NUM_SWRS_DT_PARAMS * map_length);
  198. if (ret) {
  199. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  200. __func__, prop);
  201. ret = -EINVAL;
  202. goto err_pdata_fail;
  203. }
  204. for (i = 0; i < map_length; i++) {
  205. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  206. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  207. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  208. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  209. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  210. if (port_num != old_port_num)
  211. ch_iter = 0;
  212. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  213. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  214. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  215. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  216. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  217. old_port_num = port_num;
  218. }
  219. *num_ports = port_num;
  220. kfree(dt_array);
  221. return 0;
  222. err_pdata_fail:
  223. kfree(dt_array);
  224. err:
  225. return ret;
  226. }
  227. static int wcd937x_tx_connect_port(struct snd_soc_component *component,
  228. u8 slv_port_type, u8 enable)
  229. {
  230. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  231. u8 port_id;
  232. u8 num_ch;
  233. u8 ch_mask;
  234. u32 ch_rate;
  235. u8 port_type;
  236. u8 num_port = 1;
  237. int ret = 0;
  238. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  239. &num_ch, &ch_mask, &ch_rate,
  240. &port_type, CODEC_TX);
  241. if (ret)
  242. return ret;
  243. if (enable)
  244. ret = swr_connect_port(wcd937x->tx_swr_dev, &port_id,
  245. num_port, &ch_mask, &ch_rate,
  246. &num_ch, &port_type);
  247. else
  248. ret = swr_disconnect_port(wcd937x->tx_swr_dev, &port_id,
  249. num_port, &ch_mask, &port_type);
  250. return ret;
  251. }
  252. static int wcd937x_rx_connect_port(struct snd_soc_component *component,
  253. u8 slv_port_type, u8 enable)
  254. {
  255. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  256. u8 port_id;
  257. u8 num_ch;
  258. u8 ch_mask;
  259. u32 ch_rate;
  260. u8 port_type;
  261. u8 num_port = 1;
  262. int ret = 0;
  263. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  264. &num_ch, &ch_mask, &ch_rate,
  265. &port_type, CODEC_RX);
  266. if (ret)
  267. return ret;
  268. if (enable)
  269. ret = swr_connect_port(wcd937x->rx_swr_dev, &port_id,
  270. num_port, &ch_mask, &ch_rate,
  271. &num_ch, &port_type);
  272. else
  273. ret = swr_disconnect_port(wcd937x->rx_swr_dev, &port_id,
  274. num_port, &ch_mask, &port_type);
  275. return ret;
  276. }
  277. static int wcd937x_rx_clk_enable(struct snd_soc_component *component)
  278. {
  279. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  280. if (wcd937x->rx_clk_cnt == 0) {
  281. snd_soc_component_update_bits(component,
  282. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x08, 0x08);
  283. snd_soc_component_update_bits(component,
  284. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  285. snd_soc_component_update_bits(component,
  286. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x01);
  287. snd_soc_component_update_bits(component,
  288. WCD937X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  289. snd_soc_component_update_bits(component,
  290. WCD937X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  291. snd_soc_component_update_bits(component,
  292. WCD937X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  293. snd_soc_component_update_bits(component,
  294. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  295. }
  296. wcd937x->rx_clk_cnt++;
  297. return 0;
  298. }
  299. static int wcd937x_rx_clk_disable(struct snd_soc_component *component)
  300. {
  301. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  302. if (wcd937x->rx_clk_cnt == 0) {
  303. dev_dbg(wcd937x->dev, "%s:clk already disabled\n", __func__);
  304. return 0;
  305. }
  306. wcd937x->rx_clk_cnt--;
  307. if (wcd937x->rx_clk_cnt == 0) {
  308. snd_soc_component_update_bits(component,
  309. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x00);
  310. snd_soc_component_update_bits(component,
  311. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  312. 0x02, 0x00);
  313. snd_soc_component_update_bits(component,
  314. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  315. 0x01, 0x00);
  316. }
  317. return 0;
  318. }
  319. /*
  320. * wcd937x_soc_get_mbhc: get wcd937x_mbhc handle of corresponding component
  321. * @component: handle to snd_soc_component *
  322. *
  323. * return wcd937x_mbhc handle or error code in case of failure
  324. */
  325. struct wcd937x_mbhc *wcd937x_soc_get_mbhc(struct snd_soc_component *component)
  326. {
  327. struct wcd937x_priv *wcd937x;
  328. if (!component) {
  329. pr_err("%s: Invalid params, NULL component\n", __func__);
  330. return NULL;
  331. }
  332. wcd937x = snd_soc_component_get_drvdata(component);
  333. if (!wcd937x) {
  334. pr_err("%s: Invalid params, NULL tavil\n", __func__);
  335. return NULL;
  336. }
  337. return wcd937x->mbhc;
  338. }
  339. EXPORT_SYMBOL(wcd937x_soc_get_mbhc);
  340. static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  341. struct snd_kcontrol *kcontrol,
  342. int event)
  343. {
  344. struct snd_soc_component *component =
  345. snd_soc_dapm_to_component(w->dapm);
  346. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  347. int hph_mode = wcd937x->hph_mode;
  348. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  349. w->name, event);
  350. switch (event) {
  351. case SND_SOC_DAPM_PRE_PMU:
  352. wcd937x_rx_clk_enable(component);
  353. snd_soc_component_update_bits(component,
  354. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  355. 0x01, 0x01);
  356. snd_soc_component_update_bits(component,
  357. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  358. 0x04, 0x04);
  359. snd_soc_component_update_bits(component,
  360. WCD937X_HPH_RDAC_CLK_CTL1,
  361. 0x80, 0x00);
  362. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  363. break;
  364. case SND_SOC_DAPM_POST_PMU:
  365. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  366. snd_soc_component_update_bits(component,
  367. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  368. 0x0F, 0x02);
  369. else if (hph_mode == CLS_H_LOHIFI)
  370. snd_soc_component_update_bits(component,
  371. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  372. 0x0F, 0x06);
  373. if (wcd937x->comp1_enable) {
  374. snd_soc_component_update_bits(component,
  375. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  376. 0x02, 0x02);
  377. snd_soc_component_update_bits(component,
  378. WCD937X_HPH_L_EN, 0x20, 0x00);
  379. if (wcd937x->comp2_enable) {
  380. snd_soc_component_update_bits(component,
  381. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  382. 0x01, 0x01);
  383. snd_soc_component_update_bits(component,
  384. WCD937X_HPH_R_EN, 0x20, 0x00);
  385. }
  386. /*
  387. * 5ms sleep is required after COMP is enabled as per
  388. * HW requirement
  389. */
  390. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  391. usleep_range(5000, 5100);
  392. clear_bit(HPH_COMP_DELAY,
  393. &wcd937x->status_mask);
  394. }
  395. } else {
  396. snd_soc_component_update_bits(component,
  397. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  398. 0x02, 0x00);
  399. snd_soc_component_update_bits(component,
  400. WCD937X_HPH_L_EN, 0x20, 0x20);
  401. }
  402. snd_soc_component_update_bits(component,
  403. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  404. break;
  405. case SND_SOC_DAPM_POST_PMD:
  406. snd_soc_component_update_bits(component,
  407. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  408. 0x0F, 0x01);
  409. break;
  410. }
  411. return 0;
  412. }
  413. static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  414. struct snd_kcontrol *kcontrol,
  415. int event)
  416. {
  417. struct snd_soc_component *component =
  418. snd_soc_dapm_to_component(w->dapm);
  419. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  420. int hph_mode = wcd937x->hph_mode;
  421. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  422. w->name, event);
  423. switch (event) {
  424. case SND_SOC_DAPM_PRE_PMU:
  425. wcd937x_rx_clk_enable(component);
  426. snd_soc_component_update_bits(component,
  427. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  428. snd_soc_component_update_bits(component,
  429. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  430. snd_soc_component_update_bits(component,
  431. WCD937X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  432. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  433. break;
  434. case SND_SOC_DAPM_POST_PMU:
  435. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  436. snd_soc_component_update_bits(component,
  437. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  438. 0x0F, 0x02);
  439. else if (hph_mode == CLS_H_LOHIFI)
  440. snd_soc_component_update_bits(component,
  441. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  442. 0x0F, 0x06);
  443. if (wcd937x->comp2_enable) {
  444. snd_soc_component_update_bits(component,
  445. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  446. 0x01, 0x01);
  447. snd_soc_component_update_bits(component,
  448. WCD937X_HPH_R_EN, 0x20, 0x00);
  449. if (wcd937x->comp1_enable) {
  450. snd_soc_component_update_bits(component,
  451. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  452. 0x02, 0x02);
  453. snd_soc_component_update_bits(component,
  454. WCD937X_HPH_L_EN, 0x20, 0x00);
  455. }
  456. /*
  457. * 5ms sleep is required after COMP is enabled as per
  458. * HW requirement
  459. */
  460. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  461. usleep_range(5000, 5100);
  462. clear_bit(HPH_COMP_DELAY,
  463. &wcd937x->status_mask);
  464. }
  465. } else {
  466. snd_soc_component_update_bits(component,
  467. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  468. 0x01, 0x00);
  469. snd_soc_component_update_bits(component,
  470. WCD937X_HPH_R_EN, 0x20, 0x20);
  471. }
  472. snd_soc_component_update_bits(component,
  473. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  474. break;
  475. case SND_SOC_DAPM_POST_PMD:
  476. snd_soc_component_update_bits(component,
  477. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  478. 0x0F, 0x01);
  479. break;
  480. }
  481. return 0;
  482. }
  483. static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  484. struct snd_kcontrol *kcontrol,
  485. int event)
  486. {
  487. struct snd_soc_component *component =
  488. snd_soc_dapm_to_component(w->dapm);
  489. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  490. int hph_mode = wcd937x->hph_mode;
  491. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  492. w->name, event);
  493. switch (event) {
  494. case SND_SOC_DAPM_PRE_PMU:
  495. wcd937x_rx_clk_enable(component);
  496. snd_soc_component_update_bits(component,
  497. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  498. 0x04, 0x04);
  499. snd_soc_component_update_bits(component,
  500. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  501. 0x01, 0x01);
  502. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  503. snd_soc_component_update_bits(component,
  504. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  505. 0x0F, 0x02);
  506. else if (hph_mode == CLS_H_LOHIFI)
  507. snd_soc_component_update_bits(component,
  508. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  509. 0x0F, 0x06);
  510. snd_soc_component_update_bits(component,
  511. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  512. 0x02, 0x02);
  513. usleep_range(5000, 5010);
  514. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  515. WCD_CLSH_EVENT_PRE_DAC,
  516. WCD_CLSH_STATE_EAR,
  517. hph_mode);
  518. break;
  519. case SND_SOC_DAPM_POST_PMD:
  520. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI ||
  521. hph_mode == CLS_H_HIFI)
  522. snd_soc_component_update_bits(component,
  523. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  524. 0x0F, 0x01);
  525. break;
  526. };
  527. return 0;
  528. }
  529. static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  530. struct snd_kcontrol *kcontrol,
  531. int event)
  532. {
  533. struct snd_soc_component *component =
  534. snd_soc_dapm_to_component(w->dapm);
  535. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  536. int hph_mode = wcd937x->hph_mode;
  537. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  538. w->name, event);
  539. switch (event) {
  540. case SND_SOC_DAPM_PRE_PMU:
  541. wcd937x_rx_clk_enable(component);
  542. snd_soc_component_update_bits(component,
  543. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  544. 0x04, 0x04);
  545. snd_soc_component_update_bits(component,
  546. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  547. 0x04, 0x04);
  548. snd_soc_component_update_bits(component,
  549. WCD937X_DIGITAL_CDC_AUX_GAIN_CTL,
  550. 0x01, 0x01);
  551. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  552. WCD_CLSH_EVENT_PRE_DAC,
  553. WCD_CLSH_STATE_AUX,
  554. hph_mode);
  555. break;
  556. case SND_SOC_DAPM_POST_PMD:
  557. wcd937x_rx_clk_disable(component);
  558. snd_soc_component_update_bits(component,
  559. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  560. 0x04, 0x00);
  561. break;
  562. };
  563. return 0;
  564. }
  565. static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  566. struct snd_kcontrol *kcontrol,
  567. int event)
  568. {
  569. struct snd_soc_component *component =
  570. snd_soc_dapm_to_component(w->dapm);
  571. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  572. int ret = 0;
  573. int hph_mode = wcd937x->hph_mode;
  574. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  575. w->name, event);
  576. switch (event) {
  577. case SND_SOC_DAPM_PRE_PMU:
  578. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  579. wcd937x->rx_swr_dev->dev_num,
  580. true);
  581. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  582. WCD_CLSH_EVENT_PRE_DAC,
  583. WCD_CLSH_STATE_HPHR,
  584. hph_mode);
  585. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  586. 0x10, 0x10);
  587. usleep_range(100, 110);
  588. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  589. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  590. wcd937x->rx_swr_dev->dev_num,
  591. true);
  592. snd_soc_component_update_bits(component,
  593. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  594. break;
  595. case SND_SOC_DAPM_POST_PMU:
  596. /*
  597. * 7ms sleep is required after PA is enabled as per
  598. * HW requirement. If compander is disabled, then
  599. * 20ms delay is required.
  600. */
  601. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  602. if (!wcd937x->comp2_enable)
  603. usleep_range(20000, 20100);
  604. else
  605. usleep_range(7000, 7100);
  606. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  607. }
  608. snd_soc_component_update_bits(component,
  609. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  610. 0x02, 0x02);
  611. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  612. snd_soc_component_update_bits(component,
  613. WCD937X_ANA_RX_SUPPLIES,
  614. 0x02, 0x02);
  615. if (wcd937x->update_wcd_event)
  616. wcd937x->update_wcd_event(wcd937x->handle,
  617. WCD_BOLERO_EVT_RX_MUTE,
  618. (WCD_RX2 << 0x10));
  619. break;
  620. case SND_SOC_DAPM_PRE_PMD:
  621. if (wcd937x->update_wcd_event)
  622. wcd937x->update_wcd_event(wcd937x->handle,
  623. WCD_BOLERO_EVT_RX_MUTE,
  624. (WCD_RX2 << 0x10 | 0x1));
  625. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  626. WCD_EVENT_PRE_HPHR_PA_OFF,
  627. &wcd937x->mbhc->wcd_mbhc);
  628. break;
  629. case SND_SOC_DAPM_POST_PMD:
  630. usleep_range(7000, 7010);
  631. snd_soc_component_update_bits(component,
  632. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  633. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  634. WCD_EVENT_POST_HPHR_PA_OFF,
  635. &wcd937x->mbhc->wcd_mbhc);
  636. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  637. 0x10, 0x00);
  638. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  639. WCD_CLSH_EVENT_POST_PA,
  640. WCD_CLSH_STATE_HPHR,
  641. hph_mode);
  642. break;
  643. };
  644. return ret;
  645. }
  646. static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  647. struct snd_kcontrol *kcontrol,
  648. int event)
  649. {
  650. struct snd_soc_component *component =
  651. snd_soc_dapm_to_component(w->dapm);
  652. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  653. int ret = 0;
  654. int hph_mode = wcd937x->hph_mode;
  655. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  656. w->name, event);
  657. switch (event) {
  658. case SND_SOC_DAPM_PRE_PMU:
  659. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  660. wcd937x->rx_swr_dev->dev_num,
  661. true);
  662. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  663. WCD_CLSH_EVENT_PRE_DAC,
  664. WCD_CLSH_STATE_HPHL,
  665. hph_mode);
  666. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  667. 0x20, 0x20);
  668. usleep_range(100, 110);
  669. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  670. snd_soc_component_update_bits(component,
  671. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  672. break;
  673. case SND_SOC_DAPM_POST_PMU:
  674. /*
  675. * 7ms sleep is required after PA is enabled as per
  676. * HW requirement. If compander is disabled, then
  677. * 20ms delay is required.
  678. */
  679. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  680. if (!wcd937x->comp1_enable)
  681. usleep_range(20000, 20100);
  682. else
  683. usleep_range(7000, 7100);
  684. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  685. }
  686. snd_soc_component_update_bits(component,
  687. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  688. 0x02, 0x02);
  689. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  690. snd_soc_component_update_bits(component,
  691. WCD937X_ANA_RX_SUPPLIES,
  692. 0x02, 0x02);
  693. if (wcd937x->update_wcd_event)
  694. wcd937x->update_wcd_event(wcd937x->handle,
  695. WCD_BOLERO_EVT_RX_MUTE,
  696. (WCD_RX1 << 0x10));
  697. break;
  698. case SND_SOC_DAPM_PRE_PMD:
  699. if (wcd937x->update_wcd_event)
  700. wcd937x->update_wcd_event(wcd937x->handle,
  701. WCD_BOLERO_EVT_RX_MUTE,
  702. (WCD_RX1 << 0x10 | 0x1));
  703. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  704. WCD_EVENT_PRE_HPHL_PA_OFF,
  705. &wcd937x->mbhc->wcd_mbhc);
  706. break;
  707. case SND_SOC_DAPM_POST_PMD:
  708. usleep_range(7000, 7010);
  709. snd_soc_component_update_bits(component,
  710. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  711. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  712. WCD_EVENT_POST_HPHL_PA_OFF,
  713. &wcd937x->mbhc->wcd_mbhc);
  714. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  715. 0x20, 0x00);
  716. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  717. WCD_CLSH_EVENT_POST_PA,
  718. WCD_CLSH_STATE_HPHL,
  719. hph_mode);
  720. break;
  721. };
  722. return ret;
  723. }
  724. static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  725. struct snd_kcontrol *kcontrol,
  726. int event)
  727. {
  728. struct snd_soc_component *component =
  729. snd_soc_dapm_to_component(w->dapm);
  730. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  731. int hph_mode = wcd937x->hph_mode;
  732. int ret = 0;
  733. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  734. w->name, event);
  735. switch (event) {
  736. case SND_SOC_DAPM_PRE_PMU:
  737. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  738. wcd937x->rx_swr_dev->dev_num,
  739. true);
  740. snd_soc_component_update_bits(component,
  741. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  742. break;
  743. case SND_SOC_DAPM_POST_PMU:
  744. usleep_range(1000, 1010);
  745. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  746. snd_soc_component_update_bits(component,
  747. WCD937X_ANA_RX_SUPPLIES,
  748. 0x02, 0x02);
  749. if (wcd937x->update_wcd_event)
  750. wcd937x->update_wcd_event(wcd937x->handle,
  751. WCD_BOLERO_EVT_RX_MUTE,
  752. (WCD_RX3 << 0x10));
  753. break;
  754. case SND_SOC_DAPM_PRE_PMD:
  755. if (wcd937x->update_wcd_event)
  756. wcd937x->update_wcd_event(wcd937x->handle,
  757. WCD_BOLERO_EVT_RX_MUTE,
  758. (WCD_RX3 << 0x10 | 0x1));
  759. break;
  760. case SND_SOC_DAPM_POST_PMD:
  761. /* Add delay as per hw requirement */
  762. usleep_range(2000, 2010);
  763. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  764. WCD_CLSH_EVENT_POST_PA,
  765. WCD_CLSH_STATE_AUX,
  766. hph_mode);
  767. snd_soc_component_update_bits(component,
  768. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  769. break;
  770. };
  771. return ret;
  772. }
  773. static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  774. struct snd_kcontrol *kcontrol,
  775. int event)
  776. {
  777. struct snd_soc_component *component =
  778. snd_soc_dapm_to_component(w->dapm);
  779. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  780. int hph_mode = wcd937x->hph_mode;
  781. int ret = 0;
  782. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  783. w->name, event);
  784. switch (event) {
  785. case SND_SOC_DAPM_PRE_PMU:
  786. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  787. wcd937x->rx_swr_dev->dev_num,
  788. true);
  789. /*
  790. * Enable watchdog interrupt for HPHL or AUX
  791. * depending on mux value
  792. */
  793. wcd937x->ear_rx_path =
  794. snd_soc_component_read32(
  795. component, WCD937X_DIGITAL_CDC_EAR_PATH_CTL);
  796. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  797. snd_soc_component_update_bits(component,
  798. WCD937X_DIGITAL_PDM_WD_CTL2,
  799. 0x05, 0x05);
  800. else
  801. snd_soc_component_update_bits(component,
  802. WCD937X_DIGITAL_PDM_WD_CTL0,
  803. 0x17, 0x13);
  804. break;
  805. case SND_SOC_DAPM_POST_PMU:
  806. usleep_range(6000, 6010);
  807. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  808. snd_soc_component_update_bits(component,
  809. WCD937X_ANA_RX_SUPPLIES,
  810. 0x02, 0x02);
  811. if (wcd937x->update_wcd_event)
  812. wcd937x->update_wcd_event(wcd937x->handle,
  813. WCD_BOLERO_EVT_RX_MUTE,
  814. (WCD_RX1 << 0x10));
  815. break;
  816. case SND_SOC_DAPM_PRE_PMD:
  817. if (wcd937x->update_wcd_event)
  818. wcd937x->update_wcd_event(wcd937x->handle,
  819. WCD_BOLERO_EVT_RX_MUTE,
  820. (WCD_RX1 << 0x10 | 0x1));
  821. break;
  822. case SND_SOC_DAPM_POST_PMD:
  823. usleep_range(7000, 7010);
  824. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  825. WCD_CLSH_EVENT_POST_PA,
  826. WCD_CLSH_STATE_EAR,
  827. hph_mode);
  828. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  829. snd_soc_component_update_bits(component,
  830. WCD937X_DIGITAL_PDM_WD_CTL2,
  831. 0x05, 0x00);
  832. else
  833. snd_soc_component_update_bits(component,
  834. WCD937X_DIGITAL_PDM_WD_CTL0,
  835. 0x17, 0x00);
  836. break;
  837. };
  838. return ret;
  839. }
  840. static int wcd937x_enable_clsh(struct snd_soc_dapm_widget *w,
  841. struct snd_kcontrol *kcontrol,
  842. int event)
  843. {
  844. struct snd_soc_component *component =
  845. snd_soc_dapm_to_component(w->dapm);
  846. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  847. int mode = wcd937x->hph_mode;
  848. int ret = 0;
  849. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  850. w->name, event);
  851. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  852. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  853. wcd937x_rx_connect_port(component, CLSH,
  854. SND_SOC_DAPM_EVENT_ON(event));
  855. }
  856. if (SND_SOC_DAPM_EVENT_OFF(event))
  857. ret = swr_slvdev_datapath_control(
  858. wcd937x->rx_swr_dev,
  859. wcd937x->rx_swr_dev->dev_num,
  860. false);
  861. return ret;
  862. }
  863. static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w,
  864. struct snd_kcontrol *kcontrol,
  865. int event)
  866. {
  867. struct snd_soc_component *component =
  868. snd_soc_dapm_to_component(w->dapm);
  869. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  870. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  871. w->name, event);
  872. switch (event) {
  873. case SND_SOC_DAPM_PRE_PMU:
  874. wcd937x_rx_connect_port(component, HPH_L, true);
  875. if (wcd937x->comp1_enable)
  876. wcd937x_rx_connect_port(component, COMP_L, true);
  877. break;
  878. case SND_SOC_DAPM_POST_PMD:
  879. wcd937x_rx_connect_port(component, HPH_L, false);
  880. if (wcd937x->comp1_enable)
  881. wcd937x_rx_connect_port(component, COMP_L, false);
  882. wcd937x_rx_clk_disable(component);
  883. snd_soc_component_update_bits(component,
  884. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  885. 0x01, 0x00);
  886. break;
  887. };
  888. return 0;
  889. }
  890. static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w,
  891. struct snd_kcontrol *kcontrol, int event)
  892. {
  893. struct snd_soc_component *component =
  894. snd_soc_dapm_to_component(w->dapm);
  895. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  896. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  897. w->name, event);
  898. switch (event) {
  899. case SND_SOC_DAPM_PRE_PMU:
  900. wcd937x_rx_connect_port(component, HPH_R, true);
  901. if (wcd937x->comp2_enable)
  902. wcd937x_rx_connect_port(component, COMP_R, true);
  903. break;
  904. case SND_SOC_DAPM_POST_PMD:
  905. wcd937x_rx_connect_port(component, HPH_R, false);
  906. if (wcd937x->comp2_enable)
  907. wcd937x_rx_connect_port(component, COMP_R, false);
  908. wcd937x_rx_clk_disable(component);
  909. snd_soc_component_update_bits(component,
  910. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  911. 0x02, 0x00);
  912. break;
  913. };
  914. return 0;
  915. }
  916. static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w,
  917. struct snd_kcontrol *kcontrol,
  918. int event)
  919. {
  920. struct snd_soc_component *component =
  921. snd_soc_dapm_to_component(w->dapm);
  922. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  923. w->name, event);
  924. switch (event) {
  925. case SND_SOC_DAPM_PRE_PMU:
  926. wcd937x_rx_connect_port(component, LO, true);
  927. break;
  928. case SND_SOC_DAPM_POST_PMD:
  929. wcd937x_rx_connect_port(component, LO, false);
  930. usleep_range(6000, 6010);
  931. wcd937x_rx_clk_disable(component);
  932. snd_soc_component_update_bits(component,
  933. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  934. break;
  935. }
  936. return 0;
  937. }
  938. static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  939. struct snd_kcontrol *kcontrol,
  940. int event)
  941. {
  942. struct snd_soc_component *component =
  943. snd_soc_dapm_to_component(w->dapm);
  944. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  945. u16 dmic_clk_reg;
  946. s32 *dmic_clk_cnt;
  947. unsigned int dmic;
  948. char *wname;
  949. int ret = 0;
  950. wname = strpbrk(w->name, "012345");
  951. if (!wname) {
  952. dev_err(component->dev, "%s: widget not found\n", __func__);
  953. return -EINVAL;
  954. }
  955. ret = kstrtouint(wname, 10, &dmic);
  956. if (ret < 0) {
  957. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  958. __func__);
  959. return -EINVAL;
  960. }
  961. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  962. w->name, event);
  963. switch (dmic) {
  964. case 0:
  965. case 1:
  966. dmic_clk_cnt = &(wcd937x->dmic_0_1_clk_cnt);
  967. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC0_CTL;
  968. break;
  969. case 2:
  970. case 3:
  971. dmic_clk_cnt = &(wcd937x->dmic_2_3_clk_cnt);
  972. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL;
  973. break;
  974. case 4:
  975. case 5:
  976. dmic_clk_cnt = &(wcd937x->dmic_4_5_clk_cnt);
  977. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL;
  978. break;
  979. default:
  980. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  981. __func__);
  982. return -EINVAL;
  983. };
  984. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  985. __func__, event, dmic, *dmic_clk_cnt);
  986. switch (event) {
  987. case SND_SOC_DAPM_PRE_PMU:
  988. snd_soc_component_update_bits(component,
  989. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  990. snd_soc_component_update_bits(component,
  991. dmic_clk_reg, 0x07, 0x02);
  992. snd_soc_component_update_bits(component,
  993. dmic_clk_reg, 0x08, 0x08);
  994. snd_soc_component_update_bits(component,
  995. dmic_clk_reg, 0x70, 0x20);
  996. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), true);
  997. break;
  998. case SND_SOC_DAPM_POST_PMD:
  999. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1000. break;
  1001. };
  1002. return 0;
  1003. }
  1004. /*
  1005. * wcd937x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1006. * @micb_mv: micbias in mv
  1007. *
  1008. * return register value converted
  1009. */
  1010. int wcd937x_get_micb_vout_ctl_val(u32 micb_mv)
  1011. {
  1012. /* min micbias voltage is 1V and maximum is 2.85V */
  1013. if (micb_mv < 1000 || micb_mv > 2850) {
  1014. pr_err("%s: unsupported micbias voltage\n", __func__);
  1015. return -EINVAL;
  1016. }
  1017. return (micb_mv - 1000) / 50;
  1018. }
  1019. EXPORT_SYMBOL(wcd937x_get_micb_vout_ctl_val);
  1020. /*
  1021. * wcd937x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1022. * @component: handle to snd_soc_component *
  1023. * @req_volt: micbias voltage to be set
  1024. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1025. *
  1026. * return 0 if adjustment is success or error code in case of failure
  1027. */
  1028. int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1029. int req_volt, int micb_num)
  1030. {
  1031. struct wcd937x_priv *wcd937x =
  1032. snd_soc_component_get_drvdata(component);
  1033. int cur_vout_ctl, req_vout_ctl;
  1034. int micb_reg, micb_val, micb_en;
  1035. int ret = 0;
  1036. switch (micb_num) {
  1037. case MIC_BIAS_1:
  1038. micb_reg = WCD937X_ANA_MICB1;
  1039. break;
  1040. case MIC_BIAS_2:
  1041. micb_reg = WCD937X_ANA_MICB2;
  1042. break;
  1043. case MIC_BIAS_3:
  1044. micb_reg = WCD937X_ANA_MICB3;
  1045. break;
  1046. default:
  1047. return -EINVAL;
  1048. }
  1049. mutex_lock(&wcd937x->micb_lock);
  1050. /*
  1051. * If requested micbias voltage is same as current micbias
  1052. * voltage, then just return. Otherwise, adjust voltage as
  1053. * per requested value. If micbias is already enabled, then
  1054. * to avoid slow micbias ramp-up or down enable pull-up
  1055. * momentarily, change the micbias value and then re-enable
  1056. * micbias.
  1057. */
  1058. micb_val = snd_soc_component_read32(component, micb_reg);
  1059. micb_en = (micb_val & 0xC0) >> 6;
  1060. cur_vout_ctl = micb_val & 0x3F;
  1061. req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt);
  1062. if (req_vout_ctl < 0) {
  1063. ret = -EINVAL;
  1064. goto exit;
  1065. }
  1066. if (cur_vout_ctl == req_vout_ctl) {
  1067. ret = 0;
  1068. goto exit;
  1069. }
  1070. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1071. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1072. req_volt, micb_en);
  1073. if (micb_en == 0x1)
  1074. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1075. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1076. if (micb_en == 0x1) {
  1077. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1078. /*
  1079. * Add 2ms delay as per HW requirement after enabling
  1080. * micbias
  1081. */
  1082. usleep_range(2000, 2100);
  1083. }
  1084. exit:
  1085. mutex_unlock(&wcd937x->micb_lock);
  1086. return ret;
  1087. }
  1088. EXPORT_SYMBOL(wcd937x_mbhc_micb_adjust_voltage);
  1089. static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1090. struct snd_kcontrol *kcontrol,
  1091. int event)
  1092. {
  1093. struct snd_soc_component *component =
  1094. snd_soc_dapm_to_component(w->dapm);
  1095. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1096. int ret = 0;
  1097. switch (event) {
  1098. case SND_SOC_DAPM_PRE_PMU:
  1099. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1100. wcd937x->tx_swr_dev->dev_num,
  1101. true);
  1102. break;
  1103. case SND_SOC_DAPM_POST_PMD:
  1104. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1105. wcd937x->tx_swr_dev->dev_num,
  1106. false);
  1107. break;
  1108. };
  1109. return ret;
  1110. }
  1111. static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1112. struct snd_kcontrol *kcontrol,
  1113. int event){
  1114. struct snd_soc_component *component =
  1115. snd_soc_dapm_to_component(w->dapm);
  1116. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1117. w->name, event);
  1118. switch (event) {
  1119. case SND_SOC_DAPM_PRE_PMU:
  1120. snd_soc_component_update_bits(component,
  1121. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1122. snd_soc_component_update_bits(component,
  1123. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1124. snd_soc_component_update_bits(component,
  1125. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1126. wcd937x_tx_connect_port(component, ADC1 + (w->shift), true);
  1127. break;
  1128. case SND_SOC_DAPM_POST_PMD:
  1129. wcd937x_tx_connect_port(component, ADC1 + (w->shift), false);
  1130. snd_soc_component_update_bits(component,
  1131. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1132. break;
  1133. };
  1134. return 0;
  1135. }
  1136. static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
  1137. struct snd_kcontrol *kcontrol, int event)
  1138. {
  1139. struct snd_soc_component *component =
  1140. snd_soc_dapm_to_component(w->dapm);
  1141. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1142. w->name, event);
  1143. switch (event) {
  1144. case SND_SOC_DAPM_PRE_PMU:
  1145. snd_soc_component_update_bits(component,
  1146. WCD937X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1147. snd_soc_component_update_bits(component,
  1148. WCD937X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1149. snd_soc_component_update_bits(component,
  1150. WCD937X_ANA_TX_CH2, 0x40, 0x40);
  1151. snd_soc_component_update_bits(component,
  1152. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x30, 0x30);
  1153. snd_soc_component_update_bits(component,
  1154. WCD937X_ANA_TX_CH1, 0x80, 0x80);
  1155. snd_soc_component_update_bits(component,
  1156. WCD937X_ANA_TX_CH2, 0x40, 0x00);
  1157. snd_soc_component_update_bits(component,
  1158. WCD937X_ANA_TX_CH2, 0x80, 0x80);
  1159. break;
  1160. case SND_SOC_DAPM_POST_PMD:
  1161. snd_soc_component_update_bits(component,
  1162. WCD937X_ANA_TX_CH1, 0x80, 0x00);
  1163. snd_soc_component_update_bits(component,
  1164. WCD937X_ANA_TX_CH2, 0x80, 0x00);
  1165. snd_soc_component_update_bits(component,
  1166. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1167. snd_soc_component_update_bits(component,
  1168. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1169. snd_soc_component_update_bits(component,
  1170. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1171. break;
  1172. };
  1173. return 0;
  1174. }
  1175. int wcd937x_micbias_control(struct snd_soc_component *component,
  1176. int micb_num, int req, bool is_dapm)
  1177. {
  1178. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1179. int micb_index = micb_num - 1;
  1180. u16 micb_reg;
  1181. int pre_off_event = 0, post_off_event = 0;
  1182. int post_on_event = 0, post_dapm_off = 0;
  1183. int post_dapm_on = 0;
  1184. if ((micb_index < 0) || (micb_index > WCD937X_MAX_MICBIAS - 1)) {
  1185. dev_err(component->dev, "%s: Invalid micbias index, micb_ind:%d\n",
  1186. __func__, micb_index);
  1187. return -EINVAL;
  1188. }
  1189. switch (micb_num) {
  1190. case MIC_BIAS_1:
  1191. micb_reg = WCD937X_ANA_MICB1;
  1192. break;
  1193. case MIC_BIAS_2:
  1194. micb_reg = WCD937X_ANA_MICB2;
  1195. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1196. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1197. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1198. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1199. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1200. break;
  1201. case MIC_BIAS_3:
  1202. micb_reg = WCD937X_ANA_MICB3;
  1203. break;
  1204. default:
  1205. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1206. __func__, micb_num);
  1207. return -EINVAL;
  1208. };
  1209. mutex_lock(&wcd937x->micb_lock);
  1210. switch (req) {
  1211. case MICB_PULLUP_ENABLE:
  1212. wcd937x->pullup_ref[micb_index]++;
  1213. if ((wcd937x->pullup_ref[micb_index] == 1) &&
  1214. (wcd937x->micb_ref[micb_index] == 0))
  1215. snd_soc_component_update_bits(component, micb_reg,
  1216. 0xC0, 0x80);
  1217. break;
  1218. case MICB_PULLUP_DISABLE:
  1219. if (wcd937x->pullup_ref[micb_index] > 0)
  1220. wcd937x->pullup_ref[micb_index]--;
  1221. if ((wcd937x->pullup_ref[micb_index] == 0) &&
  1222. (wcd937x->micb_ref[micb_index] == 0))
  1223. snd_soc_component_update_bits(component, micb_reg,
  1224. 0xC0, 0x00);
  1225. break;
  1226. case MICB_ENABLE:
  1227. wcd937x->micb_ref[micb_index]++;
  1228. if (wcd937x->micb_ref[micb_index] == 1) {
  1229. snd_soc_component_update_bits(component,
  1230. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1231. snd_soc_component_update_bits(component,
  1232. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1233. snd_soc_component_update_bits(component,
  1234. WCD937X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1235. snd_soc_component_update_bits(component,
  1236. WCD937X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1237. snd_soc_component_update_bits(component,
  1238. WCD937X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1239. snd_soc_component_update_bits(component,
  1240. micb_reg, 0xC0, 0x40);
  1241. if (post_on_event)
  1242. blocking_notifier_call_chain(
  1243. &wcd937x->mbhc->notifier, post_on_event,
  1244. &wcd937x->mbhc->wcd_mbhc);
  1245. }
  1246. if (is_dapm && post_dapm_on && wcd937x->mbhc)
  1247. blocking_notifier_call_chain(
  1248. &wcd937x->mbhc->notifier, post_dapm_on,
  1249. &wcd937x->mbhc->wcd_mbhc);
  1250. break;
  1251. case MICB_DISABLE:
  1252. if (wcd937x->micb_ref[micb_index] > 0)
  1253. wcd937x->micb_ref[micb_index]--;
  1254. if ((wcd937x->micb_ref[micb_index] == 0) &&
  1255. (wcd937x->pullup_ref[micb_index] > 0))
  1256. snd_soc_component_update_bits(component, micb_reg,
  1257. 0xC0, 0x80);
  1258. else if ((wcd937x->micb_ref[micb_index] == 0) &&
  1259. (wcd937x->pullup_ref[micb_index] == 0)) {
  1260. if (pre_off_event && wcd937x->mbhc)
  1261. blocking_notifier_call_chain(
  1262. &wcd937x->mbhc->notifier, pre_off_event,
  1263. &wcd937x->mbhc->wcd_mbhc);
  1264. snd_soc_component_update_bits(component, micb_reg,
  1265. 0xC0, 0x00);
  1266. if (post_off_event && wcd937x->mbhc)
  1267. blocking_notifier_call_chain(
  1268. &wcd937x->mbhc->notifier,
  1269. post_off_event,
  1270. &wcd937x->mbhc->wcd_mbhc);
  1271. }
  1272. if (is_dapm && post_dapm_off && wcd937x->mbhc)
  1273. blocking_notifier_call_chain(
  1274. &wcd937x->mbhc->notifier, post_dapm_off,
  1275. &wcd937x->mbhc->wcd_mbhc);
  1276. break;
  1277. };
  1278. dev_dbg(component->dev, "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1279. __func__, micb_num, wcd937x->micb_ref[micb_index],
  1280. wcd937x->pullup_ref[micb_index]);
  1281. mutex_unlock(&wcd937x->micb_lock);
  1282. return 0;
  1283. }
  1284. EXPORT_SYMBOL(wcd937x_micbias_control);
  1285. static int wcd937x_get_logical_addr(struct swr_device *swr_dev)
  1286. {
  1287. int ret = 0;
  1288. uint8_t devnum = 0;
  1289. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1290. if (ret) {
  1291. dev_err(&swr_dev->dev,
  1292. "%s get devnum %d for dev addr %lx failed\n",
  1293. __func__, devnum, swr_dev->addr);
  1294. swr_remove_device(swr_dev);
  1295. return ret;
  1296. }
  1297. swr_dev->dev_num = devnum;
  1298. return 0;
  1299. }
  1300. static int wcd937x_event_notify(struct notifier_block *block,
  1301. unsigned long val,
  1302. void *data)
  1303. {
  1304. u16 event = (val & 0xffff);
  1305. u16 amic = (val >> 0x10);
  1306. u16 mask = 0x40, reg = 0x0;
  1307. int ret = 0;
  1308. struct wcd937x_priv *wcd937x = dev_get_drvdata((struct device *)data);
  1309. struct snd_soc_component *component = wcd937x->component;
  1310. struct wcd_mbhc *mbhc;
  1311. switch (event) {
  1312. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1313. if (amic == 0x1 || amic == 0x2)
  1314. reg = WCD937X_ANA_TX_CH2;
  1315. else if (amic == 0x3)
  1316. reg = WCD937X_ANA_TX_CH3_HPF;
  1317. else
  1318. return 0;
  1319. if (amic == 0x2)
  1320. mask = 0x20;
  1321. snd_soc_component_update_bits(component, reg, mask, 0x00);
  1322. break;
  1323. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1324. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  1325. 0xC0, 0x00);
  1326. snd_soc_component_update_bits(component, WCD937X_ANA_EAR,
  1327. 0x80, 0x00);
  1328. snd_soc_component_update_bits(component, WCD937X_AUX_AUXPA,
  1329. 0x80, 0x00);
  1330. break;
  1331. case BOLERO_WCD_EVT_SSR_DOWN:
  1332. wcd937x_reset_low(wcd937x->dev);
  1333. break;
  1334. case BOLERO_WCD_EVT_SSR_UP:
  1335. wcd937x_reset(wcd937x->dev);
  1336. wcd937x_get_logical_addr(wcd937x->tx_swr_dev);
  1337. wcd937x_get_logical_addr(wcd937x->rx_swr_dev);
  1338. regcache_mark_dirty(wcd937x->regmap);
  1339. regcache_sync(wcd937x->regmap);
  1340. /* Initialize MBHC module */
  1341. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1342. ret = wcd937x_mbhc_post_ssr_init(wcd937x->mbhc, component);
  1343. if (ret) {
  1344. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1345. __func__);
  1346. } else {
  1347. wcd937x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1348. }
  1349. break;
  1350. default:
  1351. dev_err(component->dev, "%s: invalid event %d\n", __func__,
  1352. event);
  1353. break;
  1354. }
  1355. return 0;
  1356. }
  1357. static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1358. int event)
  1359. {
  1360. struct snd_soc_component *component =
  1361. snd_soc_dapm_to_component(w->dapm);
  1362. int micb_num;
  1363. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1364. __func__, w->name, event);
  1365. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1366. micb_num = MIC_BIAS_1;
  1367. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1368. micb_num = MIC_BIAS_2;
  1369. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1370. micb_num = MIC_BIAS_3;
  1371. else
  1372. return -EINVAL;
  1373. switch (event) {
  1374. case SND_SOC_DAPM_PRE_PMU:
  1375. wcd937x_micbias_control(component, micb_num,
  1376. MICB_ENABLE, true);
  1377. break;
  1378. case SND_SOC_DAPM_POST_PMU:
  1379. usleep_range(1000, 1100);
  1380. break;
  1381. case SND_SOC_DAPM_POST_PMD:
  1382. wcd937x_micbias_control(component, micb_num,
  1383. MICB_DISABLE, true);
  1384. break;
  1385. };
  1386. return 0;
  1387. }
  1388. static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1389. struct snd_kcontrol *kcontrol,
  1390. int event)
  1391. {
  1392. return __wcd937x_codec_enable_micbias(w, event);
  1393. }
  1394. static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1395. struct snd_ctl_elem_value *ucontrol)
  1396. {
  1397. struct snd_soc_component *component =
  1398. snd_soc_kcontrol_component(kcontrol);
  1399. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1400. ucontrol->value.integer.value[0] = wcd937x->hph_mode;
  1401. return 0;
  1402. }
  1403. static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1404. struct snd_ctl_elem_value *ucontrol)
  1405. {
  1406. struct snd_soc_component *component =
  1407. snd_soc_kcontrol_component(kcontrol);
  1408. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1409. u32 mode_val;
  1410. mode_val = ucontrol->value.enumerated.item[0];
  1411. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1412. if (mode_val == 0) {
  1413. dev_warn(component->dev, "%s:Invalid HPH Mode, default to class_AB\n",
  1414. __func__);
  1415. mode_val = 3; /* enum will be updated later */
  1416. }
  1417. wcd937x->hph_mode = mode_val;
  1418. return 0;
  1419. }
  1420. static int wcd937x_get_compander(struct snd_kcontrol *kcontrol,
  1421. struct snd_ctl_elem_value *ucontrol)
  1422. {
  1423. struct snd_soc_component *component =
  1424. snd_soc_kcontrol_component(kcontrol);
  1425. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1426. bool hphr;
  1427. struct soc_multi_mixer_control *mc;
  1428. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1429. hphr = mc->shift;
  1430. ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable :
  1431. wcd937x->comp1_enable;
  1432. return 0;
  1433. }
  1434. static int wcd937x_set_compander(struct snd_kcontrol *kcontrol,
  1435. struct snd_ctl_elem_value *ucontrol)
  1436. {
  1437. struct snd_soc_component *component =
  1438. snd_soc_kcontrol_component(kcontrol);
  1439. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1440. int value = ucontrol->value.integer.value[0];
  1441. bool hphr;
  1442. struct soc_multi_mixer_control *mc;
  1443. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1444. hphr = mc->shift;
  1445. if (hphr)
  1446. wcd937x->comp2_enable = value;
  1447. else
  1448. wcd937x->comp1_enable = value;
  1449. return 0;
  1450. }
  1451. static int wcd937x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  1452. struct snd_kcontrol *kcontrol,
  1453. int event)
  1454. {
  1455. struct snd_soc_component *component =
  1456. snd_soc_dapm_to_component(w->dapm);
  1457. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1458. struct wcd937x_pdata *pdata = NULL;
  1459. int ret = 0;
  1460. pdata = dev_get_platdata(wcd937x->dev);
  1461. if (!pdata) {
  1462. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  1463. return -EINVAL;
  1464. }
  1465. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1466. w->name, event);
  1467. switch (event) {
  1468. case SND_SOC_DAPM_PRE_PMU:
  1469. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  1470. dev_dbg(component->dev,
  1471. "%s: buck already in enabled state\n",
  1472. __func__);
  1473. return 0;
  1474. }
  1475. ret = msm_cdc_enable_ondemand_supply(wcd937x->dev,
  1476. wcd937x->supplies,
  1477. pdata->regulator,
  1478. pdata->num_supplies,
  1479. "cdc-vdd-buck");
  1480. if (ret == -EINVAL) {
  1481. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  1482. __func__);
  1483. return ret;
  1484. }
  1485. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1486. /*
  1487. * 200us sleep is required after LDO15 is enabled as per
  1488. * HW requirement
  1489. */
  1490. usleep_range(200, 250);
  1491. break;
  1492. case SND_SOC_DAPM_POST_PMD:
  1493. set_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1494. break;
  1495. }
  1496. return 0;
  1497. }
  1498. static const char * const rx_hph_mode_mux_text[] = {
  1499. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1500. "CLS_H_ULP", "CLS_AB_HIFI",
  1501. };
  1502. static const struct soc_enum rx_hph_mode_mux_enum =
  1503. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1504. rx_hph_mode_mux_text);
  1505. static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
  1506. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1507. wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put),
  1508. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1509. wcd937x_get_compander, wcd937x_set_compander),
  1510. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1511. wcd937x_get_compander, wcd937x_set_compander),
  1512. SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain),
  1513. SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain),
  1514. SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0,
  1515. analog_gain),
  1516. SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0,
  1517. analog_gain),
  1518. SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0,
  1519. analog_gain),
  1520. };
  1521. static const struct snd_kcontrol_new adc1_switch[] = {
  1522. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1523. };
  1524. static const struct snd_kcontrol_new adc2_switch[] = {
  1525. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1526. };
  1527. static const struct snd_kcontrol_new adc3_switch[] = {
  1528. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1529. };
  1530. static const struct snd_kcontrol_new dmic1_switch[] = {
  1531. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1532. };
  1533. static const struct snd_kcontrol_new dmic2_switch[] = {
  1534. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1535. };
  1536. static const struct snd_kcontrol_new dmic3_switch[] = {
  1537. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1538. };
  1539. static const struct snd_kcontrol_new dmic4_switch[] = {
  1540. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1541. };
  1542. static const struct snd_kcontrol_new dmic5_switch[] = {
  1543. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1544. };
  1545. static const struct snd_kcontrol_new dmic6_switch[] = {
  1546. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1547. };
  1548. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  1549. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1550. };
  1551. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  1552. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1553. };
  1554. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  1555. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1556. };
  1557. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  1558. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1559. };
  1560. static const char * const adc2_mux_text[] = {
  1561. "INP2", "INP3"
  1562. };
  1563. static const char * const rdac3_mux_text[] = {
  1564. "RX1", "RX3"
  1565. };
  1566. static const struct soc_enum adc2_enum =
  1567. SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7,
  1568. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  1569. static const struct soc_enum rdac3_enum =
  1570. SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  1571. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  1572. static const struct snd_kcontrol_new tx_adc2_mux =
  1573. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  1574. static const struct snd_kcontrol_new rx_rdac3_mux =
  1575. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  1576. static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = {
  1577. /*input widgets*/
  1578. SND_SOC_DAPM_INPUT("AMIC1"),
  1579. SND_SOC_DAPM_INPUT("AMIC2"),
  1580. SND_SOC_DAPM_INPUT("AMIC3"),
  1581. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  1582. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  1583. SND_SOC_DAPM_INPUT("IN3_AUX"),
  1584. /*tx widgets*/
  1585. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  1586. wcd937x_codec_enable_adc,
  1587. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1588. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  1589. wcd937x_codec_enable_adc,
  1590. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1591. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  1592. NULL, 0, wcd937x_enable_req,
  1593. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1594. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
  1595. NULL, 0, wcd937x_enable_req,
  1596. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1597. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  1598. &tx_adc2_mux),
  1599. /*tx mixers*/
  1600. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  1601. adc1_switch, ARRAY_SIZE(adc1_switch),
  1602. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1603. SND_SOC_DAPM_POST_PMD),
  1604. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  1605. adc2_switch, ARRAY_SIZE(adc2_switch),
  1606. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1607. SND_SOC_DAPM_POST_PMD),
  1608. /* micbias widgets*/
  1609. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  1610. wcd937x_codec_enable_micbias,
  1611. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1612. SND_SOC_DAPM_POST_PMD),
  1613. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  1614. wcd937x_codec_enable_micbias,
  1615. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1616. SND_SOC_DAPM_POST_PMD),
  1617. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  1618. wcd937x_codec_enable_micbias,
  1619. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1620. SND_SOC_DAPM_POST_PMD),
  1621. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  1622. wcd937x_codec_enable_vdd_buck,
  1623. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1624. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  1625. wcd937x_enable_clsh,
  1626. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1627. /*rx widgets*/
  1628. SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0,
  1629. wcd937x_codec_enable_ear_pa,
  1630. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1631. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1632. SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0,
  1633. wcd937x_codec_enable_aux_pa,
  1634. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1635. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1636. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0,
  1637. wcd937x_codec_enable_hphl_pa,
  1638. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1639. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1640. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0,
  1641. wcd937x_codec_enable_hphr_pa,
  1642. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1643. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1644. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  1645. wcd937x_codec_hphl_dac_event,
  1646. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1647. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1648. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  1649. wcd937x_codec_hphr_dac_event,
  1650. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1651. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1652. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  1653. wcd937x_codec_ear_dac_event,
  1654. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1655. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1656. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  1657. wcd937x_codec_aux_dac_event,
  1658. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1659. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1660. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  1661. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  1662. wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  1663. SND_SOC_DAPM_POST_PMD),
  1664. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  1665. wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  1666. SND_SOC_DAPM_POST_PMD),
  1667. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  1668. wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  1669. SND_SOC_DAPM_POST_PMD),
  1670. /* rx mixer widgets*/
  1671. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  1672. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  1673. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  1674. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  1675. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  1676. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  1677. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  1678. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  1679. /*output widgets tx*/
  1680. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  1681. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  1682. /*output widgets rx*/
  1683. SND_SOC_DAPM_OUTPUT("EAR"),
  1684. SND_SOC_DAPM_OUTPUT("AUX"),
  1685. SND_SOC_DAPM_OUTPUT("HPHL"),
  1686. SND_SOC_DAPM_OUTPUT("HPHR"),
  1687. };
  1688. static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = {
  1689. /*input widgets*/
  1690. SND_SOC_DAPM_INPUT("AMIC4"),
  1691. /*tx widgets*/
  1692. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  1693. wcd937x_codec_enable_adc,
  1694. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1695. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
  1696. NULL, 0, wcd937x_enable_req,
  1697. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1698. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  1699. wcd937x_codec_enable_dmic,
  1700. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1701. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  1702. wcd937x_codec_enable_dmic,
  1703. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1704. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  1705. wcd937x_codec_enable_dmic,
  1706. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1707. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  1708. wcd937x_codec_enable_dmic,
  1709. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1710. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  1711. wcd937x_codec_enable_dmic,
  1712. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1713. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  1714. wcd937x_codec_enable_dmic,
  1715. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1716. /*tx mixer widgets*/
  1717. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  1718. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  1719. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1720. SND_SOC_DAPM_POST_PMD),
  1721. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  1722. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  1723. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1724. SND_SOC_DAPM_POST_PMD),
  1725. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  1726. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  1727. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1728. SND_SOC_DAPM_POST_PMD),
  1729. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  1730. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  1731. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1732. SND_SOC_DAPM_POST_PMD),
  1733. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  1734. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  1735. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1736. SND_SOC_DAPM_POST_PMD),
  1737. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  1738. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  1739. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1740. SND_SOC_DAPM_POST_PMD),
  1741. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  1742. ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl,
  1743. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1744. /*output widgets*/
  1745. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  1746. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  1747. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  1748. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  1749. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  1750. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  1751. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  1752. };
  1753. static const struct snd_soc_dapm_route wcd937x_audio_map[] = {
  1754. {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
  1755. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  1756. {"ADC1 REQ", NULL, "ADC1"},
  1757. {"ADC1", NULL, "AMIC1"},
  1758. {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
  1759. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  1760. {"ADC2 REQ", NULL, "ADC2"},
  1761. {"ADC2", NULL, "ADC2 MUX"},
  1762. {"ADC2 MUX", "INP3", "AMIC3"},
  1763. {"ADC2 MUX", "INP2", "AMIC2"},
  1764. {"IN1_HPHL", NULL, "VDD_BUCK"},
  1765. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  1766. {"RX1", NULL, "IN1_HPHL"},
  1767. {"RDAC1", NULL, "RX1"},
  1768. {"HPHL_RDAC", "Switch", "RDAC1"},
  1769. {"HPHL PGA", NULL, "HPHL_RDAC"},
  1770. {"HPHL", NULL, "HPHL PGA"},
  1771. {"IN2_HPHR", NULL, "VDD_BUCK"},
  1772. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  1773. {"RX2", NULL, "IN2_HPHR"},
  1774. {"RDAC2", NULL, "RX2"},
  1775. {"HPHR_RDAC", "Switch", "RDAC2"},
  1776. {"HPHR PGA", NULL, "HPHR_RDAC"},
  1777. {"HPHR", NULL, "HPHR PGA"},
  1778. {"IN3_AUX", NULL, "VDD_BUCK"},
  1779. {"IN3_AUX", NULL, "CLS_H_PORT"},
  1780. {"RX3", NULL, "IN3_AUX"},
  1781. {"RDAC4", NULL, "RX3"},
  1782. {"AUX_RDAC", "Switch", "RDAC4"},
  1783. {"AUX PGA", NULL, "AUX_RDAC"},
  1784. {"AUX", NULL, "AUX PGA"},
  1785. {"RDAC3_MUX", "RX3", "RX3"},
  1786. {"RDAC3_MUX", "RX1", "RX1"},
  1787. {"RDAC3", NULL, "RDAC3_MUX"},
  1788. {"EAR_RDAC", "Switch", "RDAC3"},
  1789. {"EAR PGA", NULL, "EAR_RDAC"},
  1790. {"EAR", NULL, "EAR PGA"},
  1791. };
  1792. static const struct snd_soc_dapm_route wcd9375_audio_map[] = {
  1793. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  1794. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  1795. {"ADC3 REQ", NULL, "ADC3"},
  1796. {"ADC3", NULL, "AMIC4"},
  1797. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  1798. {"DMIC1_MIXER", "Switch", "DMIC1"},
  1799. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  1800. {"DMIC2_MIXER", "Switch", "DMIC2"},
  1801. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  1802. {"DMIC3_MIXER", "Switch", "DMIC3"},
  1803. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  1804. {"DMIC4_MIXER", "Switch", "DMIC4"},
  1805. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  1806. {"DMIC5_MIXER", "Switch", "DMIC5"},
  1807. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  1808. {"DMIC6_MIXER", "Switch", "DMIC6"},
  1809. };
  1810. static ssize_t wcd937x_version_read(struct snd_info_entry *entry,
  1811. void *file_private_data,
  1812. struct file *file,
  1813. char __user *buf, size_t count,
  1814. loff_t pos)
  1815. {
  1816. struct wcd937x_priv *priv;
  1817. char buffer[WCD937X_VERSION_ENTRY_SIZE];
  1818. int len = 0;
  1819. priv = (struct wcd937x_priv *) entry->private_data;
  1820. if (!priv) {
  1821. pr_err("%s: wcd937x priv is null\n", __func__);
  1822. return -EINVAL;
  1823. }
  1824. switch (priv->version) {
  1825. case WCD937X_VERSION_1_0:
  1826. len = snprintf(buffer, sizeof(buffer), "WCD937X_1_0\n");
  1827. break;
  1828. default:
  1829. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  1830. }
  1831. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  1832. }
  1833. static struct snd_info_entry_ops wcd937x_info_ops = {
  1834. .read = wcd937x_version_read,
  1835. };
  1836. /*
  1837. * wcd937x_info_create_codec_entry - creates wcd937x module
  1838. * @codec_root: The parent directory
  1839. * @component: component instance
  1840. *
  1841. * Creates wcd937x module and version entry under the given
  1842. * parent directory.
  1843. *
  1844. * Return: 0 on success or negative error code on failure.
  1845. */
  1846. int wcd937x_info_create_codec_entry(struct snd_info_entry *codec_root,
  1847. struct snd_soc_component *component)
  1848. {
  1849. struct snd_info_entry *version_entry;
  1850. struct wcd937x_priv *priv;
  1851. struct snd_soc_card *card;
  1852. if (!codec_root || !component)
  1853. return -EINVAL;
  1854. priv = snd_soc_component_get_drvdata(component);
  1855. if (priv->entry) {
  1856. dev_dbg(priv->dev,
  1857. "%s:wcd937x module already created\n", __func__);
  1858. return 0;
  1859. }
  1860. card = component->card;
  1861. priv->entry = snd_info_create_subdir(codec_root->module,
  1862. "wcd937x", codec_root);
  1863. if (!priv->entry) {
  1864. dev_dbg(component->dev, "%s: failed to create wcd937x entry\n",
  1865. __func__);
  1866. return -ENOMEM;
  1867. }
  1868. version_entry = snd_info_create_card_entry(card->snd_card,
  1869. "version",
  1870. priv->entry);
  1871. if (!version_entry) {
  1872. dev_dbg(component->dev, "%s: failed to create wcd937x version entry\n",
  1873. __func__);
  1874. return -ENOMEM;
  1875. }
  1876. version_entry->private_data = priv;
  1877. version_entry->size = WCD937X_VERSION_ENTRY_SIZE;
  1878. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  1879. version_entry->c.ops = &wcd937x_info_ops;
  1880. if (snd_info_register(version_entry) < 0) {
  1881. snd_info_free_entry(version_entry);
  1882. return -ENOMEM;
  1883. }
  1884. priv->version_entry = version_entry;
  1885. return 0;
  1886. }
  1887. EXPORT_SYMBOL(wcd937x_info_create_codec_entry);
  1888. static int wcd937x_soc_codec_probe(struct snd_soc_component *component)
  1889. {
  1890. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1891. struct snd_soc_dapm_context *dapm =
  1892. snd_soc_component_get_dapm(component);
  1893. int variant;
  1894. int ret = -EINVAL;
  1895. dev_info(component->dev, "%s()\n", __func__);
  1896. wcd937x = snd_soc_component_get_drvdata(component);
  1897. if (!wcd937x)
  1898. return -EINVAL;
  1899. wcd937x->component = component;
  1900. variant = (snd_soc_component_read32(
  1901. component, WCD937X_DIGITAL_EFUSE_REG_0) & 0x0E) >> 1;
  1902. wcd937x->variant = variant;
  1903. wcd937x->fw_data = devm_kzalloc(component->dev,
  1904. sizeof(*(wcd937x->fw_data)),
  1905. GFP_KERNEL);
  1906. if (!wcd937x->fw_data) {
  1907. dev_err(component->dev, "Failed to allocate fw_data\n");
  1908. ret = -ENOMEM;
  1909. goto err;
  1910. }
  1911. set_bit(WCD9XXX_MBHC_CAL, wcd937x->fw_data->cal_bit);
  1912. ret = wcd_cal_create_hwdep(wcd937x->fw_data,
  1913. WCD9XXX_CODEC_HWDEP_NODE, component);
  1914. if (ret < 0) {
  1915. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  1916. goto err_hwdep;
  1917. }
  1918. ret = wcd937x_mbhc_init(&wcd937x->mbhc, component, wcd937x->fw_data);
  1919. if (ret) {
  1920. pr_err("%s: mbhc initialization failed\n", __func__);
  1921. goto err_hwdep;
  1922. }
  1923. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  1924. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  1925. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  1926. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  1927. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  1928. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  1929. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  1930. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  1931. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  1932. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  1933. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  1934. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  1935. snd_soc_dapm_sync(dapm);
  1936. wcd_cls_h_init(&wcd937x->clsh_info);
  1937. wcd937x_init_reg(component);
  1938. if (wcd937x->variant == WCD9375_VARIANT) {
  1939. ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets,
  1940. ARRAY_SIZE(wcd9375_dapm_widgets));
  1941. if (ret < 0) {
  1942. dev_err(component->dev, "%s: Failed to add snd_ctls\n",
  1943. __func__);
  1944. goto err_hwdep;
  1945. }
  1946. ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map,
  1947. ARRAY_SIZE(wcd9375_audio_map));
  1948. if (ret < 0) {
  1949. dev_err(component->dev, "%s: Failed to add routes\n",
  1950. __func__);
  1951. goto err_hwdep;
  1952. }
  1953. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  1954. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  1955. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  1956. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  1957. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  1958. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  1959. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  1960. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  1961. snd_soc_dapm_sync(dapm);
  1962. }
  1963. wcd937x->version = WCD937X_VERSION_1_0;
  1964. /* Register event notifier */
  1965. wcd937x->nblock.notifier_call = wcd937x_event_notify;
  1966. if (wcd937x->register_notifier) {
  1967. ret = wcd937x->register_notifier(wcd937x->handle,
  1968. &wcd937x->nblock,
  1969. true);
  1970. if (ret) {
  1971. dev_err(component->dev,
  1972. "%s: Failed to register notifier %d\n",
  1973. __func__, ret);
  1974. return ret;
  1975. }
  1976. }
  1977. return ret;
  1978. err_hwdep:
  1979. wcd937x->fw_data = NULL;
  1980. err:
  1981. return ret;
  1982. }
  1983. static void wcd937x_soc_codec_remove(struct snd_soc_component *component)
  1984. {
  1985. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1986. if (!wcd937x)
  1987. return;
  1988. if (wcd937x->register_notifier)
  1989. wcd937x->register_notifier(wcd937x->handle,
  1990. &wcd937x->nblock,
  1991. false);
  1992. return;
  1993. }
  1994. static const struct snd_soc_component_driver soc_codec_dev_wcd937x = {
  1995. .name = DRV_NAME,
  1996. .probe = wcd937x_soc_codec_probe,
  1997. .remove = wcd937x_soc_codec_remove,
  1998. .controls = wcd937x_snd_controls,
  1999. .num_controls = ARRAY_SIZE(wcd937x_snd_controls),
  2000. .dapm_widgets = wcd937x_dapm_widgets,
  2001. .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets),
  2002. .dapm_routes = wcd937x_audio_map,
  2003. .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map),
  2004. };
  2005. #ifdef CONFIG_PM_SLEEP
  2006. static int wcd937x_suspend(struct device *dev)
  2007. {
  2008. struct wcd937x_priv *wcd937x = NULL;
  2009. int ret = 0;
  2010. struct wcd937x_pdata *pdata = NULL;
  2011. if (!dev)
  2012. return -ENODEV;
  2013. wcd937x = dev_get_drvdata(dev);
  2014. if (!wcd937x)
  2015. return -EINVAL;
  2016. pdata = dev_get_platdata(wcd937x->dev);
  2017. if (!pdata) {
  2018. dev_err(dev, "%s: pdata is NULL\n", __func__);
  2019. return -EINVAL;
  2020. }
  2021. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  2022. ret = msm_cdc_disable_ondemand_supply(wcd937x->dev,
  2023. wcd937x->supplies,
  2024. pdata->regulator,
  2025. pdata->num_supplies,
  2026. "cdc-vdd-buck");
  2027. if (ret == -EINVAL) {
  2028. dev_err(dev, "%s: vdd buck is not disabled\n",
  2029. __func__);
  2030. return 0;
  2031. }
  2032. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  2033. }
  2034. return 0;
  2035. }
  2036. static int wcd937x_resume(struct device *dev)
  2037. {
  2038. return 0;
  2039. }
  2040. #endif
  2041. static int wcd937x_reset(struct device *dev)
  2042. {
  2043. struct wcd937x_priv *wcd937x = NULL;
  2044. int rc = 0;
  2045. int value = 0;
  2046. if (!dev)
  2047. return -ENODEV;
  2048. wcd937x = dev_get_drvdata(dev);
  2049. if (!wcd937x)
  2050. return -EINVAL;
  2051. if (!wcd937x->rst_np) {
  2052. dev_err(dev, "%s: reset gpio device node not specified\n",
  2053. __func__);
  2054. return -EINVAL;
  2055. }
  2056. value = msm_cdc_pinctrl_get_state(wcd937x->rst_np);
  2057. if (value > 0)
  2058. return 0;
  2059. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2060. if (rc) {
  2061. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2062. __func__);
  2063. return rc;
  2064. }
  2065. /* 20ms sleep required after pulling the reset gpio to LOW */
  2066. usleep_range(20, 30);
  2067. rc = msm_cdc_pinctrl_select_active_state(wcd937x->rst_np);
  2068. if (rc) {
  2069. dev_err(dev, "%s: wcd active state request fail!\n",
  2070. __func__);
  2071. return rc;
  2072. }
  2073. /* 20ms sleep required after pulling the reset gpio to HIGH */
  2074. usleep_range(20, 30);
  2075. return rc;
  2076. }
  2077. static int wcd937x_read_of_property_u32(struct device *dev, const char *name,
  2078. u32 *val)
  2079. {
  2080. int rc = 0;
  2081. rc = of_property_read_u32(dev->of_node, name, val);
  2082. if (rc)
  2083. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2084. __func__, name, dev->of_node->full_name);
  2085. return rc;
  2086. }
  2087. static void wcd937x_dt_parse_micbias_info(struct device *dev,
  2088. struct wcd937x_micbias_setting *mb)
  2089. {
  2090. u32 prop_val = 0;
  2091. int rc = 0;
  2092. /* MB1 */
  2093. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2094. NULL)) {
  2095. rc = wcd937x_read_of_property_u32(dev,
  2096. "qcom,cdc-micbias1-mv",
  2097. &prop_val);
  2098. if (!rc)
  2099. mb->micb1_mv = prop_val;
  2100. } else {
  2101. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2102. __func__);
  2103. }
  2104. /* MB2 */
  2105. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2106. NULL)) {
  2107. rc = wcd937x_read_of_property_u32(dev,
  2108. "qcom,cdc-micbias2-mv",
  2109. &prop_val);
  2110. if (!rc)
  2111. mb->micb2_mv = prop_val;
  2112. } else {
  2113. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2114. __func__);
  2115. }
  2116. /* MB3 */
  2117. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2118. NULL)) {
  2119. rc = wcd937x_read_of_property_u32(dev,
  2120. "qcom,cdc-micbias3-mv",
  2121. &prop_val);
  2122. if (!rc)
  2123. mb->micb3_mv = prop_val;
  2124. } else {
  2125. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2126. __func__);
  2127. }
  2128. }
  2129. static int wcd937x_reset_low(struct device *dev)
  2130. {
  2131. struct wcd937x_priv *wcd937x = NULL;
  2132. int rc = 0;
  2133. if (!dev)
  2134. return -ENODEV;
  2135. wcd937x = dev_get_drvdata(dev);
  2136. if (!wcd937x)
  2137. return -EINVAL;
  2138. if (!wcd937x->rst_np) {
  2139. dev_err(dev, "%s: reset gpio device node not specified\n",
  2140. __func__);
  2141. return -EINVAL;
  2142. }
  2143. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2144. if (rc) {
  2145. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2146. __func__);
  2147. return rc;
  2148. }
  2149. /* 20ms sleep required after pulling the reset gpio to LOW */
  2150. usleep_range(20, 30);
  2151. return rc;
  2152. }
  2153. struct wcd937x_pdata *wcd937x_populate_dt_data(struct device *dev)
  2154. {
  2155. struct wcd937x_pdata *pdata = NULL;
  2156. pdata = devm_kzalloc(dev, sizeof(struct wcd937x_pdata),
  2157. GFP_KERNEL);
  2158. if (!pdata)
  2159. return NULL;
  2160. pdata->rst_np = of_parse_phandle(dev->of_node,
  2161. "qcom,wcd-rst-gpio-node", 0);
  2162. if (!pdata->rst_np) {
  2163. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2164. __func__, "qcom,wcd-rst-gpio-node",
  2165. dev->of_node->full_name);
  2166. return NULL;
  2167. }
  2168. /* Parse power supplies */
  2169. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2170. &pdata->num_supplies);
  2171. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2172. dev_err(dev, "%s: no power supplies defined for codec\n",
  2173. __func__);
  2174. return NULL;
  2175. }
  2176. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2177. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2178. wcd937x_dt_parse_micbias_info(dev, &pdata->micbias);
  2179. return pdata;
  2180. }
  2181. static int wcd937x_wakeup(void *handle, bool enable)
  2182. {
  2183. struct wcd937x_priv *priv;
  2184. if (!handle) {
  2185. pr_err("%s: NULL handle\n", __func__);
  2186. return -EINVAL;
  2187. }
  2188. priv = (struct wcd937x_priv *)handle;
  2189. if (!priv->tx_swr_dev) {
  2190. pr_err("%s: tx swr dev is NULL\n", __func__);
  2191. return -EINVAL;
  2192. }
  2193. if (enable)
  2194. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2195. else
  2196. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2197. }
  2198. static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data)
  2199. {
  2200. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2201. __func__, irq);
  2202. return IRQ_HANDLED;
  2203. }
  2204. static int wcd937x_bind(struct device *dev)
  2205. {
  2206. int ret = 0, i = 0;
  2207. struct wcd937x_priv *wcd937x = NULL;
  2208. struct wcd937x_pdata *pdata = NULL;
  2209. struct wcd_ctrl_platform_data *plat_data = NULL;
  2210. wcd937x = devm_kzalloc(dev, sizeof(struct wcd937x_priv), GFP_KERNEL);
  2211. if (!wcd937x)
  2212. return -ENOMEM;
  2213. dev_set_drvdata(dev, wcd937x);
  2214. pdata = wcd937x_populate_dt_data(dev);
  2215. if (!pdata) {
  2216. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2217. return -EINVAL;
  2218. }
  2219. wcd937x->dev = dev;
  2220. wcd937x->dev->platform_data = pdata;
  2221. wcd937x->rst_np = pdata->rst_np;
  2222. ret = msm_cdc_init_supplies(dev, &wcd937x->supplies,
  2223. pdata->regulator, pdata->num_supplies);
  2224. if (!wcd937x->supplies) {
  2225. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2226. __func__);
  2227. return ret;
  2228. }
  2229. plat_data = dev_get_platdata(dev->parent);
  2230. if (!plat_data) {
  2231. dev_err(dev, "%s: platform data from parent is NULL\n",
  2232. __func__);
  2233. return -EINVAL;
  2234. }
  2235. wcd937x->handle = (void *)plat_data->handle;
  2236. if (!wcd937x->handle) {
  2237. dev_err(dev, "%s: handle is NULL\n", __func__);
  2238. return -EINVAL;
  2239. }
  2240. wcd937x->update_wcd_event = plat_data->update_wcd_event;
  2241. if (!wcd937x->update_wcd_event) {
  2242. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2243. __func__);
  2244. return -EINVAL;
  2245. }
  2246. wcd937x->register_notifier = plat_data->register_notifier;
  2247. if (!wcd937x->register_notifier) {
  2248. dev_err(dev, "%s: register_notifier api is null!\n",
  2249. __func__);
  2250. return -EINVAL;
  2251. }
  2252. ret = msm_cdc_enable_static_supplies(dev, wcd937x->supplies,
  2253. pdata->regulator,
  2254. pdata->num_supplies);
  2255. if (ret) {
  2256. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2257. __func__);
  2258. return ret;
  2259. }
  2260. wcd937x_reset(dev);
  2261. /*
  2262. * Add 5msec delay to provide sufficient time for
  2263. * soundwire auto enumeration of slave devices as
  2264. * as per HW requirement.
  2265. */
  2266. usleep_range(5000, 5010);
  2267. wcd937x->wakeup = wcd937x_wakeup;
  2268. ret = component_bind_all(dev, wcd937x);
  2269. if (ret) {
  2270. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2271. __func__, ret);
  2272. return ret;
  2273. }
  2274. ret = wcd937x_parse_port_mapping(dev, "qcom,rx_swr_ch_map", CODEC_RX);
  2275. ret |= wcd937x_parse_port_mapping(dev, "qcom,tx_swr_ch_map", CODEC_TX);
  2276. if (ret) {
  2277. dev_err(dev, "Failed to read port mapping\n");
  2278. goto err;
  2279. }
  2280. wcd937x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2281. if (!wcd937x->rx_swr_dev) {
  2282. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2283. __func__);
  2284. ret = -ENODEV;
  2285. goto err;
  2286. }
  2287. wcd937x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2288. if (!wcd937x->tx_swr_dev) {
  2289. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2290. __func__);
  2291. ret = -ENODEV;
  2292. goto err;
  2293. }
  2294. wcd937x->regmap = devm_regmap_init_swr(wcd937x->tx_swr_dev,
  2295. &wcd937x_regmap_config);
  2296. if (!wcd937x->regmap) {
  2297. dev_err(dev, "%s: Regmap init failed\n",
  2298. __func__);
  2299. goto err;
  2300. }
  2301. /* Set all interupts as edge triggered */
  2302. for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++)
  2303. regmap_write(wcd937x->regmap,
  2304. (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2305. wcd937x_regmap_irq_chip.irq_drv_data = wcd937x;
  2306. wcd937x->irq_info.wcd_regmap_irq_chip = &wcd937x_regmap_irq_chip;
  2307. wcd937x->irq_info.codec_name = "WCD937X";
  2308. wcd937x->irq_info.regmap = wcd937x->regmap;
  2309. wcd937x->irq_info.dev = dev;
  2310. ret = wcd_irq_init(&wcd937x->irq_info, &wcd937x->virq);
  2311. if (ret) {
  2312. dev_err(dev, "%s: IRQ init failed: %d\n",
  2313. __func__, ret);
  2314. goto err;
  2315. }
  2316. wcd937x->tx_swr_dev->slave_irq = wcd937x->virq;
  2317. mutex_init(&wcd937x->micb_lock);
  2318. /* Request for watchdog interrupt */
  2319. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT,
  2320. "HPHR PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2321. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT,
  2322. "HPHL PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2323. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT,
  2324. "AUX PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2325. /* Enable watchdog interrupt for HPH and AUX */
  2326. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT);
  2327. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT);
  2328. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  2329. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x,
  2330. NULL, 0);
  2331. if (ret) {
  2332. dev_err(dev, "%s: Codec registration failed\n",
  2333. __func__);
  2334. goto err_irq;
  2335. }
  2336. return ret;
  2337. err_irq:
  2338. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2339. err:
  2340. component_unbind_all(dev, wcd937x);
  2341. return ret;
  2342. }
  2343. static void wcd937x_unbind(struct device *dev)
  2344. {
  2345. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  2346. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2347. snd_soc_unregister_component(dev);
  2348. component_unbind_all(dev, wcd937x);
  2349. mutex_destroy(&wcd937x->micb_lock);
  2350. }
  2351. static const struct of_device_id wcd937x_dt_match[] = {
  2352. { .compatible = "qcom,wcd937x-codec" },
  2353. {}
  2354. };
  2355. static const struct component_master_ops wcd937x_comp_ops = {
  2356. .bind = wcd937x_bind,
  2357. .unbind = wcd937x_unbind,
  2358. };
  2359. static int wcd937x_compare_of(struct device *dev, void *data)
  2360. {
  2361. return dev->of_node == data;
  2362. }
  2363. static void wcd937x_release_of(struct device *dev, void *data)
  2364. {
  2365. of_node_put(data);
  2366. }
  2367. static int wcd937x_add_slave_components(struct device *dev,
  2368. struct component_match **matchptr)
  2369. {
  2370. struct device_node *np, *rx_node, *tx_node;
  2371. np = dev->of_node;
  2372. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  2373. if (!rx_node) {
  2374. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  2375. return -ENODEV;
  2376. }
  2377. of_node_get(rx_node);
  2378. component_match_add_release(dev, matchptr,
  2379. wcd937x_release_of,
  2380. wcd937x_compare_of,
  2381. rx_node);
  2382. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  2383. if (!tx_node) {
  2384. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  2385. return -ENODEV;
  2386. }
  2387. of_node_get(tx_node);
  2388. component_match_add_release(dev, matchptr,
  2389. wcd937x_release_of,
  2390. wcd937x_compare_of,
  2391. tx_node);
  2392. return 0;
  2393. }
  2394. static int wcd937x_probe(struct platform_device *pdev)
  2395. {
  2396. struct component_match *match = NULL;
  2397. int ret;
  2398. ret = wcd937x_add_slave_components(&pdev->dev, &match);
  2399. if (ret)
  2400. return ret;
  2401. return component_master_add_with_match(&pdev->dev,
  2402. &wcd937x_comp_ops, match);
  2403. }
  2404. static int wcd937x_remove(struct platform_device *pdev)
  2405. {
  2406. component_master_del(&pdev->dev, &wcd937x_comp_ops);
  2407. return 0;
  2408. }
  2409. #ifdef CONFIG_PM_SLEEP
  2410. static const struct dev_pm_ops wcd937x_dev_pm_ops = {
  2411. SET_SYSTEM_SLEEP_PM_OPS(
  2412. wcd937x_suspend,
  2413. wcd937x_resume
  2414. )
  2415. };
  2416. #endif
  2417. static struct platform_driver wcd937x_codec_driver = {
  2418. .probe = wcd937x_probe,
  2419. .remove = wcd937x_remove,
  2420. .driver = {
  2421. .name = "wcd937x_codec",
  2422. .owner = THIS_MODULE,
  2423. .of_match_table = of_match_ptr(wcd937x_dt_match),
  2424. #ifdef CONFIG_PM_SLEEP
  2425. .pm = &wcd937x_dev_pm_ops,
  2426. #endif
  2427. },
  2428. };
  2429. module_platform_driver(wcd937x_codec_driver);
  2430. MODULE_DESCRIPTION("WCD937X Codec driver");
  2431. MODULE_LICENSE("GPL v2");