main.c 102 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/delay.h>
  7. #include <linux/devcoredump.h>
  8. #include <linux/elf.h>
  9. #include <linux/jiffies.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/of_device.h>
  13. #include <linux/of_gpio.h>
  14. #include <linux/pm_wakeup.h>
  15. #include <linux/reboot.h>
  16. #include <linux/rwsem.h>
  17. #include <linux/suspend.h>
  18. #include <linux/timer.h>
  19. #include <linux/version.h>
  20. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0))
  21. #include <linux/panic_notifier.h>
  22. #endif
  23. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  24. #include <soc/qcom/minidump.h>
  25. #endif
  26. #include "cnss_plat_ipc_qmi.h"
  27. #include "cnss_utils.h"
  28. #include "main.h"
  29. #include "bus.h"
  30. #include "debug.h"
  31. #include "genl.h"
  32. #define CNSS_DUMP_FORMAT_VER 0x11
  33. #define CNSS_DUMP_FORMAT_VER_V2 0x22
  34. #define CNSS_DUMP_MAGIC_VER_V2 0x42445953
  35. #define CNSS_DUMP_NAME "CNSS_WLAN"
  36. #define CNSS_DUMP_DESC_SIZE 0x1000
  37. #define CNSS_DUMP_SEG_VER 0x1
  38. #define FILE_SYSTEM_READY 1
  39. #define FW_READY_TIMEOUT 20000
  40. #define FW_ASSERT_TIMEOUT 5000
  41. #define CNSS_EVENT_PENDING 2989
  42. #define POWER_RESET_MIN_DELAY_MS 100
  43. #define CNSS_QUIRKS_DEFAULT 0
  44. #ifdef CONFIG_CNSS_EMULATION
  45. #define CNSS_MHI_TIMEOUT_DEFAULT 90000
  46. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 2000
  47. #define CNSS_QMI_TIMEOUT_DEFAULT 90000
  48. #else
  49. #define CNSS_MHI_TIMEOUT_DEFAULT 0
  50. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 25
  51. #define CNSS_QMI_TIMEOUT_DEFAULT 10000
  52. #endif
  53. #define CNSS_BDF_TYPE_DEFAULT CNSS_BDF_ELF
  54. #define CNSS_TIME_SYNC_PERIOD_DEFAULT 900000
  55. #define CNSS_DMS_QMI_CONNECTION_WAIT_MS 50
  56. #define CNSS_DMS_QMI_CONNECTION_WAIT_RETRY 200
  57. #define CNSS_DAEMON_CONNECT_TIMEOUT_MS 30000
  58. #define CNSS_CAL_DB_FILE_NAME "wlfw_cal_db.bin"
  59. #define CNSS_CAL_START_PROBE_WAIT_RETRY_MAX 100
  60. #define CNSS_CAL_START_PROBE_WAIT_MS 500
  61. enum cnss_cal_db_op {
  62. CNSS_CAL_DB_UPLOAD,
  63. CNSS_CAL_DB_DOWNLOAD,
  64. CNSS_CAL_DB_INVALID_OP,
  65. };
  66. static struct cnss_plat_data *plat_env;
  67. static DECLARE_RWSEM(cnss_pm_sem);
  68. static struct cnss_fw_files FW_FILES_QCA6174_FW_3_0 = {
  69. "qwlan30.bin", "bdwlan30.bin", "otp30.bin", "utf30.bin",
  70. "utfbd30.bin", "epping30.bin", "evicted30.bin"
  71. };
  72. static struct cnss_fw_files FW_FILES_DEFAULT = {
  73. "qwlan.bin", "bdwlan.bin", "otp.bin", "utf.bin",
  74. "utfbd.bin", "epping.bin", "evicted.bin"
  75. };
  76. struct cnss_driver_event {
  77. struct list_head list;
  78. enum cnss_driver_event_type type;
  79. bool sync;
  80. struct completion complete;
  81. int ret;
  82. void *data;
  83. };
  84. static void cnss_set_plat_priv(struct platform_device *plat_dev,
  85. struct cnss_plat_data *plat_priv)
  86. {
  87. plat_env = plat_priv;
  88. }
  89. struct cnss_plat_data *cnss_get_plat_priv(struct platform_device *plat_dev)
  90. {
  91. return plat_env;
  92. }
  93. /**
  94. * cnss_get_mem_seg_count - Get segment count of memory
  95. * @type: memory type
  96. * @seg: segment count
  97. *
  98. * Return: 0 on success, negative value on failure
  99. */
  100. int cnss_get_mem_seg_count(enum cnss_remote_mem_type type, u32 *seg)
  101. {
  102. struct cnss_plat_data *plat_priv;
  103. plat_priv = cnss_get_plat_priv(NULL);
  104. if (!plat_priv)
  105. return -ENODEV;
  106. switch (type) {
  107. case CNSS_REMOTE_MEM_TYPE_FW:
  108. *seg = plat_priv->fw_mem_seg_len;
  109. break;
  110. case CNSS_REMOTE_MEM_TYPE_QDSS:
  111. *seg = plat_priv->qdss_mem_seg_len;
  112. break;
  113. default:
  114. return -EINVAL;
  115. }
  116. return 0;
  117. }
  118. EXPORT_SYMBOL(cnss_get_mem_seg_count);
  119. /**
  120. * cnss_get_mem_segment_info - Get memory info of different type
  121. * @type: memory type
  122. * @segment: array to save the segment info
  123. * @seg: segment count
  124. *
  125. * Return: 0 on success, negative value on failure
  126. */
  127. int cnss_get_mem_segment_info(enum cnss_remote_mem_type type,
  128. struct cnss_mem_segment segment[],
  129. u32 segment_count)
  130. {
  131. struct cnss_plat_data *plat_priv;
  132. u32 i;
  133. plat_priv = cnss_get_plat_priv(NULL);
  134. if (!plat_priv)
  135. return -ENODEV;
  136. switch (type) {
  137. case CNSS_REMOTE_MEM_TYPE_FW:
  138. if (segment_count > plat_priv->fw_mem_seg_len)
  139. segment_count = plat_priv->fw_mem_seg_len;
  140. for (i = 0; i < segment_count; i++) {
  141. segment[i].size = plat_priv->fw_mem[i].size;
  142. segment[i].va = plat_priv->fw_mem[i].va;
  143. segment[i].pa = plat_priv->fw_mem[i].pa;
  144. }
  145. break;
  146. case CNSS_REMOTE_MEM_TYPE_QDSS:
  147. if (segment_count > plat_priv->qdss_mem_seg_len)
  148. segment_count = plat_priv->qdss_mem_seg_len;
  149. for (i = 0; i < segment_count; i++) {
  150. segment[i].size = plat_priv->qdss_mem[i].size;
  151. segment[i].va = plat_priv->qdss_mem[i].va;
  152. segment[i].pa = plat_priv->qdss_mem[i].pa;
  153. }
  154. break;
  155. default:
  156. return -EINVAL;
  157. }
  158. return 0;
  159. }
  160. EXPORT_SYMBOL(cnss_get_mem_segment_info);
  161. int cnss_set_feature_list(struct cnss_plat_data *plat_priv,
  162. enum cnss_feature_v01 feature)
  163. {
  164. if (unlikely(!plat_priv || feature >= CNSS_MAX_FEATURE_V01))
  165. return -EINVAL;
  166. plat_priv->feature_list |= 1 << feature;
  167. return 0;
  168. }
  169. int cnss_get_feature_list(struct cnss_plat_data *plat_priv,
  170. u64 *feature_list)
  171. {
  172. if (unlikely(!plat_priv))
  173. return -EINVAL;
  174. *feature_list = plat_priv->feature_list;
  175. return 0;
  176. }
  177. static int cnss_pm_notify(struct notifier_block *b,
  178. unsigned long event, void *p)
  179. {
  180. switch (event) {
  181. case PM_SUSPEND_PREPARE:
  182. down_write(&cnss_pm_sem);
  183. break;
  184. case PM_POST_SUSPEND:
  185. up_write(&cnss_pm_sem);
  186. break;
  187. }
  188. return NOTIFY_DONE;
  189. }
  190. static struct notifier_block cnss_pm_notifier = {
  191. .notifier_call = cnss_pm_notify,
  192. };
  193. void cnss_pm_stay_awake(struct cnss_plat_data *plat_priv)
  194. {
  195. if (atomic_inc_return(&plat_priv->pm_count) != 1)
  196. return;
  197. cnss_pr_dbg("PM stay awake, state: 0x%lx, count: %d\n",
  198. plat_priv->driver_state,
  199. atomic_read(&plat_priv->pm_count));
  200. pm_stay_awake(&plat_priv->plat_dev->dev);
  201. }
  202. void cnss_pm_relax(struct cnss_plat_data *plat_priv)
  203. {
  204. int r = atomic_dec_return(&plat_priv->pm_count);
  205. WARN_ON(r < 0);
  206. if (r != 0)
  207. return;
  208. cnss_pr_dbg("PM relax, state: 0x%lx, count: %d\n",
  209. plat_priv->driver_state,
  210. atomic_read(&plat_priv->pm_count));
  211. pm_relax(&plat_priv->plat_dev->dev);
  212. }
  213. void cnss_lock_pm_sem(struct device *dev)
  214. {
  215. down_read(&cnss_pm_sem);
  216. }
  217. EXPORT_SYMBOL(cnss_lock_pm_sem);
  218. void cnss_release_pm_sem(struct device *dev)
  219. {
  220. up_read(&cnss_pm_sem);
  221. }
  222. EXPORT_SYMBOL(cnss_release_pm_sem);
  223. int cnss_get_fw_files_for_target(struct device *dev,
  224. struct cnss_fw_files *pfw_files,
  225. u32 target_type, u32 target_version)
  226. {
  227. if (!pfw_files)
  228. return -ENODEV;
  229. switch (target_version) {
  230. case QCA6174_REV3_VERSION:
  231. case QCA6174_REV3_2_VERSION:
  232. memcpy(pfw_files, &FW_FILES_QCA6174_FW_3_0, sizeof(*pfw_files));
  233. break;
  234. default:
  235. memcpy(pfw_files, &FW_FILES_DEFAULT, sizeof(*pfw_files));
  236. cnss_pr_err("Unknown target version, type: 0x%X, version: 0x%X",
  237. target_type, target_version);
  238. break;
  239. }
  240. return 0;
  241. }
  242. EXPORT_SYMBOL(cnss_get_fw_files_for_target);
  243. int cnss_get_platform_cap(struct device *dev, struct cnss_platform_cap *cap)
  244. {
  245. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  246. if (!plat_priv)
  247. return -ENODEV;
  248. if (!cap)
  249. return -EINVAL;
  250. *cap = plat_priv->cap;
  251. cnss_pr_dbg("Platform cap_flag is 0x%x\n", cap->cap_flag);
  252. return 0;
  253. }
  254. EXPORT_SYMBOL(cnss_get_platform_cap);
  255. void cnss_request_pm_qos(struct device *dev, u32 qos_val)
  256. {
  257. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  258. if (!plat_priv)
  259. return;
  260. cpu_latency_qos_add_request(&plat_priv->qos_request, qos_val);
  261. }
  262. EXPORT_SYMBOL(cnss_request_pm_qos);
  263. void cnss_remove_pm_qos(struct device *dev)
  264. {
  265. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  266. if (!plat_priv)
  267. return;
  268. cpu_latency_qos_remove_request(&plat_priv->qos_request);
  269. }
  270. EXPORT_SYMBOL(cnss_remove_pm_qos);
  271. int cnss_wlan_enable(struct device *dev,
  272. struct cnss_wlan_enable_cfg *config,
  273. enum cnss_driver_mode mode,
  274. const char *host_version)
  275. {
  276. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  277. int ret = 0;
  278. if (!plat_priv)
  279. return -ENODEV;
  280. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  281. return 0;
  282. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  283. return 0;
  284. if (!config || !host_version) {
  285. cnss_pr_err("Invalid config or host_version pointer\n");
  286. return -EINVAL;
  287. }
  288. cnss_pr_dbg("Mode: %d, config: %pK, host_version: %s\n",
  289. mode, config, host_version);
  290. if (mode == CNSS_WALTEST || mode == CNSS_CCPM)
  291. goto skip_cfg;
  292. ret = cnss_wlfw_wlan_cfg_send_sync(plat_priv, config, host_version);
  293. if (ret)
  294. goto out;
  295. skip_cfg:
  296. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, mode);
  297. out:
  298. return ret;
  299. }
  300. EXPORT_SYMBOL(cnss_wlan_enable);
  301. int cnss_wlan_disable(struct device *dev, enum cnss_driver_mode mode)
  302. {
  303. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  304. int ret = 0;
  305. if (!plat_priv)
  306. return -ENODEV;
  307. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  308. return 0;
  309. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  310. return 0;
  311. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  312. cnss_bus_free_qdss_mem(plat_priv);
  313. return ret;
  314. }
  315. EXPORT_SYMBOL(cnss_wlan_disable);
  316. int cnss_athdiag_read(struct device *dev, u32 offset, u32 mem_type,
  317. u32 data_len, u8 *output)
  318. {
  319. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  320. int ret = 0;
  321. if (!plat_priv) {
  322. cnss_pr_err("plat_priv is NULL!\n");
  323. return -EINVAL;
  324. }
  325. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  326. return 0;
  327. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  328. cnss_pr_err("Invalid state for athdiag read: 0x%lx\n",
  329. plat_priv->driver_state);
  330. ret = -EINVAL;
  331. goto out;
  332. }
  333. ret = cnss_wlfw_athdiag_read_send_sync(plat_priv, offset, mem_type,
  334. data_len, output);
  335. out:
  336. return ret;
  337. }
  338. EXPORT_SYMBOL(cnss_athdiag_read);
  339. int cnss_athdiag_write(struct device *dev, u32 offset, u32 mem_type,
  340. u32 data_len, u8 *input)
  341. {
  342. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  343. int ret = 0;
  344. if (!plat_priv) {
  345. cnss_pr_err("plat_priv is NULL!\n");
  346. return -EINVAL;
  347. }
  348. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  349. return 0;
  350. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  351. cnss_pr_err("Invalid state for athdiag write: 0x%lx\n",
  352. plat_priv->driver_state);
  353. ret = -EINVAL;
  354. goto out;
  355. }
  356. ret = cnss_wlfw_athdiag_write_send_sync(plat_priv, offset, mem_type,
  357. data_len, input);
  358. out:
  359. return ret;
  360. }
  361. EXPORT_SYMBOL(cnss_athdiag_write);
  362. int cnss_set_fw_log_mode(struct device *dev, u8 fw_log_mode)
  363. {
  364. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  365. if (!plat_priv)
  366. return -ENODEV;
  367. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  368. return 0;
  369. return cnss_wlfw_ini_send_sync(plat_priv, fw_log_mode);
  370. }
  371. EXPORT_SYMBOL(cnss_set_fw_log_mode);
  372. int cnss_set_pcie_gen_speed(struct device *dev, u8 pcie_gen_speed)
  373. {
  374. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  375. if (!plat_priv)
  376. return -EINVAL;
  377. if (plat_priv->device_id != QCA6490_DEVICE_ID ||
  378. !plat_priv->fw_pcie_gen_switch)
  379. return -EOPNOTSUPP;
  380. if (pcie_gen_speed < QMI_PCIE_GEN_SPEED_1_V01 ||
  381. pcie_gen_speed > QMI_PCIE_GEN_SPEED_3_V01)
  382. return -EINVAL;
  383. cnss_pr_dbg("WLAN provided PCIE gen speed: %d\n", pcie_gen_speed);
  384. plat_priv->pcie_gen_speed = pcie_gen_speed;
  385. return 0;
  386. }
  387. EXPORT_SYMBOL(cnss_set_pcie_gen_speed);
  388. static int cnss_fw_mem_ready_hdlr(struct cnss_plat_data *plat_priv)
  389. {
  390. int ret = 0;
  391. if (!plat_priv)
  392. return -ENODEV;
  393. set_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  394. ret = cnss_wlfw_tgt_cap_send_sync(plat_priv);
  395. if (ret)
  396. goto out;
  397. if (plat_priv->hds_enabled)
  398. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_HDS);
  399. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_REGDB);
  400. ret = cnss_wlfw_bdf_dnld_send_sync(plat_priv,
  401. plat_priv->ctrl_params.bdf_type);
  402. if (ret)
  403. goto out;
  404. ret = cnss_bus_load_m3(plat_priv);
  405. if (ret)
  406. goto out;
  407. ret = cnss_wlfw_m3_dnld_send_sync(plat_priv);
  408. if (ret)
  409. goto out;
  410. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  411. return 0;
  412. out:
  413. return ret;
  414. }
  415. static int cnss_request_antenna_sharing(struct cnss_plat_data *plat_priv)
  416. {
  417. int ret = 0;
  418. if (!plat_priv->antenna) {
  419. ret = cnss_wlfw_antenna_switch_send_sync(plat_priv);
  420. if (ret)
  421. goto out;
  422. }
  423. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state)) {
  424. ret = coex_antenna_switch_to_wlan_send_sync_msg(plat_priv);
  425. if (ret)
  426. goto out;
  427. }
  428. ret = cnss_wlfw_antenna_grant_send_sync(plat_priv);
  429. if (ret)
  430. goto out;
  431. return 0;
  432. out:
  433. return ret;
  434. }
  435. static void cnss_release_antenna_sharing(struct cnss_plat_data *plat_priv)
  436. {
  437. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state))
  438. coex_antenna_switch_to_mdm_send_sync_msg(plat_priv);
  439. }
  440. static int cnss_setup_dms_mac(struct cnss_plat_data *plat_priv)
  441. {
  442. u32 i;
  443. int ret = 0;
  444. struct cnss_plat_ipc_daemon_config *cfg;
  445. ret = cnss_qmi_get_dms_mac(plat_priv);
  446. if (ret == 0 && plat_priv->dms.mac_valid)
  447. goto qmi_send;
  448. /* DTSI property use-nv-mac is used to force DMS MAC address for WLAN.
  449. * Thus assert on failure to get MAC from DMS even after retries
  450. */
  451. if (plat_priv->use_nv_mac) {
  452. /* Check if Daemon says platform support DMS MAC provisioning */
  453. cfg = cnss_plat_ipc_qmi_daemon_config();
  454. if (cfg) {
  455. if (!cfg->dms_mac_addr_supported) {
  456. cnss_pr_err("DMS MAC address not supported\n");
  457. CNSS_ASSERT(0);
  458. return -EINVAL;
  459. }
  460. }
  461. for (i = 0; i < CNSS_DMS_QMI_CONNECTION_WAIT_RETRY; i++) {
  462. if (plat_priv->dms.mac_valid)
  463. break;
  464. ret = cnss_qmi_get_dms_mac(plat_priv);
  465. if (ret == 0)
  466. break;
  467. msleep(CNSS_DMS_QMI_CONNECTION_WAIT_MS);
  468. }
  469. if (!plat_priv->dms.mac_valid) {
  470. cnss_pr_err("Unable to get MAC from DMS after retries\n");
  471. CNSS_ASSERT(0);
  472. return -EINVAL;
  473. }
  474. }
  475. qmi_send:
  476. if (plat_priv->dms.mac_valid)
  477. ret =
  478. cnss_wlfw_wlan_mac_req_send_sync(plat_priv, plat_priv->dms.mac,
  479. ARRAY_SIZE(plat_priv->dms.mac));
  480. return ret;
  481. }
  482. static int cnss_cal_db_mem_update(struct cnss_plat_data *plat_priv,
  483. enum cnss_cal_db_op op, u32 *size)
  484. {
  485. int ret = 0;
  486. u32 timeout = cnss_get_timeout(plat_priv,
  487. CNSS_TIMEOUT_DAEMON_CONNECTION);
  488. enum cnss_plat_ipc_qmi_client_id_v01 client_id =
  489. CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01;
  490. if (op >= CNSS_CAL_DB_INVALID_OP)
  491. return -EINVAL;
  492. if (!plat_priv->cbc_file_download) {
  493. cnss_pr_info("CAL DB file not required as per BDF\n");
  494. return 0;
  495. }
  496. if (*size == 0) {
  497. cnss_pr_err("Invalid cal file size\n");
  498. return -EINVAL;
  499. }
  500. if (!test_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state)) {
  501. cnss_pr_info("Waiting for CNSS Daemon connection\n");
  502. ret = wait_for_completion_timeout(&plat_priv->daemon_connected,
  503. msecs_to_jiffies(timeout));
  504. if (!ret) {
  505. cnss_pr_err("Daemon not yet connected\n");
  506. CNSS_ASSERT(0);
  507. return ret;
  508. }
  509. }
  510. if (!plat_priv->cal_mem->va) {
  511. cnss_pr_err("CAL DB Memory not setup for FW\n");
  512. return -EINVAL;
  513. }
  514. /* Copy CAL DB file contents to/from CAL_TYPE_DDR mem allocated to FW */
  515. if (op == CNSS_CAL_DB_DOWNLOAD) {
  516. cnss_pr_dbg("Initiating Calibration file download to mem\n");
  517. ret = cnss_plat_ipc_qmi_file_download(client_id,
  518. CNSS_CAL_DB_FILE_NAME,
  519. plat_priv->cal_mem->va,
  520. size);
  521. } else {
  522. cnss_pr_dbg("Initiating Calibration mem upload to file\n");
  523. ret = cnss_plat_ipc_qmi_file_upload(client_id,
  524. CNSS_CAL_DB_FILE_NAME,
  525. plat_priv->cal_mem->va,
  526. *size);
  527. }
  528. if (ret)
  529. cnss_pr_err("Cal DB file %s %s failure\n",
  530. CNSS_CAL_DB_FILE_NAME,
  531. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload");
  532. else
  533. cnss_pr_dbg("Cal DB file %s %s size %d done\n",
  534. CNSS_CAL_DB_FILE_NAME,
  535. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload",
  536. *size);
  537. return ret;
  538. }
  539. static int cnss_cal_mem_upload_to_file(struct cnss_plat_data *plat_priv)
  540. {
  541. if (plat_priv->cal_file_size > plat_priv->cal_mem->size) {
  542. cnss_pr_err("Cal file size is larger than Cal DB Mem size\n");
  543. return -EINVAL;
  544. }
  545. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_UPLOAD,
  546. &plat_priv->cal_file_size);
  547. }
  548. static int cnss_cal_file_download_to_mem(struct cnss_plat_data *plat_priv,
  549. u32 *cal_file_size)
  550. {
  551. /* To download pass the total size of cal DB mem allocated.
  552. * After cal file is download to mem, its size is updated in
  553. * return pointer
  554. */
  555. *cal_file_size = plat_priv->cal_mem->size;
  556. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_DOWNLOAD,
  557. cal_file_size);
  558. }
  559. static int cnss_fw_ready_hdlr(struct cnss_plat_data *plat_priv)
  560. {
  561. int ret = 0;
  562. u32 cal_file_size = 0;
  563. if (!plat_priv)
  564. return -ENODEV;
  565. cnss_pr_dbg("Processing FW Init Done..\n");
  566. del_timer(&plat_priv->fw_boot_timer);
  567. set_bit(CNSS_FW_READY, &plat_priv->driver_state);
  568. clear_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state);
  569. cnss_wlfw_send_pcie_gen_speed_sync(plat_priv);
  570. if (test_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state)) {
  571. clear_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state);
  572. clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  573. }
  574. if (test_bit(ENABLE_WALTEST, &plat_priv->ctrl_params.quirks)) {
  575. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  576. CNSS_WALTEST);
  577. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  578. cnss_request_antenna_sharing(plat_priv);
  579. cnss_cal_file_download_to_mem(plat_priv, &cal_file_size);
  580. cnss_wlfw_cal_report_req_send_sync(plat_priv, cal_file_size);
  581. plat_priv->cal_time = jiffies;
  582. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  583. CNSS_CALIBRATION);
  584. } else {
  585. ret = cnss_setup_dms_mac(plat_priv);
  586. ret = cnss_bus_call_driver_probe(plat_priv);
  587. }
  588. if (ret && test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  589. goto out;
  590. else if (ret)
  591. goto shutdown;
  592. cnss_vreg_unvote_type(plat_priv, CNSS_VREG_PRIM);
  593. return 0;
  594. shutdown:
  595. cnss_bus_dev_shutdown(plat_priv);
  596. clear_bit(CNSS_FW_READY, &plat_priv->driver_state);
  597. clear_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  598. out:
  599. return ret;
  600. }
  601. static char *cnss_driver_event_to_str(enum cnss_driver_event_type type)
  602. {
  603. switch (type) {
  604. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  605. return "SERVER_ARRIVE";
  606. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  607. return "SERVER_EXIT";
  608. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  609. return "REQUEST_MEM";
  610. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  611. return "FW_MEM_READY";
  612. case CNSS_DRIVER_EVENT_FW_READY:
  613. return "FW_READY";
  614. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  615. return "COLD_BOOT_CAL_START";
  616. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  617. return "COLD_BOOT_CAL_DONE";
  618. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  619. return "REGISTER_DRIVER";
  620. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  621. return "UNREGISTER_DRIVER";
  622. case CNSS_DRIVER_EVENT_RECOVERY:
  623. return "RECOVERY";
  624. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  625. return "FORCE_FW_ASSERT";
  626. case CNSS_DRIVER_EVENT_POWER_UP:
  627. return "POWER_UP";
  628. case CNSS_DRIVER_EVENT_POWER_DOWN:
  629. return "POWER_DOWN";
  630. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  631. return "IDLE_RESTART";
  632. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  633. return "IDLE_SHUTDOWN";
  634. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  635. return "IMS_WFC_CALL_IND";
  636. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  637. return "WLFW_TWC_CFG_IND";
  638. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  639. return "QDSS_TRACE_REQ_MEM";
  640. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  641. return "FW_MEM_FILE_SAVE";
  642. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  643. return "QDSS_TRACE_FREE";
  644. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  645. return "QDSS_TRACE_REQ_DATA";
  646. case CNSS_DRIVER_EVENT_MAX:
  647. return "EVENT_MAX";
  648. }
  649. return "UNKNOWN";
  650. };
  651. int cnss_driver_event_post(struct cnss_plat_data *plat_priv,
  652. enum cnss_driver_event_type type,
  653. u32 flags, void *data)
  654. {
  655. struct cnss_driver_event *event;
  656. unsigned long irq_flags;
  657. int gfp = GFP_KERNEL;
  658. int ret = 0;
  659. if (!plat_priv)
  660. return -ENODEV;
  661. cnss_pr_dbg("Posting event: %s(%d)%s, state: 0x%lx flags: 0x%0x\n",
  662. cnss_driver_event_to_str(type), type,
  663. flags ? "-sync" : "", plat_priv->driver_state, flags);
  664. if (type >= CNSS_DRIVER_EVENT_MAX) {
  665. cnss_pr_err("Invalid Event type: %d, can't post", type);
  666. return -EINVAL;
  667. }
  668. if (in_interrupt() || irqs_disabled())
  669. gfp = GFP_ATOMIC;
  670. event = kzalloc(sizeof(*event), gfp);
  671. if (!event)
  672. return -ENOMEM;
  673. cnss_pm_stay_awake(plat_priv);
  674. event->type = type;
  675. event->data = data;
  676. init_completion(&event->complete);
  677. event->ret = CNSS_EVENT_PENDING;
  678. event->sync = !!(flags & CNSS_EVENT_SYNC);
  679. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  680. list_add_tail(&event->list, &plat_priv->event_list);
  681. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  682. queue_work(plat_priv->event_wq, &plat_priv->event_work);
  683. if (!(flags & CNSS_EVENT_SYNC))
  684. goto out;
  685. if (flags & CNSS_EVENT_UNKILLABLE)
  686. wait_for_completion(&event->complete);
  687. else if (flags & CNSS_EVENT_UNINTERRUPTIBLE)
  688. ret = wait_for_completion_killable(&event->complete);
  689. else
  690. ret = wait_for_completion_interruptible(&event->complete);
  691. cnss_pr_dbg("Completed event: %s(%d), state: 0x%lx, ret: %d/%d\n",
  692. cnss_driver_event_to_str(type), type,
  693. plat_priv->driver_state, ret, event->ret);
  694. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  695. if (ret == -ERESTARTSYS && event->ret == CNSS_EVENT_PENDING) {
  696. event->sync = false;
  697. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  698. ret = -EINTR;
  699. goto out;
  700. }
  701. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  702. ret = event->ret;
  703. kfree(event);
  704. out:
  705. cnss_pm_relax(plat_priv);
  706. return ret;
  707. }
  708. /**
  709. * cnss_get_timeout - Get timeout for corresponding type.
  710. * @plat_priv: Pointer to platform driver context.
  711. * @cnss_timeout_type: Timeout type.
  712. *
  713. * Return: Timeout in milliseconds.
  714. */
  715. unsigned int cnss_get_timeout(struct cnss_plat_data *plat_priv,
  716. enum cnss_timeout_type timeout_type)
  717. {
  718. unsigned int qmi_timeout = cnss_get_qmi_timeout(plat_priv);
  719. switch (timeout_type) {
  720. case CNSS_TIMEOUT_QMI:
  721. return qmi_timeout;
  722. case CNSS_TIMEOUT_POWER_UP:
  723. return (qmi_timeout << 2);
  724. case CNSS_TIMEOUT_IDLE_RESTART:
  725. /* In idle restart power up sequence, we have fw_boot_timer to
  726. * handle FW initialization failure.
  727. * It uses WLAN_MISSION_MODE_TIMEOUT, so setup 3x that time to
  728. * account for FW dump collection and FW re-initialization on
  729. * retry.
  730. */
  731. return (qmi_timeout + WLAN_MISSION_MODE_TIMEOUT * 3);
  732. case CNSS_TIMEOUT_CALIBRATION:
  733. /* Similar to mission mode, in CBC if FW init fails
  734. * fw recovery is tried. Thus return 2x the CBC timeout.
  735. */
  736. return (qmi_timeout + WLAN_COLD_BOOT_CAL_TIMEOUT * 2);
  737. case CNSS_TIMEOUT_WLAN_WATCHDOG:
  738. return ((qmi_timeout << 1) + WLAN_WD_TIMEOUT_MS);
  739. case CNSS_TIMEOUT_RDDM:
  740. return CNSS_RDDM_TIMEOUT_MS;
  741. case CNSS_TIMEOUT_RECOVERY:
  742. return RECOVERY_TIMEOUT;
  743. case CNSS_TIMEOUT_DAEMON_CONNECTION:
  744. return qmi_timeout + CNSS_DAEMON_CONNECT_TIMEOUT_MS;
  745. default:
  746. return qmi_timeout;
  747. }
  748. }
  749. unsigned int cnss_get_boot_timeout(struct device *dev)
  750. {
  751. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  752. if (!plat_priv) {
  753. cnss_pr_err("plat_priv is NULL\n");
  754. return 0;
  755. }
  756. return cnss_get_timeout(plat_priv, CNSS_TIMEOUT_QMI);
  757. }
  758. EXPORT_SYMBOL(cnss_get_boot_timeout);
  759. int cnss_power_up(struct device *dev)
  760. {
  761. int ret = 0;
  762. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  763. unsigned int timeout;
  764. if (!plat_priv) {
  765. cnss_pr_err("plat_priv is NULL\n");
  766. return -ENODEV;
  767. }
  768. cnss_pr_dbg("Powering up device\n");
  769. ret = cnss_driver_event_post(plat_priv,
  770. CNSS_DRIVER_EVENT_POWER_UP,
  771. CNSS_EVENT_SYNC, NULL);
  772. if (ret)
  773. goto out;
  774. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  775. goto out;
  776. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_POWER_UP);
  777. reinit_completion(&plat_priv->power_up_complete);
  778. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  779. msecs_to_jiffies(timeout));
  780. if (!ret) {
  781. cnss_pr_err("Timeout (%ums) waiting for power up to complete\n",
  782. timeout);
  783. ret = -EAGAIN;
  784. goto out;
  785. }
  786. return 0;
  787. out:
  788. return ret;
  789. }
  790. EXPORT_SYMBOL(cnss_power_up);
  791. int cnss_power_down(struct device *dev)
  792. {
  793. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  794. if (!plat_priv) {
  795. cnss_pr_err("plat_priv is NULL\n");
  796. return -ENODEV;
  797. }
  798. cnss_pr_dbg("Powering down device\n");
  799. return cnss_driver_event_post(plat_priv,
  800. CNSS_DRIVER_EVENT_POWER_DOWN,
  801. CNSS_EVENT_SYNC, NULL);
  802. }
  803. EXPORT_SYMBOL(cnss_power_down);
  804. int cnss_idle_restart(struct device *dev)
  805. {
  806. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  807. unsigned int timeout;
  808. int ret = 0;
  809. if (!plat_priv) {
  810. cnss_pr_err("plat_priv is NULL\n");
  811. return -ENODEV;
  812. }
  813. if (!mutex_trylock(&plat_priv->driver_ops_lock)) {
  814. cnss_pr_dbg("Another driver operation is in progress, ignore idle restart\n");
  815. return -EBUSY;
  816. }
  817. cnss_pr_dbg("Doing idle restart\n");
  818. reinit_completion(&plat_priv->power_up_complete);
  819. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  820. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  821. ret = -EINVAL;
  822. goto out;
  823. }
  824. ret = cnss_driver_event_post(plat_priv,
  825. CNSS_DRIVER_EVENT_IDLE_RESTART,
  826. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  827. if (ret)
  828. goto out;
  829. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  830. ret = cnss_bus_call_driver_probe(plat_priv);
  831. goto out;
  832. }
  833. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_IDLE_RESTART);
  834. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  835. msecs_to_jiffies(timeout));
  836. if (plat_priv->power_up_error) {
  837. ret = plat_priv->power_up_error;
  838. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  839. cnss_pr_dbg("Power up error:%d, exiting\n",
  840. plat_priv->power_up_error);
  841. goto out;
  842. }
  843. if (!ret) {
  844. /* This exception occurs after attempting retry of FW recovery.
  845. * Thus we can safely power off the device.
  846. */
  847. cnss_fatal_err("Timeout (%ums) waiting for idle restart to complete\n",
  848. timeout);
  849. ret = -ETIMEDOUT;
  850. cnss_power_down(dev);
  851. CNSS_ASSERT(0);
  852. goto out;
  853. }
  854. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  855. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  856. del_timer(&plat_priv->fw_boot_timer);
  857. ret = -EINVAL;
  858. goto out;
  859. }
  860. mutex_unlock(&plat_priv->driver_ops_lock);
  861. return 0;
  862. out:
  863. mutex_unlock(&plat_priv->driver_ops_lock);
  864. return ret;
  865. }
  866. EXPORT_SYMBOL(cnss_idle_restart);
  867. int cnss_idle_shutdown(struct device *dev)
  868. {
  869. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  870. unsigned int timeout;
  871. int ret;
  872. if (!plat_priv) {
  873. cnss_pr_err("plat_priv is NULL\n");
  874. return -ENODEV;
  875. }
  876. if (test_bit(CNSS_IN_SUSPEND_RESUME, &plat_priv->driver_state)) {
  877. cnss_pr_dbg("System suspend or resume in progress, ignore idle shutdown\n");
  878. return -EAGAIN;
  879. }
  880. cnss_pr_dbg("Doing idle shutdown\n");
  881. if (!test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state) &&
  882. !test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  883. goto skip_wait;
  884. reinit_completion(&plat_priv->recovery_complete);
  885. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RECOVERY);
  886. ret = wait_for_completion_timeout(&plat_priv->recovery_complete,
  887. msecs_to_jiffies(timeout));
  888. if (!ret) {
  889. cnss_pr_err("Timeout (%ums) waiting for recovery to complete\n",
  890. timeout);
  891. CNSS_ASSERT(0);
  892. }
  893. skip_wait:
  894. return cnss_driver_event_post(plat_priv,
  895. CNSS_DRIVER_EVENT_IDLE_SHUTDOWN,
  896. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  897. }
  898. EXPORT_SYMBOL(cnss_idle_shutdown);
  899. static int cnss_get_resources(struct cnss_plat_data *plat_priv)
  900. {
  901. int ret = 0;
  902. ret = cnss_get_vreg_type(plat_priv, CNSS_VREG_PRIM);
  903. if (ret) {
  904. cnss_pr_err("Failed to get vreg, err = %d\n", ret);
  905. goto out;
  906. }
  907. ret = cnss_get_clk(plat_priv);
  908. if (ret) {
  909. cnss_pr_err("Failed to get clocks, err = %d\n", ret);
  910. goto put_vreg;
  911. }
  912. ret = cnss_get_pinctrl(plat_priv);
  913. if (ret) {
  914. cnss_pr_err("Failed to get pinctrl, err = %d\n", ret);
  915. goto put_clk;
  916. }
  917. return 0;
  918. put_clk:
  919. cnss_put_clk(plat_priv);
  920. put_vreg:
  921. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  922. out:
  923. return ret;
  924. }
  925. static void cnss_put_resources(struct cnss_plat_data *plat_priv)
  926. {
  927. cnss_put_clk(plat_priv);
  928. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  929. }
  930. #if IS_ENABLED(CONFIG_ESOC) && IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  931. static int cnss_modem_notifier_nb(struct notifier_block *nb,
  932. unsigned long code,
  933. void *ss_handle)
  934. {
  935. struct cnss_plat_data *plat_priv =
  936. container_of(nb, struct cnss_plat_data, modem_nb);
  937. struct cnss_esoc_info *esoc_info;
  938. cnss_pr_dbg("Modem notifier: event %lu\n", code);
  939. if (!plat_priv)
  940. return NOTIFY_DONE;
  941. esoc_info = &plat_priv->esoc_info;
  942. if (code == SUBSYS_AFTER_POWERUP)
  943. esoc_info->modem_current_status = 1;
  944. else if (code == SUBSYS_BEFORE_SHUTDOWN)
  945. esoc_info->modem_current_status = 0;
  946. else
  947. return NOTIFY_DONE;
  948. if (!cnss_bus_call_driver_modem_status(plat_priv,
  949. esoc_info->modem_current_status))
  950. return NOTIFY_DONE;
  951. return NOTIFY_OK;
  952. }
  953. static int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  954. {
  955. int ret = 0;
  956. struct device *dev;
  957. struct cnss_esoc_info *esoc_info;
  958. struct esoc_desc *esoc_desc;
  959. const char *client_desc;
  960. dev = &plat_priv->plat_dev->dev;
  961. esoc_info = &plat_priv->esoc_info;
  962. esoc_info->notify_modem_status =
  963. of_property_read_bool(dev->of_node,
  964. "qcom,notify-modem-status");
  965. if (!esoc_info->notify_modem_status)
  966. goto out;
  967. ret = of_property_read_string_index(dev->of_node, "esoc-names", 0,
  968. &client_desc);
  969. if (ret) {
  970. cnss_pr_dbg("esoc-names is not defined in DT, skip!\n");
  971. } else {
  972. esoc_desc = devm_register_esoc_client(dev, client_desc);
  973. if (IS_ERR_OR_NULL(esoc_desc)) {
  974. ret = PTR_RET(esoc_desc);
  975. cnss_pr_err("Failed to register esoc_desc, err = %d\n",
  976. ret);
  977. goto out;
  978. }
  979. esoc_info->esoc_desc = esoc_desc;
  980. }
  981. plat_priv->modem_nb.notifier_call = cnss_modem_notifier_nb;
  982. esoc_info->modem_current_status = 0;
  983. esoc_info->modem_notify_handler =
  984. subsys_notif_register_notifier(esoc_info->esoc_desc ?
  985. esoc_info->esoc_desc->name :
  986. "modem", &plat_priv->modem_nb);
  987. if (IS_ERR(esoc_info->modem_notify_handler)) {
  988. ret = PTR_ERR(esoc_info->modem_notify_handler);
  989. cnss_pr_err("Failed to register esoc notifier, err = %d\n",
  990. ret);
  991. goto unreg_esoc;
  992. }
  993. return 0;
  994. unreg_esoc:
  995. if (esoc_info->esoc_desc)
  996. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  997. out:
  998. return ret;
  999. }
  1000. static void cnss_unregister_esoc(struct cnss_plat_data *plat_priv)
  1001. {
  1002. struct device *dev;
  1003. struct cnss_esoc_info *esoc_info;
  1004. dev = &plat_priv->plat_dev->dev;
  1005. esoc_info = &plat_priv->esoc_info;
  1006. if (esoc_info->notify_modem_status)
  1007. subsys_notif_unregister_notifier
  1008. (esoc_info->modem_notify_handler,
  1009. &plat_priv->modem_nb);
  1010. if (esoc_info->esoc_desc)
  1011. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  1012. }
  1013. #else
  1014. static inline int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  1015. {
  1016. return 0;
  1017. }
  1018. static inline void cnss_unregister_esoc(struct cnss_plat_data *plat_priv) {}
  1019. #endif
  1020. int cnss_enable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1021. {
  1022. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1023. int ret = 0;
  1024. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1025. return 0;
  1026. enable_irq(sol_gpio->dev_sol_irq);
  1027. ret = enable_irq_wake(sol_gpio->dev_sol_irq);
  1028. if (ret)
  1029. cnss_pr_err("Failed to enable device SOL as wake IRQ, err = %d\n",
  1030. ret);
  1031. return ret;
  1032. }
  1033. int cnss_disable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1034. {
  1035. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1036. int ret = 0;
  1037. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1038. return 0;
  1039. ret = disable_irq_wake(sol_gpio->dev_sol_irq);
  1040. if (ret)
  1041. cnss_pr_err("Failed to disable device SOL as wake IRQ, err = %d\n",
  1042. ret);
  1043. disable_irq(sol_gpio->dev_sol_irq);
  1044. return ret;
  1045. }
  1046. int cnss_get_dev_sol_value(struct cnss_plat_data *plat_priv)
  1047. {
  1048. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1049. if (sol_gpio->dev_sol_gpio < 0)
  1050. return -EINVAL;
  1051. return gpio_get_value(sol_gpio->dev_sol_gpio);
  1052. }
  1053. static irqreturn_t cnss_dev_sol_handler(int irq, void *data)
  1054. {
  1055. struct cnss_plat_data *plat_priv = data;
  1056. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1057. sol_gpio->dev_sol_counter++;
  1058. cnss_pr_dbg("WLAN device SOL IRQ (%u) is asserted #%u\n",
  1059. irq, sol_gpio->dev_sol_counter);
  1060. /* Make sure abort current suspend */
  1061. cnss_pm_stay_awake(plat_priv);
  1062. cnss_pm_relax(plat_priv);
  1063. pm_system_wakeup();
  1064. cnss_bus_handle_dev_sol_irq(plat_priv);
  1065. return IRQ_HANDLED;
  1066. }
  1067. static int cnss_init_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1068. {
  1069. struct device *dev = &plat_priv->plat_dev->dev;
  1070. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1071. int ret = 0;
  1072. sol_gpio->dev_sol_gpio = of_get_named_gpio(dev->of_node,
  1073. "wlan-dev-sol-gpio", 0);
  1074. if (sol_gpio->dev_sol_gpio < 0)
  1075. goto out;
  1076. cnss_pr_dbg("Get device SOL GPIO (%d) from device node\n",
  1077. sol_gpio->dev_sol_gpio);
  1078. ret = gpio_request(sol_gpio->dev_sol_gpio, "wlan_dev_sol_gpio");
  1079. if (ret) {
  1080. cnss_pr_err("Failed to request device SOL GPIO, err = %d\n",
  1081. ret);
  1082. goto out;
  1083. }
  1084. gpio_direction_input(sol_gpio->dev_sol_gpio);
  1085. sol_gpio->dev_sol_irq = gpio_to_irq(sol_gpio->dev_sol_gpio);
  1086. ret = request_irq(sol_gpio->dev_sol_irq, cnss_dev_sol_handler,
  1087. IRQF_TRIGGER_FALLING, "wlan_dev_sol_irq", plat_priv);
  1088. if (ret) {
  1089. cnss_pr_err("Failed to request device SOL IRQ, err = %d\n", ret);
  1090. goto free_gpio;
  1091. }
  1092. return 0;
  1093. free_gpio:
  1094. gpio_free(sol_gpio->dev_sol_gpio);
  1095. out:
  1096. return ret;
  1097. }
  1098. static void cnss_deinit_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1099. {
  1100. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1101. if (sol_gpio->dev_sol_gpio < 0)
  1102. return;
  1103. free_irq(sol_gpio->dev_sol_irq, plat_priv);
  1104. gpio_free(sol_gpio->dev_sol_gpio);
  1105. }
  1106. int cnss_set_host_sol_value(struct cnss_plat_data *plat_priv, int value)
  1107. {
  1108. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1109. if (sol_gpio->host_sol_gpio < 0)
  1110. return -EINVAL;
  1111. if (value)
  1112. cnss_pr_dbg("Assert host SOL GPIO\n");
  1113. gpio_set_value(sol_gpio->host_sol_gpio, value);
  1114. return 0;
  1115. }
  1116. int cnss_get_host_sol_value(struct cnss_plat_data *plat_priv)
  1117. {
  1118. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1119. if (sol_gpio->host_sol_gpio < 0)
  1120. return -EINVAL;
  1121. return gpio_get_value(sol_gpio->host_sol_gpio);
  1122. }
  1123. static int cnss_init_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1124. {
  1125. struct device *dev = &plat_priv->plat_dev->dev;
  1126. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1127. int ret = 0;
  1128. sol_gpio->host_sol_gpio = of_get_named_gpio(dev->of_node,
  1129. "wlan-host-sol-gpio", 0);
  1130. if (sol_gpio->host_sol_gpio < 0)
  1131. goto out;
  1132. cnss_pr_dbg("Get host SOL GPIO (%d) from device node\n",
  1133. sol_gpio->host_sol_gpio);
  1134. ret = gpio_request(sol_gpio->host_sol_gpio, "wlan_host_sol_gpio");
  1135. if (ret) {
  1136. cnss_pr_err("Failed to request host SOL GPIO, err = %d\n",
  1137. ret);
  1138. goto out;
  1139. }
  1140. gpio_direction_output(sol_gpio->host_sol_gpio, 0);
  1141. return 0;
  1142. out:
  1143. return ret;
  1144. }
  1145. static void cnss_deinit_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1146. {
  1147. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1148. if (sol_gpio->host_sol_gpio < 0)
  1149. return;
  1150. gpio_free(sol_gpio->host_sol_gpio);
  1151. }
  1152. static int cnss_init_sol_gpio(struct cnss_plat_data *plat_priv)
  1153. {
  1154. int ret;
  1155. ret = cnss_init_dev_sol_gpio(plat_priv);
  1156. if (ret)
  1157. goto out;
  1158. ret = cnss_init_host_sol_gpio(plat_priv);
  1159. if (ret)
  1160. goto deinit_dev_sol;
  1161. return 0;
  1162. deinit_dev_sol:
  1163. cnss_deinit_dev_sol_gpio(plat_priv);
  1164. out:
  1165. return ret;
  1166. }
  1167. static void cnss_deinit_sol_gpio(struct cnss_plat_data *plat_priv)
  1168. {
  1169. cnss_deinit_host_sol_gpio(plat_priv);
  1170. cnss_deinit_dev_sol_gpio(plat_priv);
  1171. }
  1172. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1173. static int cnss_subsys_powerup(const struct subsys_desc *subsys_desc)
  1174. {
  1175. struct cnss_plat_data *plat_priv;
  1176. int ret = 0;
  1177. if (!subsys_desc->dev) {
  1178. cnss_pr_err("dev from subsys_desc is NULL\n");
  1179. return -ENODEV;
  1180. }
  1181. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1182. if (!plat_priv) {
  1183. cnss_pr_err("plat_priv is NULL\n");
  1184. return -ENODEV;
  1185. }
  1186. if (!plat_priv->driver_state) {
  1187. cnss_pr_dbg("Powerup is ignored\n");
  1188. return 0;
  1189. }
  1190. ret = cnss_bus_dev_powerup(plat_priv);
  1191. if (ret)
  1192. __pm_relax(plat_priv->recovery_ws);
  1193. return ret;
  1194. }
  1195. static int cnss_subsys_shutdown(const struct subsys_desc *subsys_desc,
  1196. bool force_stop)
  1197. {
  1198. struct cnss_plat_data *plat_priv;
  1199. if (!subsys_desc->dev) {
  1200. cnss_pr_err("dev from subsys_desc is NULL\n");
  1201. return -ENODEV;
  1202. }
  1203. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1204. if (!plat_priv) {
  1205. cnss_pr_err("plat_priv is NULL\n");
  1206. return -ENODEV;
  1207. }
  1208. if (!plat_priv->driver_state) {
  1209. cnss_pr_dbg("shutdown is ignored\n");
  1210. return 0;
  1211. }
  1212. return cnss_bus_dev_shutdown(plat_priv);
  1213. }
  1214. void cnss_device_crashed(struct device *dev)
  1215. {
  1216. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1217. struct cnss_subsys_info *subsys_info;
  1218. if (!plat_priv)
  1219. return;
  1220. subsys_info = &plat_priv->subsys_info;
  1221. if (subsys_info->subsys_device) {
  1222. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1223. subsys_set_crash_status(subsys_info->subsys_device, true);
  1224. subsystem_restart_dev(subsys_info->subsys_device);
  1225. }
  1226. }
  1227. EXPORT_SYMBOL(cnss_device_crashed);
  1228. static void cnss_subsys_crash_shutdown(const struct subsys_desc *subsys_desc)
  1229. {
  1230. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1231. if (!plat_priv) {
  1232. cnss_pr_err("plat_priv is NULL\n");
  1233. return;
  1234. }
  1235. cnss_bus_dev_crash_shutdown(plat_priv);
  1236. }
  1237. static int cnss_subsys_ramdump(int enable,
  1238. const struct subsys_desc *subsys_desc)
  1239. {
  1240. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1241. if (!plat_priv) {
  1242. cnss_pr_err("plat_priv is NULL\n");
  1243. return -ENODEV;
  1244. }
  1245. if (!enable)
  1246. return 0;
  1247. return cnss_bus_dev_ramdump(plat_priv);
  1248. }
  1249. static void cnss_recovery_work_handler(struct work_struct *work)
  1250. {
  1251. }
  1252. #else
  1253. static void cnss_recovery_work_handler(struct work_struct *work)
  1254. {
  1255. int ret;
  1256. struct cnss_plat_data *plat_priv =
  1257. container_of(work, struct cnss_plat_data, recovery_work);
  1258. if (!plat_priv->recovery_enabled)
  1259. panic("subsys-restart: Resetting the SoC wlan crashed\n");
  1260. cnss_bus_dev_shutdown(plat_priv);
  1261. cnss_bus_dev_ramdump(plat_priv);
  1262. msleep(POWER_RESET_MIN_DELAY_MS);
  1263. ret = cnss_bus_dev_powerup(plat_priv);
  1264. if (ret)
  1265. __pm_relax(plat_priv->recovery_ws);
  1266. return;
  1267. }
  1268. void cnss_device_crashed(struct device *dev)
  1269. {
  1270. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1271. if (!plat_priv)
  1272. return;
  1273. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1274. schedule_work(&plat_priv->recovery_work);
  1275. }
  1276. EXPORT_SYMBOL(cnss_device_crashed);
  1277. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  1278. void *cnss_get_virt_ramdump_mem(struct device *dev, unsigned long *size)
  1279. {
  1280. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1281. struct cnss_ramdump_info *ramdump_info;
  1282. if (!plat_priv)
  1283. return NULL;
  1284. ramdump_info = &plat_priv->ramdump_info;
  1285. *size = ramdump_info->ramdump_size;
  1286. return ramdump_info->ramdump_va;
  1287. }
  1288. EXPORT_SYMBOL(cnss_get_virt_ramdump_mem);
  1289. static const char *cnss_recovery_reason_to_str(enum cnss_recovery_reason reason)
  1290. {
  1291. switch (reason) {
  1292. case CNSS_REASON_DEFAULT:
  1293. return "DEFAULT";
  1294. case CNSS_REASON_LINK_DOWN:
  1295. return "LINK_DOWN";
  1296. case CNSS_REASON_RDDM:
  1297. return "RDDM";
  1298. case CNSS_REASON_TIMEOUT:
  1299. return "TIMEOUT";
  1300. }
  1301. return "UNKNOWN";
  1302. };
  1303. static int cnss_do_recovery(struct cnss_plat_data *plat_priv,
  1304. enum cnss_recovery_reason reason)
  1305. {
  1306. plat_priv->recovery_count++;
  1307. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  1308. goto self_recovery;
  1309. if (test_bit(SKIP_RECOVERY, &plat_priv->ctrl_params.quirks)) {
  1310. cnss_pr_dbg("Skip device recovery\n");
  1311. return 0;
  1312. }
  1313. /* FW recovery sequence has multiple steps and firmware load requires
  1314. * linux PM in awake state. Thus hold the cnss wake source until
  1315. * WLAN MISSION enabled. CNSS_TIMEOUT_RECOVERY option should cover all
  1316. * time taken in this process.
  1317. */
  1318. pm_wakeup_ws_event(plat_priv->recovery_ws,
  1319. cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RECOVERY),
  1320. true);
  1321. switch (reason) {
  1322. case CNSS_REASON_LINK_DOWN:
  1323. if (!cnss_bus_check_link_status(plat_priv)) {
  1324. cnss_pr_dbg("Skip link down recovery as link is already up\n");
  1325. return 0;
  1326. }
  1327. if (test_bit(LINK_DOWN_SELF_RECOVERY,
  1328. &plat_priv->ctrl_params.quirks))
  1329. goto self_recovery;
  1330. if (!cnss_bus_recover_link_down(plat_priv)) {
  1331. /* clear recovery bit here to avoid skipping
  1332. * the recovery work for RDDM later
  1333. */
  1334. clear_bit(CNSS_DRIVER_RECOVERY,
  1335. &plat_priv->driver_state);
  1336. return 0;
  1337. }
  1338. break;
  1339. case CNSS_REASON_RDDM:
  1340. cnss_bus_collect_dump_info(plat_priv, false);
  1341. break;
  1342. case CNSS_REASON_DEFAULT:
  1343. case CNSS_REASON_TIMEOUT:
  1344. break;
  1345. default:
  1346. cnss_pr_err("Unsupported recovery reason: %s(%d)\n",
  1347. cnss_recovery_reason_to_str(reason), reason);
  1348. break;
  1349. }
  1350. cnss_bus_device_crashed(plat_priv);
  1351. return 0;
  1352. self_recovery:
  1353. cnss_pr_dbg("Going for self recovery\n");
  1354. cnss_bus_dev_shutdown(plat_priv);
  1355. if (test_bit(LINK_DOWN_SELF_RECOVERY, &plat_priv->ctrl_params.quirks))
  1356. clear_bit(LINK_DOWN_SELF_RECOVERY,
  1357. &plat_priv->ctrl_params.quirks);
  1358. cnss_bus_dev_powerup(plat_priv);
  1359. return 0;
  1360. }
  1361. static int cnss_driver_recovery_hdlr(struct cnss_plat_data *plat_priv,
  1362. void *data)
  1363. {
  1364. struct cnss_recovery_data *recovery_data = data;
  1365. int ret = 0;
  1366. cnss_pr_dbg("Driver recovery is triggered with reason: %s(%d)\n",
  1367. cnss_recovery_reason_to_str(recovery_data->reason),
  1368. recovery_data->reason);
  1369. if (!plat_priv->driver_state) {
  1370. cnss_pr_err("Improper driver state, ignore recovery\n");
  1371. ret = -EINVAL;
  1372. goto out;
  1373. }
  1374. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  1375. cnss_pr_err("Reboot is in progress, ignore recovery\n");
  1376. ret = -EINVAL;
  1377. goto out;
  1378. }
  1379. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1380. cnss_pr_err("Recovery is already in progress\n");
  1381. CNSS_ASSERT(0);
  1382. ret = -EINVAL;
  1383. goto out;
  1384. }
  1385. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1386. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1387. cnss_pr_err("Driver unload or idle shutdown is in progress, ignore recovery\n");
  1388. ret = -EINVAL;
  1389. goto out;
  1390. }
  1391. switch (plat_priv->device_id) {
  1392. case QCA6174_DEVICE_ID:
  1393. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1394. test_bit(CNSS_DRIVER_IDLE_RESTART,
  1395. &plat_priv->driver_state)) {
  1396. cnss_pr_err("Driver load or idle restart is in progress, ignore recovery\n");
  1397. ret = -EINVAL;
  1398. goto out;
  1399. }
  1400. break;
  1401. default:
  1402. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  1403. set_bit(CNSS_FW_BOOT_RECOVERY,
  1404. &plat_priv->driver_state);
  1405. }
  1406. break;
  1407. }
  1408. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1409. ret = cnss_do_recovery(plat_priv, recovery_data->reason);
  1410. out:
  1411. kfree(data);
  1412. return ret;
  1413. }
  1414. int cnss_self_recovery(struct device *dev,
  1415. enum cnss_recovery_reason reason)
  1416. {
  1417. cnss_schedule_recovery(dev, reason);
  1418. return 0;
  1419. }
  1420. EXPORT_SYMBOL(cnss_self_recovery);
  1421. void cnss_schedule_recovery(struct device *dev,
  1422. enum cnss_recovery_reason reason)
  1423. {
  1424. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1425. struct cnss_recovery_data *data;
  1426. int gfp = GFP_KERNEL;
  1427. if (!test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  1428. cnss_bus_update_status(plat_priv, CNSS_FW_DOWN);
  1429. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1430. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1431. cnss_pr_dbg("Driver unload or idle shutdown is in progress, ignore schedule recovery\n");
  1432. return;
  1433. }
  1434. if (in_interrupt() || irqs_disabled())
  1435. gfp = GFP_ATOMIC;
  1436. data = kzalloc(sizeof(*data), gfp);
  1437. if (!data)
  1438. return;
  1439. data->reason = reason;
  1440. cnss_driver_event_post(plat_priv,
  1441. CNSS_DRIVER_EVENT_RECOVERY,
  1442. 0, data);
  1443. }
  1444. EXPORT_SYMBOL(cnss_schedule_recovery);
  1445. int cnss_force_fw_assert(struct device *dev)
  1446. {
  1447. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1448. if (!plat_priv) {
  1449. cnss_pr_err("plat_priv is NULL\n");
  1450. return -ENODEV;
  1451. }
  1452. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1453. cnss_pr_info("Forced FW assert is not supported\n");
  1454. return -EOPNOTSUPP;
  1455. }
  1456. if (cnss_bus_is_device_down(plat_priv)) {
  1457. cnss_pr_info("Device is already in bad state, ignore force assert\n");
  1458. return 0;
  1459. }
  1460. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1461. cnss_pr_info("Recovery is already in progress, ignore forced FW assert\n");
  1462. return 0;
  1463. }
  1464. if (in_interrupt() || irqs_disabled())
  1465. cnss_driver_event_post(plat_priv,
  1466. CNSS_DRIVER_EVENT_FORCE_FW_ASSERT,
  1467. 0, NULL);
  1468. else
  1469. cnss_bus_force_fw_assert_hdlr(plat_priv);
  1470. return 0;
  1471. }
  1472. EXPORT_SYMBOL(cnss_force_fw_assert);
  1473. int cnss_force_collect_rddm(struct device *dev)
  1474. {
  1475. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1476. unsigned int timeout;
  1477. int ret = 0;
  1478. if (!plat_priv) {
  1479. cnss_pr_err("plat_priv is NULL\n");
  1480. return -ENODEV;
  1481. }
  1482. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1483. cnss_pr_info("Force collect rddm is not supported\n");
  1484. return -EOPNOTSUPP;
  1485. }
  1486. if (cnss_bus_is_device_down(plat_priv)) {
  1487. cnss_pr_info("Device is already in bad state, wait to collect rddm\n");
  1488. goto wait_rddm;
  1489. }
  1490. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1491. cnss_pr_info("Recovery is already in progress, wait to collect rddm\n");
  1492. goto wait_rddm;
  1493. }
  1494. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1495. test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1496. test_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state) ||
  1497. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1498. cnss_pr_info("Loading/Unloading/idle restart/shutdown is in progress, ignore forced collect rddm\n");
  1499. return 0;
  1500. }
  1501. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  1502. if (ret)
  1503. return ret;
  1504. wait_rddm:
  1505. reinit_completion(&plat_priv->rddm_complete);
  1506. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RDDM);
  1507. ret = wait_for_completion_timeout(&plat_priv->rddm_complete,
  1508. msecs_to_jiffies(timeout));
  1509. if (!ret) {
  1510. cnss_pr_err("Timeout (%ums) waiting for RDDM to complete\n",
  1511. timeout);
  1512. ret = -ETIMEDOUT;
  1513. } else if (ret > 0) {
  1514. ret = 0;
  1515. }
  1516. return ret;
  1517. }
  1518. EXPORT_SYMBOL(cnss_force_collect_rddm);
  1519. int cnss_qmi_send_get(struct device *dev)
  1520. {
  1521. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1522. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1523. return 0;
  1524. return cnss_bus_qmi_send_get(plat_priv);
  1525. }
  1526. EXPORT_SYMBOL(cnss_qmi_send_get);
  1527. int cnss_qmi_send_put(struct device *dev)
  1528. {
  1529. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1530. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1531. return 0;
  1532. return cnss_bus_qmi_send_put(plat_priv);
  1533. }
  1534. EXPORT_SYMBOL(cnss_qmi_send_put);
  1535. int cnss_qmi_send(struct device *dev, int type, void *cmd,
  1536. int cmd_len, void *cb_ctx,
  1537. int (*cb)(void *ctx, void *event, int event_len))
  1538. {
  1539. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1540. int ret;
  1541. if (!plat_priv)
  1542. return -ENODEV;
  1543. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1544. return -EINVAL;
  1545. plat_priv->get_info_cb = cb;
  1546. plat_priv->get_info_cb_ctx = cb_ctx;
  1547. ret = cnss_wlfw_get_info_send_sync(plat_priv, type, cmd, cmd_len);
  1548. if (ret) {
  1549. plat_priv->get_info_cb = NULL;
  1550. plat_priv->get_info_cb_ctx = NULL;
  1551. }
  1552. return ret;
  1553. }
  1554. EXPORT_SYMBOL(cnss_qmi_send);
  1555. static int cnss_cold_boot_cal_start_hdlr(struct cnss_plat_data *plat_priv)
  1556. {
  1557. int ret = 0;
  1558. u32 retry = 0, timeout;
  1559. if (test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state)) {
  1560. cnss_pr_dbg("Calibration complete. Ignore calibration req\n");
  1561. goto out;
  1562. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  1563. cnss_pr_dbg("Calibration in progress. Ignore new calibration req\n");
  1564. goto out;
  1565. }
  1566. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1567. test_bit(CNSS_DRIVER_PROBED, &plat_priv->driver_state) ||
  1568. test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  1569. cnss_pr_err("WLAN in mission mode before cold boot calibration\n");
  1570. CNSS_ASSERT(0);
  1571. return -EINVAL;
  1572. }
  1573. while (retry++ < CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  1574. if (test_bit(CNSS_PCI_PROBE_DONE, &plat_priv->driver_state))
  1575. break;
  1576. msleep(CNSS_CAL_START_PROBE_WAIT_MS);
  1577. if (retry == CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  1578. cnss_pr_err("Calibration start failed as PCI probe not complete\n");
  1579. CNSS_ASSERT(0);
  1580. ret = -EINVAL;
  1581. goto mark_cal_fail;
  1582. }
  1583. }
  1584. set_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1585. if (test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state)) {
  1586. timeout = cnss_get_timeout(plat_priv,
  1587. CNSS_TIMEOUT_CALIBRATION);
  1588. cnss_pr_dbg("Restarting calibration %ds timeout\n",
  1589. timeout / 1000);
  1590. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  1591. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  1592. msecs_to_jiffies(timeout));
  1593. }
  1594. reinit_completion(&plat_priv->cal_complete);
  1595. ret = cnss_bus_dev_powerup(plat_priv);
  1596. mark_cal_fail:
  1597. if (ret) {
  1598. complete(&plat_priv->cal_complete);
  1599. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1600. /* Set CBC done in driver state to mark attempt and note error
  1601. * since calibration cannot be retried at boot.
  1602. */
  1603. plat_priv->cal_done = CNSS_CAL_FAILURE;
  1604. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  1605. }
  1606. out:
  1607. return ret;
  1608. }
  1609. static int cnss_cold_boot_cal_done_hdlr(struct cnss_plat_data *plat_priv,
  1610. void *data)
  1611. {
  1612. struct cnss_cal_info *cal_info = data;
  1613. if (!test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state) ||
  1614. test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state))
  1615. goto out;
  1616. switch (cal_info->cal_status) {
  1617. case CNSS_CAL_DONE:
  1618. cnss_pr_dbg("Calibration completed successfully\n");
  1619. plat_priv->cal_done = true;
  1620. break;
  1621. case CNSS_CAL_TIMEOUT:
  1622. case CNSS_CAL_FAILURE:
  1623. cnss_pr_dbg("Calibration failed. Status: %d, force shutdown\n",
  1624. cal_info->cal_status);
  1625. break;
  1626. default:
  1627. cnss_pr_err("Unknown calibration status: %u\n",
  1628. cal_info->cal_status);
  1629. break;
  1630. }
  1631. cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  1632. cnss_bus_free_qdss_mem(plat_priv);
  1633. cnss_release_antenna_sharing(plat_priv);
  1634. cnss_bus_dev_shutdown(plat_priv);
  1635. msleep(POWER_RESET_MIN_DELAY_MS);
  1636. complete(&plat_priv->cal_complete);
  1637. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1638. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  1639. if (cal_info->cal_status == CNSS_CAL_DONE) {
  1640. cnss_cal_mem_upload_to_file(plat_priv);
  1641. if (!test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state))
  1642. goto out;
  1643. cnss_pr_dbg("Schedule WLAN driver load\n");
  1644. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  1645. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  1646. 0);
  1647. }
  1648. out:
  1649. kfree(data);
  1650. return 0;
  1651. }
  1652. static int cnss_power_up_hdlr(struct cnss_plat_data *plat_priv)
  1653. {
  1654. int ret;
  1655. ret = cnss_bus_dev_powerup(plat_priv);
  1656. if (ret)
  1657. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  1658. return ret;
  1659. }
  1660. static int cnss_power_down_hdlr(struct cnss_plat_data *plat_priv)
  1661. {
  1662. cnss_bus_dev_shutdown(plat_priv);
  1663. return 0;
  1664. }
  1665. static int cnss_qdss_trace_req_mem_hdlr(struct cnss_plat_data *plat_priv)
  1666. {
  1667. int ret = 0;
  1668. ret = cnss_bus_alloc_qdss_mem(plat_priv);
  1669. if (ret < 0)
  1670. return ret;
  1671. return cnss_wlfw_qdss_trace_mem_info_send_sync(plat_priv);
  1672. }
  1673. static void *cnss_get_fw_mem_pa_to_va(struct cnss_fw_mem *fw_mem,
  1674. u32 mem_seg_len, u64 pa, u32 size)
  1675. {
  1676. int i = 0;
  1677. u64 offset = 0;
  1678. void *va = NULL;
  1679. u64 local_pa;
  1680. u32 local_size;
  1681. for (i = 0; i < mem_seg_len; i++) {
  1682. local_pa = (u64)fw_mem[i].pa;
  1683. local_size = (u32)fw_mem[i].size;
  1684. if (pa == local_pa && size <= local_size) {
  1685. va = fw_mem[i].va;
  1686. break;
  1687. }
  1688. if (pa > local_pa &&
  1689. pa < local_pa + local_size &&
  1690. pa + size <= local_pa + local_size) {
  1691. offset = pa - local_pa;
  1692. va = fw_mem[i].va + offset;
  1693. break;
  1694. }
  1695. }
  1696. return va;
  1697. }
  1698. static int cnss_fw_mem_file_save_hdlr(struct cnss_plat_data *plat_priv,
  1699. void *data)
  1700. {
  1701. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  1702. struct cnss_fw_mem *fw_mem_seg;
  1703. int ret = 0L;
  1704. void *va = NULL;
  1705. u32 i, fw_mem_seg_len;
  1706. switch (event_data->mem_type) {
  1707. case QMI_WLFW_MEM_TYPE_DDR_V01:
  1708. if (!plat_priv->fw_mem_seg_len)
  1709. goto invalid_mem_save;
  1710. fw_mem_seg = plat_priv->fw_mem;
  1711. fw_mem_seg_len = plat_priv->fw_mem_seg_len;
  1712. break;
  1713. case QMI_WLFW_MEM_QDSS_V01:
  1714. if (!plat_priv->qdss_mem_seg_len)
  1715. goto invalid_mem_save;
  1716. fw_mem_seg = plat_priv->qdss_mem;
  1717. fw_mem_seg_len = plat_priv->qdss_mem_seg_len;
  1718. break;
  1719. default:
  1720. goto invalid_mem_save;
  1721. }
  1722. for (i = 0; i < event_data->mem_seg_len; i++) {
  1723. va = cnss_get_fw_mem_pa_to_va(fw_mem_seg, fw_mem_seg_len,
  1724. event_data->mem_seg[i].addr,
  1725. event_data->mem_seg[i].size);
  1726. if (!va) {
  1727. cnss_pr_err("Fail to find matching va of pa %pa for mem type: %d\n",
  1728. &event_data->mem_seg[i].addr,
  1729. event_data->mem_type);
  1730. ret = -EINVAL;
  1731. break;
  1732. }
  1733. ret = cnss_genl_send_msg(va, CNSS_GENL_MSG_TYPE_QDSS,
  1734. event_data->file_name,
  1735. event_data->mem_seg[i].size);
  1736. if (ret < 0) {
  1737. cnss_pr_err("Fail to save fw mem data: %d\n",
  1738. ret);
  1739. break;
  1740. }
  1741. }
  1742. kfree(data);
  1743. return ret;
  1744. invalid_mem_save:
  1745. cnss_pr_err("FW Mem type %d not allocated. Invalid save request\n",
  1746. event_data->mem_type);
  1747. kfree(data);
  1748. return -EINVAL;
  1749. }
  1750. static int cnss_qdss_trace_free_hdlr(struct cnss_plat_data *plat_priv)
  1751. {
  1752. cnss_bus_free_qdss_mem(plat_priv);
  1753. return 0;
  1754. }
  1755. static int cnss_qdss_trace_req_data_hdlr(struct cnss_plat_data *plat_priv,
  1756. void *data)
  1757. {
  1758. int ret = 0;
  1759. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  1760. if (!plat_priv)
  1761. return -ENODEV;
  1762. ret = cnss_wlfw_qdss_data_send_sync(plat_priv, event_data->file_name,
  1763. event_data->total_size);
  1764. kfree(data);
  1765. return ret;
  1766. }
  1767. static void cnss_driver_event_work(struct work_struct *work)
  1768. {
  1769. struct cnss_plat_data *plat_priv =
  1770. container_of(work, struct cnss_plat_data, event_work);
  1771. struct cnss_driver_event *event;
  1772. unsigned long flags;
  1773. int ret = 0;
  1774. if (!plat_priv) {
  1775. cnss_pr_err("plat_priv is NULL!\n");
  1776. return;
  1777. }
  1778. cnss_pm_stay_awake(plat_priv);
  1779. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1780. while (!list_empty(&plat_priv->event_list)) {
  1781. event = list_first_entry(&plat_priv->event_list,
  1782. struct cnss_driver_event, list);
  1783. list_del(&event->list);
  1784. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  1785. cnss_pr_dbg("Processing driver event: %s%s(%d), state: 0x%lx\n",
  1786. cnss_driver_event_to_str(event->type),
  1787. event->sync ? "-sync" : "", event->type,
  1788. plat_priv->driver_state);
  1789. switch (event->type) {
  1790. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  1791. ret = cnss_wlfw_server_arrive(plat_priv, event->data);
  1792. break;
  1793. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  1794. ret = cnss_wlfw_server_exit(plat_priv);
  1795. break;
  1796. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  1797. ret = cnss_bus_alloc_fw_mem(plat_priv);
  1798. if (ret)
  1799. break;
  1800. ret = cnss_wlfw_respond_mem_send_sync(plat_priv);
  1801. break;
  1802. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  1803. ret = cnss_fw_mem_ready_hdlr(plat_priv);
  1804. break;
  1805. case CNSS_DRIVER_EVENT_FW_READY:
  1806. ret = cnss_fw_ready_hdlr(plat_priv);
  1807. break;
  1808. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  1809. ret = cnss_cold_boot_cal_start_hdlr(plat_priv);
  1810. break;
  1811. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  1812. ret = cnss_cold_boot_cal_done_hdlr(plat_priv,
  1813. event->data);
  1814. break;
  1815. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  1816. ret = cnss_bus_register_driver_hdlr(plat_priv,
  1817. event->data);
  1818. break;
  1819. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  1820. ret = cnss_bus_unregister_driver_hdlr(plat_priv);
  1821. break;
  1822. case CNSS_DRIVER_EVENT_RECOVERY:
  1823. ret = cnss_driver_recovery_hdlr(plat_priv,
  1824. event->data);
  1825. break;
  1826. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  1827. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  1828. break;
  1829. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  1830. set_bit(CNSS_DRIVER_IDLE_RESTART,
  1831. &plat_priv->driver_state);
  1832. /* fall through */
  1833. case CNSS_DRIVER_EVENT_POWER_UP:
  1834. ret = cnss_power_up_hdlr(plat_priv);
  1835. break;
  1836. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  1837. set_bit(CNSS_DRIVER_IDLE_SHUTDOWN,
  1838. &plat_priv->driver_state);
  1839. /* fall through */
  1840. case CNSS_DRIVER_EVENT_POWER_DOWN:
  1841. ret = cnss_power_down_hdlr(plat_priv);
  1842. break;
  1843. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  1844. ret = cnss_process_wfc_call_ind_event(plat_priv,
  1845. event->data);
  1846. break;
  1847. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  1848. ret = cnss_process_twt_cfg_ind_event(plat_priv,
  1849. event->data);
  1850. break;
  1851. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  1852. ret = cnss_qdss_trace_req_mem_hdlr(plat_priv);
  1853. break;
  1854. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  1855. ret = cnss_fw_mem_file_save_hdlr(plat_priv,
  1856. event->data);
  1857. break;
  1858. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  1859. ret = cnss_qdss_trace_free_hdlr(plat_priv);
  1860. break;
  1861. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  1862. ret = cnss_qdss_trace_req_data_hdlr(plat_priv,
  1863. event->data);
  1864. break;
  1865. default:
  1866. cnss_pr_err("Invalid driver event type: %d",
  1867. event->type);
  1868. kfree(event);
  1869. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1870. continue;
  1871. }
  1872. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1873. if (event->sync) {
  1874. event->ret = ret;
  1875. complete(&event->complete);
  1876. continue;
  1877. }
  1878. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  1879. kfree(event);
  1880. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1881. }
  1882. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  1883. cnss_pm_relax(plat_priv);
  1884. }
  1885. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1886. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  1887. {
  1888. int ret = 0;
  1889. struct cnss_subsys_info *subsys_info;
  1890. subsys_info = &plat_priv->subsys_info;
  1891. subsys_info->subsys_desc.name = "wlan";
  1892. subsys_info->subsys_desc.owner = THIS_MODULE;
  1893. subsys_info->subsys_desc.powerup = cnss_subsys_powerup;
  1894. subsys_info->subsys_desc.shutdown = cnss_subsys_shutdown;
  1895. subsys_info->subsys_desc.ramdump = cnss_subsys_ramdump;
  1896. subsys_info->subsys_desc.crash_shutdown = cnss_subsys_crash_shutdown;
  1897. subsys_info->subsys_desc.dev = &plat_priv->plat_dev->dev;
  1898. subsys_info->subsys_device = subsys_register(&subsys_info->subsys_desc);
  1899. if (IS_ERR(subsys_info->subsys_device)) {
  1900. ret = PTR_ERR(subsys_info->subsys_device);
  1901. cnss_pr_err("Failed to register subsys, err = %d\n", ret);
  1902. goto out;
  1903. }
  1904. subsys_info->subsys_handle =
  1905. subsystem_get(subsys_info->subsys_desc.name);
  1906. if (!subsys_info->subsys_handle) {
  1907. cnss_pr_err("Failed to get subsys_handle!\n");
  1908. ret = -EINVAL;
  1909. goto unregister_subsys;
  1910. } else if (IS_ERR(subsys_info->subsys_handle)) {
  1911. ret = PTR_ERR(subsys_info->subsys_handle);
  1912. cnss_pr_err("Failed to do subsystem_get, err = %d\n", ret);
  1913. goto unregister_subsys;
  1914. }
  1915. return 0;
  1916. unregister_subsys:
  1917. subsys_unregister(subsys_info->subsys_device);
  1918. out:
  1919. return ret;
  1920. }
  1921. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  1922. {
  1923. struct cnss_subsys_info *subsys_info;
  1924. subsys_info = &plat_priv->subsys_info;
  1925. subsystem_put(subsys_info->subsys_handle);
  1926. subsys_unregister(subsys_info->subsys_device);
  1927. }
  1928. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  1929. {
  1930. struct cnss_subsys_info *subsys_info = &plat_priv->subsys_info;
  1931. return create_ramdump_device(subsys_info->subsys_desc.name,
  1932. subsys_info->subsys_desc.dev);
  1933. }
  1934. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  1935. void *ramdump_dev)
  1936. {
  1937. destroy_ramdump_device(ramdump_dev);
  1938. }
  1939. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  1940. {
  1941. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  1942. struct ramdump_segment segment;
  1943. memset(&segment, 0, sizeof(segment));
  1944. segment.v_address = (void __iomem *)ramdump_info->ramdump_va;
  1945. segment.size = ramdump_info->ramdump_size;
  1946. return qcom_ramdump(ramdump_info->ramdump_dev, &segment, 1);
  1947. }
  1948. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  1949. {
  1950. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  1951. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  1952. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  1953. struct ramdump_segment *ramdump_segs, *s;
  1954. struct cnss_dump_meta_info meta_info = {0};
  1955. int i, ret = 0;
  1956. ramdump_segs = kcalloc(dump_data->nentries + 1,
  1957. sizeof(*ramdump_segs),
  1958. GFP_KERNEL);
  1959. if (!ramdump_segs)
  1960. return -ENOMEM;
  1961. s = ramdump_segs + 1;
  1962. for (i = 0; i < dump_data->nentries; i++) {
  1963. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  1964. cnss_pr_err("Unsupported dump type: %d",
  1965. dump_seg->type);
  1966. continue;
  1967. }
  1968. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  1969. meta_info.entry[dump_seg->type].type = dump_seg->type;
  1970. meta_info.entry[dump_seg->type].entry_start = i + 1;
  1971. }
  1972. meta_info.entry[dump_seg->type].entry_num++;
  1973. s->address = dump_seg->address;
  1974. s->v_address = (void __iomem *)dump_seg->v_address;
  1975. s->size = dump_seg->size;
  1976. s++;
  1977. dump_seg++;
  1978. }
  1979. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  1980. meta_info.version = CNSS_RAMDUMP_VERSION;
  1981. meta_info.chipset = plat_priv->device_id;
  1982. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  1983. ramdump_segs->v_address = (void __iomem *)(&meta_info);
  1984. ramdump_segs->size = sizeof(meta_info);
  1985. ret = qcom_elf_ramdump(info_v2->ramdump_dev, ramdump_segs,
  1986. dump_data->nentries + 1);
  1987. kfree(ramdump_segs);
  1988. return ret;
  1989. }
  1990. #else
  1991. static int cnss_panic_handler(struct notifier_block *nb, unsigned long action,
  1992. void *data)
  1993. {
  1994. struct cnss_plat_data *plat_priv =
  1995. container_of(nb, struct cnss_plat_data, panic_nb);
  1996. cnss_bus_dev_crash_shutdown(plat_priv);
  1997. return NOTIFY_DONE;
  1998. }
  1999. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  2000. {
  2001. int ret;
  2002. if (!plat_priv)
  2003. return -ENODEV;
  2004. plat_priv->panic_nb.notifier_call = cnss_panic_handler;
  2005. ret = atomic_notifier_chain_register(&panic_notifier_list,
  2006. &plat_priv->panic_nb);
  2007. if (ret) {
  2008. cnss_pr_err("Failed to register panic handler\n");
  2009. return -EINVAL;
  2010. }
  2011. return 0;
  2012. }
  2013. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  2014. {
  2015. int ret;
  2016. ret = atomic_notifier_chain_unregister(&panic_notifier_list,
  2017. &plat_priv->panic_nb);
  2018. if (ret)
  2019. cnss_pr_err("Failed to unregister panic handler\n");
  2020. }
  2021. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  2022. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  2023. {
  2024. return &plat_priv->plat_dev->dev;
  2025. }
  2026. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  2027. void *ramdump_dev)
  2028. {
  2029. }
  2030. #endif
  2031. #if IS_ENABLED(CONFIG_QCOM_RAMDUMP)
  2032. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2033. {
  2034. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  2035. struct qcom_dump_segment segment;
  2036. struct list_head head;
  2037. INIT_LIST_HEAD(&head);
  2038. memset(&segment, 0, sizeof(segment));
  2039. segment.va = ramdump_info->ramdump_va;
  2040. segment.size = ramdump_info->ramdump_size;
  2041. list_add(&segment.node, &head);
  2042. return qcom_dump(&head, ramdump_info->ramdump_dev);
  2043. }
  2044. #else
  2045. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2046. {
  2047. return 0;
  2048. }
  2049. /* Using completion event inside dynamically allocated ramdump_desc
  2050. * may result a race between freeing the event after setting it to
  2051. * complete inside dev coredump free callback and the thread that is
  2052. * waiting for completion.
  2053. */
  2054. DECLARE_COMPLETION(dump_done);
  2055. #define TIMEOUT_SAVE_DUMP_MS 30000
  2056. #define SIZEOF_ELF_STRUCT(__xhdr) \
  2057. static inline size_t sizeof_elf_##__xhdr(unsigned char class) \
  2058. { \
  2059. if (class == ELFCLASS32) \
  2060. return sizeof(struct elf32_##__xhdr); \
  2061. else \
  2062. return sizeof(struct elf64_##__xhdr); \
  2063. }
  2064. SIZEOF_ELF_STRUCT(phdr)
  2065. SIZEOF_ELF_STRUCT(hdr)
  2066. #define set_xhdr_property(__xhdr, arg, class, member, value) \
  2067. do { \
  2068. if (class == ELFCLASS32) \
  2069. ((struct elf32_##__xhdr *)arg)->member = value; \
  2070. else \
  2071. ((struct elf64_##__xhdr *)arg)->member = value; \
  2072. } while (0)
  2073. #define set_ehdr_property(arg, class, member, value) \
  2074. set_xhdr_property(hdr, arg, class, member, value)
  2075. #define set_phdr_property(arg, class, member, value) \
  2076. set_xhdr_property(phdr, arg, class, member, value)
  2077. /* These replace qcom_ramdump driver APIs called from common API
  2078. * cnss_do_elf_dump() by the ones defined here.
  2079. */
  2080. #define qcom_dump_segment cnss_qcom_dump_segment
  2081. #define qcom_elf_dump cnss_qcom_elf_dump
  2082. #define dump_enabled cnss_dump_enabled
  2083. struct cnss_qcom_dump_segment {
  2084. struct list_head node;
  2085. dma_addr_t da;
  2086. void *va;
  2087. size_t size;
  2088. };
  2089. struct cnss_qcom_ramdump_desc {
  2090. void *data;
  2091. struct completion dump_done;
  2092. };
  2093. static ssize_t cnss_qcom_devcd_readv(char *buffer, loff_t offset, size_t count,
  2094. void *data, size_t datalen)
  2095. {
  2096. struct cnss_qcom_ramdump_desc *desc = data;
  2097. return memory_read_from_buffer(buffer, count, &offset, desc->data,
  2098. datalen);
  2099. }
  2100. static void cnss_qcom_devcd_freev(void *data)
  2101. {
  2102. struct cnss_qcom_ramdump_desc *desc = data;
  2103. cnss_pr_dbg("Free dump data for dev coredump\n");
  2104. complete(&dump_done);
  2105. vfree(desc->data);
  2106. kfree(desc);
  2107. }
  2108. static int cnss_qcom_devcd_dump(struct device *dev, void *data, size_t datalen,
  2109. gfp_t gfp)
  2110. {
  2111. struct cnss_qcom_ramdump_desc *desc;
  2112. unsigned int timeout = TIMEOUT_SAVE_DUMP_MS;
  2113. int ret;
  2114. desc = kmalloc(sizeof(*desc), GFP_KERNEL);
  2115. if (!desc)
  2116. return -ENOMEM;
  2117. desc->data = data;
  2118. reinit_completion(&dump_done);
  2119. dev_coredumpm(dev, NULL, desc, datalen, gfp,
  2120. cnss_qcom_devcd_readv, cnss_qcom_devcd_freev);
  2121. ret = wait_for_completion_timeout(&dump_done,
  2122. msecs_to_jiffies(timeout));
  2123. if (!ret)
  2124. cnss_pr_err("Timeout waiting (%dms) for saving dump to file system\n",
  2125. timeout);
  2126. return ret ? 0 : -ETIMEDOUT;
  2127. }
  2128. /* Since the elf32 and elf64 identification is identical apart from
  2129. * the class, use elf32 by default.
  2130. */
  2131. static void init_elf_identification(struct elf32_hdr *ehdr, unsigned char class)
  2132. {
  2133. memcpy(ehdr->e_ident, ELFMAG, SELFMAG);
  2134. ehdr->e_ident[EI_CLASS] = class;
  2135. ehdr->e_ident[EI_DATA] = ELFDATA2LSB;
  2136. ehdr->e_ident[EI_VERSION] = EV_CURRENT;
  2137. ehdr->e_ident[EI_OSABI] = ELFOSABI_NONE;
  2138. }
  2139. int cnss_qcom_elf_dump(struct list_head *segs, struct device *dev,
  2140. unsigned char class)
  2141. {
  2142. struct cnss_qcom_dump_segment *segment;
  2143. void *phdr, *ehdr;
  2144. size_t data_size, offset;
  2145. int phnum = 0;
  2146. void *data;
  2147. void __iomem *ptr;
  2148. if (!segs || list_empty(segs))
  2149. return -EINVAL;
  2150. data_size = sizeof_elf_hdr(class);
  2151. list_for_each_entry(segment, segs, node) {
  2152. data_size += sizeof_elf_phdr(class) + segment->size;
  2153. phnum++;
  2154. }
  2155. data = vmalloc(data_size);
  2156. if (!data)
  2157. return -ENOMEM;
  2158. cnss_pr_dbg("Creating ELF file with size %d\n", data_size);
  2159. ehdr = data;
  2160. memset(ehdr, 0, sizeof_elf_hdr(class));
  2161. init_elf_identification(ehdr, class);
  2162. set_ehdr_property(ehdr, class, e_type, ET_CORE);
  2163. set_ehdr_property(ehdr, class, e_machine, EM_NONE);
  2164. set_ehdr_property(ehdr, class, e_version, EV_CURRENT);
  2165. set_ehdr_property(ehdr, class, e_phoff, sizeof_elf_hdr(class));
  2166. set_ehdr_property(ehdr, class, e_ehsize, sizeof_elf_hdr(class));
  2167. set_ehdr_property(ehdr, class, e_phentsize, sizeof_elf_phdr(class));
  2168. set_ehdr_property(ehdr, class, e_phnum, phnum);
  2169. phdr = data + sizeof_elf_hdr(class);
  2170. offset = sizeof_elf_hdr(class) + sizeof_elf_phdr(class) * phnum;
  2171. list_for_each_entry(segment, segs, node) {
  2172. memset(phdr, 0, sizeof_elf_phdr(class));
  2173. set_phdr_property(phdr, class, p_type, PT_LOAD);
  2174. set_phdr_property(phdr, class, p_offset, offset);
  2175. set_phdr_property(phdr, class, p_vaddr, segment->da);
  2176. set_phdr_property(phdr, class, p_paddr, segment->da);
  2177. set_phdr_property(phdr, class, p_filesz, segment->size);
  2178. set_phdr_property(phdr, class, p_memsz, segment->size);
  2179. set_phdr_property(phdr, class, p_flags, PF_R | PF_W | PF_X);
  2180. set_phdr_property(phdr, class, p_align, 0);
  2181. if (segment->va) {
  2182. memcpy(data + offset, segment->va, segment->size);
  2183. } else {
  2184. ptr = devm_ioremap(dev, segment->da, segment->size);
  2185. if (!ptr) {
  2186. cnss_pr_err("Invalid coredump segment (%pad, %zu)\n",
  2187. &segment->da, segment->size);
  2188. memset(data + offset, 0xff, segment->size);
  2189. } else {
  2190. memcpy_fromio(data + offset, ptr,
  2191. segment->size);
  2192. }
  2193. }
  2194. offset += segment->size;
  2195. phdr += sizeof_elf_phdr(class);
  2196. }
  2197. return cnss_qcom_devcd_dump(dev, data, data_size, GFP_KERNEL);
  2198. }
  2199. /* Saving dump to file system is always needed in this case. */
  2200. static bool cnss_dump_enabled(void)
  2201. {
  2202. return true;
  2203. }
  2204. #endif /* CONFIG_QCOM_RAMDUMP */
  2205. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  2206. {
  2207. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2208. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  2209. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  2210. struct qcom_dump_segment *seg;
  2211. struct cnss_dump_meta_info meta_info = {0};
  2212. struct list_head head;
  2213. int i, ret = 0;
  2214. if (!dump_enabled()) {
  2215. cnss_pr_info("Dump collection is not enabled\n");
  2216. return ret;
  2217. }
  2218. INIT_LIST_HEAD(&head);
  2219. for (i = 0; i < dump_data->nentries; i++) {
  2220. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  2221. cnss_pr_err("Unsupported dump type: %d",
  2222. dump_seg->type);
  2223. continue;
  2224. }
  2225. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2226. if (!seg)
  2227. continue;
  2228. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  2229. meta_info.entry[dump_seg->type].type = dump_seg->type;
  2230. meta_info.entry[dump_seg->type].entry_start = i + 1;
  2231. }
  2232. meta_info.entry[dump_seg->type].entry_num++;
  2233. seg->da = dump_seg->address;
  2234. seg->va = dump_seg->v_address;
  2235. seg->size = dump_seg->size;
  2236. list_add_tail(&seg->node, &head);
  2237. dump_seg++;
  2238. }
  2239. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2240. if (!seg)
  2241. goto do_elf_dump;
  2242. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  2243. meta_info.version = CNSS_RAMDUMP_VERSION;
  2244. meta_info.chipset = plat_priv->device_id;
  2245. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  2246. seg->va = &meta_info;
  2247. seg->size = sizeof(meta_info);
  2248. list_add(&seg->node, &head);
  2249. do_elf_dump:
  2250. ret = qcom_elf_dump(&head, info_v2->ramdump_dev, ELF_CLASS);
  2251. while (!list_empty(&head)) {
  2252. seg = list_first_entry(&head, struct qcom_dump_segment, node);
  2253. list_del(&seg->node);
  2254. kfree(seg);
  2255. }
  2256. return ret;
  2257. }
  2258. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  2259. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  2260. static int cnss_init_dump_entry(struct cnss_plat_data *plat_priv)
  2261. {
  2262. struct cnss_ramdump_info *ramdump_info;
  2263. struct msm_dump_entry dump_entry;
  2264. ramdump_info = &plat_priv->ramdump_info;
  2265. ramdump_info->dump_data.addr = ramdump_info->ramdump_pa;
  2266. ramdump_info->dump_data.len = ramdump_info->ramdump_size;
  2267. ramdump_info->dump_data.version = CNSS_DUMP_FORMAT_VER;
  2268. ramdump_info->dump_data.magic = CNSS_DUMP_MAGIC_VER_V2;
  2269. strlcpy(ramdump_info->dump_data.name, CNSS_DUMP_NAME,
  2270. sizeof(ramdump_info->dump_data.name));
  2271. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2272. dump_entry.addr = virt_to_phys(&ramdump_info->dump_data);
  2273. return msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  2274. &dump_entry);
  2275. }
  2276. static int cnss_register_ramdump_v1(struct cnss_plat_data *plat_priv)
  2277. {
  2278. int ret = 0;
  2279. struct device *dev;
  2280. struct cnss_ramdump_info *ramdump_info;
  2281. u32 ramdump_size = 0;
  2282. dev = &plat_priv->plat_dev->dev;
  2283. ramdump_info = &plat_priv->ramdump_info;
  2284. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  2285. &ramdump_size) == 0) {
  2286. ramdump_info->ramdump_va =
  2287. dma_alloc_coherent(dev, ramdump_size,
  2288. &ramdump_info->ramdump_pa,
  2289. GFP_KERNEL);
  2290. if (ramdump_info->ramdump_va)
  2291. ramdump_info->ramdump_size = ramdump_size;
  2292. }
  2293. cnss_pr_dbg("ramdump va: %pK, pa: %pa\n",
  2294. ramdump_info->ramdump_va, &ramdump_info->ramdump_pa);
  2295. if (ramdump_info->ramdump_size == 0) {
  2296. cnss_pr_info("Ramdump will not be collected");
  2297. goto out;
  2298. }
  2299. ret = cnss_init_dump_entry(plat_priv);
  2300. if (ret) {
  2301. cnss_pr_err("Failed to setup dump table, err = %d\n", ret);
  2302. goto free_ramdump;
  2303. }
  2304. ramdump_info->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  2305. if (!ramdump_info->ramdump_dev) {
  2306. cnss_pr_err("Failed to create ramdump device!");
  2307. ret = -ENOMEM;
  2308. goto free_ramdump;
  2309. }
  2310. return 0;
  2311. free_ramdump:
  2312. dma_free_coherent(dev, ramdump_info->ramdump_size,
  2313. ramdump_info->ramdump_va, ramdump_info->ramdump_pa);
  2314. out:
  2315. return ret;
  2316. }
  2317. static void cnss_unregister_ramdump_v1(struct cnss_plat_data *plat_priv)
  2318. {
  2319. struct device *dev;
  2320. struct cnss_ramdump_info *ramdump_info;
  2321. dev = &plat_priv->plat_dev->dev;
  2322. ramdump_info = &plat_priv->ramdump_info;
  2323. if (ramdump_info->ramdump_dev)
  2324. cnss_destroy_ramdump_device(plat_priv,
  2325. ramdump_info->ramdump_dev);
  2326. if (ramdump_info->ramdump_va)
  2327. dma_free_coherent(dev, ramdump_info->ramdump_size,
  2328. ramdump_info->ramdump_va,
  2329. ramdump_info->ramdump_pa);
  2330. }
  2331. /**
  2332. * cnss_ignore_dump_data_reg_fail - Ignore Ramdump table register failure
  2333. * @ret: Error returned by msm_dump_data_register_nominidump
  2334. *
  2335. * For Lahaina GKI boot, we dont have support for mem dump feature. So
  2336. * ignore failure.
  2337. *
  2338. * Return: Same given error code if mem dump feature enabled, 0 otherwise
  2339. */
  2340. static int cnss_ignore_dump_data_reg_fail(int ret)
  2341. {
  2342. return ret;
  2343. }
  2344. static int cnss_register_ramdump_v2(struct cnss_plat_data *plat_priv)
  2345. {
  2346. int ret = 0;
  2347. struct cnss_ramdump_info_v2 *info_v2;
  2348. struct cnss_dump_data *dump_data;
  2349. struct msm_dump_entry dump_entry;
  2350. struct device *dev = &plat_priv->plat_dev->dev;
  2351. u32 ramdump_size = 0;
  2352. info_v2 = &plat_priv->ramdump_info_v2;
  2353. dump_data = &info_v2->dump_data;
  2354. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  2355. &ramdump_size) == 0)
  2356. info_v2->ramdump_size = ramdump_size;
  2357. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  2358. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  2359. if (!info_v2->dump_data_vaddr)
  2360. return -ENOMEM;
  2361. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  2362. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  2363. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  2364. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  2365. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  2366. sizeof(dump_data->name));
  2367. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2368. dump_entry.addr = virt_to_phys(dump_data);
  2369. ret = msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  2370. &dump_entry);
  2371. if (ret) {
  2372. ret = cnss_ignore_dump_data_reg_fail(ret);
  2373. cnss_pr_err("Failed to setup dump table, %s (%d)\n",
  2374. ret ? "Error" : "Ignoring", ret);
  2375. goto free_ramdump;
  2376. }
  2377. info_v2->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  2378. if (!info_v2->ramdump_dev) {
  2379. cnss_pr_err("Failed to create ramdump device!\n");
  2380. ret = -ENOMEM;
  2381. goto free_ramdump;
  2382. }
  2383. return 0;
  2384. free_ramdump:
  2385. kfree(info_v2->dump_data_vaddr);
  2386. info_v2->dump_data_vaddr = NULL;
  2387. return ret;
  2388. }
  2389. static void cnss_unregister_ramdump_v2(struct cnss_plat_data *plat_priv)
  2390. {
  2391. struct cnss_ramdump_info_v2 *info_v2;
  2392. info_v2 = &plat_priv->ramdump_info_v2;
  2393. if (info_v2->ramdump_dev)
  2394. cnss_destroy_ramdump_device(plat_priv, info_v2->ramdump_dev);
  2395. kfree(info_v2->dump_data_vaddr);
  2396. info_v2->dump_data_vaddr = NULL;
  2397. info_v2->dump_data_valid = false;
  2398. }
  2399. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  2400. {
  2401. int ret = 0;
  2402. switch (plat_priv->device_id) {
  2403. case QCA6174_DEVICE_ID:
  2404. ret = cnss_register_ramdump_v1(plat_priv);
  2405. break;
  2406. case QCA6290_DEVICE_ID:
  2407. case QCA6390_DEVICE_ID:
  2408. case QCA6490_DEVICE_ID:
  2409. case KIWI_DEVICE_ID:
  2410. ret = cnss_register_ramdump_v2(plat_priv);
  2411. break;
  2412. default:
  2413. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  2414. ret = -ENODEV;
  2415. break;
  2416. }
  2417. return ret;
  2418. }
  2419. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  2420. {
  2421. switch (plat_priv->device_id) {
  2422. case QCA6174_DEVICE_ID:
  2423. cnss_unregister_ramdump_v1(plat_priv);
  2424. break;
  2425. case QCA6290_DEVICE_ID:
  2426. case QCA6390_DEVICE_ID:
  2427. case QCA6490_DEVICE_ID:
  2428. case KIWI_DEVICE_ID:
  2429. cnss_unregister_ramdump_v2(plat_priv);
  2430. break;
  2431. default:
  2432. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  2433. break;
  2434. }
  2435. }
  2436. #else
  2437. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  2438. {
  2439. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2440. struct cnss_dump_data *dump_data = dump_data = &info_v2->dump_data;
  2441. struct device *dev = &plat_priv->plat_dev->dev;
  2442. u32 ramdump_size = 0;
  2443. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  2444. &ramdump_size) == 0)
  2445. info_v2->ramdump_size = ramdump_size;
  2446. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  2447. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  2448. if (!info_v2->dump_data_vaddr)
  2449. return -ENOMEM;
  2450. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  2451. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  2452. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  2453. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  2454. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  2455. sizeof(dump_data->name));
  2456. info_v2->ramdump_dev = dev;
  2457. return 0;
  2458. }
  2459. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  2460. {
  2461. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2462. info_v2->ramdump_dev = NULL;
  2463. kfree(info_v2->dump_data_vaddr);
  2464. info_v2->dump_data_vaddr = NULL;
  2465. info_v2->dump_data_valid = false;
  2466. }
  2467. #endif /* CONFIG_QCOM_MEMORY_DUMP_V2 */
  2468. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  2469. int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
  2470. phys_addr_t *pa, unsigned long attrs)
  2471. {
  2472. struct sg_table sgt;
  2473. int ret;
  2474. ret = dma_get_sgtable_attrs(dev, &sgt, va, dma, size, attrs);
  2475. if (ret) {
  2476. cnss_pr_err("Failed to get sgtable for va: 0x%pK, dma: %pa, size: 0x%zx, attrs: 0x%x\n",
  2477. va, &dma, size, attrs);
  2478. return -EINVAL;
  2479. }
  2480. *pa = page_to_phys(sg_page(sgt.sgl));
  2481. sg_free_table(&sgt);
  2482. return 0;
  2483. }
  2484. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  2485. enum cnss_fw_dump_type type, int seg_no,
  2486. void *va, phys_addr_t pa, size_t size)
  2487. {
  2488. struct md_region md_entry;
  2489. int ret;
  2490. switch (type) {
  2491. case CNSS_FW_IMAGE:
  2492. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  2493. seg_no);
  2494. break;
  2495. case CNSS_FW_RDDM:
  2496. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  2497. seg_no);
  2498. break;
  2499. case CNSS_FW_REMOTE_HEAP:
  2500. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  2501. seg_no);
  2502. break;
  2503. default:
  2504. cnss_pr_err("Unknown dump type ID: %d\n", type);
  2505. return -EINVAL;
  2506. }
  2507. md_entry.phys_addr = pa;
  2508. md_entry.virt_addr = (uintptr_t)va;
  2509. md_entry.size = size;
  2510. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2511. cnss_pr_dbg("Mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  2512. md_entry.name, va, &pa, size);
  2513. ret = msm_minidump_add_region(&md_entry);
  2514. if (ret < 0)
  2515. cnss_pr_err("Failed to add mini dump region, err = %d\n", ret);
  2516. return ret;
  2517. }
  2518. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  2519. enum cnss_fw_dump_type type, int seg_no,
  2520. void *va, phys_addr_t pa, size_t size)
  2521. {
  2522. struct md_region md_entry;
  2523. int ret;
  2524. switch (type) {
  2525. case CNSS_FW_IMAGE:
  2526. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  2527. seg_no);
  2528. break;
  2529. case CNSS_FW_RDDM:
  2530. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  2531. seg_no);
  2532. break;
  2533. case CNSS_FW_REMOTE_HEAP:
  2534. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  2535. seg_no);
  2536. break;
  2537. default:
  2538. cnss_pr_err("Unknown dump type ID: %d\n", type);
  2539. return -EINVAL;
  2540. }
  2541. md_entry.phys_addr = pa;
  2542. md_entry.virt_addr = (uintptr_t)va;
  2543. md_entry.size = size;
  2544. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2545. cnss_pr_dbg("Remove mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  2546. md_entry.name, va, &pa, size);
  2547. ret = msm_minidump_remove_region(&md_entry);
  2548. if (ret)
  2549. cnss_pr_err("Failed to remove mini dump region, err = %d\n",
  2550. ret);
  2551. return ret;
  2552. }
  2553. #else
  2554. int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
  2555. phys_addr_t *pa, unsigned long attrs)
  2556. {
  2557. return 0;
  2558. }
  2559. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  2560. enum cnss_fw_dump_type type, int seg_no,
  2561. void *va, phys_addr_t pa, size_t size)
  2562. {
  2563. return 0;
  2564. }
  2565. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  2566. enum cnss_fw_dump_type type, int seg_no,
  2567. void *va, phys_addr_t pa, size_t size)
  2568. {
  2569. return 0;
  2570. }
  2571. #endif /* CONFIG_QCOM_MINIDUMP */
  2572. int cnss_request_firmware_direct(struct cnss_plat_data *plat_priv,
  2573. const struct firmware **fw_entry,
  2574. const char *filename)
  2575. {
  2576. if (IS_ENABLED(CONFIG_CNSS_REQ_FW_DIRECT))
  2577. return request_firmware_direct(fw_entry, filename,
  2578. &plat_priv->plat_dev->dev);
  2579. else
  2580. return firmware_request_nowarn(fw_entry, filename,
  2581. &plat_priv->plat_dev->dev);
  2582. }
  2583. #if IS_ENABLED(CONFIG_INTERCONNECT)
  2584. /**
  2585. * cnss_register_bus_scale() - Setup interconnect voting data
  2586. * @plat_priv: Platform data structure
  2587. *
  2588. * For different interconnect path configured in device tree setup voting data
  2589. * for list of bandwidth requirements.
  2590. *
  2591. * Result: 0 for success. -EINVAL if not configured
  2592. */
  2593. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  2594. {
  2595. int ret = -EINVAL;
  2596. u32 idx, i, j, cfg_arr_size, *cfg_arr = NULL;
  2597. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  2598. struct device *dev = &plat_priv->plat_dev->dev;
  2599. INIT_LIST_HEAD(&plat_priv->icc.list_head);
  2600. ret = of_property_read_u32(dev->of_node,
  2601. "qcom,icc-path-count",
  2602. &plat_priv->icc.path_count);
  2603. if (ret) {
  2604. cnss_pr_dbg("Platform Bus Interconnect path not configured\n");
  2605. return 0;
  2606. }
  2607. ret = of_property_read_u32(plat_priv->plat_dev->dev.of_node,
  2608. "qcom,bus-bw-cfg-count",
  2609. &plat_priv->icc.bus_bw_cfg_count);
  2610. if (ret) {
  2611. cnss_pr_err("Failed to get Bus BW Config table size\n");
  2612. goto cleanup;
  2613. }
  2614. cfg_arr_size = plat_priv->icc.path_count *
  2615. plat_priv->icc.bus_bw_cfg_count * CNSS_ICC_VOTE_MAX;
  2616. cfg_arr = kcalloc(cfg_arr_size, sizeof(*cfg_arr), GFP_KERNEL);
  2617. if (!cfg_arr) {
  2618. cnss_pr_err("Failed to alloc cfg table mem\n");
  2619. ret = -ENOMEM;
  2620. goto cleanup;
  2621. }
  2622. ret = of_property_read_u32_array(plat_priv->plat_dev->dev.of_node,
  2623. "qcom,bus-bw-cfg", cfg_arr,
  2624. cfg_arr_size);
  2625. if (ret) {
  2626. cnss_pr_err("Invalid Bus BW Config Table\n");
  2627. goto cleanup;
  2628. }
  2629. cnss_pr_dbg("ICC Path_Count: %d BW_CFG_Count: %d\n",
  2630. plat_priv->icc.path_count, plat_priv->icc.bus_bw_cfg_count);
  2631. for (idx = 0; idx < plat_priv->icc.path_count; idx++) {
  2632. bus_bw_info = devm_kzalloc(dev, sizeof(*bus_bw_info),
  2633. GFP_KERNEL);
  2634. if (!bus_bw_info) {
  2635. ret = -ENOMEM;
  2636. goto out;
  2637. }
  2638. ret = of_property_read_string_index(dev->of_node,
  2639. "interconnect-names", idx,
  2640. &bus_bw_info->icc_name);
  2641. if (ret)
  2642. goto out;
  2643. bus_bw_info->icc_path =
  2644. of_icc_get(&plat_priv->plat_dev->dev,
  2645. bus_bw_info->icc_name);
  2646. if (IS_ERR(bus_bw_info->icc_path)) {
  2647. ret = PTR_ERR(bus_bw_info->icc_path);
  2648. if (ret != -EPROBE_DEFER) {
  2649. cnss_pr_err("Failed to get Interconnect path for %s. Err: %d\n",
  2650. bus_bw_info->icc_name, ret);
  2651. goto out;
  2652. }
  2653. }
  2654. bus_bw_info->cfg_table =
  2655. devm_kcalloc(dev, plat_priv->icc.bus_bw_cfg_count,
  2656. sizeof(*bus_bw_info->cfg_table),
  2657. GFP_KERNEL);
  2658. if (!bus_bw_info->cfg_table) {
  2659. ret = -ENOMEM;
  2660. goto out;
  2661. }
  2662. cnss_pr_dbg("ICC Vote CFG for path: %s\n",
  2663. bus_bw_info->icc_name);
  2664. for (i = 0, j = (idx * plat_priv->icc.bus_bw_cfg_count *
  2665. CNSS_ICC_VOTE_MAX);
  2666. i < plat_priv->icc.bus_bw_cfg_count;
  2667. i++, j += 2) {
  2668. bus_bw_info->cfg_table[i].avg_bw = cfg_arr[j];
  2669. bus_bw_info->cfg_table[i].peak_bw = cfg_arr[j + 1];
  2670. cnss_pr_dbg("ICC Vote BW: %d avg: %d peak: %d\n",
  2671. i, bus_bw_info->cfg_table[i].avg_bw,
  2672. bus_bw_info->cfg_table[i].peak_bw);
  2673. }
  2674. list_add_tail(&bus_bw_info->list,
  2675. &plat_priv->icc.list_head);
  2676. }
  2677. kfree(cfg_arr);
  2678. return 0;
  2679. out:
  2680. list_for_each_entry_safe(bus_bw_info, tmp,
  2681. &plat_priv->icc.list_head, list) {
  2682. list_del(&bus_bw_info->list);
  2683. }
  2684. cleanup:
  2685. kfree(cfg_arr);
  2686. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  2687. return ret;
  2688. }
  2689. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv)
  2690. {
  2691. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  2692. list_for_each_entry_safe(bus_bw_info, tmp,
  2693. &plat_priv->icc.list_head, list) {
  2694. list_del(&bus_bw_info->list);
  2695. if (bus_bw_info->icc_path)
  2696. icc_put(bus_bw_info->icc_path);
  2697. }
  2698. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  2699. }
  2700. #else
  2701. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  2702. {
  2703. return 0;
  2704. }
  2705. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv) {}
  2706. #endif /* CONFIG_INTERCONNECT */
  2707. void cnss_daemon_connection_update_cb(void *cb_ctx, bool status)
  2708. {
  2709. struct cnss_plat_data *plat_priv = cb_ctx;
  2710. if (!plat_priv) {
  2711. cnss_pr_err("%s: Invalid context\n", __func__);
  2712. return;
  2713. }
  2714. if (status) {
  2715. cnss_pr_info("CNSS Daemon connected\n");
  2716. set_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  2717. complete(&plat_priv->daemon_connected);
  2718. } else {
  2719. cnss_pr_info("CNSS Daemon disconnected\n");
  2720. reinit_completion(&plat_priv->daemon_connected);
  2721. clear_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  2722. }
  2723. }
  2724. static ssize_t enable_hds_store(struct device *dev,
  2725. struct device_attribute *attr,
  2726. const char *buf, size_t count)
  2727. {
  2728. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2729. unsigned int enable_hds = 0;
  2730. if (!plat_priv)
  2731. return -ENODEV;
  2732. if (sscanf(buf, "%du", &enable_hds) != 1) {
  2733. cnss_pr_err("Invalid enable_hds sysfs command\n");
  2734. return -EINVAL;
  2735. }
  2736. if (enable_hds)
  2737. plat_priv->hds_enabled = true;
  2738. else
  2739. plat_priv->hds_enabled = false;
  2740. cnss_pr_dbg("%s HDS file download, count is %zu\n",
  2741. plat_priv->hds_enabled ? "Enable" : "Disable", count);
  2742. return count;
  2743. }
  2744. static ssize_t recovery_store(struct device *dev,
  2745. struct device_attribute *attr,
  2746. const char *buf, size_t count)
  2747. {
  2748. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2749. unsigned int recovery = 0;
  2750. if (!plat_priv)
  2751. return -ENODEV;
  2752. if (sscanf(buf, "%du", &recovery) != 1) {
  2753. cnss_pr_err("Invalid recovery sysfs command\n");
  2754. return -EINVAL;
  2755. }
  2756. if (recovery)
  2757. plat_priv->recovery_enabled = true;
  2758. else
  2759. plat_priv->recovery_enabled = false;
  2760. cnss_pr_dbg("%s WLAN recovery, count is %zu\n",
  2761. plat_priv->recovery_enabled ? "Enable" : "Disable", count);
  2762. return count;
  2763. }
  2764. static ssize_t shutdown_store(struct device *dev,
  2765. struct device_attribute *attr,
  2766. const char *buf, size_t count)
  2767. {
  2768. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2769. if (plat_priv) {
  2770. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  2771. del_timer(&plat_priv->fw_boot_timer);
  2772. complete_all(&plat_priv->power_up_complete);
  2773. complete_all(&plat_priv->cal_complete);
  2774. }
  2775. cnss_pr_dbg("Received shutdown notification\n");
  2776. return count;
  2777. }
  2778. static ssize_t fs_ready_store(struct device *dev,
  2779. struct device_attribute *attr,
  2780. const char *buf, size_t count)
  2781. {
  2782. int fs_ready = 0;
  2783. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2784. if (sscanf(buf, "%du", &fs_ready) != 1)
  2785. return -EINVAL;
  2786. cnss_pr_dbg("File system is ready, fs_ready is %d, count is %zu\n",
  2787. fs_ready, count);
  2788. if (!plat_priv) {
  2789. cnss_pr_err("plat_priv is NULL\n");
  2790. return count;
  2791. }
  2792. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks)) {
  2793. cnss_pr_dbg("QMI is bypassed\n");
  2794. return count;
  2795. }
  2796. switch (plat_priv->device_id) {
  2797. case QCA6290_DEVICE_ID:
  2798. case QCA6390_DEVICE_ID:
  2799. case QCA6490_DEVICE_ID:
  2800. case KIWI_DEVICE_ID:
  2801. break;
  2802. default:
  2803. cnss_pr_err("Not supported for device ID 0x%lx\n",
  2804. plat_priv->device_id);
  2805. return count;
  2806. }
  2807. if (fs_ready == FILE_SYSTEM_READY && plat_priv->cbc_enabled) {
  2808. cnss_driver_event_post(plat_priv,
  2809. CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
  2810. 0, NULL);
  2811. }
  2812. return count;
  2813. }
  2814. static ssize_t qdss_trace_start_store(struct device *dev,
  2815. struct device_attribute *attr,
  2816. const char *buf, size_t count)
  2817. {
  2818. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2819. wlfw_qdss_trace_start(plat_priv);
  2820. cnss_pr_dbg("Received QDSS start command\n");
  2821. return count;
  2822. }
  2823. static ssize_t qdss_trace_stop_store(struct device *dev,
  2824. struct device_attribute *attr,
  2825. const char *buf, size_t count)
  2826. {
  2827. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2828. u32 option = 0;
  2829. if (sscanf(buf, "%du", &option) != 1)
  2830. return -EINVAL;
  2831. wlfw_qdss_trace_stop(plat_priv, option);
  2832. cnss_pr_dbg("Received QDSS stop command\n");
  2833. return count;
  2834. }
  2835. static ssize_t qdss_conf_download_store(struct device *dev,
  2836. struct device_attribute *attr,
  2837. const char *buf, size_t count)
  2838. {
  2839. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2840. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  2841. cnss_pr_dbg("Received QDSS download config command\n");
  2842. return count;
  2843. }
  2844. static ssize_t hw_trace_override_store(struct device *dev,
  2845. struct device_attribute *attr,
  2846. const char *buf, size_t count)
  2847. {
  2848. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2849. int tmp = 0;
  2850. if (sscanf(buf, "%du", &tmp) != 1)
  2851. return -EINVAL;
  2852. plat_priv->hw_trc_override = tmp;
  2853. cnss_pr_dbg("Received QDSS hw_trc_override indication\n");
  2854. return count;
  2855. }
  2856. static ssize_t charger_mode_store(struct device *dev,
  2857. struct device_attribute *attr,
  2858. const char *buf, size_t count)
  2859. {
  2860. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2861. int tmp = 0;
  2862. if (sscanf(buf, "%du", &tmp) != 1)
  2863. return -EINVAL;
  2864. plat_priv->charger_mode = tmp;
  2865. cnss_pr_dbg("Received Charger Mode: %d\n", tmp);
  2866. return count;
  2867. }
  2868. static DEVICE_ATTR_WO(fs_ready);
  2869. static DEVICE_ATTR_WO(shutdown);
  2870. static DEVICE_ATTR_WO(recovery);
  2871. static DEVICE_ATTR_WO(enable_hds);
  2872. static DEVICE_ATTR_WO(qdss_trace_start);
  2873. static DEVICE_ATTR_WO(qdss_trace_stop);
  2874. static DEVICE_ATTR_WO(qdss_conf_download);
  2875. static DEVICE_ATTR_WO(hw_trace_override);
  2876. static DEVICE_ATTR_WO(charger_mode);
  2877. static struct attribute *cnss_attrs[] = {
  2878. &dev_attr_fs_ready.attr,
  2879. &dev_attr_shutdown.attr,
  2880. &dev_attr_recovery.attr,
  2881. &dev_attr_enable_hds.attr,
  2882. &dev_attr_qdss_trace_start.attr,
  2883. &dev_attr_qdss_trace_stop.attr,
  2884. &dev_attr_qdss_conf_download.attr,
  2885. &dev_attr_hw_trace_override.attr,
  2886. &dev_attr_charger_mode.attr,
  2887. NULL,
  2888. };
  2889. static struct attribute_group cnss_attr_group = {
  2890. .attrs = cnss_attrs,
  2891. };
  2892. static int cnss_create_sysfs_link(struct cnss_plat_data *plat_priv)
  2893. {
  2894. struct device *dev = &plat_priv->plat_dev->dev;
  2895. int ret;
  2896. ret = sysfs_create_link(kernel_kobj, &dev->kobj, "cnss");
  2897. if (ret) {
  2898. cnss_pr_err("Failed to create cnss link, err = %d\n",
  2899. ret);
  2900. goto out;
  2901. }
  2902. /* This is only for backward compatibility. */
  2903. ret = sysfs_create_link(kernel_kobj, &dev->kobj, "shutdown_wlan");
  2904. if (ret) {
  2905. cnss_pr_err("Failed to create shutdown_wlan link, err = %d\n",
  2906. ret);
  2907. goto rm_cnss_link;
  2908. }
  2909. return 0;
  2910. rm_cnss_link:
  2911. sysfs_remove_link(kernel_kobj, "cnss");
  2912. out:
  2913. return ret;
  2914. }
  2915. static void cnss_remove_sysfs_link(struct cnss_plat_data *plat_priv)
  2916. {
  2917. sysfs_remove_link(kernel_kobj, "shutdown_wlan");
  2918. sysfs_remove_link(kernel_kobj, "cnss");
  2919. }
  2920. static int cnss_create_sysfs(struct cnss_plat_data *plat_priv)
  2921. {
  2922. int ret = 0;
  2923. ret = devm_device_add_group(&plat_priv->plat_dev->dev,
  2924. &cnss_attr_group);
  2925. if (ret) {
  2926. cnss_pr_err("Failed to create cnss device group, err = %d\n",
  2927. ret);
  2928. goto out;
  2929. }
  2930. cnss_create_sysfs_link(plat_priv);
  2931. return 0;
  2932. out:
  2933. return ret;
  2934. }
  2935. static void cnss_remove_sysfs(struct cnss_plat_data *plat_priv)
  2936. {
  2937. cnss_remove_sysfs_link(plat_priv);
  2938. devm_device_remove_group(&plat_priv->plat_dev->dev, &cnss_attr_group);
  2939. }
  2940. static int cnss_event_work_init(struct cnss_plat_data *plat_priv)
  2941. {
  2942. spin_lock_init(&plat_priv->event_lock);
  2943. plat_priv->event_wq = alloc_workqueue("cnss_driver_event",
  2944. WQ_UNBOUND, 1);
  2945. if (!plat_priv->event_wq) {
  2946. cnss_pr_err("Failed to create event workqueue!\n");
  2947. return -EFAULT;
  2948. }
  2949. INIT_WORK(&plat_priv->event_work, cnss_driver_event_work);
  2950. INIT_LIST_HEAD(&plat_priv->event_list);
  2951. return 0;
  2952. }
  2953. static void cnss_event_work_deinit(struct cnss_plat_data *plat_priv)
  2954. {
  2955. destroy_workqueue(plat_priv->event_wq);
  2956. }
  2957. static int cnss_reboot_notifier(struct notifier_block *nb,
  2958. unsigned long action,
  2959. void *data)
  2960. {
  2961. struct cnss_plat_data *plat_priv =
  2962. container_of(nb, struct cnss_plat_data, reboot_nb);
  2963. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  2964. del_timer(&plat_priv->fw_boot_timer);
  2965. complete_all(&plat_priv->power_up_complete);
  2966. complete_all(&plat_priv->cal_complete);
  2967. cnss_pr_dbg("Reboot is in progress with action %d\n", action);
  2968. return NOTIFY_DONE;
  2969. }
  2970. static int cnss_misc_init(struct cnss_plat_data *plat_priv)
  2971. {
  2972. int ret;
  2973. ret = cnss_init_sol_gpio(plat_priv);
  2974. if (ret)
  2975. return ret;
  2976. timer_setup(&plat_priv->fw_boot_timer,
  2977. cnss_bus_fw_boot_timeout_hdlr, 0);
  2978. ret = register_pm_notifier(&cnss_pm_notifier);
  2979. if (ret)
  2980. cnss_pr_err("Failed to register PM notifier, err = %d\n", ret);
  2981. plat_priv->reboot_nb.notifier_call = cnss_reboot_notifier;
  2982. ret = register_reboot_notifier(&plat_priv->reboot_nb);
  2983. if (ret)
  2984. cnss_pr_err("Failed to register reboot notifier, err = %d\n",
  2985. ret);
  2986. ret = device_init_wakeup(&plat_priv->plat_dev->dev, true);
  2987. if (ret)
  2988. cnss_pr_err("Failed to init platform device wakeup source, err = %d\n",
  2989. ret);
  2990. INIT_WORK(&plat_priv->recovery_work, cnss_recovery_work_handler);
  2991. init_completion(&plat_priv->power_up_complete);
  2992. init_completion(&plat_priv->cal_complete);
  2993. init_completion(&plat_priv->rddm_complete);
  2994. init_completion(&plat_priv->recovery_complete);
  2995. init_completion(&plat_priv->daemon_connected);
  2996. mutex_init(&plat_priv->dev_lock);
  2997. mutex_init(&plat_priv->driver_ops_lock);
  2998. plat_priv->recovery_ws =
  2999. wakeup_source_register(&plat_priv->plat_dev->dev,
  3000. "CNSS_FW_RECOVERY");
  3001. if (!plat_priv->recovery_ws)
  3002. cnss_pr_err("Failed to setup FW recovery wake source\n");
  3003. ret = cnss_plat_ipc_register(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  3004. cnss_daemon_connection_update_cb,
  3005. plat_priv);
  3006. if (ret)
  3007. cnss_pr_err("QMI IPC connection call back register failed, err = %d\n",
  3008. ret);
  3009. return 0;
  3010. }
  3011. static void cnss_misc_deinit(struct cnss_plat_data *plat_priv)
  3012. {
  3013. cnss_plat_ipc_unregister(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  3014. plat_priv);
  3015. complete_all(&plat_priv->recovery_complete);
  3016. complete_all(&plat_priv->rddm_complete);
  3017. complete_all(&plat_priv->cal_complete);
  3018. complete_all(&plat_priv->power_up_complete);
  3019. complete_all(&plat_priv->daemon_connected);
  3020. device_init_wakeup(&plat_priv->plat_dev->dev, false);
  3021. unregister_reboot_notifier(&plat_priv->reboot_nb);
  3022. unregister_pm_notifier(&cnss_pm_notifier);
  3023. del_timer(&plat_priv->fw_boot_timer);
  3024. wakeup_source_unregister(plat_priv->recovery_ws);
  3025. cnss_deinit_sol_gpio(plat_priv);
  3026. }
  3027. static void cnss_init_control_params(struct cnss_plat_data *plat_priv)
  3028. {
  3029. plat_priv->ctrl_params.quirks = CNSS_QUIRKS_DEFAULT;
  3030. plat_priv->cbc_enabled = !IS_ENABLED(CONFIG_CNSS_EMULATION) &&
  3031. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3032. "qcom,wlan-cbc-enabled");
  3033. plat_priv->ctrl_params.mhi_timeout = CNSS_MHI_TIMEOUT_DEFAULT;
  3034. plat_priv->ctrl_params.mhi_m2_timeout = CNSS_MHI_M2_TIMEOUT_DEFAULT;
  3035. plat_priv->ctrl_params.qmi_timeout = CNSS_QMI_TIMEOUT_DEFAULT;
  3036. plat_priv->ctrl_params.bdf_type = CNSS_BDF_TYPE_DEFAULT;
  3037. plat_priv->ctrl_params.time_sync_period = CNSS_TIME_SYNC_PERIOD_DEFAULT;
  3038. /* Set adsp_pc_enabled default value to true as ADSP pc is always
  3039. * enabled by default
  3040. */
  3041. plat_priv->adsp_pc_enabled = true;
  3042. }
  3043. static void cnss_get_pm_domain_info(struct cnss_plat_data *plat_priv)
  3044. {
  3045. struct device *dev = &plat_priv->plat_dev->dev;
  3046. plat_priv->use_pm_domain =
  3047. of_property_read_bool(dev->of_node, "use-pm-domain");
  3048. cnss_pr_dbg("use-pm-domain is %d\n", plat_priv->use_pm_domain);
  3049. }
  3050. static void cnss_get_wlaon_pwr_ctrl_info(struct cnss_plat_data *plat_priv)
  3051. {
  3052. struct device *dev = &plat_priv->plat_dev->dev;
  3053. plat_priv->set_wlaon_pwr_ctrl =
  3054. of_property_read_bool(dev->of_node, "qcom,set-wlaon-pwr-ctrl");
  3055. cnss_pr_dbg("set_wlaon_pwr_ctrl is %d\n",
  3056. plat_priv->set_wlaon_pwr_ctrl);
  3057. }
  3058. static bool cnss_use_fw_path_with_prefix(struct cnss_plat_data *plat_priv)
  3059. {
  3060. return (of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3061. "qcom,converged-dt") ||
  3062. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3063. "qcom,same-dt-multi-dev") ||
  3064. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3065. "qcom,multi-wlan-exchg"));
  3066. }
  3067. static const struct platform_device_id cnss_platform_id_table[] = {
  3068. { .name = "qca6174", .driver_data = QCA6174_DEVICE_ID, },
  3069. { .name = "qca6290", .driver_data = QCA6290_DEVICE_ID, },
  3070. { .name = "qca6390", .driver_data = QCA6390_DEVICE_ID, },
  3071. { .name = "qca6490", .driver_data = QCA6490_DEVICE_ID, },
  3072. { .name = "kiwi", .driver_data = KIWI_DEVICE_ID, },
  3073. { .name = "qcaconv", .driver_data = 0, },
  3074. { },
  3075. };
  3076. static const struct of_device_id cnss_of_match_table[] = {
  3077. {
  3078. .compatible = "qcom,cnss",
  3079. .data = (void *)&cnss_platform_id_table[0]},
  3080. {
  3081. .compatible = "qcom,cnss-qca6290",
  3082. .data = (void *)&cnss_platform_id_table[1]},
  3083. {
  3084. .compatible = "qcom,cnss-qca6390",
  3085. .data = (void *)&cnss_platform_id_table[2]},
  3086. {
  3087. .compatible = "qcom,cnss-qca6490",
  3088. .data = (void *)&cnss_platform_id_table[3]},
  3089. {
  3090. .compatible = "qcom,cnss-kiwi",
  3091. .data = (void *)&cnss_platform_id_table[4]},
  3092. {
  3093. .compatible = "qcom,cnss-qca-converged",
  3094. .data = (void *)&cnss_platform_id_table[5]},
  3095. { },
  3096. };
  3097. MODULE_DEVICE_TABLE(of, cnss_of_match_table);
  3098. static inline bool
  3099. cnss_use_nv_mac(struct cnss_plat_data *plat_priv)
  3100. {
  3101. return of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3102. "use-nv-mac");
  3103. }
  3104. static int cnss_get_dev_cfg_node(struct cnss_plat_data *plat_priv)
  3105. {
  3106. struct device_node *child;
  3107. u32 id, i;
  3108. int id_n, ret;
  3109. int wlan_sw_ctrl_gpio = plat_priv->pinctrl_info.wlan_sw_ctrl_gpio;
  3110. u8 gpio_value;
  3111. if (!plat_priv->is_converged_dt)
  3112. return 0;
  3113. gpio_value = gpio_get_value(wlan_sw_ctrl_gpio);
  3114. cnss_pr_dbg("Value of WLAN_SW_CTRL GPIO: %d\n", gpio_value);
  3115. for_each_available_child_of_node(plat_priv->plat_dev->dev.of_node,
  3116. child) {
  3117. if (strcmp(child->name, "chip_cfg"))
  3118. continue;
  3119. id_n = of_property_count_u32_elems(child, "supported-ids");
  3120. if (id_n <= 0) {
  3121. cnss_pr_err("Device id is NOT set\n");
  3122. return -EINVAL;
  3123. }
  3124. for (i = 0; i < id_n; i++) {
  3125. ret = of_property_read_u32_index(child,
  3126. "supported-ids",
  3127. i, &id);
  3128. if (ret) {
  3129. cnss_pr_err("Failed to read supported ids\n");
  3130. return -EINVAL;
  3131. }
  3132. if (gpio_value && id == QCA6490_DEVICE_ID) {
  3133. plat_priv->plat_dev->dev.of_node = child;
  3134. plat_priv->device_id = QCA6490_DEVICE_ID;
  3135. cnss_utils_update_device_type(CNSS_HSP_DEVICE_TYPE);
  3136. cnss_pr_dbg("got node[%s@%d] for device[0x%x]\n",
  3137. child->name, i, id);
  3138. return 0;
  3139. } else if (!gpio_value && id == KIWI_DEVICE_ID) {
  3140. plat_priv->plat_dev->dev.of_node = child;
  3141. plat_priv->device_id = KIWI_DEVICE_ID;
  3142. cnss_utils_update_device_type(CNSS_HMT_DEVICE_TYPE);
  3143. cnss_pr_dbg("got node[%s@%d] for device[0x%x]\n",
  3144. child->name, i, id);
  3145. return 0;
  3146. }
  3147. }
  3148. }
  3149. return -EINVAL;
  3150. }
  3151. static inline bool
  3152. cnss_is_converged_dt(struct cnss_plat_data *plat_priv)
  3153. {
  3154. return of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3155. "qcom,converged-dt");
  3156. }
  3157. static int cnss_probe(struct platform_device *plat_dev)
  3158. {
  3159. int ret = 0;
  3160. struct cnss_plat_data *plat_priv;
  3161. const struct of_device_id *of_id;
  3162. const struct platform_device_id *device_id;
  3163. int retry = 0;
  3164. if (cnss_get_plat_priv(plat_dev)) {
  3165. cnss_pr_err("Driver is already initialized!\n");
  3166. ret = -EEXIST;
  3167. goto out;
  3168. }
  3169. of_id = of_match_device(cnss_of_match_table, &plat_dev->dev);
  3170. if (!of_id || !of_id->data) {
  3171. cnss_pr_err("Failed to find of match device!\n");
  3172. ret = -ENODEV;
  3173. goto out;
  3174. }
  3175. device_id = of_id->data;
  3176. plat_priv = devm_kzalloc(&plat_dev->dev, sizeof(*plat_priv),
  3177. GFP_KERNEL);
  3178. if (!plat_priv) {
  3179. ret = -ENOMEM;
  3180. goto out;
  3181. }
  3182. plat_priv->plat_dev = plat_dev;
  3183. plat_priv->device_id = device_id->driver_data;
  3184. plat_priv->is_converged_dt = cnss_is_converged_dt(plat_priv);
  3185. plat_priv->use_fw_path_with_prefix =
  3186. cnss_use_fw_path_with_prefix(plat_priv);
  3187. cnss_get_wlan_sw_ctrl(plat_priv);
  3188. ret = cnss_get_dev_cfg_node(plat_priv);
  3189. if (ret) {
  3190. cnss_pr_err("Failed to get device cfg node, err = %d\n", ret);
  3191. goto reset_plat_dev;
  3192. }
  3193. plat_priv->bus_type = cnss_get_bus_type(plat_priv->device_id);
  3194. plat_priv->use_nv_mac = cnss_use_nv_mac(plat_priv);
  3195. cnss_set_plat_priv(plat_dev, plat_priv);
  3196. platform_set_drvdata(plat_dev, plat_priv);
  3197. INIT_LIST_HEAD(&plat_priv->vreg_list);
  3198. INIT_LIST_HEAD(&plat_priv->clk_list);
  3199. cnss_get_pm_domain_info(plat_priv);
  3200. cnss_get_wlaon_pwr_ctrl_info(plat_priv);
  3201. cnss_power_misc_params_init(plat_priv);
  3202. cnss_get_tcs_info(plat_priv);
  3203. cnss_get_cpr_info(plat_priv);
  3204. cnss_aop_mbox_init(plat_priv);
  3205. cnss_init_control_params(plat_priv);
  3206. ret = cnss_get_resources(plat_priv);
  3207. if (ret)
  3208. goto reset_ctx;
  3209. ret = cnss_register_esoc(plat_priv);
  3210. if (ret)
  3211. goto free_res;
  3212. ret = cnss_register_bus_scale(plat_priv);
  3213. if (ret)
  3214. goto unreg_esoc;
  3215. ret = cnss_create_sysfs(plat_priv);
  3216. if (ret)
  3217. goto unreg_bus_scale;
  3218. ret = cnss_event_work_init(plat_priv);
  3219. if (ret)
  3220. goto remove_sysfs;
  3221. ret = cnss_qmi_init(plat_priv);
  3222. if (ret)
  3223. goto deinit_event_work;
  3224. ret = cnss_dms_init(plat_priv);
  3225. if (ret)
  3226. goto deinit_qmi;
  3227. ret = cnss_debugfs_create(plat_priv);
  3228. if (ret)
  3229. goto deinit_dms;
  3230. ret = cnss_misc_init(plat_priv);
  3231. if (ret)
  3232. goto destroy_debugfs;
  3233. /* Make sure all platform related init are done before
  3234. * device power on and bus init.
  3235. */
  3236. if (!test_bit(SKIP_DEVICE_BOOT, &plat_priv->ctrl_params.quirks)) {
  3237. retry:
  3238. ret = cnss_power_on_device(plat_priv);
  3239. if (ret)
  3240. goto deinit_misc;
  3241. ret = cnss_bus_init(plat_priv);
  3242. if (ret) {
  3243. if ((ret != -EPROBE_DEFER) &&
  3244. retry++ < POWER_ON_RETRY_MAX_TIMES) {
  3245. cnss_power_off_device(plat_priv);
  3246. cnss_pr_dbg("Retry cnss_bus_init #%d\n", retry);
  3247. msleep(POWER_ON_RETRY_DELAY_MS * retry);
  3248. goto retry;
  3249. }
  3250. goto power_off;
  3251. }
  3252. }
  3253. cnss_register_coex_service(plat_priv);
  3254. cnss_register_ims_service(plat_priv);
  3255. ret = cnss_genl_init();
  3256. if (ret < 0)
  3257. cnss_pr_err("CNSS genl init failed %d\n", ret);
  3258. cnss_pr_info("Platform driver probed successfully.\n");
  3259. return 0;
  3260. power_off:
  3261. if (!test_bit(SKIP_DEVICE_BOOT, &plat_priv->ctrl_params.quirks))
  3262. cnss_power_off_device(plat_priv);
  3263. deinit_misc:
  3264. cnss_misc_deinit(plat_priv);
  3265. destroy_debugfs:
  3266. cnss_debugfs_destroy(plat_priv);
  3267. deinit_dms:
  3268. cnss_dms_deinit(plat_priv);
  3269. deinit_qmi:
  3270. cnss_qmi_deinit(plat_priv);
  3271. deinit_event_work:
  3272. cnss_event_work_deinit(plat_priv);
  3273. remove_sysfs:
  3274. cnss_remove_sysfs(plat_priv);
  3275. unreg_bus_scale:
  3276. cnss_unregister_bus_scale(plat_priv);
  3277. unreg_esoc:
  3278. cnss_unregister_esoc(plat_priv);
  3279. free_res:
  3280. cnss_put_resources(plat_priv);
  3281. reset_ctx:
  3282. platform_set_drvdata(plat_dev, NULL);
  3283. reset_plat_dev:
  3284. cnss_set_plat_priv(plat_dev, NULL);
  3285. out:
  3286. return ret;
  3287. }
  3288. static int cnss_remove(struct platform_device *plat_dev)
  3289. {
  3290. struct cnss_plat_data *plat_priv = platform_get_drvdata(plat_dev);
  3291. cnss_genl_exit();
  3292. cnss_unregister_ims_service(plat_priv);
  3293. cnss_unregister_coex_service(plat_priv);
  3294. cnss_bus_deinit(plat_priv);
  3295. cnss_misc_deinit(plat_priv);
  3296. cnss_debugfs_destroy(plat_priv);
  3297. cnss_dms_deinit(plat_priv);
  3298. cnss_qmi_deinit(plat_priv);
  3299. cnss_event_work_deinit(plat_priv);
  3300. cnss_remove_sysfs(plat_priv);
  3301. cnss_unregister_bus_scale(plat_priv);
  3302. cnss_unregister_esoc(plat_priv);
  3303. cnss_put_resources(plat_priv);
  3304. if (!IS_ERR_OR_NULL(plat_priv->mbox_chan))
  3305. mbox_free_channel(plat_priv->mbox_chan);
  3306. platform_set_drvdata(plat_dev, NULL);
  3307. plat_env = NULL;
  3308. return 0;
  3309. }
  3310. static struct platform_driver cnss_platform_driver = {
  3311. .probe = cnss_probe,
  3312. .remove = cnss_remove,
  3313. .driver = {
  3314. .name = "cnss2",
  3315. .of_match_table = cnss_of_match_table,
  3316. #ifdef CONFIG_CNSS_ASYNC
  3317. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  3318. #endif
  3319. },
  3320. };
  3321. /**
  3322. * cnss_is_valid_dt_node_found - Check if valid device tree node present
  3323. *
  3324. * Valid device tree node means a node with "compatible" property from the
  3325. * device match table and "status" property is not disabled.
  3326. *
  3327. * Return: true if valid device tree node found, false if not found
  3328. */
  3329. static bool cnss_is_valid_dt_node_found(void)
  3330. {
  3331. struct device_node *dn = NULL;
  3332. for_each_matching_node(dn, cnss_of_match_table) {
  3333. if (of_device_is_available(dn))
  3334. break;
  3335. }
  3336. if (dn)
  3337. return true;
  3338. return false;
  3339. }
  3340. static int __init cnss_initialize(void)
  3341. {
  3342. int ret = 0;
  3343. if (!cnss_is_valid_dt_node_found())
  3344. return -ENODEV;
  3345. cnss_debug_init();
  3346. ret = platform_driver_register(&cnss_platform_driver);
  3347. if (ret)
  3348. cnss_debug_deinit();
  3349. return ret;
  3350. }
  3351. static void __exit cnss_exit(void)
  3352. {
  3353. platform_driver_unregister(&cnss_platform_driver);
  3354. cnss_debug_deinit();
  3355. }
  3356. module_init(cnss_initialize);
  3357. module_exit(cnss_exit);
  3358. MODULE_LICENSE("GPL v2");
  3359. MODULE_DESCRIPTION("CNSS2 Platform Driver");