qmi.c 90 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/soc/qcom/qmi.h>
  8. #include "bus.h"
  9. #include "debug.h"
  10. #include "main.h"
  11. #include "qmi.h"
  12. #include "genl.h"
  13. #define WLFW_SERVICE_INS_ID_V01 1
  14. #define WLFW_CLIENT_ID 0x4b4e454c
  15. #define BDF_FILE_NAME_PREFIX "bdwlan"
  16. #define ELF_BDF_FILE_NAME "bdwlan.elf"
  17. #define ELF_BDF_FILE_NAME_GF "bdwlang.elf"
  18. #define ELF_BDF_FILE_NAME_PREFIX "bdwlan.e"
  19. #define ELF_BDF_FILE_NAME_GF_PREFIX "bdwlang.e"
  20. #define BIN_BDF_FILE_NAME "bdwlan.bin"
  21. #define BIN_BDF_FILE_NAME_GF "bdwlang.bin"
  22. #define BIN_BDF_FILE_NAME_PREFIX "bdwlan.b"
  23. #define BIN_BDF_FILE_NAME_GF_PREFIX "bdwlang.b"
  24. #define REGDB_FILE_NAME "regdb.bin"
  25. #define HDS_FILE_NAME "hds.bin"
  26. #define CHIP_ID_GF_MASK 0x10
  27. #define QDSS_TRACE_CONFIG_FILE "qdss_trace_config"
  28. #ifdef CONFIG_CNSS2_DEBUG
  29. #define QDSS_DEBUG_FILE_STR "debug_"
  30. #else
  31. #define QDSS_DEBUG_FILE_STR ""
  32. #endif
  33. #define HW_V1_NUMBER "v1"
  34. #define HW_V2_NUMBER "v2"
  35. #define QMI_WLFW_TIMEOUT_MS (plat_priv->ctrl_params.qmi_timeout)
  36. #define QMI_WLFW_TIMEOUT_JF msecs_to_jiffies(QMI_WLFW_TIMEOUT_MS)
  37. #define COEX_TIMEOUT QMI_WLFW_TIMEOUT_JF
  38. #define IMS_TIMEOUT QMI_WLFW_TIMEOUT_JF
  39. #define QMI_WLFW_MAX_RECV_BUF_SIZE SZ_8K
  40. #define IMSPRIVATE_SERVICE_MAX_MSG_LEN SZ_8K
  41. #define DMS_QMI_MAX_MSG_LEN SZ_256
  42. #define QMI_WLFW_MAC_READY_TIMEOUT_MS 50
  43. #define QMI_WLFW_MAC_READY_MAX_RETRY 200
  44. #ifdef CONFIG_CNSS2_DEBUG
  45. static bool ignore_qmi_failure;
  46. #define CNSS_QMI_ASSERT() CNSS_ASSERT(ignore_qmi_failure)
  47. void cnss_ignore_qmi_failure(bool ignore)
  48. {
  49. ignore_qmi_failure = ignore;
  50. }
  51. #else
  52. #define CNSS_QMI_ASSERT() do { } while (0)
  53. void cnss_ignore_qmi_failure(bool ignore) { }
  54. #endif
  55. static char *cnss_qmi_mode_to_str(enum cnss_driver_mode mode)
  56. {
  57. switch (mode) {
  58. case CNSS_MISSION:
  59. return "MISSION";
  60. case CNSS_FTM:
  61. return "FTM";
  62. case CNSS_EPPING:
  63. return "EPPING";
  64. case CNSS_WALTEST:
  65. return "WALTEST";
  66. case CNSS_OFF:
  67. return "OFF";
  68. case CNSS_CCPM:
  69. return "CCPM";
  70. case CNSS_QVIT:
  71. return "QVIT";
  72. case CNSS_CALIBRATION:
  73. return "CALIBRATION";
  74. default:
  75. return "UNKNOWN";
  76. }
  77. };
  78. static int cnss_wlfw_ind_register_send_sync(struct cnss_plat_data *plat_priv)
  79. {
  80. struct wlfw_ind_register_req_msg_v01 *req;
  81. struct wlfw_ind_register_resp_msg_v01 *resp;
  82. struct qmi_txn txn;
  83. int ret = 0;
  84. cnss_pr_dbg("Sending indication register message, state: 0x%lx\n",
  85. plat_priv->driver_state);
  86. req = kzalloc(sizeof(*req), GFP_KERNEL);
  87. if (!req)
  88. return -ENOMEM;
  89. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  90. if (!resp) {
  91. kfree(req);
  92. return -ENOMEM;
  93. }
  94. req->client_id_valid = 1;
  95. req->client_id = WLFW_CLIENT_ID;
  96. req->request_mem_enable_valid = 1;
  97. req->request_mem_enable = 1;
  98. req->fw_mem_ready_enable_valid = 1;
  99. req->fw_mem_ready_enable = 1;
  100. /* fw_ready indication is replaced by fw_init_done in HST/HSP */
  101. req->fw_init_done_enable_valid = 1;
  102. req->fw_init_done_enable = 1;
  103. req->pin_connect_result_enable_valid = 1;
  104. req->pin_connect_result_enable = 1;
  105. req->cal_done_enable_valid = 1;
  106. req->cal_done_enable = 1;
  107. req->qdss_trace_req_mem_enable_valid = 1;
  108. req->qdss_trace_req_mem_enable = 1;
  109. req->qdss_trace_save_enable_valid = 1;
  110. req->qdss_trace_save_enable = 1;
  111. req->qdss_trace_free_enable_valid = 1;
  112. req->qdss_trace_free_enable = 1;
  113. req->respond_get_info_enable_valid = 1;
  114. req->respond_get_info_enable = 1;
  115. req->wfc_call_twt_config_enable_valid = 1;
  116. req->wfc_call_twt_config_enable = 1;
  117. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  118. wlfw_ind_register_resp_msg_v01_ei, resp);
  119. if (ret < 0) {
  120. cnss_pr_err("Failed to initialize txn for indication register request, err: %d\n",
  121. ret);
  122. goto out;
  123. }
  124. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  125. QMI_WLFW_IND_REGISTER_REQ_V01,
  126. WLFW_IND_REGISTER_REQ_MSG_V01_MAX_MSG_LEN,
  127. wlfw_ind_register_req_msg_v01_ei, req);
  128. if (ret < 0) {
  129. qmi_txn_cancel(&txn);
  130. cnss_pr_err("Failed to send indication register request, err: %d\n",
  131. ret);
  132. goto out;
  133. }
  134. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  135. if (ret < 0) {
  136. cnss_pr_err("Failed to wait for response of indication register request, err: %d\n",
  137. ret);
  138. goto out;
  139. }
  140. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  141. cnss_pr_err("Indication register request failed, result: %d, err: %d\n",
  142. resp->resp.result, resp->resp.error);
  143. ret = -resp->resp.result;
  144. goto out;
  145. }
  146. if (resp->fw_status_valid) {
  147. if (resp->fw_status & QMI_WLFW_ALREADY_REGISTERED_V01) {
  148. ret = -EALREADY;
  149. goto qmi_registered;
  150. }
  151. }
  152. kfree(req);
  153. kfree(resp);
  154. return 0;
  155. out:
  156. CNSS_QMI_ASSERT();
  157. qmi_registered:
  158. kfree(req);
  159. kfree(resp);
  160. return ret;
  161. }
  162. static void cnss_wlfw_host_cap_parse_mlo(struct cnss_plat_data *plat_priv,
  163. struct wlfw_host_cap_req_msg_v01 *req)
  164. {
  165. if (plat_priv->device_id == KIWI_DEVICE_ID) {
  166. req->mlo_capable_valid = 1;
  167. req->mlo_capable = 1;
  168. req->mlo_chip_id_valid = 1;
  169. req->mlo_chip_id = 0;
  170. req->mlo_group_id_valid = 1;
  171. req->mlo_group_id = 0;
  172. req->max_mlo_peer_valid = 1;
  173. /* Max peer number generally won't change for the same device
  174. * but needs to be synced with host driver.
  175. */
  176. req->max_mlo_peer = 32;
  177. req->mlo_num_chips_valid = 1;
  178. req->mlo_num_chips = 1;
  179. req->mlo_chip_info_valid = 1;
  180. req->mlo_chip_info[0].chip_id = 0;
  181. req->mlo_chip_info[0].num_local_links = 2;
  182. req->mlo_chip_info[0].hw_link_id[0] = 0;
  183. req->mlo_chip_info[0].hw_link_id[1] = 1;
  184. req->mlo_chip_info[0].valid_mlo_link_id[0] = 1;
  185. req->mlo_chip_info[0].valid_mlo_link_id[1] = 1;
  186. }
  187. }
  188. static int cnss_wlfw_host_cap_send_sync(struct cnss_plat_data *plat_priv)
  189. {
  190. struct wlfw_host_cap_req_msg_v01 *req;
  191. struct wlfw_host_cap_resp_msg_v01 *resp;
  192. struct qmi_txn txn;
  193. int ret = 0;
  194. u64 iova_start = 0, iova_size = 0,
  195. iova_ipa_start = 0, iova_ipa_size = 0;
  196. u64 feature_list = 0;
  197. cnss_pr_dbg("Sending host capability message, state: 0x%lx\n",
  198. plat_priv->driver_state);
  199. req = kzalloc(sizeof(*req), GFP_KERNEL);
  200. if (!req)
  201. return -ENOMEM;
  202. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  203. if (!resp) {
  204. kfree(req);
  205. return -ENOMEM;
  206. }
  207. req->num_clients_valid = 1;
  208. req->num_clients = 1;
  209. cnss_pr_dbg("Number of clients is %d\n", req->num_clients);
  210. req->wake_msi = cnss_bus_get_wake_irq(plat_priv);
  211. if (req->wake_msi) {
  212. cnss_pr_dbg("WAKE MSI base data is %d\n", req->wake_msi);
  213. req->wake_msi_valid = 1;
  214. }
  215. req->bdf_support_valid = 1;
  216. req->bdf_support = 1;
  217. req->m3_support_valid = 1;
  218. req->m3_support = 1;
  219. req->m3_cache_support_valid = 1;
  220. req->m3_cache_support = 1;
  221. req->cal_done_valid = 1;
  222. req->cal_done = plat_priv->cal_done;
  223. cnss_pr_dbg("Calibration done is %d\n", plat_priv->cal_done);
  224. if (!cnss_bus_get_iova(plat_priv, &iova_start, &iova_size) &&
  225. !cnss_bus_get_iova_ipa(plat_priv, &iova_ipa_start,
  226. &iova_ipa_size)) {
  227. req->ddr_range_valid = 1;
  228. req->ddr_range[0].start = iova_start;
  229. req->ddr_range[0].size = iova_size + iova_ipa_size;
  230. cnss_pr_dbg("Sending iova starting 0x%llx with size 0x%llx\n",
  231. req->ddr_range[0].start, req->ddr_range[0].size);
  232. }
  233. req->host_build_type_valid = 1;
  234. req->host_build_type = cnss_get_host_build_type();
  235. cnss_wlfw_host_cap_parse_mlo(plat_priv, req);
  236. ret = cnss_get_feature_list(plat_priv, &feature_list);
  237. if (!ret) {
  238. req->feature_list_valid = 1;
  239. req->feature_list = feature_list;
  240. cnss_pr_dbg("Sending feature list 0x%llx\n",
  241. req->feature_list);
  242. }
  243. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  244. wlfw_host_cap_resp_msg_v01_ei, resp);
  245. if (ret < 0) {
  246. cnss_pr_err("Failed to initialize txn for host capability request, err: %d\n",
  247. ret);
  248. goto out;
  249. }
  250. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  251. QMI_WLFW_HOST_CAP_REQ_V01,
  252. WLFW_HOST_CAP_REQ_MSG_V01_MAX_MSG_LEN,
  253. wlfw_host_cap_req_msg_v01_ei, req);
  254. if (ret < 0) {
  255. qmi_txn_cancel(&txn);
  256. cnss_pr_err("Failed to send host capability request, err: %d\n",
  257. ret);
  258. goto out;
  259. }
  260. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  261. if (ret < 0) {
  262. cnss_pr_err("Failed to wait for response of host capability request, err: %d\n",
  263. ret);
  264. goto out;
  265. }
  266. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  267. cnss_pr_err("Host capability request failed, result: %d, err: %d\n",
  268. resp->resp.result, resp->resp.error);
  269. ret = -resp->resp.result;
  270. goto out;
  271. }
  272. kfree(req);
  273. kfree(resp);
  274. return 0;
  275. out:
  276. CNSS_QMI_ASSERT();
  277. kfree(req);
  278. kfree(resp);
  279. return ret;
  280. }
  281. int cnss_wlfw_respond_mem_send_sync(struct cnss_plat_data *plat_priv)
  282. {
  283. struct wlfw_respond_mem_req_msg_v01 *req;
  284. struct wlfw_respond_mem_resp_msg_v01 *resp;
  285. struct qmi_txn txn;
  286. struct cnss_fw_mem *fw_mem = plat_priv->fw_mem;
  287. int ret = 0, i;
  288. cnss_pr_dbg("Sending respond memory message, state: 0x%lx\n",
  289. plat_priv->driver_state);
  290. req = kzalloc(sizeof(*req), GFP_KERNEL);
  291. if (!req)
  292. return -ENOMEM;
  293. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  294. if (!resp) {
  295. kfree(req);
  296. return -ENOMEM;
  297. }
  298. req->mem_seg_len = plat_priv->fw_mem_seg_len;
  299. for (i = 0; i < req->mem_seg_len; i++) {
  300. if (!fw_mem[i].pa || !fw_mem[i].size) {
  301. if (fw_mem[i].type == 0) {
  302. cnss_pr_err("Invalid memory for FW type, segment = %d\n",
  303. i);
  304. ret = -EINVAL;
  305. goto out;
  306. }
  307. cnss_pr_err("Memory for FW is not available for type: %u\n",
  308. fw_mem[i].type);
  309. ret = -ENOMEM;
  310. goto out;
  311. }
  312. cnss_pr_dbg("Memory for FW, va: 0x%pK, pa: %pa, size: 0x%zx, type: %u\n",
  313. fw_mem[i].va, &fw_mem[i].pa,
  314. fw_mem[i].size, fw_mem[i].type);
  315. req->mem_seg[i].addr = fw_mem[i].pa;
  316. req->mem_seg[i].size = fw_mem[i].size;
  317. req->mem_seg[i].type = fw_mem[i].type;
  318. }
  319. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  320. wlfw_respond_mem_resp_msg_v01_ei, resp);
  321. if (ret < 0) {
  322. cnss_pr_err("Failed to initialize txn for respond memory request, err: %d\n",
  323. ret);
  324. goto out;
  325. }
  326. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  327. QMI_WLFW_RESPOND_MEM_REQ_V01,
  328. WLFW_RESPOND_MEM_REQ_MSG_V01_MAX_MSG_LEN,
  329. wlfw_respond_mem_req_msg_v01_ei, req);
  330. if (ret < 0) {
  331. qmi_txn_cancel(&txn);
  332. cnss_pr_err("Failed to send respond memory request, err: %d\n",
  333. ret);
  334. goto out;
  335. }
  336. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  337. if (ret < 0) {
  338. cnss_pr_err("Failed to wait for response of respond memory request, err: %d\n",
  339. ret);
  340. goto out;
  341. }
  342. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  343. cnss_pr_err("Respond memory request failed, result: %d, err: %d\n",
  344. resp->resp.result, resp->resp.error);
  345. ret = -resp->resp.result;
  346. goto out;
  347. }
  348. kfree(req);
  349. kfree(resp);
  350. return 0;
  351. out:
  352. CNSS_QMI_ASSERT();
  353. kfree(req);
  354. kfree(resp);
  355. return ret;
  356. }
  357. int cnss_wlfw_tgt_cap_send_sync(struct cnss_plat_data *plat_priv)
  358. {
  359. struct wlfw_cap_req_msg_v01 *req;
  360. struct wlfw_cap_resp_msg_v01 *resp;
  361. struct qmi_txn txn;
  362. char *fw_build_timestamp;
  363. int ret = 0, i;
  364. cnss_pr_dbg("Sending target capability message, state: 0x%lx\n",
  365. plat_priv->driver_state);
  366. req = kzalloc(sizeof(*req), GFP_KERNEL);
  367. if (!req)
  368. return -ENOMEM;
  369. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  370. if (!resp) {
  371. kfree(req);
  372. return -ENOMEM;
  373. }
  374. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  375. wlfw_cap_resp_msg_v01_ei, resp);
  376. if (ret < 0) {
  377. cnss_pr_err("Failed to initialize txn for target capability request, err: %d\n",
  378. ret);
  379. goto out;
  380. }
  381. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  382. QMI_WLFW_CAP_REQ_V01,
  383. WLFW_CAP_REQ_MSG_V01_MAX_MSG_LEN,
  384. wlfw_cap_req_msg_v01_ei, req);
  385. if (ret < 0) {
  386. qmi_txn_cancel(&txn);
  387. cnss_pr_err("Failed to send respond target capability request, err: %d\n",
  388. ret);
  389. goto out;
  390. }
  391. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  392. if (ret < 0) {
  393. cnss_pr_err("Failed to wait for response of target capability request, err: %d\n",
  394. ret);
  395. goto out;
  396. }
  397. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  398. cnss_pr_err("Target capability request failed, result: %d, err: %d\n",
  399. resp->resp.result, resp->resp.error);
  400. ret = -resp->resp.result;
  401. goto out;
  402. }
  403. if (resp->chip_info_valid) {
  404. plat_priv->chip_info.chip_id = resp->chip_info.chip_id;
  405. plat_priv->chip_info.chip_family = resp->chip_info.chip_family;
  406. }
  407. if (resp->board_info_valid)
  408. plat_priv->board_info.board_id = resp->board_info.board_id;
  409. else
  410. plat_priv->board_info.board_id = 0xFF;
  411. if (resp->soc_info_valid)
  412. plat_priv->soc_info.soc_id = resp->soc_info.soc_id;
  413. if (resp->fw_version_info_valid) {
  414. plat_priv->fw_version_info.fw_version =
  415. resp->fw_version_info.fw_version;
  416. fw_build_timestamp = resp->fw_version_info.fw_build_timestamp;
  417. fw_build_timestamp[QMI_WLFW_MAX_TIMESTAMP_LEN] = '\0';
  418. strlcpy(plat_priv->fw_version_info.fw_build_timestamp,
  419. resp->fw_version_info.fw_build_timestamp,
  420. QMI_WLFW_MAX_TIMESTAMP_LEN + 1);
  421. }
  422. if (resp->fw_build_id_valid) {
  423. resp->fw_build_id[QMI_WLFW_MAX_BUILD_ID_LEN] = '\0';
  424. strlcpy(plat_priv->fw_build_id, resp->fw_build_id,
  425. QMI_WLFW_MAX_BUILD_ID_LEN + 1);
  426. }
  427. if (resp->voltage_mv_valid) {
  428. plat_priv->cpr_info.voltage = resp->voltage_mv;
  429. cnss_pr_dbg("Voltage for CPR: %dmV\n",
  430. plat_priv->cpr_info.voltage);
  431. cnss_update_cpr_info(plat_priv);
  432. }
  433. if (resp->time_freq_hz_valid) {
  434. plat_priv->device_freq_hz = resp->time_freq_hz;
  435. cnss_pr_dbg("Device frequency is %d HZ\n",
  436. plat_priv->device_freq_hz);
  437. }
  438. if (resp->otp_version_valid)
  439. plat_priv->otp_version = resp->otp_version;
  440. if (resp->dev_mem_info_valid) {
  441. for (i = 0; i < QMI_WLFW_MAX_DEV_MEM_NUM_V01; i++) {
  442. plat_priv->dev_mem_info[i].start =
  443. resp->dev_mem_info[i].start;
  444. plat_priv->dev_mem_info[i].size =
  445. resp->dev_mem_info[i].size;
  446. cnss_pr_buf("Device memory info[%d]: start = 0x%llx, size = 0x%llx\n",
  447. i, plat_priv->dev_mem_info[i].start,
  448. plat_priv->dev_mem_info[i].size);
  449. }
  450. }
  451. if (resp->fw_caps_valid)
  452. plat_priv->fw_pcie_gen_switch =
  453. !!(resp->fw_caps & QMI_WLFW_HOST_PCIE_GEN_SWITCH_V01);
  454. cnss_pr_dbg("Target capability: chip_id: 0x%x, chip_family: 0x%x, board_id: 0x%x, soc_id: 0x%x, otp_version: 0x%x\n",
  455. plat_priv->chip_info.chip_id,
  456. plat_priv->chip_info.chip_family,
  457. plat_priv->board_info.board_id, plat_priv->soc_info.soc_id,
  458. plat_priv->otp_version);
  459. cnss_pr_dbg("fw_version: 0x%x, fw_build_timestamp: %s, fw_build_id: %s\n",
  460. plat_priv->fw_version_info.fw_version,
  461. plat_priv->fw_version_info.fw_build_timestamp,
  462. plat_priv->fw_build_id);
  463. kfree(req);
  464. kfree(resp);
  465. return 0;
  466. out:
  467. CNSS_QMI_ASSERT();
  468. kfree(req);
  469. kfree(resp);
  470. return ret;
  471. }
  472. static int cnss_get_bdf_file_name(struct cnss_plat_data *plat_priv,
  473. u32 bdf_type, char *filename,
  474. u32 filename_len)
  475. {
  476. char filename_tmp[MAX_FIRMWARE_NAME_LEN];
  477. int ret = 0;
  478. switch (bdf_type) {
  479. case CNSS_BDF_ELF:
  480. /* Board ID will be equal or less than 0xFF in GF mask case */
  481. if (plat_priv->board_info.board_id == 0xFF) {
  482. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  483. snprintf(filename_tmp, filename_len,
  484. ELF_BDF_FILE_NAME_GF);
  485. else
  486. snprintf(filename_tmp, filename_len,
  487. ELF_BDF_FILE_NAME);
  488. } else if (plat_priv->board_info.board_id < 0xFF) {
  489. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  490. snprintf(filename_tmp, filename_len,
  491. ELF_BDF_FILE_NAME_GF_PREFIX "%02x",
  492. plat_priv->board_info.board_id);
  493. else
  494. snprintf(filename_tmp, filename_len,
  495. ELF_BDF_FILE_NAME_PREFIX "%02x",
  496. plat_priv->board_info.board_id);
  497. } else {
  498. snprintf(filename_tmp, filename_len,
  499. BDF_FILE_NAME_PREFIX "%02x.e%02x",
  500. plat_priv->board_info.board_id >> 8 & 0xFF,
  501. plat_priv->board_info.board_id & 0xFF);
  502. }
  503. break;
  504. case CNSS_BDF_BIN:
  505. if (plat_priv->board_info.board_id == 0xFF) {
  506. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  507. snprintf(filename_tmp, filename_len,
  508. BIN_BDF_FILE_NAME_GF);
  509. else
  510. snprintf(filename_tmp, filename_len,
  511. BIN_BDF_FILE_NAME);
  512. } else if (plat_priv->board_info.board_id < 0xFF) {
  513. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  514. snprintf(filename_tmp, filename_len,
  515. BIN_BDF_FILE_NAME_GF_PREFIX "%02x",
  516. plat_priv->board_info.board_id);
  517. else
  518. snprintf(filename_tmp, filename_len,
  519. BIN_BDF_FILE_NAME_PREFIX "%02x",
  520. plat_priv->board_info.board_id);
  521. } else {
  522. snprintf(filename_tmp, filename_len,
  523. BDF_FILE_NAME_PREFIX "%02x.b%02x",
  524. plat_priv->board_info.board_id >> 8 & 0xFF,
  525. plat_priv->board_info.board_id & 0xFF);
  526. }
  527. break;
  528. case CNSS_BDF_REGDB:
  529. snprintf(filename_tmp, filename_len, REGDB_FILE_NAME);
  530. break;
  531. case CNSS_BDF_HDS:
  532. snprintf(filename_tmp, filename_len, HDS_FILE_NAME);
  533. break;
  534. default:
  535. cnss_pr_err("Invalid BDF type: %d\n",
  536. plat_priv->ctrl_params.bdf_type);
  537. ret = -EINVAL;
  538. break;
  539. }
  540. if (!ret)
  541. cnss_bus_add_fw_prefix_name(plat_priv, filename, filename_tmp);
  542. return ret;
  543. }
  544. int cnss_wlfw_bdf_dnld_send_sync(struct cnss_plat_data *plat_priv,
  545. u32 bdf_type)
  546. {
  547. struct wlfw_bdf_download_req_msg_v01 *req;
  548. struct wlfw_bdf_download_resp_msg_v01 *resp;
  549. struct qmi_txn txn;
  550. char filename[MAX_FIRMWARE_NAME_LEN];
  551. const struct firmware *fw_entry = NULL;
  552. const u8 *temp;
  553. unsigned int remaining;
  554. int ret = 0;
  555. cnss_pr_dbg("Sending BDF download message, state: 0x%lx, type: %d\n",
  556. plat_priv->driver_state, bdf_type);
  557. req = kzalloc(sizeof(*req), GFP_KERNEL);
  558. if (!req)
  559. return -ENOMEM;
  560. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  561. if (!resp) {
  562. kfree(req);
  563. return -ENOMEM;
  564. }
  565. ret = cnss_get_bdf_file_name(plat_priv, bdf_type,
  566. filename, sizeof(filename));
  567. if (ret)
  568. goto err_req_fw;
  569. if (bdf_type == CNSS_BDF_REGDB)
  570. ret = cnss_request_firmware_direct(plat_priv, &fw_entry,
  571. filename);
  572. else
  573. ret = firmware_request_nowarn(&fw_entry, filename,
  574. &plat_priv->plat_dev->dev);
  575. if (ret) {
  576. cnss_pr_err("Failed to load BDF: %s, ret: %d\n", filename, ret);
  577. goto err_req_fw;
  578. }
  579. temp = fw_entry->data;
  580. remaining = fw_entry->size;
  581. cnss_pr_dbg("Downloading BDF: %s, size: %u\n", filename, remaining);
  582. while (remaining) {
  583. req->valid = 1;
  584. req->file_id_valid = 1;
  585. req->file_id = plat_priv->board_info.board_id;
  586. req->total_size_valid = 1;
  587. req->total_size = remaining;
  588. req->seg_id_valid = 1;
  589. req->data_valid = 1;
  590. req->end_valid = 1;
  591. req->bdf_type_valid = 1;
  592. req->bdf_type = bdf_type;
  593. if (remaining > QMI_WLFW_MAX_DATA_SIZE_V01) {
  594. req->data_len = QMI_WLFW_MAX_DATA_SIZE_V01;
  595. } else {
  596. req->data_len = remaining;
  597. req->end = 1;
  598. }
  599. memcpy(req->data, temp, req->data_len);
  600. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  601. wlfw_bdf_download_resp_msg_v01_ei, resp);
  602. if (ret < 0) {
  603. cnss_pr_err("Failed to initialize txn for BDF download request, err: %d\n",
  604. ret);
  605. goto err_send;
  606. }
  607. ret = qmi_send_request
  608. (&plat_priv->qmi_wlfw, NULL, &txn,
  609. QMI_WLFW_BDF_DOWNLOAD_REQ_V01,
  610. WLFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN,
  611. wlfw_bdf_download_req_msg_v01_ei, req);
  612. if (ret < 0) {
  613. qmi_txn_cancel(&txn);
  614. cnss_pr_err("Failed to send respond BDF download request, err: %d\n",
  615. ret);
  616. goto err_send;
  617. }
  618. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  619. if (ret < 0) {
  620. cnss_pr_err("Failed to wait for response of BDF download request, err: %d\n",
  621. ret);
  622. goto err_send;
  623. }
  624. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  625. cnss_pr_err("BDF download request failed, result: %d, err: %d\n",
  626. resp->resp.result, resp->resp.error);
  627. ret = -resp->resp.result;
  628. goto err_send;
  629. }
  630. remaining -= req->data_len;
  631. temp += req->data_len;
  632. req->seg_id++;
  633. }
  634. release_firmware(fw_entry);
  635. if (resp->host_bdf_data_valid) {
  636. /* QCA6490 enable S3E regulator for IPA configuration only */
  637. if (!(resp->host_bdf_data & QMI_WLFW_HW_XPA_V01))
  638. cnss_enable_int_pow_amp_vreg(plat_priv);
  639. plat_priv->cbc_file_download =
  640. resp->host_bdf_data & QMI_WLFW_CBC_FILE_DOWNLOAD_V01;
  641. cnss_pr_info("Host BDF config: HW_XPA: %d CalDB: %d\n",
  642. resp->host_bdf_data & QMI_WLFW_HW_XPA_V01,
  643. plat_priv->cbc_file_download);
  644. }
  645. kfree(req);
  646. kfree(resp);
  647. return 0;
  648. err_send:
  649. release_firmware(fw_entry);
  650. err_req_fw:
  651. if (!(bdf_type == CNSS_BDF_REGDB ||
  652. test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state) ||
  653. ret == -EAGAIN))
  654. CNSS_QMI_ASSERT();
  655. kfree(req);
  656. kfree(resp);
  657. return ret;
  658. }
  659. int cnss_wlfw_m3_dnld_send_sync(struct cnss_plat_data *plat_priv)
  660. {
  661. struct wlfw_m3_info_req_msg_v01 *req;
  662. struct wlfw_m3_info_resp_msg_v01 *resp;
  663. struct qmi_txn txn;
  664. struct cnss_fw_mem *m3_mem = &plat_priv->m3_mem;
  665. int ret = 0;
  666. cnss_pr_dbg("Sending M3 information message, state: 0x%lx\n",
  667. plat_priv->driver_state);
  668. req = kzalloc(sizeof(*req), GFP_KERNEL);
  669. if (!req)
  670. return -ENOMEM;
  671. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  672. if (!resp) {
  673. kfree(req);
  674. return -ENOMEM;
  675. }
  676. if (!m3_mem->pa || !m3_mem->size) {
  677. cnss_pr_err("Memory for M3 is not available\n");
  678. ret = -ENOMEM;
  679. goto out;
  680. }
  681. cnss_pr_dbg("M3 memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  682. m3_mem->va, &m3_mem->pa, m3_mem->size);
  683. req->addr = plat_priv->m3_mem.pa;
  684. req->size = plat_priv->m3_mem.size;
  685. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  686. wlfw_m3_info_resp_msg_v01_ei, resp);
  687. if (ret < 0) {
  688. cnss_pr_err("Failed to initialize txn for M3 information request, err: %d\n",
  689. ret);
  690. goto out;
  691. }
  692. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  693. QMI_WLFW_M3_INFO_REQ_V01,
  694. WLFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  695. wlfw_m3_info_req_msg_v01_ei, req);
  696. if (ret < 0) {
  697. qmi_txn_cancel(&txn);
  698. cnss_pr_err("Failed to send M3 information request, err: %d\n",
  699. ret);
  700. goto out;
  701. }
  702. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  703. if (ret < 0) {
  704. cnss_pr_err("Failed to wait for response of M3 information request, err: %d\n",
  705. ret);
  706. goto out;
  707. }
  708. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  709. cnss_pr_err("M3 information request failed, result: %d, err: %d\n",
  710. resp->resp.result, resp->resp.error);
  711. ret = -resp->resp.result;
  712. goto out;
  713. }
  714. kfree(req);
  715. kfree(resp);
  716. return 0;
  717. out:
  718. CNSS_QMI_ASSERT();
  719. kfree(req);
  720. kfree(resp);
  721. return ret;
  722. }
  723. int cnss_wlfw_wlan_mac_req_send_sync(struct cnss_plat_data *plat_priv,
  724. u8 *mac, u32 mac_len)
  725. {
  726. struct wlfw_mac_addr_req_msg_v01 req;
  727. struct wlfw_mac_addr_resp_msg_v01 resp = {0};
  728. struct qmi_txn txn;
  729. int ret;
  730. if (!plat_priv || !mac || mac_len != QMI_WLFW_MAC_ADDR_SIZE_V01)
  731. return -EINVAL;
  732. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  733. wlfw_mac_addr_resp_msg_v01_ei, &resp);
  734. if (ret < 0) {
  735. cnss_pr_err("Failed to initialize txn for mac req, err: %d\n",
  736. ret);
  737. ret = -EIO;
  738. goto out;
  739. }
  740. cnss_pr_dbg("Sending WLAN mac req [%pM], state: 0x%lx\n",
  741. mac, plat_priv->driver_state);
  742. memcpy(req.mac_addr, mac, mac_len);
  743. req.mac_addr_valid = 1;
  744. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  745. QMI_WLFW_MAC_ADDR_REQ_V01,
  746. WLFW_MAC_ADDR_REQ_MSG_V01_MAX_MSG_LEN,
  747. wlfw_mac_addr_req_msg_v01_ei, &req);
  748. if (ret < 0) {
  749. qmi_txn_cancel(&txn);
  750. cnss_pr_err("Failed to send mac req, err: %d\n", ret);
  751. ret = -EIO;
  752. goto out;
  753. }
  754. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  755. if (ret < 0) {
  756. cnss_pr_err("Failed to wait for resp of mac req, err: %d\n",
  757. ret);
  758. ret = -EIO;
  759. goto out;
  760. }
  761. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  762. cnss_pr_err("WLAN mac req failed, result: %d, err: %d\n",
  763. resp.resp.result);
  764. ret = -resp.resp.result;
  765. }
  766. out:
  767. return ret;
  768. }
  769. int cnss_wlfw_qdss_data_send_sync(struct cnss_plat_data *plat_priv, char *file_name,
  770. u32 total_size)
  771. {
  772. int ret = 0;
  773. struct wlfw_qdss_trace_data_req_msg_v01 *req;
  774. struct wlfw_qdss_trace_data_resp_msg_v01 *resp;
  775. unsigned char *p_qdss_trace_data_temp, *p_qdss_trace_data = NULL;
  776. unsigned int remaining;
  777. struct qmi_txn txn;
  778. cnss_pr_dbg("%s\n", __func__);
  779. req = kzalloc(sizeof(*req), GFP_KERNEL);
  780. if (!req)
  781. return -ENOMEM;
  782. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  783. if (!resp) {
  784. kfree(req);
  785. return -ENOMEM;
  786. }
  787. p_qdss_trace_data = kzalloc(total_size, GFP_KERNEL);
  788. if (!p_qdss_trace_data) {
  789. ret = ENOMEM;
  790. goto end;
  791. }
  792. remaining = total_size;
  793. p_qdss_trace_data_temp = p_qdss_trace_data;
  794. while (remaining && resp->end == 0) {
  795. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  796. wlfw_qdss_trace_data_resp_msg_v01_ei, resp);
  797. if (ret < 0) {
  798. cnss_pr_err("Fail to init txn for QDSS trace resp %d\n",
  799. ret);
  800. goto fail;
  801. }
  802. ret = qmi_send_request
  803. (&plat_priv->qmi_wlfw, NULL, &txn,
  804. QMI_WLFW_QDSS_TRACE_DATA_REQ_V01,
  805. WLFW_QDSS_TRACE_DATA_REQ_MSG_V01_MAX_MSG_LEN,
  806. wlfw_qdss_trace_data_req_msg_v01_ei, req);
  807. if (ret < 0) {
  808. qmi_txn_cancel(&txn);
  809. cnss_pr_err("Fail to send QDSS trace data req %d\n",
  810. ret);
  811. goto fail;
  812. }
  813. ret = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  814. if (ret < 0) {
  815. cnss_pr_err("QDSS trace resp wait failed with rc %d\n",
  816. ret);
  817. goto fail;
  818. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  819. cnss_pr_err("QMI QDSS trace request rejected, result:%d error:%d\n",
  820. resp->resp.result, resp->resp.error);
  821. ret = -resp->resp.result;
  822. goto fail;
  823. } else {
  824. ret = 0;
  825. }
  826. cnss_pr_dbg("%s: response total size %d data len %d",
  827. __func__, resp->total_size, resp->data_len);
  828. if ((resp->total_size_valid == 1 &&
  829. resp->total_size == total_size) &&
  830. (resp->seg_id_valid == 1 && resp->seg_id == req->seg_id) &&
  831. (resp->data_valid == 1 &&
  832. resp->data_len <= QMI_WLFW_MAX_DATA_SIZE_V01)) {
  833. memcpy(p_qdss_trace_data_temp,
  834. resp->data, resp->data_len);
  835. } else {
  836. cnss_pr_err("%s: Unmatched qdss trace data, Expect total_size %u, seg_id %u, Recv total_size_valid %u, total_size %u, seg_id_valid %u, seg_id %u, data_len_valid %u, data_len %u",
  837. __func__,
  838. total_size, req->seg_id,
  839. resp->total_size_valid,
  840. resp->total_size,
  841. resp->seg_id_valid,
  842. resp->seg_id,
  843. resp->data_valid,
  844. resp->data_len);
  845. ret = -1;
  846. goto fail;
  847. }
  848. remaining -= resp->data_len;
  849. p_qdss_trace_data_temp += resp->data_len;
  850. req->seg_id++;
  851. }
  852. if (remaining == 0 && (resp->end_valid && resp->end)) {
  853. ret = cnss_genl_send_msg(p_qdss_trace_data,
  854. CNSS_GENL_MSG_TYPE_QDSS, file_name,
  855. total_size);
  856. if (ret < 0) {
  857. cnss_pr_err("Fail to save QDSS trace data: %d\n",
  858. ret);
  859. ret = -1;
  860. goto fail;
  861. }
  862. } else {
  863. cnss_pr_err("%s: QDSS trace file corrupted: remaining %u, end_valid %u, end %u",
  864. __func__,
  865. remaining, resp->end_valid, resp->end);
  866. ret = -1;
  867. goto fail;
  868. }
  869. fail:
  870. kfree(p_qdss_trace_data);
  871. end:
  872. kfree(req);
  873. kfree(resp);
  874. return ret;
  875. }
  876. void cnss_get_qdss_cfg_filename(struct cnss_plat_data *plat_priv,
  877. char *filename, u32 filename_len)
  878. {
  879. char filename_tmp[MAX_FIRMWARE_NAME_LEN];
  880. char *debug_str = QDSS_DEBUG_FILE_STR;
  881. if (plat_priv->device_id == KIWI_DEVICE_ID)
  882. debug_str = "";
  883. if (plat_priv->device_version.major_version == FW_V2_NUMBER)
  884. snprintf(filename_tmp, filename_len, QDSS_TRACE_CONFIG_FILE
  885. "_%s%s.cfg", debug_str, HW_V2_NUMBER);
  886. else
  887. snprintf(filename_tmp, filename_len, QDSS_TRACE_CONFIG_FILE
  888. "_%s%s.cfg", debug_str, HW_V1_NUMBER);
  889. cnss_bus_add_fw_prefix_name(plat_priv, filename, filename_tmp);
  890. }
  891. int cnss_wlfw_qdss_dnld_send_sync(struct cnss_plat_data *plat_priv)
  892. {
  893. struct wlfw_qdss_trace_config_download_req_msg_v01 *req;
  894. struct wlfw_qdss_trace_config_download_resp_msg_v01 *resp;
  895. struct qmi_txn txn;
  896. const struct firmware *fw_entry = NULL;
  897. const u8 *temp;
  898. char qdss_cfg_filename[MAX_FIRMWARE_NAME_LEN];
  899. unsigned int remaining;
  900. int ret = 0;
  901. cnss_pr_dbg("Sending QDSS config download message, state: 0x%lx\n",
  902. plat_priv->driver_state);
  903. req = kzalloc(sizeof(*req), GFP_KERNEL);
  904. if (!req)
  905. return -ENOMEM;
  906. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  907. if (!resp) {
  908. kfree(req);
  909. return -ENOMEM;
  910. }
  911. cnss_get_qdss_cfg_filename(plat_priv, qdss_cfg_filename, sizeof(qdss_cfg_filename));
  912. ret = cnss_request_firmware_direct(plat_priv, &fw_entry,
  913. qdss_cfg_filename);
  914. if (ret) {
  915. cnss_pr_dbg("Unable to load %s\n",
  916. qdss_cfg_filename);
  917. goto err_req_fw;
  918. }
  919. temp = fw_entry->data;
  920. remaining = fw_entry->size;
  921. cnss_pr_dbg("Downloading QDSS: %s, size: %u\n",
  922. qdss_cfg_filename, remaining);
  923. while (remaining) {
  924. req->total_size_valid = 1;
  925. req->total_size = remaining;
  926. req->seg_id_valid = 1;
  927. req->data_valid = 1;
  928. req->end_valid = 1;
  929. if (remaining > QMI_WLFW_MAX_DATA_SIZE_V01) {
  930. req->data_len = QMI_WLFW_MAX_DATA_SIZE_V01;
  931. } else {
  932. req->data_len = remaining;
  933. req->end = 1;
  934. }
  935. memcpy(req->data, temp, req->data_len);
  936. ret = qmi_txn_init
  937. (&plat_priv->qmi_wlfw, &txn,
  938. wlfw_qdss_trace_config_download_resp_msg_v01_ei,
  939. resp);
  940. if (ret < 0) {
  941. cnss_pr_err("Failed to initialize txn for QDSS download request, err: %d\n",
  942. ret);
  943. goto err_send;
  944. }
  945. ret = qmi_send_request
  946. (&plat_priv->qmi_wlfw, NULL, &txn,
  947. QMI_WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_V01,
  948. WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN,
  949. wlfw_qdss_trace_config_download_req_msg_v01_ei, req);
  950. if (ret < 0) {
  951. qmi_txn_cancel(&txn);
  952. cnss_pr_err("Failed to send respond QDSS download request, err: %d\n",
  953. ret);
  954. goto err_send;
  955. }
  956. ret = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  957. if (ret < 0) {
  958. cnss_pr_err("Failed to wait for response of QDSS download request, err: %d\n",
  959. ret);
  960. goto err_send;
  961. }
  962. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  963. cnss_pr_err("QDSS download request failed, result: %d, err: %d\n",
  964. resp->resp.result, resp->resp.error);
  965. ret = -resp->resp.result;
  966. goto err_send;
  967. }
  968. remaining -= req->data_len;
  969. temp += req->data_len;
  970. req->seg_id++;
  971. }
  972. release_firmware(fw_entry);
  973. kfree(req);
  974. kfree(resp);
  975. return 0;
  976. err_send:
  977. release_firmware(fw_entry);
  978. err_req_fw:
  979. kfree(req);
  980. kfree(resp);
  981. return ret;
  982. }
  983. static int wlfw_send_qdss_trace_mode_req
  984. (struct cnss_plat_data *plat_priv,
  985. enum wlfw_qdss_trace_mode_enum_v01 mode,
  986. unsigned long long option)
  987. {
  988. int rc = 0;
  989. int tmp = 0;
  990. struct wlfw_qdss_trace_mode_req_msg_v01 *req;
  991. struct wlfw_qdss_trace_mode_resp_msg_v01 *resp;
  992. struct qmi_txn txn;
  993. if (!plat_priv)
  994. return -ENODEV;
  995. req = kzalloc(sizeof(*req), GFP_KERNEL);
  996. if (!req)
  997. return -ENOMEM;
  998. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  999. if (!resp) {
  1000. kfree(req);
  1001. return -ENOMEM;
  1002. }
  1003. req->mode_valid = 1;
  1004. req->mode = mode;
  1005. req->option_valid = 1;
  1006. req->option = option;
  1007. tmp = plat_priv->hw_trc_override;
  1008. req->hw_trc_disable_override_valid = 1;
  1009. req->hw_trc_disable_override =
  1010. (tmp > QMI_PARAM_DISABLE_V01 ? QMI_PARAM_DISABLE_V01 :
  1011. (tmp < 0 ? QMI_PARAM_INVALID_V01 : tmp));
  1012. cnss_pr_dbg("%s: mode %u, option %llu, hw_trc_disable_override: %u",
  1013. __func__, mode, option, req->hw_trc_disable_override);
  1014. rc = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1015. wlfw_qdss_trace_mode_resp_msg_v01_ei, resp);
  1016. if (rc < 0) {
  1017. cnss_pr_err("Fail to init txn for QDSS Mode resp %d\n",
  1018. rc);
  1019. goto out;
  1020. }
  1021. rc = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1022. QMI_WLFW_QDSS_TRACE_MODE_REQ_V01,
  1023. WLFW_QDSS_TRACE_MODE_REQ_MSG_V01_MAX_MSG_LEN,
  1024. wlfw_qdss_trace_mode_req_msg_v01_ei, req);
  1025. if (rc < 0) {
  1026. qmi_txn_cancel(&txn);
  1027. cnss_pr_err("Fail to send QDSS Mode req %d\n", rc);
  1028. goto out;
  1029. }
  1030. rc = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  1031. if (rc < 0) {
  1032. cnss_pr_err("QDSS Mode resp wait failed with rc %d\n",
  1033. rc);
  1034. goto out;
  1035. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1036. cnss_pr_err("QMI QDSS Mode request rejected, result:%d error:%d\n",
  1037. resp->resp.result, resp->resp.error);
  1038. rc = -resp->resp.result;
  1039. goto out;
  1040. }
  1041. kfree(resp);
  1042. kfree(req);
  1043. return rc;
  1044. out:
  1045. kfree(resp);
  1046. kfree(req);
  1047. CNSS_QMI_ASSERT();
  1048. return rc;
  1049. }
  1050. int wlfw_qdss_trace_start(struct cnss_plat_data *plat_priv)
  1051. {
  1052. return wlfw_send_qdss_trace_mode_req(plat_priv,
  1053. QMI_WLFW_QDSS_TRACE_ON_V01, 0);
  1054. }
  1055. int wlfw_qdss_trace_stop(struct cnss_plat_data *plat_priv, unsigned long long option)
  1056. {
  1057. return wlfw_send_qdss_trace_mode_req(plat_priv, QMI_WLFW_QDSS_TRACE_OFF_V01,
  1058. option);
  1059. }
  1060. int cnss_wlfw_wlan_mode_send_sync(struct cnss_plat_data *plat_priv,
  1061. enum cnss_driver_mode mode)
  1062. {
  1063. struct wlfw_wlan_mode_req_msg_v01 *req;
  1064. struct wlfw_wlan_mode_resp_msg_v01 *resp;
  1065. struct qmi_txn txn;
  1066. int ret = 0;
  1067. if (!plat_priv)
  1068. return -ENODEV;
  1069. cnss_pr_dbg("Sending mode message, mode: %s(%d), state: 0x%lx\n",
  1070. cnss_qmi_mode_to_str(mode), mode, plat_priv->driver_state);
  1071. if (mode == CNSS_OFF &&
  1072. test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1073. cnss_pr_dbg("Recovery is in progress, ignore mode off request\n");
  1074. return 0;
  1075. }
  1076. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1077. if (!req)
  1078. return -ENOMEM;
  1079. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1080. if (!resp) {
  1081. kfree(req);
  1082. return -ENOMEM;
  1083. }
  1084. req->mode = (enum wlfw_driver_mode_enum_v01)mode;
  1085. req->hw_debug_valid = 1;
  1086. req->hw_debug = 0;
  1087. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1088. wlfw_wlan_mode_resp_msg_v01_ei, resp);
  1089. if (ret < 0) {
  1090. cnss_pr_err("Failed to initialize txn for mode request, mode: %s(%d), err: %d\n",
  1091. cnss_qmi_mode_to_str(mode), mode, ret);
  1092. goto out;
  1093. }
  1094. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1095. QMI_WLFW_WLAN_MODE_REQ_V01,
  1096. WLFW_WLAN_MODE_REQ_MSG_V01_MAX_MSG_LEN,
  1097. wlfw_wlan_mode_req_msg_v01_ei, req);
  1098. if (ret < 0) {
  1099. qmi_txn_cancel(&txn);
  1100. cnss_pr_err("Failed to send mode request, mode: %s(%d), err: %d\n",
  1101. cnss_qmi_mode_to_str(mode), mode, ret);
  1102. goto out;
  1103. }
  1104. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1105. if (ret < 0) {
  1106. cnss_pr_err("Failed to wait for response of mode request, mode: %s(%d), err: %d\n",
  1107. cnss_qmi_mode_to_str(mode), mode, ret);
  1108. goto out;
  1109. }
  1110. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1111. cnss_pr_err("Mode request failed, mode: %s(%d), result: %d, err: %d\n",
  1112. cnss_qmi_mode_to_str(mode), mode, resp->resp.result,
  1113. resp->resp.error);
  1114. ret = -resp->resp.result;
  1115. goto out;
  1116. }
  1117. kfree(req);
  1118. kfree(resp);
  1119. return 0;
  1120. out:
  1121. if (mode == CNSS_OFF) {
  1122. cnss_pr_dbg("WLFW service is disconnected while sending mode off request\n");
  1123. ret = 0;
  1124. } else {
  1125. CNSS_QMI_ASSERT();
  1126. }
  1127. kfree(req);
  1128. kfree(resp);
  1129. return ret;
  1130. }
  1131. int cnss_wlfw_wlan_cfg_send_sync(struct cnss_plat_data *plat_priv,
  1132. struct cnss_wlan_enable_cfg *config,
  1133. const char *host_version)
  1134. {
  1135. struct wlfw_wlan_cfg_req_msg_v01 *req;
  1136. struct wlfw_wlan_cfg_resp_msg_v01 *resp;
  1137. struct qmi_txn txn;
  1138. u32 i;
  1139. int ret = 0;
  1140. if (!plat_priv)
  1141. return -ENODEV;
  1142. cnss_pr_dbg("Sending WLAN config message, state: 0x%lx\n",
  1143. plat_priv->driver_state);
  1144. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1145. if (!req)
  1146. return -ENOMEM;
  1147. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1148. if (!resp) {
  1149. kfree(req);
  1150. return -ENOMEM;
  1151. }
  1152. req->host_version_valid = 1;
  1153. strlcpy(req->host_version, host_version,
  1154. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  1155. req->tgt_cfg_valid = 1;
  1156. if (config->num_ce_tgt_cfg > QMI_WLFW_MAX_NUM_CE_V01)
  1157. req->tgt_cfg_len = QMI_WLFW_MAX_NUM_CE_V01;
  1158. else
  1159. req->tgt_cfg_len = config->num_ce_tgt_cfg;
  1160. for (i = 0; i < req->tgt_cfg_len; i++) {
  1161. req->tgt_cfg[i].pipe_num = config->ce_tgt_cfg[i].pipe_num;
  1162. req->tgt_cfg[i].pipe_dir = config->ce_tgt_cfg[i].pipe_dir;
  1163. req->tgt_cfg[i].nentries = config->ce_tgt_cfg[i].nentries;
  1164. req->tgt_cfg[i].nbytes_max = config->ce_tgt_cfg[i].nbytes_max;
  1165. req->tgt_cfg[i].flags = config->ce_tgt_cfg[i].flags;
  1166. }
  1167. req->svc_cfg_valid = 1;
  1168. if (config->num_ce_svc_pipe_cfg > QMI_WLFW_MAX_NUM_SVC_V01)
  1169. req->svc_cfg_len = QMI_WLFW_MAX_NUM_SVC_V01;
  1170. else
  1171. req->svc_cfg_len = config->num_ce_svc_pipe_cfg;
  1172. for (i = 0; i < req->svc_cfg_len; i++) {
  1173. req->svc_cfg[i].service_id = config->ce_svc_cfg[i].service_id;
  1174. req->svc_cfg[i].pipe_dir = config->ce_svc_cfg[i].pipe_dir;
  1175. req->svc_cfg[i].pipe_num = config->ce_svc_cfg[i].pipe_num;
  1176. }
  1177. req->shadow_reg_v2_valid = 1;
  1178. if (config->num_shadow_reg_v2_cfg >
  1179. QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01)
  1180. req->shadow_reg_v2_len = QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01;
  1181. else
  1182. req->shadow_reg_v2_len = config->num_shadow_reg_v2_cfg;
  1183. memcpy(req->shadow_reg_v2, config->shadow_reg_v2_cfg,
  1184. sizeof(struct wlfw_shadow_reg_v2_cfg_s_v01)
  1185. * req->shadow_reg_v2_len);
  1186. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1187. wlfw_wlan_cfg_resp_msg_v01_ei, resp);
  1188. if (ret < 0) {
  1189. cnss_pr_err("Failed to initialize txn for WLAN config request, err: %d\n",
  1190. ret);
  1191. goto out;
  1192. }
  1193. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1194. QMI_WLFW_WLAN_CFG_REQ_V01,
  1195. WLFW_WLAN_CFG_REQ_MSG_V01_MAX_MSG_LEN,
  1196. wlfw_wlan_cfg_req_msg_v01_ei, req);
  1197. if (ret < 0) {
  1198. qmi_txn_cancel(&txn);
  1199. cnss_pr_err("Failed to send WLAN config request, err: %d\n",
  1200. ret);
  1201. goto out;
  1202. }
  1203. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1204. if (ret < 0) {
  1205. cnss_pr_err("Failed to wait for response of WLAN config request, err: %d\n",
  1206. ret);
  1207. goto out;
  1208. }
  1209. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1210. cnss_pr_err("WLAN config request failed, result: %d, err: %d\n",
  1211. resp->resp.result, resp->resp.error);
  1212. ret = -resp->resp.result;
  1213. goto out;
  1214. }
  1215. kfree(req);
  1216. kfree(resp);
  1217. return 0;
  1218. out:
  1219. CNSS_QMI_ASSERT();
  1220. kfree(req);
  1221. kfree(resp);
  1222. return ret;
  1223. }
  1224. int cnss_wlfw_athdiag_read_send_sync(struct cnss_plat_data *plat_priv,
  1225. u32 offset, u32 mem_type,
  1226. u32 data_len, u8 *data)
  1227. {
  1228. struct wlfw_athdiag_read_req_msg_v01 *req;
  1229. struct wlfw_athdiag_read_resp_msg_v01 *resp;
  1230. struct qmi_txn txn;
  1231. int ret = 0;
  1232. if (!plat_priv)
  1233. return -ENODEV;
  1234. if (!data || data_len == 0 || data_len > QMI_WLFW_MAX_DATA_SIZE_V01) {
  1235. cnss_pr_err("Invalid parameters for athdiag read: data %pK, data_len %u\n",
  1236. data, data_len);
  1237. return -EINVAL;
  1238. }
  1239. cnss_pr_dbg("athdiag read: state 0x%lx, offset %x, mem_type %x, data_len %u\n",
  1240. plat_priv->driver_state, offset, mem_type, data_len);
  1241. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1242. if (!req)
  1243. return -ENOMEM;
  1244. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1245. if (!resp) {
  1246. kfree(req);
  1247. return -ENOMEM;
  1248. }
  1249. req->offset = offset;
  1250. req->mem_type = mem_type;
  1251. req->data_len = data_len;
  1252. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1253. wlfw_athdiag_read_resp_msg_v01_ei, resp);
  1254. if (ret < 0) {
  1255. cnss_pr_err("Failed to initialize txn for athdiag read request, err: %d\n",
  1256. ret);
  1257. goto out;
  1258. }
  1259. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1260. QMI_WLFW_ATHDIAG_READ_REQ_V01,
  1261. WLFW_ATHDIAG_READ_REQ_MSG_V01_MAX_MSG_LEN,
  1262. wlfw_athdiag_read_req_msg_v01_ei, req);
  1263. if (ret < 0) {
  1264. qmi_txn_cancel(&txn);
  1265. cnss_pr_err("Failed to send athdiag read request, err: %d\n",
  1266. ret);
  1267. goto out;
  1268. }
  1269. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1270. if (ret < 0) {
  1271. cnss_pr_err("Failed to wait for response of athdiag read request, err: %d\n",
  1272. ret);
  1273. goto out;
  1274. }
  1275. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1276. cnss_pr_err("Athdiag read request failed, result: %d, err: %d\n",
  1277. resp->resp.result, resp->resp.error);
  1278. ret = -resp->resp.result;
  1279. goto out;
  1280. }
  1281. if (!resp->data_valid || resp->data_len != data_len) {
  1282. cnss_pr_err("athdiag read data is invalid, data_valid = %u, data_len = %u\n",
  1283. resp->data_valid, resp->data_len);
  1284. ret = -EINVAL;
  1285. goto out;
  1286. }
  1287. memcpy(data, resp->data, resp->data_len);
  1288. kfree(req);
  1289. kfree(resp);
  1290. return 0;
  1291. out:
  1292. kfree(req);
  1293. kfree(resp);
  1294. return ret;
  1295. }
  1296. int cnss_wlfw_athdiag_write_send_sync(struct cnss_plat_data *plat_priv,
  1297. u32 offset, u32 mem_type,
  1298. u32 data_len, u8 *data)
  1299. {
  1300. struct wlfw_athdiag_write_req_msg_v01 *req;
  1301. struct wlfw_athdiag_write_resp_msg_v01 *resp;
  1302. struct qmi_txn txn;
  1303. int ret = 0;
  1304. if (!plat_priv)
  1305. return -ENODEV;
  1306. if (!data || data_len == 0 || data_len > QMI_WLFW_MAX_DATA_SIZE_V01) {
  1307. cnss_pr_err("Invalid parameters for athdiag write: data %pK, data_len %u\n",
  1308. data, data_len);
  1309. return -EINVAL;
  1310. }
  1311. cnss_pr_dbg("athdiag write: state 0x%lx, offset %x, mem_type %x, data_len %u, data %pK\n",
  1312. plat_priv->driver_state, offset, mem_type, data_len, data);
  1313. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1314. if (!req)
  1315. return -ENOMEM;
  1316. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1317. if (!resp) {
  1318. kfree(req);
  1319. return -ENOMEM;
  1320. }
  1321. req->offset = offset;
  1322. req->mem_type = mem_type;
  1323. req->data_len = data_len;
  1324. memcpy(req->data, data, data_len);
  1325. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1326. wlfw_athdiag_write_resp_msg_v01_ei, resp);
  1327. if (ret < 0) {
  1328. cnss_pr_err("Failed to initialize txn for athdiag write request, err: %d\n",
  1329. ret);
  1330. goto out;
  1331. }
  1332. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1333. QMI_WLFW_ATHDIAG_WRITE_REQ_V01,
  1334. WLFW_ATHDIAG_WRITE_REQ_MSG_V01_MAX_MSG_LEN,
  1335. wlfw_athdiag_write_req_msg_v01_ei, req);
  1336. if (ret < 0) {
  1337. qmi_txn_cancel(&txn);
  1338. cnss_pr_err("Failed to send athdiag write request, err: %d\n",
  1339. ret);
  1340. goto out;
  1341. }
  1342. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1343. if (ret < 0) {
  1344. cnss_pr_err("Failed to wait for response of athdiag write request, err: %d\n",
  1345. ret);
  1346. goto out;
  1347. }
  1348. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1349. cnss_pr_err("Athdiag write request failed, result: %d, err: %d\n",
  1350. resp->resp.result, resp->resp.error);
  1351. ret = -resp->resp.result;
  1352. goto out;
  1353. }
  1354. kfree(req);
  1355. kfree(resp);
  1356. return 0;
  1357. out:
  1358. kfree(req);
  1359. kfree(resp);
  1360. return ret;
  1361. }
  1362. int cnss_wlfw_ini_send_sync(struct cnss_plat_data *plat_priv,
  1363. u8 fw_log_mode)
  1364. {
  1365. struct wlfw_ini_req_msg_v01 *req;
  1366. struct wlfw_ini_resp_msg_v01 *resp;
  1367. struct qmi_txn txn;
  1368. int ret = 0;
  1369. if (!plat_priv)
  1370. return -ENODEV;
  1371. cnss_pr_dbg("Sending ini sync request, state: 0x%lx, fw_log_mode: %d\n",
  1372. plat_priv->driver_state, fw_log_mode);
  1373. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1374. if (!req)
  1375. return -ENOMEM;
  1376. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1377. if (!resp) {
  1378. kfree(req);
  1379. return -ENOMEM;
  1380. }
  1381. req->enablefwlog_valid = 1;
  1382. req->enablefwlog = fw_log_mode;
  1383. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1384. wlfw_ini_resp_msg_v01_ei, resp);
  1385. if (ret < 0) {
  1386. cnss_pr_err("Failed to initialize txn for ini request, fw_log_mode: %d, err: %d\n",
  1387. fw_log_mode, ret);
  1388. goto out;
  1389. }
  1390. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1391. QMI_WLFW_INI_REQ_V01,
  1392. WLFW_INI_REQ_MSG_V01_MAX_MSG_LEN,
  1393. wlfw_ini_req_msg_v01_ei, req);
  1394. if (ret < 0) {
  1395. qmi_txn_cancel(&txn);
  1396. cnss_pr_err("Failed to send ini request, fw_log_mode: %d, err: %d\n",
  1397. fw_log_mode, ret);
  1398. goto out;
  1399. }
  1400. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1401. if (ret < 0) {
  1402. cnss_pr_err("Failed to wait for response of ini request, fw_log_mode: %d, err: %d\n",
  1403. fw_log_mode, ret);
  1404. goto out;
  1405. }
  1406. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1407. cnss_pr_err("Ini request failed, fw_log_mode: %d, result: %d, err: %d\n",
  1408. fw_log_mode, resp->resp.result, resp->resp.error);
  1409. ret = -resp->resp.result;
  1410. goto out;
  1411. }
  1412. kfree(req);
  1413. kfree(resp);
  1414. return 0;
  1415. out:
  1416. kfree(req);
  1417. kfree(resp);
  1418. return ret;
  1419. }
  1420. int cnss_wlfw_send_pcie_gen_speed_sync(struct cnss_plat_data *plat_priv)
  1421. {
  1422. struct wlfw_pcie_gen_switch_req_msg_v01 req;
  1423. struct wlfw_pcie_gen_switch_resp_msg_v01 resp = {0};
  1424. struct qmi_txn txn;
  1425. int ret = 0;
  1426. if (!plat_priv)
  1427. return -ENODEV;
  1428. if (plat_priv->pcie_gen_speed == QMI_PCIE_GEN_SPEED_INVALID_V01 ||
  1429. !plat_priv->fw_pcie_gen_switch) {
  1430. cnss_pr_dbg("PCIE Gen speed not setup\n");
  1431. return 0;
  1432. }
  1433. cnss_pr_dbg("Sending PCIE Gen speed: %d state: 0x%lx\n",
  1434. plat_priv->pcie_gen_speed, plat_priv->driver_state);
  1435. req.pcie_speed = (enum wlfw_pcie_gen_speed_v01)
  1436. plat_priv->pcie_gen_speed;
  1437. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1438. wlfw_pcie_gen_switch_resp_msg_v01_ei, &resp);
  1439. if (ret < 0) {
  1440. cnss_pr_err("Failed to initialize txn for PCIE speed switch err: %d\n",
  1441. ret);
  1442. goto out;
  1443. }
  1444. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1445. QMI_WLFW_PCIE_GEN_SWITCH_REQ_V01,
  1446. WLFW_PCIE_GEN_SWITCH_REQ_MSG_V01_MAX_MSG_LEN,
  1447. wlfw_pcie_gen_switch_req_msg_v01_ei, &req);
  1448. if (ret < 0) {
  1449. qmi_txn_cancel(&txn);
  1450. cnss_pr_err("Failed to send PCIE speed switch, err: %d\n", ret);
  1451. goto out;
  1452. }
  1453. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1454. if (ret < 0) {
  1455. cnss_pr_err("Failed to wait for PCIE Gen switch resp, err: %d\n",
  1456. ret);
  1457. goto out;
  1458. }
  1459. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  1460. cnss_pr_err("PCIE Gen Switch req failed, Speed: %d, result: %d, err: %d\n",
  1461. plat_priv->pcie_gen_speed, resp.resp.result,
  1462. resp.resp.error);
  1463. ret = -resp.resp.result;
  1464. }
  1465. out:
  1466. /* Reset PCIE Gen speed after one time use */
  1467. plat_priv->pcie_gen_speed = QMI_PCIE_GEN_SPEED_INVALID_V01;
  1468. return ret;
  1469. }
  1470. int cnss_wlfw_antenna_switch_send_sync(struct cnss_plat_data *plat_priv)
  1471. {
  1472. struct wlfw_antenna_switch_req_msg_v01 *req;
  1473. struct wlfw_antenna_switch_resp_msg_v01 *resp;
  1474. struct qmi_txn txn;
  1475. int ret = 0;
  1476. if (!plat_priv)
  1477. return -ENODEV;
  1478. cnss_pr_dbg("Sending antenna switch sync request, state: 0x%lx\n",
  1479. plat_priv->driver_state);
  1480. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1481. if (!req)
  1482. return -ENOMEM;
  1483. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1484. if (!resp) {
  1485. kfree(req);
  1486. return -ENOMEM;
  1487. }
  1488. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1489. wlfw_antenna_switch_resp_msg_v01_ei, resp);
  1490. if (ret < 0) {
  1491. cnss_pr_err("Failed to initialize txn for antenna switch request, err: %d\n",
  1492. ret);
  1493. goto out;
  1494. }
  1495. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1496. QMI_WLFW_ANTENNA_SWITCH_REQ_V01,
  1497. WLFW_ANTENNA_SWITCH_REQ_MSG_V01_MAX_MSG_LEN,
  1498. wlfw_antenna_switch_req_msg_v01_ei, req);
  1499. if (ret < 0) {
  1500. qmi_txn_cancel(&txn);
  1501. cnss_pr_err("Failed to send antenna switch request, err: %d\n",
  1502. ret);
  1503. goto out;
  1504. }
  1505. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1506. if (ret < 0) {
  1507. cnss_pr_err("Failed to wait for response of antenna switch request, err: %d\n",
  1508. ret);
  1509. goto out;
  1510. }
  1511. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1512. cnss_pr_dbg("Antenna switch request failed, result: %d, err: %d\n",
  1513. resp->resp.result, resp->resp.error);
  1514. ret = -resp->resp.result;
  1515. goto out;
  1516. }
  1517. if (resp->antenna_valid)
  1518. plat_priv->antenna = resp->antenna;
  1519. cnss_pr_dbg("Antenna valid: %u, antenna 0x%llx\n",
  1520. resp->antenna_valid, resp->antenna);
  1521. kfree(req);
  1522. kfree(resp);
  1523. return 0;
  1524. out:
  1525. kfree(req);
  1526. kfree(resp);
  1527. return ret;
  1528. }
  1529. int cnss_wlfw_antenna_grant_send_sync(struct cnss_plat_data *plat_priv)
  1530. {
  1531. struct wlfw_antenna_grant_req_msg_v01 *req;
  1532. struct wlfw_antenna_grant_resp_msg_v01 *resp;
  1533. struct qmi_txn txn;
  1534. int ret = 0;
  1535. if (!plat_priv)
  1536. return -ENODEV;
  1537. cnss_pr_dbg("Sending antenna grant sync request, state: 0x%lx, grant 0x%llx\n",
  1538. plat_priv->driver_state, plat_priv->grant);
  1539. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1540. if (!req)
  1541. return -ENOMEM;
  1542. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1543. if (!resp) {
  1544. kfree(req);
  1545. return -ENOMEM;
  1546. }
  1547. req->grant_valid = 1;
  1548. req->grant = plat_priv->grant;
  1549. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1550. wlfw_antenna_grant_resp_msg_v01_ei, resp);
  1551. if (ret < 0) {
  1552. cnss_pr_err("Failed to initialize txn for antenna grant request, err: %d\n",
  1553. ret);
  1554. goto out;
  1555. }
  1556. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1557. QMI_WLFW_ANTENNA_GRANT_REQ_V01,
  1558. WLFW_ANTENNA_GRANT_REQ_MSG_V01_MAX_MSG_LEN,
  1559. wlfw_antenna_grant_req_msg_v01_ei, req);
  1560. if (ret < 0) {
  1561. qmi_txn_cancel(&txn);
  1562. cnss_pr_err("Failed to send antenna grant request, err: %d\n",
  1563. ret);
  1564. goto out;
  1565. }
  1566. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1567. if (ret < 0) {
  1568. cnss_pr_err("Failed to wait for response of antenna grant request, err: %d\n",
  1569. ret);
  1570. goto out;
  1571. }
  1572. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1573. cnss_pr_err("Antenna grant request failed, result: %d, err: %d\n",
  1574. resp->resp.result, resp->resp.error);
  1575. ret = -resp->resp.result;
  1576. goto out;
  1577. }
  1578. kfree(req);
  1579. kfree(resp);
  1580. return 0;
  1581. out:
  1582. kfree(req);
  1583. kfree(resp);
  1584. return ret;
  1585. }
  1586. int cnss_wlfw_qdss_trace_mem_info_send_sync(struct cnss_plat_data *plat_priv)
  1587. {
  1588. struct wlfw_qdss_trace_mem_info_req_msg_v01 *req;
  1589. struct wlfw_qdss_trace_mem_info_resp_msg_v01 *resp;
  1590. struct qmi_txn txn;
  1591. struct cnss_fw_mem *qdss_mem = plat_priv->qdss_mem;
  1592. int ret = 0;
  1593. int i;
  1594. cnss_pr_dbg("Sending QDSS trace mem info, state: 0x%lx\n",
  1595. plat_priv->driver_state);
  1596. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1597. if (!req)
  1598. return -ENOMEM;
  1599. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1600. if (!resp) {
  1601. kfree(req);
  1602. return -ENOMEM;
  1603. }
  1604. req->mem_seg_len = plat_priv->qdss_mem_seg_len;
  1605. for (i = 0; i < req->mem_seg_len; i++) {
  1606. cnss_pr_dbg("Memory for FW, va: 0x%pK, pa: %pa, size: 0x%zx, type: %u\n",
  1607. qdss_mem[i].va, &qdss_mem[i].pa,
  1608. qdss_mem[i].size, qdss_mem[i].type);
  1609. req->mem_seg[i].addr = qdss_mem[i].pa;
  1610. req->mem_seg[i].size = qdss_mem[i].size;
  1611. req->mem_seg[i].type = qdss_mem[i].type;
  1612. }
  1613. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1614. wlfw_qdss_trace_mem_info_resp_msg_v01_ei, resp);
  1615. if (ret < 0) {
  1616. cnss_pr_err("Fail to initialize txn for QDSS trace mem request: err %d\n",
  1617. ret);
  1618. goto out;
  1619. }
  1620. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1621. QMI_WLFW_QDSS_TRACE_MEM_INFO_REQ_V01,
  1622. WLFW_QDSS_TRACE_MEM_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  1623. wlfw_qdss_trace_mem_info_req_msg_v01_ei, req);
  1624. if (ret < 0) {
  1625. qmi_txn_cancel(&txn);
  1626. cnss_pr_err("Fail to send QDSS trace mem info request: err %d\n",
  1627. ret);
  1628. goto out;
  1629. }
  1630. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1631. if (ret < 0) {
  1632. cnss_pr_err("Fail to wait for response of QDSS trace mem info request, err %d\n",
  1633. ret);
  1634. goto out;
  1635. }
  1636. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1637. cnss_pr_err("QDSS trace mem info request failed, result: %d, err: %d\n",
  1638. resp->resp.result, resp->resp.error);
  1639. ret = -resp->resp.result;
  1640. goto out;
  1641. }
  1642. kfree(req);
  1643. kfree(resp);
  1644. return 0;
  1645. out:
  1646. kfree(req);
  1647. kfree(resp);
  1648. return ret;
  1649. }
  1650. static int cnss_wlfw_wfc_call_status_send_sync
  1651. (struct cnss_plat_data *plat_priv,
  1652. const struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg)
  1653. {
  1654. struct wlfw_wfc_call_status_req_msg_v01 *req;
  1655. struct wlfw_wfc_call_status_resp_msg_v01 *resp;
  1656. struct qmi_txn txn;
  1657. int ret = 0;
  1658. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  1659. cnss_pr_err("Drop IMS WFC indication as FW not initialized\n");
  1660. return -EINVAL;
  1661. }
  1662. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1663. if (!req)
  1664. return -ENOMEM;
  1665. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1666. if (!resp) {
  1667. kfree(req);
  1668. return -ENOMEM;
  1669. }
  1670. /**
  1671. * WFC Call r1 design has CNSS as pass thru using opaque hex buffer.
  1672. * But in r2 update QMI structure is expanded and as an effect qmi
  1673. * decoded structures have padding. Thus we cannot use buffer design.
  1674. * For backward compatibility for r1 design copy only wfc_call_active
  1675. * value in hex buffer.
  1676. */
  1677. req->wfc_call_status_len = sizeof(ind_msg->wfc_call_active);
  1678. req->wfc_call_status[0] = ind_msg->wfc_call_active;
  1679. /* wfc_call_active is mandatory in IMS indication */
  1680. req->wfc_call_active_valid = 1;
  1681. req->wfc_call_active = ind_msg->wfc_call_active;
  1682. req->all_wfc_calls_held_valid = ind_msg->all_wfc_calls_held_valid;
  1683. req->all_wfc_calls_held = ind_msg->all_wfc_calls_held;
  1684. req->is_wfc_emergency_valid = ind_msg->is_wfc_emergency_valid;
  1685. req->is_wfc_emergency = ind_msg->is_wfc_emergency;
  1686. req->twt_ims_start_valid = ind_msg->twt_ims_start_valid;
  1687. req->twt_ims_start = ind_msg->twt_ims_start;
  1688. req->twt_ims_int_valid = ind_msg->twt_ims_int_valid;
  1689. req->twt_ims_int = ind_msg->twt_ims_int;
  1690. req->media_quality_valid = ind_msg->media_quality_valid;
  1691. req->media_quality =
  1692. (enum wlfw_wfc_media_quality_v01)ind_msg->media_quality;
  1693. cnss_pr_dbg("CNSS->FW: WFC_CALL_REQ: state: 0x%lx\n",
  1694. plat_priv->driver_state);
  1695. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1696. wlfw_wfc_call_status_resp_msg_v01_ei, resp);
  1697. if (ret < 0) {
  1698. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Txn Init: Err %d\n",
  1699. ret);
  1700. goto out;
  1701. }
  1702. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1703. QMI_WLFW_WFC_CALL_STATUS_REQ_V01,
  1704. WLFW_WFC_CALL_STATUS_REQ_MSG_V01_MAX_MSG_LEN,
  1705. wlfw_wfc_call_status_req_msg_v01_ei, req);
  1706. if (ret < 0) {
  1707. qmi_txn_cancel(&txn);
  1708. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Send Err: %d\n",
  1709. ret);
  1710. goto out;
  1711. }
  1712. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1713. if (ret < 0) {
  1714. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: QMI Wait Err: %d\n",
  1715. ret);
  1716. goto out;
  1717. }
  1718. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1719. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: Result: %d Err: %d\n",
  1720. resp->resp.result, resp->resp.error);
  1721. ret = -resp->resp.result;
  1722. goto out;
  1723. }
  1724. ret = 0;
  1725. out:
  1726. kfree(req);
  1727. kfree(resp);
  1728. return ret;
  1729. }
  1730. int cnss_wlfw_dynamic_feature_mask_send_sync(struct cnss_plat_data *plat_priv)
  1731. {
  1732. struct wlfw_dynamic_feature_mask_req_msg_v01 *req;
  1733. struct wlfw_dynamic_feature_mask_resp_msg_v01 *resp;
  1734. struct qmi_txn txn;
  1735. int ret = 0;
  1736. cnss_pr_dbg("Sending dynamic feature mask 0x%llx, state: 0x%lx\n",
  1737. plat_priv->dynamic_feature,
  1738. plat_priv->driver_state);
  1739. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1740. if (!req)
  1741. return -ENOMEM;
  1742. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1743. if (!resp) {
  1744. kfree(req);
  1745. return -ENOMEM;
  1746. }
  1747. req->mask_valid = 1;
  1748. req->mask = plat_priv->dynamic_feature;
  1749. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1750. wlfw_dynamic_feature_mask_resp_msg_v01_ei, resp);
  1751. if (ret < 0) {
  1752. cnss_pr_err("Fail to initialize txn for dynamic feature mask request: err %d\n",
  1753. ret);
  1754. goto out;
  1755. }
  1756. ret = qmi_send_request
  1757. (&plat_priv->qmi_wlfw, NULL, &txn,
  1758. QMI_WLFW_DYNAMIC_FEATURE_MASK_REQ_V01,
  1759. WLFW_DYNAMIC_FEATURE_MASK_REQ_MSG_V01_MAX_MSG_LEN,
  1760. wlfw_dynamic_feature_mask_req_msg_v01_ei, req);
  1761. if (ret < 0) {
  1762. qmi_txn_cancel(&txn);
  1763. cnss_pr_err("Fail to send dynamic feature mask request: err %d\n",
  1764. ret);
  1765. goto out;
  1766. }
  1767. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1768. if (ret < 0) {
  1769. cnss_pr_err("Fail to wait for response of dynamic feature mask request, err %d\n",
  1770. ret);
  1771. goto out;
  1772. }
  1773. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1774. cnss_pr_err("Dynamic feature mask request failed, result: %d, err: %d\n",
  1775. resp->resp.result, resp->resp.error);
  1776. ret = -resp->resp.result;
  1777. goto out;
  1778. }
  1779. out:
  1780. kfree(req);
  1781. kfree(resp);
  1782. return ret;
  1783. }
  1784. int cnss_wlfw_get_info_send_sync(struct cnss_plat_data *plat_priv, int type,
  1785. void *cmd, int cmd_len)
  1786. {
  1787. struct wlfw_get_info_req_msg_v01 *req;
  1788. struct wlfw_get_info_resp_msg_v01 *resp;
  1789. struct qmi_txn txn;
  1790. int ret = 0;
  1791. cnss_pr_buf("Sending get info message, type: %d, cmd length: %d, state: 0x%lx\n",
  1792. type, cmd_len, plat_priv->driver_state);
  1793. if (cmd_len > QMI_WLFW_MAX_DATA_SIZE_V01)
  1794. return -EINVAL;
  1795. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1796. if (!req)
  1797. return -ENOMEM;
  1798. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1799. if (!resp) {
  1800. kfree(req);
  1801. return -ENOMEM;
  1802. }
  1803. req->type = type;
  1804. req->data_len = cmd_len;
  1805. memcpy(req->data, cmd, req->data_len);
  1806. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1807. wlfw_get_info_resp_msg_v01_ei, resp);
  1808. if (ret < 0) {
  1809. cnss_pr_err("Failed to initialize txn for get info request, err: %d\n",
  1810. ret);
  1811. goto out;
  1812. }
  1813. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1814. QMI_WLFW_GET_INFO_REQ_V01,
  1815. WLFW_GET_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  1816. wlfw_get_info_req_msg_v01_ei, req);
  1817. if (ret < 0) {
  1818. qmi_txn_cancel(&txn);
  1819. cnss_pr_err("Failed to send get info request, err: %d\n",
  1820. ret);
  1821. goto out;
  1822. }
  1823. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1824. if (ret < 0) {
  1825. cnss_pr_err("Failed to wait for response of get info request, err: %d\n",
  1826. ret);
  1827. goto out;
  1828. }
  1829. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1830. cnss_pr_err("Get info request failed, result: %d, err: %d\n",
  1831. resp->resp.result, resp->resp.error);
  1832. ret = -resp->resp.result;
  1833. goto out;
  1834. }
  1835. kfree(req);
  1836. kfree(resp);
  1837. return 0;
  1838. out:
  1839. kfree(req);
  1840. kfree(resp);
  1841. return ret;
  1842. }
  1843. unsigned int cnss_get_qmi_timeout(struct cnss_plat_data *plat_priv)
  1844. {
  1845. return QMI_WLFW_TIMEOUT_MS;
  1846. }
  1847. static void cnss_wlfw_request_mem_ind_cb(struct qmi_handle *qmi_wlfw,
  1848. struct sockaddr_qrtr *sq,
  1849. struct qmi_txn *txn, const void *data)
  1850. {
  1851. struct cnss_plat_data *plat_priv =
  1852. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  1853. const struct wlfw_request_mem_ind_msg_v01 *ind_msg = data;
  1854. int i;
  1855. cnss_pr_dbg("Received QMI WLFW request memory indication\n");
  1856. if (!txn) {
  1857. cnss_pr_err("Spurious indication\n");
  1858. return;
  1859. }
  1860. plat_priv->fw_mem_seg_len = ind_msg->mem_seg_len;
  1861. for (i = 0; i < plat_priv->fw_mem_seg_len; i++) {
  1862. cnss_pr_dbg("FW requests for memory, size: 0x%x, type: %u\n",
  1863. ind_msg->mem_seg[i].size, ind_msg->mem_seg[i].type);
  1864. plat_priv->fw_mem[i].type = ind_msg->mem_seg[i].type;
  1865. plat_priv->fw_mem[i].size = ind_msg->mem_seg[i].size;
  1866. if (plat_priv->fw_mem[i].type == CNSS_MEM_TYPE_DDR)
  1867. plat_priv->fw_mem[i].attrs |=
  1868. DMA_ATTR_FORCE_CONTIGUOUS;
  1869. if (plat_priv->fw_mem[i].type == CNSS_MEM_CAL_V01)
  1870. plat_priv->cal_mem = &plat_priv->fw_mem[i];
  1871. }
  1872. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_REQUEST_MEM,
  1873. 0, NULL);
  1874. }
  1875. static void cnss_wlfw_fw_mem_ready_ind_cb(struct qmi_handle *qmi_wlfw,
  1876. struct sockaddr_qrtr *sq,
  1877. struct qmi_txn *txn, const void *data)
  1878. {
  1879. struct cnss_plat_data *plat_priv =
  1880. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  1881. cnss_pr_dbg("Received QMI WLFW FW memory ready indication\n");
  1882. if (!txn) {
  1883. cnss_pr_err("Spurious indication\n");
  1884. return;
  1885. }
  1886. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_MEM_READY,
  1887. 0, NULL);
  1888. }
  1889. /**
  1890. * cnss_wlfw_fw_ready_ind_cb: FW ready indication handler (Helium arch)
  1891. *
  1892. * This event is not required for HST/ HSP as FW calibration done is
  1893. * provided in QMI_WLFW_CAL_DONE_IND_V01
  1894. */
  1895. static void cnss_wlfw_fw_ready_ind_cb(struct qmi_handle *qmi_wlfw,
  1896. struct sockaddr_qrtr *sq,
  1897. struct qmi_txn *txn, const void *data)
  1898. {
  1899. struct cnss_plat_data *plat_priv =
  1900. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  1901. struct cnss_cal_info *cal_info;
  1902. if (!txn) {
  1903. cnss_pr_err("Spurious indication\n");
  1904. return;
  1905. }
  1906. if (plat_priv->device_id == QCA6390_DEVICE_ID ||
  1907. plat_priv->device_id == QCA6490_DEVICE_ID) {
  1908. cnss_pr_dbg("Ignore FW Ready Indication for HST/HSP");
  1909. return;
  1910. }
  1911. cnss_pr_dbg("Received QMI WLFW FW ready indication.\n");
  1912. cal_info = kzalloc(sizeof(*cal_info), GFP_KERNEL);
  1913. if (!cal_info)
  1914. return;
  1915. cal_info->cal_status = CNSS_CAL_DONE;
  1916. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE,
  1917. 0, cal_info);
  1918. }
  1919. static void cnss_wlfw_fw_init_done_ind_cb(struct qmi_handle *qmi_wlfw,
  1920. struct sockaddr_qrtr *sq,
  1921. struct qmi_txn *txn, const void *data)
  1922. {
  1923. struct cnss_plat_data *plat_priv =
  1924. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  1925. cnss_pr_dbg("Received QMI WLFW FW initialization done indication\n");
  1926. if (!txn) {
  1927. cnss_pr_err("Spurious indication\n");
  1928. return;
  1929. }
  1930. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_READY, 0, NULL);
  1931. }
  1932. static void cnss_wlfw_pin_result_ind_cb(struct qmi_handle *qmi_wlfw,
  1933. struct sockaddr_qrtr *sq,
  1934. struct qmi_txn *txn, const void *data)
  1935. {
  1936. struct cnss_plat_data *plat_priv =
  1937. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  1938. const struct wlfw_pin_connect_result_ind_msg_v01 *ind_msg = data;
  1939. cnss_pr_dbg("Received QMI WLFW pin connect result indication\n");
  1940. if (!txn) {
  1941. cnss_pr_err("Spurious indication\n");
  1942. return;
  1943. }
  1944. if (ind_msg->pwr_pin_result_valid)
  1945. plat_priv->pin_result.fw_pwr_pin_result =
  1946. ind_msg->pwr_pin_result;
  1947. if (ind_msg->phy_io_pin_result_valid)
  1948. plat_priv->pin_result.fw_phy_io_pin_result =
  1949. ind_msg->phy_io_pin_result;
  1950. if (ind_msg->rf_pin_result_valid)
  1951. plat_priv->pin_result.fw_rf_pin_result = ind_msg->rf_pin_result;
  1952. cnss_pr_dbg("Pin connect Result: pwr_pin: 0x%x phy_io_pin: 0x%x rf_io_pin: 0x%x\n",
  1953. ind_msg->pwr_pin_result, ind_msg->phy_io_pin_result,
  1954. ind_msg->rf_pin_result);
  1955. }
  1956. int cnss_wlfw_cal_report_req_send_sync(struct cnss_plat_data *plat_priv,
  1957. u32 cal_file_download_size)
  1958. {
  1959. struct wlfw_cal_report_req_msg_v01 req = {0};
  1960. struct wlfw_cal_report_resp_msg_v01 resp = {0};
  1961. struct qmi_txn txn;
  1962. int ret = 0;
  1963. cnss_pr_dbg("Sending cal file report request. File size: %d, state: 0x%lx\n",
  1964. cal_file_download_size, plat_priv->driver_state);
  1965. req.cal_file_download_size_valid = 1;
  1966. req.cal_file_download_size = cal_file_download_size;
  1967. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1968. wlfw_cal_report_resp_msg_v01_ei, &resp);
  1969. if (ret < 0) {
  1970. cnss_pr_err("Failed to initialize txn for Cal Report request, err: %d\n",
  1971. ret);
  1972. goto out;
  1973. }
  1974. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1975. QMI_WLFW_CAL_REPORT_REQ_V01,
  1976. WLFW_CAL_REPORT_REQ_MSG_V01_MAX_MSG_LEN,
  1977. wlfw_cal_report_req_msg_v01_ei, &req);
  1978. if (ret < 0) {
  1979. qmi_txn_cancel(&txn);
  1980. cnss_pr_err("Failed to send Cal Report request, err: %d\n",
  1981. ret);
  1982. goto out;
  1983. }
  1984. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1985. if (ret < 0) {
  1986. cnss_pr_err("Failed to wait for response of Cal Report request, err: %d\n",
  1987. ret);
  1988. goto out;
  1989. }
  1990. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  1991. cnss_pr_err("Cal Report request failed, result: %d, err: %d\n",
  1992. resp.resp.result, resp.resp.error);
  1993. ret = -resp.resp.result;
  1994. goto out;
  1995. }
  1996. out:
  1997. return ret;
  1998. }
  1999. static void cnss_wlfw_cal_done_ind_cb(struct qmi_handle *qmi_wlfw,
  2000. struct sockaddr_qrtr *sq,
  2001. struct qmi_txn *txn, const void *data)
  2002. {
  2003. struct cnss_plat_data *plat_priv =
  2004. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2005. const struct wlfw_cal_done_ind_msg_v01 *ind = data;
  2006. struct cnss_cal_info *cal_info;
  2007. cnss_pr_dbg("Received Cal done indication. File size: %d\n",
  2008. ind->cal_file_upload_size);
  2009. cnss_pr_info("Calibration took %d ms\n",
  2010. jiffies_to_msecs(jiffies - plat_priv->cal_time));
  2011. if (!txn) {
  2012. cnss_pr_err("Spurious indication\n");
  2013. return;
  2014. }
  2015. if (ind->cal_file_upload_size_valid)
  2016. plat_priv->cal_file_size = ind->cal_file_upload_size;
  2017. cal_info = kzalloc(sizeof(*cal_info), GFP_KERNEL);
  2018. if (!cal_info)
  2019. return;
  2020. cal_info->cal_status = CNSS_CAL_DONE;
  2021. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE,
  2022. 0, cal_info);
  2023. }
  2024. static void cnss_wlfw_qdss_trace_req_mem_ind_cb(struct qmi_handle *qmi_wlfw,
  2025. struct sockaddr_qrtr *sq,
  2026. struct qmi_txn *txn,
  2027. const void *data)
  2028. {
  2029. struct cnss_plat_data *plat_priv =
  2030. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2031. const struct wlfw_qdss_trace_req_mem_ind_msg_v01 *ind_msg = data;
  2032. int i;
  2033. cnss_pr_dbg("Received QMI WLFW QDSS trace request mem indication\n");
  2034. if (!txn) {
  2035. cnss_pr_err("Spurious indication\n");
  2036. return;
  2037. }
  2038. if (plat_priv->qdss_mem_seg_len) {
  2039. cnss_pr_err("Ignore double allocation for QDSS trace, current len %u\n",
  2040. plat_priv->qdss_mem_seg_len);
  2041. return;
  2042. }
  2043. plat_priv->qdss_mem_seg_len = ind_msg->mem_seg_len;
  2044. for (i = 0; i < plat_priv->qdss_mem_seg_len; i++) {
  2045. cnss_pr_dbg("QDSS requests for memory, size: 0x%x, type: %u\n",
  2046. ind_msg->mem_seg[i].size, ind_msg->mem_seg[i].type);
  2047. plat_priv->qdss_mem[i].type = ind_msg->mem_seg[i].type;
  2048. plat_priv->qdss_mem[i].size = ind_msg->mem_seg[i].size;
  2049. }
  2050. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM,
  2051. 0, NULL);
  2052. }
  2053. /**
  2054. * cnss_wlfw_fw_mem_file_save_ind_cb: Save given FW mem to filesystem
  2055. *
  2056. * QDSS_TRACE_SAVE_IND feature is overloaded to provide any host allocated
  2057. * fw memory segment for dumping to file system. Only one type of mem can be
  2058. * saved per indication and is provided in mem seg index 0.
  2059. *
  2060. * Return: None
  2061. */
  2062. static void cnss_wlfw_fw_mem_file_save_ind_cb(struct qmi_handle *qmi_wlfw,
  2063. struct sockaddr_qrtr *sq,
  2064. struct qmi_txn *txn,
  2065. const void *data)
  2066. {
  2067. struct cnss_plat_data *plat_priv =
  2068. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2069. const struct wlfw_qdss_trace_save_ind_msg_v01 *ind_msg = data;
  2070. struct cnss_qmi_event_fw_mem_file_save_data *event_data;
  2071. int i = 0;
  2072. if (!txn || !data) {
  2073. cnss_pr_err("Spurious indication\n");
  2074. return;
  2075. }
  2076. cnss_pr_dbg("QMI fw_mem_file_save: source: %d mem_seg: %d type: %u len: %u\n",
  2077. ind_msg->source, ind_msg->mem_seg_valid,
  2078. ind_msg->mem_seg[0].type, ind_msg->mem_seg_len);
  2079. event_data = kzalloc(sizeof(*event_data), GFP_KERNEL);
  2080. if (!event_data)
  2081. return;
  2082. event_data->mem_type = ind_msg->mem_seg[0].type;
  2083. event_data->mem_seg_len = ind_msg->mem_seg_len;
  2084. event_data->total_size = ind_msg->total_size;
  2085. if (ind_msg->mem_seg_valid) {
  2086. if (ind_msg->mem_seg_len > QMI_WLFW_MAX_STR_LEN_V01) {
  2087. cnss_pr_err("Invalid seg len indication\n");
  2088. goto free_event_data;
  2089. }
  2090. for (i = 0; i < ind_msg->mem_seg_len; i++) {
  2091. event_data->mem_seg[i].addr = ind_msg->mem_seg[i].addr;
  2092. event_data->mem_seg[i].size = ind_msg->mem_seg[i].size;
  2093. if (event_data->mem_type != ind_msg->mem_seg[i].type) {
  2094. cnss_pr_err("FW Mem file save ind cannot have multiple mem types\n");
  2095. goto free_event_data;
  2096. }
  2097. cnss_pr_dbg("seg-%d: addr 0x%llx size 0x%x\n",
  2098. i, ind_msg->mem_seg[i].addr,
  2099. ind_msg->mem_seg[i].size);
  2100. }
  2101. }
  2102. if (ind_msg->file_name_valid)
  2103. strlcpy(event_data->file_name, ind_msg->file_name,
  2104. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2105. if (ind_msg->source == 1) {
  2106. if (!ind_msg->file_name_valid)
  2107. strlcpy(event_data->file_name, "qdss_trace_wcss_etb",
  2108. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2109. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA,
  2110. 0, event_data);
  2111. } else {
  2112. if (event_data->mem_type == QMI_WLFW_MEM_QDSS_V01) {
  2113. if (!ind_msg->file_name_valid)
  2114. strlcpy(event_data->file_name, "qdss_trace_ddr",
  2115. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2116. } else {
  2117. if (!ind_msg->file_name_valid)
  2118. strlcpy(event_data->file_name, "fw_mem_dump",
  2119. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2120. }
  2121. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE,
  2122. 0, event_data);
  2123. }
  2124. return;
  2125. free_event_data:
  2126. kfree(event_data);
  2127. }
  2128. static void cnss_wlfw_qdss_trace_free_ind_cb(struct qmi_handle *qmi_wlfw,
  2129. struct sockaddr_qrtr *sq,
  2130. struct qmi_txn *txn,
  2131. const void *data)
  2132. {
  2133. struct cnss_plat_data *plat_priv =
  2134. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2135. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_FREE,
  2136. 0, NULL);
  2137. }
  2138. static void cnss_wlfw_respond_get_info_ind_cb(struct qmi_handle *qmi_wlfw,
  2139. struct sockaddr_qrtr *sq,
  2140. struct qmi_txn *txn,
  2141. const void *data)
  2142. {
  2143. struct cnss_plat_data *plat_priv =
  2144. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2145. const struct wlfw_respond_get_info_ind_msg_v01 *ind_msg = data;
  2146. cnss_pr_buf("Received QMI WLFW respond get info indication\n");
  2147. if (!txn) {
  2148. cnss_pr_err("Spurious indication\n");
  2149. return;
  2150. }
  2151. cnss_pr_buf("Extract message with event length: %d, type: %d, is last: %d, seq no: %d\n",
  2152. ind_msg->data_len, ind_msg->type,
  2153. ind_msg->is_last, ind_msg->seq_no);
  2154. if (plat_priv->get_info_cb_ctx && plat_priv->get_info_cb)
  2155. plat_priv->get_info_cb(plat_priv->get_info_cb_ctx,
  2156. (void *)ind_msg->data,
  2157. ind_msg->data_len);
  2158. }
  2159. static int cnss_ims_wfc_call_twt_cfg_send_sync
  2160. (struct cnss_plat_data *plat_priv,
  2161. const struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg)
  2162. {
  2163. struct ims_private_service_wfc_call_twt_config_req_msg_v01 *req;
  2164. struct ims_private_service_wfc_call_twt_config_rsp_msg_v01 *resp;
  2165. struct qmi_txn txn;
  2166. int ret = 0;
  2167. if (!test_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state)) {
  2168. cnss_pr_err("Drop FW WFC indication as IMS QMI not connected\n");
  2169. return -EINVAL;
  2170. }
  2171. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2172. if (!req)
  2173. return -ENOMEM;
  2174. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2175. if (!resp) {
  2176. kfree(req);
  2177. return -ENOMEM;
  2178. }
  2179. req->twt_sta_start_valid = ind_msg->twt_sta_start_valid;
  2180. req->twt_sta_start = ind_msg->twt_sta_start;
  2181. req->twt_sta_int_valid = ind_msg->twt_sta_int_valid;
  2182. req->twt_sta_int = ind_msg->twt_sta_int;
  2183. req->twt_sta_upo_valid = ind_msg->twt_sta_upo_valid;
  2184. req->twt_sta_upo = ind_msg->twt_sta_upo;
  2185. req->twt_sta_sp_valid = ind_msg->twt_sta_sp_valid;
  2186. req->twt_sta_sp = ind_msg->twt_sta_sp;
  2187. req->twt_sta_dl_valid = req->twt_sta_dl_valid;
  2188. req->twt_sta_dl = req->twt_sta_dl;
  2189. req->twt_sta_config_changed_valid =
  2190. ind_msg->twt_sta_config_changed_valid;
  2191. req->twt_sta_config_changed = ind_msg->twt_sta_config_changed;
  2192. cnss_pr_dbg("CNSS->IMS: TWT_CFG_REQ: state: 0x%lx\n",
  2193. plat_priv->driver_state);
  2194. ret =
  2195. qmi_txn_init(&plat_priv->ims_qmi, &txn,
  2196. ims_private_service_wfc_call_twt_config_rsp_msg_v01_ei,
  2197. resp);
  2198. if (ret < 0) {
  2199. cnss_pr_err("CNSS->IMS: TWT_CFG_REQ: QMI Txn Init Err: %d\n",
  2200. ret);
  2201. goto out;
  2202. }
  2203. ret =
  2204. qmi_send_request(&plat_priv->ims_qmi, NULL, &txn,
  2205. QMI_IMS_PRIVATE_SERVICE_WFC_CALL_TWT_CONFIG_REQ_V01,
  2206. IMS_PRIVATE_SERVICE_WFC_CALL_TWT_CONFIG_REQ_MSG_V01_MAX_MSG_LEN,
  2207. ims_private_service_wfc_call_twt_config_req_msg_v01_ei, req);
  2208. if (ret < 0) {
  2209. qmi_txn_cancel(&txn);
  2210. cnss_pr_err("CNSS->IMS: TWT_CFG_REQ: QMI Send Err: %d\n", ret);
  2211. goto out;
  2212. }
  2213. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2214. if (ret < 0) {
  2215. cnss_pr_err("IMS->CNSS: TWT_CFG_RSP: QMI Wait Err: %d\n", ret);
  2216. goto out;
  2217. }
  2218. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2219. cnss_pr_err("IMS->CNSS: TWT_CFG_RSP: Result: %d Err: %d\n",
  2220. resp->resp.result, resp->resp.error);
  2221. ret = -resp->resp.result;
  2222. goto out;
  2223. }
  2224. ret = 0;
  2225. out:
  2226. kfree(req);
  2227. kfree(resp);
  2228. return ret;
  2229. }
  2230. int cnss_process_twt_cfg_ind_event(struct cnss_plat_data *plat_priv,
  2231. void *data)
  2232. {
  2233. int ret;
  2234. struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg = data;
  2235. ret = cnss_ims_wfc_call_twt_cfg_send_sync(plat_priv, ind_msg);
  2236. kfree(data);
  2237. return ret;
  2238. }
  2239. static void cnss_wlfw_process_twt_cfg_ind(struct qmi_handle *qmi_wlfw,
  2240. struct sockaddr_qrtr *sq,
  2241. struct qmi_txn *txn,
  2242. const void *data)
  2243. {
  2244. struct cnss_plat_data *plat_priv =
  2245. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2246. const struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg = data;
  2247. struct wlfw_wfc_call_twt_config_ind_msg_v01 *event_data;
  2248. if (!txn) {
  2249. cnss_pr_err("FW->CNSS: TWT_CFG_IND: Spurious indication\n");
  2250. return;
  2251. }
  2252. if (!ind_msg) {
  2253. cnss_pr_err("FW->CNSS: TWT_CFG_IND: Invalid indication\n");
  2254. return;
  2255. }
  2256. cnss_pr_dbg("FW->CNSS: TWT_CFG_IND: %x %llx, %x %x, %x %x, %x %x, %x %x, %x %x\n",
  2257. ind_msg->twt_sta_start_valid, ind_msg->twt_sta_start,
  2258. ind_msg->twt_sta_int_valid, ind_msg->twt_sta_int,
  2259. ind_msg->twt_sta_upo_valid, ind_msg->twt_sta_upo,
  2260. ind_msg->twt_sta_sp_valid, ind_msg->twt_sta_sp,
  2261. ind_msg->twt_sta_dl_valid, ind_msg->twt_sta_dl,
  2262. ind_msg->twt_sta_config_changed_valid,
  2263. ind_msg->twt_sta_config_changed);
  2264. event_data = kmemdup(ind_msg, sizeof(*event_data), GFP_KERNEL);
  2265. if (!event_data)
  2266. return;
  2267. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND, 0,
  2268. event_data);
  2269. }
  2270. static struct qmi_msg_handler qmi_wlfw_msg_handlers[] = {
  2271. {
  2272. .type = QMI_INDICATION,
  2273. .msg_id = QMI_WLFW_REQUEST_MEM_IND_V01,
  2274. .ei = wlfw_request_mem_ind_msg_v01_ei,
  2275. .decoded_size = sizeof(struct wlfw_request_mem_ind_msg_v01),
  2276. .fn = cnss_wlfw_request_mem_ind_cb
  2277. },
  2278. {
  2279. .type = QMI_INDICATION,
  2280. .msg_id = QMI_WLFW_FW_MEM_READY_IND_V01,
  2281. .ei = wlfw_fw_mem_ready_ind_msg_v01_ei,
  2282. .decoded_size = sizeof(struct wlfw_fw_mem_ready_ind_msg_v01),
  2283. .fn = cnss_wlfw_fw_mem_ready_ind_cb
  2284. },
  2285. {
  2286. .type = QMI_INDICATION,
  2287. .msg_id = QMI_WLFW_FW_READY_IND_V01,
  2288. .ei = wlfw_fw_ready_ind_msg_v01_ei,
  2289. .decoded_size = sizeof(struct wlfw_fw_ready_ind_msg_v01),
  2290. .fn = cnss_wlfw_fw_ready_ind_cb
  2291. },
  2292. {
  2293. .type = QMI_INDICATION,
  2294. .msg_id = QMI_WLFW_FW_INIT_DONE_IND_V01,
  2295. .ei = wlfw_fw_init_done_ind_msg_v01_ei,
  2296. .decoded_size = sizeof(struct wlfw_fw_init_done_ind_msg_v01),
  2297. .fn = cnss_wlfw_fw_init_done_ind_cb
  2298. },
  2299. {
  2300. .type = QMI_INDICATION,
  2301. .msg_id = QMI_WLFW_PIN_CONNECT_RESULT_IND_V01,
  2302. .ei = wlfw_pin_connect_result_ind_msg_v01_ei,
  2303. .decoded_size =
  2304. sizeof(struct wlfw_pin_connect_result_ind_msg_v01),
  2305. .fn = cnss_wlfw_pin_result_ind_cb
  2306. },
  2307. {
  2308. .type = QMI_INDICATION,
  2309. .msg_id = QMI_WLFW_CAL_DONE_IND_V01,
  2310. .ei = wlfw_cal_done_ind_msg_v01_ei,
  2311. .decoded_size = sizeof(struct wlfw_cal_done_ind_msg_v01),
  2312. .fn = cnss_wlfw_cal_done_ind_cb
  2313. },
  2314. {
  2315. .type = QMI_INDICATION,
  2316. .msg_id = QMI_WLFW_QDSS_TRACE_REQ_MEM_IND_V01,
  2317. .ei = wlfw_qdss_trace_req_mem_ind_msg_v01_ei,
  2318. .decoded_size =
  2319. sizeof(struct wlfw_qdss_trace_req_mem_ind_msg_v01),
  2320. .fn = cnss_wlfw_qdss_trace_req_mem_ind_cb
  2321. },
  2322. {
  2323. .type = QMI_INDICATION,
  2324. .msg_id = QMI_WLFW_QDSS_TRACE_SAVE_IND_V01,
  2325. .ei = wlfw_qdss_trace_save_ind_msg_v01_ei,
  2326. .decoded_size =
  2327. sizeof(struct wlfw_qdss_trace_save_ind_msg_v01),
  2328. .fn = cnss_wlfw_fw_mem_file_save_ind_cb
  2329. },
  2330. {
  2331. .type = QMI_INDICATION,
  2332. .msg_id = QMI_WLFW_QDSS_TRACE_FREE_IND_V01,
  2333. .ei = wlfw_qdss_trace_free_ind_msg_v01_ei,
  2334. .decoded_size =
  2335. sizeof(struct wlfw_qdss_trace_free_ind_msg_v01),
  2336. .fn = cnss_wlfw_qdss_trace_free_ind_cb
  2337. },
  2338. {
  2339. .type = QMI_INDICATION,
  2340. .msg_id = QMI_WLFW_RESPOND_GET_INFO_IND_V01,
  2341. .ei = wlfw_respond_get_info_ind_msg_v01_ei,
  2342. .decoded_size =
  2343. sizeof(struct wlfw_respond_get_info_ind_msg_v01),
  2344. .fn = cnss_wlfw_respond_get_info_ind_cb
  2345. },
  2346. {
  2347. .type = QMI_INDICATION,
  2348. .msg_id = QMI_WLFW_WFC_CALL_TWT_CONFIG_IND_V01,
  2349. .ei = wlfw_wfc_call_twt_config_ind_msg_v01_ei,
  2350. .decoded_size =
  2351. sizeof(struct wlfw_wfc_call_twt_config_ind_msg_v01),
  2352. .fn = cnss_wlfw_process_twt_cfg_ind
  2353. },
  2354. {}
  2355. };
  2356. static int cnss_wlfw_connect_to_server(struct cnss_plat_data *plat_priv,
  2357. void *data)
  2358. {
  2359. struct cnss_qmi_event_server_arrive_data *event_data = data;
  2360. struct qmi_handle *qmi_wlfw = &plat_priv->qmi_wlfw;
  2361. struct sockaddr_qrtr sq = { 0 };
  2362. int ret = 0;
  2363. if (!event_data)
  2364. return -EINVAL;
  2365. sq.sq_family = AF_QIPCRTR;
  2366. sq.sq_node = event_data->node;
  2367. sq.sq_port = event_data->port;
  2368. ret = kernel_connect(qmi_wlfw->sock, (struct sockaddr *)&sq,
  2369. sizeof(sq), 0);
  2370. if (ret < 0) {
  2371. cnss_pr_err("Failed to connect to QMI WLFW remote service port\n");
  2372. goto out;
  2373. }
  2374. set_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state);
  2375. cnss_pr_info("QMI WLFW service connected, state: 0x%lx\n",
  2376. plat_priv->driver_state);
  2377. kfree(data);
  2378. return 0;
  2379. out:
  2380. CNSS_QMI_ASSERT();
  2381. kfree(data);
  2382. return ret;
  2383. }
  2384. int cnss_wlfw_server_arrive(struct cnss_plat_data *plat_priv, void *data)
  2385. {
  2386. int ret = 0;
  2387. if (!plat_priv)
  2388. return -ENODEV;
  2389. if (test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state)) {
  2390. cnss_pr_err("Unexpected WLFW server arrive\n");
  2391. CNSS_ASSERT(0);
  2392. return -EINVAL;
  2393. }
  2394. cnss_ignore_qmi_failure(false);
  2395. ret = cnss_wlfw_connect_to_server(plat_priv, data);
  2396. if (ret < 0)
  2397. goto out;
  2398. ret = cnss_wlfw_ind_register_send_sync(plat_priv);
  2399. if (ret < 0) {
  2400. if (ret == -EALREADY)
  2401. ret = 0;
  2402. goto out;
  2403. }
  2404. ret = cnss_wlfw_host_cap_send_sync(plat_priv);
  2405. if (ret < 0)
  2406. goto out;
  2407. return 0;
  2408. out:
  2409. return ret;
  2410. }
  2411. int cnss_wlfw_server_exit(struct cnss_plat_data *plat_priv)
  2412. {
  2413. int ret;
  2414. if (!plat_priv)
  2415. return -ENODEV;
  2416. clear_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state);
  2417. cnss_pr_info("QMI WLFW service disconnected, state: 0x%lx\n",
  2418. plat_priv->driver_state);
  2419. cnss_qmi_deinit(plat_priv);
  2420. clear_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state);
  2421. ret = cnss_qmi_init(plat_priv);
  2422. if (ret < 0) {
  2423. cnss_pr_err("QMI WLFW service registraton failed, ret\n", ret);
  2424. CNSS_ASSERT(0);
  2425. }
  2426. return 0;
  2427. }
  2428. static int wlfw_new_server(struct qmi_handle *qmi_wlfw,
  2429. struct qmi_service *service)
  2430. {
  2431. struct cnss_plat_data *plat_priv =
  2432. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2433. struct cnss_qmi_event_server_arrive_data *event_data;
  2434. if (plat_priv && test_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state)) {
  2435. cnss_pr_info("WLFW server delete in progress, Ignore server arrive, state: 0x%lx\n",
  2436. plat_priv->driver_state);
  2437. return 0;
  2438. }
  2439. cnss_pr_dbg("WLFW server arriving: node %u port %u\n",
  2440. service->node, service->port);
  2441. event_data = kzalloc(sizeof(*event_data), GFP_KERNEL);
  2442. if (!event_data)
  2443. return -ENOMEM;
  2444. event_data->node = service->node;
  2445. event_data->port = service->port;
  2446. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_SERVER_ARRIVE,
  2447. 0, event_data);
  2448. return 0;
  2449. }
  2450. static void wlfw_del_server(struct qmi_handle *qmi_wlfw,
  2451. struct qmi_service *service)
  2452. {
  2453. struct cnss_plat_data *plat_priv =
  2454. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2455. if (plat_priv && test_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state)) {
  2456. cnss_pr_info("WLFW server delete in progress, Ignore server delete, state: 0x%lx\n",
  2457. plat_priv->driver_state);
  2458. return;
  2459. }
  2460. cnss_pr_dbg("WLFW server exiting\n");
  2461. if (plat_priv) {
  2462. cnss_ignore_qmi_failure(true);
  2463. set_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state);
  2464. }
  2465. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_SERVER_EXIT,
  2466. 0, NULL);
  2467. }
  2468. static struct qmi_ops qmi_wlfw_ops = {
  2469. .new_server = wlfw_new_server,
  2470. .del_server = wlfw_del_server,
  2471. };
  2472. int cnss_qmi_init(struct cnss_plat_data *plat_priv)
  2473. {
  2474. int ret = 0;
  2475. ret = qmi_handle_init(&plat_priv->qmi_wlfw,
  2476. QMI_WLFW_MAX_RECV_BUF_SIZE,
  2477. &qmi_wlfw_ops, qmi_wlfw_msg_handlers);
  2478. if (ret < 0) {
  2479. cnss_pr_err("Failed to initialize WLFW QMI handle, err: %d\n",
  2480. ret);
  2481. goto out;
  2482. }
  2483. ret = qmi_add_lookup(&plat_priv->qmi_wlfw, WLFW_SERVICE_ID_V01,
  2484. WLFW_SERVICE_VERS_V01, WLFW_SERVICE_INS_ID_V01);
  2485. if (ret < 0)
  2486. cnss_pr_err("Failed to add WLFW QMI lookup, err: %d\n", ret);
  2487. out:
  2488. return ret;
  2489. }
  2490. void cnss_qmi_deinit(struct cnss_plat_data *plat_priv)
  2491. {
  2492. qmi_handle_release(&plat_priv->qmi_wlfw);
  2493. }
  2494. int cnss_qmi_get_dms_mac(struct cnss_plat_data *plat_priv)
  2495. {
  2496. struct dms_get_mac_address_req_msg_v01 req;
  2497. struct dms_get_mac_address_resp_msg_v01 resp;
  2498. struct qmi_txn txn;
  2499. int ret = 0;
  2500. if (!test_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state)) {
  2501. cnss_pr_err("DMS QMI connection not established\n");
  2502. return -EINVAL;
  2503. }
  2504. cnss_pr_dbg("Requesting DMS MAC address");
  2505. memset(&resp, 0, sizeof(resp));
  2506. ret = qmi_txn_init(&plat_priv->qmi_dms, &txn,
  2507. dms_get_mac_address_resp_msg_v01_ei, &resp);
  2508. if (ret < 0) {
  2509. cnss_pr_err("Failed to initialize txn for dms, err: %d\n",
  2510. ret);
  2511. goto out;
  2512. }
  2513. req.device = DMS_DEVICE_MAC_WLAN_V01;
  2514. ret = qmi_send_request(&plat_priv->qmi_dms, NULL, &txn,
  2515. QMI_DMS_GET_MAC_ADDRESS_REQ_V01,
  2516. DMS_GET_MAC_ADDRESS_REQ_MSG_V01_MAX_MSG_LEN,
  2517. dms_get_mac_address_req_msg_v01_ei, &req);
  2518. if (ret < 0) {
  2519. qmi_txn_cancel(&txn);
  2520. cnss_pr_err("Failed to send QMI_DMS_GET_MAC_ADDRESS_REQ_V01, err: %d\n",
  2521. ret);
  2522. goto out;
  2523. }
  2524. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2525. if (ret < 0) {
  2526. cnss_pr_err("Failed to wait for QMI_DMS_GET_MAC_ADDRESS_RESP_V01, err: %d\n",
  2527. ret);
  2528. goto out;
  2529. }
  2530. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  2531. cnss_pr_err("QMI_DMS_GET_MAC_ADDRESS_REQ_V01 failed, result: %d, err: %d\n",
  2532. resp.resp.result, resp.resp.error);
  2533. ret = -resp.resp.result;
  2534. goto out;
  2535. }
  2536. if (!resp.mac_address_valid ||
  2537. resp.mac_address_len != QMI_WLFW_MAC_ADDR_SIZE_V01) {
  2538. cnss_pr_err("Invalid MAC address received from DMS\n");
  2539. plat_priv->dms.mac_valid = false;
  2540. goto out;
  2541. }
  2542. plat_priv->dms.mac_valid = true;
  2543. memcpy(plat_priv->dms.mac, resp.mac_address, QMI_WLFW_MAC_ADDR_SIZE_V01);
  2544. cnss_pr_info("Received DMS MAC: [%pM]\n", plat_priv->dms.mac);
  2545. out:
  2546. return ret;
  2547. }
  2548. static int cnss_dms_connect_to_server(struct cnss_plat_data *plat_priv,
  2549. unsigned int node, unsigned int port)
  2550. {
  2551. struct qmi_handle *qmi_dms = &plat_priv->qmi_dms;
  2552. struct sockaddr_qrtr sq = {0};
  2553. int ret = 0;
  2554. sq.sq_family = AF_QIPCRTR;
  2555. sq.sq_node = node;
  2556. sq.sq_port = port;
  2557. ret = kernel_connect(qmi_dms->sock, (struct sockaddr *)&sq,
  2558. sizeof(sq), 0);
  2559. if (ret < 0) {
  2560. cnss_pr_err("Failed to connect to QMI DMS remote service Node: %d Port: %d\n",
  2561. node, port);
  2562. goto out;
  2563. }
  2564. set_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state);
  2565. cnss_pr_info("QMI DMS service connected, state: 0x%lx\n",
  2566. plat_priv->driver_state);
  2567. out:
  2568. return ret;
  2569. }
  2570. static int dms_new_server(struct qmi_handle *qmi_dms,
  2571. struct qmi_service *service)
  2572. {
  2573. struct cnss_plat_data *plat_priv =
  2574. container_of(qmi_dms, struct cnss_plat_data, qmi_dms);
  2575. if (!service)
  2576. return -EINVAL;
  2577. return cnss_dms_connect_to_server(plat_priv, service->node,
  2578. service->port);
  2579. }
  2580. static void dms_del_server(struct qmi_handle *qmi_dms,
  2581. struct qmi_service *service)
  2582. {
  2583. struct cnss_plat_data *plat_priv =
  2584. container_of(qmi_dms, struct cnss_plat_data, qmi_dms);
  2585. clear_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state);
  2586. cnss_pr_info("QMI DMS service disconnected, state: 0x%lx\n",
  2587. plat_priv->driver_state);
  2588. }
  2589. static struct qmi_ops qmi_dms_ops = {
  2590. .new_server = dms_new_server,
  2591. .del_server = dms_del_server,
  2592. };
  2593. int cnss_dms_init(struct cnss_plat_data *plat_priv)
  2594. {
  2595. int ret = 0;
  2596. ret = qmi_handle_init(&plat_priv->qmi_dms, DMS_QMI_MAX_MSG_LEN,
  2597. &qmi_dms_ops, NULL);
  2598. if (ret < 0) {
  2599. cnss_pr_err("Failed to initialize DMS handle, err: %d\n", ret);
  2600. goto out;
  2601. }
  2602. ret = qmi_add_lookup(&plat_priv->qmi_dms, DMS_SERVICE_ID_V01,
  2603. DMS_SERVICE_VERS_V01, 0);
  2604. if (ret < 0)
  2605. cnss_pr_err("Failed to add DMS lookup, err: %d\n", ret);
  2606. out:
  2607. return ret;
  2608. }
  2609. void cnss_dms_deinit(struct cnss_plat_data *plat_priv)
  2610. {
  2611. qmi_handle_release(&plat_priv->qmi_dms);
  2612. }
  2613. int coex_antenna_switch_to_wlan_send_sync_msg(struct cnss_plat_data *plat_priv)
  2614. {
  2615. int ret;
  2616. struct coex_antenna_switch_to_wlan_req_msg_v01 *req;
  2617. struct coex_antenna_switch_to_wlan_resp_msg_v01 *resp;
  2618. struct qmi_txn txn;
  2619. if (!plat_priv)
  2620. return -ENODEV;
  2621. cnss_pr_dbg("Sending coex antenna switch_to_wlan\n");
  2622. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2623. if (!req)
  2624. return -ENOMEM;
  2625. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2626. if (!resp) {
  2627. kfree(req);
  2628. return -ENOMEM;
  2629. }
  2630. req->antenna = plat_priv->antenna;
  2631. ret = qmi_txn_init(&plat_priv->coex_qmi, &txn,
  2632. coex_antenna_switch_to_wlan_resp_msg_v01_ei, resp);
  2633. if (ret < 0) {
  2634. cnss_pr_err("Fail to init txn for coex antenna switch_to_wlan resp %d\n",
  2635. ret);
  2636. goto out;
  2637. }
  2638. ret = qmi_send_request
  2639. (&plat_priv->coex_qmi, NULL, &txn,
  2640. QMI_COEX_SWITCH_ANTENNA_TO_WLAN_REQ_V01,
  2641. COEX_ANTENNA_SWITCH_TO_WLAN_REQ_MSG_V01_MAX_MSG_LEN,
  2642. coex_antenna_switch_to_wlan_req_msg_v01_ei, req);
  2643. if (ret < 0) {
  2644. qmi_txn_cancel(&txn);
  2645. cnss_pr_err("Fail to send coex antenna switch_to_wlan req %d\n",
  2646. ret);
  2647. goto out;
  2648. }
  2649. ret = qmi_txn_wait(&txn, COEX_TIMEOUT);
  2650. if (ret < 0) {
  2651. cnss_pr_err("Coex antenna switch_to_wlan resp wait failed with ret %d\n",
  2652. ret);
  2653. goto out;
  2654. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2655. cnss_pr_err("Coex antenna switch_to_wlan request rejected, result:%d error:%d\n",
  2656. resp->resp.result, resp->resp.error);
  2657. ret = -resp->resp.result;
  2658. goto out;
  2659. }
  2660. if (resp->grant_valid)
  2661. plat_priv->grant = resp->grant;
  2662. cnss_pr_dbg("Coex antenna grant: 0x%llx\n", resp->grant);
  2663. kfree(resp);
  2664. kfree(req);
  2665. return 0;
  2666. out:
  2667. kfree(resp);
  2668. kfree(req);
  2669. return ret;
  2670. }
  2671. int coex_antenna_switch_to_mdm_send_sync_msg(struct cnss_plat_data *plat_priv)
  2672. {
  2673. int ret;
  2674. struct coex_antenna_switch_to_mdm_req_msg_v01 *req;
  2675. struct coex_antenna_switch_to_mdm_resp_msg_v01 *resp;
  2676. struct qmi_txn txn;
  2677. if (!plat_priv)
  2678. return -ENODEV;
  2679. cnss_pr_dbg("Sending coex antenna switch_to_mdm\n");
  2680. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2681. if (!req)
  2682. return -ENOMEM;
  2683. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2684. if (!resp) {
  2685. kfree(req);
  2686. return -ENOMEM;
  2687. }
  2688. req->antenna = plat_priv->antenna;
  2689. ret = qmi_txn_init(&plat_priv->coex_qmi, &txn,
  2690. coex_antenna_switch_to_mdm_resp_msg_v01_ei, resp);
  2691. if (ret < 0) {
  2692. cnss_pr_err("Fail to init txn for coex antenna switch_to_mdm resp %d\n",
  2693. ret);
  2694. goto out;
  2695. }
  2696. ret = qmi_send_request
  2697. (&plat_priv->coex_qmi, NULL, &txn,
  2698. QMI_COEX_SWITCH_ANTENNA_TO_MDM_REQ_V01,
  2699. COEX_ANTENNA_SWITCH_TO_MDM_REQ_MSG_V01_MAX_MSG_LEN,
  2700. coex_antenna_switch_to_mdm_req_msg_v01_ei, req);
  2701. if (ret < 0) {
  2702. qmi_txn_cancel(&txn);
  2703. cnss_pr_err("Fail to send coex antenna switch_to_mdm req %d\n",
  2704. ret);
  2705. goto out;
  2706. }
  2707. ret = qmi_txn_wait(&txn, COEX_TIMEOUT);
  2708. if (ret < 0) {
  2709. cnss_pr_err("Coex antenna switch_to_mdm resp wait failed with ret %d\n",
  2710. ret);
  2711. goto out;
  2712. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2713. cnss_pr_err("Coex antenna switch_to_mdm request rejected, result:%d error:%d\n",
  2714. resp->resp.result, resp->resp.error);
  2715. ret = -resp->resp.result;
  2716. goto out;
  2717. }
  2718. kfree(resp);
  2719. kfree(req);
  2720. return 0;
  2721. out:
  2722. kfree(resp);
  2723. kfree(req);
  2724. return ret;
  2725. }
  2726. static int coex_new_server(struct qmi_handle *qmi,
  2727. struct qmi_service *service)
  2728. {
  2729. struct cnss_plat_data *plat_priv =
  2730. container_of(qmi, struct cnss_plat_data, coex_qmi);
  2731. struct sockaddr_qrtr sq = { 0 };
  2732. int ret = 0;
  2733. cnss_pr_dbg("COEX server arrive: node %u port %u\n",
  2734. service->node, service->port);
  2735. sq.sq_family = AF_QIPCRTR;
  2736. sq.sq_node = service->node;
  2737. sq.sq_port = service->port;
  2738. ret = kernel_connect(qmi->sock, (struct sockaddr *)&sq, sizeof(sq), 0);
  2739. if (ret < 0) {
  2740. cnss_pr_err("Fail to connect to remote service port\n");
  2741. return ret;
  2742. }
  2743. set_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state);
  2744. cnss_pr_dbg("COEX Server Connected: 0x%lx\n",
  2745. plat_priv->driver_state);
  2746. return 0;
  2747. }
  2748. static void coex_del_server(struct qmi_handle *qmi,
  2749. struct qmi_service *service)
  2750. {
  2751. struct cnss_plat_data *plat_priv =
  2752. container_of(qmi, struct cnss_plat_data, coex_qmi);
  2753. cnss_pr_dbg("COEX server exit\n");
  2754. clear_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state);
  2755. }
  2756. static struct qmi_ops coex_qmi_ops = {
  2757. .new_server = coex_new_server,
  2758. .del_server = coex_del_server,
  2759. };
  2760. int cnss_register_coex_service(struct cnss_plat_data *plat_priv)
  2761. { int ret;
  2762. ret = qmi_handle_init(&plat_priv->coex_qmi,
  2763. COEX_SERVICE_MAX_MSG_LEN,
  2764. &coex_qmi_ops, NULL);
  2765. if (ret < 0)
  2766. return ret;
  2767. ret = qmi_add_lookup(&plat_priv->coex_qmi, COEX_SERVICE_ID_V01,
  2768. COEX_SERVICE_VERS_V01, 0);
  2769. return ret;
  2770. }
  2771. void cnss_unregister_coex_service(struct cnss_plat_data *plat_priv)
  2772. {
  2773. qmi_handle_release(&plat_priv->coex_qmi);
  2774. }
  2775. /* IMS Service */
  2776. int ims_subscribe_for_indication_send_async(struct cnss_plat_data *plat_priv)
  2777. {
  2778. int ret;
  2779. struct ims_private_service_subscribe_for_indications_req_msg_v01 *req;
  2780. struct qmi_txn *txn;
  2781. if (!plat_priv)
  2782. return -ENODEV;
  2783. cnss_pr_dbg("Sending ASYNC ims subscribe for indication\n");
  2784. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2785. if (!req)
  2786. return -ENOMEM;
  2787. req->wfc_call_status_valid = 1;
  2788. req->wfc_call_status = 1;
  2789. txn = &plat_priv->txn;
  2790. ret = qmi_txn_init(&plat_priv->ims_qmi, txn, NULL, NULL);
  2791. if (ret < 0) {
  2792. cnss_pr_err("Fail to init txn for ims subscribe for indication resp %d\n",
  2793. ret);
  2794. goto out;
  2795. }
  2796. ret = qmi_send_request
  2797. (&plat_priv->ims_qmi, NULL, txn,
  2798. QMI_IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_V01,
  2799. IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_MSG_V01_MAX_MSG_LEN,
  2800. ims_private_service_subscribe_for_indications_req_msg_v01_ei, req);
  2801. if (ret < 0) {
  2802. qmi_txn_cancel(txn);
  2803. cnss_pr_err("Fail to send ims subscribe for indication req %d\n",
  2804. ret);
  2805. goto out;
  2806. }
  2807. kfree(req);
  2808. return 0;
  2809. out:
  2810. kfree(req);
  2811. return ret;
  2812. }
  2813. static void ims_subscribe_for_indication_resp_cb(struct qmi_handle *qmi,
  2814. struct sockaddr_qrtr *sq,
  2815. struct qmi_txn *txn,
  2816. const void *data)
  2817. {
  2818. const
  2819. struct ims_private_service_subscribe_for_indications_rsp_msg_v01 *resp =
  2820. data;
  2821. cnss_pr_dbg("Received IMS subscribe indication response\n");
  2822. if (!txn) {
  2823. cnss_pr_err("spurious response\n");
  2824. return;
  2825. }
  2826. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2827. cnss_pr_err("IMS subscribe for indication request rejected, result:%d error:%d\n",
  2828. resp->resp.result, resp->resp.error);
  2829. txn->result = -resp->resp.result;
  2830. }
  2831. }
  2832. int cnss_process_wfc_call_ind_event(struct cnss_plat_data *plat_priv,
  2833. void *data)
  2834. {
  2835. int ret;
  2836. struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg = data;
  2837. ret = cnss_wlfw_wfc_call_status_send_sync(plat_priv, ind_msg);
  2838. kfree(data);
  2839. return ret;
  2840. }
  2841. static void
  2842. cnss_ims_process_wfc_call_ind_cb(struct qmi_handle *ims_qmi,
  2843. struct sockaddr_qrtr *sq,
  2844. struct qmi_txn *txn, const void *data)
  2845. {
  2846. struct cnss_plat_data *plat_priv =
  2847. container_of(ims_qmi, struct cnss_plat_data, ims_qmi);
  2848. const
  2849. struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg = data;
  2850. struct ims_private_service_wfc_call_status_ind_msg_v01 *event_data;
  2851. if (!txn) {
  2852. cnss_pr_err("IMS->CNSS: WFC_CALL_IND: Spurious indication\n");
  2853. return;
  2854. }
  2855. if (!ind_msg) {
  2856. cnss_pr_err("IMS->CNSS: WFC_CALL_IND: Invalid indication\n");
  2857. return;
  2858. }
  2859. cnss_pr_dbg("IMS->CNSS: WFC_CALL_IND: %x, %x %x, %x %x, %x %llx, %x %x, %x %x\n",
  2860. ind_msg->wfc_call_active, ind_msg->all_wfc_calls_held_valid,
  2861. ind_msg->all_wfc_calls_held,
  2862. ind_msg->is_wfc_emergency_valid, ind_msg->is_wfc_emergency,
  2863. ind_msg->twt_ims_start_valid, ind_msg->twt_ims_start,
  2864. ind_msg->twt_ims_int_valid, ind_msg->twt_ims_int,
  2865. ind_msg->media_quality_valid, ind_msg->media_quality);
  2866. event_data = kmemdup(ind_msg, sizeof(*event_data), GFP_KERNEL);
  2867. if (!event_data)
  2868. return;
  2869. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND,
  2870. 0, event_data);
  2871. }
  2872. static struct qmi_msg_handler qmi_ims_msg_handlers[] = {
  2873. {
  2874. .type = QMI_RESPONSE,
  2875. .msg_id =
  2876. QMI_IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_V01,
  2877. .ei =
  2878. ims_private_service_subscribe_for_indications_rsp_msg_v01_ei,
  2879. .decoded_size = sizeof(struct
  2880. ims_private_service_subscribe_for_indications_rsp_msg_v01),
  2881. .fn = ims_subscribe_for_indication_resp_cb
  2882. },
  2883. {
  2884. .type = QMI_INDICATION,
  2885. .msg_id = QMI_IMS_PRIVATE_SERVICE_WFC_CALL_STATUS_IND_V01,
  2886. .ei = ims_private_service_wfc_call_status_ind_msg_v01_ei,
  2887. .decoded_size =
  2888. sizeof(struct ims_private_service_wfc_call_status_ind_msg_v01),
  2889. .fn = cnss_ims_process_wfc_call_ind_cb
  2890. },
  2891. {}
  2892. };
  2893. static int ims_new_server(struct qmi_handle *qmi,
  2894. struct qmi_service *service)
  2895. {
  2896. struct cnss_plat_data *plat_priv =
  2897. container_of(qmi, struct cnss_plat_data, ims_qmi);
  2898. struct sockaddr_qrtr sq = { 0 };
  2899. int ret = 0;
  2900. cnss_pr_dbg("IMS server arrive: node %u port %u\n",
  2901. service->node, service->port);
  2902. sq.sq_family = AF_QIPCRTR;
  2903. sq.sq_node = service->node;
  2904. sq.sq_port = service->port;
  2905. ret = kernel_connect(qmi->sock, (struct sockaddr *)&sq, sizeof(sq), 0);
  2906. if (ret < 0) {
  2907. cnss_pr_err("Fail to connect to remote service port\n");
  2908. return ret;
  2909. }
  2910. set_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state);
  2911. cnss_pr_dbg("IMS Server Connected: 0x%lx\n",
  2912. plat_priv->driver_state);
  2913. ret = ims_subscribe_for_indication_send_async(plat_priv);
  2914. return ret;
  2915. }
  2916. static void ims_del_server(struct qmi_handle *qmi,
  2917. struct qmi_service *service)
  2918. {
  2919. struct cnss_plat_data *plat_priv =
  2920. container_of(qmi, struct cnss_plat_data, ims_qmi);
  2921. cnss_pr_dbg("IMS server exit\n");
  2922. clear_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state);
  2923. }
  2924. static struct qmi_ops ims_qmi_ops = {
  2925. .new_server = ims_new_server,
  2926. .del_server = ims_del_server,
  2927. };
  2928. int cnss_register_ims_service(struct cnss_plat_data *plat_priv)
  2929. { int ret;
  2930. ret = qmi_handle_init(&plat_priv->ims_qmi,
  2931. IMSPRIVATE_SERVICE_MAX_MSG_LEN,
  2932. &ims_qmi_ops, qmi_ims_msg_handlers);
  2933. if (ret < 0)
  2934. return ret;
  2935. ret = qmi_add_lookup(&plat_priv->ims_qmi, IMSPRIVATE_SERVICE_ID_V01,
  2936. IMSPRIVATE_SERVICE_VERS_V01, 0);
  2937. return ret;
  2938. }
  2939. void cnss_unregister_ims_service(struct cnss_plat_data *plat_priv)
  2940. {
  2941. qmi_handle_release(&plat_priv->ims_qmi);
  2942. }