dp_tx.c 138 KB

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  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #include "dp_ipa.h"
  31. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  32. #include "if_meta_hdr.h"
  33. #endif
  34. #include "enet.h"
  35. #include "dp_internal.h"
  36. #ifdef FEATURE_WDS
  37. #include "dp_txrx_wds.h"
  38. #endif
  39. #ifdef ATH_SUPPORT_IQUE
  40. #include "dp_txrx_me.h"
  41. #endif
  42. #include "dp_hist.h"
  43. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  44. #include <dp_swlm.h>
  45. #endif
  46. /* Flag to skip CCE classify when mesh or tid override enabled */
  47. #define DP_TX_SKIP_CCE_CLASSIFY \
  48. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  49. /* TODO Add support in TSO */
  50. #define DP_DESC_NUM_FRAG(x) 0
  51. /* disable TQM_BYPASS */
  52. #define TQM_BYPASS_WAR 0
  53. /* invalid peer id for reinject*/
  54. #define DP_INVALID_PEER 0XFFFE
  55. /*mapping between hal encrypt type and cdp_sec_type*/
  56. #define MAX_CDP_SEC_TYPE 12
  57. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  58. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  59. HAL_TX_ENCRYPT_TYPE_WEP_128,
  60. HAL_TX_ENCRYPT_TYPE_WEP_104,
  61. HAL_TX_ENCRYPT_TYPE_WEP_40,
  62. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  63. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  64. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  65. HAL_TX_ENCRYPT_TYPE_WAPI,
  66. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  67. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  68. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  69. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  70. #ifdef QCA_TX_LIMIT_CHECK
  71. /**
  72. * dp_tx_limit_check - Check if allocated tx descriptors reached
  73. * soc max limit and pdev max limit
  74. * @vdev: DP vdev handle
  75. *
  76. * Return: true if allocated tx descriptors reached max configured value, else
  77. * false
  78. */
  79. static inline bool
  80. dp_tx_limit_check(struct dp_vdev *vdev)
  81. {
  82. struct dp_pdev *pdev = vdev->pdev;
  83. struct dp_soc *soc = pdev->soc;
  84. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  85. soc->num_tx_allowed) {
  86. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  87. "%s: queued packets are more than max tx, drop the frame",
  88. __func__);
  89. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  90. return true;
  91. }
  92. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  93. pdev->num_tx_allowed) {
  94. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  95. "%s: queued packets are more than max tx, drop the frame",
  96. __func__);
  97. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  98. return true;
  99. }
  100. return false;
  101. }
  102. /**
  103. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  104. * reached soc max limit
  105. * @vdev: DP vdev handle
  106. *
  107. * Return: true if allocated tx descriptors reached max configured value, else
  108. * false
  109. */
  110. static inline bool
  111. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  112. {
  113. struct dp_pdev *pdev = vdev->pdev;
  114. struct dp_soc *soc = pdev->soc;
  115. if (qdf_atomic_read(&soc->num_tx_exception) >=
  116. soc->num_msdu_exception_desc) {
  117. dp_info("exc packets are more than max drop the exc pkt");
  118. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  119. return true;
  120. }
  121. return false;
  122. }
  123. /**
  124. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  125. * @vdev: DP pdev handle
  126. *
  127. * Return: void
  128. */
  129. static inline void
  130. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  131. {
  132. struct dp_soc *soc = pdev->soc;
  133. qdf_atomic_inc(&pdev->num_tx_outstanding);
  134. qdf_atomic_inc(&soc->num_tx_outstanding);
  135. }
  136. /**
  137. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  138. * @vdev: DP pdev handle
  139. *
  140. * Return: void
  141. */
  142. static inline void
  143. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  144. {
  145. struct dp_soc *soc = pdev->soc;
  146. qdf_atomic_dec(&pdev->num_tx_outstanding);
  147. qdf_atomic_dec(&soc->num_tx_outstanding);
  148. }
  149. #else //QCA_TX_LIMIT_CHECK
  150. static inline bool
  151. dp_tx_limit_check(struct dp_vdev *vdev)
  152. {
  153. return false;
  154. }
  155. static inline bool
  156. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  157. {
  158. return false;
  159. }
  160. static inline void
  161. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  162. {
  163. qdf_atomic_inc(&pdev->num_tx_outstanding);
  164. }
  165. static inline void
  166. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  167. {
  168. qdf_atomic_dec(&pdev->num_tx_outstanding);
  169. }
  170. #endif //QCA_TX_LIMIT_CHECK
  171. #if defined(FEATURE_TSO)
  172. /**
  173. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  174. *
  175. * @soc - core txrx main context
  176. * @seg_desc - tso segment descriptor
  177. * @num_seg_desc - tso number segment descriptor
  178. */
  179. static void dp_tx_tso_unmap_segment(
  180. struct dp_soc *soc,
  181. struct qdf_tso_seg_elem_t *seg_desc,
  182. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  183. {
  184. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  185. if (qdf_unlikely(!seg_desc)) {
  186. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  187. __func__, __LINE__);
  188. qdf_assert(0);
  189. } else if (qdf_unlikely(!num_seg_desc)) {
  190. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  191. __func__, __LINE__);
  192. qdf_assert(0);
  193. } else {
  194. bool is_last_seg;
  195. /* no tso segment left to do dma unmap */
  196. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  197. return;
  198. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  199. true : false;
  200. qdf_nbuf_unmap_tso_segment(soc->osdev,
  201. seg_desc, is_last_seg);
  202. num_seg_desc->num_seg.tso_cmn_num_seg--;
  203. }
  204. }
  205. /**
  206. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  207. * back to the freelist
  208. *
  209. * @soc - soc device handle
  210. * @tx_desc - Tx software descriptor
  211. */
  212. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  213. struct dp_tx_desc_s *tx_desc)
  214. {
  215. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  216. if (qdf_unlikely(!tx_desc->tso_desc)) {
  217. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  218. "%s %d TSO desc is NULL!",
  219. __func__, __LINE__);
  220. qdf_assert(0);
  221. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  222. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  223. "%s %d TSO num desc is NULL!",
  224. __func__, __LINE__);
  225. qdf_assert(0);
  226. } else {
  227. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  228. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  229. /* Add the tso num segment into the free list */
  230. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  231. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  232. tx_desc->tso_num_desc);
  233. tx_desc->tso_num_desc = NULL;
  234. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  235. }
  236. /* Add the tso segment into the free list*/
  237. dp_tx_tso_desc_free(soc,
  238. tx_desc->pool_id, tx_desc->tso_desc);
  239. tx_desc->tso_desc = NULL;
  240. }
  241. }
  242. #else
  243. static void dp_tx_tso_unmap_segment(
  244. struct dp_soc *soc,
  245. struct qdf_tso_seg_elem_t *seg_desc,
  246. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  247. {
  248. }
  249. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  250. struct dp_tx_desc_s *tx_desc)
  251. {
  252. }
  253. #endif
  254. /**
  255. * dp_tx_desc_release() - Release Tx Descriptor
  256. * @tx_desc : Tx Descriptor
  257. * @desc_pool_id: Descriptor Pool ID
  258. *
  259. * Deallocate all resources attached to Tx descriptor and free the Tx
  260. * descriptor.
  261. *
  262. * Return:
  263. */
  264. static void
  265. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  266. {
  267. struct dp_pdev *pdev = tx_desc->pdev;
  268. struct dp_soc *soc;
  269. uint8_t comp_status = 0;
  270. qdf_assert(pdev);
  271. soc = pdev->soc;
  272. dp_tx_outstanding_dec(pdev);
  273. if (tx_desc->frm_type == dp_tx_frm_tso)
  274. dp_tx_tso_desc_release(soc, tx_desc);
  275. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  276. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  277. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  278. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  279. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  280. qdf_atomic_dec(&soc->num_tx_exception);
  281. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  282. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  283. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  284. soc->hal_soc);
  285. else
  286. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  287. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  288. "Tx Completion Release desc %d status %d outstanding %d",
  289. tx_desc->id, comp_status,
  290. qdf_atomic_read(&pdev->num_tx_outstanding));
  291. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  292. return;
  293. }
  294. /**
  295. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  296. * @vdev: DP vdev Handle
  297. * @nbuf: skb
  298. * @msdu_info: msdu_info required to create HTT metadata
  299. *
  300. * Prepares and fills HTT metadata in the frame pre-header for special frames
  301. * that should be transmitted using varying transmit parameters.
  302. * There are 2 VDEV modes that currently needs this special metadata -
  303. * 1) Mesh Mode
  304. * 2) DSRC Mode
  305. *
  306. * Return: HTT metadata size
  307. *
  308. */
  309. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  310. struct dp_tx_msdu_info_s *msdu_info)
  311. {
  312. uint32_t *meta_data = msdu_info->meta_data;
  313. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  314. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  315. uint8_t htt_desc_size;
  316. /* Size rounded of multiple of 8 bytes */
  317. uint8_t htt_desc_size_aligned;
  318. uint8_t *hdr = NULL;
  319. /*
  320. * Metadata - HTT MSDU Extension header
  321. */
  322. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  323. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  324. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  325. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  326. meta_data[0])) {
  327. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  328. htt_desc_size_aligned)) {
  329. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  330. htt_desc_size_aligned);
  331. if (!nbuf) {
  332. /*
  333. * qdf_nbuf_realloc_headroom won't do skb_clone
  334. * as skb_realloc_headroom does. so, no free is
  335. * needed here.
  336. */
  337. DP_STATS_INC(vdev,
  338. tx_i.dropped.headroom_insufficient,
  339. 1);
  340. qdf_print(" %s[%d] skb_realloc_headroom failed",
  341. __func__, __LINE__);
  342. return 0;
  343. }
  344. }
  345. /* Fill and add HTT metaheader */
  346. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  347. if (!hdr) {
  348. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  349. "Error in filling HTT metadata");
  350. return 0;
  351. }
  352. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  353. } else if (vdev->opmode == wlan_op_mode_ocb) {
  354. /* Todo - Add support for DSRC */
  355. }
  356. return htt_desc_size_aligned;
  357. }
  358. /**
  359. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  360. * @tso_seg: TSO segment to process
  361. * @ext_desc: Pointer to MSDU extension descriptor
  362. *
  363. * Return: void
  364. */
  365. #if defined(FEATURE_TSO)
  366. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  367. void *ext_desc)
  368. {
  369. uint8_t num_frag;
  370. uint32_t tso_flags;
  371. /*
  372. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  373. * tcp_flag_mask
  374. *
  375. * Checksum enable flags are set in TCL descriptor and not in Extension
  376. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  377. */
  378. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  379. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  380. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  381. tso_seg->tso_flags.ip_len);
  382. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  383. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  384. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  385. uint32_t lo = 0;
  386. uint32_t hi = 0;
  387. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  388. (tso_seg->tso_frags[num_frag].length));
  389. qdf_dmaaddr_to_32s(
  390. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  391. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  392. tso_seg->tso_frags[num_frag].length);
  393. }
  394. return;
  395. }
  396. #else
  397. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  398. void *ext_desc)
  399. {
  400. return;
  401. }
  402. #endif
  403. #if defined(FEATURE_TSO)
  404. /**
  405. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  406. * allocated and free them
  407. *
  408. * @soc: soc handle
  409. * @free_seg: list of tso segments
  410. * @msdu_info: msdu descriptor
  411. *
  412. * Return - void
  413. */
  414. static void dp_tx_free_tso_seg_list(
  415. struct dp_soc *soc,
  416. struct qdf_tso_seg_elem_t *free_seg,
  417. struct dp_tx_msdu_info_s *msdu_info)
  418. {
  419. struct qdf_tso_seg_elem_t *next_seg;
  420. while (free_seg) {
  421. next_seg = free_seg->next;
  422. dp_tx_tso_desc_free(soc,
  423. msdu_info->tx_queue.desc_pool_id,
  424. free_seg);
  425. free_seg = next_seg;
  426. }
  427. }
  428. /**
  429. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  430. * allocated and free them
  431. *
  432. * @soc: soc handle
  433. * @free_num_seg: list of tso number segments
  434. * @msdu_info: msdu descriptor
  435. * Return - void
  436. */
  437. static void dp_tx_free_tso_num_seg_list(
  438. struct dp_soc *soc,
  439. struct qdf_tso_num_seg_elem_t *free_num_seg,
  440. struct dp_tx_msdu_info_s *msdu_info)
  441. {
  442. struct qdf_tso_num_seg_elem_t *next_num_seg;
  443. while (free_num_seg) {
  444. next_num_seg = free_num_seg->next;
  445. dp_tso_num_seg_free(soc,
  446. msdu_info->tx_queue.desc_pool_id,
  447. free_num_seg);
  448. free_num_seg = next_num_seg;
  449. }
  450. }
  451. /**
  452. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  453. * do dma unmap for each segment
  454. *
  455. * @soc: soc handle
  456. * @free_seg: list of tso segments
  457. * @num_seg_desc: tso number segment descriptor
  458. *
  459. * Return - void
  460. */
  461. static void dp_tx_unmap_tso_seg_list(
  462. struct dp_soc *soc,
  463. struct qdf_tso_seg_elem_t *free_seg,
  464. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  465. {
  466. struct qdf_tso_seg_elem_t *next_seg;
  467. if (qdf_unlikely(!num_seg_desc)) {
  468. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  469. return;
  470. }
  471. while (free_seg) {
  472. next_seg = free_seg->next;
  473. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  474. free_seg = next_seg;
  475. }
  476. }
  477. #ifdef FEATURE_TSO_STATS
  478. /**
  479. * dp_tso_get_stats_idx: Retrieve the tso packet id
  480. * @pdev - pdev handle
  481. *
  482. * Return: id
  483. */
  484. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  485. {
  486. uint32_t stats_idx;
  487. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  488. % CDP_MAX_TSO_PACKETS);
  489. return stats_idx;
  490. }
  491. #else
  492. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  493. {
  494. return 0;
  495. }
  496. #endif /* FEATURE_TSO_STATS */
  497. /**
  498. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  499. * free the tso segments descriptor and
  500. * tso num segments descriptor
  501. *
  502. * @soc: soc handle
  503. * @msdu_info: msdu descriptor
  504. * @tso_seg_unmap: flag to show if dma unmap is necessary
  505. *
  506. * Return - void
  507. */
  508. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  509. struct dp_tx_msdu_info_s *msdu_info,
  510. bool tso_seg_unmap)
  511. {
  512. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  513. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  514. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  515. tso_info->tso_num_seg_list;
  516. /* do dma unmap for each segment */
  517. if (tso_seg_unmap)
  518. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  519. /* free all tso number segment descriptor though looks only have 1 */
  520. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  521. /* free all tso segment descriptor */
  522. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  523. }
  524. /**
  525. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  526. * @vdev: virtual device handle
  527. * @msdu: network buffer
  528. * @msdu_info: meta data associated with the msdu
  529. *
  530. * Return: QDF_STATUS_SUCCESS success
  531. */
  532. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  533. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  534. {
  535. struct qdf_tso_seg_elem_t *tso_seg;
  536. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  537. struct dp_soc *soc = vdev->pdev->soc;
  538. struct dp_pdev *pdev = vdev->pdev;
  539. struct qdf_tso_info_t *tso_info;
  540. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  541. tso_info = &msdu_info->u.tso_info;
  542. tso_info->curr_seg = NULL;
  543. tso_info->tso_seg_list = NULL;
  544. tso_info->num_segs = num_seg;
  545. msdu_info->frm_type = dp_tx_frm_tso;
  546. tso_info->tso_num_seg_list = NULL;
  547. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  548. while (num_seg) {
  549. tso_seg = dp_tx_tso_desc_alloc(
  550. soc, msdu_info->tx_queue.desc_pool_id);
  551. if (tso_seg) {
  552. tso_seg->next = tso_info->tso_seg_list;
  553. tso_info->tso_seg_list = tso_seg;
  554. num_seg--;
  555. } else {
  556. dp_err_rl("Failed to alloc tso seg desc");
  557. DP_STATS_INC_PKT(vdev->pdev,
  558. tso_stats.tso_no_mem_dropped, 1,
  559. qdf_nbuf_len(msdu));
  560. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  561. return QDF_STATUS_E_NOMEM;
  562. }
  563. }
  564. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  565. tso_num_seg = dp_tso_num_seg_alloc(soc,
  566. msdu_info->tx_queue.desc_pool_id);
  567. if (tso_num_seg) {
  568. tso_num_seg->next = tso_info->tso_num_seg_list;
  569. tso_info->tso_num_seg_list = tso_num_seg;
  570. } else {
  571. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  572. __func__);
  573. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  574. return QDF_STATUS_E_NOMEM;
  575. }
  576. msdu_info->num_seg =
  577. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  578. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  579. msdu_info->num_seg);
  580. if (!(msdu_info->num_seg)) {
  581. /*
  582. * Free allocated TSO seg desc and number seg desc,
  583. * do unmap for segments if dma map has done.
  584. */
  585. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  586. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  587. return QDF_STATUS_E_INVAL;
  588. }
  589. tso_info->curr_seg = tso_info->tso_seg_list;
  590. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  591. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  592. msdu, msdu_info->num_seg);
  593. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  594. tso_info->msdu_stats_idx);
  595. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  596. return QDF_STATUS_SUCCESS;
  597. }
  598. #else
  599. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  600. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  601. {
  602. return QDF_STATUS_E_NOMEM;
  603. }
  604. #endif
  605. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  606. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  607. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  608. /**
  609. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  610. * @vdev: DP Vdev handle
  611. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  612. * @desc_pool_id: Descriptor Pool ID
  613. *
  614. * Return:
  615. */
  616. static
  617. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  618. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  619. {
  620. uint8_t i;
  621. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  622. struct dp_tx_seg_info_s *seg_info;
  623. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  624. struct dp_soc *soc = vdev->pdev->soc;
  625. /* Allocate an extension descriptor */
  626. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  627. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  628. if (!msdu_ext_desc) {
  629. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  630. return NULL;
  631. }
  632. if (msdu_info->exception_fw &&
  633. qdf_unlikely(vdev->mesh_vdev)) {
  634. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  635. &msdu_info->meta_data[0],
  636. sizeof(struct htt_tx_msdu_desc_ext2_t));
  637. qdf_atomic_inc(&soc->num_tx_exception);
  638. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  639. }
  640. switch (msdu_info->frm_type) {
  641. case dp_tx_frm_sg:
  642. case dp_tx_frm_me:
  643. case dp_tx_frm_raw:
  644. seg_info = msdu_info->u.sg_info.curr_seg;
  645. /* Update the buffer pointers in MSDU Extension Descriptor */
  646. for (i = 0; i < seg_info->frag_cnt; i++) {
  647. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  648. seg_info->frags[i].paddr_lo,
  649. seg_info->frags[i].paddr_hi,
  650. seg_info->frags[i].len);
  651. }
  652. break;
  653. case dp_tx_frm_tso:
  654. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  655. &cached_ext_desc[0]);
  656. break;
  657. default:
  658. break;
  659. }
  660. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  661. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  662. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  663. msdu_ext_desc->vaddr);
  664. return msdu_ext_desc;
  665. }
  666. /**
  667. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  668. *
  669. * @skb: skb to be traced
  670. * @msdu_id: msdu_id of the packet
  671. * @vdev_id: vdev_id of the packet
  672. *
  673. * Return: None
  674. */
  675. #ifdef DP_DISABLE_TX_PKT_TRACE
  676. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  677. uint8_t vdev_id)
  678. {
  679. }
  680. #else
  681. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  682. uint8_t vdev_id)
  683. {
  684. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  685. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  686. DPTRACE(qdf_dp_trace_ptr(skb,
  687. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  688. QDF_TRACE_DEFAULT_PDEV_ID,
  689. qdf_nbuf_data_addr(skb),
  690. sizeof(qdf_nbuf_data(skb)),
  691. msdu_id, vdev_id));
  692. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  693. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  694. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  695. msdu_id, QDF_TX));
  696. }
  697. #endif
  698. /**
  699. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  700. * @vdev: DP vdev handle
  701. * @nbuf: skb
  702. * @desc_pool_id: Descriptor pool ID
  703. * @meta_data: Metadata to the fw
  704. * @tx_exc_metadata: Handle that holds exception path metadata
  705. * Allocate and prepare Tx descriptor with msdu information.
  706. *
  707. * Return: Pointer to Tx Descriptor on success,
  708. * NULL on failure
  709. */
  710. static
  711. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  712. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  713. struct dp_tx_msdu_info_s *msdu_info,
  714. struct cdp_tx_exception_metadata *tx_exc_metadata)
  715. {
  716. uint8_t align_pad;
  717. uint8_t is_exception = 0;
  718. uint8_t htt_hdr_size;
  719. struct dp_tx_desc_s *tx_desc;
  720. struct dp_pdev *pdev = vdev->pdev;
  721. struct dp_soc *soc = pdev->soc;
  722. if (dp_tx_limit_check(vdev))
  723. return NULL;
  724. /* Allocate software Tx descriptor */
  725. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  726. if (qdf_unlikely(!tx_desc)) {
  727. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  728. return NULL;
  729. }
  730. dp_tx_outstanding_inc(pdev);
  731. /* Initialize the SW tx descriptor */
  732. tx_desc->nbuf = nbuf;
  733. tx_desc->frm_type = dp_tx_frm_std;
  734. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  735. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  736. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  737. tx_desc->vdev_id = vdev->vdev_id;
  738. tx_desc->pdev = pdev;
  739. tx_desc->msdu_ext_desc = NULL;
  740. tx_desc->pkt_offset = 0;
  741. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  742. if (qdf_unlikely(vdev->multipass_en)) {
  743. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  744. goto failure;
  745. }
  746. /*
  747. * For special modes (vdev_type == ocb or mesh), data frames should be
  748. * transmitted using varying transmit parameters (tx spec) which include
  749. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  750. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  751. * These frames are sent as exception packets to firmware.
  752. *
  753. * HW requirement is that metadata should always point to a
  754. * 8-byte aligned address. So we add alignment pad to start of buffer.
  755. * HTT Metadata should be ensured to be multiple of 8-bytes,
  756. * to get 8-byte aligned start address along with align_pad added
  757. *
  758. * |-----------------------------|
  759. * | |
  760. * |-----------------------------| <-----Buffer Pointer Address given
  761. * | | ^ in HW descriptor (aligned)
  762. * | HTT Metadata | |
  763. * | | |
  764. * | | | Packet Offset given in descriptor
  765. * | | |
  766. * |-----------------------------| |
  767. * | Alignment Pad | v
  768. * |-----------------------------| <----- Actual buffer start address
  769. * | SKB Data | (Unaligned)
  770. * | |
  771. * | |
  772. * | |
  773. * | |
  774. * | |
  775. * |-----------------------------|
  776. */
  777. if (qdf_unlikely((msdu_info->exception_fw)) ||
  778. (vdev->opmode == wlan_op_mode_ocb) ||
  779. (tx_exc_metadata &&
  780. tx_exc_metadata->is_tx_sniffer)) {
  781. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  782. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  783. DP_STATS_INC(vdev,
  784. tx_i.dropped.headroom_insufficient, 1);
  785. goto failure;
  786. }
  787. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  788. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  789. "qdf_nbuf_push_head failed");
  790. goto failure;
  791. }
  792. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  793. msdu_info);
  794. if (htt_hdr_size == 0)
  795. goto failure;
  796. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  797. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  798. is_exception = 1;
  799. }
  800. #if !TQM_BYPASS_WAR
  801. if (is_exception || tx_exc_metadata)
  802. #endif
  803. {
  804. /* Temporary WAR due to TQM VP issues */
  805. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  806. qdf_atomic_inc(&soc->num_tx_exception);
  807. }
  808. return tx_desc;
  809. failure:
  810. dp_tx_desc_release(tx_desc, desc_pool_id);
  811. return NULL;
  812. }
  813. /**
  814. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  815. * @vdev: DP vdev handle
  816. * @nbuf: skb
  817. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  818. * @desc_pool_id : Descriptor Pool ID
  819. *
  820. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  821. * information. For frames wth fragments, allocate and prepare
  822. * an MSDU extension descriptor
  823. *
  824. * Return: Pointer to Tx Descriptor on success,
  825. * NULL on failure
  826. */
  827. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  828. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  829. uint8_t desc_pool_id)
  830. {
  831. struct dp_tx_desc_s *tx_desc;
  832. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  833. struct dp_pdev *pdev = vdev->pdev;
  834. struct dp_soc *soc = pdev->soc;
  835. if (dp_tx_limit_check(vdev))
  836. return NULL;
  837. /* Allocate software Tx descriptor */
  838. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  839. if (!tx_desc) {
  840. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  841. return NULL;
  842. }
  843. dp_tx_outstanding_inc(pdev);
  844. /* Initialize the SW tx descriptor */
  845. tx_desc->nbuf = nbuf;
  846. tx_desc->frm_type = msdu_info->frm_type;
  847. tx_desc->tx_encap_type = vdev->tx_encap_type;
  848. tx_desc->vdev_id = vdev->vdev_id;
  849. tx_desc->pdev = pdev;
  850. tx_desc->pkt_offset = 0;
  851. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  852. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  853. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  854. /* Handle scattered frames - TSO/SG/ME */
  855. /* Allocate and prepare an extension descriptor for scattered frames */
  856. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  857. if (!msdu_ext_desc) {
  858. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  859. "%s Tx Extension Descriptor Alloc Fail",
  860. __func__);
  861. goto failure;
  862. }
  863. #if TQM_BYPASS_WAR
  864. /* Temporary WAR due to TQM VP issues */
  865. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  866. qdf_atomic_inc(&soc->num_tx_exception);
  867. #endif
  868. if (qdf_unlikely(msdu_info->exception_fw))
  869. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  870. tx_desc->msdu_ext_desc = msdu_ext_desc;
  871. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  872. return tx_desc;
  873. failure:
  874. dp_tx_desc_release(tx_desc, desc_pool_id);
  875. return NULL;
  876. }
  877. /**
  878. * dp_tx_prepare_raw() - Prepare RAW packet TX
  879. * @vdev: DP vdev handle
  880. * @nbuf: buffer pointer
  881. * @seg_info: Pointer to Segment info Descriptor to be prepared
  882. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  883. * descriptor
  884. *
  885. * Return:
  886. */
  887. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  888. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  889. {
  890. qdf_nbuf_t curr_nbuf = NULL;
  891. uint16_t total_len = 0;
  892. qdf_dma_addr_t paddr;
  893. int32_t i;
  894. int32_t mapped_buf_num = 0;
  895. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  896. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  897. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  898. /* Continue only if frames are of DATA type */
  899. if (!DP_FRAME_IS_DATA(qos_wh)) {
  900. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  901. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  902. "Pkt. recd is of not data type");
  903. goto error;
  904. }
  905. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  906. if (vdev->raw_mode_war &&
  907. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  908. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  909. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  910. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  911. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  912. if (QDF_STATUS_SUCCESS !=
  913. qdf_nbuf_map_nbytes_single(vdev->osdev,
  914. curr_nbuf,
  915. QDF_DMA_TO_DEVICE,
  916. curr_nbuf->len)) {
  917. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  918. "%s dma map error ", __func__);
  919. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  920. mapped_buf_num = i;
  921. goto error;
  922. }
  923. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  924. seg_info->frags[i].paddr_lo = paddr;
  925. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  926. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  927. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  928. total_len += qdf_nbuf_len(curr_nbuf);
  929. }
  930. seg_info->frag_cnt = i;
  931. seg_info->total_len = total_len;
  932. seg_info->next = NULL;
  933. sg_info->curr_seg = seg_info;
  934. msdu_info->frm_type = dp_tx_frm_raw;
  935. msdu_info->num_seg = 1;
  936. return nbuf;
  937. error:
  938. i = 0;
  939. while (nbuf) {
  940. curr_nbuf = nbuf;
  941. if (i < mapped_buf_num) {
  942. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  943. QDF_DMA_TO_DEVICE,
  944. curr_nbuf->len);
  945. i++;
  946. }
  947. nbuf = qdf_nbuf_next(nbuf);
  948. qdf_nbuf_free(curr_nbuf);
  949. }
  950. return NULL;
  951. }
  952. /**
  953. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  954. * @soc: DP soc handle
  955. * @nbuf: Buffer pointer
  956. *
  957. * unmap the chain of nbufs that belong to this RAW frame.
  958. *
  959. * Return: None
  960. */
  961. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  962. qdf_nbuf_t nbuf)
  963. {
  964. qdf_nbuf_t cur_nbuf = nbuf;
  965. do {
  966. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  967. QDF_DMA_TO_DEVICE,
  968. cur_nbuf->len);
  969. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  970. } while (cur_nbuf);
  971. }
  972. #ifdef VDEV_PEER_PROTOCOL_COUNT
  973. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, nbuf) \
  974. { \
  975. qdf_nbuf_t nbuf_local; \
  976. struct dp_vdev *vdev_local = vdev_hdl; \
  977. do { \
  978. if (qdf_likely(!((vdev_local)->peer_protocol_count_track))) \
  979. break; \
  980. nbuf_local = nbuf; \
  981. if (qdf_unlikely(((vdev_local)->tx_encap_type) == \
  982. htt_cmn_pkt_type_raw)) \
  983. break; \
  984. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local)))) \
  985. break; \
  986. else if (qdf_nbuf_is_tso((nbuf_local))) \
  987. break; \
  988. dp_vdev_peer_stats_update_protocol_cnt((vdev_local), \
  989. (nbuf_local), \
  990. NULL, 1, 0); \
  991. } while (0); \
  992. }
  993. #else
  994. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, skb)
  995. #endif
  996. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  997. /**
  998. * dp_tx_update_stats() - Update soc level tx stats
  999. * @soc: DP soc handle
  1000. * @nbuf: packet being transmitted
  1001. *
  1002. * Returns: none
  1003. */
  1004. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1005. qdf_nbuf_t nbuf)
  1006. {
  1007. DP_STATS_INC_PKT(soc, tx.egress, 1, qdf_nbuf_len(nbuf));
  1008. }
  1009. /**
  1010. * dp_tx_attempt_coalescing() - Check and attempt TCL register write coalescing
  1011. * @soc: Datapath soc handle
  1012. * @tx_desc: tx packet descriptor
  1013. * @tid: TID for pkt transmission
  1014. *
  1015. * Returns: 1, if coalescing is to be done
  1016. * 0, if coalescing is not to be done
  1017. */
  1018. static inline int
  1019. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1020. struct dp_tx_desc_s *tx_desc,
  1021. uint8_t tid)
  1022. {
  1023. struct dp_swlm *swlm = &soc->swlm;
  1024. union swlm_data swlm_query_data;
  1025. struct dp_swlm_tcl_data tcl_data;
  1026. QDF_STATUS status;
  1027. int ret;
  1028. if (qdf_unlikely(!swlm->is_enabled))
  1029. return 0;
  1030. tcl_data.nbuf = tx_desc->nbuf;
  1031. tcl_data.tid = tid;
  1032. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1033. swlm_query_data.tcl_data = &tcl_data;
  1034. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1035. if (QDF_IS_STATUS_ERROR(status)) {
  1036. dp_swlm_tcl_reset_session_data(soc);
  1037. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1038. return 0;
  1039. }
  1040. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1041. if (ret) {
  1042. DP_STATS_INC(swlm, tcl.coalesce_success, 1);
  1043. } else {
  1044. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1045. }
  1046. return ret;
  1047. }
  1048. /**
  1049. * dp_tx_ring_access_end() - HAL ring access end for data transmission
  1050. * @soc: Datapath soc handle
  1051. * @hal_ring_hdl: HAL ring handle
  1052. * @coalesce: Coalesce the current write or not
  1053. *
  1054. * Returns: none
  1055. */
  1056. static inline void
  1057. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1058. int coalesce)
  1059. {
  1060. if (coalesce)
  1061. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1062. else
  1063. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1064. }
  1065. #else
  1066. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1067. qdf_nbuf_t nbuf)
  1068. {
  1069. }
  1070. static inline int
  1071. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1072. struct dp_tx_desc_s *tx_desc,
  1073. uint8_t tid)
  1074. {
  1075. return 0;
  1076. }
  1077. static inline void
  1078. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1079. int coalesce)
  1080. {
  1081. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1082. }
  1083. #endif
  1084. /**
  1085. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  1086. * @soc: DP Soc Handle
  1087. * @vdev: DP vdev handle
  1088. * @tx_desc: Tx Descriptor Handle
  1089. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1090. * @fw_metadata: Metadata to send to Target Firmware along with frame
  1091. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  1092. * @tx_exc_metadata: Handle that holds exception path meta data
  1093. *
  1094. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  1095. * from software Tx descriptor
  1096. *
  1097. * Return: QDF_STATUS_SUCCESS: success
  1098. * QDF_STATUS_E_RESOURCES: Error return
  1099. */
  1100. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  1101. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  1102. uint16_t fw_metadata, uint8_t ring_id,
  1103. struct cdp_tx_exception_metadata
  1104. *tx_exc_metadata)
  1105. {
  1106. uint8_t type;
  1107. void *hal_tx_desc;
  1108. uint32_t *hal_tx_desc_cached;
  1109. int coalesce = 0;
  1110. /*
  1111. * Setting it initialization statically here to avoid
  1112. * a memset call jump with qdf_mem_set call
  1113. */
  1114. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1115. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  1116. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  1117. tx_exc_metadata->sec_type : vdev->sec_type);
  1118. /* Return Buffer Manager ID */
  1119. uint8_t bm_id = dp_tx_get_rbm_id(soc, ring_id);
  1120. hal_ring_handle_t hal_ring_hdl = NULL;
  1121. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1122. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  1123. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1124. return QDF_STATUS_E_RESOURCES;
  1125. }
  1126. hal_tx_desc_cached = (void *) cached_desc;
  1127. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  1128. type = HAL_TX_BUF_TYPE_EXT_DESC;
  1129. tx_desc->dma_addr = tx_desc->msdu_ext_desc->paddr;
  1130. if (tx_desc->msdu_ext_desc->flags &
  1131. DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1132. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1133. else
  1134. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1135. } else {
  1136. tx_desc->length = qdf_nbuf_len(tx_desc->nbuf) -
  1137. tx_desc->pkt_offset;
  1138. type = HAL_TX_BUF_TYPE_BUFFER;
  1139. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1140. }
  1141. qdf_assert_always(tx_desc->dma_addr);
  1142. hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
  1143. tx_desc->dma_addr, bm_id, tx_desc->id,
  1144. type);
  1145. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  1146. vdev->lmac_id);
  1147. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  1148. vdev->search_type);
  1149. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  1150. vdev->bss_ast_idx);
  1151. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  1152. vdev->dscp_tid_map_id);
  1153. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  1154. sec_type_map[sec_type]);
  1155. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1156. (vdev->bss_ast_hash & 0xF));
  1157. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1158. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  1159. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1160. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  1161. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  1162. vdev->hal_desc_addr_search_flags);
  1163. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1164. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1165. /* verify checksum offload configuration*/
  1166. if (vdev->csum_enabled &&
  1167. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  1168. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  1169. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1170. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1171. }
  1172. if (tid != HTT_TX_EXT_TID_INVALID)
  1173. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1174. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  1175. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  1176. if (qdf_unlikely(vdev->pdev->delay_stats_flag) ||
  1177. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  1178. soc->wlan_cfg_ctx)))
  1179. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  1180. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  1181. tx_desc->length, type, (uint64_t)tx_desc->dma_addr,
  1182. tx_desc->pkt_offset, tx_desc->id);
  1183. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  1184. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1185. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1186. "%s %d : HAL RING Access Failed -- %pK",
  1187. __func__, __LINE__, hal_ring_hdl);
  1188. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1189. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1190. return status;
  1191. }
  1192. /* Sync cached descriptor with HW */
  1193. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1194. if (qdf_unlikely(!hal_tx_desc)) {
  1195. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1196. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1197. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1198. goto ring_access_fail;
  1199. }
  1200. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1201. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1202. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  1203. coalesce = dp_tx_attempt_coalescing(soc, vdev, tx_desc, tid);
  1204. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
  1205. dp_tx_update_stats(soc, tx_desc->nbuf);
  1206. status = QDF_STATUS_SUCCESS;
  1207. ring_access_fail:
  1208. if (hif_pm_runtime_get(soc->hif_handle,
  1209. RTPM_ID_DW_TX_HW_ENQUEUE) == 0) {
  1210. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1211. hif_pm_runtime_put(soc->hif_handle,
  1212. RTPM_ID_DW_TX_HW_ENQUEUE);
  1213. } else {
  1214. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1215. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1216. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1217. }
  1218. return status;
  1219. }
  1220. /**
  1221. * dp_cce_classify() - Classify the frame based on CCE rules
  1222. * @vdev: DP vdev handle
  1223. * @nbuf: skb
  1224. *
  1225. * Classify frames based on CCE rules
  1226. * Return: bool( true if classified,
  1227. * else false)
  1228. */
  1229. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1230. {
  1231. qdf_ether_header_t *eh = NULL;
  1232. uint16_t ether_type;
  1233. qdf_llc_t *llcHdr;
  1234. qdf_nbuf_t nbuf_clone = NULL;
  1235. qdf_dot3_qosframe_t *qos_wh = NULL;
  1236. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1237. /*
  1238. * In case of mesh packets or hlos tid override enabled,
  1239. * don't do any classification
  1240. */
  1241. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1242. & DP_TX_SKIP_CCE_CLASSIFY))
  1243. return false;
  1244. }
  1245. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1246. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1247. ether_type = eh->ether_type;
  1248. llcHdr = (qdf_llc_t *)(nbuf->data +
  1249. sizeof(qdf_ether_header_t));
  1250. } else {
  1251. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1252. /* For encrypted packets don't do any classification */
  1253. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1254. return false;
  1255. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1256. if (qdf_unlikely(
  1257. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1258. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1259. ether_type = *(uint16_t *)(nbuf->data
  1260. + QDF_IEEE80211_4ADDR_HDR_LEN
  1261. + sizeof(qdf_llc_t)
  1262. - sizeof(ether_type));
  1263. llcHdr = (qdf_llc_t *)(nbuf->data +
  1264. QDF_IEEE80211_4ADDR_HDR_LEN);
  1265. } else {
  1266. ether_type = *(uint16_t *)(nbuf->data
  1267. + QDF_IEEE80211_3ADDR_HDR_LEN
  1268. + sizeof(qdf_llc_t)
  1269. - sizeof(ether_type));
  1270. llcHdr = (qdf_llc_t *)(nbuf->data +
  1271. QDF_IEEE80211_3ADDR_HDR_LEN);
  1272. }
  1273. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1274. && (ether_type ==
  1275. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1276. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1277. return true;
  1278. }
  1279. }
  1280. return false;
  1281. }
  1282. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1283. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1284. sizeof(*llcHdr));
  1285. nbuf_clone = qdf_nbuf_clone(nbuf);
  1286. if (qdf_unlikely(nbuf_clone)) {
  1287. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1288. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1289. qdf_nbuf_pull_head(nbuf_clone,
  1290. sizeof(qdf_net_vlanhdr_t));
  1291. }
  1292. }
  1293. } else {
  1294. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1295. nbuf_clone = qdf_nbuf_clone(nbuf);
  1296. if (qdf_unlikely(nbuf_clone)) {
  1297. qdf_nbuf_pull_head(nbuf_clone,
  1298. sizeof(qdf_net_vlanhdr_t));
  1299. }
  1300. }
  1301. }
  1302. if (qdf_unlikely(nbuf_clone))
  1303. nbuf = nbuf_clone;
  1304. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1305. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1306. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1307. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1308. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1309. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1310. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1311. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1312. if (qdf_unlikely(nbuf_clone))
  1313. qdf_nbuf_free(nbuf_clone);
  1314. return true;
  1315. }
  1316. if (qdf_unlikely(nbuf_clone))
  1317. qdf_nbuf_free(nbuf_clone);
  1318. return false;
  1319. }
  1320. /**
  1321. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1322. * @vdev: DP vdev handle
  1323. * @nbuf: skb
  1324. *
  1325. * Extract the DSCP or PCP information from frame and map into TID value.
  1326. *
  1327. * Return: void
  1328. */
  1329. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1330. struct dp_tx_msdu_info_s *msdu_info)
  1331. {
  1332. uint8_t tos = 0, dscp_tid_override = 0;
  1333. uint8_t *hdr_ptr, *L3datap;
  1334. uint8_t is_mcast = 0;
  1335. qdf_ether_header_t *eh = NULL;
  1336. qdf_ethervlan_header_t *evh = NULL;
  1337. uint16_t ether_type;
  1338. qdf_llc_t *llcHdr;
  1339. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1340. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1341. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1342. eh = (qdf_ether_header_t *)nbuf->data;
  1343. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1344. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1345. } else {
  1346. qdf_dot3_qosframe_t *qos_wh =
  1347. (qdf_dot3_qosframe_t *) nbuf->data;
  1348. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1349. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1350. return;
  1351. }
  1352. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1353. ether_type = eh->ether_type;
  1354. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1355. /*
  1356. * Check if packet is dot3 or eth2 type.
  1357. */
  1358. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1359. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1360. sizeof(*llcHdr));
  1361. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1362. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1363. sizeof(*llcHdr);
  1364. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1365. + sizeof(*llcHdr) +
  1366. sizeof(qdf_net_vlanhdr_t));
  1367. } else {
  1368. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1369. sizeof(*llcHdr);
  1370. }
  1371. } else {
  1372. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1373. evh = (qdf_ethervlan_header_t *) eh;
  1374. ether_type = evh->ether_type;
  1375. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1376. }
  1377. }
  1378. /*
  1379. * Find priority from IP TOS DSCP field
  1380. */
  1381. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1382. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1383. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1384. /* Only for unicast frames */
  1385. if (!is_mcast) {
  1386. /* send it on VO queue */
  1387. msdu_info->tid = DP_VO_TID;
  1388. }
  1389. } else {
  1390. /*
  1391. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1392. * from TOS byte.
  1393. */
  1394. tos = ip->ip_tos;
  1395. dscp_tid_override = 1;
  1396. }
  1397. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1398. /* TODO
  1399. * use flowlabel
  1400. *igmpmld cases to be handled in phase 2
  1401. */
  1402. unsigned long ver_pri_flowlabel;
  1403. unsigned long pri;
  1404. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1405. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1406. DP_IPV6_PRIORITY_SHIFT;
  1407. tos = pri;
  1408. dscp_tid_override = 1;
  1409. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1410. msdu_info->tid = DP_VO_TID;
  1411. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1412. /* Only for unicast frames */
  1413. if (!is_mcast) {
  1414. /* send ucast arp on VO queue */
  1415. msdu_info->tid = DP_VO_TID;
  1416. }
  1417. }
  1418. /*
  1419. * Assign all MCAST packets to BE
  1420. */
  1421. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1422. if (is_mcast) {
  1423. tos = 0;
  1424. dscp_tid_override = 1;
  1425. }
  1426. }
  1427. if (dscp_tid_override == 1) {
  1428. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1429. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1430. }
  1431. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1432. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1433. return;
  1434. }
  1435. /**
  1436. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1437. * @vdev: DP vdev handle
  1438. * @nbuf: skb
  1439. *
  1440. * Software based TID classification is required when more than 2 DSCP-TID
  1441. * mapping tables are needed.
  1442. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1443. *
  1444. * Return: void
  1445. */
  1446. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1447. struct dp_tx_msdu_info_s *msdu_info)
  1448. {
  1449. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1450. /*
  1451. * skip_sw_tid_classification flag will set in below cases-
  1452. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1453. * 2. hlos_tid_override enabled for vdev
  1454. * 3. mesh mode enabled for vdev
  1455. */
  1456. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1457. /* Update tid in msdu_info from skb priority */
  1458. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1459. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1460. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1461. return;
  1462. }
  1463. return;
  1464. }
  1465. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1466. }
  1467. #ifdef FEATURE_WLAN_TDLS
  1468. /**
  1469. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1470. * @soc: datapath SOC
  1471. * @vdev: datapath vdev
  1472. * @tx_desc: TX descriptor
  1473. *
  1474. * Return: None
  1475. */
  1476. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1477. struct dp_vdev *vdev,
  1478. struct dp_tx_desc_s *tx_desc)
  1479. {
  1480. if (vdev) {
  1481. if (vdev->is_tdls_frame) {
  1482. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1483. vdev->is_tdls_frame = false;
  1484. }
  1485. }
  1486. }
  1487. /**
  1488. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1489. * @soc: dp_soc handle
  1490. * @tx_desc: TX descriptor
  1491. * @vdev: datapath vdev handle
  1492. *
  1493. * Return: None
  1494. */
  1495. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1496. struct dp_tx_desc_s *tx_desc)
  1497. {
  1498. struct hal_tx_completion_status ts = {0};
  1499. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1500. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1501. DP_MOD_ID_TDLS);
  1502. if (qdf_unlikely(!vdev)) {
  1503. dp_err_rl("vdev is null!");
  1504. goto error;
  1505. }
  1506. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1507. if (vdev->tx_non_std_data_callback.func) {
  1508. qdf_nbuf_set_next(nbuf, NULL);
  1509. vdev->tx_non_std_data_callback.func(
  1510. vdev->tx_non_std_data_callback.ctxt,
  1511. nbuf, ts.status);
  1512. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1513. return;
  1514. } else {
  1515. dp_err_rl("callback func is null");
  1516. }
  1517. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1518. error:
  1519. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1520. qdf_nbuf_free(nbuf);
  1521. }
  1522. /**
  1523. * dp_tx_msdu_single_map() - do nbuf map
  1524. * @vdev: DP vdev handle
  1525. * @tx_desc: DP TX descriptor pointer
  1526. * @nbuf: skb pointer
  1527. *
  1528. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1529. * operation done in other component.
  1530. *
  1531. * Return: QDF_STATUS
  1532. */
  1533. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1534. struct dp_tx_desc_s *tx_desc,
  1535. qdf_nbuf_t nbuf)
  1536. {
  1537. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1538. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1539. nbuf,
  1540. QDF_DMA_TO_DEVICE,
  1541. nbuf->len);
  1542. else
  1543. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1544. QDF_DMA_TO_DEVICE);
  1545. }
  1546. #else
  1547. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1548. struct dp_vdev *vdev,
  1549. struct dp_tx_desc_s *tx_desc)
  1550. {
  1551. }
  1552. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1553. struct dp_tx_desc_s *tx_desc)
  1554. {
  1555. }
  1556. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1557. struct dp_tx_desc_s *tx_desc,
  1558. qdf_nbuf_t nbuf)
  1559. {
  1560. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1561. nbuf,
  1562. QDF_DMA_TO_DEVICE,
  1563. nbuf->len);
  1564. }
  1565. #endif
  1566. #ifdef MESH_MODE_SUPPORT
  1567. /**
  1568. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1569. * @soc: datapath SOC
  1570. * @vdev: datapath vdev
  1571. * @tx_desc: TX descriptor
  1572. *
  1573. * Return: None
  1574. */
  1575. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1576. struct dp_vdev *vdev,
  1577. struct dp_tx_desc_s *tx_desc)
  1578. {
  1579. if (qdf_unlikely(vdev->mesh_vdev))
  1580. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1581. }
  1582. /**
  1583. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1584. * @soc: dp_soc handle
  1585. * @tx_desc: TX descriptor
  1586. * @vdev: datapath vdev handle
  1587. *
  1588. * Return: None
  1589. */
  1590. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1591. struct dp_tx_desc_s *tx_desc)
  1592. {
  1593. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1594. struct dp_vdev *vdev = NULL;
  1595. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1596. qdf_nbuf_free(nbuf);
  1597. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1598. } else {
  1599. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1600. DP_MOD_ID_MESH);
  1601. if (vdev && vdev->osif_tx_free_ext)
  1602. vdev->osif_tx_free_ext((nbuf));
  1603. else
  1604. qdf_nbuf_free(nbuf);
  1605. if (vdev)
  1606. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1607. }
  1608. }
  1609. #else
  1610. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1611. struct dp_vdev *vdev,
  1612. struct dp_tx_desc_s *tx_desc)
  1613. {
  1614. }
  1615. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1616. struct dp_tx_desc_s *tx_desc)
  1617. {
  1618. }
  1619. #endif
  1620. /**
  1621. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1622. * @vdev: DP vdev handle
  1623. * @nbuf: skb
  1624. *
  1625. * Return: 1 if frame needs to be dropped else 0
  1626. */
  1627. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1628. {
  1629. struct dp_pdev *pdev = NULL;
  1630. struct dp_ast_entry *src_ast_entry = NULL;
  1631. struct dp_ast_entry *dst_ast_entry = NULL;
  1632. struct dp_soc *soc = NULL;
  1633. qdf_assert(vdev);
  1634. pdev = vdev->pdev;
  1635. qdf_assert(pdev);
  1636. soc = pdev->soc;
  1637. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1638. (soc, dstmac, vdev->pdev->pdev_id);
  1639. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1640. (soc, srcmac, vdev->pdev->pdev_id);
  1641. if (dst_ast_entry && src_ast_entry) {
  1642. if (dst_ast_entry->peer_id ==
  1643. src_ast_entry->peer_id)
  1644. return 1;
  1645. }
  1646. return 0;
  1647. }
  1648. /**
  1649. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1650. * @vdev: DP vdev handle
  1651. * @nbuf: skb
  1652. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1653. * @meta_data: Metadata to the fw
  1654. * @tx_q: Tx queue to be used for this Tx frame
  1655. * @peer_id: peer_id of the peer in case of NAWDS frames
  1656. * @tx_exc_metadata: Handle that holds exception path metadata
  1657. *
  1658. * Return: NULL on success,
  1659. * nbuf when it fails to send
  1660. */
  1661. qdf_nbuf_t
  1662. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1663. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1664. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1665. {
  1666. struct dp_pdev *pdev = vdev->pdev;
  1667. struct dp_soc *soc = pdev->soc;
  1668. struct dp_tx_desc_s *tx_desc;
  1669. QDF_STATUS status;
  1670. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1671. uint16_t htt_tcl_metadata = 0;
  1672. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1673. uint8_t tid = msdu_info->tid;
  1674. struct cdp_tid_tx_stats *tid_stats = NULL;
  1675. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1676. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1677. msdu_info, tx_exc_metadata);
  1678. if (!tx_desc) {
  1679. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1680. vdev, tx_q->desc_pool_id);
  1681. drop_code = TX_DESC_ERR;
  1682. goto fail_return;
  1683. }
  1684. if (qdf_unlikely(soc->cce_disable)) {
  1685. if (dp_cce_classify(vdev, nbuf) == true) {
  1686. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1687. tid = DP_VO_TID;
  1688. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1689. }
  1690. }
  1691. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1692. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1693. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1694. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1695. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1696. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1697. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1698. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1699. peer_id);
  1700. } else
  1701. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1702. if (msdu_info->exception_fw)
  1703. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1704. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1705. !pdev->enhanced_stats_en);
  1706. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1707. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1708. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1709. /* Handle failure */
  1710. dp_err("qdf_nbuf_map failed");
  1711. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1712. drop_code = TX_DMA_MAP_ERR;
  1713. goto release_desc;
  1714. }
  1715. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1716. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1717. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1718. if (status != QDF_STATUS_SUCCESS) {
  1719. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1720. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1721. __func__, tx_desc, tx_q->ring_id);
  1722. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1723. QDF_DMA_TO_DEVICE,
  1724. nbuf->len);
  1725. drop_code = TX_HW_ENQUEUE;
  1726. goto release_desc;
  1727. }
  1728. return NULL;
  1729. release_desc:
  1730. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1731. fail_return:
  1732. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1733. tid_stats = &pdev->stats.tid_stats.
  1734. tid_tx_stats[tx_q->ring_id][tid];
  1735. tid_stats->swdrop_cnt[drop_code]++;
  1736. return nbuf;
  1737. }
  1738. /**
  1739. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1740. * @vdev: DP vdev handle
  1741. * @nbuf: skb
  1742. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1743. *
  1744. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1745. *
  1746. * Return: NULL on success,
  1747. * nbuf when it fails to send
  1748. */
  1749. #if QDF_LOCK_STATS
  1750. noinline
  1751. #else
  1752. #endif
  1753. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1754. struct dp_tx_msdu_info_s *msdu_info)
  1755. {
  1756. uint32_t i;
  1757. struct dp_pdev *pdev = vdev->pdev;
  1758. struct dp_soc *soc = pdev->soc;
  1759. struct dp_tx_desc_s *tx_desc;
  1760. bool is_cce_classified = false;
  1761. QDF_STATUS status;
  1762. uint16_t htt_tcl_metadata = 0;
  1763. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1764. struct cdp_tid_tx_stats *tid_stats = NULL;
  1765. if (qdf_unlikely(soc->cce_disable)) {
  1766. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1767. if (is_cce_classified) {
  1768. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1769. msdu_info->tid = DP_VO_TID;
  1770. }
  1771. }
  1772. if (msdu_info->frm_type == dp_tx_frm_me)
  1773. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1774. i = 0;
  1775. /* Print statement to track i and num_seg */
  1776. /*
  1777. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1778. * descriptors using information in msdu_info
  1779. */
  1780. while (i < msdu_info->num_seg) {
  1781. /*
  1782. * Setup Tx descriptor for an MSDU, and MSDU extension
  1783. * descriptor
  1784. */
  1785. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1786. tx_q->desc_pool_id);
  1787. if (!tx_desc) {
  1788. if (msdu_info->frm_type == dp_tx_frm_me) {
  1789. dp_tx_me_free_buf(pdev,
  1790. (void *)(msdu_info->u.sg_info
  1791. .curr_seg->frags[0].vaddr));
  1792. i++;
  1793. continue;
  1794. }
  1795. goto done;
  1796. }
  1797. if (msdu_info->frm_type == dp_tx_frm_me) {
  1798. tx_desc->me_buffer =
  1799. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1800. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1801. }
  1802. if (is_cce_classified)
  1803. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1804. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1805. if (msdu_info->exception_fw) {
  1806. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1807. }
  1808. /*
  1809. * Enqueue the Tx MSDU descriptor to HW for transmit
  1810. */
  1811. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1812. htt_tcl_metadata, tx_q->ring_id, NULL);
  1813. if (status != QDF_STATUS_SUCCESS) {
  1814. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1815. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1816. __func__, tx_desc, tx_q->ring_id);
  1817. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1818. tid_stats = &pdev->stats.tid_stats.
  1819. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1820. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1821. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1822. if (msdu_info->frm_type == dp_tx_frm_me) {
  1823. i++;
  1824. continue;
  1825. }
  1826. goto done;
  1827. }
  1828. /*
  1829. * TODO
  1830. * if tso_info structure can be modified to have curr_seg
  1831. * as first element, following 2 blocks of code (for TSO and SG)
  1832. * can be combined into 1
  1833. */
  1834. /*
  1835. * For frames with multiple segments (TSO, ME), jump to next
  1836. * segment.
  1837. */
  1838. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1839. if (msdu_info->u.tso_info.curr_seg->next) {
  1840. msdu_info->u.tso_info.curr_seg =
  1841. msdu_info->u.tso_info.curr_seg->next;
  1842. /*
  1843. * If this is a jumbo nbuf, then increment the number of
  1844. * nbuf users for each additional segment of the msdu.
  1845. * This will ensure that the skb is freed only after
  1846. * receiving tx completion for all segments of an nbuf
  1847. */
  1848. qdf_nbuf_inc_users(nbuf);
  1849. /* Check with MCL if this is needed */
  1850. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1851. }
  1852. }
  1853. /*
  1854. * For Multicast-Unicast converted packets,
  1855. * each converted frame (for a client) is represented as
  1856. * 1 segment
  1857. */
  1858. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1859. (msdu_info->frm_type == dp_tx_frm_me)) {
  1860. if (msdu_info->u.sg_info.curr_seg->next) {
  1861. msdu_info->u.sg_info.curr_seg =
  1862. msdu_info->u.sg_info.curr_seg->next;
  1863. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1864. }
  1865. }
  1866. i++;
  1867. }
  1868. nbuf = NULL;
  1869. done:
  1870. return nbuf;
  1871. }
  1872. /**
  1873. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1874. * for SG frames
  1875. * @vdev: DP vdev handle
  1876. * @nbuf: skb
  1877. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1878. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1879. *
  1880. * Return: NULL on success,
  1881. * nbuf when it fails to send
  1882. */
  1883. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1884. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1885. {
  1886. uint32_t cur_frag, nr_frags, i;
  1887. qdf_dma_addr_t paddr;
  1888. struct dp_tx_sg_info_s *sg_info;
  1889. sg_info = &msdu_info->u.sg_info;
  1890. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1891. if (QDF_STATUS_SUCCESS !=
  1892. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  1893. QDF_DMA_TO_DEVICE,
  1894. qdf_nbuf_headlen(nbuf))) {
  1895. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1896. "dma map error");
  1897. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1898. qdf_nbuf_free(nbuf);
  1899. return NULL;
  1900. }
  1901. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  1902. seg_info->frags[0].paddr_lo = paddr;
  1903. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1904. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1905. seg_info->frags[0].vaddr = (void *) nbuf;
  1906. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1907. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1908. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1909. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1910. "frag dma map error");
  1911. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1912. goto map_err;
  1913. }
  1914. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  1915. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1916. seg_info->frags[cur_frag + 1].paddr_hi =
  1917. ((uint64_t) paddr) >> 32;
  1918. seg_info->frags[cur_frag + 1].len =
  1919. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1920. }
  1921. seg_info->frag_cnt = (cur_frag + 1);
  1922. seg_info->total_len = qdf_nbuf_len(nbuf);
  1923. seg_info->next = NULL;
  1924. sg_info->curr_seg = seg_info;
  1925. msdu_info->frm_type = dp_tx_frm_sg;
  1926. msdu_info->num_seg = 1;
  1927. return nbuf;
  1928. map_err:
  1929. /* restore paddr into nbuf before calling unmap */
  1930. qdf_nbuf_mapped_paddr_set(nbuf,
  1931. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  1932. ((uint64_t)
  1933. seg_info->frags[0].paddr_hi) << 32));
  1934. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1935. QDF_DMA_TO_DEVICE,
  1936. seg_info->frags[0].len);
  1937. for (i = 1; i <= cur_frag; i++) {
  1938. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  1939. (seg_info->frags[i].paddr_lo | ((uint64_t)
  1940. seg_info->frags[i].paddr_hi) << 32),
  1941. seg_info->frags[i].len,
  1942. QDF_DMA_TO_DEVICE);
  1943. }
  1944. qdf_nbuf_free(nbuf);
  1945. return NULL;
  1946. }
  1947. /**
  1948. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  1949. * @vdev: DP vdev handle
  1950. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1951. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  1952. *
  1953. * Return: NULL on failure,
  1954. * nbuf when extracted successfully
  1955. */
  1956. static
  1957. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  1958. struct dp_tx_msdu_info_s *msdu_info,
  1959. uint16_t ppdu_cookie)
  1960. {
  1961. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1962. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1963. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1964. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  1965. (msdu_info->meta_data[5], 1);
  1966. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  1967. (msdu_info->meta_data[5], 1);
  1968. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  1969. (msdu_info->meta_data[6], ppdu_cookie);
  1970. msdu_info->exception_fw = 1;
  1971. msdu_info->is_tx_sniffer = 1;
  1972. }
  1973. #ifdef MESH_MODE_SUPPORT
  1974. /**
  1975. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1976. and prepare msdu_info for mesh frames.
  1977. * @vdev: DP vdev handle
  1978. * @nbuf: skb
  1979. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1980. *
  1981. * Return: NULL on failure,
  1982. * nbuf when extracted successfully
  1983. */
  1984. static
  1985. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1986. struct dp_tx_msdu_info_s *msdu_info)
  1987. {
  1988. struct meta_hdr_s *mhdr;
  1989. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1990. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1991. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1992. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1993. msdu_info->exception_fw = 0;
  1994. goto remove_meta_hdr;
  1995. }
  1996. msdu_info->exception_fw = 1;
  1997. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1998. meta_data->host_tx_desc_pool = 1;
  1999. meta_data->update_peer_cache = 1;
  2000. meta_data->learning_frame = 1;
  2001. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2002. meta_data->power = mhdr->power;
  2003. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2004. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2005. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2006. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2007. meta_data->dyn_bw = 1;
  2008. meta_data->valid_pwr = 1;
  2009. meta_data->valid_mcs_mask = 1;
  2010. meta_data->valid_nss_mask = 1;
  2011. meta_data->valid_preamble_type = 1;
  2012. meta_data->valid_retries = 1;
  2013. meta_data->valid_bw_info = 1;
  2014. }
  2015. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2016. meta_data->encrypt_type = 0;
  2017. meta_data->valid_encrypt_type = 1;
  2018. meta_data->learning_frame = 0;
  2019. }
  2020. meta_data->valid_key_flags = 1;
  2021. meta_data->key_flags = (mhdr->keyix & 0x3);
  2022. remove_meta_hdr:
  2023. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2024. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2025. "qdf_nbuf_pull_head failed");
  2026. qdf_nbuf_free(nbuf);
  2027. return NULL;
  2028. }
  2029. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2030. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2031. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  2032. " tid %d to_fw %d",
  2033. __func__, msdu_info->meta_data[0],
  2034. msdu_info->meta_data[1],
  2035. msdu_info->meta_data[2],
  2036. msdu_info->meta_data[3],
  2037. msdu_info->meta_data[4],
  2038. msdu_info->meta_data[5],
  2039. msdu_info->tid, msdu_info->exception_fw);
  2040. return nbuf;
  2041. }
  2042. #else
  2043. static
  2044. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2045. struct dp_tx_msdu_info_s *msdu_info)
  2046. {
  2047. return nbuf;
  2048. }
  2049. #endif
  2050. /**
  2051. * dp_check_exc_metadata() - Checks if parameters are valid
  2052. * @tx_exc - holds all exception path parameters
  2053. *
  2054. * Returns true when all the parameters are valid else false
  2055. *
  2056. */
  2057. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2058. {
  2059. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  2060. HTT_INVALID_TID);
  2061. bool invalid_encap_type =
  2062. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2063. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2064. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2065. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2066. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2067. tx_exc->ppdu_cookie == 0);
  2068. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2069. invalid_cookie) {
  2070. return false;
  2071. }
  2072. return true;
  2073. }
  2074. /**
  2075. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2076. * @nbuf: qdf_nbuf_t
  2077. * @vdev: struct dp_vdev *
  2078. *
  2079. * Allow packet for processing only if it is for peer client which is
  2080. * connected with same vap. Drop packet if client is connected to
  2081. * different vap.
  2082. *
  2083. * Return: QDF_STATUS
  2084. */
  2085. static inline QDF_STATUS
  2086. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2087. {
  2088. struct dp_ast_entry *dst_ast_entry = NULL;
  2089. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2090. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2091. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2092. return QDF_STATUS_SUCCESS;
  2093. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2094. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2095. eh->ether_dhost,
  2096. vdev->vdev_id);
  2097. /* If there is no ast entry, return failure */
  2098. if (qdf_unlikely(!dst_ast_entry)) {
  2099. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2100. return QDF_STATUS_E_FAILURE;
  2101. }
  2102. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2103. return QDF_STATUS_SUCCESS;
  2104. }
  2105. /**
  2106. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2107. * @soc: DP soc handle
  2108. * @vdev_id: id of DP vdev handle
  2109. * @nbuf: skb
  2110. * @tx_exc_metadata: Handle that holds exception path meta data
  2111. *
  2112. * Entry point for Core Tx layer (DP_TX) invoked from
  2113. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2114. *
  2115. * Return: NULL on success,
  2116. * nbuf when it fails to send
  2117. */
  2118. qdf_nbuf_t
  2119. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2120. qdf_nbuf_t nbuf,
  2121. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2122. {
  2123. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2124. qdf_ether_header_t *eh = NULL;
  2125. struct dp_tx_msdu_info_s msdu_info;
  2126. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2127. DP_MOD_ID_TX_EXCEPTION);
  2128. if (qdf_unlikely(!vdev))
  2129. goto fail;
  2130. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2131. if (!tx_exc_metadata)
  2132. goto fail;
  2133. msdu_info.tid = tx_exc_metadata->tid;
  2134. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2135. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2136. QDF_MAC_ADDR_REF(nbuf->data));
  2137. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2138. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2139. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2140. "Invalid parameters in exception path");
  2141. goto fail;
  2142. }
  2143. /* Basic sanity checks for unsupported packets */
  2144. /* MESH mode */
  2145. if (qdf_unlikely(vdev->mesh_vdev)) {
  2146. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2147. "Mesh mode is not supported in exception path");
  2148. goto fail;
  2149. }
  2150. /* TSO or SG */
  2151. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  2152. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2153. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2154. "TSO and SG are not supported in exception path");
  2155. goto fail;
  2156. }
  2157. /* RAW */
  2158. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2159. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2160. "Raw frame is not supported in exception path");
  2161. goto fail;
  2162. }
  2163. /* Mcast enhancement*/
  2164. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  2165. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2166. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2167. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2168. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  2169. }
  2170. }
  2171. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2172. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2173. qdf_nbuf_len(nbuf));
  2174. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2175. tx_exc_metadata->ppdu_cookie);
  2176. }
  2177. /*
  2178. * Get HW Queue to use for this frame.
  2179. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2180. * dedicated for data and 1 for command.
  2181. * "queue_id" maps to one hardware ring.
  2182. * With each ring, we also associate a unique Tx descriptor pool
  2183. * to minimize lock contention for these resources.
  2184. */
  2185. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2186. /*
  2187. * Check exception descriptors
  2188. */
  2189. if (dp_tx_exception_limit_check(vdev))
  2190. goto fail;
  2191. /* Single linear frame */
  2192. /*
  2193. * If nbuf is a simple linear frame, use send_single function to
  2194. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2195. * SRNG. There is no need to setup a MSDU extension descriptor.
  2196. */
  2197. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2198. tx_exc_metadata->peer_id, tx_exc_metadata);
  2199. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2200. return nbuf;
  2201. fail:
  2202. if (vdev)
  2203. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2204. dp_verbose_debug("pkt send failed");
  2205. return nbuf;
  2206. }
  2207. /**
  2208. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2209. * in exception path in special case to avoid regular exception path chk.
  2210. * @soc: DP soc handle
  2211. * @vdev_id: id of DP vdev handle
  2212. * @nbuf: skb
  2213. * @tx_exc_metadata: Handle that holds exception path meta data
  2214. *
  2215. * Entry point for Core Tx layer (DP_TX) invoked from
  2216. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2217. *
  2218. * Return: NULL on success,
  2219. * nbuf when it fails to send
  2220. */
  2221. qdf_nbuf_t
  2222. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2223. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2224. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2225. {
  2226. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2227. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2228. DP_MOD_ID_TX_EXCEPTION);
  2229. if (qdf_unlikely(!vdev))
  2230. goto fail;
  2231. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2232. == QDF_STATUS_E_FAILURE)) {
  2233. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2234. goto fail;
  2235. }
  2236. /* Unref count as it will agin be taken inside dp_tx_exception */
  2237. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2238. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2239. fail:
  2240. if (vdev)
  2241. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2242. dp_verbose_debug("pkt send failed");
  2243. return nbuf;
  2244. }
  2245. /**
  2246. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2247. * @soc: DP soc handle
  2248. * @vdev_id: DP vdev handle
  2249. * @nbuf: skb
  2250. *
  2251. * Entry point for Core Tx layer (DP_TX) invoked from
  2252. * hard_start_xmit in OSIF/HDD
  2253. *
  2254. * Return: NULL on success,
  2255. * nbuf when it fails to send
  2256. */
  2257. #ifdef MESH_MODE_SUPPORT
  2258. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2259. qdf_nbuf_t nbuf)
  2260. {
  2261. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2262. struct meta_hdr_s *mhdr;
  2263. qdf_nbuf_t nbuf_mesh = NULL;
  2264. qdf_nbuf_t nbuf_clone = NULL;
  2265. struct dp_vdev *vdev;
  2266. uint8_t no_enc_frame = 0;
  2267. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2268. if (!nbuf_mesh) {
  2269. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2270. "qdf_nbuf_unshare failed");
  2271. return nbuf;
  2272. }
  2273. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2274. if (!vdev) {
  2275. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2276. "vdev is NULL for vdev_id %d", vdev_id);
  2277. return nbuf;
  2278. }
  2279. nbuf = nbuf_mesh;
  2280. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2281. if ((vdev->sec_type != cdp_sec_type_none) &&
  2282. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2283. no_enc_frame = 1;
  2284. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2285. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2286. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2287. !no_enc_frame) {
  2288. nbuf_clone = qdf_nbuf_clone(nbuf);
  2289. if (!nbuf_clone) {
  2290. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2291. "qdf_nbuf_clone failed");
  2292. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2293. return nbuf;
  2294. }
  2295. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2296. }
  2297. if (nbuf_clone) {
  2298. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2299. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2300. } else {
  2301. qdf_nbuf_free(nbuf_clone);
  2302. }
  2303. }
  2304. if (no_enc_frame)
  2305. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2306. else
  2307. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2308. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2309. if ((!nbuf) && no_enc_frame) {
  2310. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2311. }
  2312. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2313. return nbuf;
  2314. }
  2315. #else
  2316. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2317. qdf_nbuf_t nbuf)
  2318. {
  2319. return dp_tx_send(soc, vdev_id, nbuf);
  2320. }
  2321. #endif
  2322. /**
  2323. * dp_tx_nawds_handler() - NAWDS handler
  2324. *
  2325. * @soc: DP soc handle
  2326. * @vdev_id: id of DP vdev handle
  2327. * @msdu_info: msdu_info required to create HTT metadata
  2328. * @nbuf: skb
  2329. *
  2330. * This API transfers the multicast frames with the peer id
  2331. * on NAWDS enabled peer.
  2332. * Return: none
  2333. */
  2334. static inline
  2335. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2336. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2337. {
  2338. struct dp_peer *peer = NULL;
  2339. qdf_nbuf_t nbuf_clone = NULL;
  2340. uint16_t peer_id = DP_INVALID_PEER;
  2341. uint16_t sa_peer_id = DP_INVALID_PEER;
  2342. struct dp_ast_entry *ast_entry = NULL;
  2343. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2344. if (qdf_nbuf_get_tx_ftype(nbuf) == CB_FTYPE_INTRABSS_FWD) {
  2345. qdf_spin_lock_bh(&soc->ast_lock);
  2346. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2347. (soc,
  2348. (uint8_t *)(eh->ether_shost),
  2349. vdev->pdev->pdev_id);
  2350. if (ast_entry)
  2351. sa_peer_id = ast_entry->peer_id;
  2352. qdf_spin_unlock_bh(&soc->ast_lock);
  2353. }
  2354. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2355. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2356. if (!peer->bss_peer && peer->nawds_enabled) {
  2357. peer_id = peer->peer_id;
  2358. /* Multicast packets needs to be
  2359. * dropped in case of intra bss forwarding
  2360. */
  2361. if (sa_peer_id == peer->peer_id) {
  2362. QDF_TRACE(QDF_MODULE_ID_DP,
  2363. QDF_TRACE_LEVEL_DEBUG,
  2364. " %s: multicast packet", __func__);
  2365. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  2366. continue;
  2367. }
  2368. nbuf_clone = qdf_nbuf_clone(nbuf);
  2369. if (!nbuf_clone) {
  2370. QDF_TRACE(QDF_MODULE_ID_DP,
  2371. QDF_TRACE_LEVEL_ERROR,
  2372. FL("nbuf clone failed"));
  2373. break;
  2374. }
  2375. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2376. msdu_info, peer_id,
  2377. NULL);
  2378. if (nbuf_clone) {
  2379. QDF_TRACE(QDF_MODULE_ID_DP,
  2380. QDF_TRACE_LEVEL_DEBUG,
  2381. FL("pkt send failed"));
  2382. qdf_nbuf_free(nbuf_clone);
  2383. } else {
  2384. if (peer_id != DP_INVALID_PEER)
  2385. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2386. 1, qdf_nbuf_len(nbuf));
  2387. }
  2388. }
  2389. }
  2390. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2391. }
  2392. /**
  2393. * dp_tx_send() - Transmit a frame on a given VAP
  2394. * @soc: DP soc handle
  2395. * @vdev_id: id of DP vdev handle
  2396. * @nbuf: skb
  2397. *
  2398. * Entry point for Core Tx layer (DP_TX) invoked from
  2399. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2400. * cases
  2401. *
  2402. * Return: NULL on success,
  2403. * nbuf when it fails to send
  2404. */
  2405. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2406. qdf_nbuf_t nbuf)
  2407. {
  2408. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2409. uint16_t peer_id = HTT_INVALID_PEER;
  2410. /*
  2411. * doing a memzero is causing additional function call overhead
  2412. * so doing static stack clearing
  2413. */
  2414. struct dp_tx_msdu_info_s msdu_info = {0};
  2415. struct dp_vdev *vdev = NULL;
  2416. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2417. return nbuf;
  2418. /*
  2419. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2420. * this in per packet path.
  2421. *
  2422. * As in this path vdev memory is already protected with netdev
  2423. * tx lock
  2424. */
  2425. vdev = soc->vdev_id_map[vdev_id];
  2426. if (qdf_unlikely(!vdev))
  2427. return nbuf;
  2428. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2429. QDF_MAC_ADDR_REF(nbuf->data));
  2430. /*
  2431. * Set Default Host TID value to invalid TID
  2432. * (TID override disabled)
  2433. */
  2434. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2435. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2436. if (qdf_unlikely(vdev->mesh_vdev)) {
  2437. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2438. &msdu_info);
  2439. if (!nbuf_mesh) {
  2440. dp_verbose_debug("Extracting mesh metadata failed");
  2441. return nbuf;
  2442. }
  2443. nbuf = nbuf_mesh;
  2444. }
  2445. /*
  2446. * Get HW Queue to use for this frame.
  2447. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2448. * dedicated for data and 1 for command.
  2449. * "queue_id" maps to one hardware ring.
  2450. * With each ring, we also associate a unique Tx descriptor pool
  2451. * to minimize lock contention for these resources.
  2452. */
  2453. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2454. /*
  2455. * TCL H/W supports 2 DSCP-TID mapping tables.
  2456. * Table 1 - Default DSCP-TID mapping table
  2457. * Table 2 - 1 DSCP-TID override table
  2458. *
  2459. * If we need a different DSCP-TID mapping for this vap,
  2460. * call tid_classify to extract DSCP/ToS from frame and
  2461. * map to a TID and store in msdu_info. This is later used
  2462. * to fill in TCL Input descriptor (per-packet TID override).
  2463. */
  2464. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2465. /*
  2466. * Classify the frame and call corresponding
  2467. * "prepare" function which extracts the segment (TSO)
  2468. * and fragmentation information (for TSO , SG, ME, or Raw)
  2469. * into MSDU_INFO structure which is later used to fill
  2470. * SW and HW descriptors.
  2471. */
  2472. if (qdf_nbuf_is_tso(nbuf)) {
  2473. dp_verbose_debug("TSO frame %pK", vdev);
  2474. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2475. qdf_nbuf_len(nbuf));
  2476. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2477. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2478. qdf_nbuf_len(nbuf));
  2479. return nbuf;
  2480. }
  2481. goto send_multiple;
  2482. }
  2483. /* SG */
  2484. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2485. struct dp_tx_seg_info_s seg_info = {0};
  2486. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2487. if (!nbuf)
  2488. return NULL;
  2489. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2490. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2491. qdf_nbuf_len(nbuf));
  2492. goto send_multiple;
  2493. }
  2494. #ifdef ATH_SUPPORT_IQUE
  2495. /* Mcast to Ucast Conversion*/
  2496. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  2497. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2498. qdf_nbuf_data(nbuf);
  2499. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2500. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2501. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2502. DP_STATS_INC_PKT(vdev,
  2503. tx_i.mcast_en.mcast_pkt, 1,
  2504. qdf_nbuf_len(nbuf));
  2505. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2506. QDF_STATUS_SUCCESS) {
  2507. return NULL;
  2508. }
  2509. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2510. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2511. QDF_STATUS_SUCCESS) {
  2512. return NULL;
  2513. }
  2514. }
  2515. }
  2516. }
  2517. #endif
  2518. /* RAW */
  2519. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2520. struct dp_tx_seg_info_s seg_info = {0};
  2521. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2522. if (!nbuf)
  2523. return NULL;
  2524. dp_verbose_debug("Raw frame %pK", vdev);
  2525. goto send_multiple;
  2526. }
  2527. if (qdf_unlikely(vdev->nawds_enabled)) {
  2528. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2529. qdf_nbuf_data(nbuf);
  2530. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2531. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2532. peer_id = DP_INVALID_PEER;
  2533. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2534. 1, qdf_nbuf_len(nbuf));
  2535. }
  2536. /* Single linear frame */
  2537. /*
  2538. * If nbuf is a simple linear frame, use send_single function to
  2539. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2540. * SRNG. There is no need to setup a MSDU extension descriptor.
  2541. */
  2542. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2543. return nbuf;
  2544. send_multiple:
  2545. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2546. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2547. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2548. return nbuf;
  2549. }
  2550. /**
  2551. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  2552. * case to vaoid check in perpkt path.
  2553. * @soc: DP soc handle
  2554. * @vdev_id: id of DP vdev handle
  2555. * @nbuf: skb
  2556. *
  2557. * Entry point for Core Tx layer (DP_TX) invoked from
  2558. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  2559. * with special condition to avoid per pkt check in dp_tx_send
  2560. *
  2561. * Return: NULL on success,
  2562. * nbuf when it fails to send
  2563. */
  2564. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2565. uint8_t vdev_id, qdf_nbuf_t nbuf)
  2566. {
  2567. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2568. struct dp_vdev *vdev = NULL;
  2569. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2570. return nbuf;
  2571. /*
  2572. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2573. * this in per packet path.
  2574. *
  2575. * As in this path vdev memory is already protected with netdev
  2576. * tx lock
  2577. */
  2578. vdev = soc->vdev_id_map[vdev_id];
  2579. if (qdf_unlikely(!vdev))
  2580. return nbuf;
  2581. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2582. == QDF_STATUS_E_FAILURE)) {
  2583. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2584. return nbuf;
  2585. }
  2586. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  2587. }
  2588. /**
  2589. * dp_tx_reinject_handler() - Tx Reinject Handler
  2590. * @soc: datapath soc handle
  2591. * @vdev: datapath vdev handle
  2592. * @tx_desc: software descriptor head pointer
  2593. * @status : Tx completion status from HTT descriptor
  2594. *
  2595. * This function reinjects frames back to Target.
  2596. * Todo - Host queue needs to be added
  2597. *
  2598. * Return: none
  2599. */
  2600. static
  2601. void dp_tx_reinject_handler(struct dp_soc *soc,
  2602. struct dp_vdev *vdev,
  2603. struct dp_tx_desc_s *tx_desc,
  2604. uint8_t *status)
  2605. {
  2606. struct dp_peer *peer = NULL;
  2607. uint32_t peer_id = HTT_INVALID_PEER;
  2608. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2609. qdf_nbuf_t nbuf_copy = NULL;
  2610. struct dp_tx_msdu_info_s msdu_info;
  2611. #ifdef WDS_VENDOR_EXTENSION
  2612. int is_mcast = 0, is_ucast = 0;
  2613. int num_peers_3addr = 0;
  2614. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2615. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2616. #endif
  2617. qdf_assert(vdev);
  2618. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2619. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2620. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2621. "%s Tx reinject path", __func__);
  2622. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2623. qdf_nbuf_len(tx_desc->nbuf));
  2624. #ifdef WDS_VENDOR_EXTENSION
  2625. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2626. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2627. } else {
  2628. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2629. }
  2630. is_ucast = !is_mcast;
  2631. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2632. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2633. if (peer->bss_peer)
  2634. continue;
  2635. /* Detect wds peers that use 3-addr framing for mcast.
  2636. * if there are any, the bss_peer is used to send the
  2637. * the mcast frame using 3-addr format. all wds enabled
  2638. * peers that use 4-addr framing for mcast frames will
  2639. * be duplicated and sent as 4-addr frames below.
  2640. */
  2641. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2642. num_peers_3addr = 1;
  2643. break;
  2644. }
  2645. }
  2646. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2647. #endif
  2648. if (qdf_unlikely(vdev->mesh_vdev)) {
  2649. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2650. } else {
  2651. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2652. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2653. if ((peer->peer_id != HTT_INVALID_PEER) &&
  2654. #ifdef WDS_VENDOR_EXTENSION
  2655. /*
  2656. * . if 3-addr STA, then send on BSS Peer
  2657. * . if Peer WDS enabled and accept 4-addr mcast,
  2658. * send mcast on that peer only
  2659. * . if Peer WDS enabled and accept 4-addr ucast,
  2660. * send ucast on that peer only
  2661. */
  2662. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2663. (peer->wds_enabled &&
  2664. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2665. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2666. #else
  2667. ((peer->bss_peer &&
  2668. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))))) {
  2669. #endif
  2670. peer_id = DP_INVALID_PEER;
  2671. nbuf_copy = qdf_nbuf_copy(nbuf);
  2672. if (!nbuf_copy) {
  2673. QDF_TRACE(QDF_MODULE_ID_DP,
  2674. QDF_TRACE_LEVEL_DEBUG,
  2675. FL("nbuf copy failed"));
  2676. break;
  2677. }
  2678. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2679. nbuf_copy,
  2680. &msdu_info,
  2681. peer_id,
  2682. NULL);
  2683. if (nbuf_copy) {
  2684. QDF_TRACE(QDF_MODULE_ID_DP,
  2685. QDF_TRACE_LEVEL_DEBUG,
  2686. FL("pkt send failed"));
  2687. qdf_nbuf_free(nbuf_copy);
  2688. }
  2689. }
  2690. }
  2691. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2692. }
  2693. qdf_nbuf_free(nbuf);
  2694. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2695. }
  2696. /**
  2697. * dp_tx_inspect_handler() - Tx Inspect Handler
  2698. * @soc: datapath soc handle
  2699. * @vdev: datapath vdev handle
  2700. * @tx_desc: software descriptor head pointer
  2701. * @status : Tx completion status from HTT descriptor
  2702. *
  2703. * Handles Tx frames sent back to Host for inspection
  2704. * (ProxyARP)
  2705. *
  2706. * Return: none
  2707. */
  2708. static void dp_tx_inspect_handler(struct dp_soc *soc,
  2709. struct dp_vdev *vdev,
  2710. struct dp_tx_desc_s *tx_desc,
  2711. uint8_t *status)
  2712. {
  2713. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2714. "%s Tx inspect path",
  2715. __func__);
  2716. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  2717. qdf_nbuf_len(tx_desc->nbuf));
  2718. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2719. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2720. }
  2721. #ifdef FEATURE_PERPKT_INFO
  2722. /**
  2723. * dp_get_completion_indication_for_stack() - send completion to stack
  2724. * @soc : dp_soc handle
  2725. * @pdev: dp_pdev handle
  2726. * @peer: dp peer handle
  2727. * @ts: transmit completion status structure
  2728. * @netbuf: Buffer pointer for free
  2729. *
  2730. * This function is used for indication whether buffer needs to be
  2731. * sent to stack for freeing or not
  2732. */
  2733. QDF_STATUS
  2734. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2735. struct dp_pdev *pdev,
  2736. struct dp_peer *peer,
  2737. struct hal_tx_completion_status *ts,
  2738. qdf_nbuf_t netbuf,
  2739. uint64_t time_latency)
  2740. {
  2741. struct tx_capture_hdr *ppdu_hdr;
  2742. uint16_t peer_id = ts->peer_id;
  2743. uint32_t ppdu_id = ts->ppdu_id;
  2744. uint8_t first_msdu = ts->first_msdu;
  2745. uint8_t last_msdu = ts->last_msdu;
  2746. uint32_t txcap_hdr_size = sizeof(struct tx_capture_hdr);
  2747. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2748. !pdev->latency_capture_enable))
  2749. return QDF_STATUS_E_NOSUPPORT;
  2750. if (!peer) {
  2751. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2752. FL("Peer Invalid"));
  2753. return QDF_STATUS_E_INVAL;
  2754. }
  2755. if (pdev->mcopy_mode) {
  2756. /* If mcopy is enabled and mcopy_mode is M_COPY deliver 1st MSDU
  2757. * per PPDU. If mcopy_mode is M_COPY_EXTENDED deliver 1st MSDU
  2758. * for each MPDU
  2759. */
  2760. if (pdev->mcopy_mode == M_COPY) {
  2761. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2762. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2763. return QDF_STATUS_E_INVAL;
  2764. }
  2765. }
  2766. if (!first_msdu)
  2767. return QDF_STATUS_E_INVAL;
  2768. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2769. pdev->m_copy_id.tx_peer_id = peer_id;
  2770. }
  2771. if (qdf_unlikely(qdf_nbuf_headroom(netbuf) < txcap_hdr_size)) {
  2772. netbuf = qdf_nbuf_realloc_headroom(netbuf, txcap_hdr_size);
  2773. if (!netbuf) {
  2774. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2775. FL("No headroom"));
  2776. return QDF_STATUS_E_NOMEM;
  2777. }
  2778. }
  2779. if (!qdf_nbuf_push_head(netbuf, txcap_hdr_size)) {
  2780. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2781. FL("No headroom"));
  2782. return QDF_STATUS_E_NOMEM;
  2783. }
  2784. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2785. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2786. QDF_MAC_ADDR_SIZE);
  2787. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2788. QDF_MAC_ADDR_SIZE);
  2789. ppdu_hdr->ppdu_id = ppdu_id;
  2790. ppdu_hdr->peer_id = peer_id;
  2791. ppdu_hdr->first_msdu = first_msdu;
  2792. ppdu_hdr->last_msdu = last_msdu;
  2793. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2794. ppdu_hdr->tsf = ts->tsf;
  2795. ppdu_hdr->time_latency = time_latency;
  2796. }
  2797. return QDF_STATUS_SUCCESS;
  2798. }
  2799. /**
  2800. * dp_send_completion_to_stack() - send completion to stack
  2801. * @soc : dp_soc handle
  2802. * @pdev: dp_pdev handle
  2803. * @peer_id: peer_id of the peer for which completion came
  2804. * @ppdu_id: ppdu_id
  2805. * @netbuf: Buffer pointer for free
  2806. *
  2807. * This function is used to send completion to stack
  2808. * to free buffer
  2809. */
  2810. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2811. uint16_t peer_id, uint32_t ppdu_id,
  2812. qdf_nbuf_t netbuf)
  2813. {
  2814. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2815. netbuf, peer_id,
  2816. WDI_NO_VAL, pdev->pdev_id);
  2817. }
  2818. #else
  2819. static QDF_STATUS
  2820. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2821. struct dp_pdev *pdev,
  2822. struct dp_peer *peer,
  2823. struct hal_tx_completion_status *ts,
  2824. qdf_nbuf_t netbuf,
  2825. uint64_t time_latency)
  2826. {
  2827. return QDF_STATUS_E_NOSUPPORT;
  2828. }
  2829. static void
  2830. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2831. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2832. {
  2833. }
  2834. #endif
  2835. /**
  2836. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2837. * @soc: Soc handle
  2838. * @desc: software Tx descriptor to be processed
  2839. *
  2840. * Return: none
  2841. */
  2842. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2843. struct dp_tx_desc_s *desc)
  2844. {
  2845. qdf_nbuf_t nbuf = desc->nbuf;
  2846. /* nbuf already freed in vdev detach path */
  2847. if (!nbuf)
  2848. return;
  2849. /* If it is TDLS mgmt, don't unmap or free the frame */
  2850. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2851. return dp_non_std_tx_comp_free_buff(soc, desc);
  2852. /* 0 : MSDU buffer, 1 : MLE */
  2853. if (desc->msdu_ext_desc) {
  2854. /* TSO free */
  2855. if (hal_tx_ext_desc_get_tso_enable(
  2856. desc->msdu_ext_desc->vaddr)) {
  2857. /* unmap eash TSO seg before free the nbuf */
  2858. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2859. desc->tso_num_desc);
  2860. qdf_nbuf_free(nbuf);
  2861. return;
  2862. }
  2863. }
  2864. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2865. QDF_DMA_TO_DEVICE, nbuf->len);
  2866. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2867. return dp_mesh_tx_comp_free_buff(soc, desc);
  2868. qdf_nbuf_free(nbuf);
  2869. }
  2870. #ifdef MESH_MODE_SUPPORT
  2871. /**
  2872. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2873. * in mesh meta header
  2874. * @tx_desc: software descriptor head pointer
  2875. * @ts: pointer to tx completion stats
  2876. * Return: none
  2877. */
  2878. static
  2879. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2880. struct hal_tx_completion_status *ts)
  2881. {
  2882. struct meta_hdr_s *mhdr;
  2883. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2884. if (!tx_desc->msdu_ext_desc) {
  2885. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2886. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2887. "netbuf %pK offset %d",
  2888. netbuf, tx_desc->pkt_offset);
  2889. return;
  2890. }
  2891. }
  2892. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2893. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2894. "netbuf %pK offset %lu", netbuf,
  2895. sizeof(struct meta_hdr_s));
  2896. return;
  2897. }
  2898. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2899. mhdr->rssi = ts->ack_frame_rssi;
  2900. mhdr->band = tx_desc->pdev->operating_channel.band;
  2901. mhdr->channel = tx_desc->pdev->operating_channel.num;
  2902. }
  2903. #else
  2904. static
  2905. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2906. struct hal_tx_completion_status *ts)
  2907. {
  2908. }
  2909. #endif
  2910. #ifdef QCA_PEER_EXT_STATS
  2911. /*
  2912. * dp_tx_compute_tid_delay() - Compute per TID delay
  2913. * @stats: Per TID delay stats
  2914. * @tx_desc: Software Tx descriptor
  2915. *
  2916. * Compute the software enqueue and hw enqueue delays and
  2917. * update the respective histograms
  2918. *
  2919. * Return: void
  2920. */
  2921. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  2922. struct dp_tx_desc_s *tx_desc)
  2923. {
  2924. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  2925. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2926. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  2927. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  2928. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2929. timestamp_hw_enqueue = tx_desc->timestamp;
  2930. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2931. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2932. timestamp_hw_enqueue);
  2933. /*
  2934. * Update the Tx software enqueue delay and HW enque-Completion delay.
  2935. */
  2936. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  2937. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  2938. }
  2939. /*
  2940. * dp_tx_update_peer_ext_stats() - Update the peer extended stats
  2941. * @peer: DP peer context
  2942. * @tx_desc: Tx software descriptor
  2943. * @tid: Transmission ID
  2944. * @ring_id: Rx CPU context ID/CPU_ID
  2945. *
  2946. * Update the peer extended stats. These are enhanced other
  2947. * delay stats per msdu level.
  2948. *
  2949. * Return: void
  2950. */
  2951. static void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  2952. struct dp_tx_desc_s *tx_desc,
  2953. uint8_t tid, uint8_t ring_id)
  2954. {
  2955. struct dp_pdev *pdev = peer->vdev->pdev;
  2956. struct dp_soc *soc = NULL;
  2957. struct cdp_peer_ext_stats *pext_stats = NULL;
  2958. soc = pdev->soc;
  2959. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  2960. return;
  2961. pext_stats = peer->pext_stats;
  2962. qdf_assert(pext_stats);
  2963. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  2964. /*
  2965. * For non-TID packets use the TID 9
  2966. */
  2967. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2968. tid = CDP_MAX_DATA_TIDS - 1;
  2969. dp_tx_compute_tid_delay(&pext_stats->delay_stats[tid][ring_id],
  2970. tx_desc);
  2971. }
  2972. #else
  2973. static inline void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  2974. struct dp_tx_desc_s *tx_desc,
  2975. uint8_t tid, uint8_t ring_id)
  2976. {
  2977. }
  2978. #endif
  2979. /**
  2980. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2981. * to pass in correct fields
  2982. *
  2983. * @vdev: pdev handle
  2984. * @tx_desc: tx descriptor
  2985. * @tid: tid value
  2986. * @ring_id: TCL or WBM ring number for transmit path
  2987. * Return: none
  2988. */
  2989. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2990. struct dp_tx_desc_s *tx_desc,
  2991. uint8_t tid, uint8_t ring_id)
  2992. {
  2993. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2994. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2995. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2996. return;
  2997. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  2998. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2999. timestamp_hw_enqueue = tx_desc->timestamp;
  3000. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3001. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3002. timestamp_hw_enqueue);
  3003. interframe_delay = (uint32_t)(timestamp_ingress -
  3004. vdev->prev_tx_enq_tstamp);
  3005. /*
  3006. * Delay in software enqueue
  3007. */
  3008. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  3009. CDP_DELAY_STATS_SW_ENQ, ring_id);
  3010. /*
  3011. * Delay between packet enqueued to HW and Tx completion
  3012. */
  3013. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  3014. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  3015. /*
  3016. * Update interframe delay stats calculated at hardstart receive point.
  3017. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3018. * interframe delay will not be calculate correctly for 1st frame.
  3019. * On the other side, this will help in avoiding extra per packet check
  3020. * of !vdev->prev_tx_enq_tstamp.
  3021. */
  3022. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  3023. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  3024. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3025. }
  3026. #ifdef DISABLE_DP_STATS
  3027. static
  3028. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3029. {
  3030. }
  3031. #else
  3032. static
  3033. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3034. {
  3035. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3036. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3037. if (subtype != QDF_PROTO_INVALID)
  3038. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  3039. }
  3040. #endif
  3041. /**
  3042. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3043. * per wbm ring
  3044. *
  3045. * @tx_desc: software descriptor head pointer
  3046. * @ts: Tx completion status
  3047. * @peer: peer handle
  3048. * @ring_id: ring number
  3049. *
  3050. * Return: None
  3051. */
  3052. static inline void
  3053. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3054. struct hal_tx_completion_status *ts,
  3055. struct dp_peer *peer, uint8_t ring_id)
  3056. {
  3057. struct dp_pdev *pdev = peer->vdev->pdev;
  3058. struct dp_soc *soc = NULL;
  3059. uint8_t mcs, pkt_type;
  3060. uint8_t tid = ts->tid;
  3061. uint32_t length;
  3062. struct cdp_tid_tx_stats *tid_stats;
  3063. if (!pdev)
  3064. return;
  3065. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3066. tid = CDP_MAX_DATA_TIDS - 1;
  3067. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3068. soc = pdev->soc;
  3069. mcs = ts->mcs;
  3070. pkt_type = ts->pkt_type;
  3071. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3072. dp_err("Release source is not from TQM");
  3073. return;
  3074. }
  3075. length = qdf_nbuf_len(tx_desc->nbuf);
  3076. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  3077. if (qdf_unlikely(pdev->delay_stats_flag))
  3078. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  3079. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  3080. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  3081. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  3082. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3083. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  3084. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  3085. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  3086. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  3087. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  3088. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  3089. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  3090. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  3091. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  3092. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  3093. /*
  3094. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  3095. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  3096. * are no completions for failed cases. Hence updating tx_failed from
  3097. * data path. Please note that if tx_failed is fixed to be from ppdu,
  3098. * then this has to be removed
  3099. */
  3100. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  3101. peer->stats.tx.dropped.fw_rem_notx +
  3102. peer->stats.tx.dropped.fw_rem_tx +
  3103. peer->stats.tx.dropped.age_out +
  3104. peer->stats.tx.dropped.fw_reason1 +
  3105. peer->stats.tx.dropped.fw_reason2 +
  3106. peer->stats.tx.dropped.fw_reason3;
  3107. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3108. tid_stats->tqm_status_cnt[ts->status]++;
  3109. }
  3110. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3111. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  3112. return;
  3113. }
  3114. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  3115. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  3116. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  3117. /*
  3118. * Following Rate Statistics are updated from HTT PPDU events from FW.
  3119. * Return from here if HTT PPDU events are enabled.
  3120. */
  3121. if (!(soc->process_tx_status))
  3122. return;
  3123. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3124. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  3125. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3126. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  3127. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3128. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3129. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3130. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3131. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3132. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3133. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3134. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3135. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3136. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3137. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3138. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3139. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3140. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3141. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3142. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3143. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  3144. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  3145. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3146. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3147. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  3148. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  3149. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  3150. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  3151. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  3152. &peer->stats, ts->peer_id,
  3153. UPDATE_PEER_STATS, pdev->pdev_id);
  3154. #endif
  3155. }
  3156. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3157. /**
  3158. * dp_tx_flow_pool_lock() - take flow pool lock
  3159. * @soc: core txrx main context
  3160. * @tx_desc: tx desc
  3161. *
  3162. * Return: None
  3163. */
  3164. static inline
  3165. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3166. struct dp_tx_desc_s *tx_desc)
  3167. {
  3168. struct dp_tx_desc_pool_s *pool;
  3169. uint8_t desc_pool_id;
  3170. desc_pool_id = tx_desc->pool_id;
  3171. pool = &soc->tx_desc[desc_pool_id];
  3172. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3173. }
  3174. /**
  3175. * dp_tx_flow_pool_unlock() - release flow pool lock
  3176. * @soc: core txrx main context
  3177. * @tx_desc: tx desc
  3178. *
  3179. * Return: None
  3180. */
  3181. static inline
  3182. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3183. struct dp_tx_desc_s *tx_desc)
  3184. {
  3185. struct dp_tx_desc_pool_s *pool;
  3186. uint8_t desc_pool_id;
  3187. desc_pool_id = tx_desc->pool_id;
  3188. pool = &soc->tx_desc[desc_pool_id];
  3189. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3190. }
  3191. #else
  3192. static inline
  3193. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3194. {
  3195. }
  3196. static inline
  3197. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3198. {
  3199. }
  3200. #endif
  3201. /**
  3202. * dp_tx_notify_completion() - Notify tx completion for this desc
  3203. * @soc: core txrx main context
  3204. * @vdev: datapath vdev handle
  3205. * @tx_desc: tx desc
  3206. * @netbuf: buffer
  3207. * @status: tx status
  3208. *
  3209. * Return: none
  3210. */
  3211. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3212. struct dp_vdev *vdev,
  3213. struct dp_tx_desc_s *tx_desc,
  3214. qdf_nbuf_t netbuf,
  3215. uint8_t status)
  3216. {
  3217. void *osif_dev;
  3218. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3219. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3220. qdf_assert(tx_desc);
  3221. dp_tx_flow_pool_lock(soc, tx_desc);
  3222. if (!vdev ||
  3223. !vdev->osif_vdev) {
  3224. dp_tx_flow_pool_unlock(soc, tx_desc);
  3225. return;
  3226. }
  3227. osif_dev = vdev->osif_vdev;
  3228. tx_compl_cbk = vdev->tx_comp;
  3229. dp_tx_flow_pool_unlock(soc, tx_desc);
  3230. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3231. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3232. if (tx_compl_cbk)
  3233. tx_compl_cbk(netbuf, osif_dev, flag);
  3234. }
  3235. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3236. * @pdev: pdev handle
  3237. * @tid: tid value
  3238. * @txdesc_ts: timestamp from txdesc
  3239. * @ppdu_id: ppdu id
  3240. *
  3241. * Return: none
  3242. */
  3243. #ifdef FEATURE_PERPKT_INFO
  3244. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3245. struct dp_peer *peer,
  3246. uint8_t tid,
  3247. uint64_t txdesc_ts,
  3248. uint32_t ppdu_id)
  3249. {
  3250. uint64_t delta_ms;
  3251. struct cdp_tx_sojourn_stats *sojourn_stats;
  3252. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  3253. return;
  3254. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3255. tid >= CDP_DATA_TID_MAX))
  3256. return;
  3257. if (qdf_unlikely(!pdev->sojourn_buf))
  3258. return;
  3259. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3260. qdf_nbuf_data(pdev->sojourn_buf);
  3261. sojourn_stats->cookie = (void *)peer->rdkstats_ctx;
  3262. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  3263. txdesc_ts;
  3264. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  3265. delta_ms);
  3266. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3267. sojourn_stats->num_msdus[tid] = 1;
  3268. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3269. peer->avg_sojourn_msdu[tid].internal;
  3270. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3271. pdev->sojourn_buf, HTT_INVALID_PEER,
  3272. WDI_NO_VAL, pdev->pdev_id);
  3273. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3274. sojourn_stats->num_msdus[tid] = 0;
  3275. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3276. }
  3277. #else
  3278. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3279. struct dp_peer *peer,
  3280. uint8_t tid,
  3281. uint64_t txdesc_ts,
  3282. uint32_t ppdu_id)
  3283. {
  3284. }
  3285. #endif
  3286. /**
  3287. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3288. * @soc: DP Soc handle
  3289. * @tx_desc: software Tx descriptor
  3290. * @ts : Tx completion status from HAL/HTT descriptor
  3291. *
  3292. * Return: none
  3293. */
  3294. static inline void
  3295. dp_tx_comp_process_desc(struct dp_soc *soc,
  3296. struct dp_tx_desc_s *desc,
  3297. struct hal_tx_completion_status *ts,
  3298. struct dp_peer *peer)
  3299. {
  3300. uint64_t time_latency = 0;
  3301. /*
  3302. * m_copy/tx_capture modes are not supported for
  3303. * scatter gather packets
  3304. */
  3305. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3306. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3307. desc->timestamp);
  3308. }
  3309. if (!(desc->msdu_ext_desc)) {
  3310. if (QDF_STATUS_SUCCESS ==
  3311. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  3312. return;
  3313. }
  3314. if (QDF_STATUS_SUCCESS ==
  3315. dp_get_completion_indication_for_stack(soc,
  3316. desc->pdev,
  3317. peer, ts,
  3318. desc->nbuf,
  3319. time_latency)) {
  3320. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  3321. QDF_DMA_TO_DEVICE,
  3322. desc->nbuf->len);
  3323. dp_send_completion_to_stack(soc,
  3324. desc->pdev,
  3325. ts->peer_id,
  3326. ts->ppdu_id,
  3327. desc->nbuf);
  3328. return;
  3329. }
  3330. }
  3331. dp_tx_comp_free_buf(soc, desc);
  3332. }
  3333. #ifdef DISABLE_DP_STATS
  3334. /**
  3335. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3336. * @soc: core txrx main context
  3337. * @tx_desc: tx desc
  3338. * @status: tx status
  3339. *
  3340. * Return: none
  3341. */
  3342. static inline
  3343. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3344. struct dp_vdev *vdev,
  3345. struct dp_tx_desc_s *tx_desc,
  3346. uint8_t status)
  3347. {
  3348. }
  3349. #else
  3350. static inline
  3351. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3352. struct dp_vdev *vdev,
  3353. struct dp_tx_desc_s *tx_desc,
  3354. uint8_t status)
  3355. {
  3356. void *osif_dev;
  3357. ol_txrx_stats_rx_fp stats_cbk;
  3358. uint8_t pkt_type;
  3359. qdf_assert(tx_desc);
  3360. if (!vdev ||
  3361. !vdev->osif_vdev ||
  3362. !vdev->stats_cb)
  3363. return;
  3364. osif_dev = vdev->osif_vdev;
  3365. stats_cbk = vdev->stats_cb;
  3366. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3367. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3368. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3369. &pkt_type);
  3370. }
  3371. #endif
  3372. /**
  3373. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3374. * @soc: DP soc handle
  3375. * @tx_desc: software descriptor head pointer
  3376. * @ts: Tx completion status
  3377. * @peer: peer handle
  3378. * @ring_id: ring number
  3379. *
  3380. * Return: none
  3381. */
  3382. static inline
  3383. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3384. struct dp_tx_desc_s *tx_desc,
  3385. struct hal_tx_completion_status *ts,
  3386. struct dp_peer *peer, uint8_t ring_id)
  3387. {
  3388. uint32_t length;
  3389. qdf_ether_header_t *eh;
  3390. struct dp_vdev *vdev = NULL;
  3391. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3392. uint8_t dp_status;
  3393. if (!nbuf) {
  3394. dp_info_rl("invalid tx descriptor. nbuf NULL");
  3395. goto out;
  3396. }
  3397. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3398. length = qdf_nbuf_len(nbuf);
  3399. dp_status = qdf_dp_get_status_from_htt(ts->status);
  3400. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3401. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3402. QDF_TRACE_DEFAULT_PDEV_ID,
  3403. qdf_nbuf_data_addr(nbuf),
  3404. sizeof(qdf_nbuf_data(nbuf)),
  3405. tx_desc->id,
  3406. dp_status));
  3407. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3408. "-------------------- \n"
  3409. "Tx Completion Stats: \n"
  3410. "-------------------- \n"
  3411. "ack_frame_rssi = %d \n"
  3412. "first_msdu = %d \n"
  3413. "last_msdu = %d \n"
  3414. "msdu_part_of_amsdu = %d \n"
  3415. "rate_stats valid = %d \n"
  3416. "bw = %d \n"
  3417. "pkt_type = %d \n"
  3418. "stbc = %d \n"
  3419. "ldpc = %d \n"
  3420. "sgi = %d \n"
  3421. "mcs = %d \n"
  3422. "ofdma = %d \n"
  3423. "tones_in_ru = %d \n"
  3424. "tsf = %d \n"
  3425. "ppdu_id = %d \n"
  3426. "transmit_cnt = %d \n"
  3427. "tid = %d \n"
  3428. "peer_id = %d\n",
  3429. ts->ack_frame_rssi, ts->first_msdu,
  3430. ts->last_msdu, ts->msdu_part_of_amsdu,
  3431. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3432. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3433. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3434. ts->transmit_cnt, ts->tid, ts->peer_id);
  3435. /* Update SoC level stats */
  3436. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3437. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3438. if (!peer) {
  3439. dp_err_rl("peer is null or deletion in progress");
  3440. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3441. goto out;
  3442. }
  3443. vdev = peer->vdev;
  3444. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  3445. /* Update per-packet stats for mesh mode */
  3446. if (qdf_unlikely(vdev->mesh_vdev) &&
  3447. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3448. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3449. /* Update peer level stats */
  3450. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  3451. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3452. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  3453. if ((peer->vdev->tx_encap_type ==
  3454. htt_cmn_pkt_type_ethernet) &&
  3455. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3456. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  3457. }
  3458. }
  3459. } else {
  3460. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3461. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3462. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3463. if (qdf_unlikely(peer->in_twt)) {
  3464. DP_STATS_INC_PKT(peer,
  3465. tx.tx_success_twt,
  3466. 1, length);
  3467. }
  3468. }
  3469. }
  3470. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3471. dp_tx_update_peer_ext_stats(peer, tx_desc, ts->tid, ring_id);
  3472. #ifdef QCA_SUPPORT_RDK_STATS
  3473. if (soc->rdkstats_enabled)
  3474. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3475. tx_desc->timestamp,
  3476. ts->ppdu_id);
  3477. #endif
  3478. out:
  3479. return;
  3480. }
  3481. /**
  3482. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3483. * @soc: core txrx main context
  3484. * @comp_head: software descriptor head pointer
  3485. * @ring_id: ring number
  3486. *
  3487. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3488. * and release the software descriptors after processing is complete
  3489. *
  3490. * Return: none
  3491. */
  3492. static void
  3493. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3494. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3495. {
  3496. struct dp_tx_desc_s *desc;
  3497. struct dp_tx_desc_s *next;
  3498. struct hal_tx_completion_status ts;
  3499. struct dp_peer *peer = NULL;
  3500. uint16_t peer_id = DP_INVALID_PEER;
  3501. qdf_nbuf_t netbuf;
  3502. desc = comp_head;
  3503. while (desc) {
  3504. if (peer_id != desc->peer_id) {
  3505. if (peer)
  3506. dp_peer_unref_delete(peer,
  3507. DP_MOD_ID_TX_COMP);
  3508. peer_id = desc->peer_id;
  3509. peer = dp_peer_get_ref_by_id(soc, peer_id,
  3510. DP_MOD_ID_TX_COMP);
  3511. }
  3512. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3513. struct dp_pdev *pdev = desc->pdev;
  3514. if (qdf_likely(peer)) {
  3515. /*
  3516. * Increment peer statistics
  3517. * Minimal statistics update done here
  3518. */
  3519. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1,
  3520. desc->length);
  3521. if (desc->tx_status !=
  3522. HAL_TX_TQM_RR_FRAME_ACKED)
  3523. DP_STATS_INC(peer, tx.tx_failed, 1);
  3524. }
  3525. qdf_assert(pdev);
  3526. dp_tx_outstanding_dec(pdev);
  3527. /*
  3528. * Calling a QDF WRAPPER here is creating signifcant
  3529. * performance impact so avoided the wrapper call here
  3530. */
  3531. next = desc->next;
  3532. qdf_mem_unmap_nbytes_single(soc->osdev,
  3533. desc->dma_addr,
  3534. QDF_DMA_TO_DEVICE,
  3535. desc->length);
  3536. qdf_nbuf_free(desc->nbuf);
  3537. dp_tx_desc_free(soc, desc, desc->pool_id);
  3538. desc = next;
  3539. continue;
  3540. }
  3541. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3542. dp_tx_comp_process_tx_status(soc, desc, &ts, peer, ring_id);
  3543. netbuf = desc->nbuf;
  3544. /* check tx complete notification */
  3545. if (peer &&
  3546. QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  3547. dp_tx_notify_completion(soc, peer->vdev, desc,
  3548. netbuf, ts.status);
  3549. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3550. next = desc->next;
  3551. dp_tx_desc_release(desc, desc->pool_id);
  3552. desc = next;
  3553. }
  3554. if (peer)
  3555. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3556. }
  3557. /**
  3558. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  3559. * @tx_desc: software descriptor head pointer
  3560. * @status : Tx completion status from HTT descriptor
  3561. * @ring_id: ring number
  3562. *
  3563. * This function will process HTT Tx indication messages from Target
  3564. *
  3565. * Return: none
  3566. */
  3567. static
  3568. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  3569. uint8_t ring_id)
  3570. {
  3571. uint8_t tx_status;
  3572. struct dp_pdev *pdev;
  3573. struct dp_vdev *vdev;
  3574. struct dp_soc *soc;
  3575. struct hal_tx_completion_status ts = {0};
  3576. uint32_t *htt_desc = (uint32_t *)status;
  3577. struct dp_peer *peer;
  3578. struct cdp_tid_tx_stats *tid_stats = NULL;
  3579. struct htt_soc *htt_handle;
  3580. /*
  3581. * If the descriptor is already freed in vdev_detach,
  3582. * continue to next descriptor
  3583. */
  3584. if ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) && !tx_desc->flags) {
  3585. QDF_TRACE(QDF_MODULE_ID_DP,
  3586. QDF_TRACE_LEVEL_INFO,
  3587. "Descriptor freed in vdev_detach %d",
  3588. tx_desc->id);
  3589. return;
  3590. }
  3591. pdev = tx_desc->pdev;
  3592. soc = pdev->soc;
  3593. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3594. QDF_TRACE(QDF_MODULE_ID_DP,
  3595. QDF_TRACE_LEVEL_INFO,
  3596. "pdev in down state %d",
  3597. tx_desc->id);
  3598. dp_tx_comp_free_buf(soc, tx_desc);
  3599. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3600. return;
  3601. }
  3602. qdf_assert(tx_desc->pdev);
  3603. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  3604. DP_MOD_ID_HTT_COMP);
  3605. if (!vdev)
  3606. return;
  3607. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3608. htt_handle = (struct htt_soc *)soc->htt_handle;
  3609. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3610. switch (tx_status) {
  3611. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3612. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3613. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3614. {
  3615. uint8_t tid;
  3616. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3617. ts.peer_id =
  3618. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3619. htt_desc[2]);
  3620. ts.tid =
  3621. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3622. htt_desc[2]);
  3623. } else {
  3624. ts.peer_id = HTT_INVALID_PEER;
  3625. ts.tid = HTT_INVALID_TID;
  3626. }
  3627. ts.ppdu_id =
  3628. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3629. htt_desc[1]);
  3630. ts.ack_frame_rssi =
  3631. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3632. htt_desc[1]);
  3633. ts.tsf = htt_desc[3];
  3634. ts.first_msdu = 1;
  3635. ts.last_msdu = 1;
  3636. tid = ts.tid;
  3637. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3638. tid = CDP_MAX_DATA_TIDS - 1;
  3639. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3640. if (qdf_unlikely(pdev->delay_stats_flag))
  3641. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3642. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3643. tid_stats->htt_status_cnt[tx_status]++;
  3644. }
  3645. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3646. DP_MOD_ID_HTT_COMP);
  3647. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, peer, ring_id);
  3648. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3649. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3650. if (qdf_likely(peer))
  3651. dp_peer_unref_delete(peer, DP_MOD_ID_HTT_COMP);
  3652. break;
  3653. }
  3654. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3655. {
  3656. dp_tx_reinject_handler(soc, vdev, tx_desc, status);
  3657. break;
  3658. }
  3659. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3660. {
  3661. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  3662. break;
  3663. }
  3664. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  3665. {
  3666. dp_tx_mec_handler(vdev, status);
  3667. break;
  3668. }
  3669. default:
  3670. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3671. "%s Invalid HTT tx_status %d\n",
  3672. __func__, tx_status);
  3673. break;
  3674. }
  3675. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3676. }
  3677. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3678. static inline
  3679. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3680. {
  3681. bool limit_hit = false;
  3682. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3683. limit_hit =
  3684. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  3685. if (limit_hit)
  3686. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3687. return limit_hit;
  3688. }
  3689. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3690. {
  3691. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3692. }
  3693. #else
  3694. static inline
  3695. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3696. {
  3697. return false;
  3698. }
  3699. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3700. {
  3701. return false;
  3702. }
  3703. #endif
  3704. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3705. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3706. uint32_t quota)
  3707. {
  3708. void *tx_comp_hal_desc;
  3709. uint8_t buffer_src;
  3710. uint8_t pool_id;
  3711. uint32_t tx_desc_id;
  3712. struct dp_tx_desc_s *tx_desc = NULL;
  3713. struct dp_tx_desc_s *head_desc = NULL;
  3714. struct dp_tx_desc_s *tail_desc = NULL;
  3715. uint32_t num_processed = 0;
  3716. uint32_t count;
  3717. uint32_t num_avail_for_reap = 0;
  3718. bool force_break = false;
  3719. DP_HIST_INIT();
  3720. more_data:
  3721. /* Re-initialize local variables to be re-used */
  3722. head_desc = NULL;
  3723. tail_desc = NULL;
  3724. count = 0;
  3725. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  3726. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  3727. return 0;
  3728. }
  3729. num_avail_for_reap = hal_srng_dst_num_valid(soc->hal_soc, hal_ring_hdl, 0);
  3730. if (num_avail_for_reap >= quota)
  3731. num_avail_for_reap = quota;
  3732. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  3733. /* Find head descriptor from completion ring */
  3734. while (qdf_likely(num_avail_for_reap)) {
  3735. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  3736. if (qdf_unlikely(!tx_comp_hal_desc))
  3737. break;
  3738. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  3739. /* If this buffer was not released by TQM or FW, then it is not
  3740. * Tx completion indication, assert */
  3741. if (qdf_unlikely(buffer_src !=
  3742. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  3743. (qdf_unlikely(buffer_src !=
  3744. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  3745. uint8_t wbm_internal_error;
  3746. dp_err_rl(
  3747. "Tx comp release_src != TQM | FW but from %d",
  3748. buffer_src);
  3749. hal_dump_comp_desc(tx_comp_hal_desc);
  3750. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  3751. /* When WBM sees NULL buffer_addr_info in any of
  3752. * ingress rings it sends an error indication,
  3753. * with wbm_internal_error=1, to a specific ring.
  3754. * The WBM2SW ring used to indicate these errors is
  3755. * fixed in HW, and that ring is being used as Tx
  3756. * completion ring. These errors are not related to
  3757. * Tx completions, and should just be ignored
  3758. */
  3759. wbm_internal_error = hal_get_wbm_internal_error(
  3760. soc->hal_soc,
  3761. tx_comp_hal_desc);
  3762. if (wbm_internal_error) {
  3763. dp_err_rl("Tx comp wbm_internal_error!!");
  3764. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  3765. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  3766. buffer_src)
  3767. dp_handle_wbm_internal_error(
  3768. soc,
  3769. tx_comp_hal_desc,
  3770. hal_tx_comp_get_buffer_type(
  3771. tx_comp_hal_desc));
  3772. } else {
  3773. dp_err_rl("Tx comp wbm_internal_error false");
  3774. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  3775. }
  3776. continue;
  3777. }
  3778. /* Get descriptor id */
  3779. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  3780. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3781. DP_TX_DESC_ID_POOL_OS;
  3782. /* Find Tx descriptor */
  3783. tx_desc = dp_tx_desc_find(soc, pool_id,
  3784. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3785. DP_TX_DESC_ID_PAGE_OS,
  3786. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3787. DP_TX_DESC_ID_OFFSET_OS);
  3788. /*
  3789. * If the release source is FW, process the HTT status
  3790. */
  3791. if (qdf_unlikely(buffer_src ==
  3792. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3793. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  3794. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  3795. htt_tx_status);
  3796. dp_tx_process_htt_completion(tx_desc,
  3797. htt_tx_status, ring_id);
  3798. } else {
  3799. tx_desc->peer_id =
  3800. hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  3801. tx_desc->tx_status =
  3802. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  3803. /*
  3804. * If the fast completion mode is enabled extended
  3805. * metadata from descriptor is not copied
  3806. */
  3807. if (qdf_likely(tx_desc->flags &
  3808. DP_TX_DESC_FLAG_SIMPLE))
  3809. goto add_to_pool;
  3810. /*
  3811. * If the descriptor is already freed in vdev_detach,
  3812. * continue to next descriptor
  3813. */
  3814. if (qdf_unlikely
  3815. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  3816. !tx_desc->flags)) {
  3817. QDF_TRACE(QDF_MODULE_ID_DP,
  3818. QDF_TRACE_LEVEL_INFO,
  3819. "Descriptor freed in vdev_detach %d",
  3820. tx_desc_id);
  3821. continue;
  3822. }
  3823. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3824. QDF_TRACE(QDF_MODULE_ID_DP,
  3825. QDF_TRACE_LEVEL_INFO,
  3826. "pdev in down state %d",
  3827. tx_desc_id);
  3828. dp_tx_comp_free_buf(soc, tx_desc);
  3829. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3830. goto next_desc;
  3831. }
  3832. /* Pool id is not matching. Error */
  3833. if (tx_desc->pool_id != pool_id) {
  3834. QDF_TRACE(QDF_MODULE_ID_DP,
  3835. QDF_TRACE_LEVEL_FATAL,
  3836. "Tx Comp pool id %d not matched %d",
  3837. pool_id, tx_desc->pool_id);
  3838. qdf_assert_always(0);
  3839. }
  3840. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  3841. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  3842. QDF_TRACE(QDF_MODULE_ID_DP,
  3843. QDF_TRACE_LEVEL_FATAL,
  3844. "Txdesc invalid, flgs = %x,id = %d",
  3845. tx_desc->flags, tx_desc_id);
  3846. qdf_assert_always(0);
  3847. }
  3848. /* Collect hw completion contents */
  3849. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  3850. &tx_desc->comp, 1);
  3851. add_to_pool:
  3852. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  3853. /* First ring descriptor on the cycle */
  3854. if (!head_desc) {
  3855. head_desc = tx_desc;
  3856. tail_desc = tx_desc;
  3857. }
  3858. tail_desc->next = tx_desc;
  3859. tx_desc->next = NULL;
  3860. tail_desc = tx_desc;
  3861. }
  3862. next_desc:
  3863. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3864. /*
  3865. * Processed packet count is more than given quota
  3866. * stop to processing
  3867. */
  3868. count++;
  3869. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  3870. break;
  3871. }
  3872. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  3873. /* Process the reaped descriptors */
  3874. if (head_desc)
  3875. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  3876. if (dp_tx_comp_enable_eol_data_check(soc)) {
  3877. if (num_processed >= quota)
  3878. force_break = true;
  3879. if (!force_break &&
  3880. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  3881. hal_ring_hdl)) {
  3882. DP_STATS_INC(soc, tx.hp_oos2, 1);
  3883. if (!hif_exec_should_yield(soc->hif_handle,
  3884. int_ctx->dp_intr_id))
  3885. goto more_data;
  3886. }
  3887. }
  3888. DP_TX_HIST_STATS_PER_PDEV();
  3889. return num_processed;
  3890. }
  3891. #ifdef FEATURE_WLAN_TDLS
  3892. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3893. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3894. {
  3895. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3896. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3897. DP_MOD_ID_TDLS);
  3898. if (!vdev) {
  3899. dp_err("vdev handle for id %d is NULL", vdev_id);
  3900. return NULL;
  3901. }
  3902. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3903. vdev->is_tdls_frame = true;
  3904. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  3905. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  3906. }
  3907. #endif
  3908. static void dp_tx_vdev_update_feature_flags(struct dp_vdev *vdev)
  3909. {
  3910. struct wlan_cfg_dp_soc_ctxt *cfg;
  3911. struct dp_soc *soc;
  3912. soc = vdev->pdev->soc;
  3913. if (!soc)
  3914. return;
  3915. cfg = soc->wlan_cfg_ctx;
  3916. if (!cfg)
  3917. return;
  3918. if (vdev->opmode == wlan_op_mode_ndi)
  3919. vdev->csum_enabled = wlan_cfg_get_nan_checksum_offload(cfg);
  3920. else if ((vdev->subtype == wlan_op_subtype_p2p_device) ||
  3921. (vdev->subtype == wlan_op_subtype_p2p_cli) ||
  3922. (vdev->subtype == wlan_op_subtype_p2p_go))
  3923. vdev->csum_enabled = wlan_cfg_get_p2p_checksum_offload(cfg);
  3924. else
  3925. vdev->csum_enabled = wlan_cfg_get_checksum_offload(cfg);
  3926. }
  3927. /**
  3928. * dp_tx_vdev_attach() - attach vdev to dp tx
  3929. * @vdev: virtual device instance
  3930. *
  3931. * Return: QDF_STATUS_SUCCESS: success
  3932. * QDF_STATUS_E_RESOURCES: Error return
  3933. */
  3934. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3935. {
  3936. int pdev_id;
  3937. /*
  3938. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3939. */
  3940. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3941. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3942. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3943. vdev->vdev_id);
  3944. pdev_id =
  3945. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  3946. vdev->pdev->pdev_id);
  3947. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  3948. /*
  3949. * Set HTT Extension Valid bit to 0 by default
  3950. */
  3951. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3952. dp_tx_vdev_update_search_flags(vdev);
  3953. dp_tx_vdev_update_feature_flags(vdev);
  3954. return QDF_STATUS_SUCCESS;
  3955. }
  3956. #ifndef FEATURE_WDS
  3957. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3958. {
  3959. return false;
  3960. }
  3961. #endif
  3962. /**
  3963. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3964. * @vdev: virtual device instance
  3965. *
  3966. * Return: void
  3967. *
  3968. */
  3969. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3970. {
  3971. struct dp_soc *soc = vdev->pdev->soc;
  3972. /*
  3973. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3974. * for TDLS link
  3975. *
  3976. * Enable AddrY (SA based search) only for non-WDS STA and
  3977. * ProxySTA VAP (in HKv1) modes.
  3978. *
  3979. * In all other VAP modes, only DA based search should be
  3980. * enabled
  3981. */
  3982. if (vdev->opmode == wlan_op_mode_sta &&
  3983. vdev->tdls_link_connected)
  3984. vdev->hal_desc_addr_search_flags =
  3985. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3986. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3987. !dp_tx_da_search_override(vdev))
  3988. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3989. else
  3990. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3991. /* Set search type only when peer map v2 messaging is enabled
  3992. * as we will have the search index (AST hash) only when v2 is
  3993. * enabled
  3994. */
  3995. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3996. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3997. else
  3998. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3999. }
  4000. static inline bool
  4001. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4002. struct dp_vdev *vdev,
  4003. struct dp_tx_desc_s *tx_desc)
  4004. {
  4005. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4006. return false;
  4007. /*
  4008. * if vdev is given, then only check whether desc
  4009. * vdev match. if vdev is NULL, then check whether
  4010. * desc pdev match.
  4011. */
  4012. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4013. (tx_desc->pdev == pdev);
  4014. }
  4015. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4016. /**
  4017. * dp_tx_desc_flush() - release resources associated
  4018. * to TX Desc
  4019. *
  4020. * @dp_pdev: Handle to DP pdev structure
  4021. * @vdev: virtual device instance
  4022. * NULL: no specific Vdev is required and check all allcated TX desc
  4023. * on this pdev.
  4024. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4025. *
  4026. * @force_free:
  4027. * true: flush the TX desc.
  4028. * false: only reset the Vdev in each allocated TX desc
  4029. * that associated to current Vdev.
  4030. *
  4031. * This function will go through the TX desc pool to flush
  4032. * the outstanding TX data or reset Vdev to NULL in associated TX
  4033. * Desc.
  4034. */
  4035. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4036. bool force_free)
  4037. {
  4038. uint8_t i;
  4039. uint32_t j;
  4040. uint32_t num_desc, page_id, offset;
  4041. uint16_t num_desc_per_page;
  4042. struct dp_soc *soc = pdev->soc;
  4043. struct dp_tx_desc_s *tx_desc = NULL;
  4044. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4045. if (!vdev && !force_free) {
  4046. dp_err("Reset TX desc vdev, Vdev param is required!");
  4047. return;
  4048. }
  4049. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4050. tx_desc_pool = &soc->tx_desc[i];
  4051. if (!(tx_desc_pool->pool_size) ||
  4052. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4053. !(tx_desc_pool->desc_pages.cacheable_pages))
  4054. continue;
  4055. /*
  4056. * Add flow pool lock protection in case pool is freed
  4057. * due to all tx_desc is recycled when handle TX completion.
  4058. * this is not necessary when do force flush as:
  4059. * a. double lock will happen if dp_tx_desc_release is
  4060. * also trying to acquire it.
  4061. * b. dp interrupt has been disabled before do force TX desc
  4062. * flush in dp_pdev_deinit().
  4063. */
  4064. if (!force_free)
  4065. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4066. num_desc = tx_desc_pool->pool_size;
  4067. num_desc_per_page =
  4068. tx_desc_pool->desc_pages.num_element_per_page;
  4069. for (j = 0; j < num_desc; j++) {
  4070. page_id = j / num_desc_per_page;
  4071. offset = j % num_desc_per_page;
  4072. if (qdf_unlikely(!(tx_desc_pool->
  4073. desc_pages.cacheable_pages)))
  4074. break;
  4075. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4076. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4077. /*
  4078. * Free TX desc if force free is
  4079. * required, otherwise only reset vdev
  4080. * in this TX desc.
  4081. */
  4082. if (force_free) {
  4083. dp_tx_comp_free_buf(soc, tx_desc);
  4084. dp_tx_desc_release(tx_desc, i);
  4085. } else {
  4086. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4087. }
  4088. }
  4089. }
  4090. if (!force_free)
  4091. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4092. }
  4093. }
  4094. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4095. /**
  4096. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4097. *
  4098. * @soc: Handle to DP soc structure
  4099. * @tx_desc: pointer of one TX desc
  4100. * @desc_pool_id: TX Desc pool id
  4101. */
  4102. static inline void
  4103. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4104. uint8_t desc_pool_id)
  4105. {
  4106. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4107. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4108. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4109. }
  4110. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4111. bool force_free)
  4112. {
  4113. uint8_t i, num_pool;
  4114. uint32_t j;
  4115. uint32_t num_desc, page_id, offset;
  4116. uint16_t num_desc_per_page;
  4117. struct dp_soc *soc = pdev->soc;
  4118. struct dp_tx_desc_s *tx_desc = NULL;
  4119. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4120. if (!vdev && !force_free) {
  4121. dp_err("Reset TX desc vdev, Vdev param is required!");
  4122. return;
  4123. }
  4124. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4125. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4126. for (i = 0; i < num_pool; i++) {
  4127. tx_desc_pool = &soc->tx_desc[i];
  4128. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4129. continue;
  4130. num_desc_per_page =
  4131. tx_desc_pool->desc_pages.num_element_per_page;
  4132. for (j = 0; j < num_desc; j++) {
  4133. page_id = j / num_desc_per_page;
  4134. offset = j % num_desc_per_page;
  4135. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4136. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4137. if (force_free) {
  4138. dp_tx_comp_free_buf(soc, tx_desc);
  4139. dp_tx_desc_release(tx_desc, i);
  4140. } else {
  4141. dp_tx_desc_reset_vdev(soc, tx_desc,
  4142. i);
  4143. }
  4144. }
  4145. }
  4146. }
  4147. }
  4148. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4149. /**
  4150. * dp_tx_vdev_detach() - detach vdev from dp tx
  4151. * @vdev: virtual device instance
  4152. *
  4153. * Return: QDF_STATUS_SUCCESS: success
  4154. * QDF_STATUS_E_RESOURCES: Error return
  4155. */
  4156. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4157. {
  4158. struct dp_pdev *pdev = vdev->pdev;
  4159. /* Reset TX desc associated to this Vdev as NULL */
  4160. dp_tx_desc_flush(pdev, vdev, false);
  4161. dp_tx_vdev_multipass_deinit(vdev);
  4162. return QDF_STATUS_SUCCESS;
  4163. }
  4164. /**
  4165. * dp_tx_pdev_attach() - attach pdev to dp tx
  4166. * @pdev: physical device instance
  4167. *
  4168. * Return: QDF_STATUS_SUCCESS: success
  4169. * QDF_STATUS_E_RESOURCES: Error return
  4170. */
  4171. QDF_STATUS dp_tx_pdev_init(struct dp_pdev *pdev)
  4172. {
  4173. struct dp_soc *soc = pdev->soc;
  4174. /* Initialize Flow control counters */
  4175. qdf_atomic_init(&pdev->num_tx_outstanding);
  4176. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  4177. /* Initialize descriptors in TCL Ring */
  4178. hal_tx_init_data_ring(soc->hal_soc,
  4179. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  4180. }
  4181. return QDF_STATUS_SUCCESS;
  4182. }
  4183. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4184. /* Pools will be allocated dynamically */
  4185. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4186. int num_desc)
  4187. {
  4188. uint8_t i;
  4189. for (i = 0; i < num_pool; i++) {
  4190. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4191. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4192. }
  4193. return QDF_STATUS_SUCCESS;
  4194. }
  4195. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4196. int num_desc)
  4197. {
  4198. return QDF_STATUS_SUCCESS;
  4199. }
  4200. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4201. {
  4202. }
  4203. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4204. {
  4205. uint8_t i;
  4206. for (i = 0; i < num_pool; i++)
  4207. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4208. }
  4209. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4210. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4211. int num_desc)
  4212. {
  4213. uint8_t i, count;
  4214. /* Allocate software Tx descriptor pools */
  4215. for (i = 0; i < num_pool; i++) {
  4216. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4217. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4218. FL("Tx Desc Pool alloc %d failed %pK"),
  4219. i, soc);
  4220. goto fail;
  4221. }
  4222. }
  4223. return QDF_STATUS_SUCCESS;
  4224. fail:
  4225. for (count = 0; count < i; count++)
  4226. dp_tx_desc_pool_free(soc, count);
  4227. return QDF_STATUS_E_NOMEM;
  4228. }
  4229. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4230. int num_desc)
  4231. {
  4232. uint8_t i;
  4233. for (i = 0; i < num_pool; i++) {
  4234. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4235. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4236. FL("Tx Desc Pool init %d failed %pK"),
  4237. i, soc);
  4238. return QDF_STATUS_E_NOMEM;
  4239. }
  4240. }
  4241. return QDF_STATUS_SUCCESS;
  4242. }
  4243. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4244. {
  4245. uint8_t i;
  4246. for (i = 0; i < num_pool; i++)
  4247. dp_tx_desc_pool_deinit(soc, i);
  4248. }
  4249. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4250. {
  4251. uint8_t i;
  4252. for (i = 0; i < num_pool; i++)
  4253. dp_tx_desc_pool_free(soc, i);
  4254. }
  4255. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4256. /**
  4257. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4258. * @soc: core txrx main context
  4259. * @num_pool: number of pools
  4260. *
  4261. */
  4262. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4263. {
  4264. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4265. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4266. }
  4267. /**
  4268. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4269. * @soc: core txrx main context
  4270. * @num_pool: number of pools
  4271. *
  4272. */
  4273. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4274. {
  4275. dp_tx_tso_desc_pool_free(soc, num_pool);
  4276. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4277. }
  4278. /**
  4279. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4280. * @soc: core txrx main context
  4281. *
  4282. * This function frees all tx related descriptors as below
  4283. * 1. Regular TX descriptors (static pools)
  4284. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4285. * 3. TSO descriptors
  4286. *
  4287. */
  4288. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4289. {
  4290. uint8_t num_pool;
  4291. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4292. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4293. dp_tx_ext_desc_pool_free(soc, num_pool);
  4294. dp_tx_delete_static_pools(soc, num_pool);
  4295. }
  4296. /**
  4297. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4298. * @soc: core txrx main context
  4299. *
  4300. * This function de-initializes all tx related descriptors as below
  4301. * 1. Regular TX descriptors (static pools)
  4302. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4303. * 3. TSO descriptors
  4304. *
  4305. */
  4306. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4307. {
  4308. uint8_t num_pool;
  4309. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4310. dp_tx_flow_control_deinit(soc);
  4311. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4312. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4313. dp_tx_deinit_static_pools(soc, num_pool);
  4314. }
  4315. /**
  4316. * dp_tso_attach() - TSO attach handler
  4317. * @txrx_soc: Opaque Dp handle
  4318. *
  4319. * Reserve TSO descriptor buffers
  4320. *
  4321. * Return: QDF_STATUS_E_FAILURE on failure or
  4322. * QDF_STATUS_SUCCESS on success
  4323. */
  4324. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4325. uint8_t num_pool,
  4326. uint16_t num_desc)
  4327. {
  4328. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4329. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4330. return QDF_STATUS_E_FAILURE;
  4331. }
  4332. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4333. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4334. num_pool, soc);
  4335. return QDF_STATUS_E_FAILURE;
  4336. }
  4337. return QDF_STATUS_SUCCESS;
  4338. }
  4339. /**
  4340. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4341. * @soc: DP soc handle
  4342. * @num_pool: Number of pools
  4343. * @num_desc: Number of descriptors
  4344. *
  4345. * Initialize TSO descriptor pools
  4346. *
  4347. * Return: QDF_STATUS_E_FAILURE on failure or
  4348. * QDF_STATUS_SUCCESS on success
  4349. */
  4350. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4351. uint8_t num_pool,
  4352. uint16_t num_desc)
  4353. {
  4354. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4355. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4356. return QDF_STATUS_E_FAILURE;
  4357. }
  4358. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4359. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4360. num_pool, soc);
  4361. return QDF_STATUS_E_FAILURE;
  4362. }
  4363. return QDF_STATUS_SUCCESS;
  4364. }
  4365. /**
  4366. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4367. * @soc: core txrx main context
  4368. *
  4369. * This function allocates memory for following descriptor pools
  4370. * 1. regular sw tx descriptor pools (static pools)
  4371. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4372. * 3. TSO descriptor pools
  4373. *
  4374. * Return: QDF_STATUS_SUCCESS: success
  4375. * QDF_STATUS_E_RESOURCES: Error return
  4376. */
  4377. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4378. {
  4379. uint8_t num_pool;
  4380. uint32_t num_desc;
  4381. uint32_t num_ext_desc;
  4382. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4383. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4384. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4385. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4386. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4387. __func__, num_pool, num_desc);
  4388. if ((num_pool > MAX_TXDESC_POOLS) ||
  4389. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4390. goto fail1;
  4391. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4392. goto fail1;
  4393. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4394. goto fail2;
  4395. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4396. return QDF_STATUS_SUCCESS;
  4397. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4398. goto fail3;
  4399. return QDF_STATUS_SUCCESS;
  4400. fail3:
  4401. dp_tx_ext_desc_pool_free(soc, num_pool);
  4402. fail2:
  4403. dp_tx_delete_static_pools(soc, num_pool);
  4404. fail1:
  4405. return QDF_STATUS_E_RESOURCES;
  4406. }
  4407. /**
  4408. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4409. * @soc: core txrx main context
  4410. *
  4411. * This function initializes the following TX descriptor pools
  4412. * 1. regular sw tx descriptor pools (static pools)
  4413. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4414. * 3. TSO descriptor pools
  4415. *
  4416. * Return: QDF_STATUS_SUCCESS: success
  4417. * QDF_STATUS_E_RESOURCES: Error return
  4418. */
  4419. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4420. {
  4421. uint8_t num_pool;
  4422. uint32_t num_desc;
  4423. uint32_t num_ext_desc;
  4424. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4425. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4426. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4427. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4428. goto fail1;
  4429. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4430. goto fail2;
  4431. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4432. return QDF_STATUS_SUCCESS;
  4433. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4434. goto fail3;
  4435. dp_tx_flow_control_init(soc);
  4436. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4437. return QDF_STATUS_SUCCESS;
  4438. fail3:
  4439. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4440. fail2:
  4441. dp_tx_deinit_static_pools(soc, num_pool);
  4442. fail1:
  4443. return QDF_STATUS_E_RESOURCES;
  4444. }
  4445. /**
  4446. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4447. * @txrx_soc: dp soc handle
  4448. *
  4449. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4450. * QDF_STATUS_E_FAILURE
  4451. */
  4452. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4453. {
  4454. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4455. uint8_t num_pool;
  4456. uint32_t num_desc;
  4457. uint32_t num_ext_desc;
  4458. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4459. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4460. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4461. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4462. return QDF_STATUS_E_FAILURE;
  4463. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4464. return QDF_STATUS_E_FAILURE;
  4465. return QDF_STATUS_SUCCESS;
  4466. }
  4467. /**
  4468. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4469. * @txrx_soc: dp soc handle
  4470. *
  4471. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4472. */
  4473. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4474. {
  4475. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4476. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4477. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4478. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4479. return QDF_STATUS_SUCCESS;
  4480. }