sde_encoder.c 139 KB

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  1. /*
  2. * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/kthread.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/input.h>
  22. #include <linux/seq_file.h>
  23. #include <linux/sde_rsc.h>
  24. #include "msm_drv.h"
  25. #include "sde_kms.h"
  26. #include <drm/drm_crtc.h>
  27. #include <drm/drm_probe_helper.h>
  28. #include "sde_hwio.h"
  29. #include "sde_hw_catalog.h"
  30. #include "sde_hw_intf.h"
  31. #include "sde_hw_ctl.h"
  32. #include "sde_formats.h"
  33. #include "sde_encoder.h"
  34. #include "sde_encoder_phys.h"
  35. #include "sde_hw_dsc.h"
  36. #include "sde_crtc.h"
  37. #include "sde_trace.h"
  38. #include "sde_core_irq.h"
  39. #include "sde_hw_top.h"
  40. #include "sde_hw_qdss.h"
  41. #include "sde_encoder_dce.h"
  42. #define SDE_DEBUG_ENC(e, fmt, ...) SDE_DEBUG("enc%d " fmt,\
  43. (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  44. #define SDE_ERROR_ENC(e, fmt, ...) SDE_ERROR("enc%d " fmt,\
  45. (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  46. #define SDE_DEBUG_PHYS(p, fmt, ...) SDE_DEBUG("enc%d intf%d pp%d " fmt,\
  47. (p) ? (p)->parent->base.id : -1, \
  48. (p) ? (p)->intf_idx - INTF_0 : -1, \
  49. (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  50. ##__VA_ARGS__)
  51. #define SDE_ERROR_PHYS(p, fmt, ...) SDE_ERROR("enc%d intf%d pp%d " fmt,\
  52. (p) ? (p)->parent->base.id : -1, \
  53. (p) ? (p)->intf_idx - INTF_0 : -1, \
  54. (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  55. ##__VA_ARGS__)
  56. #define MISR_BUFF_SIZE 256
  57. #define IDLE_SHORT_TIMEOUT 1
  58. #define EVT_TIME_OUT_SPLIT 2
  59. /* Maximum number of VSYNC wait attempts for RSC state transition */
  60. #define MAX_RSC_WAIT 5
  61. #define TOPOLOGY_DUALPIPE_MERGE_MODE(x) \
  62. (((x) == SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE) || \
  63. ((x) == SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE) || \
  64. ((x) == SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_VDC) || \
  65. ((x) == SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC))
  66. /**
  67. * enum sde_enc_rc_events - events for resource control state machine
  68. * @SDE_ENC_RC_EVENT_KICKOFF:
  69. * This event happens at NORMAL priority.
  70. * Event that signals the start of the transfer. When this event is
  71. * received, enable MDP/DSI core clocks and request RSC with CMD state.
  72. * Regardless of the previous state, the resource should be in ON state
  73. * at the end of this event. At the end of this event, a delayed work is
  74. * scheduled to go to IDLE_PC state after IDLE_POWERCOLLAPSE_DURATION
  75. * ktime.
  76. * @SDE_ENC_RC_EVENT_PRE_STOP:
  77. * This event happens at NORMAL priority.
  78. * This event, when received during the ON state, set RSC to IDLE, and
  79. * and leave the RC STATE in the PRE_OFF state.
  80. * It should be followed by the STOP event as part of encoder disable.
  81. * If received during IDLE or OFF states, it will do nothing.
  82. * @SDE_ENC_RC_EVENT_STOP:
  83. * This event happens at NORMAL priority.
  84. * When this event is received, disable all the MDP/DSI core clocks, and
  85. * disable IRQs. It should be called from the PRE_OFF or IDLE states.
  86. * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
  87. * PRE_OFF is expected when PRE_STOP was executed during the ON state.
  88. * Resource state should be in OFF at the end of the event.
  89. * @SDE_ENC_RC_EVENT_PRE_MODESET:
  90. * This event happens at NORMAL priority from a work item.
  91. * Event signals that there is a seamless mode switch is in prgoress. A
  92. * client needs to turn of only irq - leave clocks ON to reduce the mode
  93. * switch latency.
  94. * @SDE_ENC_RC_EVENT_POST_MODESET:
  95. * This event happens at NORMAL priority from a work item.
  96. * Event signals that seamless mode switch is complete and resources are
  97. * acquired. Clients wants to turn on the irq again and update the rsc
  98. * with new vtotal.
  99. * @SDE_ENC_RC_EVENT_ENTER_IDLE:
  100. * This event happens at NORMAL priority from a work item.
  101. * Event signals that there were no frame updates for
  102. * IDLE_POWERCOLLAPSE_DURATION time. This would disable MDP/DSI core clocks
  103. * and request RSC with IDLE state and change the resource state to IDLE.
  104. * @SDE_ENC_RC_EVENT_EARLY_WAKEUP:
  105. * This event is triggered from the input event thread when touch event is
  106. * received from the input device. On receiving this event,
  107. * - If the device is in SDE_ENC_RC_STATE_IDLE state, it turns ON the
  108. clocks and enable RSC.
  109. * - If the device is in SDE_ENC_RC_STATE_ON state, it resets the delayed
  110. * off work since a new commit is imminent.
  111. */
  112. enum sde_enc_rc_events {
  113. SDE_ENC_RC_EVENT_KICKOFF = 1,
  114. SDE_ENC_RC_EVENT_PRE_STOP,
  115. SDE_ENC_RC_EVENT_STOP,
  116. SDE_ENC_RC_EVENT_PRE_MODESET,
  117. SDE_ENC_RC_EVENT_POST_MODESET,
  118. SDE_ENC_RC_EVENT_ENTER_IDLE,
  119. SDE_ENC_RC_EVENT_EARLY_WAKEUP,
  120. };
  121. void sde_encoder_uidle_enable(struct drm_encoder *drm_enc, bool enable)
  122. {
  123. struct sde_encoder_virt *sde_enc;
  124. int i;
  125. sde_enc = to_sde_encoder_virt(drm_enc);
  126. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  127. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  128. if (phys && phys->hw_ctl && phys->hw_ctl->ops.uidle_enable) {
  129. SDE_EVT32(DRMID(drm_enc), enable);
  130. phys->hw_ctl->ops.uidle_enable(phys->hw_ctl, enable);
  131. }
  132. }
  133. }
  134. static void _sde_encoder_pm_qos_add_request(struct drm_encoder *drm_enc)
  135. {
  136. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  137. struct msm_drm_private *priv;
  138. struct sde_kms *sde_kms;
  139. struct device *cpu_dev;
  140. struct cpumask *cpu_mask = NULL;
  141. int cpu = 0;
  142. u32 cpu_dma_latency;
  143. priv = drm_enc->dev->dev_private;
  144. sde_kms = to_sde_kms(priv->kms);
  145. if (!sde_kms->catalog || !sde_kms->catalog->perf.cpu_mask)
  146. return;
  147. cpu_dma_latency = sde_kms->catalog->perf.cpu_dma_latency;
  148. cpumask_clear(&sde_enc->valid_cpu_mask);
  149. if (sde_enc->mode_info.frame_rate > FPS60)
  150. cpu_mask = to_cpumask(&sde_kms->catalog->perf.cpu_mask_perf);
  151. if (!cpu_mask &&
  152. sde_encoder_check_curr_mode(drm_enc,
  153. MSM_DISPLAY_CMD_MODE))
  154. cpu_mask = to_cpumask(&sde_kms->catalog->perf.cpu_mask);
  155. if (!cpu_mask)
  156. return;
  157. for_each_cpu(cpu, cpu_mask) {
  158. cpu_dev = get_cpu_device(cpu);
  159. if (!cpu_dev) {
  160. SDE_ERROR("%s: failed to get cpu%d device\n", __func__,
  161. cpu);
  162. return;
  163. }
  164. cpumask_set_cpu(cpu, &sde_enc->valid_cpu_mask);
  165. dev_pm_qos_add_request(cpu_dev,
  166. &sde_enc->pm_qos_cpu_req[cpu],
  167. DEV_PM_QOS_RESUME_LATENCY, cpu_dma_latency);
  168. SDE_EVT32_VERBOSE(DRMID(drm_enc), cpu_dma_latency, cpu);
  169. }
  170. }
  171. static void _sde_encoder_pm_qos_remove_request(struct drm_encoder *drm_enc)
  172. {
  173. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  174. struct device *cpu_dev;
  175. int cpu = 0;
  176. for_each_cpu(cpu, &sde_enc->valid_cpu_mask) {
  177. cpu_dev = get_cpu_device(cpu);
  178. if (!cpu_dev) {
  179. SDE_ERROR("%s: failed to get cpu%d device\n", __func__,
  180. cpu);
  181. continue;
  182. }
  183. dev_pm_qos_remove_request(&sde_enc->pm_qos_cpu_req[cpu]);
  184. SDE_EVT32_VERBOSE(DRMID(drm_enc), cpu);
  185. }
  186. cpumask_clear(&sde_enc->valid_cpu_mask);
  187. }
  188. static bool _sde_encoder_is_autorefresh_enabled(
  189. struct sde_encoder_virt *sde_enc)
  190. {
  191. struct drm_connector *drm_conn;
  192. if (!sde_enc->cur_master ||
  193. !(sde_enc->disp_info.capabilities & MSM_DISPLAY_CAP_CMD_MODE))
  194. return false;
  195. drm_conn = sde_enc->cur_master->connector;
  196. if (!drm_conn || !drm_conn->state)
  197. return false;
  198. return sde_connector_get_property(drm_conn->state,
  199. CONNECTOR_PROP_AUTOREFRESH) ? true : false;
  200. }
  201. static void sde_configure_qdss(struct sde_encoder_virt *sde_enc,
  202. struct sde_hw_qdss *hw_qdss,
  203. struct sde_encoder_phys *phys, bool enable)
  204. {
  205. if (sde_enc->qdss_status == enable)
  206. return;
  207. sde_enc->qdss_status = enable;
  208. phys->hw_mdptop->ops.set_mdp_hw_events(phys->hw_mdptop,
  209. sde_enc->qdss_status);
  210. hw_qdss->ops.enable_qdss_events(hw_qdss, sde_enc->qdss_status);
  211. }
  212. static int _sde_encoder_wait_timeout(int32_t drm_id, int32_t hw_id,
  213. s64 timeout_ms, struct sde_encoder_wait_info *info)
  214. {
  215. int rc = 0;
  216. s64 wait_time_jiffies = msecs_to_jiffies(timeout_ms);
  217. ktime_t cur_ktime;
  218. ktime_t exp_ktime = ktime_add_ms(ktime_get(), timeout_ms);
  219. do {
  220. rc = wait_event_timeout(*(info->wq),
  221. atomic_read(info->atomic_cnt) == info->count_check,
  222. wait_time_jiffies);
  223. cur_ktime = ktime_get();
  224. SDE_EVT32(drm_id, hw_id, rc, ktime_to_ms(cur_ktime),
  225. timeout_ms, atomic_read(info->atomic_cnt),
  226. info->count_check);
  227. /* If we timed out, counter is valid and time is less, wait again */
  228. } while ((atomic_read(info->atomic_cnt) != info->count_check) &&
  229. (rc == 0) &&
  230. (ktime_compare_safe(exp_ktime, cur_ktime) > 0));
  231. return rc;
  232. }
  233. bool sde_encoder_is_primary_display(struct drm_encoder *drm_enc)
  234. {
  235. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  236. return sde_enc &&
  237. (sde_enc->disp_info.display_type ==
  238. SDE_CONNECTOR_PRIMARY);
  239. }
  240. bool sde_encoder_is_dsi_display(struct drm_encoder *drm_enc)
  241. {
  242. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  243. return sde_enc &&
  244. (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DSI);
  245. }
  246. int sde_encoder_in_cont_splash(struct drm_encoder *drm_enc)
  247. {
  248. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  249. return sde_enc && sde_enc->cur_master &&
  250. sde_enc->cur_master->cont_splash_enabled;
  251. }
  252. void sde_encoder_helper_report_irq_timeout(struct sde_encoder_phys *phys_enc,
  253. enum sde_intr_idx intr_idx)
  254. {
  255. SDE_EVT32(DRMID(phys_enc->parent),
  256. phys_enc->intf_idx - INTF_0,
  257. phys_enc->hw_pp->idx - PINGPONG_0,
  258. intr_idx);
  259. SDE_ERROR_PHYS(phys_enc, "irq %d timeout\n", intr_idx);
  260. if (phys_enc->parent_ops.handle_frame_done)
  261. phys_enc->parent_ops.handle_frame_done(
  262. phys_enc->parent, phys_enc,
  263. SDE_ENCODER_FRAME_EVENT_ERROR);
  264. }
  265. int sde_encoder_helper_wait_for_irq(struct sde_encoder_phys *phys_enc,
  266. enum sde_intr_idx intr_idx,
  267. struct sde_encoder_wait_info *wait_info)
  268. {
  269. struct sde_encoder_irq *irq;
  270. u32 irq_status;
  271. int ret, i;
  272. if (!phys_enc || !wait_info || intr_idx >= INTR_IDX_MAX) {
  273. SDE_ERROR("invalid params\n");
  274. return -EINVAL;
  275. }
  276. irq = &phys_enc->irq[intr_idx];
  277. /* note: do master / slave checking outside */
  278. /* return EWOULDBLOCK since we know the wait isn't necessary */
  279. if (phys_enc->enable_state == SDE_ENC_DISABLED) {
  280. SDE_ERROR_PHYS(phys_enc, "encoder is disabled\n");
  281. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  282. irq->irq_idx, intr_idx, SDE_EVTLOG_ERROR);
  283. return -EWOULDBLOCK;
  284. }
  285. if (irq->irq_idx < 0) {
  286. SDE_DEBUG_PHYS(phys_enc, "irq %s hw %d disabled, skip wait\n",
  287. irq->name, irq->hw_idx);
  288. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  289. irq->irq_idx);
  290. return 0;
  291. }
  292. SDE_DEBUG_PHYS(phys_enc, "pending_cnt %d\n",
  293. atomic_read(wait_info->atomic_cnt));
  294. SDE_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  295. irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
  296. atomic_read(wait_info->atomic_cnt), SDE_EVTLOG_FUNC_ENTRY);
  297. /*
  298. * Some module X may disable interrupt for longer duration
  299. * and it may trigger all interrupts including timer interrupt
  300. * when module X again enable the interrupt.
  301. * That may cause interrupt wait timeout API in this API.
  302. * It is handled by split the wait timer in two halves.
  303. */
  304. for (i = 0; i < EVT_TIME_OUT_SPLIT; i++) {
  305. ret = _sde_encoder_wait_timeout(DRMID(phys_enc->parent),
  306. irq->hw_idx,
  307. (wait_info->timeout_ms/EVT_TIME_OUT_SPLIT),
  308. wait_info);
  309. if (ret)
  310. break;
  311. }
  312. if (ret <= 0) {
  313. irq_status = sde_core_irq_read(phys_enc->sde_kms,
  314. irq->irq_idx, true);
  315. if (irq_status) {
  316. unsigned long flags;
  317. SDE_EVT32(DRMID(phys_enc->parent), intr_idx,
  318. irq->hw_idx, irq->irq_idx,
  319. phys_enc->hw_pp->idx - PINGPONG_0,
  320. atomic_read(wait_info->atomic_cnt));
  321. SDE_DEBUG_PHYS(phys_enc,
  322. "done but irq %d not triggered\n",
  323. irq->irq_idx);
  324. local_irq_save(flags);
  325. irq->cb.func(phys_enc, irq->irq_idx);
  326. local_irq_restore(flags);
  327. ret = 0;
  328. } else {
  329. ret = -ETIMEDOUT;
  330. SDE_EVT32(DRMID(phys_enc->parent), intr_idx,
  331. irq->hw_idx, irq->irq_idx,
  332. phys_enc->hw_pp->idx - PINGPONG_0,
  333. atomic_read(wait_info->atomic_cnt), irq_status,
  334. SDE_EVTLOG_ERROR);
  335. }
  336. } else {
  337. ret = 0;
  338. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  339. irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
  340. atomic_read(wait_info->atomic_cnt));
  341. }
  342. SDE_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  343. irq->irq_idx, ret, phys_enc->hw_pp->idx - PINGPONG_0,
  344. atomic_read(wait_info->atomic_cnt), SDE_EVTLOG_FUNC_EXIT);
  345. return ret;
  346. }
  347. int sde_encoder_helper_register_irq(struct sde_encoder_phys *phys_enc,
  348. enum sde_intr_idx intr_idx)
  349. {
  350. struct sde_encoder_irq *irq;
  351. int ret = 0;
  352. if (!phys_enc || intr_idx >= INTR_IDX_MAX) {
  353. SDE_ERROR("invalid params\n");
  354. return -EINVAL;
  355. }
  356. irq = &phys_enc->irq[intr_idx];
  357. if (irq->irq_idx >= 0) {
  358. SDE_DEBUG_PHYS(phys_enc,
  359. "skipping already registered irq %s type %d\n",
  360. irq->name, irq->intr_type);
  361. return 0;
  362. }
  363. irq->irq_idx = sde_core_irq_idx_lookup(phys_enc->sde_kms,
  364. irq->intr_type, irq->hw_idx);
  365. if (irq->irq_idx < 0) {
  366. SDE_ERROR_PHYS(phys_enc,
  367. "failed to lookup IRQ index for %s type:%d\n",
  368. irq->name, irq->intr_type);
  369. return -EINVAL;
  370. }
  371. ret = sde_core_irq_register_callback(phys_enc->sde_kms, irq->irq_idx,
  372. &irq->cb);
  373. if (ret) {
  374. SDE_ERROR_PHYS(phys_enc,
  375. "failed to register IRQ callback for %s\n",
  376. irq->name);
  377. irq->irq_idx = -EINVAL;
  378. return ret;
  379. }
  380. ret = sde_core_irq_enable(phys_enc->sde_kms, &irq->irq_idx, 1);
  381. if (ret) {
  382. SDE_ERROR_PHYS(phys_enc,
  383. "enable IRQ for intr:%s failed, irq_idx %d\n",
  384. irq->name, irq->irq_idx);
  385. sde_core_irq_unregister_callback(phys_enc->sde_kms,
  386. irq->irq_idx, &irq->cb);
  387. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  388. irq->irq_idx, SDE_EVTLOG_ERROR);
  389. irq->irq_idx = -EINVAL;
  390. return ret;
  391. }
  392. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx, irq->irq_idx);
  393. SDE_DEBUG_PHYS(phys_enc, "registered irq %s idx: %d\n",
  394. irq->name, irq->irq_idx);
  395. return ret;
  396. }
  397. int sde_encoder_helper_unregister_irq(struct sde_encoder_phys *phys_enc,
  398. enum sde_intr_idx intr_idx)
  399. {
  400. struct sde_encoder_irq *irq;
  401. int ret;
  402. if (!phys_enc) {
  403. SDE_ERROR("invalid encoder\n");
  404. return -EINVAL;
  405. }
  406. irq = &phys_enc->irq[intr_idx];
  407. /* silently skip irqs that weren't registered */
  408. if (irq->irq_idx < 0) {
  409. SDE_ERROR(
  410. "extra unregister irq, enc%d intr_idx:0x%x hw_idx:0x%x irq_idx:0x%x\n",
  411. DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  412. irq->irq_idx);
  413. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  414. irq->irq_idx, SDE_EVTLOG_ERROR);
  415. return 0;
  416. }
  417. ret = sde_core_irq_disable(phys_enc->sde_kms, &irq->irq_idx, 1);
  418. if (ret)
  419. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  420. irq->irq_idx, ret, SDE_EVTLOG_ERROR);
  421. ret = sde_core_irq_unregister_callback(phys_enc->sde_kms, irq->irq_idx,
  422. &irq->cb);
  423. if (ret)
  424. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  425. irq->irq_idx, ret, SDE_EVTLOG_ERROR);
  426. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx, irq->irq_idx);
  427. SDE_DEBUG_PHYS(phys_enc, "unregistered %d\n", irq->irq_idx);
  428. irq->irq_idx = -EINVAL;
  429. return 0;
  430. }
  431. void sde_encoder_get_hw_resources(struct drm_encoder *drm_enc,
  432. struct sde_encoder_hw_resources *hw_res,
  433. struct drm_connector_state *conn_state)
  434. {
  435. struct sde_encoder_virt *sde_enc = NULL;
  436. int ret, i = 0;
  437. if (!hw_res || !drm_enc || !conn_state || !hw_res->comp_info) {
  438. SDE_ERROR("rc %d, drm_enc %d, res %d, state %d, comp-info %d\n",
  439. -EINVAL, !drm_enc, !hw_res, !conn_state,
  440. hw_res ? !hw_res->comp_info : 0);
  441. return;
  442. }
  443. sde_enc = to_sde_encoder_virt(drm_enc);
  444. SDE_DEBUG_ENC(sde_enc, "\n");
  445. hw_res->display_num_of_h_tiles = sde_enc->display_num_of_h_tiles;
  446. hw_res->display_type = sde_enc->disp_info.display_type;
  447. /* Query resources used by phys encs, expected to be without overlap */
  448. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  449. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  450. if (phys && phys->ops.get_hw_resources)
  451. phys->ops.get_hw_resources(phys, hw_res, conn_state);
  452. }
  453. /*
  454. * NOTE: Do not use sde_encoder_get_mode_info here as this function is
  455. * called from atomic_check phase. Use the below API to get mode
  456. * information of the temporary conn_state passed
  457. */
  458. ret = sde_connector_state_get_topology(conn_state, &hw_res->topology);
  459. if (ret)
  460. SDE_ERROR("failed to get topology ret %d\n", ret);
  461. ret = sde_connector_state_get_compression_info(conn_state,
  462. hw_res->comp_info);
  463. if (ret)
  464. SDE_ERROR("failed to get compression info ret %d\n", ret);
  465. }
  466. void sde_encoder_destroy(struct drm_encoder *drm_enc)
  467. {
  468. struct sde_encoder_virt *sde_enc = NULL;
  469. int i = 0;
  470. if (!drm_enc) {
  471. SDE_ERROR("invalid encoder\n");
  472. return;
  473. }
  474. sde_enc = to_sde_encoder_virt(drm_enc);
  475. SDE_DEBUG_ENC(sde_enc, "\n");
  476. mutex_lock(&sde_enc->enc_lock);
  477. sde_rsc_client_destroy(sde_enc->rsc_client);
  478. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  479. struct sde_encoder_phys *phys;
  480. phys = sde_enc->phys_vid_encs[i];
  481. if (phys && phys->ops.destroy) {
  482. phys->ops.destroy(phys);
  483. --sde_enc->num_phys_encs;
  484. sde_enc->phys_encs[i] = NULL;
  485. }
  486. phys = sde_enc->phys_cmd_encs[i];
  487. if (phys && phys->ops.destroy) {
  488. phys->ops.destroy(phys);
  489. --sde_enc->num_phys_encs;
  490. sde_enc->phys_encs[i] = NULL;
  491. }
  492. }
  493. if (sde_enc->num_phys_encs)
  494. SDE_ERROR_ENC(sde_enc, "expected 0 num_phys_encs not %d\n",
  495. sde_enc->num_phys_encs);
  496. sde_enc->num_phys_encs = 0;
  497. mutex_unlock(&sde_enc->enc_lock);
  498. drm_encoder_cleanup(drm_enc);
  499. mutex_destroy(&sde_enc->enc_lock);
  500. kfree(sde_enc->input_handler);
  501. sde_enc->input_handler = NULL;
  502. kfree(sde_enc);
  503. }
  504. void sde_encoder_helper_update_intf_cfg(
  505. struct sde_encoder_phys *phys_enc)
  506. {
  507. struct sde_encoder_virt *sde_enc;
  508. struct sde_hw_intf_cfg_v1 *intf_cfg;
  509. enum sde_3d_blend_mode mode_3d;
  510. if (!phys_enc || !phys_enc->hw_pp) {
  511. SDE_ERROR("invalid args, encoder %d\n", !phys_enc);
  512. return;
  513. }
  514. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  515. intf_cfg = &sde_enc->cur_master->intf_cfg_v1;
  516. SDE_DEBUG_ENC(sde_enc,
  517. "intf_cfg updated for %d at idx %d\n",
  518. phys_enc->intf_idx,
  519. intf_cfg->intf_count);
  520. /* setup interface configuration */
  521. if (intf_cfg->intf_count >= MAX_INTF_PER_CTL_V1) {
  522. pr_err("invalid inf_count %d\n", intf_cfg->intf_count);
  523. return;
  524. }
  525. intf_cfg->intf[intf_cfg->intf_count++] = phys_enc->intf_idx;
  526. if (phys_enc == sde_enc->cur_master) {
  527. if (sde_enc->cur_master->intf_mode == INTF_MODE_CMD)
  528. intf_cfg->intf_mode_sel = SDE_CTL_MODE_SEL_CMD;
  529. else
  530. intf_cfg->intf_mode_sel = SDE_CTL_MODE_SEL_VID;
  531. }
  532. /* configure this interface as master for split display */
  533. if (phys_enc->split_role == ENC_ROLE_MASTER)
  534. intf_cfg->intf_master = phys_enc->hw_intf->idx;
  535. /* setup which pp blk will connect to this intf */
  536. if (phys_enc->hw_intf->ops.bind_pingpong_blk)
  537. phys_enc->hw_intf->ops.bind_pingpong_blk(
  538. phys_enc->hw_intf,
  539. true,
  540. phys_enc->hw_pp->idx);
  541. /*setup merge_3d configuration */
  542. mode_3d = sde_encoder_helper_get_3d_blend_mode(phys_enc);
  543. if (mode_3d && phys_enc->hw_pp->merge_3d &&
  544. intf_cfg->merge_3d_count < MAX_MERGE_3D_PER_CTL_V1)
  545. intf_cfg->merge_3d[intf_cfg->merge_3d_count++] =
  546. phys_enc->hw_pp->merge_3d->idx;
  547. if (phys_enc->hw_pp->ops.setup_3d_mode)
  548. phys_enc->hw_pp->ops.setup_3d_mode(phys_enc->hw_pp,
  549. mode_3d);
  550. }
  551. void sde_encoder_helper_split_config(
  552. struct sde_encoder_phys *phys_enc,
  553. enum sde_intf interface)
  554. {
  555. struct sde_encoder_virt *sde_enc;
  556. struct split_pipe_cfg *cfg;
  557. struct sde_hw_mdp *hw_mdptop;
  558. enum sde_rm_topology_name topology;
  559. struct msm_display_info *disp_info;
  560. if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
  561. SDE_ERROR("invalid arg(s), encoder %d\n", !phys_enc);
  562. return;
  563. }
  564. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  565. hw_mdptop = phys_enc->hw_mdptop;
  566. disp_info = &sde_enc->disp_info;
  567. cfg = &phys_enc->hw_intf->cfg;
  568. memset(cfg, 0, sizeof(*cfg));
  569. if (disp_info->intf_type != DRM_MODE_CONNECTOR_DSI)
  570. return;
  571. if (disp_info->capabilities & MSM_DISPLAY_SPLIT_LINK)
  572. cfg->split_link_en = true;
  573. /**
  574. * disable split modes since encoder will be operating in as the only
  575. * encoder, either for the entire use case in the case of, for example,
  576. * single DSI, or for this frame in the case of left/right only partial
  577. * update.
  578. */
  579. if (phys_enc->split_role == ENC_ROLE_SOLO) {
  580. if (hw_mdptop->ops.setup_split_pipe)
  581. hw_mdptop->ops.setup_split_pipe(hw_mdptop, cfg);
  582. if (hw_mdptop->ops.setup_pp_split)
  583. hw_mdptop->ops.setup_pp_split(hw_mdptop, cfg);
  584. return;
  585. }
  586. cfg->en = true;
  587. cfg->mode = phys_enc->intf_mode;
  588. cfg->intf = interface;
  589. if (cfg->en && phys_enc->ops.needs_single_flush &&
  590. phys_enc->ops.needs_single_flush(phys_enc))
  591. cfg->split_flush_en = true;
  592. topology = sde_connector_get_topology_name(phys_enc->connector);
  593. if (topology == SDE_RM_TOPOLOGY_PPSPLIT)
  594. cfg->pp_split_slave = cfg->intf;
  595. else
  596. cfg->pp_split_slave = INTF_MAX;
  597. if (phys_enc->split_role == ENC_ROLE_MASTER) {
  598. SDE_DEBUG_ENC(sde_enc, "enable %d\n", cfg->en);
  599. if (hw_mdptop->ops.setup_split_pipe)
  600. hw_mdptop->ops.setup_split_pipe(hw_mdptop, cfg);
  601. } else if (sde_enc->hw_pp[0]) {
  602. /*
  603. * slave encoder
  604. * - determine split index from master index,
  605. * assume master is first pp
  606. */
  607. cfg->pp_split_index = sde_enc->hw_pp[0]->idx - PINGPONG_0;
  608. SDE_DEBUG_ENC(sde_enc, "master using pp%d\n",
  609. cfg->pp_split_index);
  610. if (hw_mdptop->ops.setup_pp_split)
  611. hw_mdptop->ops.setup_pp_split(hw_mdptop, cfg);
  612. }
  613. }
  614. bool sde_encoder_in_clone_mode(struct drm_encoder *drm_enc)
  615. {
  616. struct sde_encoder_virt *sde_enc;
  617. int i = 0;
  618. if (!drm_enc)
  619. return false;
  620. sde_enc = to_sde_encoder_virt(drm_enc);
  621. if (!sde_enc)
  622. return false;
  623. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  624. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  625. if (phys && phys->in_clone_mode)
  626. return true;
  627. }
  628. return false;
  629. }
  630. static int _sde_encoder_atomic_check_phys_enc(struct sde_encoder_virt *sde_enc,
  631. struct drm_crtc_state *crtc_state,
  632. struct drm_connector_state *conn_state)
  633. {
  634. const struct drm_display_mode *mode;
  635. struct drm_display_mode *adj_mode;
  636. int i = 0;
  637. int ret = 0;
  638. mode = &crtc_state->mode;
  639. adj_mode = &crtc_state->adjusted_mode;
  640. /* perform atomic check on the first physical encoder (master) */
  641. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  642. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  643. if (phys && phys->ops.atomic_check)
  644. ret = phys->ops.atomic_check(phys, crtc_state,
  645. conn_state);
  646. else if (phys && phys->ops.mode_fixup)
  647. if (!phys->ops.mode_fixup(phys, mode, adj_mode))
  648. ret = -EINVAL;
  649. if (ret) {
  650. SDE_ERROR_ENC(sde_enc,
  651. "mode unsupported, phys idx %d\n", i);
  652. break;
  653. }
  654. }
  655. return ret;
  656. }
  657. static int _sde_encoder_atomic_check_pu_roi(struct sde_encoder_virt *sde_enc,
  658. struct drm_crtc_state *crtc_state,
  659. struct drm_connector_state *conn_state,
  660. struct sde_connector_state *sde_conn_state,
  661. struct sde_crtc_state *sde_crtc_state)
  662. {
  663. int ret = 0;
  664. if (crtc_state->mode_changed || crtc_state->active_changed) {
  665. struct sde_rect mode_roi, roi;
  666. mode_roi.x = 0;
  667. mode_roi.y = 0;
  668. mode_roi.w = crtc_state->adjusted_mode.hdisplay;
  669. mode_roi.h = crtc_state->adjusted_mode.vdisplay;
  670. if (sde_conn_state->rois.num_rects) {
  671. sde_kms_rect_merge_rectangles(
  672. &sde_conn_state->rois, &roi);
  673. if (!sde_kms_rect_is_equal(&mode_roi, &roi)) {
  674. SDE_ERROR_ENC(sde_enc,
  675. "roi (%d,%d,%d,%d) on connector invalid during modeset\n",
  676. roi.x, roi.y, roi.w, roi.h);
  677. ret = -EINVAL;
  678. }
  679. }
  680. if (sde_crtc_state->user_roi_list.num_rects) {
  681. sde_kms_rect_merge_rectangles(
  682. &sde_crtc_state->user_roi_list, &roi);
  683. if (!sde_kms_rect_is_equal(&mode_roi, &roi)) {
  684. SDE_ERROR_ENC(sde_enc,
  685. "roi (%d,%d,%d,%d) on crtc invalid during modeset\n",
  686. roi.x, roi.y, roi.w, roi.h);
  687. ret = -EINVAL;
  688. }
  689. }
  690. }
  691. return ret;
  692. }
  693. static int _sde_encoder_atomic_check_reserve(struct drm_encoder *drm_enc,
  694. struct drm_crtc_state *crtc_state,
  695. struct drm_connector_state *conn_state,
  696. struct sde_encoder_virt *sde_enc, struct sde_kms *sde_kms,
  697. struct sde_connector *sde_conn,
  698. struct sde_connector_state *sde_conn_state)
  699. {
  700. int ret = 0;
  701. struct drm_display_mode *adj_mode = &crtc_state->adjusted_mode;
  702. if (sde_conn && drm_atomic_crtc_needs_modeset(crtc_state)) {
  703. struct msm_display_topology *topology = NULL;
  704. ret = sde_connector_get_mode_info(&sde_conn->base,
  705. adj_mode, &sde_conn_state->mode_info);
  706. if (ret) {
  707. SDE_ERROR_ENC(sde_enc,
  708. "failed to get mode info, rc = %d\n", ret);
  709. return ret;
  710. }
  711. if (sde_conn_state->mode_info.comp_info.comp_type &&
  712. sde_conn_state->mode_info.comp_info.comp_ratio >=
  713. MSM_DISPLAY_COMPRESSION_RATIO_MAX) {
  714. SDE_ERROR_ENC(sde_enc,
  715. "invalid compression ratio: %d\n",
  716. sde_conn_state->mode_info.comp_info.comp_ratio);
  717. ret = -EINVAL;
  718. return ret;
  719. }
  720. /* Reserve dynamic resources, indicating atomic_check phase */
  721. ret = sde_rm_reserve(&sde_kms->rm, drm_enc, crtc_state,
  722. conn_state, true);
  723. if (ret) {
  724. SDE_ERROR_ENC(sde_enc,
  725. "RM failed to reserve resources, rc = %d\n",
  726. ret);
  727. return ret;
  728. }
  729. /**
  730. * Update connector state with the topology selected for the
  731. * resource set validated. Reset the topology if we are
  732. * de-activating crtc.
  733. */
  734. if (crtc_state->active)
  735. topology = &sde_conn_state->mode_info.topology;
  736. ret = sde_rm_update_topology(&sde_kms->rm,
  737. conn_state, topology);
  738. if (ret) {
  739. SDE_ERROR_ENC(sde_enc,
  740. "RM failed to update topology, rc: %d\n", ret);
  741. return ret;
  742. }
  743. ret = sde_connector_set_blob_data(conn_state->connector,
  744. conn_state,
  745. CONNECTOR_PROP_SDE_INFO);
  746. if (ret) {
  747. SDE_ERROR_ENC(sde_enc,
  748. "connector failed to update info, rc: %d\n",
  749. ret);
  750. return ret;
  751. }
  752. }
  753. return ret;
  754. }
  755. static int sde_encoder_virt_atomic_check(
  756. struct drm_encoder *drm_enc, struct drm_crtc_state *crtc_state,
  757. struct drm_connector_state *conn_state)
  758. {
  759. struct sde_encoder_virt *sde_enc;
  760. struct sde_kms *sde_kms;
  761. const struct drm_display_mode *mode;
  762. struct drm_display_mode *adj_mode;
  763. struct sde_connector *sde_conn = NULL;
  764. struct sde_connector_state *sde_conn_state = NULL;
  765. struct sde_crtc_state *sde_crtc_state = NULL;
  766. enum sde_rm_topology_name old_top;
  767. int ret = 0;
  768. if (!drm_enc || !crtc_state || !conn_state) {
  769. SDE_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
  770. !drm_enc, !crtc_state, !conn_state);
  771. return -EINVAL;
  772. }
  773. sde_enc = to_sde_encoder_virt(drm_enc);
  774. SDE_DEBUG_ENC(sde_enc, "\n");
  775. sde_kms = sde_encoder_get_kms(drm_enc);
  776. if (!sde_kms)
  777. return -EINVAL;
  778. mode = &crtc_state->mode;
  779. adj_mode = &crtc_state->adjusted_mode;
  780. sde_conn = to_sde_connector(conn_state->connector);
  781. sde_conn_state = to_sde_connector_state(conn_state);
  782. sde_crtc_state = to_sde_crtc_state(crtc_state);
  783. SDE_EVT32(DRMID(drm_enc), crtc_state->mode_changed,
  784. crtc_state->active_changed, crtc_state->connectors_changed);
  785. ret = _sde_encoder_atomic_check_phys_enc(sde_enc, crtc_state,
  786. conn_state);
  787. if (ret)
  788. return ret;
  789. ret = _sde_encoder_atomic_check_pu_roi(sde_enc, crtc_state,
  790. conn_state, sde_conn_state, sde_crtc_state);
  791. if (ret)
  792. return ret;
  793. /**
  794. * record topology in previous atomic state to be able to handle
  795. * topology transitions correctly.
  796. */
  797. old_top = sde_connector_get_property(conn_state,
  798. CONNECTOR_PROP_TOPOLOGY_NAME);
  799. ret = sde_connector_set_old_topology_name(conn_state, old_top);
  800. if (ret)
  801. return ret;
  802. ret = _sde_encoder_atomic_check_reserve(drm_enc, crtc_state,
  803. conn_state, sde_enc, sde_kms, sde_conn, sde_conn_state);
  804. if (ret)
  805. return ret;
  806. ret = sde_connector_roi_v1_check_roi(conn_state);
  807. if (ret) {
  808. SDE_ERROR_ENC(sde_enc, "connector roi check failed, rc: %d",
  809. ret);
  810. return ret;
  811. }
  812. drm_mode_set_crtcinfo(adj_mode, 0);
  813. SDE_EVT32(DRMID(drm_enc), adj_mode->flags, adj_mode->private_flags);
  814. return ret;
  815. }
  816. static void _sde_encoder_get_connector_roi(
  817. struct sde_encoder_virt *sde_enc,
  818. struct sde_rect *merged_conn_roi)
  819. {
  820. struct drm_connector *drm_conn;
  821. struct sde_connector_state *c_state;
  822. if (!sde_enc || !merged_conn_roi)
  823. return;
  824. drm_conn = sde_enc->phys_encs[0]->connector;
  825. if (!drm_conn || !drm_conn->state)
  826. return;
  827. c_state = to_sde_connector_state(drm_conn->state);
  828. sde_kms_rect_merge_rectangles(&c_state->rois, merged_conn_roi);
  829. }
  830. static int _sde_encoder_update_roi(struct drm_encoder *drm_enc)
  831. {
  832. struct sde_encoder_virt *sde_enc;
  833. struct drm_connector *drm_conn;
  834. struct drm_display_mode *adj_mode;
  835. struct sde_rect roi;
  836. if (!drm_enc) {
  837. SDE_ERROR("invalid encoder parameter\n");
  838. return -EINVAL;
  839. }
  840. sde_enc = to_sde_encoder_virt(drm_enc);
  841. if (!sde_enc->crtc || !sde_enc->crtc->state) {
  842. SDE_ERROR("invalid crtc parameter\n");
  843. return -EINVAL;
  844. }
  845. if (!sde_enc->cur_master) {
  846. SDE_ERROR("invalid cur_master parameter\n");
  847. return -EINVAL;
  848. }
  849. adj_mode = &sde_enc->cur_master->cached_mode;
  850. drm_conn = sde_enc->cur_master->connector;
  851. _sde_encoder_get_connector_roi(sde_enc, &roi);
  852. if (sde_kms_rect_is_null(&roi)) {
  853. roi.w = adj_mode->hdisplay;
  854. roi.h = adj_mode->vdisplay;
  855. }
  856. memcpy(&sde_enc->prv_conn_roi, &sde_enc->cur_conn_roi,
  857. sizeof(sde_enc->prv_conn_roi));
  858. memcpy(&sde_enc->cur_conn_roi, &roi, sizeof(sde_enc->cur_conn_roi));
  859. return 0;
  860. }
  861. void sde_encoder_helper_vsync_config(struct sde_encoder_phys *phys_enc,
  862. u32 vsync_source, bool is_dummy)
  863. {
  864. struct sde_vsync_source_cfg vsync_cfg = { 0 };
  865. struct sde_kms *sde_kms;
  866. struct sde_hw_mdp *hw_mdptop;
  867. struct sde_encoder_virt *sde_enc;
  868. int i;
  869. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  870. if (!sde_enc) {
  871. SDE_ERROR("invalid param sde_enc:%d\n", sde_enc != NULL);
  872. return;
  873. } else if (sde_enc->num_phys_encs > ARRAY_SIZE(sde_enc->hw_pp)) {
  874. SDE_ERROR("invalid num phys enc %d/%d\n",
  875. sde_enc->num_phys_encs,
  876. (int) ARRAY_SIZE(sde_enc->hw_pp));
  877. return;
  878. }
  879. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  880. if (!sde_kms) {
  881. SDE_ERROR("invalid sde_kms\n");
  882. return;
  883. }
  884. hw_mdptop = sde_kms->hw_mdp;
  885. if (!hw_mdptop) {
  886. SDE_ERROR("invalid mdptop\n");
  887. return;
  888. }
  889. if (hw_mdptop->ops.setup_vsync_source) {
  890. for (i = 0; i < sde_enc->num_phys_encs; i++)
  891. vsync_cfg.ppnumber[i] = sde_enc->hw_pp[i]->idx;
  892. vsync_cfg.pp_count = sde_enc->num_phys_encs;
  893. vsync_cfg.frame_rate = sde_enc->mode_info.frame_rate;
  894. vsync_cfg.vsync_source = vsync_source;
  895. vsync_cfg.is_dummy = is_dummy;
  896. hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
  897. }
  898. }
  899. static void _sde_encoder_update_vsync_source(struct sde_encoder_virt *sde_enc,
  900. struct msm_display_info *disp_info, bool is_dummy)
  901. {
  902. struct sde_encoder_phys *phys;
  903. int i;
  904. u32 vsync_source;
  905. if (!sde_enc || !disp_info) {
  906. SDE_ERROR("invalid param sde_enc:%d or disp_info:%d\n",
  907. sde_enc != NULL, disp_info != NULL);
  908. return;
  909. } else if (sde_enc->num_phys_encs > ARRAY_SIZE(sde_enc->hw_pp)) {
  910. SDE_ERROR("invalid num phys enc %d/%d\n",
  911. sde_enc->num_phys_encs,
  912. (int) ARRAY_SIZE(sde_enc->hw_pp));
  913. return;
  914. }
  915. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_CMD_MODE)) {
  916. if (is_dummy)
  917. vsync_source = SDE_VSYNC_SOURCE_WD_TIMER_0 -
  918. sde_enc->te_source;
  919. else if (disp_info->is_te_using_watchdog_timer)
  920. vsync_source = SDE_VSYNC_SOURCE_WD_TIMER_4;
  921. else
  922. vsync_source = sde_enc->te_source;
  923. SDE_EVT32(DRMID(&sde_enc->base), vsync_source, is_dummy,
  924. disp_info->is_te_using_watchdog_timer);
  925. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  926. phys = sde_enc->phys_encs[i];
  927. if (phys && phys->ops.setup_vsync_source)
  928. phys->ops.setup_vsync_source(phys,
  929. vsync_source, is_dummy);
  930. }
  931. }
  932. }
  933. int sde_encoder_helper_switch_vsync(struct drm_encoder *drm_enc,
  934. bool watchdog_te)
  935. {
  936. struct sde_encoder_virt *sde_enc;
  937. struct msm_display_info disp_info;
  938. if (!drm_enc) {
  939. pr_err("invalid drm encoder\n");
  940. return -EINVAL;
  941. }
  942. sde_enc = to_sde_encoder_virt(drm_enc);
  943. sde_encoder_control_te(drm_enc, false);
  944. memcpy(&disp_info, &sde_enc->disp_info, sizeof(disp_info));
  945. disp_info.is_te_using_watchdog_timer = watchdog_te;
  946. _sde_encoder_update_vsync_source(sde_enc, &disp_info, false);
  947. sde_encoder_control_te(drm_enc, true);
  948. return 0;
  949. }
  950. static int _sde_encoder_rsc_client_update_vsync_wait(
  951. struct drm_encoder *drm_enc, struct sde_encoder_virt *sde_enc,
  952. int wait_vblank_crtc_id)
  953. {
  954. int wait_refcount = 0, ret = 0;
  955. int pipe = -1;
  956. int wait_count = 0;
  957. struct drm_crtc *primary_crtc;
  958. struct drm_crtc *crtc;
  959. crtc = sde_enc->crtc;
  960. if (wait_vblank_crtc_id)
  961. wait_refcount =
  962. sde_rsc_client_get_vsync_refcount(sde_enc->rsc_client);
  963. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id, wait_refcount,
  964. SDE_EVTLOG_FUNC_ENTRY);
  965. if (crtc->base.id != wait_vblank_crtc_id) {
  966. primary_crtc = drm_crtc_find(drm_enc->dev,
  967. NULL, wait_vblank_crtc_id);
  968. if (!primary_crtc) {
  969. SDE_ERROR_ENC(sde_enc,
  970. "failed to find primary crtc id %d\n",
  971. wait_vblank_crtc_id);
  972. return -EINVAL;
  973. }
  974. pipe = drm_crtc_index(primary_crtc);
  975. }
  976. /**
  977. * note: VBLANK is expected to be enabled at this point in
  978. * resource control state machine if on primary CRTC
  979. */
  980. for (wait_count = 0; wait_count < MAX_RSC_WAIT; wait_count++) {
  981. if (sde_rsc_client_is_state_update_complete(
  982. sde_enc->rsc_client))
  983. break;
  984. if (crtc->base.id == wait_vblank_crtc_id)
  985. ret = sde_encoder_wait_for_event(drm_enc,
  986. MSM_ENC_VBLANK);
  987. else
  988. drm_wait_one_vblank(drm_enc->dev, pipe);
  989. if (ret) {
  990. SDE_ERROR_ENC(sde_enc,
  991. "wait for vblank failed ret:%d\n", ret);
  992. /**
  993. * rsc hardware may hang without vsync. avoid rsc hang
  994. * by generating the vsync from watchdog timer.
  995. */
  996. if (crtc->base.id == wait_vblank_crtc_id)
  997. sde_encoder_helper_switch_vsync(drm_enc, true);
  998. }
  999. }
  1000. if (wait_count >= MAX_RSC_WAIT)
  1001. SDE_EVT32(DRMID(drm_enc), wait_vblank_crtc_id, wait_count,
  1002. SDE_EVTLOG_ERROR);
  1003. if (wait_refcount)
  1004. sde_rsc_client_reset_vsync_refcount(sde_enc->rsc_client);
  1005. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id, wait_refcount,
  1006. SDE_EVTLOG_FUNC_EXIT);
  1007. return ret;
  1008. }
  1009. static int _sde_encoder_update_rsc_client(
  1010. struct drm_encoder *drm_enc, bool enable)
  1011. {
  1012. struct sde_encoder_virt *sde_enc;
  1013. struct drm_crtc *crtc;
  1014. enum sde_rsc_state rsc_state = SDE_RSC_IDLE_STATE;
  1015. struct sde_rsc_cmd_config *rsc_config;
  1016. int ret;
  1017. struct msm_display_info *disp_info;
  1018. struct msm_mode_info *mode_info;
  1019. int wait_vblank_crtc_id = SDE_RSC_INVALID_CRTC_ID;
  1020. u32 qsync_mode = 0, v_front_porch;
  1021. struct drm_display_mode *mode;
  1022. bool is_vid_mode;
  1023. struct drm_encoder *enc;
  1024. if (!drm_enc || !drm_enc->dev) {
  1025. SDE_ERROR("invalid encoder arguments\n");
  1026. return -EINVAL;
  1027. }
  1028. sde_enc = to_sde_encoder_virt(drm_enc);
  1029. mode_info = &sde_enc->mode_info;
  1030. crtc = sde_enc->crtc;
  1031. if (!sde_enc->crtc) {
  1032. SDE_ERROR("invalid crtc parameter\n");
  1033. return -EINVAL;
  1034. }
  1035. disp_info = &sde_enc->disp_info;
  1036. rsc_config = &sde_enc->rsc_config;
  1037. if (!sde_enc->rsc_client) {
  1038. SDE_DEBUG_ENC(sde_enc, "rsc client not created\n");
  1039. return 0;
  1040. }
  1041. /**
  1042. * only primary command mode panel without Qsync can request CMD state.
  1043. * all other panels/displays can request for VID state including
  1044. * secondary command mode panel.
  1045. * Clone mode encoder can request CLK STATE only.
  1046. */
  1047. if (sde_enc->cur_master)
  1048. qsync_mode = sde_connector_get_qsync_mode(
  1049. sde_enc->cur_master->connector);
  1050. if (sde_encoder_in_clone_mode(drm_enc) ||
  1051. (disp_info->display_type != SDE_CONNECTOR_PRIMARY) ||
  1052. (disp_info->display_type && qsync_mode))
  1053. rsc_state = enable ? SDE_RSC_CLK_STATE : SDE_RSC_IDLE_STATE;
  1054. else if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1055. rsc_state = enable ? SDE_RSC_CMD_STATE : SDE_RSC_IDLE_STATE;
  1056. else if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE))
  1057. rsc_state = enable ? SDE_RSC_VID_STATE : SDE_RSC_IDLE_STATE;
  1058. drm_for_each_encoder(enc, drm_enc->dev) {
  1059. if (enc->base.id != drm_enc->base.id &&
  1060. sde_encoder_in_cont_splash(enc))
  1061. rsc_state = SDE_RSC_CLK_STATE;
  1062. }
  1063. SDE_EVT32(rsc_state, qsync_mode);
  1064. is_vid_mode = sde_encoder_check_curr_mode(&sde_enc->base,
  1065. MSM_DISPLAY_VIDEO_MODE);
  1066. mode = &sde_enc->crtc->state->mode;
  1067. v_front_porch = mode->vsync_start - mode->vdisplay;
  1068. /* compare specific items and reconfigure the rsc */
  1069. if ((rsc_config->fps != mode_info->frame_rate) ||
  1070. (rsc_config->vtotal != mode_info->vtotal) ||
  1071. (rsc_config->prefill_lines != mode_info->prefill_lines) ||
  1072. (rsc_config->jitter_numer != mode_info->jitter_numer) ||
  1073. (rsc_config->jitter_denom != mode_info->jitter_denom)) {
  1074. rsc_config->fps = mode_info->frame_rate;
  1075. rsc_config->vtotal = mode_info->vtotal;
  1076. /*
  1077. * for video mode, prefill lines should not go beyond vertical
  1078. * front porch for RSCC configuration. This will ensure bw
  1079. * downvotes are not sent within the active region. Additional
  1080. * -1 is to give one line time for rscc mode min_threshold.
  1081. */
  1082. if (is_vid_mode && (mode_info->prefill_lines >= v_front_porch))
  1083. rsc_config->prefill_lines = v_front_porch - 1;
  1084. else
  1085. rsc_config->prefill_lines = mode_info->prefill_lines;
  1086. rsc_config->jitter_numer = mode_info->jitter_numer;
  1087. rsc_config->jitter_denom = mode_info->jitter_denom;
  1088. sde_enc->rsc_state_init = false;
  1089. }
  1090. if (rsc_state != SDE_RSC_IDLE_STATE && !sde_enc->rsc_state_init
  1091. && (disp_info->display_type == SDE_CONNECTOR_PRIMARY)) {
  1092. /* update it only once */
  1093. sde_enc->rsc_state_init = true;
  1094. ret = sde_rsc_client_state_update(sde_enc->rsc_client,
  1095. rsc_state, rsc_config, crtc->base.id,
  1096. &wait_vblank_crtc_id);
  1097. } else {
  1098. ret = sde_rsc_client_state_update(sde_enc->rsc_client,
  1099. rsc_state, NULL, crtc->base.id,
  1100. &wait_vblank_crtc_id);
  1101. }
  1102. /**
  1103. * if RSC performed a state change that requires a VBLANK wait, it will
  1104. * set wait_vblank_crtc_id to the CRTC whose VBLANK we must wait on.
  1105. *
  1106. * if we are the primary display, we will need to enable and wait
  1107. * locally since we hold the commit thread
  1108. *
  1109. * if we are an external display, we must send a signal to the primary
  1110. * to enable its VBLANK and wait one, since the RSC hardware is driven
  1111. * by the primary panel's VBLANK signals
  1112. */
  1113. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id);
  1114. if (ret) {
  1115. SDE_ERROR_ENC(sde_enc,
  1116. "sde rsc client update failed ret:%d\n", ret);
  1117. return ret;
  1118. } else if (wait_vblank_crtc_id == SDE_RSC_INVALID_CRTC_ID) {
  1119. return ret;
  1120. }
  1121. ret = _sde_encoder_rsc_client_update_vsync_wait(drm_enc,
  1122. sde_enc, wait_vblank_crtc_id);
  1123. return ret;
  1124. }
  1125. static void _sde_encoder_irq_control(struct drm_encoder *drm_enc, bool enable)
  1126. {
  1127. struct sde_encoder_virt *sde_enc;
  1128. int i;
  1129. if (!drm_enc) {
  1130. SDE_ERROR("invalid encoder\n");
  1131. return;
  1132. }
  1133. sde_enc = to_sde_encoder_virt(drm_enc);
  1134. SDE_DEBUG_ENC(sde_enc, "enable:%d\n", enable);
  1135. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1136. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1137. if (phys && phys->ops.irq_control)
  1138. phys->ops.irq_control(phys, enable);
  1139. }
  1140. }
  1141. /* keep track of the userspace vblank during modeset */
  1142. static void _sde_encoder_modeset_helper_locked(struct drm_encoder *drm_enc,
  1143. u32 sw_event)
  1144. {
  1145. struct sde_encoder_virt *sde_enc;
  1146. bool enable;
  1147. int i;
  1148. if (!drm_enc) {
  1149. SDE_ERROR("invalid encoder\n");
  1150. return;
  1151. }
  1152. sde_enc = to_sde_encoder_virt(drm_enc);
  1153. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, vblank_enabled:%d\n",
  1154. sw_event, sde_enc->vblank_enabled);
  1155. /* nothing to do if vblank not enabled by userspace */
  1156. if (!sde_enc->vblank_enabled)
  1157. return;
  1158. /* disable vblank on pre_modeset */
  1159. if (sw_event == SDE_ENC_RC_EVENT_PRE_MODESET)
  1160. enable = false;
  1161. /* enable vblank on post_modeset */
  1162. else if (sw_event == SDE_ENC_RC_EVENT_POST_MODESET)
  1163. enable = true;
  1164. else
  1165. return;
  1166. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1167. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1168. if (phys && phys->ops.control_vblank_irq)
  1169. phys->ops.control_vblank_irq(phys, enable);
  1170. }
  1171. }
  1172. struct sde_rsc_client *sde_encoder_get_rsc_client(struct drm_encoder *drm_enc)
  1173. {
  1174. struct sde_encoder_virt *sde_enc;
  1175. if (!drm_enc)
  1176. return NULL;
  1177. sde_enc = to_sde_encoder_virt(drm_enc);
  1178. return sde_enc->rsc_client;
  1179. }
  1180. static int _sde_encoder_resource_control_helper(struct drm_encoder *drm_enc,
  1181. bool enable)
  1182. {
  1183. struct sde_kms *sde_kms;
  1184. struct sde_encoder_virt *sde_enc;
  1185. int rc;
  1186. sde_enc = to_sde_encoder_virt(drm_enc);
  1187. sde_kms = sde_encoder_get_kms(drm_enc);
  1188. if (!sde_kms)
  1189. return -EINVAL;
  1190. SDE_DEBUG_ENC(sde_enc, "enable:%d\n", enable);
  1191. SDE_EVT32(DRMID(drm_enc), enable);
  1192. if (!sde_enc->cur_master) {
  1193. SDE_ERROR("encoder master not set\n");
  1194. return -EINVAL;
  1195. }
  1196. if (enable) {
  1197. /* enable SDE core clks */
  1198. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  1199. if (rc < 0) {
  1200. SDE_ERROR("failed to enable power resource %d\n", rc);
  1201. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  1202. return rc;
  1203. }
  1204. sde_enc->elevated_ahb_vote = true;
  1205. /* enable DSI clks */
  1206. rc = sde_connector_clk_ctrl(sde_enc->cur_master->connector,
  1207. true);
  1208. if (rc) {
  1209. SDE_ERROR("failed to enable clk control %d\n", rc);
  1210. pm_runtime_put_sync(drm_enc->dev->dev);
  1211. return rc;
  1212. }
  1213. /* enable all the irq */
  1214. _sde_encoder_irq_control(drm_enc, true);
  1215. _sde_encoder_pm_qos_add_request(drm_enc);
  1216. } else {
  1217. _sde_encoder_pm_qos_remove_request(drm_enc);
  1218. /* disable all the irq */
  1219. _sde_encoder_irq_control(drm_enc, false);
  1220. /* disable DSI clks */
  1221. sde_connector_clk_ctrl(sde_enc->cur_master->connector, false);
  1222. /* disable SDE core clks */
  1223. pm_runtime_put_sync(drm_enc->dev->dev);
  1224. }
  1225. return 0;
  1226. }
  1227. static void sde_encoder_misr_configure(struct drm_encoder *drm_enc,
  1228. bool enable, u32 frame_count)
  1229. {
  1230. struct sde_encoder_virt *sde_enc;
  1231. int i;
  1232. if (!drm_enc) {
  1233. SDE_ERROR("invalid encoder\n");
  1234. return;
  1235. }
  1236. sde_enc = to_sde_encoder_virt(drm_enc);
  1237. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1238. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1239. if (!phys || !phys->ops.setup_misr)
  1240. continue;
  1241. phys->ops.setup_misr(phys, enable, frame_count);
  1242. }
  1243. }
  1244. static void sde_encoder_input_event_handler(struct input_handle *handle,
  1245. unsigned int type, unsigned int code, int value)
  1246. {
  1247. struct drm_encoder *drm_enc = NULL;
  1248. struct sde_encoder_virt *sde_enc = NULL;
  1249. struct msm_drm_thread *disp_thread = NULL;
  1250. struct msm_drm_private *priv = NULL;
  1251. if (!handle || !handle->handler || !handle->handler->private) {
  1252. SDE_ERROR("invalid encoder for the input event\n");
  1253. return;
  1254. }
  1255. drm_enc = (struct drm_encoder *)handle->handler->private;
  1256. if (!drm_enc->dev || !drm_enc->dev->dev_private) {
  1257. SDE_ERROR("invalid parameters\n");
  1258. return;
  1259. }
  1260. priv = drm_enc->dev->dev_private;
  1261. sde_enc = to_sde_encoder_virt(drm_enc);
  1262. if (!sde_enc->crtc || (sde_enc->crtc->index
  1263. >= ARRAY_SIZE(priv->disp_thread))) {
  1264. SDE_DEBUG_ENC(sde_enc,
  1265. "invalid cached CRTC: %d or crtc index: %d\n",
  1266. sde_enc->crtc == NULL,
  1267. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  1268. return;
  1269. }
  1270. SDE_EVT32_VERBOSE(DRMID(drm_enc));
  1271. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1272. kthread_queue_work(&disp_thread->worker,
  1273. &sde_enc->input_event_work);
  1274. }
  1275. void sde_encoder_control_idle_pc(struct drm_encoder *drm_enc, bool enable)
  1276. {
  1277. struct sde_encoder_virt *sde_enc;
  1278. if (!drm_enc) {
  1279. SDE_ERROR("invalid encoder\n");
  1280. return;
  1281. }
  1282. sde_enc = to_sde_encoder_virt(drm_enc);
  1283. /* return early if there is no state change */
  1284. if (sde_enc->idle_pc_enabled == enable)
  1285. return;
  1286. sde_enc->idle_pc_enabled = enable;
  1287. SDE_DEBUG("idle-pc state:%d\n", sde_enc->idle_pc_enabled);
  1288. SDE_EVT32(sde_enc->idle_pc_enabled);
  1289. }
  1290. static void _sde_encoder_rc_restart_delayed(struct sde_encoder_virt *sde_enc,
  1291. u32 sw_event)
  1292. {
  1293. struct drm_encoder *drm_enc = &sde_enc->base;
  1294. struct msm_drm_private *priv;
  1295. unsigned int lp, idle_pc_duration;
  1296. struct msm_drm_thread *disp_thread;
  1297. /* set idle timeout based on master connector's lp value */
  1298. if (sde_enc->cur_master)
  1299. lp = sde_connector_get_lp(
  1300. sde_enc->cur_master->connector);
  1301. else
  1302. lp = SDE_MODE_DPMS_ON;
  1303. if (lp == SDE_MODE_DPMS_LP2)
  1304. idle_pc_duration = IDLE_SHORT_TIMEOUT;
  1305. else
  1306. idle_pc_duration = IDLE_POWERCOLLAPSE_DURATION;
  1307. priv = drm_enc->dev->dev_private;
  1308. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1309. kthread_mod_delayed_work(
  1310. &disp_thread->worker,
  1311. &sde_enc->delayed_off_work,
  1312. msecs_to_jiffies(idle_pc_duration));
  1313. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1314. idle_pc_duration, SDE_EVTLOG_FUNC_CASE2);
  1315. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work scheduled\n",
  1316. sw_event);
  1317. }
  1318. static void _sde_encoder_rc_cancel_delayed(struct sde_encoder_virt *sde_enc,
  1319. u32 sw_event)
  1320. {
  1321. if (kthread_cancel_delayed_work_sync(
  1322. &sde_enc->delayed_off_work))
  1323. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work cancelled\n",
  1324. sw_event);
  1325. }
  1326. static void _sde_encoder_rc_kickoff_delayed(struct sde_encoder_virt *sde_enc,
  1327. u32 sw_event)
  1328. {
  1329. if (_sde_encoder_is_autorefresh_enabled(sde_enc))
  1330. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1331. else
  1332. _sde_encoder_rc_restart_delayed(sde_enc, sw_event);
  1333. }
  1334. static int _sde_encoder_rc_kickoff(struct drm_encoder *drm_enc,
  1335. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1336. {
  1337. int ret = 0;
  1338. mutex_lock(&sde_enc->rc_lock);
  1339. /* return if the resource control is already in ON state */
  1340. if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON) {
  1341. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in ON state\n",
  1342. sw_event);
  1343. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1344. SDE_EVTLOG_FUNC_CASE1);
  1345. goto end;
  1346. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_OFF &&
  1347. sde_enc->rc_state != SDE_ENC_RC_STATE_IDLE) {
  1348. SDE_ERROR_ENC(sde_enc, "sw_event:%d, rc in state %d\n",
  1349. sw_event, sde_enc->rc_state);
  1350. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1351. SDE_EVTLOG_ERROR);
  1352. goto end;
  1353. }
  1354. if (is_vid_mode && sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1355. _sde_encoder_irq_control(drm_enc, true);
  1356. } else {
  1357. /* enable all the clks and resources */
  1358. ret = _sde_encoder_resource_control_helper(drm_enc,
  1359. true);
  1360. if (ret) {
  1361. SDE_ERROR_ENC(sde_enc,
  1362. "sw_event:%d, rc in state %d\n",
  1363. sw_event, sde_enc->rc_state);
  1364. SDE_EVT32(DRMID(drm_enc), sw_event,
  1365. sde_enc->rc_state,
  1366. SDE_EVTLOG_ERROR);
  1367. goto end;
  1368. }
  1369. _sde_encoder_update_rsc_client(drm_enc, true);
  1370. }
  1371. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1372. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE1);
  1373. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1374. end:
  1375. _sde_encoder_rc_kickoff_delayed(sde_enc, sw_event);
  1376. mutex_unlock(&sde_enc->rc_lock);
  1377. return ret;
  1378. }
  1379. static int _sde_encoder_rc_pre_stop(struct drm_encoder *drm_enc,
  1380. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1381. {
  1382. /* cancel delayed off work, if any */
  1383. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1384. mutex_lock(&sde_enc->rc_lock);
  1385. if (is_vid_mode &&
  1386. sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1387. _sde_encoder_irq_control(drm_enc, true);
  1388. }
  1389. /* skip if is already OFF or IDLE, resources are off already */
  1390. else if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF ||
  1391. sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1392. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in %d state\n",
  1393. sw_event, sde_enc->rc_state);
  1394. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1395. SDE_EVTLOG_FUNC_CASE3);
  1396. goto end;
  1397. }
  1398. /**
  1399. * IRQs are still enabled currently, which allows wait for
  1400. * VBLANK which RSC may require to correctly transition to OFF
  1401. */
  1402. _sde_encoder_update_rsc_client(drm_enc, false);
  1403. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1404. SDE_ENC_RC_STATE_PRE_OFF,
  1405. SDE_EVTLOG_FUNC_CASE3);
  1406. sde_enc->rc_state = SDE_ENC_RC_STATE_PRE_OFF;
  1407. end:
  1408. mutex_unlock(&sde_enc->rc_lock);
  1409. return 0;
  1410. }
  1411. static int _sde_encoder_rc_stop(struct drm_encoder *drm_enc,
  1412. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1413. {
  1414. int ret = 0;
  1415. mutex_lock(&sde_enc->rc_lock);
  1416. /* return if the resource control is already in OFF state */
  1417. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1418. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1419. sw_event);
  1420. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1421. SDE_EVTLOG_FUNC_CASE4);
  1422. goto end;
  1423. } else if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON ||
  1424. sde_enc->rc_state == SDE_ENC_RC_STATE_MODESET) {
  1425. SDE_ERROR_ENC(sde_enc, "sw_event:%d, rc in state %d\n",
  1426. sw_event, sde_enc->rc_state);
  1427. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1428. SDE_EVTLOG_ERROR);
  1429. ret = -EINVAL;
  1430. goto end;
  1431. }
  1432. /**
  1433. * expect to arrive here only if in either idle state or pre-off
  1434. * and in IDLE state the resources are already disabled
  1435. */
  1436. if (sde_enc->rc_state == SDE_ENC_RC_STATE_PRE_OFF)
  1437. _sde_encoder_resource_control_helper(drm_enc, false);
  1438. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1439. SDE_ENC_RC_STATE_OFF, SDE_EVTLOG_FUNC_CASE4);
  1440. sde_enc->rc_state = SDE_ENC_RC_STATE_OFF;
  1441. end:
  1442. mutex_unlock(&sde_enc->rc_lock);
  1443. return ret;
  1444. }
  1445. static int _sde_encoder_rc_pre_modeset(struct drm_encoder *drm_enc,
  1446. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1447. {
  1448. int ret = 0;
  1449. /* cancel delayed off work, if any */
  1450. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1451. mutex_lock(&sde_enc->rc_lock);
  1452. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1453. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1454. sw_event);
  1455. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1456. SDE_EVTLOG_FUNC_CASE5);
  1457. goto end;
  1458. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
  1459. /* enable all the clks and resources */
  1460. ret = _sde_encoder_resource_control_helper(drm_enc,
  1461. true);
  1462. if (ret) {
  1463. SDE_ERROR_ENC(sde_enc,
  1464. "sw_event:%d, rc in state %d\n",
  1465. sw_event, sde_enc->rc_state);
  1466. SDE_EVT32(DRMID(drm_enc), sw_event,
  1467. sde_enc->rc_state,
  1468. SDE_EVTLOG_ERROR);
  1469. goto end;
  1470. }
  1471. _sde_encoder_update_rsc_client(drm_enc, true);
  1472. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1473. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE5);
  1474. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1475. }
  1476. ret = sde_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
  1477. if (ret && ret != -EWOULDBLOCK) {
  1478. SDE_ERROR_ENC(sde_enc,
  1479. "wait for commit done returned %d\n",
  1480. ret);
  1481. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1482. ret, SDE_EVTLOG_ERROR);
  1483. ret = -EINVAL;
  1484. goto end;
  1485. }
  1486. _sde_encoder_irq_control(drm_enc, false);
  1487. _sde_encoder_modeset_helper_locked(drm_enc, sw_event);
  1488. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1489. SDE_ENC_RC_STATE_MODESET, SDE_EVTLOG_FUNC_CASE5);
  1490. sde_enc->rc_state = SDE_ENC_RC_STATE_MODESET;
  1491. _sde_encoder_pm_qos_remove_request(drm_enc);
  1492. end:
  1493. mutex_unlock(&sde_enc->rc_lock);
  1494. return ret;
  1495. }
  1496. static int _sde_encoder_rc_post_modeset(struct drm_encoder *drm_enc,
  1497. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1498. {
  1499. int ret = 0;
  1500. mutex_lock(&sde_enc->rc_lock);
  1501. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1502. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1503. sw_event);
  1504. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1505. SDE_EVTLOG_FUNC_CASE5);
  1506. goto end;
  1507. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_MODESET) {
  1508. SDE_ERROR_ENC(sde_enc,
  1509. "sw_event:%d, rc:%d !MODESET state\n",
  1510. sw_event, sde_enc->rc_state);
  1511. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1512. SDE_EVTLOG_ERROR);
  1513. ret = -EINVAL;
  1514. goto end;
  1515. }
  1516. _sde_encoder_modeset_helper_locked(drm_enc, sw_event);
  1517. _sde_encoder_irq_control(drm_enc, true);
  1518. _sde_encoder_update_rsc_client(drm_enc, true);
  1519. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1520. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE6);
  1521. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1522. _sde_encoder_pm_qos_add_request(drm_enc);
  1523. end:
  1524. mutex_unlock(&sde_enc->rc_lock);
  1525. return ret;
  1526. }
  1527. static int _sde_encoder_rc_idle(struct drm_encoder *drm_enc,
  1528. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1529. {
  1530. struct msm_drm_private *priv;
  1531. struct sde_kms *sde_kms;
  1532. struct drm_crtc *crtc = drm_enc->crtc;
  1533. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  1534. priv = drm_enc->dev->dev_private;
  1535. sde_kms = to_sde_kms(priv->kms);
  1536. mutex_lock(&sde_enc->rc_lock);
  1537. if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
  1538. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc:%d !ON state\n",
  1539. sw_event, sde_enc->rc_state);
  1540. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1541. SDE_EVTLOG_ERROR);
  1542. goto end;
  1543. } else if (sde_crtc_frame_pending(sde_enc->crtc)) {
  1544. SDE_DEBUG_ENC(sde_enc, "skip idle entry");
  1545. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1546. sde_crtc_frame_pending(sde_enc->crtc),
  1547. SDE_EVTLOG_ERROR);
  1548. _sde_encoder_rc_kickoff_delayed(sde_enc, sw_event);
  1549. goto end;
  1550. }
  1551. if (is_vid_mode) {
  1552. _sde_encoder_irq_control(drm_enc, false);
  1553. } else {
  1554. /* disable all the clks and resources */
  1555. _sde_encoder_update_rsc_client(drm_enc, false);
  1556. _sde_encoder_resource_control_helper(drm_enc, false);
  1557. if (!sde_kms->perf.bw_vote_mode)
  1558. memset(&sde_crtc->cur_perf, 0,
  1559. sizeof(struct sde_core_perf_params));
  1560. }
  1561. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1562. SDE_ENC_RC_STATE_IDLE, SDE_EVTLOG_FUNC_CASE7);
  1563. sde_enc->rc_state = SDE_ENC_RC_STATE_IDLE;
  1564. end:
  1565. mutex_unlock(&sde_enc->rc_lock);
  1566. return 0;
  1567. }
  1568. static int _sde_encoder_rc_early_wakeup(struct drm_encoder *drm_enc,
  1569. u32 sw_event, struct sde_encoder_virt *sde_enc,
  1570. struct msm_drm_private *priv, bool is_vid_mode)
  1571. {
  1572. bool autorefresh_enabled = false;
  1573. struct msm_drm_thread *disp_thread;
  1574. int ret = 0;
  1575. if (!sde_enc->crtc ||
  1576. sde_enc->crtc->index >= ARRAY_SIZE(priv->disp_thread)) {
  1577. SDE_DEBUG_ENC(sde_enc,
  1578. "invalid crtc:%d or crtc index:%d , sw_event:%u\n",
  1579. sde_enc->crtc == NULL,
  1580. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL,
  1581. sw_event);
  1582. return -EINVAL;
  1583. }
  1584. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1585. mutex_lock(&sde_enc->rc_lock);
  1586. if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON) {
  1587. if (sde_enc->cur_master &&
  1588. sde_enc->cur_master->ops.is_autorefresh_enabled)
  1589. autorefresh_enabled =
  1590. sde_enc->cur_master->ops.is_autorefresh_enabled(
  1591. sde_enc->cur_master);
  1592. if (autorefresh_enabled) {
  1593. SDE_DEBUG_ENC(sde_enc,
  1594. "not handling early wakeup since auto refresh is enabled\n");
  1595. goto end;
  1596. }
  1597. if (!sde_crtc_frame_pending(sde_enc->crtc))
  1598. kthread_mod_delayed_work(&disp_thread->worker,
  1599. &sde_enc->delayed_off_work,
  1600. msecs_to_jiffies(
  1601. IDLE_POWERCOLLAPSE_DURATION));
  1602. } else if (sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1603. /* enable all the clks and resources */
  1604. ret = _sde_encoder_resource_control_helper(drm_enc,
  1605. true);
  1606. if (ret) {
  1607. SDE_ERROR_ENC(sde_enc,
  1608. "sw_event:%d, rc in state %d\n",
  1609. sw_event, sde_enc->rc_state);
  1610. SDE_EVT32(DRMID(drm_enc), sw_event,
  1611. sde_enc->rc_state,
  1612. SDE_EVTLOG_ERROR);
  1613. goto end;
  1614. }
  1615. _sde_encoder_update_rsc_client(drm_enc, true);
  1616. /*
  1617. * In some cases, commit comes with slight delay
  1618. * (> 80 ms)after early wake up, prevent clock switch
  1619. * off to avoid jank in next update. So, increase the
  1620. * command mode idle timeout sufficiently to prevent
  1621. * such case.
  1622. */
  1623. kthread_mod_delayed_work(&disp_thread->worker,
  1624. &sde_enc->delayed_off_work,
  1625. msecs_to_jiffies(
  1626. IDLE_POWERCOLLAPSE_IN_EARLY_WAKEUP));
  1627. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1628. }
  1629. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1630. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE8);
  1631. end:
  1632. mutex_unlock(&sde_enc->rc_lock);
  1633. return ret;
  1634. }
  1635. static int sde_encoder_resource_control(struct drm_encoder *drm_enc,
  1636. u32 sw_event)
  1637. {
  1638. struct sde_encoder_virt *sde_enc;
  1639. struct msm_drm_private *priv;
  1640. int ret = 0;
  1641. bool is_vid_mode = false;
  1642. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  1643. SDE_ERROR("invalid encoder parameters, sw_event:%u\n",
  1644. sw_event);
  1645. return -EINVAL;
  1646. }
  1647. sde_enc = to_sde_encoder_virt(drm_enc);
  1648. priv = drm_enc->dev->dev_private;
  1649. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_VIDEO_MODE))
  1650. is_vid_mode = true;
  1651. /*
  1652. * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
  1653. * events and return early for other events (ie wb display).
  1654. */
  1655. if (!sde_enc->idle_pc_enabled &&
  1656. (sw_event != SDE_ENC_RC_EVENT_KICKOFF &&
  1657. sw_event != SDE_ENC_RC_EVENT_PRE_MODESET &&
  1658. sw_event != SDE_ENC_RC_EVENT_POST_MODESET &&
  1659. sw_event != SDE_ENC_RC_EVENT_STOP &&
  1660. sw_event != SDE_ENC_RC_EVENT_PRE_STOP))
  1661. return 0;
  1662. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, idle_pc:%d\n",
  1663. sw_event, sde_enc->idle_pc_enabled);
  1664. SDE_EVT32_VERBOSE(DRMID(drm_enc), sw_event, sde_enc->idle_pc_enabled,
  1665. sde_enc->rc_state, SDE_EVTLOG_FUNC_ENTRY);
  1666. switch (sw_event) {
  1667. case SDE_ENC_RC_EVENT_KICKOFF:
  1668. ret = _sde_encoder_rc_kickoff(drm_enc, sw_event, sde_enc,
  1669. is_vid_mode);
  1670. break;
  1671. case SDE_ENC_RC_EVENT_PRE_STOP:
  1672. ret = _sde_encoder_rc_pre_stop(drm_enc, sw_event, sde_enc,
  1673. is_vid_mode);
  1674. break;
  1675. case SDE_ENC_RC_EVENT_STOP:
  1676. ret = _sde_encoder_rc_stop(drm_enc, sw_event, sde_enc);
  1677. break;
  1678. case SDE_ENC_RC_EVENT_PRE_MODESET:
  1679. ret = _sde_encoder_rc_pre_modeset(drm_enc, sw_event, sde_enc);
  1680. break;
  1681. case SDE_ENC_RC_EVENT_POST_MODESET:
  1682. ret = _sde_encoder_rc_post_modeset(drm_enc, sw_event, sde_enc);
  1683. break;
  1684. case SDE_ENC_RC_EVENT_ENTER_IDLE:
  1685. ret = _sde_encoder_rc_idle(drm_enc, sw_event, sde_enc,
  1686. is_vid_mode);
  1687. break;
  1688. case SDE_ENC_RC_EVENT_EARLY_WAKEUP:
  1689. ret = _sde_encoder_rc_early_wakeup(drm_enc, sw_event, sde_enc,
  1690. priv, is_vid_mode);
  1691. break;
  1692. default:
  1693. SDE_EVT32(DRMID(drm_enc), sw_event, SDE_EVTLOG_ERROR);
  1694. SDE_ERROR("unexpected sw_event: %d\n", sw_event);
  1695. break;
  1696. }
  1697. SDE_EVT32_VERBOSE(DRMID(drm_enc), sw_event, sde_enc->idle_pc_enabled,
  1698. sde_enc->rc_state, SDE_EVTLOG_FUNC_EXIT);
  1699. return ret;
  1700. }
  1701. static void sde_encoder_virt_mode_switch(struct drm_encoder *drm_enc,
  1702. enum sde_intf_mode intf_mode, struct drm_display_mode *adj_mode)
  1703. {
  1704. int i = 0;
  1705. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1706. if (intf_mode == INTF_MODE_CMD)
  1707. sde_enc->disp_info.curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  1708. else if (intf_mode == INTF_MODE_VIDEO)
  1709. sde_enc->disp_info.curr_panel_mode = MSM_DISPLAY_CMD_MODE;
  1710. _sde_encoder_update_rsc_client(drm_enc, true);
  1711. if (intf_mode == INTF_MODE_CMD) {
  1712. for (i = 0; i < sde_enc->num_phys_encs; i++)
  1713. sde_enc->phys_encs[i] = sde_enc->phys_vid_encs[i];
  1714. SDE_DEBUG_ENC(sde_enc, "switch to video physical encoder\n");
  1715. SDE_EVT32(DRMID(&sde_enc->base), intf_mode,
  1716. msm_is_mode_seamless_poms(adj_mode),
  1717. SDE_EVTLOG_FUNC_CASE1);
  1718. } else if (intf_mode == INTF_MODE_VIDEO) {
  1719. for (i = 0; i < sde_enc->num_phys_encs; i++)
  1720. sde_enc->phys_encs[i] = sde_enc->phys_cmd_encs[i];
  1721. SDE_EVT32(DRMID(&sde_enc->base), intf_mode,
  1722. msm_is_mode_seamless_poms(adj_mode),
  1723. SDE_EVTLOG_FUNC_CASE2);
  1724. SDE_DEBUG_ENC(sde_enc, "switch to command physical encoder\n");
  1725. }
  1726. }
  1727. static struct drm_connector *_sde_encoder_get_connector(
  1728. struct drm_device *dev, struct drm_encoder *drm_enc)
  1729. {
  1730. struct drm_connector_list_iter conn_iter;
  1731. struct drm_connector *conn = NULL, *conn_search;
  1732. drm_connector_list_iter_begin(dev, &conn_iter);
  1733. drm_for_each_connector_iter(conn_search, &conn_iter) {
  1734. if (conn_search->encoder == drm_enc) {
  1735. conn = conn_search;
  1736. break;
  1737. }
  1738. }
  1739. drm_connector_list_iter_end(&conn_iter);
  1740. return conn;
  1741. }
  1742. static void _sde_encoder_virt_populate_hw_res(struct drm_encoder *drm_enc)
  1743. {
  1744. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1745. struct sde_kms *sde_kms = sde_encoder_get_kms(drm_enc);
  1746. struct sde_rm_hw_iter pp_iter, qdss_iter;
  1747. struct sde_rm_hw_iter dsc_iter, vdc_iter;
  1748. struct sde_rm_hw_request request_hw;
  1749. int i;
  1750. sde_rm_init_hw_iter(&pp_iter, drm_enc->base.id, SDE_HW_BLK_PINGPONG);
  1751. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1752. sde_enc->hw_pp[i] = NULL;
  1753. if (!sde_rm_get_hw(&sde_kms->rm, &pp_iter))
  1754. break;
  1755. sde_enc->hw_pp[i] = (struct sde_hw_pingpong *) pp_iter.hw;
  1756. }
  1757. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1758. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1759. if (phys) {
  1760. sde_rm_init_hw_iter(&qdss_iter, drm_enc->base.id,
  1761. SDE_HW_BLK_QDSS);
  1762. for (i = 0; i < QDSS_MAX; i++) {
  1763. if (sde_rm_get_hw(&sde_kms->rm, &qdss_iter)) {
  1764. phys->hw_qdss =
  1765. (struct sde_hw_qdss *)qdss_iter.hw;
  1766. break;
  1767. }
  1768. }
  1769. }
  1770. }
  1771. sde_rm_init_hw_iter(&dsc_iter, drm_enc->base.id, SDE_HW_BLK_DSC);
  1772. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1773. sde_enc->hw_dsc[i] = NULL;
  1774. if (!sde_rm_get_hw(&sde_kms->rm, &dsc_iter))
  1775. break;
  1776. sde_enc->hw_dsc[i] = (struct sde_hw_dsc *) dsc_iter.hw;
  1777. }
  1778. sde_rm_init_hw_iter(&vdc_iter, drm_enc->base.id, SDE_HW_BLK_VDC);
  1779. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1780. sde_enc->hw_vdc[i] = NULL;
  1781. if (!sde_rm_get_hw(&sde_kms->rm, &vdc_iter))
  1782. break;
  1783. sde_enc->hw_vdc[i] = (struct sde_hw_vdc *) vdc_iter.hw;
  1784. }
  1785. /* Get PP for DSC configuration */
  1786. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1787. struct sde_hw_pingpong *pp = NULL;
  1788. unsigned long features = 0;
  1789. if (!sde_enc->hw_dsc[i])
  1790. continue;
  1791. request_hw.id = sde_enc->hw_dsc[i]->base.id;
  1792. request_hw.type = SDE_HW_BLK_PINGPONG;
  1793. if (!sde_rm_request_hw_blk(&sde_kms->rm, &request_hw))
  1794. break;
  1795. pp = (struct sde_hw_pingpong *) request_hw.hw;
  1796. features = pp->ops.get_hw_caps(pp);
  1797. if (test_bit(SDE_PINGPONG_DSC, &features))
  1798. sde_enc->hw_dsc_pp[i] = pp;
  1799. else
  1800. sde_enc->hw_dsc_pp[i] = NULL;
  1801. }
  1802. }
  1803. static int sde_encoder_virt_modeset_rc(struct drm_encoder *drm_enc,
  1804. struct drm_display_mode *adj_mode, bool pre_modeset)
  1805. {
  1806. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1807. enum sde_intf_mode intf_mode;
  1808. int ret;
  1809. bool is_cmd_mode;
  1810. if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1811. is_cmd_mode = true;
  1812. if (pre_modeset) {
  1813. intf_mode = sde_encoder_get_intf_mode(drm_enc);
  1814. if (msm_is_mode_seamless_dms(adj_mode) ||
  1815. (msm_is_mode_seamless_dyn_clk(adj_mode) &&
  1816. is_cmd_mode)) {
  1817. /* restore resource state before releasing them */
  1818. ret = sde_encoder_resource_control(drm_enc,
  1819. SDE_ENC_RC_EVENT_PRE_MODESET);
  1820. if (ret) {
  1821. SDE_ERROR_ENC(sde_enc,
  1822. "sde resource control failed: %d\n",
  1823. ret);
  1824. return ret;
  1825. }
  1826. /*
  1827. * Disable dce before switching the mode and after pre-
  1828. * modeset to guarantee previous kickoff has finished.
  1829. */
  1830. sde_encoder_dce_disable(sde_enc);
  1831. } else if (msm_is_mode_seamless_poms(adj_mode)) {
  1832. _sde_encoder_modeset_helper_locked(drm_enc,
  1833. SDE_ENC_RC_EVENT_PRE_MODESET);
  1834. sde_encoder_virt_mode_switch(drm_enc, intf_mode,
  1835. adj_mode);
  1836. }
  1837. } else {
  1838. if (msm_is_mode_seamless_dms(adj_mode) ||
  1839. (msm_is_mode_seamless_dyn_clk(adj_mode) &&
  1840. is_cmd_mode))
  1841. sde_encoder_resource_control(&sde_enc->base,
  1842. SDE_ENC_RC_EVENT_POST_MODESET);
  1843. else if (msm_is_mode_seamless_poms(adj_mode))
  1844. _sde_encoder_modeset_helper_locked(drm_enc,
  1845. SDE_ENC_RC_EVENT_POST_MODESET);
  1846. }
  1847. return 0;
  1848. }
  1849. static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc,
  1850. struct drm_display_mode *mode,
  1851. struct drm_display_mode *adj_mode)
  1852. {
  1853. struct sde_encoder_virt *sde_enc;
  1854. struct sde_kms *sde_kms;
  1855. struct drm_connector *conn;
  1856. int i = 0, ret;
  1857. if (!drm_enc) {
  1858. SDE_ERROR("invalid encoder\n");
  1859. return;
  1860. }
  1861. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  1862. SDE_ERROR("power resource is not enabled\n");
  1863. return;
  1864. }
  1865. sde_kms = sde_encoder_get_kms(drm_enc);
  1866. if (!sde_kms)
  1867. return;
  1868. sde_enc = to_sde_encoder_virt(drm_enc);
  1869. SDE_DEBUG_ENC(sde_enc, "\n");
  1870. SDE_EVT32(DRMID(drm_enc));
  1871. /*
  1872. * cache the crtc in sde_enc on enable for duration of use case
  1873. * for correctly servicing asynchronous irq events and timers
  1874. */
  1875. if (!drm_enc->crtc) {
  1876. SDE_ERROR("invalid crtc\n");
  1877. return;
  1878. }
  1879. sde_enc->crtc = drm_enc->crtc;
  1880. sde_crtc_set_qos_dirty(drm_enc->crtc);
  1881. /* get and store the mode_info */
  1882. conn = _sde_encoder_get_connector(sde_kms->dev, drm_enc);
  1883. if (!conn) {
  1884. SDE_ERROR_ENC(sde_enc, "failed to find attached connector\n");
  1885. return;
  1886. } else if (!conn->state) {
  1887. SDE_ERROR_ENC(sde_enc, "invalid connector state\n");
  1888. return;
  1889. }
  1890. sde_connector_state_get_mode_info(conn->state, &sde_enc->mode_info);
  1891. sde_encoder_dce_set_bpp(sde_enc->mode_info, sde_enc->crtc);
  1892. /* release resources before seamless mode change */
  1893. ret = sde_encoder_virt_modeset_rc(drm_enc, adj_mode, true);
  1894. if (ret)
  1895. return;
  1896. /* reserve dynamic resources now, indicating non test-only */
  1897. ret = sde_rm_reserve(&sde_kms->rm, drm_enc, drm_enc->crtc->state,
  1898. conn->state, false);
  1899. if (ret) {
  1900. SDE_ERROR_ENC(sde_enc,
  1901. "failed to reserve hw resources, %d\n", ret);
  1902. return;
  1903. }
  1904. /* assign the reserved HW blocks to this encoder */
  1905. _sde_encoder_virt_populate_hw_res(drm_enc);
  1906. /* perform mode_set on phys_encs */
  1907. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1908. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1909. if (phys) {
  1910. if (!sde_enc->hw_pp[i] && sde_enc->topology.num_intf) {
  1911. SDE_ERROR_ENC(sde_enc,
  1912. "invalid pingpong block for the encoder\n");
  1913. return;
  1914. }
  1915. phys->hw_pp = sde_enc->hw_pp[i];
  1916. phys->connector = conn->state->connector;
  1917. if (phys->ops.mode_set)
  1918. phys->ops.mode_set(phys, mode, adj_mode);
  1919. }
  1920. }
  1921. /* update resources after seamless mode change */
  1922. sde_encoder_virt_modeset_rc(drm_enc, adj_mode, false);
  1923. }
  1924. void sde_encoder_control_te(struct drm_encoder *drm_enc, bool enable)
  1925. {
  1926. struct sde_encoder_virt *sde_enc;
  1927. struct sde_encoder_phys *phys;
  1928. int i;
  1929. if (!drm_enc) {
  1930. SDE_ERROR("invalid parameters\n");
  1931. return;
  1932. }
  1933. sde_enc = to_sde_encoder_virt(drm_enc);
  1934. if (!sde_enc) {
  1935. SDE_ERROR("invalid sde encoder\n");
  1936. return;
  1937. }
  1938. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1939. phys = sde_enc->phys_encs[i];
  1940. if (phys && phys->ops.control_te)
  1941. phys->ops.control_te(phys, enable);
  1942. }
  1943. }
  1944. static int _sde_encoder_input_connect(struct input_handler *handler,
  1945. struct input_dev *dev, const struct input_device_id *id)
  1946. {
  1947. struct input_handle *handle;
  1948. int rc = 0;
  1949. handle = kzalloc(sizeof(*handle), GFP_KERNEL);
  1950. if (!handle)
  1951. return -ENOMEM;
  1952. handle->dev = dev;
  1953. handle->handler = handler;
  1954. handle->name = handler->name;
  1955. rc = input_register_handle(handle);
  1956. if (rc) {
  1957. pr_err("failed to register input handle\n");
  1958. goto error;
  1959. }
  1960. rc = input_open_device(handle);
  1961. if (rc) {
  1962. pr_err("failed to open input device\n");
  1963. goto error_unregister;
  1964. }
  1965. return 0;
  1966. error_unregister:
  1967. input_unregister_handle(handle);
  1968. error:
  1969. kfree(handle);
  1970. return rc;
  1971. }
  1972. static void _sde_encoder_input_disconnect(struct input_handle *handle)
  1973. {
  1974. input_close_device(handle);
  1975. input_unregister_handle(handle);
  1976. kfree(handle);
  1977. }
  1978. /**
  1979. * Structure for specifying event parameters on which to receive callbacks.
  1980. * This structure will trigger a callback in case of a touch event (specified by
  1981. * EV_ABS) where there is a change in X and Y coordinates,
  1982. */
  1983. static const struct input_device_id sde_input_ids[] = {
  1984. {
  1985. .flags = INPUT_DEVICE_ID_MATCH_EVBIT,
  1986. .evbit = { BIT_MASK(EV_ABS) },
  1987. .absbit = { [BIT_WORD(ABS_MT_POSITION_X)] =
  1988. BIT_MASK(ABS_MT_POSITION_X) |
  1989. BIT_MASK(ABS_MT_POSITION_Y) },
  1990. },
  1991. { },
  1992. };
  1993. static void _sde_encoder_input_handler_register(
  1994. struct drm_encoder *drm_enc)
  1995. {
  1996. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1997. int rc;
  1998. if (!sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1999. return;
  2000. if (sde_enc->input_handler && !sde_enc->input_handler->private) {
  2001. sde_enc->input_handler->private = sde_enc;
  2002. /* register input handler if not already registered */
  2003. rc = input_register_handler(sde_enc->input_handler);
  2004. if (rc) {
  2005. SDE_ERROR("input_handler_register failed, rc= %d\n",
  2006. rc);
  2007. kfree(sde_enc->input_handler);
  2008. }
  2009. }
  2010. }
  2011. static void _sde_encoder_input_handler_unregister(
  2012. struct drm_encoder *drm_enc)
  2013. {
  2014. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2015. if (!sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  2016. return;
  2017. if (sde_enc->input_handler && sde_enc->input_handler->private) {
  2018. input_unregister_handler(sde_enc->input_handler);
  2019. sde_enc->input_handler->private = NULL;
  2020. }
  2021. }
  2022. static int _sde_encoder_input_handler(
  2023. struct sde_encoder_virt *sde_enc)
  2024. {
  2025. struct input_handler *input_handler = NULL;
  2026. int rc = 0;
  2027. if (sde_enc->input_handler) {
  2028. SDE_ERROR_ENC(sde_enc,
  2029. "input_handle is active. unexpected\n");
  2030. return -EINVAL;
  2031. }
  2032. input_handler = kzalloc(sizeof(*sde_enc->input_handler), GFP_KERNEL);
  2033. if (!input_handler)
  2034. return -ENOMEM;
  2035. input_handler->event = sde_encoder_input_event_handler;
  2036. input_handler->connect = _sde_encoder_input_connect;
  2037. input_handler->disconnect = _sde_encoder_input_disconnect;
  2038. input_handler->name = "sde";
  2039. input_handler->id_table = sde_input_ids;
  2040. sde_enc->input_handler = input_handler;
  2041. return rc;
  2042. }
  2043. static void _sde_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
  2044. {
  2045. struct sde_encoder_virt *sde_enc = NULL;
  2046. struct sde_kms *sde_kms;
  2047. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  2048. SDE_ERROR("invalid parameters\n");
  2049. return;
  2050. }
  2051. sde_kms = sde_encoder_get_kms(drm_enc);
  2052. if (!sde_kms)
  2053. return;
  2054. sde_enc = to_sde_encoder_virt(drm_enc);
  2055. if (!sde_enc || !sde_enc->cur_master) {
  2056. SDE_DEBUG("invalid sde encoder/master\n");
  2057. return;
  2058. }
  2059. if (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DisplayPort &&
  2060. sde_enc->cur_master->hw_mdptop &&
  2061. sde_enc->cur_master->hw_mdptop->ops.intf_audio_select)
  2062. sde_enc->cur_master->hw_mdptop->ops.intf_audio_select(
  2063. sde_enc->cur_master->hw_mdptop);
  2064. if (sde_enc->cur_master->hw_mdptop &&
  2065. sde_enc->cur_master->hw_mdptop->ops.reset_ubwc)
  2066. sde_enc->cur_master->hw_mdptop->ops.reset_ubwc(
  2067. sde_enc->cur_master->hw_mdptop,
  2068. sde_kms->catalog);
  2069. if (sde_enc->cur_master->hw_ctl &&
  2070. sde_enc->cur_master->hw_ctl->ops.setup_intf_cfg_v1 &&
  2071. !sde_enc->cur_master->cont_splash_enabled)
  2072. sde_enc->cur_master->hw_ctl->ops.setup_intf_cfg_v1(
  2073. sde_enc->cur_master->hw_ctl,
  2074. &sde_enc->cur_master->intf_cfg_v1);
  2075. _sde_encoder_update_vsync_source(sde_enc, &sde_enc->disp_info, false);
  2076. sde_encoder_control_te(drm_enc, true);
  2077. memset(&sde_enc->prv_conn_roi, 0, sizeof(sde_enc->prv_conn_roi));
  2078. memset(&sde_enc->cur_conn_roi, 0, sizeof(sde_enc->cur_conn_roi));
  2079. }
  2080. static void _sde_encoder_setup_dither(struct sde_encoder_phys *phys)
  2081. {
  2082. void *dither_cfg = NULL;
  2083. int ret = 0, i = 0;
  2084. size_t len = 0;
  2085. enum sde_rm_topology_name topology;
  2086. struct drm_encoder *drm_enc;
  2087. struct msm_display_dsc_info *dsc = NULL;
  2088. struct sde_encoder_virt *sde_enc;
  2089. struct sde_hw_pingpong *hw_pp;
  2090. u32 bpp, bpc;
  2091. if (!phys || !phys->connector || !phys->hw_pp ||
  2092. !phys->hw_pp->ops.setup_dither || !phys->parent)
  2093. return;
  2094. topology = sde_connector_get_topology_name(phys->connector);
  2095. if ((topology == SDE_RM_TOPOLOGY_PPSPLIT) &&
  2096. (phys->split_role == ENC_ROLE_SLAVE))
  2097. return;
  2098. drm_enc = phys->parent;
  2099. sde_enc = to_sde_encoder_virt(drm_enc);
  2100. dsc = &sde_enc->mode_info.comp_info.dsc_info;
  2101. bpc = dsc->config.bits_per_component;
  2102. bpp = dsc->config.bits_per_pixel;
  2103. /* disable dither for 10 bpp or 10bpc dsc config */
  2104. if (bpp == 10 || bpc == 10) {
  2105. phys->hw_pp->ops.setup_dither(phys->hw_pp, NULL, 0);
  2106. return;
  2107. }
  2108. ret = sde_connector_get_dither_cfg(phys->connector,
  2109. phys->connector->state, &dither_cfg,
  2110. &len, sde_enc->idle_pc_restore);
  2111. /* skip reg writes when return values are invalid or no data */
  2112. if (ret && ret == -ENODATA)
  2113. return;
  2114. if (TOPOLOGY_DUALPIPE_MERGE_MODE(topology)) {
  2115. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  2116. hw_pp = sde_enc->hw_pp[i];
  2117. phys->hw_pp->ops.setup_dither(hw_pp,
  2118. dither_cfg, len);
  2119. }
  2120. } else {
  2121. phys->hw_pp->ops.setup_dither(phys->hw_pp,
  2122. dither_cfg, len);
  2123. }
  2124. }
  2125. void sde_encoder_virt_restore(struct drm_encoder *drm_enc)
  2126. {
  2127. struct sde_encoder_virt *sde_enc = NULL;
  2128. int i;
  2129. if (!drm_enc) {
  2130. SDE_ERROR("invalid encoder\n");
  2131. return;
  2132. }
  2133. sde_enc = to_sde_encoder_virt(drm_enc);
  2134. if (!sde_enc->cur_master) {
  2135. SDE_DEBUG("virt encoder has no master\n");
  2136. return;
  2137. }
  2138. memset(&sde_enc->cur_master->intf_cfg_v1, 0,
  2139. sizeof(sde_enc->cur_master->intf_cfg_v1));
  2140. sde_enc->idle_pc_restore = true;
  2141. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2142. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2143. if (!phys)
  2144. continue;
  2145. if (phys->hw_ctl && phys->hw_ctl->ops.clear_pending_flush)
  2146. phys->hw_ctl->ops.clear_pending_flush(phys->hw_ctl);
  2147. if ((phys != sde_enc->cur_master) && phys->ops.restore)
  2148. phys->ops.restore(phys);
  2149. _sde_encoder_setup_dither(phys);
  2150. }
  2151. if (sde_enc->cur_master->ops.restore)
  2152. sde_enc->cur_master->ops.restore(sde_enc->cur_master);
  2153. _sde_encoder_virt_enable_helper(drm_enc);
  2154. }
  2155. static void sde_encoder_off_work(struct kthread_work *work)
  2156. {
  2157. struct sde_encoder_virt *sde_enc = container_of(work,
  2158. struct sde_encoder_virt, delayed_off_work.work);
  2159. struct drm_encoder *drm_enc;
  2160. if (!sde_enc) {
  2161. SDE_ERROR("invalid sde encoder\n");
  2162. return;
  2163. }
  2164. drm_enc = &sde_enc->base;
  2165. SDE_ATRACE_BEGIN("sde_encoder_off_work");
  2166. sde_encoder_idle_request(drm_enc);
  2167. SDE_ATRACE_END("sde_encoder_off_work");
  2168. }
  2169. static void sde_encoder_virt_enable(struct drm_encoder *drm_enc)
  2170. {
  2171. struct sde_encoder_virt *sde_enc = NULL;
  2172. int i, ret = 0;
  2173. struct msm_compression_info *comp_info = NULL;
  2174. struct drm_display_mode *cur_mode = NULL;
  2175. struct msm_display_info *disp_info;
  2176. if (!drm_enc) {
  2177. SDE_ERROR("invalid encoder\n");
  2178. return;
  2179. }
  2180. sde_enc = to_sde_encoder_virt(drm_enc);
  2181. disp_info = &sde_enc->disp_info;
  2182. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  2183. SDE_ERROR("power resource is not enabled\n");
  2184. return;
  2185. }
  2186. if (drm_enc->crtc && !sde_enc->crtc)
  2187. sde_enc->crtc = drm_enc->crtc;
  2188. comp_info = &sde_enc->mode_info.comp_info;
  2189. cur_mode = &sde_enc->base.crtc->state->adjusted_mode;
  2190. SDE_DEBUG_ENC(sde_enc, "\n");
  2191. SDE_EVT32(DRMID(drm_enc), cur_mode->hdisplay, cur_mode->vdisplay);
  2192. sde_enc->cur_master = NULL;
  2193. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2194. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2195. if (phys && phys->ops.is_master && phys->ops.is_master(phys)) {
  2196. SDE_DEBUG_ENC(sde_enc, "master is now idx %d\n", i);
  2197. sde_enc->cur_master = phys;
  2198. break;
  2199. }
  2200. }
  2201. if (!sde_enc->cur_master) {
  2202. SDE_ERROR("virt encoder has no master! num_phys %d\n", i);
  2203. return;
  2204. }
  2205. _sde_encoder_input_handler_register(drm_enc);
  2206. if (!(msm_is_mode_seamless_vrr(cur_mode)
  2207. || msm_is_mode_seamless_dms(cur_mode)
  2208. || msm_is_mode_seamless_dyn_clk(cur_mode)))
  2209. kthread_init_delayed_work(&sde_enc->delayed_off_work,
  2210. sde_encoder_off_work);
  2211. ret = sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_KICKOFF);
  2212. if (ret) {
  2213. SDE_ERROR_ENC(sde_enc, "sde resource control failed: %d\n",
  2214. ret);
  2215. return;
  2216. }
  2217. memset(&sde_enc->cur_master->intf_cfg_v1, 0,
  2218. sizeof(sde_enc->cur_master->intf_cfg_v1));
  2219. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2220. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2221. if (!phys)
  2222. continue;
  2223. phys->comp_type = comp_info->comp_type;
  2224. phys->comp_ratio = comp_info->comp_ratio;
  2225. phys->frame_trigger_mode = sde_enc->frame_trigger_mode;
  2226. phys->poms_align_vsync = disp_info->poms_align_vsync;
  2227. if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC) {
  2228. phys->dsc_extra_pclk_cycle_cnt =
  2229. comp_info->dsc_info.pclk_per_line;
  2230. phys->dsc_extra_disp_width =
  2231. comp_info->dsc_info.extra_width;
  2232. phys->dce_bytes_per_line =
  2233. comp_info->dsc_info.bytes_per_pkt *
  2234. comp_info->dsc_info.pkt_per_line;
  2235. } else if (phys->comp_type == MSM_DISPLAY_COMPRESSION_VDC) {
  2236. phys->dce_bytes_per_line =
  2237. comp_info->vdc_info.bytes_per_pkt *
  2238. comp_info->vdc_info.pkt_per_line;
  2239. }
  2240. if (phys != sde_enc->cur_master) {
  2241. /**
  2242. * on DMS request, the encoder will be enabled
  2243. * already. Invoke restore to reconfigure the
  2244. * new mode.
  2245. */
  2246. if ((msm_is_mode_seamless_dms(cur_mode) ||
  2247. msm_is_mode_seamless_dyn_clk(cur_mode)) &&
  2248. phys->ops.restore)
  2249. phys->ops.restore(phys);
  2250. else if (phys->ops.enable)
  2251. phys->ops.enable(phys);
  2252. }
  2253. if (sde_enc->misr_enable && phys->ops.setup_misr &&
  2254. (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE)))
  2255. phys->ops.setup_misr(phys, true,
  2256. sde_enc->misr_frame_count);
  2257. }
  2258. if ((msm_is_mode_seamless_dms(cur_mode) ||
  2259. msm_is_mode_seamless_dyn_clk(cur_mode)) &&
  2260. sde_enc->cur_master->ops.restore)
  2261. sde_enc->cur_master->ops.restore(sde_enc->cur_master);
  2262. else if (sde_enc->cur_master->ops.enable)
  2263. sde_enc->cur_master->ops.enable(sde_enc->cur_master);
  2264. _sde_encoder_virt_enable_helper(drm_enc);
  2265. }
  2266. static void sde_encoder_virt_disable(struct drm_encoder *drm_enc)
  2267. {
  2268. struct sde_encoder_virt *sde_enc = NULL;
  2269. struct sde_kms *sde_kms;
  2270. enum sde_intf_mode intf_mode;
  2271. int i = 0;
  2272. if (!drm_enc) {
  2273. SDE_ERROR("invalid encoder\n");
  2274. return;
  2275. } else if (!drm_enc->dev) {
  2276. SDE_ERROR("invalid dev\n");
  2277. return;
  2278. } else if (!drm_enc->dev->dev_private) {
  2279. SDE_ERROR("invalid dev_private\n");
  2280. return;
  2281. }
  2282. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  2283. SDE_ERROR("power resource is not enabled\n");
  2284. return;
  2285. }
  2286. sde_enc = to_sde_encoder_virt(drm_enc);
  2287. SDE_DEBUG_ENC(sde_enc, "\n");
  2288. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  2289. if (!sde_kms)
  2290. return;
  2291. intf_mode = sde_encoder_get_intf_mode(drm_enc);
  2292. SDE_EVT32(DRMID(drm_enc));
  2293. /* wait for idle */
  2294. sde_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
  2295. _sde_encoder_input_handler_unregister(drm_enc);
  2296. /*
  2297. * For primary command mode and video mode encoders, execute the
  2298. * resource control pre-stop operations before the physical encoders
  2299. * are disabled, to allow the rsc to transition its states properly.
  2300. *
  2301. * For other encoder types, rsc should not be enabled until after
  2302. * they have been fully disabled, so delay the pre-stop operations
  2303. * until after the physical disable calls have returned.
  2304. */
  2305. if (sde_enc->disp_info.display_type == SDE_CONNECTOR_PRIMARY &&
  2306. (intf_mode == INTF_MODE_CMD || intf_mode == INTF_MODE_VIDEO)) {
  2307. sde_encoder_resource_control(drm_enc,
  2308. SDE_ENC_RC_EVENT_PRE_STOP);
  2309. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2310. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2311. if (phys && phys->ops.disable)
  2312. phys->ops.disable(phys);
  2313. }
  2314. } else {
  2315. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2316. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2317. if (phys && phys->ops.disable)
  2318. phys->ops.disable(phys);
  2319. }
  2320. sde_encoder_resource_control(drm_enc,
  2321. SDE_ENC_RC_EVENT_PRE_STOP);
  2322. }
  2323. /*
  2324. * disable dce after the transfer is complete (for command mode)
  2325. * and after physical encoder is disabled, to make sure timing
  2326. * engine is already disabled (for video mode).
  2327. */
  2328. sde_encoder_dce_disable(sde_enc);
  2329. sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_STOP);
  2330. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2331. if (sde_enc->phys_encs[i]) {
  2332. sde_enc->phys_encs[i]->cont_splash_enabled = false;
  2333. sde_enc->phys_encs[i]->connector = NULL;
  2334. }
  2335. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  2336. }
  2337. sde_enc->cur_master = NULL;
  2338. /*
  2339. * clear the cached crtc in sde_enc on use case finish, after all the
  2340. * outstanding events and timers have been completed
  2341. */
  2342. sde_enc->crtc = NULL;
  2343. memset(&sde_enc->mode_info, 0, sizeof(sde_enc->mode_info));
  2344. SDE_DEBUG_ENC(sde_enc, "encoder disabled\n");
  2345. sde_rm_release(&sde_kms->rm, drm_enc, false);
  2346. }
  2347. void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,
  2348. struct sde_encoder_phys_wb *wb_enc)
  2349. {
  2350. struct sde_encoder_virt *sde_enc;
  2351. phys_enc->hw_ctl->ops.reset(phys_enc->hw_ctl);
  2352. sde_encoder_helper_reset_mixers(phys_enc, NULL);
  2353. if (wb_enc) {
  2354. if (wb_enc->hw_wb->ops.bind_pingpong_blk) {
  2355. wb_enc->hw_wb->ops.bind_pingpong_blk(wb_enc->hw_wb,
  2356. false, phys_enc->hw_pp->idx);
  2357. if (phys_enc->hw_ctl->ops.update_bitmask)
  2358. phys_enc->hw_ctl->ops.update_bitmask(
  2359. phys_enc->hw_ctl,
  2360. SDE_HW_FLUSH_WB,
  2361. wb_enc->hw_wb->idx, true);
  2362. }
  2363. } else {
  2364. if (phys_enc->hw_intf->ops.bind_pingpong_blk) {
  2365. phys_enc->hw_intf->ops.bind_pingpong_blk(
  2366. phys_enc->hw_intf, false,
  2367. phys_enc->hw_pp->idx);
  2368. if (phys_enc->hw_ctl->ops.update_bitmask)
  2369. phys_enc->hw_ctl->ops.update_bitmask(
  2370. phys_enc->hw_ctl,
  2371. SDE_HW_FLUSH_INTF,
  2372. phys_enc->hw_intf->idx, true);
  2373. }
  2374. }
  2375. if (phys_enc->hw_pp && phys_enc->hw_pp->ops.reset_3d_mode) {
  2376. phys_enc->hw_pp->ops.reset_3d_mode(phys_enc->hw_pp);
  2377. if (phys_enc->hw_ctl->ops.update_bitmask &&
  2378. phys_enc->hw_pp->merge_3d)
  2379. phys_enc->hw_ctl->ops.update_bitmask(
  2380. phys_enc->hw_ctl, SDE_HW_FLUSH_MERGE_3D,
  2381. phys_enc->hw_pp->merge_3d->idx, true);
  2382. }
  2383. if (phys_enc->hw_cdm && phys_enc->hw_cdm->ops.bind_pingpong_blk &&
  2384. phys_enc->hw_pp) {
  2385. phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm,
  2386. false, phys_enc->hw_pp->idx);
  2387. if (phys_enc->hw_ctl->ops.update_bitmask)
  2388. phys_enc->hw_ctl->ops.update_bitmask(
  2389. phys_enc->hw_ctl, SDE_HW_FLUSH_CDM,
  2390. phys_enc->hw_cdm->idx, true);
  2391. }
  2392. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  2393. if (phys_enc == sde_enc->cur_master && phys_enc->hw_pp &&
  2394. phys_enc->hw_ctl->ops.reset_post_disable)
  2395. phys_enc->hw_ctl->ops.reset_post_disable(
  2396. phys_enc->hw_ctl, &phys_enc->intf_cfg_v1,
  2397. phys_enc->hw_pp->merge_3d ?
  2398. phys_enc->hw_pp->merge_3d->idx : 0);
  2399. phys_enc->hw_ctl->ops.trigger_flush(phys_enc->hw_ctl);
  2400. phys_enc->hw_ctl->ops.trigger_start(phys_enc->hw_ctl);
  2401. }
  2402. static enum sde_intf sde_encoder_get_intf(struct sde_mdss_cfg *catalog,
  2403. enum sde_intf_type type, u32 controller_id)
  2404. {
  2405. int i = 0;
  2406. for (i = 0; i < catalog->intf_count; i++) {
  2407. if (catalog->intf[i].type == type
  2408. && catalog->intf[i].controller_id == controller_id) {
  2409. return catalog->intf[i].id;
  2410. }
  2411. }
  2412. return INTF_MAX;
  2413. }
  2414. static enum sde_wb sde_encoder_get_wb(struct sde_mdss_cfg *catalog,
  2415. enum sde_intf_type type, u32 controller_id)
  2416. {
  2417. if (controller_id < catalog->wb_count)
  2418. return catalog->wb[controller_id].id;
  2419. return WB_MAX;
  2420. }
  2421. void sde_encoder_perf_uidle_status(struct sde_kms *sde_kms,
  2422. struct drm_crtc *crtc)
  2423. {
  2424. struct sde_hw_uidle *uidle;
  2425. struct sde_uidle_cntr cntr;
  2426. struct sde_uidle_status status;
  2427. if (!sde_kms || !crtc || !sde_kms->hw_uidle) {
  2428. pr_err("invalid params %d %d\n",
  2429. !sde_kms, !crtc);
  2430. return;
  2431. }
  2432. /* check if perf counters are enabled and setup */
  2433. if (!sde_kms->catalog->uidle_cfg.perf_cntr_en)
  2434. return;
  2435. uidle = sde_kms->hw_uidle;
  2436. if ((sde_kms->catalog->uidle_cfg.debugfs_perf & SDE_PERF_UIDLE_STATUS)
  2437. && uidle->ops.uidle_get_status) {
  2438. uidle->ops.uidle_get_status(uidle, &status);
  2439. trace_sde_perf_uidle_status(
  2440. crtc->base.id,
  2441. status.uidle_danger_status_0,
  2442. status.uidle_danger_status_1,
  2443. status.uidle_safe_status_0,
  2444. status.uidle_safe_status_1,
  2445. status.uidle_idle_status_0,
  2446. status.uidle_idle_status_1,
  2447. status.uidle_fal_status_0,
  2448. status.uidle_fal_status_1,
  2449. status.uidle_status,
  2450. status.uidle_en_fal10);
  2451. }
  2452. if ((sde_kms->catalog->uidle_cfg.debugfs_perf & SDE_PERF_UIDLE_CNT)
  2453. && uidle->ops.uidle_get_cntr) {
  2454. uidle->ops.uidle_get_cntr(uidle, &cntr);
  2455. trace_sde_perf_uidle_cntr(
  2456. crtc->base.id,
  2457. cntr.fal1_gate_cntr,
  2458. cntr.fal10_gate_cntr,
  2459. cntr.fal_wait_gate_cntr,
  2460. cntr.fal1_num_transitions_cntr,
  2461. cntr.fal10_num_transitions_cntr,
  2462. cntr.min_gate_cntr,
  2463. cntr.max_gate_cntr);
  2464. }
  2465. }
  2466. static void sde_encoder_vblank_callback(struct drm_encoder *drm_enc,
  2467. struct sde_encoder_phys *phy_enc)
  2468. {
  2469. struct sde_encoder_virt *sde_enc = NULL;
  2470. unsigned long lock_flags;
  2471. if (!drm_enc || !phy_enc)
  2472. return;
  2473. SDE_ATRACE_BEGIN("encoder_vblank_callback");
  2474. sde_enc = to_sde_encoder_virt(drm_enc);
  2475. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2476. if (sde_enc->crtc_vblank_cb)
  2477. sde_enc->crtc_vblank_cb(sde_enc->crtc_vblank_cb_data);
  2478. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2479. if (phy_enc->sde_kms &&
  2480. phy_enc->sde_kms->catalog->uidle_cfg.debugfs_perf)
  2481. sde_encoder_perf_uidle_status(phy_enc->sde_kms, sde_enc->crtc);
  2482. atomic_inc(&phy_enc->vsync_cnt);
  2483. SDE_ATRACE_END("encoder_vblank_callback");
  2484. }
  2485. static void sde_encoder_underrun_callback(struct drm_encoder *drm_enc,
  2486. struct sde_encoder_phys *phy_enc)
  2487. {
  2488. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2489. if (!phy_enc)
  2490. return;
  2491. SDE_ATRACE_BEGIN("encoder_underrun_callback");
  2492. atomic_inc(&phy_enc->underrun_cnt);
  2493. SDE_EVT32(DRMID(drm_enc), atomic_read(&phy_enc->underrun_cnt));
  2494. if (sde_enc->cur_master->ops.get_underrun_line_count)
  2495. sde_enc->cur_master->ops.get_underrun_line_count(
  2496. sde_enc->cur_master);
  2497. trace_sde_encoder_underrun(DRMID(drm_enc),
  2498. atomic_read(&phy_enc->underrun_cnt));
  2499. SDE_DBG_CTRL("stop_ftrace");
  2500. SDE_DBG_CTRL("panic_underrun");
  2501. SDE_ATRACE_END("encoder_underrun_callback");
  2502. }
  2503. void sde_encoder_register_vblank_callback(struct drm_encoder *drm_enc,
  2504. void (*vbl_cb)(void *), void *vbl_data)
  2505. {
  2506. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2507. unsigned long lock_flags;
  2508. bool enable;
  2509. int i;
  2510. enable = vbl_cb ? true : false;
  2511. if (!drm_enc) {
  2512. SDE_ERROR("invalid encoder\n");
  2513. return;
  2514. }
  2515. SDE_DEBUG_ENC(sde_enc, "\n");
  2516. SDE_EVT32(DRMID(drm_enc), enable);
  2517. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2518. sde_enc->crtc_vblank_cb = vbl_cb;
  2519. sde_enc->crtc_vblank_cb_data = vbl_data;
  2520. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2521. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2522. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2523. if (phys && phys->ops.control_vblank_irq)
  2524. phys->ops.control_vblank_irq(phys, enable);
  2525. }
  2526. sde_enc->vblank_enabled = enable;
  2527. }
  2528. void sde_encoder_register_frame_event_callback(struct drm_encoder *drm_enc,
  2529. void (*frame_event_cb)(void *, u32 event),
  2530. struct drm_crtc *crtc)
  2531. {
  2532. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2533. unsigned long lock_flags;
  2534. bool enable;
  2535. enable = frame_event_cb ? true : false;
  2536. if (!drm_enc) {
  2537. SDE_ERROR("invalid encoder\n");
  2538. return;
  2539. }
  2540. SDE_DEBUG_ENC(sde_enc, "\n");
  2541. SDE_EVT32(DRMID(drm_enc), enable, 0);
  2542. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2543. sde_enc->crtc_frame_event_cb = frame_event_cb;
  2544. sde_enc->crtc_frame_event_cb_data.crtc = crtc;
  2545. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2546. }
  2547. static void sde_encoder_frame_done_callback(
  2548. struct drm_encoder *drm_enc,
  2549. struct sde_encoder_phys *ready_phys, u32 event)
  2550. {
  2551. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2552. unsigned int i;
  2553. bool trigger = true;
  2554. bool is_cmd_mode = false;
  2555. enum sde_rm_topology_name topology = SDE_RM_TOPOLOGY_NONE;
  2556. if (!drm_enc || !sde_enc->cur_master) {
  2557. SDE_ERROR("invalid param: drm_enc %pK, cur_master %pK\n",
  2558. drm_enc, drm_enc ? sde_enc->cur_master : 0);
  2559. return;
  2560. }
  2561. sde_enc->crtc_frame_event_cb_data.connector =
  2562. sde_enc->cur_master->connector;
  2563. if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  2564. is_cmd_mode = true;
  2565. if (event & (SDE_ENCODER_FRAME_EVENT_DONE
  2566. | SDE_ENCODER_FRAME_EVENT_ERROR
  2567. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD) && is_cmd_mode) {
  2568. if (ready_phys->connector)
  2569. topology = sde_connector_get_topology_name(
  2570. ready_phys->connector);
  2571. /* One of the physical encoders has become idle */
  2572. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2573. if (sde_enc->phys_encs[i] == ready_phys) {
  2574. SDE_EVT32_VERBOSE(DRMID(drm_enc), i,
  2575. atomic_read(&sde_enc->frame_done_cnt[i]));
  2576. if (!atomic_add_unless(
  2577. &sde_enc->frame_done_cnt[i], 1, 2)) {
  2578. SDE_EVT32(DRMID(drm_enc), event,
  2579. ready_phys->intf_idx,
  2580. SDE_EVTLOG_ERROR);
  2581. SDE_ERROR_ENC(sde_enc,
  2582. "intf idx:%d, event:%d\n",
  2583. ready_phys->intf_idx, event);
  2584. return;
  2585. }
  2586. }
  2587. if (topology != SDE_RM_TOPOLOGY_PPSPLIT &&
  2588. atomic_read(&sde_enc->frame_done_cnt[i]) == 0)
  2589. trigger = false;
  2590. }
  2591. if (trigger) {
  2592. if (sde_enc->crtc_frame_event_cb)
  2593. sde_enc->crtc_frame_event_cb(
  2594. &sde_enc->crtc_frame_event_cb_data,
  2595. event);
  2596. for (i = 0; i < sde_enc->num_phys_encs; i++)
  2597. atomic_add_unless(&sde_enc->frame_done_cnt[i],
  2598. -1, 0);
  2599. }
  2600. } else if (sde_enc->crtc_frame_event_cb) {
  2601. sde_enc->crtc_frame_event_cb(
  2602. &sde_enc->crtc_frame_event_cb_data, event);
  2603. }
  2604. }
  2605. static void sde_encoder_get_qsync_fps_callback(
  2606. struct drm_encoder *drm_enc,
  2607. u32 *qsync_fps)
  2608. {
  2609. struct msm_display_info *disp_info;
  2610. struct sde_encoder_virt *sde_enc;
  2611. if (!qsync_fps)
  2612. return;
  2613. *qsync_fps = 0;
  2614. if (!drm_enc) {
  2615. SDE_ERROR("invalid drm encoder\n");
  2616. return;
  2617. }
  2618. sde_enc = to_sde_encoder_virt(drm_enc);
  2619. disp_info = &sde_enc->disp_info;
  2620. *qsync_fps = disp_info->qsync_min_fps;
  2621. }
  2622. int sde_encoder_idle_request(struct drm_encoder *drm_enc)
  2623. {
  2624. struct sde_encoder_virt *sde_enc;
  2625. if (!drm_enc) {
  2626. SDE_ERROR("invalid drm encoder\n");
  2627. return -EINVAL;
  2628. }
  2629. sde_enc = to_sde_encoder_virt(drm_enc);
  2630. sde_encoder_resource_control(&sde_enc->base,
  2631. SDE_ENC_RC_EVENT_ENTER_IDLE);
  2632. return 0;
  2633. }
  2634. /**
  2635. * _sde_encoder_trigger_flush - trigger flush for a physical encoder
  2636. * drm_enc: Pointer to drm encoder structure
  2637. * phys: Pointer to physical encoder structure
  2638. * extra_flush: Additional bit mask to include in flush trigger
  2639. */
  2640. static inline void _sde_encoder_trigger_flush(struct drm_encoder *drm_enc,
  2641. struct sde_encoder_phys *phys,
  2642. struct sde_ctl_flush_cfg *extra_flush)
  2643. {
  2644. struct sde_hw_ctl *ctl;
  2645. unsigned long lock_flags;
  2646. struct sde_encoder_virt *sde_enc;
  2647. int pend_ret_fence_cnt;
  2648. struct sde_connector *c_conn;
  2649. if (!drm_enc || !phys) {
  2650. SDE_ERROR("invalid argument(s), drm_enc %d, phys_enc %d\n",
  2651. !drm_enc, !phys);
  2652. return;
  2653. }
  2654. sde_enc = to_sde_encoder_virt(drm_enc);
  2655. c_conn = to_sde_connector(phys->connector);
  2656. if (!phys->hw_pp) {
  2657. SDE_ERROR("invalid pingpong hw\n");
  2658. return;
  2659. }
  2660. ctl = phys->hw_ctl;
  2661. if (!ctl || !phys->ops.trigger_flush) {
  2662. SDE_ERROR("missing ctl/trigger cb\n");
  2663. return;
  2664. }
  2665. if (phys->split_role == ENC_ROLE_SKIP) {
  2666. SDE_DEBUG_ENC(to_sde_encoder_virt(phys->parent),
  2667. "skip flush pp%d ctl%d\n",
  2668. phys->hw_pp->idx - PINGPONG_0,
  2669. ctl->idx - CTL_0);
  2670. return;
  2671. }
  2672. /* update pending counts and trigger kickoff ctl flush atomically */
  2673. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2674. if (phys->ops.is_master && phys->ops.is_master(phys))
  2675. atomic_inc(&phys->pending_retire_fence_cnt);
  2676. pend_ret_fence_cnt = atomic_read(&phys->pending_retire_fence_cnt);
  2677. if (phys->hw_intf && phys->hw_intf->cap->type == INTF_DP &&
  2678. ctl->ops.update_bitmask) {
  2679. /* perform peripheral flush on every frame update for dp dsc */
  2680. if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC &&
  2681. phys->comp_ratio && c_conn->ops.update_pps) {
  2682. c_conn->ops.update_pps(phys->connector, NULL,
  2683. c_conn->display);
  2684. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_PERIPH,
  2685. phys->hw_intf->idx, 1);
  2686. }
  2687. if (sde_enc->dynamic_hdr_updated)
  2688. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_PERIPH,
  2689. phys->hw_intf->idx, 1);
  2690. }
  2691. if ((extra_flush && extra_flush->pending_flush_mask)
  2692. && ctl->ops.update_pending_flush)
  2693. ctl->ops.update_pending_flush(ctl, extra_flush);
  2694. phys->ops.trigger_flush(phys);
  2695. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2696. if (ctl->ops.get_pending_flush) {
  2697. struct sde_ctl_flush_cfg pending_flush = {0,};
  2698. ctl->ops.get_pending_flush(ctl, &pending_flush);
  2699. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0,
  2700. ctl->idx - CTL_0,
  2701. pending_flush.pending_flush_mask,
  2702. pend_ret_fence_cnt);
  2703. } else {
  2704. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0,
  2705. ctl->idx - CTL_0,
  2706. pend_ret_fence_cnt);
  2707. }
  2708. }
  2709. /**
  2710. * _sde_encoder_trigger_start - trigger start for a physical encoder
  2711. * phys: Pointer to physical encoder structure
  2712. */
  2713. static inline void _sde_encoder_trigger_start(struct sde_encoder_phys *phys)
  2714. {
  2715. struct sde_hw_ctl *ctl;
  2716. struct sde_encoder_virt *sde_enc;
  2717. if (!phys) {
  2718. SDE_ERROR("invalid argument(s)\n");
  2719. return;
  2720. }
  2721. if (!phys->hw_pp) {
  2722. SDE_ERROR("invalid pingpong hw\n");
  2723. return;
  2724. }
  2725. if (!phys->parent) {
  2726. SDE_ERROR("invalid parent\n");
  2727. return;
  2728. }
  2729. /* avoid ctrl start for encoder in clone mode */
  2730. if (phys->in_clone_mode)
  2731. return;
  2732. ctl = phys->hw_ctl;
  2733. sde_enc = to_sde_encoder_virt(phys->parent);
  2734. if (phys->split_role == ENC_ROLE_SKIP) {
  2735. SDE_DEBUG_ENC(sde_enc,
  2736. "skip start pp%d ctl%d\n",
  2737. phys->hw_pp->idx - PINGPONG_0,
  2738. ctl->idx - CTL_0);
  2739. return;
  2740. }
  2741. if (phys->ops.trigger_start && phys->enable_state != SDE_ENC_DISABLED)
  2742. phys->ops.trigger_start(phys);
  2743. }
  2744. void sde_encoder_helper_trigger_flush(struct sde_encoder_phys *phys_enc)
  2745. {
  2746. struct sde_hw_ctl *ctl;
  2747. if (!phys_enc) {
  2748. SDE_ERROR("invalid encoder\n");
  2749. return;
  2750. }
  2751. ctl = phys_enc->hw_ctl;
  2752. if (ctl && ctl->ops.trigger_flush)
  2753. ctl->ops.trigger_flush(ctl);
  2754. }
  2755. void sde_encoder_helper_trigger_start(struct sde_encoder_phys *phys_enc)
  2756. {
  2757. struct sde_hw_ctl *ctl;
  2758. if (!phys_enc) {
  2759. SDE_ERROR("invalid encoder\n");
  2760. return;
  2761. }
  2762. ctl = phys_enc->hw_ctl;
  2763. if (ctl && ctl->ops.trigger_start) {
  2764. ctl->ops.trigger_start(ctl);
  2765. SDE_EVT32(DRMID(phys_enc->parent), ctl->idx - CTL_0);
  2766. }
  2767. }
  2768. void sde_encoder_helper_hw_reset(struct sde_encoder_phys *phys_enc)
  2769. {
  2770. struct sde_encoder_virt *sde_enc;
  2771. struct sde_connector *sde_con;
  2772. void *sde_con_disp;
  2773. struct sde_hw_ctl *ctl;
  2774. int rc;
  2775. if (!phys_enc) {
  2776. SDE_ERROR("invalid encoder\n");
  2777. return;
  2778. }
  2779. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  2780. ctl = phys_enc->hw_ctl;
  2781. if (!ctl || !ctl->ops.reset)
  2782. return;
  2783. SDE_DEBUG_ENC(sde_enc, "ctl %d reset\n", ctl->idx);
  2784. SDE_EVT32(DRMID(phys_enc->parent), ctl->idx);
  2785. if (phys_enc->ops.is_master && phys_enc->ops.is_master(phys_enc) &&
  2786. phys_enc->connector) {
  2787. sde_con = to_sde_connector(phys_enc->connector);
  2788. sde_con_disp = sde_connector_get_display(phys_enc->connector);
  2789. if (sde_con->ops.soft_reset) {
  2790. rc = sde_con->ops.soft_reset(sde_con_disp);
  2791. if (rc) {
  2792. SDE_ERROR_ENC(sde_enc,
  2793. "connector soft reset failure\n");
  2794. SDE_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus",
  2795. "panic");
  2796. }
  2797. }
  2798. }
  2799. phys_enc->enable_state = SDE_ENC_ENABLED;
  2800. }
  2801. /**
  2802. * _sde_encoder_kickoff_phys - handle physical encoder kickoff
  2803. * Iterate through the physical encoders and perform consolidated flush
  2804. * and/or control start triggering as needed. This is done in the virtual
  2805. * encoder rather than the individual physical ones in order to handle
  2806. * use cases that require visibility into multiple physical encoders at
  2807. * a time.
  2808. * sde_enc: Pointer to virtual encoder structure
  2809. */
  2810. static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc)
  2811. {
  2812. struct sde_hw_ctl *ctl;
  2813. uint32_t i;
  2814. struct sde_ctl_flush_cfg pending_flush = {0,};
  2815. u32 pending_kickoff_cnt;
  2816. struct msm_drm_private *priv = NULL;
  2817. struct sde_kms *sde_kms = NULL;
  2818. struct sde_crtc_misr_info crtc_misr_info = {false, 0};
  2819. bool is_regdma_blocking = false, is_vid_mode = false;
  2820. if (!sde_enc) {
  2821. SDE_ERROR("invalid encoder\n");
  2822. return;
  2823. }
  2824. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_VIDEO_MODE))
  2825. is_vid_mode = true;
  2826. is_regdma_blocking = (is_vid_mode ||
  2827. _sde_encoder_is_autorefresh_enabled(sde_enc));
  2828. /* don't perform flush/start operations for slave encoders */
  2829. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2830. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2831. enum sde_rm_topology_name topology = SDE_RM_TOPOLOGY_NONE;
  2832. if (!phys || phys->enable_state == SDE_ENC_DISABLED)
  2833. continue;
  2834. ctl = phys->hw_ctl;
  2835. if (!ctl)
  2836. continue;
  2837. if (phys->connector)
  2838. topology = sde_connector_get_topology_name(
  2839. phys->connector);
  2840. if (!phys->ops.needs_single_flush ||
  2841. !phys->ops.needs_single_flush(phys)) {
  2842. if (ctl->ops.reg_dma_flush)
  2843. ctl->ops.reg_dma_flush(ctl, is_regdma_blocking);
  2844. _sde_encoder_trigger_flush(&sde_enc->base, phys, 0x0);
  2845. } else if (ctl->ops.get_pending_flush) {
  2846. ctl->ops.get_pending_flush(ctl, &pending_flush);
  2847. }
  2848. }
  2849. /* for split flush, combine pending flush masks and send to master */
  2850. if (pending_flush.pending_flush_mask && sde_enc->cur_master) {
  2851. ctl = sde_enc->cur_master->hw_ctl;
  2852. if (ctl->ops.reg_dma_flush)
  2853. ctl->ops.reg_dma_flush(ctl, is_regdma_blocking);
  2854. _sde_encoder_trigger_flush(&sde_enc->base, sde_enc->cur_master,
  2855. &pending_flush);
  2856. }
  2857. /* update pending_kickoff_cnt AFTER flush but before trigger start */
  2858. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2859. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2860. if (!phys || phys->enable_state == SDE_ENC_DISABLED)
  2861. continue;
  2862. if (!phys->ops.needs_single_flush ||
  2863. !phys->ops.needs_single_flush(phys)) {
  2864. pending_kickoff_cnt =
  2865. sde_encoder_phys_inc_pending(phys);
  2866. SDE_EVT32(pending_kickoff_cnt, SDE_EVTLOG_FUNC_CASE1);
  2867. } else {
  2868. pending_kickoff_cnt =
  2869. sde_encoder_phys_inc_pending(phys);
  2870. SDE_EVT32(pending_kickoff_cnt,
  2871. pending_flush.pending_flush_mask,
  2872. SDE_EVTLOG_FUNC_CASE2);
  2873. }
  2874. }
  2875. if (sde_enc->misr_enable)
  2876. sde_encoder_misr_configure(&sde_enc->base, true,
  2877. sde_enc->misr_frame_count);
  2878. sde_crtc_get_misr_info(sde_enc->crtc, &crtc_misr_info);
  2879. if (crtc_misr_info.misr_enable)
  2880. sde_crtc_misr_setup(sde_enc->crtc, true,
  2881. crtc_misr_info.misr_frame_count);
  2882. _sde_encoder_trigger_start(sde_enc->cur_master);
  2883. if (sde_enc->elevated_ahb_vote) {
  2884. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  2885. priv = sde_enc->base.dev->dev_private;
  2886. if (sde_kms != NULL) {
  2887. sde_power_scale_reg_bus(&priv->phandle,
  2888. VOTE_INDEX_LOW,
  2889. false);
  2890. }
  2891. sde_enc->elevated_ahb_vote = false;
  2892. }
  2893. }
  2894. static void _sde_encoder_ppsplit_swap_intf_for_right_only_update(
  2895. struct drm_encoder *drm_enc,
  2896. unsigned long *affected_displays,
  2897. int num_active_phys)
  2898. {
  2899. struct sde_encoder_virt *sde_enc;
  2900. struct sde_encoder_phys *master;
  2901. enum sde_rm_topology_name topology;
  2902. bool is_right_only;
  2903. if (!drm_enc || !affected_displays)
  2904. return;
  2905. sde_enc = to_sde_encoder_virt(drm_enc);
  2906. master = sde_enc->cur_master;
  2907. if (!master || !master->connector)
  2908. return;
  2909. topology = sde_connector_get_topology_name(master->connector);
  2910. if (topology != SDE_RM_TOPOLOGY_PPSPLIT)
  2911. return;
  2912. /*
  2913. * For pingpong split, the slave pingpong won't generate IRQs. For
  2914. * right-only updates, we can't swap pingpongs, or simply swap the
  2915. * master/slave assignment, we actually have to swap the interfaces
  2916. * so that the master physical encoder will use a pingpong/interface
  2917. * that generates irqs on which to wait.
  2918. */
  2919. is_right_only = !test_bit(0, affected_displays) &&
  2920. test_bit(1, affected_displays);
  2921. if (is_right_only && !sde_enc->intfs_swapped) {
  2922. /* right-only update swap interfaces */
  2923. swap(sde_enc->phys_encs[0]->intf_idx,
  2924. sde_enc->phys_encs[1]->intf_idx);
  2925. sde_enc->intfs_swapped = true;
  2926. } else if (!is_right_only && sde_enc->intfs_swapped) {
  2927. /* left-only or full update, swap back */
  2928. swap(sde_enc->phys_encs[0]->intf_idx,
  2929. sde_enc->phys_encs[1]->intf_idx);
  2930. sde_enc->intfs_swapped = false;
  2931. }
  2932. SDE_DEBUG_ENC(sde_enc,
  2933. "right_only %d swapped %d phys0->intf%d, phys1->intf%d\n",
  2934. is_right_only, sde_enc->intfs_swapped,
  2935. sde_enc->phys_encs[0]->intf_idx - INTF_0,
  2936. sde_enc->phys_encs[1]->intf_idx - INTF_0);
  2937. SDE_EVT32(DRMID(drm_enc), is_right_only, sde_enc->intfs_swapped,
  2938. sde_enc->phys_encs[0]->intf_idx - INTF_0,
  2939. sde_enc->phys_encs[1]->intf_idx - INTF_0,
  2940. *affected_displays);
  2941. /* ppsplit always uses master since ppslave invalid for irqs*/
  2942. if (num_active_phys == 1)
  2943. *affected_displays = BIT(0);
  2944. }
  2945. static void _sde_encoder_update_master(struct drm_encoder *drm_enc,
  2946. struct sde_encoder_kickoff_params *params)
  2947. {
  2948. struct sde_encoder_virt *sde_enc;
  2949. struct sde_encoder_phys *phys;
  2950. int i, num_active_phys;
  2951. bool master_assigned = false;
  2952. if (!drm_enc || !params)
  2953. return;
  2954. sde_enc = to_sde_encoder_virt(drm_enc);
  2955. if (sde_enc->num_phys_encs <= 1)
  2956. return;
  2957. /* count bits set */
  2958. num_active_phys = hweight_long(params->affected_displays);
  2959. SDE_DEBUG_ENC(sde_enc, "affected_displays 0x%lx num_active_phys %d\n",
  2960. params->affected_displays, num_active_phys);
  2961. SDE_EVT32_VERBOSE(DRMID(drm_enc), params->affected_displays,
  2962. num_active_phys);
  2963. /* for left/right only update, ppsplit master switches interface */
  2964. _sde_encoder_ppsplit_swap_intf_for_right_only_update(drm_enc,
  2965. &params->affected_displays, num_active_phys);
  2966. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2967. enum sde_enc_split_role prv_role, new_role;
  2968. bool active = false;
  2969. phys = sde_enc->phys_encs[i];
  2970. if (!phys || !phys->ops.update_split_role || !phys->hw_pp)
  2971. continue;
  2972. active = test_bit(i, &params->affected_displays);
  2973. prv_role = phys->split_role;
  2974. if (active && num_active_phys == 1)
  2975. new_role = ENC_ROLE_SOLO;
  2976. else if (active && !master_assigned)
  2977. new_role = ENC_ROLE_MASTER;
  2978. else if (active)
  2979. new_role = ENC_ROLE_SLAVE;
  2980. else
  2981. new_role = ENC_ROLE_SKIP;
  2982. phys->ops.update_split_role(phys, new_role);
  2983. if (new_role == ENC_ROLE_SOLO || new_role == ENC_ROLE_MASTER) {
  2984. sde_enc->cur_master = phys;
  2985. master_assigned = true;
  2986. }
  2987. SDE_DEBUG_ENC(sde_enc, "pp %d role prv %d new %d active %d\n",
  2988. phys->hw_pp->idx - PINGPONG_0, prv_role,
  2989. phys->split_role, active);
  2990. SDE_EVT32(DRMID(drm_enc), params->affected_displays,
  2991. phys->hw_pp->idx - PINGPONG_0, prv_role,
  2992. phys->split_role, active, num_active_phys);
  2993. }
  2994. }
  2995. bool sde_encoder_check_curr_mode(struct drm_encoder *drm_enc, u32 mode)
  2996. {
  2997. struct sde_encoder_virt *sde_enc;
  2998. struct msm_display_info *disp_info;
  2999. if (!drm_enc) {
  3000. SDE_ERROR("invalid encoder\n");
  3001. return false;
  3002. }
  3003. sde_enc = to_sde_encoder_virt(drm_enc);
  3004. disp_info = &sde_enc->disp_info;
  3005. return (disp_info->curr_panel_mode == mode);
  3006. }
  3007. void sde_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
  3008. {
  3009. struct sde_encoder_virt *sde_enc;
  3010. struct sde_encoder_phys *phys;
  3011. unsigned int i;
  3012. struct sde_hw_ctl *ctl;
  3013. if (!drm_enc) {
  3014. SDE_ERROR("invalid encoder\n");
  3015. return;
  3016. }
  3017. sde_enc = to_sde_encoder_virt(drm_enc);
  3018. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3019. phys = sde_enc->phys_encs[i];
  3020. if (phys && phys->hw_ctl && (phys == sde_enc->cur_master) &&
  3021. sde_encoder_check_curr_mode(drm_enc,
  3022. MSM_DISPLAY_CMD_MODE)) {
  3023. ctl = phys->hw_ctl;
  3024. if (ctl->ops.trigger_pending)
  3025. /* update only for command mode primary ctl */
  3026. ctl->ops.trigger_pending(ctl);
  3027. }
  3028. }
  3029. sde_enc->idle_pc_restore = false;
  3030. }
  3031. static void sde_encoder_esd_trigger_work_handler(struct kthread_work *work)
  3032. {
  3033. struct sde_encoder_virt *sde_enc = container_of(work,
  3034. struct sde_encoder_virt, esd_trigger_work);
  3035. if (!sde_enc) {
  3036. SDE_ERROR("invalid sde encoder\n");
  3037. return;
  3038. }
  3039. sde_encoder_resource_control(&sde_enc->base,
  3040. SDE_ENC_RC_EVENT_KICKOFF);
  3041. }
  3042. static void sde_encoder_input_event_work_handler(struct kthread_work *work)
  3043. {
  3044. struct sde_encoder_virt *sde_enc = container_of(work,
  3045. struct sde_encoder_virt, input_event_work);
  3046. if (!sde_enc) {
  3047. SDE_ERROR("invalid sde encoder\n");
  3048. return;
  3049. }
  3050. sde_encoder_resource_control(&sde_enc->base,
  3051. SDE_ENC_RC_EVENT_EARLY_WAKEUP);
  3052. }
  3053. int sde_encoder_poll_line_counts(struct drm_encoder *drm_enc)
  3054. {
  3055. static const uint64_t timeout_us = 50000;
  3056. static const uint64_t sleep_us = 20;
  3057. struct sde_encoder_virt *sde_enc;
  3058. ktime_t cur_ktime, exp_ktime;
  3059. uint32_t line_count, tmp, i;
  3060. if (!drm_enc) {
  3061. SDE_ERROR("invalid encoder\n");
  3062. return -EINVAL;
  3063. }
  3064. sde_enc = to_sde_encoder_virt(drm_enc);
  3065. if (!sde_enc->cur_master ||
  3066. !sde_enc->cur_master->ops.get_line_count) {
  3067. SDE_DEBUG_ENC(sde_enc, "can't get master line count\n");
  3068. SDE_EVT32(DRMID(drm_enc), SDE_EVTLOG_ERROR);
  3069. return -EINVAL;
  3070. }
  3071. exp_ktime = ktime_add_ms(ktime_get(), timeout_us / 1000);
  3072. line_count = sde_enc->cur_master->ops.get_line_count(
  3073. sde_enc->cur_master);
  3074. for (i = 0; i < (timeout_us * 2 / sleep_us); ++i) {
  3075. tmp = line_count;
  3076. line_count = sde_enc->cur_master->ops.get_line_count(
  3077. sde_enc->cur_master);
  3078. if (line_count < tmp) {
  3079. SDE_EVT32(DRMID(drm_enc), line_count);
  3080. return 0;
  3081. }
  3082. cur_ktime = ktime_get();
  3083. if (ktime_compare_safe(exp_ktime, cur_ktime) <= 0)
  3084. break;
  3085. usleep_range(sleep_us / 2, sleep_us);
  3086. }
  3087. SDE_EVT32(DRMID(drm_enc), line_count, SDE_EVTLOG_ERROR);
  3088. return -ETIMEDOUT;
  3089. }
  3090. static int _helper_flush_qsync(struct sde_encoder_phys *phys_enc)
  3091. {
  3092. struct drm_encoder *drm_enc;
  3093. struct sde_rm_hw_iter rm_iter;
  3094. bool lm_valid = false;
  3095. bool intf_valid = false;
  3096. if (!phys_enc || !phys_enc->parent) {
  3097. SDE_ERROR("invalid encoder\n");
  3098. return -EINVAL;
  3099. }
  3100. drm_enc = phys_enc->parent;
  3101. /* Flush the interfaces for AVR update or Qsync with INTF TE */
  3102. if (phys_enc->intf_mode == INTF_MODE_VIDEO ||
  3103. (phys_enc->intf_mode == INTF_MODE_CMD &&
  3104. phys_enc->has_intf_te)) {
  3105. sde_rm_init_hw_iter(&rm_iter, drm_enc->base.id,
  3106. SDE_HW_BLK_INTF);
  3107. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &rm_iter)) {
  3108. struct sde_hw_intf *hw_intf =
  3109. (struct sde_hw_intf *)rm_iter.hw;
  3110. if (!hw_intf)
  3111. continue;
  3112. if (phys_enc->hw_ctl->ops.update_bitmask)
  3113. phys_enc->hw_ctl->ops.update_bitmask(
  3114. phys_enc->hw_ctl,
  3115. SDE_HW_FLUSH_INTF,
  3116. hw_intf->idx, 1);
  3117. intf_valid = true;
  3118. }
  3119. if (!intf_valid) {
  3120. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc),
  3121. "intf not found to flush\n");
  3122. return -EFAULT;
  3123. }
  3124. } else {
  3125. sde_rm_init_hw_iter(&rm_iter, drm_enc->base.id, SDE_HW_BLK_LM);
  3126. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &rm_iter)) {
  3127. struct sde_hw_mixer *hw_lm =
  3128. (struct sde_hw_mixer *)rm_iter.hw;
  3129. if (!hw_lm)
  3130. continue;
  3131. /* update LM flush for HW without INTF TE */
  3132. if (phys_enc->hw_ctl->ops.update_bitmask_mixer)
  3133. phys_enc->hw_ctl->ops.update_bitmask_mixer(
  3134. phys_enc->hw_ctl,
  3135. hw_lm->idx, 1);
  3136. lm_valid = true;
  3137. }
  3138. if (!lm_valid) {
  3139. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc),
  3140. "lm not found to flush\n");
  3141. return -EFAULT;
  3142. }
  3143. }
  3144. return 0;
  3145. }
  3146. static void _sde_encoder_helper_hdr_plus_mempool_update(
  3147. struct sde_encoder_virt *sde_enc)
  3148. {
  3149. struct sde_connector_dyn_hdr_metadata *dhdr_meta = NULL;
  3150. struct sde_hw_mdp *mdptop = NULL;
  3151. sde_enc->dynamic_hdr_updated = false;
  3152. if (sde_enc->cur_master) {
  3153. mdptop = sde_enc->cur_master->hw_mdptop;
  3154. dhdr_meta = sde_connector_get_dyn_hdr_meta(
  3155. sde_enc->cur_master->connector);
  3156. }
  3157. if (!mdptop || !dhdr_meta || !dhdr_meta->dynamic_hdr_update)
  3158. return;
  3159. if (mdptop->ops.set_hdr_plus_metadata) {
  3160. sde_enc->dynamic_hdr_updated = true;
  3161. mdptop->ops.set_hdr_plus_metadata(
  3162. mdptop, dhdr_meta->dynamic_hdr_payload,
  3163. dhdr_meta->dynamic_hdr_payload_size,
  3164. sde_enc->cur_master->intf_idx == INTF_0 ?
  3165. 0 : 1);
  3166. }
  3167. }
  3168. void sde_encoder_needs_hw_reset(struct drm_encoder *drm_enc)
  3169. {
  3170. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  3171. struct sde_encoder_phys *phys;
  3172. int i;
  3173. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3174. phys = sde_enc->phys_encs[i];
  3175. if (phys && phys->ops.hw_reset)
  3176. phys->ops.hw_reset(phys);
  3177. }
  3178. }
  3179. int sde_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc,
  3180. struct sde_encoder_kickoff_params *params)
  3181. {
  3182. struct sde_encoder_virt *sde_enc;
  3183. struct sde_encoder_phys *phys;
  3184. struct sde_kms *sde_kms = NULL;
  3185. struct sde_crtc *sde_crtc;
  3186. bool needs_hw_reset = false, is_cmd_mode;
  3187. int i, rc, ret = 0;
  3188. struct msm_display_info *disp_info;
  3189. if (!drm_enc || !params || !drm_enc->dev ||
  3190. !drm_enc->dev->dev_private) {
  3191. SDE_ERROR("invalid args\n");
  3192. return -EINVAL;
  3193. }
  3194. sde_enc = to_sde_encoder_virt(drm_enc);
  3195. sde_kms = sde_encoder_get_kms(drm_enc);
  3196. if (!sde_kms)
  3197. return -EINVAL;
  3198. disp_info = &sde_enc->disp_info;
  3199. sde_crtc = to_sde_crtc(sde_enc->crtc);
  3200. SDE_DEBUG_ENC(sde_enc, "\n");
  3201. SDE_EVT32(DRMID(drm_enc));
  3202. is_cmd_mode = sde_encoder_check_curr_mode(drm_enc,
  3203. MSM_DISPLAY_CMD_MODE);
  3204. if (sde_enc->cur_master && sde_enc->cur_master->connector
  3205. && is_cmd_mode)
  3206. sde_enc->frame_trigger_mode = sde_connector_get_property(
  3207. sde_enc->cur_master->connector->state,
  3208. CONNECTOR_PROP_CMD_FRAME_TRIGGER_MODE);
  3209. _sde_encoder_helper_hdr_plus_mempool_update(sde_enc);
  3210. /* prepare for next kickoff, may include waiting on previous kickoff */
  3211. SDE_ATRACE_BEGIN("sde_encoder_prepare_for_kickoff");
  3212. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3213. phys = sde_enc->phys_encs[i];
  3214. params->frame_trigger_mode = sde_enc->frame_trigger_mode;
  3215. params->recovery_events_enabled =
  3216. sde_enc->recovery_events_enabled;
  3217. if (phys) {
  3218. if (phys->ops.prepare_for_kickoff) {
  3219. rc = phys->ops.prepare_for_kickoff(
  3220. phys, params);
  3221. if (rc)
  3222. ret = rc;
  3223. }
  3224. if (phys->enable_state == SDE_ENC_ERR_NEEDS_HW_RESET)
  3225. needs_hw_reset = true;
  3226. _sde_encoder_setup_dither(phys);
  3227. if (sde_enc->cur_master &&
  3228. sde_connector_is_qsync_updated(
  3229. sde_enc->cur_master->connector)) {
  3230. _helper_flush_qsync(phys);
  3231. }
  3232. }
  3233. }
  3234. rc = sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_KICKOFF);
  3235. if (rc) {
  3236. SDE_ERROR_ENC(sde_enc, "resource kickoff failed rc %d\n", rc);
  3237. ret = rc;
  3238. goto end;
  3239. }
  3240. /* if any phys needs reset, reset all phys, in-order */
  3241. if (needs_hw_reset)
  3242. sde_encoder_needs_hw_reset(drm_enc);
  3243. _sde_encoder_update_master(drm_enc, params);
  3244. _sde_encoder_update_roi(drm_enc);
  3245. if (sde_enc->cur_master && sde_enc->cur_master->connector) {
  3246. rc = sde_connector_pre_kickoff(sde_enc->cur_master->connector);
  3247. if (rc) {
  3248. SDE_ERROR_ENC(sde_enc, "kickoff conn%d failed rc %d\n",
  3249. sde_enc->cur_master->connector->base.id,
  3250. rc);
  3251. ret = rc;
  3252. }
  3253. }
  3254. if (sde_enc->cur_master &&
  3255. ((is_cmd_mode && sde_enc->cur_master->cont_splash_enabled) ||
  3256. !sde_enc->cur_master->cont_splash_enabled)) {
  3257. rc = sde_encoder_dce_setup(sde_enc, params);
  3258. if (rc) {
  3259. SDE_ERROR_ENC(sde_enc, "failed to setup DSC: %d\n", rc);
  3260. ret = rc;
  3261. }
  3262. }
  3263. sde_encoder_dce_flush(sde_enc);
  3264. if (sde_enc->cur_master && !sde_enc->cur_master->cont_splash_enabled)
  3265. sde_configure_qdss(sde_enc, sde_enc->cur_master->hw_qdss,
  3266. sde_enc->cur_master, sde_kms->qdss_enabled);
  3267. end:
  3268. SDE_ATRACE_END("sde_encoder_prepare_for_kickoff");
  3269. return ret;
  3270. }
  3271. /**
  3272. * _sde_encoder_reset_ctl_hw - reset h/w configuration for all ctl's associated
  3273. * with the specified encoder, and unstage all pipes from it
  3274. * @encoder: encoder pointer
  3275. * Returns: 0 on success
  3276. */
  3277. static int _sde_encoder_reset_ctl_hw(struct drm_encoder *drm_enc)
  3278. {
  3279. struct sde_encoder_virt *sde_enc;
  3280. struct sde_encoder_phys *phys;
  3281. unsigned int i;
  3282. int rc = 0;
  3283. if (!drm_enc) {
  3284. SDE_ERROR("invalid encoder\n");
  3285. return -EINVAL;
  3286. }
  3287. sde_enc = to_sde_encoder_virt(drm_enc);
  3288. SDE_ATRACE_BEGIN("encoder_release_lm");
  3289. SDE_DEBUG_ENC(sde_enc, "\n");
  3290. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3291. phys = sde_enc->phys_encs[i];
  3292. if (!phys)
  3293. continue;
  3294. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0);
  3295. rc = sde_encoder_helper_reset_mixers(phys, NULL);
  3296. if (rc)
  3297. SDE_EVT32(DRMID(drm_enc), rc, SDE_EVTLOG_ERROR);
  3298. }
  3299. SDE_ATRACE_END("encoder_release_lm");
  3300. return rc;
  3301. }
  3302. void sde_encoder_kickoff(struct drm_encoder *drm_enc, bool is_error)
  3303. {
  3304. struct sde_encoder_virt *sde_enc;
  3305. struct sde_encoder_phys *phys;
  3306. unsigned int i;
  3307. if (!drm_enc) {
  3308. SDE_ERROR("invalid encoder\n");
  3309. return;
  3310. }
  3311. SDE_ATRACE_BEGIN("encoder_kickoff");
  3312. sde_enc = to_sde_encoder_virt(drm_enc);
  3313. SDE_DEBUG_ENC(sde_enc, "\n");
  3314. /* create a 'no pipes' commit to release buffers on errors */
  3315. if (is_error)
  3316. _sde_encoder_reset_ctl_hw(drm_enc);
  3317. /* All phys encs are ready to go, trigger the kickoff */
  3318. _sde_encoder_kickoff_phys(sde_enc);
  3319. /* allow phys encs to handle any post-kickoff business */
  3320. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3321. phys = sde_enc->phys_encs[i];
  3322. if (phys && phys->ops.handle_post_kickoff)
  3323. phys->ops.handle_post_kickoff(phys);
  3324. }
  3325. SDE_ATRACE_END("encoder_kickoff");
  3326. }
  3327. void sde_encoder_helper_get_pp_line_count(struct drm_encoder *drm_enc,
  3328. struct sde_hw_pp_vsync_info *info)
  3329. {
  3330. struct sde_encoder_virt *sde_enc;
  3331. struct sde_encoder_phys *phys;
  3332. int i, ret;
  3333. if (!drm_enc || !info)
  3334. return;
  3335. sde_enc = to_sde_encoder_virt(drm_enc);
  3336. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3337. phys = sde_enc->phys_encs[i];
  3338. if (phys && phys->hw_intf && phys->hw_pp
  3339. && phys->hw_intf->ops.get_vsync_info) {
  3340. ret = phys->hw_intf->ops.get_vsync_info(
  3341. phys->hw_intf, &info[i]);
  3342. if (!ret) {
  3343. info[i].pp_idx = phys->hw_pp->idx - PINGPONG_0;
  3344. info[i].intf_idx = phys->hw_intf->idx - INTF_0;
  3345. }
  3346. }
  3347. }
  3348. }
  3349. int sde_encoder_helper_reset_mixers(struct sde_encoder_phys *phys_enc,
  3350. struct drm_framebuffer *fb)
  3351. {
  3352. struct drm_encoder *drm_enc;
  3353. struct sde_hw_mixer_cfg mixer;
  3354. struct sde_rm_hw_iter lm_iter;
  3355. bool lm_valid = false;
  3356. if (!phys_enc || !phys_enc->parent) {
  3357. SDE_ERROR("invalid encoder\n");
  3358. return -EINVAL;
  3359. }
  3360. drm_enc = phys_enc->parent;
  3361. memset(&mixer, 0, sizeof(mixer));
  3362. /* reset associated CTL/LMs */
  3363. if (phys_enc->hw_ctl->ops.clear_all_blendstages)
  3364. phys_enc->hw_ctl->ops.clear_all_blendstages(phys_enc->hw_ctl);
  3365. sde_rm_init_hw_iter(&lm_iter, drm_enc->base.id, SDE_HW_BLK_LM);
  3366. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &lm_iter)) {
  3367. struct sde_hw_mixer *hw_lm = (struct sde_hw_mixer *)lm_iter.hw;
  3368. if (!hw_lm)
  3369. continue;
  3370. /* need to flush LM to remove it */
  3371. if (phys_enc->hw_ctl->ops.update_bitmask_mixer)
  3372. phys_enc->hw_ctl->ops.update_bitmask_mixer(
  3373. phys_enc->hw_ctl,
  3374. hw_lm->idx, 1);
  3375. if (fb) {
  3376. /* assume a single LM if targeting a frame buffer */
  3377. if (lm_valid)
  3378. continue;
  3379. mixer.out_height = fb->height;
  3380. mixer.out_width = fb->width;
  3381. if (hw_lm->ops.setup_mixer_out)
  3382. hw_lm->ops.setup_mixer_out(hw_lm, &mixer);
  3383. }
  3384. lm_valid = true;
  3385. /* only enable border color on LM */
  3386. if (phys_enc->hw_ctl->ops.setup_blendstage)
  3387. phys_enc->hw_ctl->ops.setup_blendstage(
  3388. phys_enc->hw_ctl, hw_lm->idx, NULL);
  3389. }
  3390. if (!lm_valid) {
  3391. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc), "lm not found\n");
  3392. return -EFAULT;
  3393. }
  3394. return 0;
  3395. }
  3396. int sde_encoder_prepare_commit(struct drm_encoder *drm_enc)
  3397. {
  3398. struct sde_encoder_virt *sde_enc;
  3399. struct sde_encoder_phys *phys;
  3400. int i, rc = 0, ret = 0;
  3401. struct sde_hw_ctl *ctl;
  3402. if (!drm_enc) {
  3403. SDE_ERROR("invalid encoder\n");
  3404. return -EINVAL;
  3405. }
  3406. sde_enc = to_sde_encoder_virt(drm_enc);
  3407. /* update the qsync parameters for the current frame */
  3408. if (sde_enc->cur_master)
  3409. sde_connector_set_qsync_params(
  3410. sde_enc->cur_master->connector);
  3411. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3412. phys = sde_enc->phys_encs[i];
  3413. if (phys && phys->ops.prepare_commit)
  3414. phys->ops.prepare_commit(phys);
  3415. if (phys && phys->enable_state == SDE_ENC_ERR_NEEDS_HW_RESET)
  3416. ret = -ETIMEDOUT;
  3417. if (phys && phys->hw_ctl) {
  3418. ctl = phys->hw_ctl;
  3419. /*
  3420. * avoid clearing the pending flush during the first
  3421. * frame update after idle power collpase as the
  3422. * restore path would have updated the pending flush
  3423. */
  3424. if (!sde_enc->idle_pc_restore &&
  3425. ctl->ops.clear_pending_flush)
  3426. ctl->ops.clear_pending_flush(ctl);
  3427. }
  3428. }
  3429. if (sde_enc->cur_master && sde_enc->cur_master->connector) {
  3430. rc = sde_connector_prepare_commit(
  3431. sde_enc->cur_master->connector);
  3432. if (rc)
  3433. SDE_ERROR_ENC(sde_enc,
  3434. "prepare commit failed conn %d rc %d\n",
  3435. sde_enc->cur_master->connector->base.id,
  3436. rc);
  3437. }
  3438. return ret;
  3439. }
  3440. void sde_encoder_helper_setup_misr(struct sde_encoder_phys *phys_enc,
  3441. bool enable, u32 frame_count)
  3442. {
  3443. if (!phys_enc)
  3444. return;
  3445. if (phys_enc->hw_intf && phys_enc->hw_intf->ops.setup_misr)
  3446. phys_enc->hw_intf->ops.setup_misr(phys_enc->hw_intf,
  3447. enable, frame_count);
  3448. }
  3449. int sde_encoder_helper_collect_misr(struct sde_encoder_phys *phys_enc,
  3450. bool nonblock, u32 *misr_value)
  3451. {
  3452. if (!phys_enc)
  3453. return -EINVAL;
  3454. return phys_enc->hw_intf && phys_enc->hw_intf->ops.collect_misr ?
  3455. phys_enc->hw_intf->ops.collect_misr(phys_enc->hw_intf,
  3456. nonblock, misr_value) : -ENOTSUPP;
  3457. }
  3458. #ifdef CONFIG_DEBUG_FS
  3459. static int _sde_encoder_status_show(struct seq_file *s, void *data)
  3460. {
  3461. struct sde_encoder_virt *sde_enc;
  3462. int i;
  3463. if (!s || !s->private)
  3464. return -EINVAL;
  3465. sde_enc = s->private;
  3466. mutex_lock(&sde_enc->enc_lock);
  3467. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3468. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3469. if (!phys)
  3470. continue;
  3471. seq_printf(s, "intf:%d vsync:%8d underrun:%8d ",
  3472. phys->intf_idx - INTF_0,
  3473. atomic_read(&phys->vsync_cnt),
  3474. atomic_read(&phys->underrun_cnt));
  3475. switch (phys->intf_mode) {
  3476. case INTF_MODE_VIDEO:
  3477. seq_puts(s, "mode: video\n");
  3478. break;
  3479. case INTF_MODE_CMD:
  3480. seq_puts(s, "mode: command\n");
  3481. break;
  3482. case INTF_MODE_WB_BLOCK:
  3483. seq_puts(s, "mode: wb block\n");
  3484. break;
  3485. case INTF_MODE_WB_LINE:
  3486. seq_puts(s, "mode: wb line\n");
  3487. break;
  3488. default:
  3489. seq_puts(s, "mode: ???\n");
  3490. break;
  3491. }
  3492. }
  3493. mutex_unlock(&sde_enc->enc_lock);
  3494. return 0;
  3495. }
  3496. static int _sde_encoder_debugfs_status_open(struct inode *inode,
  3497. struct file *file)
  3498. {
  3499. return single_open(file, _sde_encoder_status_show, inode->i_private);
  3500. }
  3501. static ssize_t _sde_encoder_misr_setup(struct file *file,
  3502. const char __user *user_buf, size_t count, loff_t *ppos)
  3503. {
  3504. struct sde_encoder_virt *sde_enc;
  3505. int rc;
  3506. char buf[MISR_BUFF_SIZE + 1];
  3507. size_t buff_copy;
  3508. u32 frame_count, enable;
  3509. struct sde_kms *sde_kms = NULL;
  3510. struct drm_encoder *drm_enc;
  3511. if (!file || !file->private_data)
  3512. return -EINVAL;
  3513. sde_enc = file->private_data;
  3514. if (!sde_enc)
  3515. return -EINVAL;
  3516. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  3517. if (!sde_kms)
  3518. return -EINVAL;
  3519. drm_enc = &sde_enc->base;
  3520. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  3521. SDE_DEBUG_ENC(sde_enc, "misr enable/disable not allowed\n");
  3522. return -ENOTSUPP;
  3523. }
  3524. buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
  3525. if (copy_from_user(buf, user_buf, buff_copy))
  3526. return -EINVAL;
  3527. buf[buff_copy] = 0; /* end of string */
  3528. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
  3529. return -EINVAL;
  3530. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  3531. if (rc < 0)
  3532. return rc;
  3533. sde_enc->misr_enable = enable;
  3534. sde_enc->misr_frame_count = frame_count;
  3535. sde_encoder_misr_configure(&sde_enc->base, enable, frame_count);
  3536. pm_runtime_put_sync(drm_enc->dev->dev);
  3537. return count;
  3538. }
  3539. static ssize_t _sde_encoder_misr_read(struct file *file,
  3540. char __user *user_buff, size_t count, loff_t *ppos)
  3541. {
  3542. struct sde_encoder_virt *sde_enc;
  3543. struct sde_kms *sde_kms = NULL;
  3544. struct drm_encoder *drm_enc;
  3545. int i = 0, len = 0;
  3546. char buf[MISR_BUFF_SIZE + 1] = {'\0'};
  3547. int rc;
  3548. if (*ppos)
  3549. return 0;
  3550. if (!file || !file->private_data)
  3551. return -EINVAL;
  3552. sde_enc = file->private_data;
  3553. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  3554. if (!sde_kms)
  3555. return -EINVAL;
  3556. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  3557. SDE_DEBUG_ENC(sde_enc, "misr read not allowed\n");
  3558. return -ENOTSUPP;
  3559. }
  3560. drm_enc = &sde_enc->base;
  3561. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  3562. if (rc < 0)
  3563. return rc;
  3564. if (!sde_enc->misr_enable) {
  3565. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3566. "disabled\n");
  3567. goto buff_check;
  3568. }
  3569. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3570. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3571. u32 misr_value = 0;
  3572. if (!phys || !phys->ops.collect_misr) {
  3573. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3574. "invalid\n");
  3575. SDE_ERROR_ENC(sde_enc, "invalid misr ops\n");
  3576. continue;
  3577. }
  3578. rc = phys->ops.collect_misr(phys, false, &misr_value);
  3579. if (rc) {
  3580. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3581. "invalid\n");
  3582. SDE_ERROR_ENC(sde_enc, "failed to collect misr %d\n",
  3583. rc);
  3584. continue;
  3585. } else {
  3586. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3587. "Intf idx:%d\n",
  3588. phys->intf_idx - INTF_0);
  3589. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3590. "0x%x\n", misr_value);
  3591. }
  3592. }
  3593. buff_check:
  3594. if (count <= len) {
  3595. len = 0;
  3596. goto end;
  3597. }
  3598. if (copy_to_user(user_buff, buf, len)) {
  3599. len = -EFAULT;
  3600. goto end;
  3601. }
  3602. *ppos += len; /* increase offset */
  3603. end:
  3604. pm_runtime_put_sync(drm_enc->dev->dev);
  3605. return len;
  3606. }
  3607. static int _sde_encoder_init_debugfs(struct drm_encoder *drm_enc)
  3608. {
  3609. struct sde_encoder_virt *sde_enc;
  3610. struct sde_kms *sde_kms;
  3611. int i;
  3612. static const struct file_operations debugfs_status_fops = {
  3613. .open = _sde_encoder_debugfs_status_open,
  3614. .read = seq_read,
  3615. .llseek = seq_lseek,
  3616. .release = single_release,
  3617. };
  3618. static const struct file_operations debugfs_misr_fops = {
  3619. .open = simple_open,
  3620. .read = _sde_encoder_misr_read,
  3621. .write = _sde_encoder_misr_setup,
  3622. };
  3623. char name[SDE_NAME_SIZE];
  3624. if (!drm_enc) {
  3625. SDE_ERROR("invalid encoder\n");
  3626. return -EINVAL;
  3627. }
  3628. sde_enc = to_sde_encoder_virt(drm_enc);
  3629. sde_kms = sde_encoder_get_kms(drm_enc);
  3630. if (!sde_kms) {
  3631. SDE_ERROR("invalid sde_kms\n");
  3632. return -EINVAL;
  3633. }
  3634. snprintf(name, SDE_NAME_SIZE, "encoder%u", drm_enc->base.id);
  3635. /* create overall sub-directory for the encoder */
  3636. sde_enc->debugfs_root = debugfs_create_dir(name,
  3637. drm_enc->dev->primary->debugfs_root);
  3638. if (!sde_enc->debugfs_root)
  3639. return -ENOMEM;
  3640. /* don't error check these */
  3641. debugfs_create_file("status", 0400,
  3642. sde_enc->debugfs_root, sde_enc, &debugfs_status_fops);
  3643. debugfs_create_file("misr_data", 0600,
  3644. sde_enc->debugfs_root, sde_enc, &debugfs_misr_fops);
  3645. debugfs_create_bool("idle_power_collapse", 0600, sde_enc->debugfs_root,
  3646. &sde_enc->idle_pc_enabled);
  3647. debugfs_create_u32("frame_trigger_mode", 0400, sde_enc->debugfs_root,
  3648. &sde_enc->frame_trigger_mode);
  3649. for (i = 0; i < sde_enc->num_phys_encs; i++)
  3650. if (sde_enc->phys_encs[i] &&
  3651. sde_enc->phys_encs[i]->ops.late_register)
  3652. sde_enc->phys_encs[i]->ops.late_register(
  3653. sde_enc->phys_encs[i],
  3654. sde_enc->debugfs_root);
  3655. return 0;
  3656. }
  3657. static void _sde_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
  3658. {
  3659. struct sde_encoder_virt *sde_enc;
  3660. if (!drm_enc)
  3661. return;
  3662. sde_enc = to_sde_encoder_virt(drm_enc);
  3663. debugfs_remove_recursive(sde_enc->debugfs_root);
  3664. }
  3665. #else
  3666. static int _sde_encoder_init_debugfs(struct drm_encoder *drm_enc)
  3667. {
  3668. return 0;
  3669. }
  3670. static void _sde_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
  3671. {
  3672. }
  3673. #endif
  3674. static int sde_encoder_late_register(struct drm_encoder *encoder)
  3675. {
  3676. return _sde_encoder_init_debugfs(encoder);
  3677. }
  3678. static void sde_encoder_early_unregister(struct drm_encoder *encoder)
  3679. {
  3680. _sde_encoder_destroy_debugfs(encoder);
  3681. }
  3682. static int sde_encoder_virt_add_phys_encs(
  3683. struct msm_display_info *disp_info,
  3684. struct sde_encoder_virt *sde_enc,
  3685. struct sde_enc_phys_init_params *params)
  3686. {
  3687. struct sde_encoder_phys *enc = NULL;
  3688. u32 display_caps = disp_info->capabilities;
  3689. SDE_DEBUG_ENC(sde_enc, "\n");
  3690. /*
  3691. * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
  3692. * in this function, check up-front.
  3693. */
  3694. if (sde_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
  3695. ARRAY_SIZE(sde_enc->phys_encs)) {
  3696. SDE_ERROR_ENC(sde_enc, "too many physical encoders %d\n",
  3697. sde_enc->num_phys_encs);
  3698. return -EINVAL;
  3699. }
  3700. if (display_caps & MSM_DISPLAY_CAP_VID_MODE) {
  3701. enc = sde_encoder_phys_vid_init(params);
  3702. if (IS_ERR_OR_NULL(enc)) {
  3703. SDE_ERROR_ENC(sde_enc, "failed to init vid enc: %ld\n",
  3704. PTR_ERR(enc));
  3705. return !enc ? -EINVAL : PTR_ERR(enc);
  3706. }
  3707. sde_enc->phys_vid_encs[sde_enc->num_phys_encs] = enc;
  3708. }
  3709. if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) {
  3710. enc = sde_encoder_phys_cmd_init(params);
  3711. if (IS_ERR_OR_NULL(enc)) {
  3712. SDE_ERROR_ENC(sde_enc, "failed to init cmd enc: %ld\n",
  3713. PTR_ERR(enc));
  3714. return !enc ? -EINVAL : PTR_ERR(enc);
  3715. }
  3716. sde_enc->phys_cmd_encs[sde_enc->num_phys_encs] = enc;
  3717. }
  3718. if (disp_info->curr_panel_mode == MSM_DISPLAY_VIDEO_MODE)
  3719. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  3720. sde_enc->phys_vid_encs[sde_enc->num_phys_encs];
  3721. else
  3722. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  3723. sde_enc->phys_cmd_encs[sde_enc->num_phys_encs];
  3724. ++sde_enc->num_phys_encs;
  3725. return 0;
  3726. }
  3727. static int sde_encoder_virt_add_phys_enc_wb(struct sde_encoder_virt *sde_enc,
  3728. struct sde_enc_phys_init_params *params)
  3729. {
  3730. struct sde_encoder_phys *enc = NULL;
  3731. if (!sde_enc) {
  3732. SDE_ERROR("invalid encoder\n");
  3733. return -EINVAL;
  3734. }
  3735. SDE_DEBUG_ENC(sde_enc, "\n");
  3736. if (sde_enc->num_phys_encs + 1 >= ARRAY_SIZE(sde_enc->phys_encs)) {
  3737. SDE_ERROR_ENC(sde_enc, "too many physical encoders %d\n",
  3738. sde_enc->num_phys_encs);
  3739. return -EINVAL;
  3740. }
  3741. enc = sde_encoder_phys_wb_init(params);
  3742. if (IS_ERR_OR_NULL(enc)) {
  3743. SDE_ERROR_ENC(sde_enc, "failed to init wb enc: %ld\n",
  3744. PTR_ERR(enc));
  3745. return !enc ? -EINVAL : PTR_ERR(enc);
  3746. }
  3747. sde_enc->phys_encs[sde_enc->num_phys_encs] = enc;
  3748. ++sde_enc->num_phys_encs;
  3749. return 0;
  3750. }
  3751. static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc,
  3752. struct sde_kms *sde_kms,
  3753. struct msm_display_info *disp_info,
  3754. int *drm_enc_mode)
  3755. {
  3756. int ret = 0;
  3757. int i = 0;
  3758. enum sde_intf_type intf_type;
  3759. struct sde_encoder_virt_ops parent_ops = {
  3760. sde_encoder_vblank_callback,
  3761. sde_encoder_underrun_callback,
  3762. sde_encoder_frame_done_callback,
  3763. sde_encoder_get_qsync_fps_callback,
  3764. };
  3765. struct sde_enc_phys_init_params phys_params;
  3766. if (!sde_enc || !sde_kms) {
  3767. SDE_ERROR("invalid arg(s), enc %d kms %d\n",
  3768. !sde_enc, !sde_kms);
  3769. return -EINVAL;
  3770. }
  3771. memset(&phys_params, 0, sizeof(phys_params));
  3772. phys_params.sde_kms = sde_kms;
  3773. phys_params.parent = &sde_enc->base;
  3774. phys_params.parent_ops = parent_ops;
  3775. phys_params.enc_spinlock = &sde_enc->enc_spinlock;
  3776. phys_params.vblank_ctl_lock = &sde_enc->vblank_ctl_lock;
  3777. SDE_DEBUG("\n");
  3778. if (disp_info->intf_type == DRM_MODE_CONNECTOR_DSI) {
  3779. *drm_enc_mode = DRM_MODE_ENCODER_DSI;
  3780. intf_type = INTF_DSI;
  3781. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_HDMIA) {
  3782. *drm_enc_mode = DRM_MODE_ENCODER_TMDS;
  3783. intf_type = INTF_HDMI;
  3784. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_DisplayPort) {
  3785. if (disp_info->capabilities & MSM_DISPLAY_CAP_MST_MODE)
  3786. *drm_enc_mode = DRM_MODE_ENCODER_DPMST;
  3787. else
  3788. *drm_enc_mode = DRM_MODE_ENCODER_TMDS;
  3789. intf_type = INTF_DP;
  3790. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_VIRTUAL) {
  3791. *drm_enc_mode = DRM_MODE_ENCODER_VIRTUAL;
  3792. intf_type = INTF_WB;
  3793. } else {
  3794. SDE_ERROR_ENC(sde_enc, "unsupported display interface type\n");
  3795. return -EINVAL;
  3796. }
  3797. WARN_ON(disp_info->num_of_h_tiles < 1);
  3798. sde_enc->display_num_of_h_tiles = disp_info->num_of_h_tiles;
  3799. sde_enc->te_source = disp_info->te_source;
  3800. SDE_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
  3801. if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
  3802. (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE))
  3803. sde_enc->idle_pc_enabled = sde_kms->catalog->has_idle_pc;
  3804. mutex_lock(&sde_enc->enc_lock);
  3805. for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
  3806. /*
  3807. * Left-most tile is at index 0, content is controller id
  3808. * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
  3809. * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
  3810. */
  3811. u32 controller_id = disp_info->h_tile_instance[i];
  3812. if (disp_info->num_of_h_tiles > 1) {
  3813. if (i == 0)
  3814. phys_params.split_role = ENC_ROLE_MASTER;
  3815. else
  3816. phys_params.split_role = ENC_ROLE_SLAVE;
  3817. } else {
  3818. phys_params.split_role = ENC_ROLE_SOLO;
  3819. }
  3820. SDE_DEBUG("h_tile_instance %d = %d, split_role %d\n",
  3821. i, controller_id, phys_params.split_role);
  3822. if (sde_enc->ops.phys_init) {
  3823. struct sde_encoder_phys *enc;
  3824. enc = sde_enc->ops.phys_init(intf_type,
  3825. controller_id,
  3826. &phys_params);
  3827. if (enc) {
  3828. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  3829. enc;
  3830. ++sde_enc->num_phys_encs;
  3831. } else
  3832. SDE_ERROR_ENC(sde_enc,
  3833. "failed to add phys encs\n");
  3834. continue;
  3835. }
  3836. if (intf_type == INTF_WB) {
  3837. phys_params.intf_idx = INTF_MAX;
  3838. phys_params.wb_idx = sde_encoder_get_wb(
  3839. sde_kms->catalog,
  3840. intf_type, controller_id);
  3841. if (phys_params.wb_idx == WB_MAX) {
  3842. SDE_ERROR_ENC(sde_enc,
  3843. "could not get wb: type %d, id %d\n",
  3844. intf_type, controller_id);
  3845. ret = -EINVAL;
  3846. }
  3847. } else {
  3848. phys_params.wb_idx = WB_MAX;
  3849. phys_params.intf_idx = sde_encoder_get_intf(
  3850. sde_kms->catalog, intf_type,
  3851. controller_id);
  3852. if (phys_params.intf_idx == INTF_MAX) {
  3853. SDE_ERROR_ENC(sde_enc,
  3854. "could not get wb: type %d, id %d\n",
  3855. intf_type, controller_id);
  3856. ret = -EINVAL;
  3857. }
  3858. }
  3859. if (!ret) {
  3860. if (intf_type == INTF_WB)
  3861. ret = sde_encoder_virt_add_phys_enc_wb(sde_enc,
  3862. &phys_params);
  3863. else
  3864. ret = sde_encoder_virt_add_phys_encs(
  3865. disp_info,
  3866. sde_enc,
  3867. &phys_params);
  3868. if (ret)
  3869. SDE_ERROR_ENC(sde_enc,
  3870. "failed to add phys encs\n");
  3871. }
  3872. }
  3873. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3874. struct sde_encoder_phys *vid_phys = sde_enc->phys_vid_encs[i];
  3875. struct sde_encoder_phys *cmd_phys = sde_enc->phys_cmd_encs[i];
  3876. if (vid_phys) {
  3877. atomic_set(&vid_phys->vsync_cnt, 0);
  3878. atomic_set(&vid_phys->underrun_cnt, 0);
  3879. }
  3880. if (cmd_phys) {
  3881. atomic_set(&cmd_phys->vsync_cnt, 0);
  3882. atomic_set(&cmd_phys->underrun_cnt, 0);
  3883. }
  3884. }
  3885. mutex_unlock(&sde_enc->enc_lock);
  3886. return ret;
  3887. }
  3888. static const struct drm_encoder_helper_funcs sde_encoder_helper_funcs = {
  3889. .mode_set = sde_encoder_virt_mode_set,
  3890. .disable = sde_encoder_virt_disable,
  3891. .enable = sde_encoder_virt_enable,
  3892. .atomic_check = sde_encoder_virt_atomic_check,
  3893. };
  3894. static const struct drm_encoder_funcs sde_encoder_funcs = {
  3895. .destroy = sde_encoder_destroy,
  3896. .late_register = sde_encoder_late_register,
  3897. .early_unregister = sde_encoder_early_unregister,
  3898. };
  3899. struct drm_encoder *sde_encoder_init_with_ops(
  3900. struct drm_device *dev,
  3901. struct msm_display_info *disp_info,
  3902. const struct sde_encoder_ops *ops)
  3903. {
  3904. struct msm_drm_private *priv = dev->dev_private;
  3905. struct sde_kms *sde_kms = to_sde_kms(priv->kms);
  3906. struct drm_encoder *drm_enc = NULL;
  3907. struct sde_encoder_virt *sde_enc = NULL;
  3908. int drm_enc_mode = DRM_MODE_ENCODER_NONE;
  3909. char name[SDE_NAME_SIZE];
  3910. int ret = 0, i, intf_index = INTF_MAX;
  3911. struct sde_encoder_phys *phys = NULL;
  3912. sde_enc = kzalloc(sizeof(*sde_enc), GFP_KERNEL);
  3913. if (!sde_enc) {
  3914. ret = -ENOMEM;
  3915. goto fail;
  3916. }
  3917. if (ops)
  3918. sde_enc->ops = *ops;
  3919. mutex_init(&sde_enc->enc_lock);
  3920. ret = sde_encoder_setup_display(sde_enc, sde_kms, disp_info,
  3921. &drm_enc_mode);
  3922. if (ret)
  3923. goto fail;
  3924. sde_enc->cur_master = NULL;
  3925. spin_lock_init(&sde_enc->enc_spinlock);
  3926. mutex_init(&sde_enc->vblank_ctl_lock);
  3927. for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
  3928. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  3929. drm_enc = &sde_enc->base;
  3930. drm_encoder_init(dev, drm_enc, &sde_encoder_funcs, drm_enc_mode, NULL);
  3931. drm_encoder_helper_add(drm_enc, &sde_encoder_helper_funcs);
  3932. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3933. phys = sde_enc->phys_encs[i];
  3934. if (!phys)
  3935. continue;
  3936. if (phys->ops.is_master && phys->ops.is_master(phys))
  3937. intf_index = phys->intf_idx - INTF_0;
  3938. }
  3939. snprintf(name, SDE_NAME_SIZE, "rsc_enc%u", drm_enc->base.id);
  3940. sde_enc->rsc_client = sde_rsc_client_create(SDE_RSC_INDEX, name,
  3941. (disp_info->display_type == SDE_CONNECTOR_PRIMARY) ?
  3942. SDE_RSC_PRIMARY_DISP_CLIENT :
  3943. SDE_RSC_EXTERNAL_DISP_CLIENT, intf_index + 1);
  3944. if (IS_ERR_OR_NULL(sde_enc->rsc_client)) {
  3945. SDE_DEBUG("sde rsc client create failed :%ld\n",
  3946. PTR_ERR(sde_enc->rsc_client));
  3947. sde_enc->rsc_client = NULL;
  3948. }
  3949. if (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) {
  3950. ret = _sde_encoder_input_handler(sde_enc);
  3951. if (ret)
  3952. SDE_ERROR(
  3953. "input handler registration failed, rc = %d\n", ret);
  3954. }
  3955. mutex_init(&sde_enc->rc_lock);
  3956. kthread_init_delayed_work(&sde_enc->delayed_off_work,
  3957. sde_encoder_off_work);
  3958. sde_enc->vblank_enabled = false;
  3959. sde_enc->qdss_status = false;
  3960. kthread_init_work(&sde_enc->input_event_work,
  3961. sde_encoder_input_event_work_handler);
  3962. kthread_init_work(&sde_enc->esd_trigger_work,
  3963. sde_encoder_esd_trigger_work_handler);
  3964. memcpy(&sde_enc->disp_info, disp_info, sizeof(*disp_info));
  3965. SDE_DEBUG_ENC(sde_enc, "created\n");
  3966. return drm_enc;
  3967. fail:
  3968. SDE_ERROR("failed to create encoder\n");
  3969. if (drm_enc)
  3970. sde_encoder_destroy(drm_enc);
  3971. return ERR_PTR(ret);
  3972. }
  3973. struct drm_encoder *sde_encoder_init(
  3974. struct drm_device *dev,
  3975. struct msm_display_info *disp_info)
  3976. {
  3977. return sde_encoder_init_with_ops(dev, disp_info, NULL);
  3978. }
  3979. int sde_encoder_wait_for_event(struct drm_encoder *drm_enc,
  3980. enum msm_event_wait event)
  3981. {
  3982. int (*fn_wait)(struct sde_encoder_phys *phys_enc) = NULL;
  3983. struct sde_encoder_virt *sde_enc = NULL;
  3984. int i, ret = 0;
  3985. char atrace_buf[32];
  3986. if (!drm_enc) {
  3987. SDE_ERROR("invalid encoder\n");
  3988. return -EINVAL;
  3989. }
  3990. sde_enc = to_sde_encoder_virt(drm_enc);
  3991. SDE_DEBUG_ENC(sde_enc, "\n");
  3992. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3993. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3994. switch (event) {
  3995. case MSM_ENC_COMMIT_DONE:
  3996. fn_wait = phys->ops.wait_for_commit_done;
  3997. break;
  3998. case MSM_ENC_TX_COMPLETE:
  3999. fn_wait = phys->ops.wait_for_tx_complete;
  4000. break;
  4001. case MSM_ENC_VBLANK:
  4002. fn_wait = phys->ops.wait_for_vblank;
  4003. break;
  4004. case MSM_ENC_ACTIVE_REGION:
  4005. fn_wait = phys->ops.wait_for_active;
  4006. break;
  4007. default:
  4008. SDE_ERROR_ENC(sde_enc, "unknown wait event %d\n",
  4009. event);
  4010. return -EINVAL;
  4011. }
  4012. if (phys && fn_wait) {
  4013. snprintf(atrace_buf, sizeof(atrace_buf),
  4014. "wait_completion_event_%d", event);
  4015. SDE_ATRACE_BEGIN(atrace_buf);
  4016. ret = fn_wait(phys);
  4017. SDE_ATRACE_END(atrace_buf);
  4018. if (ret)
  4019. return ret;
  4020. }
  4021. }
  4022. return ret;
  4023. }
  4024. void sde_encoder_helper_get_jitter_bounds_ns(struct drm_encoder *drm_enc,
  4025. u64 *l_bound, u64 *u_bound)
  4026. {
  4027. struct sde_encoder_virt *sde_enc;
  4028. u64 jitter_ns, frametime_ns;
  4029. struct msm_mode_info *info;
  4030. if (!drm_enc) {
  4031. SDE_ERROR("invalid encoder\n");
  4032. return;
  4033. }
  4034. sde_enc = to_sde_encoder_virt(drm_enc);
  4035. info = &sde_enc->mode_info;
  4036. frametime_ns = (1 * 1000000000) / info->frame_rate;
  4037. jitter_ns = info->jitter_numer * frametime_ns;
  4038. do_div(jitter_ns, info->jitter_denom * 100);
  4039. *l_bound = frametime_ns - jitter_ns;
  4040. *u_bound = frametime_ns + jitter_ns;
  4041. }
  4042. u32 sde_encoder_get_fps(struct drm_encoder *drm_enc)
  4043. {
  4044. struct sde_encoder_virt *sde_enc;
  4045. if (!drm_enc) {
  4046. SDE_ERROR("invalid encoder\n");
  4047. return 0;
  4048. }
  4049. sde_enc = to_sde_encoder_virt(drm_enc);
  4050. return sde_enc->mode_info.frame_rate;
  4051. }
  4052. enum sde_intf_mode sde_encoder_get_intf_mode(struct drm_encoder *encoder)
  4053. {
  4054. struct sde_encoder_virt *sde_enc = NULL;
  4055. int i;
  4056. if (!encoder) {
  4057. SDE_ERROR("invalid encoder\n");
  4058. return INTF_MODE_NONE;
  4059. }
  4060. sde_enc = to_sde_encoder_virt(encoder);
  4061. if (sde_enc->cur_master)
  4062. return sde_enc->cur_master->intf_mode;
  4063. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4064. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4065. if (phys)
  4066. return phys->intf_mode;
  4067. }
  4068. return INTF_MODE_NONE;
  4069. }
  4070. static void _sde_encoder_cache_hw_res_cont_splash(
  4071. struct drm_encoder *encoder,
  4072. struct sde_kms *sde_kms)
  4073. {
  4074. int i, idx;
  4075. struct sde_encoder_virt *sde_enc;
  4076. struct sde_encoder_phys *phys_enc;
  4077. struct sde_rm_hw_iter dsc_iter, pp_iter, ctl_iter, intf_iter;
  4078. sde_enc = to_sde_encoder_virt(encoder);
  4079. sde_rm_init_hw_iter(&pp_iter, encoder->base.id, SDE_HW_BLK_PINGPONG);
  4080. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  4081. sde_enc->hw_pp[i] = NULL;
  4082. if (!sde_rm_get_hw(&sde_kms->rm, &pp_iter))
  4083. break;
  4084. sde_enc->hw_pp[i] = (struct sde_hw_pingpong *) pp_iter.hw;
  4085. }
  4086. sde_rm_init_hw_iter(&dsc_iter, encoder->base.id, SDE_HW_BLK_DSC);
  4087. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  4088. sde_enc->hw_dsc[i] = NULL;
  4089. if (!sde_rm_get_hw(&sde_kms->rm, &dsc_iter))
  4090. break;
  4091. sde_enc->hw_dsc[i] = (struct sde_hw_dsc *) dsc_iter.hw;
  4092. }
  4093. /*
  4094. * If we have multiple phys encoders with one controller, make
  4095. * sure to populate the controller pointer in both phys encoders.
  4096. */
  4097. for (idx = 0; idx < sde_enc->num_phys_encs; idx++) {
  4098. phys_enc = sde_enc->phys_encs[idx];
  4099. phys_enc->hw_ctl = NULL;
  4100. sde_rm_init_hw_iter(&ctl_iter, encoder->base.id,
  4101. SDE_HW_BLK_CTL);
  4102. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4103. if (sde_rm_get_hw(&sde_kms->rm, &ctl_iter)) {
  4104. phys_enc->hw_ctl =
  4105. (struct sde_hw_ctl *) ctl_iter.hw;
  4106. pr_debug("HW CTL intf_idx:%d hw_ctl:[0x%pK]\n",
  4107. phys_enc->intf_idx, phys_enc->hw_ctl);
  4108. }
  4109. }
  4110. }
  4111. sde_rm_init_hw_iter(&intf_iter, encoder->base.id, SDE_HW_BLK_INTF);
  4112. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4113. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4114. phys->hw_intf = NULL;
  4115. if (!sde_rm_get_hw(&sde_kms->rm, &intf_iter))
  4116. break;
  4117. phys->hw_intf = (struct sde_hw_intf *) intf_iter.hw;
  4118. }
  4119. }
  4120. /**
  4121. * sde_encoder_update_caps_for_cont_splash - update encoder settings during
  4122. * device bootup when cont_splash is enabled
  4123. * @drm_enc: Pointer to drm encoder structure
  4124. * @splash_display: Pointer to sde_splash_display corresponding to this encoder
  4125. * @enable: boolean indicates enable or displae state of splash
  4126. * @Return: true if successful in updating the encoder structure
  4127. */
  4128. int sde_encoder_update_caps_for_cont_splash(struct drm_encoder *encoder,
  4129. struct sde_splash_display *splash_display, bool enable)
  4130. {
  4131. struct sde_encoder_virt *sde_enc;
  4132. struct msm_drm_private *priv;
  4133. struct sde_kms *sde_kms;
  4134. struct drm_connector *conn = NULL;
  4135. struct sde_connector *sde_conn = NULL;
  4136. struct sde_connector_state *sde_conn_state = NULL;
  4137. struct drm_display_mode *drm_mode = NULL;
  4138. struct sde_encoder_phys *phys_enc;
  4139. int ret = 0, i;
  4140. if (!encoder) {
  4141. SDE_ERROR("invalid drm enc\n");
  4142. return -EINVAL;
  4143. }
  4144. sde_enc = to_sde_encoder_virt(encoder);
  4145. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  4146. if (!sde_kms) {
  4147. SDE_ERROR("invalid sde_kms\n");
  4148. return -EINVAL;
  4149. }
  4150. priv = encoder->dev->dev_private;
  4151. if (!priv->num_connectors) {
  4152. SDE_ERROR_ENC(sde_enc, "No connectors registered\n");
  4153. return -EINVAL;
  4154. }
  4155. SDE_DEBUG_ENC(sde_enc,
  4156. "num of connectors: %d\n", priv->num_connectors);
  4157. SDE_DEBUG_ENC(sde_enc, "enable: %d\n", enable);
  4158. if (!enable) {
  4159. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4160. phys_enc = sde_enc->phys_encs[i];
  4161. if (phys_enc)
  4162. phys_enc->cont_splash_enabled = false;
  4163. }
  4164. return ret;
  4165. }
  4166. if (!splash_display) {
  4167. SDE_ERROR_ENC(sde_enc, "invalid splash data\n");
  4168. return -EINVAL;
  4169. }
  4170. for (i = 0; i < priv->num_connectors; i++) {
  4171. SDE_DEBUG_ENC(sde_enc, "connector id: %d\n",
  4172. priv->connectors[i]->base.id);
  4173. sde_conn = to_sde_connector(priv->connectors[i]);
  4174. if (!sde_conn->encoder) {
  4175. SDE_DEBUG_ENC(sde_enc,
  4176. "encoder not attached to connector\n");
  4177. continue;
  4178. }
  4179. if (sde_conn->encoder->base.id
  4180. == encoder->base.id) {
  4181. conn = (priv->connectors[i]);
  4182. break;
  4183. }
  4184. }
  4185. if (!conn || !conn->state) {
  4186. SDE_ERROR_ENC(sde_enc, "connector not found\n");
  4187. return -EINVAL;
  4188. }
  4189. sde_conn_state = to_sde_connector_state(conn->state);
  4190. if (!sde_conn->ops.get_mode_info) {
  4191. SDE_ERROR_ENC(sde_enc, "conn: get_mode_info ops not found\n");
  4192. return -EINVAL;
  4193. }
  4194. ret = sde_connector_get_mode_info(&sde_conn->base,
  4195. &encoder->crtc->state->adjusted_mode,
  4196. &sde_conn_state->mode_info);
  4197. if (ret) {
  4198. SDE_ERROR_ENC(sde_enc,
  4199. "conn: ->get_mode_info failed. ret=%d\n", ret);
  4200. return ret;
  4201. }
  4202. if (sde_conn->encoder) {
  4203. conn->state->best_encoder = sde_conn->encoder;
  4204. SDE_DEBUG_ENC(sde_enc,
  4205. "configured cstate->best_encoder to ID = %d\n",
  4206. conn->state->best_encoder->base.id);
  4207. } else {
  4208. SDE_ERROR_ENC(sde_enc, "No encoder mapped to connector=%d\n",
  4209. conn->base.id);
  4210. }
  4211. ret = sde_rm_reserve(&sde_kms->rm, encoder, encoder->crtc->state,
  4212. conn->state, false);
  4213. if (ret) {
  4214. SDE_ERROR_ENC(sde_enc,
  4215. "failed to reserve hw resources, %d\n", ret);
  4216. return ret;
  4217. }
  4218. SDE_DEBUG_ENC(sde_enc, "connector topology = %llu\n",
  4219. sde_connector_get_topology_name(conn));
  4220. drm_mode = &encoder->crtc->state->adjusted_mode;
  4221. SDE_DEBUG_ENC(sde_enc, "hdisplay = %d, vdisplay = %d\n",
  4222. drm_mode->hdisplay, drm_mode->vdisplay);
  4223. drm_set_preferred_mode(conn, drm_mode->hdisplay, drm_mode->vdisplay);
  4224. if (encoder->bridge) {
  4225. SDE_DEBUG_ENC(sde_enc, "Bridge mapped to encoder\n");
  4226. /*
  4227. * For cont-splash use case, we update the mode
  4228. * configurations manually. This will skip the
  4229. * usually mode set call when actual frame is
  4230. * pushed from framework. The bridge needs to
  4231. * be updated with the current drm mode by
  4232. * calling the bridge mode set ops.
  4233. */
  4234. if (encoder->bridge->funcs) {
  4235. SDE_DEBUG_ENC(sde_enc, "calling mode_set\n");
  4236. encoder->bridge->funcs->mode_set(encoder->bridge,
  4237. drm_mode, drm_mode);
  4238. }
  4239. } else {
  4240. SDE_ERROR_ENC(sde_enc, "No bridge attached to encoder\n");
  4241. }
  4242. _sde_encoder_cache_hw_res_cont_splash(encoder, sde_kms);
  4243. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4244. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4245. if (!phys) {
  4246. SDE_ERROR_ENC(sde_enc,
  4247. "phys encoders not initialized\n");
  4248. return -EINVAL;
  4249. }
  4250. /* update connector for master and slave phys encoders */
  4251. phys->connector = conn;
  4252. phys->cont_splash_enabled = true;
  4253. phys->hw_pp = sde_enc->hw_pp[i];
  4254. if (phys->ops.cont_splash_mode_set)
  4255. phys->ops.cont_splash_mode_set(phys, drm_mode);
  4256. if (phys->ops.is_master && phys->ops.is_master(phys))
  4257. sde_enc->cur_master = phys;
  4258. }
  4259. return ret;
  4260. }
  4261. int sde_encoder_display_failure_notification(struct drm_encoder *enc,
  4262. bool skip_pre_kickoff)
  4263. {
  4264. struct msm_drm_thread *event_thread = NULL;
  4265. struct msm_drm_private *priv = NULL;
  4266. struct sde_encoder_virt *sde_enc = NULL;
  4267. if (!enc || !enc->dev || !enc->dev->dev_private) {
  4268. SDE_ERROR("invalid parameters\n");
  4269. return -EINVAL;
  4270. }
  4271. priv = enc->dev->dev_private;
  4272. sde_enc = to_sde_encoder_virt(enc);
  4273. if (!sde_enc->crtc || (sde_enc->crtc->index
  4274. >= ARRAY_SIZE(priv->event_thread))) {
  4275. SDE_DEBUG_ENC(sde_enc,
  4276. "invalid cached CRTC: %d or crtc index: %d\n",
  4277. sde_enc->crtc == NULL,
  4278. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  4279. return -EINVAL;
  4280. }
  4281. SDE_EVT32_VERBOSE(DRMID(enc));
  4282. event_thread = &priv->event_thread[sde_enc->crtc->index];
  4283. if (!skip_pre_kickoff) {
  4284. kthread_queue_work(&event_thread->worker,
  4285. &sde_enc->esd_trigger_work);
  4286. kthread_flush_work(&sde_enc->esd_trigger_work);
  4287. }
  4288. /*
  4289. * panel may stop generating te signal (vsync) during esd failure. rsc
  4290. * hardware may hang without vsync. Avoid rsc hang by generating the
  4291. * vsync from watchdog timer instead of panel.
  4292. */
  4293. sde_encoder_helper_switch_vsync(enc, true);
  4294. if (!skip_pre_kickoff)
  4295. sde_encoder_wait_for_event(enc, MSM_ENC_TX_COMPLETE);
  4296. return 0;
  4297. }
  4298. bool sde_encoder_recovery_events_enabled(struct drm_encoder *encoder)
  4299. {
  4300. struct sde_encoder_virt *sde_enc;
  4301. if (!encoder) {
  4302. SDE_ERROR("invalid drm enc\n");
  4303. return false;
  4304. }
  4305. sde_enc = to_sde_encoder_virt(encoder);
  4306. return sde_enc->recovery_events_enabled;
  4307. }
  4308. void sde_encoder_recovery_events_handler(struct drm_encoder *encoder,
  4309. bool enabled)
  4310. {
  4311. struct sde_encoder_virt *sde_enc;
  4312. if (!encoder) {
  4313. SDE_ERROR("invalid drm enc\n");
  4314. return;
  4315. }
  4316. sde_enc = to_sde_encoder_virt(encoder);
  4317. sde_enc->recovery_events_enabled = enabled;
  4318. }