Ritesh Kumar ba3d7304f5
disp: pll: Fix cfg1 value when pclk_src_mux parent is updated ...
Currently, PLL_CFG1(1:0) register is updated with cached values
in dsi_pll_enable. This can create issue when UEFI and kernel
cfg1 programming is not same. To fix it, return cached value
of cfg1 when its read in pclk_mux_read, so that pclk_mux_write
is called and cached value is updated.
Change-Id: I1e45ff0685797bf4dd2e3a52af4753425f31edfc
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org >
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