hal_be_generic_api.h 119 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_BE_GENERIC_API_H_
  20. #define _HAL_BE_GENERIC_API_H_
  21. #include <hal_be_hw_headers.h>
  22. #include "hal_be_tx.h"
  23. #include "hal_be_reo.h"
  24. #include <hal_api_mon.h>
  25. #include <hal_generic_api.h>
  26. #include "txmon_tlvs.h"
  27. /*
  28. * Debug macro to print the TLV header tag
  29. */
  30. #define SHOW_DEFINED(x) do {} while (0)
  31. #if defined(WLAN_PKT_CAPTURE_TX_2_0) && !defined(TX_MONITOR_WORD_MASK)
  32. typedef struct tx_fes_setup hal_tx_fes_setup_t;
  33. typedef struct tx_peer_entry hal_tx_peer_entry_t;
  34. typedef struct tx_queue_extension hal_tx_queue_ext_t;
  35. typedef struct tx_msdu_start hal_tx_msdu_start_t;
  36. typedef struct tx_mpdu_start hal_tx_mpdu_start_t;
  37. typedef struct tx_fes_status_end hal_tx_fes_status_end_t;
  38. typedef struct response_end_status hal_response_end_status_t;
  39. typedef struct tx_fes_status_prot hal_tx_fes_status_prot_t;
  40. typedef struct pcu_ppdu_setup_init hal_pcu_ppdu_setup_t;
  41. #endif
  42. #if defined(WLAN_FEATURE_TSF_AUTO_REPORT) || defined(WLAN_CONFIG_TX_DELAY)
  43. static inline void
  44. hal_tx_comp_get_buffer_timestamp_be(void *desc,
  45. struct hal_tx_completion_status *ts)
  46. {
  47. ts->buffer_timestamp = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  48. BUFFER_TIMESTAMP);
  49. }
  50. #else /* !(WLAN_FEATURE_TSF_AUTO_REPORT || WLAN_CONFIG_TX_DELAY) */
  51. static inline void
  52. hal_tx_comp_get_buffer_timestamp_be(void *desc,
  53. struct hal_tx_completion_status *ts)
  54. {
  55. }
  56. #endif /* WLAN_FEATURE_TSF_AUTO_REPORT || WLAN_CONFIG_TX_DELAY */
  57. /**
  58. * hal_tx_comp_get_status_generic_be() - TQM Release reason
  59. * @desc: WBM descriptor
  60. * @ts1: completion ring Tx status
  61. * @hal: hal_soc
  62. *
  63. * This function will parse the WBM completion descriptor and populate in
  64. * HAL structure
  65. *
  66. * Return: none
  67. */
  68. static inline void
  69. hal_tx_comp_get_status_generic_be(void *desc, void *ts1,
  70. struct hal_soc *hal)
  71. {
  72. uint8_t rate_stats_valid = 0;
  73. uint32_t rate_stats = 0;
  74. struct hal_tx_completion_status *ts =
  75. (struct hal_tx_completion_status *)ts1;
  76. ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  77. TQM_STATUS_NUMBER);
  78. ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  79. ACK_FRAME_RSSI);
  80. ts->first_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  81. FIRST_MSDU);
  82. ts->last_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  83. LAST_MSDU);
  84. #if 0
  85. // TODO - This has to be calculated form first and last msdu
  86. ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc,
  87. WBM2SW_COMPLETION_RING_TX,
  88. MSDU_PART_OF_AMSDU);
  89. #endif
  90. ts->peer_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  91. SW_PEER_ID);
  92. ts->tid = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, TID);
  93. ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  94. TRANSMIT_COUNT);
  95. rate_stats = HAL_TX_DESC_GET(desc, HAL_TX_COMP, TX_RATE_STATS);
  96. rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO,
  97. TX_RATE_STATS_INFO_VALID, rate_stats);
  98. ts->valid = rate_stats_valid;
  99. if (rate_stats_valid) {
  100. ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_BW,
  101. rate_stats);
  102. ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO,
  103. TRANSMIT_PKT_TYPE, rate_stats);
  104. ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO,
  105. TRANSMIT_STBC, rate_stats);
  106. ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_LDPC,
  107. rate_stats);
  108. ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_SGI,
  109. rate_stats);
  110. ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_MCS,
  111. rate_stats);
  112. ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO, OFDMA_TRANSMISSION,
  113. rate_stats);
  114. ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO, TONES_IN_RU,
  115. rate_stats);
  116. }
  117. ts->release_src = hal_tx_comp_get_buffer_source_generic_be(desc);
  118. ts->status = hal_tx_comp_get_release_reason(
  119. desc,
  120. hal_soc_to_hal_soc_handle(hal));
  121. ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6,
  122. TX_RATE_STATS_INFO_TX_RATE_STATS);
  123. hal_tx_comp_get_buffer_timestamp_be(desc, ts);
  124. }
  125. /**
  126. * hal_tx_set_pcp_tid_map_generic_be() - Configure default PCP to TID map table
  127. * @soc: HAL SoC context
  128. * @map: PCP-TID mapping table
  129. *
  130. * PCP are mapped to 8 TID values using TID values programmed
  131. * in one set of mapping registers PCP_TID_MAP_<0 to 6>
  132. * The mapping register has TID mapping for 8 PCP values
  133. *
  134. * Return: none
  135. */
  136. static void hal_tx_set_pcp_tid_map_generic_be(struct hal_soc *soc, uint8_t *map)
  137. {
  138. uint32_t addr, value;
  139. addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
  140. MAC_TCL_REG_REG_BASE);
  141. value = (map[0] |
  142. (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) |
  143. (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) |
  144. (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) |
  145. (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) |
  146. (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) |
  147. (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) |
  148. (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT));
  149. HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
  150. }
  151. /**
  152. * hal_tx_update_pcp_tid_generic_be() - Update the pcp tid map table with
  153. * value received from user-space
  154. * @soc: HAL SoC context
  155. * @pcp: pcp value
  156. * @tid : tid value
  157. *
  158. * Return: void
  159. */
  160. static void
  161. hal_tx_update_pcp_tid_generic_be(struct hal_soc *soc,
  162. uint8_t pcp, uint8_t tid)
  163. {
  164. uint32_t addr, value, regval;
  165. addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
  166. MAC_TCL_REG_REG_BASE);
  167. value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp);
  168. /* Read back previous PCP TID config and update
  169. * with new config.
  170. */
  171. regval = HAL_REG_READ(soc, addr);
  172. regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp));
  173. regval |= value;
  174. HAL_REG_WRITE(soc, addr,
  175. (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
  176. }
  177. /**
  178. * hal_tx_update_tidmap_prty_generic_be() - Update the tid map priority
  179. * @soc: HAL SoC context
  180. * @value: priority value
  181. *
  182. * Return: void
  183. */
  184. static
  185. void hal_tx_update_tidmap_prty_generic_be(struct hal_soc *soc, uint8_t value)
  186. {
  187. uint32_t addr;
  188. addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR(
  189. MAC_TCL_REG_REG_BASE);
  190. HAL_REG_WRITE(soc, addr,
  191. (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK));
  192. }
  193. /**
  194. * hal_rx_get_tlv_size_generic_be() - Get rx packet tlv size
  195. * @rx_pkt_tlv_size: TLV size for regular RX packets
  196. * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets
  197. *
  198. * Return: size of rx pkt tlv before the actual data
  199. */
  200. static void hal_rx_get_tlv_size_generic_be(uint16_t *rx_pkt_tlv_size,
  201. uint16_t *rx_mon_pkt_tlv_size)
  202. {
  203. *rx_pkt_tlv_size = RX_PKT_TLVS_LEN;
  204. /* For now mon pkt tlv is same as rx pkt tlv */
  205. *rx_mon_pkt_tlv_size = MON_RX_PKT_TLVS_LEN;
  206. }
  207. /**
  208. * hal_rx_flow_get_tuple_info_be() - Setup a flow search entry in HW FST
  209. * @rx_fst: Pointer to the Rx Flow Search Table
  210. * @hal_hash: HAL 5 tuple hash
  211. * @flow_tuple_info: 5-tuple info of the flow returned to the caller
  212. *
  213. * Return: Success/Failure
  214. */
  215. static void *
  216. hal_rx_flow_get_tuple_info_be(uint8_t *rx_fst, uint32_t hal_hash,
  217. uint8_t *flow_tuple_info)
  218. {
  219. struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
  220. void *hal_fse = NULL;
  221. struct hal_flow_tuple_info *tuple_info
  222. = (struct hal_flow_tuple_info *)flow_tuple_info;
  223. hal_fse = (uint8_t *)fst->base_vaddr +
  224. (hal_hash * HAL_RX_FST_ENTRY_SIZE);
  225. if (!hal_fse || !tuple_info)
  226. return NULL;
  227. if (!HAL_GET_FLD(hal_fse, RX_FLOW_SEARCH_ENTRY, VALID))
  228. return NULL;
  229. tuple_info->src_ip_127_96 =
  230. qdf_ntohl(HAL_GET_FLD(hal_fse,
  231. RX_FLOW_SEARCH_ENTRY,
  232. SRC_IP_127_96));
  233. tuple_info->src_ip_95_64 =
  234. qdf_ntohl(HAL_GET_FLD(hal_fse,
  235. RX_FLOW_SEARCH_ENTRY,
  236. SRC_IP_95_64));
  237. tuple_info->src_ip_63_32 =
  238. qdf_ntohl(HAL_GET_FLD(hal_fse,
  239. RX_FLOW_SEARCH_ENTRY,
  240. SRC_IP_63_32));
  241. tuple_info->src_ip_31_0 =
  242. qdf_ntohl(HAL_GET_FLD(hal_fse,
  243. RX_FLOW_SEARCH_ENTRY,
  244. SRC_IP_31_0));
  245. tuple_info->dest_ip_127_96 =
  246. qdf_ntohl(HAL_GET_FLD(hal_fse,
  247. RX_FLOW_SEARCH_ENTRY,
  248. DEST_IP_127_96));
  249. tuple_info->dest_ip_95_64 =
  250. qdf_ntohl(HAL_GET_FLD(hal_fse,
  251. RX_FLOW_SEARCH_ENTRY,
  252. DEST_IP_95_64));
  253. tuple_info->dest_ip_63_32 =
  254. qdf_ntohl(HAL_GET_FLD(hal_fse,
  255. RX_FLOW_SEARCH_ENTRY,
  256. DEST_IP_63_32));
  257. tuple_info->dest_ip_31_0 =
  258. qdf_ntohl(HAL_GET_FLD(hal_fse,
  259. RX_FLOW_SEARCH_ENTRY,
  260. DEST_IP_31_0));
  261. tuple_info->dest_port = HAL_GET_FLD(hal_fse,
  262. RX_FLOW_SEARCH_ENTRY,
  263. DEST_PORT);
  264. tuple_info->src_port = HAL_GET_FLD(hal_fse,
  265. RX_FLOW_SEARCH_ENTRY,
  266. SRC_PORT);
  267. tuple_info->l4_protocol = HAL_GET_FLD(hal_fse,
  268. RX_FLOW_SEARCH_ENTRY,
  269. L4_PROTOCOL);
  270. return hal_fse;
  271. }
  272. /**
  273. * hal_rx_flow_delete_entry_be() - Setup a flow search entry in HW FST
  274. * @rx_fst: Pointer to the Rx Flow Search Table
  275. * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST
  276. *
  277. * Return: Success/Failure
  278. */
  279. static QDF_STATUS
  280. hal_rx_flow_delete_entry_be(uint8_t *rx_fst, void *hal_rx_fse)
  281. {
  282. uint8_t *fse = (uint8_t *)hal_rx_fse;
  283. if (!HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID))
  284. return QDF_STATUS_E_NOENT;
  285. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
  286. return QDF_STATUS_SUCCESS;
  287. }
  288. /**
  289. * hal_rx_fst_get_fse_size_be() - Retrieve the size of each entry in Rx FST
  290. *
  291. * Return: size of each entry/flow in Rx FST
  292. */
  293. static inline uint32_t
  294. hal_rx_fst_get_fse_size_be(void)
  295. {
  296. return HAL_RX_FST_ENTRY_SIZE;
  297. }
  298. /*
  299. * TX MONITOR
  300. */
  301. #ifdef WLAN_PKT_CAPTURE_TX_2_0
  302. /**
  303. * hal_txmon_is_mon_buf_addr_tlv_generic_be() - api to find mon buffer tlv
  304. * @tx_tlv_hdr: pointer to TLV header
  305. *
  306. * Return: bool based on tlv tag matches monitor buffer address tlv
  307. */
  308. static inline bool
  309. hal_txmon_is_mon_buf_addr_tlv_generic_be(void *tx_tlv_hdr)
  310. {
  311. uint32_t tlv_tag;
  312. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv_hdr);
  313. if (WIFIMON_BUFFER_ADDR_E == tlv_tag)
  314. return true;
  315. return false;
  316. }
  317. /**
  318. * hal_txmon_populate_packet_info_generic_be() - api to populate packet info
  319. * @tx_tlv: pointer to TLV header
  320. * @packet_info: place holder for packet info
  321. *
  322. * Return: Address to void
  323. */
  324. static inline void
  325. hal_txmon_populate_packet_info_generic_be(void *tx_tlv, void *packet_info)
  326. {
  327. struct hal_mon_packet_info *pkt_info;
  328. struct mon_buffer_addr *addr = (struct mon_buffer_addr *)tx_tlv;
  329. pkt_info = (struct hal_mon_packet_info *)packet_info;
  330. pkt_info->sw_cookie = (((uint64_t)addr->buffer_virt_addr_63_32 << 32) |
  331. (addr->buffer_virt_addr_31_0));
  332. pkt_info->dma_length = addr->dma_length + 1;
  333. pkt_info->msdu_continuation = addr->msdu_continuation;
  334. pkt_info->truncated = addr->truncated;
  335. }
  336. /**
  337. * hal_txmon_parse_tx_fes_setup() - parse tx_fes_setup tlv
  338. *
  339. * @tx_tlv: pointer to tx_fes_setup tlv header
  340. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  341. *
  342. * Return: void
  343. */
  344. static inline void
  345. hal_txmon_parse_tx_fes_setup(void *tx_tlv,
  346. struct hal_tx_ppdu_info *tx_ppdu_info)
  347. {
  348. hal_tx_fes_setup_t *tx_fes_setup = (hal_tx_fes_setup_t *)tx_tlv;
  349. tx_ppdu_info->num_users = tx_fes_setup->number_of_users;
  350. if (tx_ppdu_info->num_users == 0)
  351. tx_ppdu_info->num_users = 1;
  352. TXMON_HAL(tx_ppdu_info, ppdu_id) = tx_fes_setup->schedule_id;
  353. TXMON_HAL_STATUS(tx_ppdu_info, ppdu_id) = tx_fes_setup->schedule_id;
  354. }
  355. /**
  356. * hal_txmon_get_num_users() - get num users from tx_fes_setup tlv
  357. *
  358. * @tx_tlv: pointer to tx_fes_setup tlv header
  359. *
  360. * Return: number of users
  361. */
  362. static inline uint8_t
  363. hal_txmon_get_num_users(void *tx_tlv)
  364. {
  365. hal_tx_fes_setup_t *tx_fes_setup = (hal_tx_fes_setup_t *)tx_tlv;
  366. return tx_fes_setup->number_of_users;
  367. }
  368. /**
  369. * hal_txmon_parse_tx_fes_status_end() - parse tx_fes_status_end tlv
  370. *
  371. * @tx_tlv: pointer to tx_fes_status_end tlv header
  372. * @ppdu_info: pointer to hal_tx_ppdu_info
  373. * @tx_status_info: pointer to hal_tx_status_info
  374. *
  375. * Return: void
  376. */
  377. static inline void
  378. hal_txmon_parse_tx_fes_status_end(void *tx_tlv,
  379. struct hal_tx_ppdu_info *ppdu_info,
  380. struct hal_tx_status_info *tx_status_info)
  381. {
  382. hal_tx_fes_status_end_t *tx_fes_end = (hal_tx_fes_status_end_t *)tx_tlv;
  383. if (tx_fes_end->phytx_abort_request_info_valid) {
  384. TXMON_STATUS_INFO(tx_status_info, phy_abort_reason) =
  385. tx_fes_end->phytx_abort_request_info_details.phytx_abort_reason;
  386. TXMON_STATUS_INFO(tx_status_info, phy_abort_user_number) =
  387. tx_fes_end->phytx_abort_request_info_details.user_number;
  388. }
  389. TXMON_STATUS_INFO(tx_status_info,
  390. response_type) = tx_fes_end->response_type;
  391. TXMON_STATUS_INFO(tx_status_info,
  392. r2r_to_follow) = tx_fes_end->r2r_end_status_to_follow;
  393. /* update phy timestamp to ppdu timestamp */
  394. TXMON_HAL_STATUS(ppdu_info, ppdu_timestamp) =
  395. (tx_fes_end->start_of_frame_timestamp_15_0 |
  396. tx_fes_end->start_of_frame_timestamp_31_16 <<
  397. HAL_TX_LSB(TX_FES_STATUS_END, START_OF_FRAME_TIMESTAMP_31_16));
  398. }
  399. /**
  400. * hal_txmon_parse_response_end_status() - parse response_end_status tlv
  401. *
  402. * @tx_tlv: pointer to response_end_status tlv header
  403. * @ppdu_info: pointer to hal_tx_ppdu_info
  404. * @tx_status_info: pointer to hal_tx_status_info
  405. *
  406. * Return: void
  407. */
  408. static inline void
  409. hal_txmon_parse_response_end_status(void *tx_tlv,
  410. struct hal_tx_ppdu_info *ppdu_info,
  411. struct hal_tx_status_info *tx_status_info)
  412. {
  413. hal_response_end_status_t *resp_end_status = NULL;
  414. resp_end_status = (hal_response_end_status_t *)tx_tlv;
  415. TXMON_HAL_STATUS(ppdu_info, bw) = resp_end_status->coex_based_tx_bw;
  416. TXMON_STATUS_INFO(tx_status_info, generated_response) =
  417. resp_end_status->generated_response;
  418. TXMON_STATUS_INFO(tx_status_info, mba_count) =
  419. resp_end_status->mba_user_count;
  420. TXMON_STATUS_INFO(tx_status_info, mba_fake_bitmap_count) =
  421. resp_end_status->mba_fake_bitmap_count;
  422. TXMON_HAL_STATUS(ppdu_info, ppdu_timestamp) =
  423. (resp_end_status->start_of_frame_timestamp_15_0 |
  424. (resp_end_status->start_of_frame_timestamp_31_16 << 16));
  425. }
  426. /**
  427. * hal_txmon_parse_pcu_ppdu_setup_init() - parse pcu_ppdu_setup_init tlv
  428. *
  429. * @tx_tlv: pointer to pcu_ppdu_setup_init tlv header
  430. * @data_status_info: pointer to data hal_tx_status_info
  431. * @prot_status_info: pointer to protection hal_tx_status_info
  432. *
  433. * Return: void
  434. */
  435. static inline void
  436. hal_txmon_parse_pcu_ppdu_setup_init(void *tx_tlv,
  437. struct hal_tx_status_info *data_status_info,
  438. struct hal_tx_status_info *prot_status_info)
  439. {
  440. hal_pcu_ppdu_setup_t *pcu_init = (hal_pcu_ppdu_setup_t *)tx_tlv;
  441. prot_status_info->protection_addr =
  442. pcu_init->use_address_fields_for_protection;
  443. /* protection frame address 1 */
  444. *(uint32_t *)&prot_status_info->addr1[0] =
  445. pcu_init->protection_frame_ad1_31_0;
  446. *(uint16_t *)&prot_status_info->addr1[4] =
  447. pcu_init->protection_frame_ad1_47_32;
  448. /* protection frame address 2 */
  449. *(uint32_t *)&prot_status_info->addr2[0] =
  450. pcu_init->protection_frame_ad2_15_0;
  451. *(uint32_t *)&prot_status_info->addr2[2] =
  452. pcu_init->protection_frame_ad2_47_16;
  453. /* protection frame address 3 */
  454. *(uint32_t *)&prot_status_info->addr3[0] =
  455. pcu_init->protection_frame_ad3_31_0;
  456. *(uint16_t *)&prot_status_info->addr3[4] =
  457. pcu_init->protection_frame_ad3_47_32;
  458. /* protection frame address 4 */
  459. *(uint32_t *)&prot_status_info->addr4[0] =
  460. pcu_init->protection_frame_ad4_15_0;
  461. *(uint32_t *)&prot_status_info->addr4[2] =
  462. pcu_init->protection_frame_ad4_47_16;
  463. }
  464. /**
  465. * hal_txmon_parse_peer_entry() - parse peer entry tlv
  466. *
  467. * @tx_tlv: pointer to peer_entry tlv header
  468. * @user_id: user_id
  469. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  470. * @tx_status_info: pointer to hal_tx_status_info
  471. *
  472. * Return: void
  473. */
  474. static inline void
  475. hal_txmon_parse_peer_entry(void *tx_tlv,
  476. uint8_t user_id,
  477. struct hal_tx_ppdu_info *tx_ppdu_info,
  478. struct hal_tx_status_info *tx_status_info)
  479. {
  480. hal_tx_peer_entry_t *peer_entry = (hal_tx_peer_entry_t *)tx_tlv;
  481. *(uint32_t *)&tx_status_info->addr1[0] =
  482. peer_entry->mac_addr_a_31_0;
  483. *(uint16_t *)&tx_status_info->addr1[4] =
  484. peer_entry->mac_addr_a_47_32;
  485. *(uint32_t *)&tx_status_info->addr2[0] =
  486. peer_entry->mac_addr_b_15_0;
  487. *(uint32_t *)&tx_status_info->addr2[2] =
  488. peer_entry->mac_addr_b_47_16;
  489. TXMON_HAL_USER(tx_ppdu_info, user_id, sw_peer_id) =
  490. peer_entry->sw_peer_id;
  491. }
  492. /**
  493. * hal_txmon_parse_queue_exten() - parse queue exten tlv
  494. *
  495. * @tx_tlv: pointer to queue exten tlv header
  496. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  497. *
  498. * Return: void
  499. */
  500. static inline void
  501. hal_txmon_parse_queue_exten(void *tx_tlv,
  502. struct hal_tx_ppdu_info *tx_ppdu_info)
  503. {
  504. hal_tx_queue_ext_t *queue_ext = (hal_tx_queue_ext_t *)tx_tlv;
  505. TXMON_HAL_STATUS(tx_ppdu_info, frame_control) = queue_ext->frame_ctl;
  506. TXMON_HAL_STATUS(tx_ppdu_info, frame_control_info_valid) = true;
  507. }
  508. /**
  509. * hal_txmon_parse_mpdu_start() - parse mpdu start tlv
  510. *
  511. * @tx_tlv: pointer to mpdu start tlv header
  512. * @user_id: user id
  513. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  514. *
  515. * Return: void
  516. */
  517. static inline void
  518. hal_txmon_parse_mpdu_start(void *tx_tlv, uint8_t user_id,
  519. struct hal_tx_ppdu_info *tx_ppdu_info)
  520. {
  521. hal_tx_mpdu_start_t *mpdu_start = (hal_tx_mpdu_start_t *)tx_tlv;
  522. TXMON_HAL_USER(tx_ppdu_info, user_id, start_seq) =
  523. mpdu_start->mpdu_sequence_number;
  524. TXMON_HAL(tx_ppdu_info, cur_usr_idx) = user_id;
  525. }
  526. /**
  527. * hal_txmon_parse_msdu_start() - parse msdu start tlv
  528. *
  529. * @tx_tlv: pointer to msdu start tlv header
  530. * @user_id: user id
  531. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  532. *
  533. * Return: void
  534. */
  535. static inline void
  536. hal_txmon_parse_msdu_start(void *tx_tlv, uint8_t user_id,
  537. struct hal_tx_ppdu_info *tx_ppdu_info)
  538. {
  539. }
  540. /**
  541. * hal_txmon_parse_tx_fes_status_prot() - parse tx_fes_status_prot tlv
  542. *
  543. * @tx_tlv: pointer to pcu_ppdu_setup_init tlv header
  544. * @ppdu_info: pointer to hal_tx_ppdu_info
  545. * @tx_status_info: pointer to hal_tx_status_info
  546. *
  547. * Return: void
  548. */
  549. static inline void
  550. hal_txmon_parse_tx_fes_status_prot(void *tx_tlv,
  551. struct hal_tx_ppdu_info *ppdu_info,
  552. struct hal_tx_status_info *tx_status_info)
  553. {
  554. hal_tx_fes_status_prot_t *fes_prot = (hal_tx_fes_status_prot_t *)tx_tlv;
  555. TXMON_HAL_STATUS(ppdu_info, ppdu_timestamp) =
  556. (fes_prot->start_of_frame_timestamp_15_0 |
  557. fes_prot->start_of_frame_timestamp_31_16 << 15);
  558. }
  559. /**
  560. * get_ru_offset_from_start_index() - api to get ru offset from ru index
  561. *
  562. * @ru_size: RU size
  563. * @start_idx: Start index
  564. *
  565. * Return: uint8_t ru allocation offset
  566. */
  567. static inline
  568. uint8_t get_ru_offset_from_start_index(uint8_t ru_size, uint8_t start_idx)
  569. {
  570. uint8_t ru_alloc_offset[HAL_MAX_DL_MU_USERS][HAL_MAX_RU_INDEX] = {
  571. {0, 0, 0, 0, 0, 0, 0},
  572. {1, 0, 0, 0, 0, 0, 0},
  573. {2, 1, 0, 0, 0, 0, 0},
  574. {3, 1, 0, 0, 0, 0, 0},
  575. {4, 0, 0, 0, 0, 0, 0},
  576. {5, 2, 1, 0, 0, 0, 0},
  577. {6, 2, 1, 0, 0, 0, 0},
  578. {7, 3, 1, 0, 0, 0, 0},
  579. {8, 3, 1, 0, 0, 0, 0},
  580. {9, 4, 2, 1, 0, 0, 0},
  581. {10, 4, 2, 1, 0, 0, 0},
  582. {11, 5, 2, 1, 0, 0, 0},
  583. {12, 5, 2, 1, 0, 0, 0},
  584. {13, 0, 0, 1, 0, 0, 0},
  585. {14, 6, 3, 1, 0, 0, 0},
  586. {15, 6, 3, 1, 0, 0, 0},
  587. {16, 7, 3, 1, 0, 0, 0},
  588. {17, 7, 3, 1, 0, 0, 0},
  589. {18, 0, 0, 0, 0, 0, 0},
  590. {19, 8, 4, 2, 1, 0, 0},
  591. {20, 8, 4, 2, 1, 0, 0},
  592. {21, 9, 4, 2, 1, 0, 0},
  593. {22, 9, 4, 2, 1, 0, 0},
  594. {23, 0, 0, 2, 1, 0, 0},
  595. {24, 10, 5, 2, 1, 0, 0},
  596. {25, 10, 5, 2, 1, 0, 0},
  597. {26, 11, 5, 2, 1, 0, 0},
  598. {27, 11, 5, 2, 1, 0, 0},
  599. {28, 12, 6, 3, 1, 0, 0},
  600. {29, 12, 6, 3, 1, 0, 0},
  601. {30, 13, 6, 3, 1, 0, 0},
  602. {31, 13, 6, 3, 1, 0, 0},
  603. {32, 0, 0, 3, 1, 0, 0},
  604. {33, 14, 7, 3, 1, 0, 0},
  605. {34, 14, 7, 3, 1, 0, 0},
  606. {35, 15, 7, 3, 1, 0, 0},
  607. {36, 15, 7, 3, 1, 0, 0},
  608. };
  609. if (start_idx >= HAL_MAX_UL_MU_USERS || ru_size >= HAL_MAX_RU_INDEX)
  610. return 0;
  611. return ru_alloc_offset[start_idx][ru_size];
  612. }
  613. /**
  614. * hal_txmon_parse_fw2sw() - parse firmware to software tlv
  615. *
  616. * @tx_tlv: pointer to firmware to software tlvmpdu start tlv header
  617. * @type: place where this tlv is generated
  618. * @status_info: pointer to hal_tx_status_info
  619. *
  620. * Return: void
  621. */
  622. static inline void
  623. hal_txmon_parse_fw2sw(void *tx_tlv, uint8_t type,
  624. struct hal_tx_status_info *status_info)
  625. {
  626. uint32_t *msg = (uint32_t *)tx_tlv;
  627. switch (type) {
  628. case TXMON_FW2SW_TYPE_FES_SETUP:
  629. {
  630. uint32_t schedule_id;
  631. uint16_t c_freq1;
  632. uint16_t c_freq2;
  633. uint16_t freq_mhz;
  634. uint8_t phy_mode;
  635. c_freq1 = TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ1_GET(*msg);
  636. c_freq2 = TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ2_GET(*msg);
  637. msg++;
  638. phy_mode = TXMON_FW2SW_MON_FES_SETUP_PHY_MODE_GET(*msg);
  639. freq_mhz = TXMON_FW2SW_MON_FES_SETUP_MHZ_GET(*msg);
  640. msg++;
  641. schedule_id = TXMON_FW2SW_MON_FES_SETUP_SCHEDULE_ID_GET(*msg);
  642. TXMON_STATUS_INFO(status_info, band_center_freq1) = c_freq1;
  643. TXMON_STATUS_INFO(status_info, band_center_freq2) = c_freq2;
  644. TXMON_STATUS_INFO(status_info, freq) = freq_mhz;
  645. TXMON_STATUS_INFO(status_info, phy_mode) = phy_mode;
  646. TXMON_STATUS_INFO(status_info, schedule_id) = schedule_id;
  647. break;
  648. }
  649. case TXMON_FW2SW_TYPE_FES_SETUP_USER:
  650. {
  651. break;
  652. }
  653. case TXMON_FW2SW_TYPE_FES_SETUP_EXT:
  654. {
  655. break;
  656. }
  657. };
  658. }
  659. /**
  660. * hal_txmon_parse_u_sig_hdr() - parse u_sig header information from tlv
  661. *
  662. * @tx_tlv: pointer to mactx_u_sig_eht_su_mu/tb tlv
  663. * @ppdu_info: pointer to hal_tx_ppdu_info
  664. *
  665. * Return: void
  666. */
  667. static inline void
  668. hal_txmon_parse_u_sig_hdr(void *tx_tlv, struct hal_tx_ppdu_info *ppdu_info)
  669. {
  670. struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)tx_tlv;
  671. struct hal_mon_usig_cmn *usig_1 = &usig->usig_1;
  672. uint8_t bad_usig_crc;
  673. bad_usig_crc = HAL_TX_DESC_GET_64(tx_tlv,
  674. MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS,
  675. CRC) ? 0 : 1;
  676. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  677. QDF_MON_STATUS_USIG_PHY_VERSION_KNOWN |
  678. QDF_MON_STATUS_USIG_BW_KNOWN |
  679. QDF_MON_STATUS_USIG_UL_DL_KNOWN |
  680. QDF_MON_STATUS_USIG_BSS_COLOR_KNOWN |
  681. QDF_MON_STATUS_USIG_TXOP_KNOWN;
  682. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  683. (usig_1->phy_version <<
  684. QDF_MON_STATUS_USIG_PHY_VERSION_SHIFT);
  685. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  686. (usig_1->bw << QDF_MON_STATUS_USIG_BW_SHIFT);
  687. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  688. (usig_1->ul_dl << QDF_MON_STATUS_USIG_UL_DL_SHIFT);
  689. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  690. (usig_1->bss_color <<
  691. QDF_MON_STATUS_USIG_BSS_COLOR_SHIFT);
  692. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  693. (usig_1->txop << QDF_MON_STATUS_USIG_TXOP_SHIFT);
  694. TXMON_HAL_STATUS(ppdu_info, usig_common) |= bad_usig_crc;
  695. TXMON_HAL_STATUS(ppdu_info, bw) = usig_1->bw;
  696. TXMON_HAL_STATUS(ppdu_info, usig_flags) = 1;
  697. }
  698. /**
  699. * hal_txmon_populate_he_data_per_user() - populate he data per user
  700. *
  701. * @usr: pointer to hal_txmon_user_desc_per_user
  702. * @user_id: user index
  703. * @ppdu_info: pointer to hal_tx_ppdu_info
  704. *
  705. * Return: void
  706. */
  707. static inline void
  708. hal_txmon_populate_he_data_per_user(struct hal_txmon_user_desc_per_user *usr,
  709. uint32_t user_id,
  710. struct hal_tx_ppdu_info *ppdu_info)
  711. {
  712. uint32_t he_data1 = TXMON_HAL_USER(ppdu_info, user_id, he_data1);
  713. uint32_t he_data2 = TXMON_HAL_USER(ppdu_info, user_id, he_data2);
  714. uint32_t he_data3 = TXMON_HAL_USER(ppdu_info, user_id, he_data3);
  715. uint32_t he_data5 = TXMON_HAL_USER(ppdu_info, user_id, he_data5);
  716. uint32_t he_data6 = TXMON_HAL_USER(ppdu_info, user_id, he_data6);
  717. /* populate */
  718. /* BEAM CHANGE */
  719. he_data1 |= QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN;
  720. he_data1 |= QDF_MON_STATUS_TXBF_KNOWN;
  721. he_data5 |= (!!usr->user_bf_type << QDF_MON_STATUS_TXBF_SHIFT);
  722. he_data3 |= (!!usr->user_bf_type << QDF_MON_STATUS_BEAM_CHANGE_SHIFT);
  723. /* UL/DL known */
  724. he_data1 |= QDF_MON_STATUS_HE_DL_UL_KNOWN;
  725. he_data3 |= (1 << QDF_MON_STATUS_DL_UL_SHIFT);
  726. /* MCS */
  727. he_data1 |= QDF_MON_STATUS_HE_MCS_KNOWN;
  728. he_data3 |= (usr->mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT);
  729. /* DCM */
  730. he_data1 |= QDF_MON_STATUS_HE_DCM_KNOWN;
  731. he_data3 |= (usr->dcm << QDF_MON_STATUS_DCM_SHIFT);
  732. /* LDPC EXTRA SYMB */
  733. he_data1 |= QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN;
  734. he_data3 |= (usr->ldpc_extra_symbol <<
  735. QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT);
  736. /* RU offset and RU */
  737. he_data2 |= QDF_MON_STATUS_RU_ALLOCATION_OFFSET_KNOWN;
  738. he_data2 |= (get_ru_offset_from_start_index(usr->ru_size,
  739. usr->ru_start_index) <<
  740. QDF_MON_STATUS_RU_ALLOCATION_SHIFT);
  741. /* Data BW and RU allocation */
  742. if (usr->ru_size < HAL_MAX_RU_INDEX) {
  743. /* update bandwidth if it is full bandwidth */
  744. he_data1 |= QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN;
  745. he_data5 = (he_data5 & 0xFFF0) | (4 + usr->ru_size);
  746. }
  747. he_data6 |= (usr->nss & 0xF);
  748. TXMON_HAL_USER(ppdu_info, user_id, mcs) = usr->mcs;
  749. /* update stack variable to ppdu_info */
  750. TXMON_HAL_USER(ppdu_info, user_id, he_data1) = he_data1;
  751. TXMON_HAL_USER(ppdu_info, user_id, he_data2) = he_data2;
  752. TXMON_HAL_USER(ppdu_info, user_id, he_data3) = he_data3;
  753. TXMON_HAL_USER(ppdu_info, user_id, he_data5) = he_data5;
  754. TXMON_HAL_USER(ppdu_info, user_id, he_data6) = he_data6;
  755. }
  756. /**
  757. * hal_txmon_get_user_desc_per_user() - get mactx user desc per user from tlv
  758. *
  759. * @tx_tlv: pointer to mactx_user_desc_per_user tlv
  760. * @usr: pointer to hal_txmon_user_desc_per_user
  761. *
  762. * Return: void
  763. */
  764. static inline void
  765. hal_txmon_get_user_desc_per_user(void *tx_tlv,
  766. struct hal_txmon_user_desc_per_user *usr)
  767. {
  768. usr->psdu_length = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  769. PSDU_LENGTH);
  770. usr->ru_start_index = HAL_TX_DESC_GET_64(tx_tlv,
  771. MACTX_USER_DESC_PER_USER,
  772. RU_START_INDEX);
  773. usr->ru_size = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  774. RU_SIZE);
  775. usr->ofdma_mu_mimo_enabled =
  776. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  777. OFDMA_MU_MIMO_ENABLED);
  778. usr->nss = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  779. NSS) + 1;
  780. usr->stream_offset = HAL_TX_DESC_GET_64(tx_tlv,
  781. MACTX_USER_DESC_PER_USER,
  782. STREAM_OFFSET);
  783. usr->mcs = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, MCS);
  784. usr->dcm = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, DCM);
  785. usr->fec_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  786. FEC_TYPE);
  787. usr->user_bf_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  788. USER_BF_TYPE);
  789. usr->drop_user_cbf = HAL_TX_DESC_GET_64(tx_tlv,
  790. MACTX_USER_DESC_PER_USER,
  791. DROP_USER_CBF);
  792. usr->ldpc_extra_symbol = HAL_TX_DESC_GET_64(tx_tlv,
  793. MACTX_USER_DESC_PER_USER,
  794. LDPC_EXTRA_SYMBOL);
  795. usr->force_extra_symbol = HAL_TX_DESC_GET_64(tx_tlv,
  796. MACTX_USER_DESC_PER_USER,
  797. FORCE_EXTRA_SYMBOL);
  798. usr->sw_peer_id = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  799. SW_PEER_ID);
  800. }
  801. /**
  802. * hal_txmon_populate_eht_sig_per_user() - populate eht sig user information
  803. *
  804. * @usr: pointer to hal_txmon_user_desc_per_user
  805. * @user_id: user index
  806. * @ppdu_info: pointer to hal_tx_ppdu_info
  807. *
  808. * Return: void
  809. */
  810. static inline void
  811. hal_txmon_populate_eht_sig_per_user(struct hal_txmon_user_desc_per_user *usr,
  812. uint32_t user_id,
  813. struct hal_tx_ppdu_info *ppdu_info)
  814. {
  815. uint32_t eht_known = 0;
  816. uint32_t eht_data[6] = {0};
  817. uint8_t i = 0;
  818. eht_known = QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_KNOWN;
  819. eht_data[0] |= (usr->ldpc_extra_symbol <<
  820. QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_SHIFT);
  821. TXMON_HAL_STATUS(ppdu_info, eht_known) |= eht_known;
  822. for (i = 0; i < 6; i++)
  823. TXMON_HAL_STATUS(ppdu_info, eht_data[i]) |= eht_data[i];
  824. }
  825. /**
  826. * hal_txmon_parse_user_desc_per_user() - parse mactx user desc per user
  827. *
  828. * @tx_tlv: pointer to mactx_user_desc_per_user tlv
  829. * @user_id: user index
  830. * @ppdu_info: pointer to hal_tx_ppdu_info
  831. *
  832. * Return: void
  833. */
  834. static inline void
  835. hal_txmon_parse_user_desc_per_user(void *tx_tlv, uint32_t user_id,
  836. struct hal_tx_ppdu_info *ppdu_info)
  837. {
  838. struct hal_txmon_user_desc_per_user usr_info = {0};
  839. hal_txmon_get_user_desc_per_user(tx_tlv, &usr_info);
  840. /* based on preamble type populate user desc user info */
  841. if (TXMON_HAL_STATUS(ppdu_info, he_flags))
  842. hal_txmon_populate_he_data_per_user(&usr_info,
  843. user_id, ppdu_info);
  844. hal_txmon_populate_eht_sig_per_user(&usr_info, user_id, ppdu_info);
  845. }
  846. /**
  847. * hal_txmon_get_user_desc_common() - update hal_txmon_usr_desc_common from tlv
  848. *
  849. * @tx_tlv: pointer to mactx_user_desc_common tlv
  850. * @usr_common: pointer to hal_txmon_usr_desc_common
  851. *
  852. * Return: void
  853. */
  854. static inline void
  855. hal_txmon_get_user_desc_common(void *tx_tlv,
  856. struct hal_txmon_usr_desc_common *usr_common)
  857. {
  858. usr_common->ltf_size =
  859. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, LTF_SIZE);
  860. usr_common->pkt_extn_pe =
  861. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  862. PACKET_EXTENSION_PE_DISAMBIGUITY);
  863. usr_common->a_factor =
  864. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  865. PACKET_EXTENSION_A_FACTOR);
  866. usr_common->center_ru_0 =
  867. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, CENTER_RU_0);
  868. usr_common->center_ru_1 =
  869. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, CENTER_RU_1);
  870. usr_common->num_ltf_symbols =
  871. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  872. NUM_LTF_SYMBOLS);
  873. usr_common->doppler_indication =
  874. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  875. DOPPLER_INDICATION);
  876. usr_common->spatial_reuse =
  877. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  878. SPATIAL_REUSE);
  879. usr_common->ru_channel_0[0] =
  880. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  881. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0);
  882. usr_common->ru_channel_0[1] =
  883. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  884. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1);
  885. usr_common->ru_channel_0[2] =
  886. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  887. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2);
  888. usr_common->ru_channel_0[3] =
  889. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  890. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3);
  891. usr_common->ru_channel_0[4] =
  892. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  893. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0);
  894. usr_common->ru_channel_0[5] =
  895. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  896. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1);
  897. usr_common->ru_channel_0[6] =
  898. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  899. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2);
  900. usr_common->ru_channel_0[7] =
  901. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  902. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3);
  903. usr_common->ru_channel_1[0] =
  904. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  905. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0);
  906. usr_common->ru_channel_1[1] =
  907. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  908. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1);
  909. usr_common->ru_channel_1[2] =
  910. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  911. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2);
  912. usr_common->ru_channel_1[3] =
  913. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  914. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3);
  915. usr_common->ru_channel_1[4] =
  916. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  917. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0);
  918. usr_common->ru_channel_1[5] =
  919. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  920. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1);
  921. usr_common->ru_channel_1[6] =
  922. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  923. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2);
  924. usr_common->ru_channel_1[7] =
  925. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  926. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3);
  927. }
  928. /**
  929. * hal_txmon_populate_he_data_common() - populate he data common information
  930. *
  931. * @usr_common: pointer to hal_txmon_usr_desc_common
  932. * @user_id: user index
  933. * @ppdu_info: pointer to hal_tx_ppdu_info
  934. *
  935. * Return: void
  936. */
  937. static inline void
  938. hal_txmon_populate_he_data_common(struct hal_txmon_usr_desc_common *usr_common,
  939. uint32_t user_id,
  940. struct hal_tx_ppdu_info *ppdu_info)
  941. {
  942. /* HE data 1 */
  943. TXMON_HAL_USER(ppdu_info,
  944. user_id, he_data1) |= QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  945. /* HE data 2 */
  946. TXMON_HAL_USER(ppdu_info, user_id,
  947. he_data2) |= (QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  948. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN);
  949. /* HE data 5 */
  950. TXMON_HAL_USER(ppdu_info, user_id, he_data5) |=
  951. (usr_common->pkt_extn_pe <<
  952. QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT) |
  953. (usr_common->a_factor << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT) |
  954. ((1 + usr_common->ltf_size) <<
  955. QDF_MON_STATUS_HE_LTF_SIZE_SHIFT) |
  956. (usr_common->num_ltf_symbols <<
  957. QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
  958. /* HE data 6 */
  959. TXMON_HAL_USER(ppdu_info, user_id,
  960. he_data6) |= (usr_common->doppler_indication <<
  961. QDF_MON_STATUS_DOPPLER_SHIFT);
  962. }
  963. /**
  964. * hal_txmon_populate_he_mu_common() - populate he mu common information
  965. *
  966. * @usr_common: pointer to hal_txmon_usr_desc_common
  967. * @user_id: user index
  968. * @ppdu_info: pointer to hal_tx_ppdu_info
  969. *
  970. * Return: void
  971. */
  972. static inline void
  973. hal_txmon_populate_he_mu_common(struct hal_txmon_usr_desc_common *usr_common,
  974. uint32_t user_id,
  975. struct hal_tx_ppdu_info *ppdu_info)
  976. {
  977. uint16_t he_mu_flag_1 = 0;
  978. uint16_t he_mu_flag_2 = 0;
  979. uint16_t i = 0;
  980. he_mu_flag_1 |= (QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN |
  981. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN |
  982. ((usr_common->center_ru_0 <<
  983. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_SHIFT) &
  984. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_VALUE));
  985. he_mu_flag_2 |= ((usr_common->center_ru_1 <<
  986. QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_SHIFT) &
  987. QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_VALUE);
  988. for (i = 0; i < usr_common->num_users; i++) {
  989. TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1;
  990. TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2;
  991. /* channel 1 */
  992. TXMON_HAL_USER(ppdu_info, i, he_RU[0]) =
  993. usr_common->ru_channel_0[0];
  994. TXMON_HAL_USER(ppdu_info, i, he_RU[1]) =
  995. usr_common->ru_channel_0[1];
  996. TXMON_HAL_USER(ppdu_info, i, he_RU[2]) =
  997. usr_common->ru_channel_0[2];
  998. TXMON_HAL_USER(ppdu_info, i, he_RU[3]) =
  999. usr_common->ru_channel_0[3];
  1000. /* channel 2 */
  1001. TXMON_HAL_USER(ppdu_info, i, he_RU[4]) =
  1002. usr_common->ru_channel_1[0];
  1003. TXMON_HAL_USER(ppdu_info, i, he_RU[5]) =
  1004. usr_common->ru_channel_1[1];
  1005. TXMON_HAL_USER(ppdu_info, i, he_RU[6]) =
  1006. usr_common->ru_channel_1[2];
  1007. TXMON_HAL_USER(ppdu_info, i, he_RU[7]) =
  1008. usr_common->ru_channel_1[3];
  1009. }
  1010. }
  1011. /**
  1012. * hal_txmon_populate_eht_sig_common() - populate eht sig common information
  1013. *
  1014. * @usr_common: pointer to hal_txmon_usr_desc_common
  1015. * @user_id: user index
  1016. * @ppdu_info: pointer to hal_tx_ppdu_info
  1017. *
  1018. * Return: void
  1019. */
  1020. static inline void
  1021. hal_txmon_populate_eht_sig_common(struct hal_txmon_usr_desc_common *usr_common,
  1022. uint32_t user_id,
  1023. struct hal_tx_ppdu_info *ppdu_info)
  1024. {
  1025. uint32_t eht_known = 0;
  1026. uint32_t eht_data[9] = {0};
  1027. uint8_t num_ru_allocation_known = 0;
  1028. uint8_t i = 0;
  1029. eht_known = (QDF_MON_STATUS_EHT_SPATIAL_REUSE_KNOWN |
  1030. QDF_MON_STATUS_EHT_EHT_LTF_KNOWN |
  1031. QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_KNOWN |
  1032. QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_KNOWN |
  1033. QDF_MON_STATUS_EHT_DISREARD_KNOWN);
  1034. eht_data[0] |= (usr_common->spatial_reuse <<
  1035. QDF_MON_STATUS_EHT_SPATIAL_REUSE_SHIFT);
  1036. eht_data[0] |= (usr_common->num_ltf_symbols <<
  1037. QDF_MON_STATUS_EHT_EHT_LTF_SHIFT);
  1038. eht_data[0] |= (usr_common->a_factor <<
  1039. QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_SHIFT);
  1040. eht_data[0] |= (usr_common->pkt_extn_pe <<
  1041. QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_SHIFT);
  1042. eht_data[0] |= (0xF << QDF_MON_STATUS_EHT_DISREGARD_SHIFT);
  1043. switch (TXMON_HAL_STATUS(ppdu_info, bw)) {
  1044. case HAL_EHT_BW_320_2:
  1045. case HAL_EHT_BW_320_1:
  1046. num_ru_allocation_known += 4;
  1047. eht_data[3] |= (usr_common->ru_channel_0[7] <<
  1048. QDF_MON_STATUS_EHT_RU_ALLOCATION2_6_SHIFT);
  1049. eht_data[3] |= (usr_common->ru_channel_0[6] <<
  1050. QDF_MON_STATUS_EHT_RU_ALLOCATION2_5_SHIFT);
  1051. eht_data[3] |= (usr_common->ru_channel_0[5] <<
  1052. QDF_MON_STATUS_EHT_RU_ALLOCATION2_4_SHIFT);
  1053. eht_data[2] |= (usr_common->ru_channel_0[4] <<
  1054. QDF_MON_STATUS_EHT_RU_ALLOCATION2_3_SHIFT);
  1055. fallthrough;
  1056. case HAL_EHT_BW_160:
  1057. num_ru_allocation_known += 2;
  1058. eht_data[2] |= (usr_common->ru_channel_0[3] <<
  1059. QDF_MON_STATUS_EHT_RU_ALLOCATION2_2_SHIFT);
  1060. eht_data[2] |= (usr_common->ru_channel_0[2] <<
  1061. QDF_MON_STATUS_EHT_RU_ALLOCATION2_1_SHIFT);
  1062. fallthrough;
  1063. case HAL_EHT_BW_80:
  1064. num_ru_allocation_known += 1;
  1065. eht_data[1] |= (usr_common->ru_channel_0[1] <<
  1066. QDF_MON_STATUS_EHT_RU_ALLOCATION1_2_SHIFT);
  1067. fallthrough;
  1068. case HAL_EHT_BW_40:
  1069. case HAL_EHT_BW_20:
  1070. num_ru_allocation_known += 1;
  1071. eht_data[1] |= (usr_common->ru_channel_0[0] <<
  1072. QDF_MON_STATUS_EHT_RU_ALLOCATION1_1_SHIFT);
  1073. break;
  1074. default:
  1075. break;
  1076. }
  1077. eht_known |= (num_ru_allocation_known <<
  1078. QDF_MON_STATUS_EHT_NUM_KNOWN_RU_ALLOCATIONS_SHIFT);
  1079. TXMON_HAL_STATUS(ppdu_info, eht_known) |= eht_known;
  1080. for (i = 0; i < 4; i++)
  1081. TXMON_HAL_STATUS(ppdu_info, eht_data[i]) |= eht_data[i];
  1082. }
  1083. /**
  1084. * hal_txmon_parse_user_desc_common() - parse mactx user desc common tlv
  1085. *
  1086. * @tx_tlv: pointer to mactx_user_desc_common tlv
  1087. * @user_id: user index
  1088. * @ppdu_info: pointer to hal_tx_ppdu_info
  1089. *
  1090. * Return: void
  1091. */
  1092. static inline void
  1093. hal_txmon_parse_user_desc_common(void *tx_tlv, uint32_t user_id,
  1094. struct hal_tx_ppdu_info *ppdu_info)
  1095. {
  1096. struct hal_txmon_usr_desc_common usr_common = {0};
  1097. usr_common.num_users = TXMON_HAL(ppdu_info, num_users);
  1098. hal_txmon_get_user_desc_common(tx_tlv, &usr_common);
  1099. TXMON_HAL_STATUS(ppdu_info,
  1100. he_mu_flags) = IS_MULTI_USERS(usr_common.num_users);
  1101. switch (TXMON_HAL_STATUS(ppdu_info, preamble_type)) {
  1102. case TXMON_PKT_TYPE_11AX:
  1103. if (TXMON_HAL_STATUS(ppdu_info, he_flags))
  1104. hal_txmon_populate_he_data_common(&usr_common,
  1105. user_id, ppdu_info);
  1106. if (TXMON_HAL_STATUS(ppdu_info, he_mu_flags))
  1107. hal_txmon_populate_he_mu_common(&usr_common,
  1108. user_id, ppdu_info);
  1109. break;
  1110. case TXMON_PKT_TYPE_11BE:
  1111. hal_txmon_populate_eht_sig_common(&usr_common,
  1112. user_id, ppdu_info);
  1113. break;
  1114. }
  1115. }
  1116. /**
  1117. * hal_txmon_parse_eht_sig_non_mumimo_user_info() - parse eht sig non mumimo tlv
  1118. *
  1119. * @tx_tlv: pointer to hal_eht_sig_non_mu_mimo_user_info
  1120. * @user_id: user index
  1121. * @ppdu_info: pointer to hal_tx_ppdu_info
  1122. *
  1123. * Return: void
  1124. */
  1125. static inline void
  1126. hal_txmon_parse_eht_sig_non_mumimo_user_info(void *tx_tlv, uint32_t user_id,
  1127. struct hal_tx_ppdu_info *ppdu_info)
  1128. {
  1129. struct hal_eht_sig_non_mu_mimo_user_info *user_info;
  1130. uint32_t idx = TXMON_HAL_STATUS(ppdu_info, num_eht_user_info_valid);
  1131. user_info = (struct hal_eht_sig_non_mu_mimo_user_info *)tx_tlv;
  1132. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1133. QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN |
  1134. QDF_MON_STATUS_EHT_USER_MCS_KNOWN |
  1135. QDF_MON_STATUS_EHT_USER_CODING_KNOWN |
  1136. QDF_MON_STATUS_EHT_USER_NSS_KNOWN |
  1137. QDF_MON_STATUS_EHT_USER_BEAMFORMING_KNOWN;
  1138. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1139. (user_info->sta_id <<
  1140. QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT);
  1141. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1142. (user_info->mcs <<
  1143. QDF_MON_STATUS_EHT_USER_MCS_SHIFT);
  1144. TXMON_HAL_STATUS(ppdu_info, mcs) = user_info->mcs;
  1145. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1146. (user_info->nss <<
  1147. QDF_MON_STATUS_EHT_USER_NSS_SHIFT);
  1148. TXMON_HAL_STATUS(ppdu_info, nss) = user_info->nss + 1;
  1149. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1150. (user_info->beamformed <<
  1151. QDF_MON_STATUS_EHT_USER_BEAMFORMING_SHIFT);
  1152. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1153. (user_info->coding <<
  1154. QDF_MON_STATUS_EHT_USER_CODING_SHIFT);
  1155. /* TODO: CRC */
  1156. TXMON_HAL_STATUS(ppdu_info, num_eht_user_info_valid) += 1;
  1157. }
  1158. /**
  1159. * hal_txmon_parse_eht_sig_mumimo_user_info() - parse eht sig mumimo tlv
  1160. *
  1161. * @tx_tlv: pointer to hal_eht_sig_mu_mimo_user_info
  1162. * @user_id: user index
  1163. * @ppdu_info: pointer to hal_tx_ppdu_info
  1164. *
  1165. * Return: void
  1166. */
  1167. static inline void
  1168. hal_txmon_parse_eht_sig_mumimo_user_info(void *tx_tlv, uint32_t user_id,
  1169. struct hal_tx_ppdu_info *ppdu_info)
  1170. {
  1171. struct hal_eht_sig_mu_mimo_user_info *user_info;
  1172. uint32_t idx = TXMON_HAL_STATUS(ppdu_info, num_eht_user_info_valid);
  1173. user_info = (struct hal_eht_sig_mu_mimo_user_info *)tx_tlv;
  1174. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1175. QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN |
  1176. QDF_MON_STATUS_EHT_USER_MCS_KNOWN |
  1177. QDF_MON_STATUS_EHT_USER_CODING_KNOWN |
  1178. QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_KNOWN;
  1179. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1180. (user_info->sta_id <<
  1181. QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT);
  1182. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1183. (user_info->mcs <<
  1184. QDF_MON_STATUS_EHT_USER_MCS_SHIFT);
  1185. TXMON_HAL_STATUS(ppdu_info, mcs) = user_info->mcs;
  1186. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1187. (user_info->coding <<
  1188. QDF_MON_STATUS_EHT_USER_CODING_SHIFT);
  1189. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1190. (user_info->spatial_coding <<
  1191. QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_SHIFT);
  1192. /* TODO: CRC */
  1193. TXMON_HAL_STATUS(ppdu_info, num_eht_user_info_valid) += 1;
  1194. }
  1195. /**
  1196. * hal_txmon_status_get_num_users_generic_be() - api to get num users
  1197. * from start of fes window
  1198. *
  1199. * @tx_tlv_hdr: pointer to TLV header
  1200. * @num_users: reference to number of user
  1201. *
  1202. * Return: status
  1203. */
  1204. static inline uint32_t
  1205. hal_txmon_status_get_num_users_generic_be(void *tx_tlv_hdr, uint8_t *num_users)
  1206. {
  1207. uint32_t tlv_tag, user_id, tlv_len;
  1208. uint32_t tlv_status = HAL_MON_TX_STATUS_PPDU_NOT_DONE;
  1209. void *tx_tlv;
  1210. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv_hdr);
  1211. user_id = HAL_RX_GET_USER_TLV32_USERID(tx_tlv_hdr);
  1212. tlv_len = HAL_RX_GET_USER_TLV32_LEN(tx_tlv_hdr);
  1213. tx_tlv = (uint8_t *)tx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE;
  1214. /* window starts with either initiator or response */
  1215. switch (tlv_tag) {
  1216. case WIFITX_FES_SETUP_E:
  1217. {
  1218. *num_users = hal_txmon_get_num_users(tx_tlv);
  1219. if (*num_users == 0)
  1220. *num_users = 1;
  1221. tlv_status = HAL_MON_TX_FES_SETUP;
  1222. break;
  1223. }
  1224. case WIFIRX_RESPONSE_REQUIRED_INFO_E:
  1225. {
  1226. *num_users = HAL_TX_DESC_GET_64(tx_tlv,
  1227. RX_RESPONSE_REQUIRED_INFO,
  1228. RESPONSE_STA_COUNT);
  1229. if (*num_users == 0)
  1230. *num_users = 1;
  1231. tlv_status = HAL_MON_RX_RESPONSE_REQUIRED_INFO;
  1232. break;
  1233. }
  1234. };
  1235. return tlv_status;
  1236. }
  1237. #ifdef MONITOR_TLV_RECORDING_ENABLE
  1238. static inline void
  1239. hal_tx_tlv_record_set_data_ppdu_info(struct hal_tx_ppdu_info *ppdu_info)
  1240. {
  1241. ppdu_info->tx_tlv_info.is_data_ppdu_info = 1;
  1242. }
  1243. #else
  1244. static inline void
  1245. hal_tx_tlv_record_set_data_ppdu_info(struct hal_tx_ppdu_info *ppdu_info)
  1246. {
  1247. }
  1248. #endif
  1249. /**
  1250. * hal_txmon_get_word_mask_generic_be() - api to get word mask for tx monitor
  1251. * @wmask: pointer to hal_txmon_word_mask_config_t
  1252. *
  1253. * Return: void
  1254. */
  1255. static inline
  1256. void hal_txmon_get_word_mask_generic_be(void *wmask)
  1257. {
  1258. hal_txmon_word_mask_config_t *word_mask = NULL;
  1259. word_mask = (hal_txmon_word_mask_config_t *)wmask;
  1260. qdf_mem_set(word_mask, sizeof(hal_txmon_word_mask_config_t), 0xFF);
  1261. word_mask->compaction_enable = 0;
  1262. }
  1263. /**
  1264. * hal_tx_get_ppdu_info() - api to get tx ppdu info
  1265. * @data_info: populate dp_ppdu_info data
  1266. * @prot_info: populate dp_ppdu_info protection
  1267. * @tlv_tag: Tag
  1268. *
  1269. * Return: dp_tx_ppdu_info pointer
  1270. */
  1271. static inline void *
  1272. hal_tx_get_ppdu_info(void *data_info, void *prot_info, uint32_t tlv_tag)
  1273. {
  1274. struct hal_tx_ppdu_info *prot_ppdu_info = prot_info;
  1275. switch (tlv_tag) {
  1276. case WIFITX_FES_SETUP_E:/* DOWNSTREAM */
  1277. case WIFITX_FLUSH_E:/* DOWNSTREAM */
  1278. case WIFIPCU_PPDU_SETUP_INIT_E:/* DOWNSTREAM */
  1279. case WIFITX_PEER_ENTRY_E:/* DOWNSTREAM */
  1280. case WIFITX_QUEUE_EXTENSION_E:/* DOWNSTREAM */
  1281. case WIFITX_MPDU_START_E:/* DOWNSTREAM */
  1282. case WIFITX_MSDU_START_E:/* DOWNSTREAM */
  1283. case WIFITX_DATA_E:/* DOWNSTREAM */
  1284. case WIFIMON_BUFFER_ADDR_E:/* DOWNSTREAM */
  1285. case WIFITX_MPDU_END_E:/* DOWNSTREAM */
  1286. case WIFITX_MSDU_END_E:/* DOWNSTREAM */
  1287. case WIFITX_LAST_MPDU_FETCHED_E:/* DOWNSTREAM */
  1288. case WIFITX_LAST_MPDU_END_E:/* DOWNSTREAM */
  1289. case WIFICOEX_TX_REQ_E:/* DOWNSTREAM */
  1290. case WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E:/* DOWNSTREAM */
  1291. case WIFINDP_PREAMBLE_DONE_E:/* DOWNSTREAM */
  1292. case WIFISCH_CRITICAL_TLV_REFERENCE_E:/* DOWNSTREAM */
  1293. case WIFITX_LOOPBACK_SETUP_E:/* DOWNSTREAM */
  1294. case WIFITX_FES_SETUP_COMPLETE_E:/* DOWNSTREAM */
  1295. case WIFITQM_MPDU_GLOBAL_START_E:/* DOWNSTREAM */
  1296. case WIFITX_WUR_DATA_E:/* DOWNSTREAM */
  1297. case WIFISCHEDULER_END_E:/* DOWNSTREAM */
  1298. case WIFITX_FES_STATUS_START_PPDU_E:/* UPSTREAM */
  1299. {
  1300. hal_tx_tlv_record_set_data_ppdu_info(data_info);
  1301. return data_info;
  1302. }
  1303. }
  1304. /*
  1305. * check current prot_tlv_status is start protection
  1306. * check current tlv_tag is either start protection or end protection
  1307. */
  1308. if (TXMON_HAL(prot_ppdu_info,
  1309. prot_tlv_status) == WIFITX_FES_STATUS_START_PROT_E) {
  1310. return prot_info;
  1311. } else if (tlv_tag == WIFITX_FES_STATUS_PROT_E ||
  1312. tlv_tag == WIFITX_FES_STATUS_START_PROT_E) {
  1313. TXMON_HAL(prot_ppdu_info, prot_tlv_status) = tlv_tag;
  1314. return prot_info;
  1315. }
  1316. hal_tx_tlv_record_set_data_ppdu_info(data_info);
  1317. return data_info;
  1318. }
  1319. #ifdef MONITOR_TLV_RECORDING_ENABLE
  1320. static inline void
  1321. hal_tx_record_tlv_info(struct hal_tx_ppdu_info *ppdu_info,
  1322. uint32_t tlv_tag)
  1323. {
  1324. ppdu_info->tx_tlv_info.tlv_tag = tlv_tag;
  1325. switch (tlv_tag) {
  1326. case WIFITX_FES_SETUP_E:
  1327. case WIFITXPCU_BUFFER_STATUS_E:
  1328. case WIFIPCU_PPDU_SETUP_INIT_E:
  1329. case WIFISCH_CRITICAL_TLV_REFERENCE_E:
  1330. case WIFITX_PEER_ENTRY_E:
  1331. case WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E:
  1332. case WIFITX_QUEUE_EXTENSION_E:
  1333. case WIFITX_FES_SETUP_COMPLETE_E:
  1334. case WIFIFW2SW_MON_E:
  1335. case WIFISCHEDULER_END_E:
  1336. case WIFITQM_MPDU_GLOBAL_START_E:
  1337. ppdu_info->tx_tlv_info.tlv_category = CATEGORY_PPDU_START;
  1338. break;
  1339. case WIFITX_MPDU_START_E:
  1340. case WIFITX_MSDU_START_E:
  1341. case WIFITX_DATA_E:
  1342. case WIFITX_MSDU_END_E:
  1343. case WIFITX_MPDU_END_E:
  1344. ppdu_info->tx_tlv_info.tlv_category = CATEGORY_MPDU;
  1345. break;
  1346. case WIFITX_LAST_MPDU_FETCHED_E:
  1347. case WIFITX_LAST_MPDU_END_E:
  1348. case WIFIPDG_TX_REQ_E:
  1349. case WIFITX_FES_STATUS_START_PPDU_E:
  1350. case WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E:
  1351. case WIFIMACTX_L_SIG_A_E:
  1352. case WIFITXPCU_PREAMBLE_DONE_E:
  1353. case WIFIMACTX_USER_DESC_COMMON_E:
  1354. case WIFIMACTX_SERVICE_E:
  1355. case WIFITXDMA_STOP_REQUEST_E:
  1356. case WIFITXPCU_USER_BUFFER_STATUS_E:
  1357. case WIFITX_FES_STATUS_USER_PPDU_E:
  1358. case WIFITX_MPDU_COUNT_TRANSFER_END_E:
  1359. case WIFIRX_START_PARAM_E:
  1360. case WIFITX_FES_STATUS_ACK_OR_BA_E:
  1361. case WIFITX_FES_STATUS_USER_RESPONSE_E:
  1362. case WIFITX_FES_STATUS_END_E:
  1363. case WIFITX_FES_STATUS_PROT_E:
  1364. case WIFIMACTX_PHY_DESC_E:
  1365. case WIFIMACTX_HE_SIG_A_SU_E:
  1366. ppdu_info->tx_tlv_info.tlv_category = CATEGORY_PPDU_END;
  1367. break;
  1368. }
  1369. }
  1370. #else
  1371. static inline void
  1372. hal_tx_record_tlv_info(struct hal_tx_ppdu_info *ppdu_info,
  1373. uint32_t tlv_tag)
  1374. {
  1375. }
  1376. #endif
  1377. /**
  1378. * hal_txmon_status_parse_tlv_generic_be() - api to parse status tlv.
  1379. * @data_ppdu_info: hal_txmon data ppdu info
  1380. * @prot_ppdu_info: hal_txmon prot ppdu info
  1381. * @data_status_info: pointer to data status info
  1382. * @prot_status_info: pointer to prot status info
  1383. * @tx_tlv_hdr: fragment of tx_tlv_hdr
  1384. * @status_frag: qdf_frag_t buffer
  1385. *
  1386. * Return: status
  1387. */
  1388. static inline uint32_t
  1389. hal_txmon_status_parse_tlv_generic_be(void *data_ppdu_info,
  1390. void *prot_ppdu_info,
  1391. void *data_status_info,
  1392. void *prot_status_info,
  1393. void *tx_tlv_hdr,
  1394. qdf_frag_t status_frag)
  1395. {
  1396. struct hal_tx_ppdu_info *ppdu_info;
  1397. struct hal_tx_status_info *tx_status_info;
  1398. struct hal_mon_packet_info *packet_info = NULL;
  1399. uint32_t tlv_tag, user_id, tlv_len, tlv_user_id;
  1400. uint32_t status = HAL_MON_TX_STATUS_PPDU_NOT_DONE;
  1401. void *tx_tlv;
  1402. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv_hdr);
  1403. tlv_user_id = HAL_RX_GET_USER_TLV32_USERID(tx_tlv_hdr);
  1404. tlv_len = HAL_RX_GET_USER_TLV32_LEN(tx_tlv_hdr);
  1405. tx_tlv = (uint8_t *)tx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE;
  1406. /* parse tlv and populate tx_ppdu_info */
  1407. ppdu_info = hal_tx_get_ppdu_info(data_ppdu_info,
  1408. prot_ppdu_info, tlv_tag);
  1409. tx_status_info = (ppdu_info->is_data ? data_status_info :
  1410. prot_status_info);
  1411. user_id = (tlv_user_id > ppdu_info->num_users ? 0 : tlv_user_id);
  1412. hal_tx_record_tlv_info(ppdu_info, tlv_tag);
  1413. switch (tlv_tag) {
  1414. /* start of initiator FES window */
  1415. case WIFITX_FES_SETUP_E:/* DOWNSTREAM - COMPACTION */
  1416. {
  1417. /* initiator PPDU window start */
  1418. hal_txmon_parse_tx_fes_setup(tx_tlv, ppdu_info);
  1419. status = HAL_MON_TX_FES_SETUP;
  1420. SHOW_DEFINED(WIFITX_FES_SETUP_E);
  1421. break;
  1422. }
  1423. /* end of initiator FES window */
  1424. case WIFITX_FES_STATUS_END_E:/* UPSTREAM - COMPACTION */
  1425. {
  1426. hal_txmon_parse_tx_fes_status_end(tx_tlv, ppdu_info,
  1427. tx_status_info);
  1428. status = HAL_MON_TX_FES_STATUS_END;
  1429. SHOW_DEFINED(WIFITX_FES_STATUS_END_E);
  1430. break;
  1431. }
  1432. /* response window open */
  1433. case WIFIRX_RESPONSE_REQUIRED_INFO_E:/* UPSTREAM */
  1434. {
  1435. /* response PPDU window start */
  1436. uint32_t ppdu_id = 0;
  1437. uint8_t reception_type = 0;
  1438. uint8_t response_sta_count = 0;
  1439. status = HAL_MON_RX_RESPONSE_REQUIRED_INFO;
  1440. ppdu_id = HAL_TX_DESC_GET_64(tx_tlv,
  1441. RX_RESPONSE_REQUIRED_INFO,
  1442. PHY_PPDU_ID);
  1443. reception_type =
  1444. HAL_TX_DESC_GET_64(tx_tlv, RX_RESPONSE_REQUIRED_INFO,
  1445. SU_OR_UPLINK_MU_RECEPTION);
  1446. response_sta_count =
  1447. HAL_TX_DESC_GET_64(tx_tlv, RX_RESPONSE_REQUIRED_INFO,
  1448. RESPONSE_STA_COUNT);
  1449. /* get mac address */
  1450. *(uint32_t *)&tx_status_info->addr1[0] =
  1451. HAL_TX_DESC_GET_64(tx_tlv,
  1452. RX_RESPONSE_REQUIRED_INFO,
  1453. ADDR1_31_0);
  1454. *(uint32_t *)&tx_status_info->addr1[4] =
  1455. HAL_TX_DESC_GET_64(tx_tlv,
  1456. RX_RESPONSE_REQUIRED_INFO,
  1457. ADDR1_47_32);
  1458. *(uint32_t *)&tx_status_info->addr2[0] =
  1459. HAL_TX_DESC_GET_64(tx_tlv,
  1460. RX_RESPONSE_REQUIRED_INFO,
  1461. ADDR2_15_0);
  1462. *(uint32_t *)&tx_status_info->addr2[2] =
  1463. HAL_TX_DESC_GET_64(tx_tlv,
  1464. RX_RESPONSE_REQUIRED_INFO,
  1465. ADDR2_47_16);
  1466. TXMON_HAL(ppdu_info, ppdu_id) = ppdu_id;
  1467. TXMON_HAL_STATUS(ppdu_info, ppdu_id) = ppdu_id;
  1468. if (response_sta_count == 0)
  1469. response_sta_count = 1;
  1470. TXMON_HAL(ppdu_info, num_users) = response_sta_count;
  1471. if (reception_type)
  1472. TXMON_STATUS_INFO(tx_status_info,
  1473. transmission_type) =
  1474. TXMON_SU_TRANSMISSION;
  1475. else
  1476. TXMON_STATUS_INFO(tx_status_info,
  1477. transmission_type) =
  1478. TXMON_MU_TRANSMISSION;
  1479. SHOW_DEFINED(WIFIRX_RESPONSE_REQUIRED_INFO_E);
  1480. break;
  1481. }
  1482. /* Response window close */
  1483. case WIFIRESPONSE_END_STATUS_E:/* UPSTREAM - COMPACTION */
  1484. {
  1485. /* response PPDU window end */
  1486. hal_txmon_parse_response_end_status(tx_tlv, ppdu_info,
  1487. tx_status_info);
  1488. status = HAL_MON_RESPONSE_END_STATUS_INFO;
  1489. SHOW_DEFINED(WIFIRESPONSE_END_STATUS_E);
  1490. break;
  1491. }
  1492. case WIFITX_FLUSH_E:/* DOWNSTREAM */
  1493. {
  1494. SHOW_DEFINED(WIFITX_FLUSH_E);
  1495. break;
  1496. }
  1497. /* Downstream tlv */
  1498. case WIFIPCU_PPDU_SETUP_INIT_E:/* DOWNSTREAM - COMPACTION */
  1499. {
  1500. hal_txmon_parse_pcu_ppdu_setup_init(tx_tlv, data_status_info,
  1501. prot_status_info);
  1502. status = HAL_MON_TX_PCU_PPDU_SETUP_INIT;
  1503. SHOW_DEFINED(WIFIPCU_PPDU_SETUP_INIT_E);
  1504. break;
  1505. }
  1506. case WIFITX_PEER_ENTRY_E:/* DOWNSTREAM - COMPACTION */
  1507. {
  1508. hal_txmon_parse_peer_entry(tx_tlv, user_id,
  1509. ppdu_info, tx_status_info);
  1510. SHOW_DEFINED(WIFITX_PEER_ENTRY_E);
  1511. break;
  1512. }
  1513. case WIFITX_QUEUE_EXTENSION_E:/* DOWNSTREAM - COMPACTION */
  1514. {
  1515. status = HAL_MON_TX_QUEUE_EXTENSION;
  1516. hal_txmon_parse_queue_exten(tx_tlv, ppdu_info);
  1517. SHOW_DEFINED(WIFITX_QUEUE_EXTENSION_E);
  1518. break;
  1519. }
  1520. /* payload and data frame handling */
  1521. case WIFITX_MPDU_START_E:/* DOWNSTREAM - COMPACTION */
  1522. {
  1523. hal_txmon_parse_mpdu_start(tx_tlv, user_id, ppdu_info);
  1524. status = HAL_MON_TX_MPDU_START;
  1525. SHOW_DEFINED(WIFITX_MPDU_START_E);
  1526. break;
  1527. }
  1528. case WIFITX_MSDU_START_E:/* DOWNSTREAM - COMPACTION */
  1529. {
  1530. hal_txmon_parse_msdu_start(tx_tlv, user_id, ppdu_info);
  1531. /* we expect frame to be 802.11 frame type */
  1532. status = HAL_MON_TX_MSDU_START;
  1533. SHOW_DEFINED(WIFITX_MSDU_START_E);
  1534. break;
  1535. }
  1536. case WIFITX_DATA_E:/* DOWNSTREAM */
  1537. {
  1538. status = HAL_MON_TX_DATA;
  1539. /*
  1540. * TODO: do we need a conversion api to convert
  1541. * user_id from hw to get host user_index
  1542. */
  1543. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1544. TXMON_STATUS_INFO(tx_status_info,
  1545. buffer) = (void *)status_frag;
  1546. TXMON_STATUS_INFO(tx_status_info,
  1547. offset) = ((void *)tx_tlv -
  1548. (void *)status_frag);
  1549. TXMON_STATUS_INFO(tx_status_info,
  1550. length) = tlv_len;
  1551. /*
  1552. * reference of the status buffer will be held in
  1553. * dp_tx_update_ppdu_info_status()
  1554. */
  1555. SHOW_DEFINED(WIFITX_DATA_E);
  1556. break;
  1557. }
  1558. case WIFIMON_BUFFER_ADDR_E:/* DOWNSTREAM */
  1559. {
  1560. packet_info = &ppdu_info->packet_info;
  1561. status = HAL_MON_TX_BUFFER_ADDR;
  1562. /*
  1563. * TODO: do we need a conversion api to convert
  1564. * user_id from hw to get host user_index
  1565. */
  1566. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1567. hal_txmon_populate_packet_info_generic_be(tx_tlv, packet_info);
  1568. SHOW_DEFINED(WIFIMON_BUFFER_ADDR_E);
  1569. break;
  1570. }
  1571. case WIFITX_MPDU_END_E:/* DOWNSTREAM */
  1572. {
  1573. /* no tlv content */
  1574. SHOW_DEFINED(WIFITX_MPDU_END_E);
  1575. break;
  1576. }
  1577. case WIFITX_MSDU_END_E:/* DOWNSTREAM */
  1578. {
  1579. /* no tlv content */
  1580. SHOW_DEFINED(WIFITX_MSDU_END_E);
  1581. break;
  1582. }
  1583. case WIFITX_LAST_MPDU_FETCHED_E:/* DOWNSTREAM */
  1584. {
  1585. /* no tlv content */
  1586. SHOW_DEFINED(WIFITX_LAST_MPDU_FETCHED_E);
  1587. break;
  1588. }
  1589. case WIFITX_LAST_MPDU_END_E:/* DOWNSTREAM */
  1590. {
  1591. /* no tlv content */
  1592. SHOW_DEFINED(WIFITX_LAST_MPDU_END_E);
  1593. break;
  1594. }
  1595. case WIFICOEX_TX_REQ_E:/* DOWNSTREAM */
  1596. {
  1597. /*
  1598. * transmitting power
  1599. * minimum transmitting power
  1600. * desired nss
  1601. * tx chain mask
  1602. * desired bw
  1603. * duration of transmit and response
  1604. *
  1605. * since most of the field we are deriving from other tlv
  1606. * we don't need to enable this in our tlv.
  1607. */
  1608. SHOW_DEFINED(WIFICOEX_TX_REQ_E);
  1609. break;
  1610. }
  1611. case WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E:/* DOWNSTREAM */
  1612. {
  1613. /* user tlv */
  1614. /*
  1615. * All Tx monitor will have 802.11 hdr
  1616. * we don't need to enable this TLV
  1617. */
  1618. SHOW_DEFINED(WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E);
  1619. break;
  1620. }
  1621. case WIFINDP_PREAMBLE_DONE_E:/* DOWNSTREAM */
  1622. {
  1623. /*
  1624. * no tlv content
  1625. *
  1626. * TLV that indicates to TXPCU that preamble phase for the NDP
  1627. * frame transmission is now over
  1628. */
  1629. SHOW_DEFINED(WIFINDP_PREAMBLE_DONE_E);
  1630. break;
  1631. }
  1632. case WIFISCH_CRITICAL_TLV_REFERENCE_E:/* DOWNSTREAM */
  1633. {
  1634. /*
  1635. * no tlv content
  1636. *
  1637. * TLV indicates to the SCH that all timing critical TLV
  1638. * has been passed on to the transmit path
  1639. */
  1640. SHOW_DEFINED(WIFISCH_CRITICAL_TLV_REFERENCE_E);
  1641. break;
  1642. }
  1643. case WIFITX_LOOPBACK_SETUP_E:/* DOWNSTREAM */
  1644. {
  1645. /*
  1646. * Loopback specific setup info - not needed for Tx monitor
  1647. */
  1648. SHOW_DEFINED(WIFITX_LOOPBACK_SETUP_E);
  1649. break;
  1650. }
  1651. case WIFITX_FES_SETUP_COMPLETE_E:/* DOWNSTREAM */
  1652. {
  1653. /*
  1654. * no tlv content
  1655. *
  1656. * TLV indicates that other modules besides the scheduler can
  1657. * now also start generating TLV's
  1658. * prevent colliding or generating TLV's out of order
  1659. */
  1660. SHOW_DEFINED(WIFITX_FES_SETUP_COMPLETE_E);
  1661. break;
  1662. }
  1663. case WIFITQM_MPDU_GLOBAL_START_E:/* DOWNSTREAM */
  1664. {
  1665. /*
  1666. * no tlv content
  1667. *
  1668. * TLV indicates to SCH that a burst of MPDU info will
  1669. * start to come in over the TLV
  1670. */
  1671. SHOW_DEFINED(WIFITQM_MPDU_GLOBAL_START_E);
  1672. break;
  1673. }
  1674. case WIFITX_WUR_DATA_E:/* DOWNSTREAM */
  1675. {
  1676. SHOW_DEFINED(WIFITX_WUR_DATA_E);
  1677. break;
  1678. }
  1679. case WIFISCHEDULER_END_E:/* DOWNSTREAM */
  1680. {
  1681. /*
  1682. * no tlv content
  1683. *
  1684. * TLV indicates END of all TLV's within the scheduler TLV
  1685. */
  1686. SHOW_DEFINED(WIFISCHEDULER_END_E);
  1687. break;
  1688. }
  1689. /* Upstream tlv */
  1690. case WIFIPDG_TX_REQ_E:
  1691. {
  1692. SHOW_DEFINED(WIFIPDG_TX_REQ_E);
  1693. break;
  1694. }
  1695. case WIFITX_FES_STATUS_START_E:
  1696. {
  1697. /*
  1698. * TLV indicating that first transmission on the medium
  1699. */
  1700. uint8_t medium_prot_type = 0;
  1701. status = HAL_MON_TX_FES_STATUS_START;
  1702. medium_prot_type = HAL_TX_DESC_GET_64(tx_tlv,
  1703. TX_FES_STATUS_START,
  1704. MEDIUM_PROT_TYPE);
  1705. ppdu_info = (struct hal_tx_ppdu_info *)prot_ppdu_info;
  1706. /* update what type of medium protection frame */
  1707. TXMON_STATUS_INFO(tx_status_info,
  1708. medium_prot_type) = medium_prot_type;
  1709. SHOW_DEFINED(WIFITX_FES_STATUS_START_E);
  1710. break;
  1711. }
  1712. case WIFITX_FES_STATUS_PROT_E:/* UPSTREAM - COMPACTION */
  1713. {
  1714. hal_txmon_parse_tx_fes_status_prot(tx_tlv, ppdu_info,
  1715. tx_status_info);
  1716. status = HAL_MON_TX_FES_STATUS_PROT;
  1717. TXMON_HAL(ppdu_info, prot_tlv_status) = tlv_tag;
  1718. SHOW_DEFINED(WIFITX_FES_STATUS_PROT_E);
  1719. break;
  1720. }
  1721. case WIFITX_FES_STATUS_START_PROT_E:
  1722. {
  1723. uint64_t tsft_64;
  1724. uint32_t response_type;
  1725. status = HAL_MON_TX_FES_STATUS_START_PROT;
  1726. TXMON_HAL(ppdu_info, prot_tlv_status) = tlv_tag;
  1727. /* timestamp */
  1728. tsft_64 = HAL_TX_DESC_GET_64(tx_tlv,
  1729. TX_FES_STATUS_START_PROT,
  1730. PROT_TIMESTAMP_LOWER_32);
  1731. tsft_64 |= (HAL_TX_DESC_GET_64(tx_tlv,
  1732. TX_FES_STATUS_START_PROT,
  1733. PROT_TIMESTAMP_UPPER_32) << 32);
  1734. response_type = HAL_TX_DESC_GET_64(tx_tlv,
  1735. TX_FES_STATUS_START_PROT,
  1736. RESPONSE_TYPE);
  1737. TXMON_STATUS_INFO(tx_status_info,
  1738. response_type) = response_type;
  1739. TXMON_HAL_STATUS(ppdu_info, tsft) = tsft_64;
  1740. SHOW_DEFINED(WIFITX_FES_STATUS_START_PROT_E);
  1741. break;
  1742. }
  1743. case WIFIPROT_TX_END_E:
  1744. {
  1745. /*
  1746. * no tlv content
  1747. *
  1748. * generated by TXPCU the moment that protection frame
  1749. * transmission has finished on the medium
  1750. */
  1751. SHOW_DEFINED(WIFIPROT_TX_END_E);
  1752. break;
  1753. }
  1754. case WIFITX_FES_STATUS_START_PPDU_E:
  1755. {
  1756. uint64_t tsft_64;
  1757. uint8_t ndp_frame;
  1758. status = HAL_MON_TX_FES_STATUS_START_PPDU;
  1759. tsft_64 = HAL_TX_DESC_GET_64(tx_tlv,
  1760. TX_FES_STATUS_START_PPDU,
  1761. PPDU_TIMESTAMP_LOWER_32);
  1762. tsft_64 |= (HAL_TX_DESC_GET_64(tx_tlv,
  1763. TX_FES_STATUS_START_PPDU,
  1764. PPDU_TIMESTAMP_UPPER_32) << 32);
  1765. ndp_frame = HAL_TX_DESC_GET_64(tx_tlv,
  1766. TX_FES_STATUS_START_PPDU,
  1767. NDP_FRAME);
  1768. TXMON_STATUS_INFO(tx_status_info, ndp_frame) = ndp_frame;
  1769. TXMON_HAL_STATUS(ppdu_info, tsft) = tsft_64;
  1770. SHOW_DEFINED(WIFITX_FES_STATUS_START_PPDU_E);
  1771. break;
  1772. }
  1773. case WIFITX_FES_STATUS_USER_PPDU_E:
  1774. {
  1775. /* user tlv */
  1776. uint16_t duration;
  1777. uint8_t transmitted_tid;
  1778. duration = HAL_TX_DESC_GET_64(tx_tlv,
  1779. TX_FES_STATUS_USER_PPDU,
  1780. DURATION);
  1781. transmitted_tid = HAL_TX_DESC_GET_64(tx_tlv,
  1782. TX_FES_STATUS_USER_PPDU,
  1783. TRANSMITTED_TID);
  1784. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1785. TXMON_HAL_USER(ppdu_info, user_id, tid) = transmitted_tid;
  1786. TXMON_HAL_USER(ppdu_info, user_id, duration) = duration;
  1787. status = HAL_MON_TX_FES_STATUS_USER_PPDU;
  1788. SHOW_DEFINED(WIFITX_FES_STATUS_USER_PPDU_E);
  1789. break;
  1790. }
  1791. case WIFIPPDU_TX_END_E:
  1792. {
  1793. /*
  1794. * no tlv content
  1795. *
  1796. * generated by TXPCU the moment that PPDU transmission has
  1797. * finished on the medium
  1798. */
  1799. SHOW_DEFINED(WIFIPPDU_TX_END_E);
  1800. break;
  1801. }
  1802. case WIFITX_FES_STATUS_USER_RESPONSE_E:
  1803. {
  1804. /*
  1805. * TLV contains the FES transmit result of the each
  1806. * of the MAC users. TLV are forwarded to HWSCH
  1807. */
  1808. SHOW_DEFINED(WIFITX_FES_STATUS_USER_RESPONSE_E);
  1809. break;
  1810. }
  1811. case WIFITX_FES_STATUS_ACK_OR_BA_E:
  1812. {
  1813. /* user tlv */
  1814. /*
  1815. * TLV generated by RXPCU and provide information related to
  1816. * the received BA or ACK frame
  1817. */
  1818. SHOW_DEFINED(WIFITX_FES_STATUS_ACK_OR_BA_E);
  1819. break;
  1820. }
  1821. case WIFITX_FES_STATUS_1K_BA_E:
  1822. {
  1823. /* user tlv */
  1824. /*
  1825. * TLV generated by RXPCU and providing information related
  1826. * to the received BA frame in case of 512/1024 bitmaps
  1827. */
  1828. SHOW_DEFINED(WIFITX_FES_STATUS_1K_BA_E);
  1829. break;
  1830. }
  1831. case WIFIRECEIVED_RESPONSE_USER_7_0_E:
  1832. {
  1833. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_7_0_E);
  1834. break;
  1835. }
  1836. case WIFIRECEIVED_RESPONSE_USER_15_8_E:
  1837. {
  1838. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_15_8_E);
  1839. break;
  1840. }
  1841. case WIFIRECEIVED_RESPONSE_USER_23_16_E:
  1842. {
  1843. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_23_16_E);
  1844. break;
  1845. }
  1846. case WIFIRECEIVED_RESPONSE_USER_31_24_E:
  1847. {
  1848. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_31_24_E);
  1849. break;
  1850. }
  1851. case WIFIRECEIVED_RESPONSE_USER_36_32_E:
  1852. {
  1853. /*
  1854. * RXPCU generates this TLV when it receives a response frame
  1855. * that TXPCU pre-announced it was waiting for and in
  1856. * RXPCU_SETUP TLV, TLV generated before the
  1857. * RECEIVED_RESPONSE_INFO TLV.
  1858. *
  1859. * received info user fields are there which is not needed
  1860. * for TX monitor
  1861. */
  1862. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_36_32_E);
  1863. break;
  1864. }
  1865. case WIFITXPCU_BUFFER_STATUS_E:
  1866. {
  1867. SHOW_DEFINED(WIFITXPCU_BUFFER_STATUS_E);
  1868. break;
  1869. }
  1870. case WIFITXPCU_USER_BUFFER_STATUS_E:
  1871. {
  1872. /*
  1873. * WIFITXPCU_USER_BUFFER_STATUS_E - user tlv
  1874. * for TX monitor we aren't interested in this tlv
  1875. */
  1876. SHOW_DEFINED(WIFITXPCU_USER_BUFFER_STATUS_E);
  1877. break;
  1878. }
  1879. case WIFITXDMA_STOP_REQUEST_E:
  1880. {
  1881. /*
  1882. * no tlv content
  1883. *
  1884. * TLV is destined to TXDMA and informs TXDMA to stop
  1885. * pushing data into the transmit path.
  1886. */
  1887. SHOW_DEFINED(WIFITXDMA_STOP_REQUEST_E);
  1888. break;
  1889. }
  1890. case WIFITX_CBF_INFO_E:
  1891. {
  1892. /*
  1893. * After NDPA + NDP is received, RXPCU sends the TX_CBF_INFO to
  1894. * TXPCU to respond the CBF frame
  1895. *
  1896. * compressed beamforming pkt doesn't has mac header
  1897. * Tx monitor not interested in this pkt.
  1898. */
  1899. SHOW_DEFINED(WIFITX_CBF_INFO_E);
  1900. break;
  1901. }
  1902. case WIFITX_MPDU_COUNT_TRANSFER_END_E:
  1903. {
  1904. /*
  1905. * no tlv content
  1906. *
  1907. * TLV indicates that TXPCU has finished generating the
  1908. * TQM_UPDATE_TX_MPDU_COUNT TLV for all users
  1909. */
  1910. SHOW_DEFINED(WIFITX_MPDU_COUNT_TRANSFER_END_E);
  1911. break;
  1912. }
  1913. case WIFIPDG_RESPONSE_E:
  1914. {
  1915. /*
  1916. * most of the feilds are already covered in
  1917. * other TLV
  1918. * This is generated by TX_PCU to PDG to calculate
  1919. * all the PHY header info.
  1920. *
  1921. * some useful fields like min transmit power,
  1922. * rate used for transmitting packet is present.
  1923. */
  1924. SHOW_DEFINED(WIFIPDG_RESPONSE_E);
  1925. break;
  1926. }
  1927. case WIFIPDG_TRIG_RESPONSE_E:
  1928. {
  1929. /* no tlv content */
  1930. SHOW_DEFINED(WIFIPDG_TRIG_RESPONSE_E);
  1931. break;
  1932. }
  1933. case WIFIRECEIVED_TRIGGER_INFO_E:
  1934. {
  1935. /*
  1936. * TLV generated by RXPCU to inform the scheduler that
  1937. * a trigger frame has been received
  1938. */
  1939. SHOW_DEFINED(WIFIRECEIVED_TRIGGER_INFO_E);
  1940. break;
  1941. }
  1942. case WIFIOFDMA_TRIGGER_DETAILS_E:
  1943. {
  1944. SHOW_DEFINED(WIFIOFDMA_TRIGGER_DETAILS_E);
  1945. break;
  1946. }
  1947. case WIFIRX_FRAME_BITMAP_ACK_E:
  1948. {
  1949. /* user tlv */
  1950. status = HAL_MON_RX_FRAME_BITMAP_ACK;
  1951. SHOW_DEFINED(WIFIRX_FRAME_BITMAP_ACK_E);
  1952. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1953. TXMON_STATUS_INFO(tx_status_info, no_bitmap_avail) =
  1954. HAL_TX_DESC_GET_64(tx_tlv,
  1955. RX_FRAME_BITMAP_ACK,
  1956. NO_BITMAP_AVAILABLE);
  1957. TXMON_STATUS_INFO(tx_status_info, explicit_ack) =
  1958. HAL_TX_DESC_GET_64(tx_tlv,
  1959. RX_FRAME_BITMAP_ACK,
  1960. EXPLICIT_ACK);
  1961. /*
  1962. * get mac address, since address is received frame
  1963. * change the order and store it
  1964. */
  1965. *(uint32_t *)&tx_status_info->addr2[0] =
  1966. HAL_TX_DESC_GET_64(tx_tlv,
  1967. RX_FRAME_BITMAP_ACK,
  1968. ADDR1_31_0);
  1969. *(uint16_t *)&tx_status_info->addr2[4] =
  1970. HAL_TX_DESC_GET_64(tx_tlv,
  1971. RX_FRAME_BITMAP_ACK,
  1972. ADDR1_47_32);
  1973. *(uint32_t *)&tx_status_info->addr1[0] =
  1974. HAL_TX_DESC_GET_64(tx_tlv,
  1975. RX_FRAME_BITMAP_ACK,
  1976. ADDR2_15_0);
  1977. *(uint32_t *)&tx_status_info->addr1[2] =
  1978. HAL_TX_DESC_GET_64(tx_tlv,
  1979. RX_FRAME_BITMAP_ACK,
  1980. ADDR2_47_16);
  1981. TXMON_STATUS_INFO(tx_status_info, explicit_ack_type) =
  1982. HAL_TX_DESC_GET_64(tx_tlv, RX_FRAME_BITMAP_ACK,
  1983. EXPLICT_ACK_TYPE);
  1984. TXMON_HAL_USER(ppdu_info, user_id, tid) =
  1985. HAL_TX_DESC_GET_64(tx_tlv,
  1986. RX_FRAME_BITMAP_ACK,
  1987. BA_TID);
  1988. TXMON_HAL_USER(ppdu_info, user_id, aid) =
  1989. HAL_TX_DESC_GET_64(tx_tlv,
  1990. RX_FRAME_BITMAP_ACK,
  1991. STA_FULL_AID);
  1992. TXMON_HAL_USER(ppdu_info, user_id, start_seq) =
  1993. HAL_TX_DESC_GET_64(tx_tlv,
  1994. RX_FRAME_BITMAP_ACK,
  1995. BA_TS_SEQ);
  1996. TXMON_HAL_USER(ppdu_info, user_id, ba_control) =
  1997. HAL_TX_DESC_GET_64(tx_tlv,
  1998. RX_FRAME_BITMAP_ACK,
  1999. BA_TS_CTRL);
  2000. TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap_sz) =
  2001. HAL_TX_DESC_GET_64(tx_tlv,
  2002. RX_FRAME_BITMAP_ACK,
  2003. BA_BITMAP_SIZE);
  2004. /* ba bitmap */
  2005. qdf_mem_copy(TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap),
  2006. &HAL_SET_FLD_OFFSET_64(tx_tlv,
  2007. RX_FRAME_BITMAP_ACK,
  2008. BA_TS_BITMAP_31_0, 0), 32);
  2009. break;
  2010. }
  2011. case WIFIRX_FRAME_1K_BITMAP_ACK_E:
  2012. {
  2013. /* user tlv */
  2014. status = HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_1K;
  2015. SHOW_DEFINED(WIFIRX_FRAME_1K_BITMAP_ACK_E);
  2016. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  2017. TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap_sz) =
  2018. (4 + HAL_TX_DESC_GET_64(tx_tlv, RX_FRAME_1K_BITMAP_ACK,
  2019. BA_BITMAP_SIZE));
  2020. TXMON_HAL_USER(ppdu_info, user_id, tid) =
  2021. HAL_TX_DESC_GET_64(tx_tlv,
  2022. RX_FRAME_1K_BITMAP_ACK,
  2023. BA_TID);
  2024. TXMON_HAL_USER(ppdu_info, user_id, aid) =
  2025. HAL_TX_DESC_GET_64(tx_tlv,
  2026. RX_FRAME_1K_BITMAP_ACK,
  2027. STA_FULL_AID);
  2028. /* get mac address */
  2029. *(uint32_t *)&tx_status_info->addr1[0] =
  2030. HAL_TX_DESC_GET_64(tx_tlv,
  2031. RX_FRAME_1K_BITMAP_ACK,
  2032. ADDR1_31_0);
  2033. *(uint16_t *)&tx_status_info->addr1[4] =
  2034. HAL_TX_DESC_GET_64(tx_tlv,
  2035. RX_FRAME_1K_BITMAP_ACK,
  2036. ADDR1_47_32);
  2037. *(uint32_t *)&tx_status_info->addr2[0] =
  2038. HAL_TX_DESC_GET_64(tx_tlv,
  2039. RX_FRAME_1K_BITMAP_ACK,
  2040. ADDR2_15_0);
  2041. *(uint32_t *)&tx_status_info->addr2[2] =
  2042. HAL_TX_DESC_GET_64(tx_tlv,
  2043. RX_FRAME_1K_BITMAP_ACK,
  2044. ADDR2_47_16);
  2045. TXMON_HAL_USER(ppdu_info, user_id, start_seq) =
  2046. HAL_TX_DESC_GET_64(tx_tlv,
  2047. RX_FRAME_1K_BITMAP_ACK,
  2048. BA_TS_SEQ);
  2049. TXMON_HAL_USER(ppdu_info, user_id, ba_control) =
  2050. HAL_TX_DESC_GET_64(tx_tlv,
  2051. RX_FRAME_1K_BITMAP_ACK,
  2052. BA_TS_CTRL);
  2053. /* memcpy ba bitmap */
  2054. qdf_mem_copy(TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap),
  2055. &HAL_SET_FLD_OFFSET_64(tx_tlv,
  2056. RX_FRAME_1K_BITMAP_ACK,
  2057. BA_TS_BITMAP_31_0, 0),
  2058. 4 << TXMON_HAL_USER(ppdu_info,
  2059. user_id, ba_bitmap_sz));
  2060. break;
  2061. }
  2062. case WIFIRESPONSE_START_STATUS_E:
  2063. {
  2064. /*
  2065. * TLV indicates which HW response the TXPCU
  2066. * started generating
  2067. *
  2068. * HW generated frames like
  2069. * ACK frame - handled
  2070. * CTS frame - handled
  2071. * BA frame - handled
  2072. * MBA frame - handled
  2073. * CBF frame - no frame header
  2074. * Trigger response - TODO
  2075. * NDP LMR - no frame header
  2076. */
  2077. SHOW_DEFINED(WIFIRESPONSE_START_STATUS_E);
  2078. break;
  2079. }
  2080. case WIFIRX_START_PARAM_E:
  2081. {
  2082. /*
  2083. * RXPCU send this TLV after PHY RX detected a frame
  2084. * in the medium
  2085. *
  2086. * TX monitor not interested in this TLV
  2087. */
  2088. SHOW_DEFINED(WIFIRX_START_PARAM_E);
  2089. break;
  2090. }
  2091. case WIFIRXPCU_EARLY_RX_INDICATION_E:
  2092. {
  2093. /*
  2094. * early indication of pkt type and mcs rate
  2095. * already captured in other tlv
  2096. */
  2097. SHOW_DEFINED(WIFIRXPCU_EARLY_RX_INDICATION_E);
  2098. break;
  2099. }
  2100. case WIFIRX_PM_INFO_E:
  2101. {
  2102. SHOW_DEFINED(WIFIRX_PM_INFO_E);
  2103. break;
  2104. }
  2105. /* Active window */
  2106. case WIFITX_FLUSH_REQ_E:
  2107. {
  2108. SHOW_DEFINED(WIFITX_FLUSH_REQ_E);
  2109. break;
  2110. }
  2111. case WIFICOEX_TX_STATUS_E:
  2112. {
  2113. /* duration are retrieved from coex tx status */
  2114. uint16_t duration;
  2115. uint8_t status_reason;
  2116. status = HAL_MON_COEX_TX_STATUS;
  2117. duration = HAL_TX_DESC_GET_64(tx_tlv,
  2118. COEX_TX_STATUS,
  2119. CURRENT_TX_DURATION);
  2120. status_reason = HAL_TX_DESC_GET_64(tx_tlv,
  2121. COEX_TX_STATUS,
  2122. TX_STATUS_REASON);
  2123. /* update duration */
  2124. if (status_reason == COEX_FES_TX_START ||
  2125. status_reason == COEX_RESPONSE_TX_START)
  2126. TXMON_HAL_USER(ppdu_info, user_id, duration) = duration;
  2127. SHOW_DEFINED(WIFICOEX_TX_STATUS_E);
  2128. break;
  2129. }
  2130. case WIFIR2R_STATUS_END_E:
  2131. {
  2132. SHOW_DEFINED(WIFIR2R_STATUS_END_E);
  2133. break;
  2134. }
  2135. case WIFIRX_PREAMBLE_E:
  2136. {
  2137. SHOW_DEFINED(WIFIRX_PREAMBLE_E);
  2138. break;
  2139. }
  2140. case WIFIMACTX_SERVICE_E:
  2141. {
  2142. SHOW_DEFINED(WIFIMACTX_SERVICE_E);
  2143. break;
  2144. }
  2145. case WIFIMACTX_U_SIG_EHT_SU_MU_E:
  2146. {
  2147. struct hal_mon_usig_hdr *usig = NULL;
  2148. struct hal_mon_usig_mu *usig_mu = NULL;
  2149. usig = (struct hal_mon_usig_hdr *)tx_tlv;
  2150. usig_mu = &usig->usig_2.mu;
  2151. hal_txmon_parse_u_sig_hdr(tx_tlv, ppdu_info);
  2152. TXMON_HAL_STATUS(ppdu_info, usig_mask) |=
  2153. QDF_MON_STATUS_USIG_DISREGARD_KNOWN |
  2154. QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN |
  2155. QDF_MON_STATUS_USIG_VALIDATE_KNOWN |
  2156. QDF_MON_STATUS_USIG_MU_VALIDATE1_KNOWN |
  2157. QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_KNOWN |
  2158. QDF_MON_STATUS_USIG_MU_VALIDATE2_KNOWN |
  2159. QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_KNOWN |
  2160. QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_KNOWN |
  2161. QDF_MON_STATUS_USIG_CRC_KNOWN |
  2162. QDF_MON_STATUS_USIG_TAIL_KNOWN;
  2163. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2164. (0x1F << QDF_MON_STATUS_USIG_DISREGARD_SHIFT);
  2165. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2166. (0x1 << QDF_MON_STATUS_USIG_MU_VALIDATE1_SHIFT);
  2167. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2168. (usig_mu->ppdu_type_comp_mode <<
  2169. QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT);
  2170. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2171. (0x1 << QDF_MON_STATUS_USIG_VALIDATE_SHIFT);
  2172. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2173. (usig_mu->punc_ch_info <<
  2174. QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_SHIFT);
  2175. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2176. (0x1 << QDF_MON_STATUS_USIG_MU_VALIDATE2_SHIFT);
  2177. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2178. (usig_mu->eht_sig_mcs <<
  2179. QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_SHIFT);
  2180. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2181. (usig_mu->num_eht_sig_sym <<
  2182. QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_SHIFT);
  2183. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2184. (usig_mu->crc << QDF_MON_STATUS_USIG_CRC_SHIFT);
  2185. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2186. (usig_mu->tail << QDF_MON_STATUS_USIG_TAIL_SHIFT);
  2187. SHOW_DEFINED(WIFIMACTX_U_SIG_EHT_SU_MU_E);
  2188. break;
  2189. }
  2190. case WIFIMACTX_U_SIG_EHT_TB_E:
  2191. {
  2192. struct hal_mon_usig_hdr *usig = NULL;
  2193. struct hal_mon_usig_tb *usig_tb = NULL;
  2194. usig = (struct hal_mon_usig_hdr *)tx_tlv;
  2195. usig_tb = &usig->usig_2.tb;
  2196. hal_txmon_parse_u_sig_hdr(tx_tlv, ppdu_info);
  2197. TXMON_HAL_STATUS(ppdu_info, usig_mask) |=
  2198. QDF_MON_STATUS_USIG_DISREGARD_KNOWN |
  2199. QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN |
  2200. QDF_MON_STATUS_USIG_VALIDATE_KNOWN |
  2201. QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_KNOWN |
  2202. QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_KNOWN |
  2203. QDF_MON_STATUS_USIG_TB_DISREGARD1_KNOWN |
  2204. QDF_MON_STATUS_USIG_CRC_KNOWN |
  2205. QDF_MON_STATUS_USIG_TAIL_KNOWN;
  2206. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2207. (0x3F << QDF_MON_STATUS_USIG_DISREGARD_SHIFT);
  2208. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2209. (usig_tb->ppdu_type_comp_mode <<
  2210. QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT);
  2211. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2212. (0x1 << QDF_MON_STATUS_USIG_VALIDATE_SHIFT);
  2213. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2214. (usig_tb->spatial_reuse_1 <<
  2215. QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_SHIFT);
  2216. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2217. (usig_tb->spatial_reuse_2 <<
  2218. QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_SHIFT);
  2219. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2220. (0x1F << QDF_MON_STATUS_USIG_TB_DISREGARD1_SHIFT);
  2221. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2222. (usig_tb->crc << QDF_MON_STATUS_USIG_CRC_SHIFT);
  2223. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2224. (usig_tb->tail << QDF_MON_STATUS_USIG_TAIL_SHIFT);
  2225. SHOW_DEFINED(WIFIMACTX_U_SIG_EHT_TB_E);
  2226. break;
  2227. }
  2228. case WIFIMACTX_EHT_SIG_USR_OFDMA_E:
  2229. {
  2230. hal_txmon_parse_eht_sig_non_mumimo_user_info(tx_tlv, user_id,
  2231. ppdu_info);
  2232. TXMON_HAL_STATUS(ppdu_info, eht_flags) = 1;
  2233. SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_OFDMA_E);
  2234. break;
  2235. }
  2236. case WIFIMACTX_EHT_SIG_USR_MU_MIMO_E:
  2237. {
  2238. hal_txmon_parse_eht_sig_mumimo_user_info(tx_tlv, user_id,
  2239. ppdu_info);
  2240. TXMON_HAL_STATUS(ppdu_info, eht_flags) = 1;
  2241. SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_MU_MIMO_E);
  2242. break;
  2243. }
  2244. case WIFIMACTX_EHT_SIG_USR_SU_E:
  2245. {
  2246. hal_txmon_parse_eht_sig_non_mumimo_user_info(tx_tlv, user_id,
  2247. ppdu_info);
  2248. TXMON_HAL_STATUS(ppdu_info, eht_flags) = 1;
  2249. SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_SU_E);
  2250. /* TODO: no radiotap info available */
  2251. break;
  2252. }
  2253. case WIFIMACTX_HE_SIG_A_SU_E:
  2254. {
  2255. uint16_t he_mu_flag_1 = 0;
  2256. uint16_t he_mu_flag_2 = 0;
  2257. uint16_t num_users = 0;
  2258. uint8_t mcs_of_sig_b = 0;
  2259. uint8_t dcm_of_sig_b = 0;
  2260. uint8_t sig_a_bw = 0;
  2261. uint8_t i = 0;
  2262. uint8_t bss_color_id;
  2263. uint8_t coding;
  2264. uint8_t stbc;
  2265. uint8_t a_factor;
  2266. uint8_t pe_disambiguity;
  2267. uint8_t txbf;
  2268. uint8_t txbw;
  2269. uint8_t txop;
  2270. status = HAL_MON_MACTX_HE_SIG_A_SU;
  2271. num_users = TXMON_HAL(ppdu_info, num_users);
  2272. mcs_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  2273. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2274. TRANSMIT_MCS);
  2275. dcm_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  2276. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2277. DCM);
  2278. sig_a_bw = HAL_TX_DESC_GET_64(tx_tlv,
  2279. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2280. TRANSMIT_BW);
  2281. bss_color_id = HAL_TX_DESC_GET_64(tx_tlv,
  2282. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2283. BSS_COLOR_ID);
  2284. coding = HAL_TX_DESC_GET_64(tx_tlv,
  2285. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2286. CODING);
  2287. stbc = HAL_TX_DESC_GET_64(tx_tlv,
  2288. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2289. STBC);
  2290. a_factor = HAL_TX_DESC_GET_64(tx_tlv,
  2291. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2292. PACKET_EXTENSION_A_FACTOR);
  2293. pe_disambiguity = HAL_TX_DESC_GET_64(tx_tlv,
  2294. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2295. PACKET_EXTENSION_PE_DISAMBIGUITY);
  2296. txbf = HAL_TX_DESC_GET_64(tx_tlv,
  2297. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2298. TXBF);
  2299. txbw = HAL_TX_DESC_GET_64(tx_tlv,
  2300. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2301. TRANSMIT_BW);
  2302. txop = HAL_TX_DESC_GET_64(tx_tlv,
  2303. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2304. TXOP_DURATION);
  2305. he_mu_flag_1 |= QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  2306. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  2307. QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN |
  2308. QDF_MON_STATUS_CHANNEL_1_RU_KNOWN |
  2309. QDF_MON_STATUS_CHANNEL_2_RU_KNOWN |
  2310. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN;
  2311. /* MCS */
  2312. he_mu_flag_1 |= mcs_of_sig_b <<
  2313. QDF_MON_STATUS_SIG_B_MCS_SHIFT;
  2314. /* DCM */
  2315. he_mu_flag_1 |= dcm_of_sig_b <<
  2316. QDF_MON_STATUS_SIG_B_DCM_SHIFT;
  2317. /* bandwidth */
  2318. he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_BANDWIDTH_KNOWN;
  2319. he_mu_flag_2 |= sig_a_bw <<
  2320. QDF_MON_STATUS_SIG_A_BANDWIDTH_SHIFT;
  2321. TXMON_HAL_STATUS(ppdu_info,
  2322. he_mu_flags) = IS_MULTI_USERS(num_users);
  2323. for (i = 0; i < num_users; i++) {
  2324. TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1;
  2325. TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2;
  2326. }
  2327. /* HE data 1 */
  2328. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |=
  2329. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  2330. QDF_MON_STATUS_HE_CODING_KNOWN;
  2331. /* HE data 2 */
  2332. TXMON_HAL_USER(ppdu_info, user_id, he_data2) |=
  2333. QDF_MON_STATUS_TXBF_KNOWN |
  2334. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  2335. QDF_MON_STATUS_TXOP_KNOWN |
  2336. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  2337. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  2338. /* HE data 3 */
  2339. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2340. bss_color_id |
  2341. (!!txbf << QDF_MON_STATUS_BEAM_CHANGE_SHIFT) |
  2342. (coding << QDF_MON_STATUS_CODING_SHIFT) |
  2343. (stbc << QDF_MON_STATUS_STBC_SHIFT);
  2344. /* HE data 6 */
  2345. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |=
  2346. (txop << QDF_MON_STATUS_TXOP_SHIFT);
  2347. SHOW_DEFINED(WIFIMACTX_HE_SIG_A_SU_E);
  2348. break;
  2349. }
  2350. case WIFIMACTX_HE_SIG_A_MU_DL_E:
  2351. {
  2352. uint16_t he_mu_flag_1 = 0;
  2353. uint16_t he_mu_flag_2 = 0;
  2354. uint16_t num_users = 0;
  2355. uint8_t bss_color_id;
  2356. uint8_t txop;
  2357. uint8_t mcs_of_sig_b = 0;
  2358. uint8_t dcm_of_sig_b = 0;
  2359. uint8_t sig_a_bw = 0;
  2360. uint8_t num_sig_b_symb = 0;
  2361. uint8_t comp_mode_sig_b = 0;
  2362. uint8_t punc_bw = 0;
  2363. uint8_t i = 0;
  2364. status = HAL_MON_MACTX_HE_SIG_A_MU_DL;
  2365. num_users = TXMON_HAL(ppdu_info, num_users);
  2366. mcs_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  2367. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2368. MCS_OF_SIG_B);
  2369. dcm_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  2370. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2371. DCM_OF_SIG_B);
  2372. sig_a_bw = HAL_TX_DESC_GET_64(tx_tlv,
  2373. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2374. TRANSMIT_BW);
  2375. num_sig_b_symb = HAL_TX_DESC_GET_64(tx_tlv,
  2376. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2377. NUM_SIG_B_SYMBOLS);
  2378. comp_mode_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  2379. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2380. COMP_MODE_SIG_B);
  2381. bss_color_id = HAL_TX_DESC_GET_64(tx_tlv,
  2382. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2383. BSS_COLOR_ID);
  2384. txop = HAL_TX_DESC_GET_64(tx_tlv,
  2385. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2386. TXOP_DURATION);
  2387. he_mu_flag_1 |= QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  2388. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  2389. QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN |
  2390. QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN |
  2391. QDF_MON_STATUS_CHANNEL_1_RU_KNOWN |
  2392. QDF_MON_STATUS_CHANNEL_2_RU_KNOWN |
  2393. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN |
  2394. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN |
  2395. QDF_MON_STATUS_SIG_B_SYMBOL_USER_KNOWN;
  2396. /* MCS */
  2397. he_mu_flag_1 |= mcs_of_sig_b <<
  2398. QDF_MON_STATUS_SIG_B_MCS_SHIFT;
  2399. /* DCM */
  2400. he_mu_flag_1 |= dcm_of_sig_b <<
  2401. QDF_MON_STATUS_SIG_B_DCM_SHIFT;
  2402. /* Compression */
  2403. he_mu_flag_2 |= comp_mode_sig_b <<
  2404. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  2405. /* bandwidth */
  2406. he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_BANDWIDTH_KNOWN;
  2407. he_mu_flag_2 |= sig_a_bw <<
  2408. QDF_MON_STATUS_SIG_A_BANDWIDTH_SHIFT;
  2409. he_mu_flag_2 |= comp_mode_sig_b <<
  2410. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  2411. /* number of symbol */
  2412. he_mu_flag_2 |= num_sig_b_symb <<
  2413. QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT;
  2414. /* puncture bw */
  2415. he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_PUNC_BANDWIDTH_KNOWN;
  2416. punc_bw = sig_a_bw;
  2417. he_mu_flag_2 |=
  2418. punc_bw << QDF_MON_STATUS_SIG_A_PUNC_BANDWIDTH_SHIFT;
  2419. /* copy per user info to all user */
  2420. TXMON_HAL_STATUS(ppdu_info,
  2421. he_mu_flags) = IS_MULTI_USERS(num_users);
  2422. for (i = 0; i < num_users; i++) {
  2423. TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1;
  2424. TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2;
  2425. }
  2426. /* HE data 1 */
  2427. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |=
  2428. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN;
  2429. /* HE data 2 */
  2430. TXMON_HAL_USER(ppdu_info, user_id, he_data2) |=
  2431. QDF_MON_STATUS_TXOP_KNOWN;
  2432. /* HE data 3 */
  2433. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= bss_color_id;
  2434. /* HE data 6 */
  2435. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |=
  2436. (txop << QDF_MON_STATUS_TXOP_SHIFT);
  2437. SHOW_DEFINED(WIFIMACTX_HE_SIG_A_MU_DL_E);
  2438. break;
  2439. }
  2440. case WIFIMACTX_HE_SIG_A_MU_UL_E:
  2441. {
  2442. SHOW_DEFINED(WIFIMACTX_HE_SIG_A_MU_UL_E);
  2443. break;
  2444. }
  2445. case WIFIMACTX_HE_SIG_B1_MU_E:
  2446. {
  2447. status = HAL_MON_MACTX_HE_SIG_B1_MU;
  2448. SHOW_DEFINED(WIFIMACTX_HE_SIG_B1_MU_E);
  2449. break;
  2450. }
  2451. case WIFIMACTX_HE_SIG_B2_MU_E:
  2452. {
  2453. /* user tlv */
  2454. uint16_t sta_id = 0;
  2455. uint16_t sta_spatial_config = 0;
  2456. uint8_t sta_mcs = 0;
  2457. uint8_t coding = 0;
  2458. uint8_t nss = 0;
  2459. uint8_t user_order = 0;
  2460. status = HAL_MON_MACTX_HE_SIG_B2_MU;
  2461. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  2462. sta_id = HAL_TX_DESC_GET_64(tx_tlv,
  2463. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2464. STA_ID);
  2465. sta_spatial_config = HAL_TX_DESC_GET_64(tx_tlv,
  2466. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2467. STA_SPATIAL_CONFIG);
  2468. sta_mcs = HAL_TX_DESC_GET_64(tx_tlv,
  2469. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2470. STA_MCS);
  2471. coding = HAL_TX_DESC_GET_64(tx_tlv,
  2472. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2473. STA_CODING);
  2474. nss = HAL_TX_DESC_GET_64(tx_tlv,
  2475. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2476. NSTS) + 1;
  2477. user_order = HAL_TX_DESC_GET_64(tx_tlv,
  2478. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2479. USER_ORDER);
  2480. /* HE data 1 */
  2481. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |=
  2482. QDF_MON_STATUS_HE_MCS_KNOWN |
  2483. QDF_MON_STATUS_HE_CODING_KNOWN;
  2484. /* HE data 2 */
  2485. /* HE data 3 */
  2486. TXMON_HAL_USER(ppdu_info, user_id, mcs) = sta_mcs;
  2487. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2488. sta_mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  2489. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2490. coding << QDF_MON_STATUS_CODING_SHIFT;
  2491. /* HE data 4 */
  2492. TXMON_HAL_USER(ppdu_info, user_id, he_data4) |=
  2493. sta_id << QDF_MON_STATUS_STA_ID_SHIFT;
  2494. /* HE data 5 */
  2495. /* HE data 6 */
  2496. TXMON_HAL_USER(ppdu_info, user_id, nss) = nss;
  2497. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= nss;
  2498. SHOW_DEFINED(WIFIMACTX_HE_SIG_B2_MU_E);
  2499. break;
  2500. }
  2501. case WIFIMACTX_HE_SIG_B2_OFDMA_E:
  2502. {
  2503. /* user tlv */
  2504. uint8_t *he_sig_b2_ofdma_info = NULL;
  2505. uint16_t sta_id = 0;
  2506. uint8_t nss = 0;
  2507. uint8_t txbf = 0;
  2508. uint8_t sta_mcs = 0;
  2509. uint8_t sta_dcm = 0;
  2510. uint8_t coding = 0;
  2511. uint8_t user_order = 0;
  2512. status = HAL_MON_MACTX_HE_SIG_B2_OFDMA;
  2513. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  2514. he_sig_b2_ofdma_info = (uint8_t *)tx_tlv +
  2515. HAL_OFFSET(MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2516. STA_ID);
  2517. sta_id = HAL_TX_DESC_GET_64(tx_tlv,
  2518. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2519. STA_ID);
  2520. nss = HAL_TX_DESC_GET_64(tx_tlv,
  2521. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2522. NSTS);
  2523. txbf = HAL_TX_DESC_GET_64(tx_tlv,
  2524. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2525. TXBF);
  2526. sta_mcs = HAL_TX_DESC_GET_64(tx_tlv,
  2527. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2528. STA_MCS);
  2529. sta_dcm = HAL_TX_DESC_GET_64(tx_tlv,
  2530. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2531. STA_DCM);
  2532. coding = HAL_TX_DESC_GET_64(tx_tlv,
  2533. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2534. STA_CODING);
  2535. user_order = HAL_TX_DESC_GET_64(tx_tlv,
  2536. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2537. USER_ORDER);
  2538. /* HE data 1 */
  2539. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |=
  2540. QDF_MON_STATUS_HE_MCS_KNOWN |
  2541. QDF_MON_STATUS_HE_CODING_KNOWN |
  2542. QDF_MON_STATUS_HE_DCM_KNOWN;
  2543. /* HE data 2 */
  2544. TXMON_HAL_USER(ppdu_info, user_id, he_data2) |=
  2545. QDF_MON_STATUS_TXBF_KNOWN;
  2546. /* HE data 3 */
  2547. TXMON_HAL_USER(ppdu_info, user_id, mcs) = sta_mcs;
  2548. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2549. sta_mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  2550. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2551. sta_dcm << QDF_MON_STATUS_DCM_SHIFT;
  2552. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2553. coding << QDF_MON_STATUS_CODING_SHIFT;
  2554. /* HE data 4 */
  2555. TXMON_HAL_USER(ppdu_info, user_id, he_data4) |=
  2556. sta_id << QDF_MON_STATUS_STA_ID_SHIFT;
  2557. /* HE data 5 */
  2558. TXMON_HAL_USER(ppdu_info, user_id, he_data5) |=
  2559. txbf << QDF_MON_STATUS_TXBF_SHIFT;
  2560. /* HE data 6 */
  2561. TXMON_HAL_USER(ppdu_info, user_id, nss) = nss;
  2562. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= nss;
  2563. SHOW_DEFINED(WIFIMACTX_HE_SIG_B2_OFDMA_E);
  2564. break;
  2565. }
  2566. case WIFIMACTX_L_SIG_A_E:
  2567. {
  2568. uint8_t *l_sig_a_info = NULL;
  2569. uint8_t rate = 0;
  2570. status = HAL_MON_MACTX_L_SIG_A;
  2571. l_sig_a_info = (uint8_t *)tx_tlv +
  2572. HAL_OFFSET(MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS,
  2573. RATE);
  2574. rate = HAL_TX_DESC_GET_64(tx_tlv,
  2575. MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS,
  2576. RATE);
  2577. switch (rate) {
  2578. case 8:
  2579. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_0MCS;
  2580. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS0;
  2581. break;
  2582. case 9:
  2583. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_1MCS;
  2584. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS1;
  2585. break;
  2586. case 10:
  2587. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_2MCS;
  2588. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS2;
  2589. break;
  2590. case 11:
  2591. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_3MCS;
  2592. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS3;
  2593. break;
  2594. case 12:
  2595. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_4MCS;
  2596. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS4;
  2597. break;
  2598. case 13:
  2599. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_5MCS;
  2600. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS5;
  2601. break;
  2602. case 14:
  2603. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_6MCS;
  2604. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS6;
  2605. break;
  2606. case 15:
  2607. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_7MCS;
  2608. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS7;
  2609. break;
  2610. default:
  2611. break;
  2612. }
  2613. TXMON_HAL_STATUS(ppdu_info, ofdm_flag) = 1;
  2614. TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU;
  2615. TXMON_HAL_STATUS(ppdu_info,
  2616. l_sig_a_info) = *((uint32_t *)l_sig_a_info);
  2617. SHOW_DEFINED(WIFIMACTX_L_SIG_A_E);
  2618. break;
  2619. }
  2620. case WIFIMACTX_L_SIG_B_E:
  2621. {
  2622. uint8_t *l_sig_b_info = NULL;
  2623. uint8_t rate = 0;
  2624. status = HAL_MON_MACTX_L_SIG_B;
  2625. l_sig_b_info = (uint8_t *)tx_tlv +
  2626. HAL_OFFSET(MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS,
  2627. RATE);
  2628. rate = HAL_TX_DESC_GET_64(tx_tlv,
  2629. MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS,
  2630. RATE);
  2631. switch (rate) {
  2632. case 1:
  2633. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_3MCS;
  2634. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS3;
  2635. break;
  2636. case 2:
  2637. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_2MCS;
  2638. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS2;
  2639. break;
  2640. case 3:
  2641. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_1MCS;
  2642. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS1;
  2643. break;
  2644. case 4:
  2645. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_0MCS;
  2646. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS0;
  2647. break;
  2648. case 5:
  2649. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_6MCS;
  2650. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS6;
  2651. break;
  2652. case 6:
  2653. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_5MCS;
  2654. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS5;
  2655. break;
  2656. case 7:
  2657. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_4MCS;
  2658. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS4;
  2659. break;
  2660. default:
  2661. break;
  2662. }
  2663. TXMON_HAL_STATUS(ppdu_info, cck_flag) = 1;
  2664. TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU;
  2665. TXMON_HAL_STATUS(ppdu_info, l_sig_b_info) = *l_sig_b_info;
  2666. SHOW_DEFINED(WIFIMACTX_L_SIG_B_E);
  2667. break;
  2668. }
  2669. case WIFIMACTX_HT_SIG_E:
  2670. {
  2671. uint8_t mcs = 0;
  2672. uint8_t bw = 0;
  2673. uint8_t is_stbc = 0;
  2674. uint8_t coding = 0;
  2675. uint8_t gi = 0;
  2676. status = HAL_MON_MACTX_HT_SIG;
  2677. mcs = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, MCS);
  2678. bw = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, CBW);
  2679. is_stbc = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, STBC);
  2680. coding = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, FEC_CODING);
  2681. gi = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, SHORT_GI);
  2682. TXMON_HAL_STATUS(ppdu_info, ldpc) =
  2683. (coding == HAL_SU_MU_CODING_LDPC) ? 1 : 0;
  2684. TXMON_HAL_STATUS(ppdu_info, ht_mcs) = mcs;
  2685. TXMON_HAL_STATUS(ppdu_info, bw) = bw;
  2686. TXMON_HAL_STATUS(ppdu_info, sgi) = gi;
  2687. TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc;
  2688. TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU;
  2689. SHOW_DEFINED(WIFIMACTX_HT_SIG_E);
  2690. break;
  2691. }
  2692. case WIFIMACTX_VHT_SIG_A_E:
  2693. {
  2694. uint8_t bandwidth = 0;
  2695. uint8_t is_stbc = 0;
  2696. uint8_t group_id = 0;
  2697. uint32_t nss_comb = 0;
  2698. uint8_t nss_su = 0;
  2699. uint8_t nss_mu[4] = {0};
  2700. uint8_t sgi = 0;
  2701. uint8_t coding = 0;
  2702. uint8_t mcs = 0;
  2703. uint8_t beamformed = 0;
  2704. uint8_t partial_aid = 0;
  2705. status = HAL_MON_MACTX_VHT_SIG_A;
  2706. bandwidth = HAL_TX_DESC_GET_64(tx_tlv,
  2707. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2708. BANDWIDTH);
  2709. is_stbc = HAL_TX_DESC_GET_64(tx_tlv,
  2710. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2711. STBC);
  2712. group_id = HAL_TX_DESC_GET_64(tx_tlv,
  2713. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2714. GROUP_ID);
  2715. /* nss_comb is su nss, MU nss and partial AID */
  2716. nss_comb = HAL_TX_DESC_GET_64(tx_tlv,
  2717. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2718. N_STS);
  2719. /* if it is SU */
  2720. nss_su = (nss_comb & 0x7) + 1;
  2721. /* partial aid - applicable only for SU */
  2722. partial_aid = (nss_comb >> 3) & 0x1F;
  2723. /* if it is MU */
  2724. nss_mu[0] = (nss_comb & 0x7) + 1;
  2725. nss_mu[1] = ((nss_comb >> 3) & 0x7) + 1;
  2726. nss_mu[2] = ((nss_comb >> 6) & 0x7) + 1;
  2727. nss_mu[3] = ((nss_comb >> 9) & 0x7) + 1;
  2728. sgi = HAL_TX_DESC_GET_64(tx_tlv,
  2729. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2730. GI_SETTING);
  2731. coding = HAL_TX_DESC_GET_64(tx_tlv,
  2732. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2733. SU_MU_CODING);
  2734. mcs = HAL_TX_DESC_GET_64(tx_tlv,
  2735. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2736. MCS);
  2737. beamformed = HAL_TX_DESC_GET_64(tx_tlv,
  2738. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2739. BEAMFORMED);
  2740. TXMON_HAL_STATUS(ppdu_info, ldpc) =
  2741. (coding == HAL_SU_MU_CODING_LDPC) ? 1 : 0;
  2742. TXMON_STATUS_INFO(tx_status_info, sw_frame_group_id) = group_id;
  2743. TXMON_HAL_STATUS(ppdu_info, sgi) = sgi;
  2744. TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc;
  2745. TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth;
  2746. TXMON_HAL_STATUS(ppdu_info, beamformed) = beamformed;
  2747. if (group_id == 0 || group_id == 63) {
  2748. TXMON_HAL_STATUS(ppdu_info, reception_type) =
  2749. HAL_RX_TYPE_SU;
  2750. TXMON_HAL_STATUS(ppdu_info, mcs) = mcs;
  2751. TXMON_HAL_STATUS(ppdu_info, nss) =
  2752. nss_su & VHT_SIG_SU_NSS_MASK;
  2753. TXMON_HAL_USER(ppdu_info, user_id,
  2754. vht_flag_values3[0]) = ((mcs << 4) |
  2755. nss_su);
  2756. } else {
  2757. TXMON_HAL_STATUS(ppdu_info, reception_type) =
  2758. HAL_RX_TYPE_MU_MIMO;
  2759. TXMON_HAL_USER(ppdu_info, user_id, mcs) = mcs;
  2760. TXMON_HAL_USER(ppdu_info, user_id, nss) =
  2761. nss_su & VHT_SIG_SU_NSS_MASK;
  2762. TXMON_HAL_USER(ppdu_info, user_id,
  2763. vht_flag_values3[0]) = ((mcs << 4) |
  2764. nss_su);
  2765. TXMON_HAL_USER(ppdu_info, user_id,
  2766. vht_flag_values3[1]) = ((mcs << 4) |
  2767. nss_mu[1]);
  2768. TXMON_HAL_USER(ppdu_info, user_id,
  2769. vht_flag_values3[2]) = ((mcs << 4) |
  2770. nss_mu[2]);
  2771. TXMON_HAL_USER(ppdu_info, user_id,
  2772. vht_flag_values3[3]) = ((mcs << 4) |
  2773. nss_mu[3]);
  2774. }
  2775. /* TODO: loop over multiple user */
  2776. TXMON_HAL_USER(ppdu_info, user_id,
  2777. vht_flag_values2) = bandwidth;
  2778. TXMON_HAL_USER(ppdu_info, user_id,
  2779. vht_flag_values4) = coding;
  2780. TXMON_HAL_USER(ppdu_info, user_id,
  2781. vht_flag_values5) = group_id;
  2782. TXMON_HAL_USER(ppdu_info, user_id,
  2783. vht_flag_values6) = partial_aid;
  2784. SHOW_DEFINED(WIFIMACTX_VHT_SIG_A_E);
  2785. break;
  2786. }
  2787. case WIFIMACTX_VHT_SIG_B_MU160_E:
  2788. {
  2789. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU160_E);
  2790. break;
  2791. }
  2792. case WIFIMACTX_VHT_SIG_B_MU80_E:
  2793. {
  2794. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU80_E);
  2795. break;
  2796. }
  2797. case WIFIMACTX_VHT_SIG_B_MU40_E:
  2798. {
  2799. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU40_E);
  2800. break;
  2801. }
  2802. case WIFIMACTX_VHT_SIG_B_MU20_E:
  2803. {
  2804. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU20_E);
  2805. break;
  2806. }
  2807. case WIFIMACTX_VHT_SIG_B_SU160_E:
  2808. {
  2809. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU160_E);
  2810. break;
  2811. }
  2812. case WIFIMACTX_VHT_SIG_B_SU80_E:
  2813. {
  2814. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU80_E);
  2815. break;
  2816. }
  2817. case WIFIMACTX_VHT_SIG_B_SU40_E:
  2818. {
  2819. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU40_E);
  2820. break;
  2821. }
  2822. case WIFIMACTX_VHT_SIG_B_SU20_E:
  2823. {
  2824. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU20_E);
  2825. break;
  2826. }
  2827. case WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E:
  2828. {
  2829. SHOW_DEFINED(WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E);
  2830. break;
  2831. }
  2832. case WIFIMACTX_USER_DESC_PER_USER_E:
  2833. {
  2834. hal_txmon_parse_user_desc_per_user(tx_tlv, user_id, ppdu_info);
  2835. SHOW_DEFINED(WIFIMACTX_USER_DESC_PER_USER_E);
  2836. break;
  2837. }
  2838. case WIFIMACTX_USER_DESC_COMMON_E:
  2839. {
  2840. hal_txmon_parse_user_desc_common(tx_tlv, user_id, ppdu_info);
  2841. /* copy per user info to all user */
  2842. SHOW_DEFINED(WIFIMACTX_USER_DESC_COMMON_E);
  2843. break;
  2844. }
  2845. case WIFIMACTX_PHY_DESC_E:
  2846. {
  2847. /* pkt_type - preamble type */
  2848. uint32_t pkt_type = 0;
  2849. uint8_t bandwidth = 0;
  2850. uint8_t is_stbc = 0;
  2851. uint8_t is_triggered = 0;
  2852. uint8_t gi = 0;
  2853. uint8_t he_ppdu_subtype = 0;
  2854. uint32_t ltf_size = 0;
  2855. uint32_t he_data1 = 0;
  2856. uint32_t he_data2 = 0;
  2857. uint32_t he_data3 = 0;
  2858. uint32_t he_data5 = 0;
  2859. uint16_t he_mu_flag_1 = 0;
  2860. uint16_t he_mu_flag_2 = 0;
  2861. uint16_t num_users = 0;
  2862. uint8_t i = 0;
  2863. SHOW_DEFINED(WIFIMACTX_PHY_DESC_E);
  2864. status = HAL_MON_MACTX_PHY_DESC;
  2865. num_users = TXMON_HAL(ppdu_info, num_users);
  2866. pkt_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, PKT_TYPE);
  2867. is_stbc = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, STBC);
  2868. is_triggered = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2869. TRIGGERED);
  2870. if (!is_triggered) {
  2871. bandwidth = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2872. BANDWIDTH);
  2873. } else {
  2874. /*
  2875. * is_triggered, bw is minimum of AP pkt bw
  2876. * or STA bw
  2877. */
  2878. bandwidth = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2879. AP_PKT_BW);
  2880. }
  2881. gi = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2882. CP_SETTING);
  2883. ltf_size = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, LTF_SIZE);
  2884. he_ppdu_subtype = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2885. HE_PPDU_SUBTYPE);
  2886. TXMON_HAL_STATUS(ppdu_info, preamble_type) = pkt_type;
  2887. TXMON_HAL_STATUS(ppdu_info, ltf_size) = ltf_size;
  2888. TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc;
  2889. TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth;
  2890. switch (ppdu_info->rx_status.preamble_type) {
  2891. case TXMON_PKT_TYPE_11N_MM:
  2892. TXMON_HAL_STATUS(ppdu_info, ht_flags) = 1;
  2893. TXMON_HAL_STATUS(ppdu_info,
  2894. rtap_flags) |= HT_SGI_PRESENT;
  2895. break;
  2896. case TXMON_PKT_TYPE_11AC:
  2897. TXMON_HAL_STATUS(ppdu_info, vht_flags) = 1;
  2898. break;
  2899. case TXMON_PKT_TYPE_11AX:
  2900. TXMON_HAL_STATUS(ppdu_info, he_flags) = 1;
  2901. break;
  2902. default:
  2903. break;
  2904. }
  2905. if (!TXMON_HAL_STATUS(ppdu_info, he_flags))
  2906. break;
  2907. /* update he flags */
  2908. /* PPDU FORMAT */
  2909. switch (he_ppdu_subtype) {
  2910. case TXMON_HE_SUBTYPE_SU:
  2911. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2912. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  2913. break;
  2914. case TXMON_HE_SUBTYPE_TRIG:
  2915. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2916. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  2917. break;
  2918. case TXMON_HE_SUBTYPE_MU:
  2919. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2920. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  2921. break;
  2922. case TXMON_HE_SUBTYPE_EXT_SU:
  2923. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2924. QDF_MON_STATUS_HE_EXT_SU_FORMAT_TYPE;
  2925. break;
  2926. };
  2927. /* STBC */
  2928. he_data1 |= QDF_MON_STATUS_HE_STBC_KNOWN;
  2929. he_data3 |= (is_stbc << QDF_MON_STATUS_STBC_SHIFT);
  2930. /* GI */
  2931. he_data2 |= QDF_MON_STATUS_HE_GI_KNOWN;
  2932. he_data5 |= (gi << QDF_MON_STATUS_GI_SHIFT);
  2933. /* Data BW and RU allocation */
  2934. he_data1 |= QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN;
  2935. he_data5 = (he_data5 & 0xFFF0) | bandwidth;
  2936. he_data2 |= QDF_MON_STATUS_LTF_SYMBOLS_KNOWN;
  2937. he_data5 |= ((1 + ltf_size) <<
  2938. QDF_MON_STATUS_HE_LTF_SIZE_SHIFT);
  2939. TXMON_HAL_STATUS(ppdu_info,
  2940. he_mu_flags) = IS_MULTI_USERS(num_users);
  2941. /* MAC TX PHY DESC is not a user tlv */
  2942. for (i = 0; i < num_users; i++) {
  2943. TXMON_HAL_USER(ppdu_info, i, he_data1) = he_data1;
  2944. TXMON_HAL_USER(ppdu_info, i, he_data2) = he_data2;
  2945. TXMON_HAL_USER(ppdu_info, i, he_data3) = he_data3;
  2946. TXMON_HAL_USER(ppdu_info, i, he_data5) = he_data5;
  2947. /* HE MU flags */
  2948. TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1;
  2949. TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2;
  2950. }
  2951. break;
  2952. }
  2953. case WIFICOEX_RX_STATUS_E:
  2954. {
  2955. SHOW_DEFINED(WIFICOEX_RX_STATUS_E);
  2956. break;
  2957. }
  2958. case WIFIRX_PPDU_ACK_REPORT_E:
  2959. {
  2960. SHOW_DEFINED(WIFIRX_PPDU_ACK_REPORT_E);
  2961. break;
  2962. }
  2963. case WIFIRX_PPDU_NO_ACK_REPORT_E:
  2964. {
  2965. SHOW_DEFINED(WIFIRX_PPDU_NO_ACK_REPORT_E);
  2966. break;
  2967. }
  2968. case WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E:
  2969. {
  2970. SHOW_DEFINED(WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E);
  2971. break;
  2972. }
  2973. case WIFITXPCU_PHYTX_DEBUG32_E:
  2974. {
  2975. SHOW_DEFINED(WIFITXPCU_PHYTX_DEBUG32_E);
  2976. break;
  2977. }
  2978. case WIFITXPCU_PREAMBLE_DONE_E:
  2979. {
  2980. SHOW_DEFINED(WIFITXPCU_PREAMBLE_DONE_E);
  2981. break;
  2982. }
  2983. case WIFIRX_PHY_SLEEP_E:
  2984. {
  2985. SHOW_DEFINED(WIFIRX_PHY_SLEEP_E);
  2986. break;
  2987. }
  2988. case WIFIRX_FRAME_BITMAP_REQ_E:
  2989. {
  2990. SHOW_DEFINED(WIFIRX_FRAME_BITMAP_REQ_E);
  2991. break;
  2992. }
  2993. case WIFIRXPCU_TX_SETUP_CLEAR_E:
  2994. {
  2995. SHOW_DEFINED(WIFIRXPCU_TX_SETUP_CLEAR_E);
  2996. break;
  2997. }
  2998. case WIFIRX_TRIG_INFO_E:
  2999. {
  3000. SHOW_DEFINED(WIFIRX_TRIG_INFO_E);
  3001. break;
  3002. }
  3003. case WIFIEXPECTED_RESPONSE_E:
  3004. {
  3005. SHOW_DEFINED(WIFIEXPECTED_RESPONSE_E);
  3006. break;
  3007. }
  3008. case WIFITRIGGER_RESPONSE_TX_DONE_E:
  3009. {
  3010. SHOW_DEFINED(WIFITRIGGER_RESPONSE_TX_DONE_E);
  3011. break;
  3012. }
  3013. case WIFIFW2SW_MON_E:
  3014. {
  3015. /* parse fw2sw tlv */
  3016. hal_txmon_parse_fw2sw(tx_tlv, tlv_user_id, data_status_info);
  3017. status = HAL_MON_TX_FW2SW;
  3018. SHOW_DEFINED(WIFIFW2SW_MON_E);
  3019. break;
  3020. }
  3021. }
  3022. return status;
  3023. }
  3024. #endif /* WLAN_PKT_CAPTURE_TX_2_0 */
  3025. #ifdef REO_SHARED_QREF_TABLE_EN
  3026. static void hal_reo_shared_qaddr_cache_clear_be(hal_soc_handle_t hal_soc_hdl)
  3027. {
  3028. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  3029. uint32_t reg_val = 0;
  3030. /* Set Qdesc clear bit to erase REO internal storage for Qdesc pointers
  3031. * of 37 peer/tids
  3032. */
  3033. reg_val = HAL_REG_READ(hal, HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE));
  3034. reg_val |= HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1);
  3035. HAL_REG_WRITE(hal,
  3036. HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
  3037. reg_val);
  3038. /* Clear Qdesc clear bit to erase REO internal storage for Qdesc pointers
  3039. * of 37 peer/tids
  3040. */
  3041. reg_val &= ~(HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1));
  3042. HAL_REG_WRITE(hal,
  3043. HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
  3044. reg_val);
  3045. hal_verbose_debug("hal_soc: %pK :Setting CLEAR_DESC_ARRAY field of"
  3046. "WCSS_UMAC_REO_R0_QDESC_ADDR_READ and resetting back"
  3047. "to erase stale entries in reo storage: regval:%x", hal, reg_val);
  3048. }
  3049. /* hal_reo_shared_qaddr_write(): Write REO tid queue addr
  3050. * LUT shared by SW and HW at the index given by peer id
  3051. * and tid.
  3052. *
  3053. * @hal_soc: hal soc pointer
  3054. * @reo_qref_addr: pointer to index pointed to be peer_id
  3055. * and tid
  3056. * @tid: tid queue number
  3057. * @hw_qdesc_paddr: reo queue addr
  3058. */
  3059. static void hal_reo_shared_qaddr_write_be(hal_soc_handle_t hal_soc_hdl,
  3060. uint16_t peer_id,
  3061. int tid,
  3062. qdf_dma_addr_t hw_qdesc_paddr)
  3063. {
  3064. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  3065. struct rx_reo_queue_reference *reo_qref;
  3066. uint32_t peer_tid_idx;
  3067. /* Plug hw_desc_addr in Host reo queue reference table */
  3068. if (HAL_PEER_ID_IS_MLO(peer_id)) {
  3069. peer_tid_idx = ((peer_id - HAL_ML_PEER_ID_START) *
  3070. DP_MAX_TIDS) + tid;
  3071. reo_qref = (struct rx_reo_queue_reference *)
  3072. &hal->reo_qref.mlo_reo_qref_table_vaddr[peer_tid_idx];
  3073. } else {
  3074. peer_tid_idx = (peer_id * DP_MAX_TIDS) + tid;
  3075. reo_qref = (struct rx_reo_queue_reference *)
  3076. &hal->reo_qref.non_mlo_reo_qref_table_vaddr[peer_tid_idx];
  3077. }
  3078. reo_qref->rx_reo_queue_desc_addr_31_0 =
  3079. hw_qdesc_paddr & 0xffffffff;
  3080. reo_qref->rx_reo_queue_desc_addr_39_32 =
  3081. (hw_qdesc_paddr & 0xff00000000) >> 32;
  3082. if (hw_qdesc_paddr != 0)
  3083. reo_qref->receive_queue_number = tid;
  3084. else
  3085. reo_qref->receive_queue_number = 0;
  3086. hal_reo_shared_qaddr_cache_clear_be(hal_soc_hdl);
  3087. hal_verbose_debug("hw_qdesc_paddr: %pK, tid: %d, reo_qref:%pK,"
  3088. "rx_reo_queue_desc_addr_31_0: %x,"
  3089. "rx_reo_queue_desc_addr_39_32: %x",
  3090. (void *)hw_qdesc_paddr, tid, reo_qref,
  3091. reo_qref->rx_reo_queue_desc_addr_31_0,
  3092. reo_qref->rx_reo_queue_desc_addr_39_32);
  3093. }
  3094. #ifdef BIG_ENDIAN_HOST
  3095. static inline void hal_reo_shared_qaddr_enable(struct hal_soc *hal)
  3096. {
  3097. HAL_REG_WRITE(hal, HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
  3098. HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, GXI_SWAP, 1) |
  3099. HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, LUT_FEATURE_ENABLE, 1));
  3100. }
  3101. #else
  3102. static inline void hal_reo_shared_qaddr_enable(struct hal_soc *hal)
  3103. {
  3104. HAL_REG_WRITE(hal, HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
  3105. HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, LUT_FEATURE_ENABLE, 1));
  3106. }
  3107. #endif
  3108. /**
  3109. * hal_reo_shared_qaddr_setup_be() - Allocate MLO and Non MLO reo queue
  3110. * reference table shared between SW and HW and initialize in Qdesc Base0
  3111. * base1 registers provided by HW.
  3112. *
  3113. * @hal_soc_hdl: HAL Soc handle
  3114. * @reo_qref: REO queue reference table
  3115. *
  3116. * Return: QDF_STATUS_SUCCESS on success else a QDF error.
  3117. */
  3118. static QDF_STATUS
  3119. hal_reo_shared_qaddr_setup_be(hal_soc_handle_t hal_soc_hdl,
  3120. struct reo_queue_ref_table *reo_qref)
  3121. {
  3122. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  3123. reo_qref->reo_qref_table_en = 1;
  3124. reo_qref->mlo_reo_qref_table_vaddr =
  3125. (uint64_t *)qdf_mem_alloc_consistent(
  3126. hal->qdf_dev, hal->qdf_dev->dev,
  3127. REO_QUEUE_REF_ML_TABLE_SIZE,
  3128. &reo_qref->mlo_reo_qref_table_paddr);
  3129. if (!reo_qref->mlo_reo_qref_table_vaddr)
  3130. return QDF_STATUS_E_NOMEM;
  3131. reo_qref->non_mlo_reo_qref_table_vaddr =
  3132. (uint64_t *)qdf_mem_alloc_consistent(
  3133. hal->qdf_dev, hal->qdf_dev->dev,
  3134. REO_QUEUE_REF_NON_ML_TABLE_SIZE,
  3135. &reo_qref->non_mlo_reo_qref_table_paddr);
  3136. if (!reo_qref->non_mlo_reo_qref_table_vaddr) {
  3137. qdf_mem_free_consistent(
  3138. hal->qdf_dev, hal->qdf_dev->dev,
  3139. REO_QUEUE_REF_ML_TABLE_SIZE,
  3140. reo_qref->mlo_reo_qref_table_vaddr,
  3141. reo_qref->mlo_reo_qref_table_paddr,
  3142. 0);
  3143. reo_qref->mlo_reo_qref_table_vaddr = NULL;
  3144. return QDF_STATUS_E_NOMEM;
  3145. }
  3146. hal_verbose_debug("MLO table start paddr:%pK,"
  3147. "Non-MLO table start paddr:%pK,"
  3148. "MLO table start vaddr: %pK,"
  3149. "Non MLO table start vaddr: %pK",
  3150. (void *)reo_qref->mlo_reo_qref_table_paddr,
  3151. (void *)reo_qref->non_mlo_reo_qref_table_paddr,
  3152. reo_qref->mlo_reo_qref_table_vaddr,
  3153. reo_qref->non_mlo_reo_qref_table_vaddr);
  3154. return QDF_STATUS_SUCCESS;
  3155. }
  3156. /**
  3157. * hal_reo_shared_qaddr_init_be() - Zero out REO qref LUT and
  3158. * write start addr of MLO and Non MLO table in HW
  3159. *
  3160. * @hal_soc_hdl: HAL Soc handle
  3161. * @qref_reset: reset qref LUT
  3162. *
  3163. * Return: None
  3164. */
  3165. static void hal_reo_shared_qaddr_init_be(hal_soc_handle_t hal_soc_hdl,
  3166. int qref_reset)
  3167. {
  3168. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  3169. if (qref_reset) {
  3170. qdf_mem_zero(hal->reo_qref.mlo_reo_qref_table_vaddr,
  3171. REO_QUEUE_REF_ML_TABLE_SIZE);
  3172. qdf_mem_zero(hal->reo_qref.non_mlo_reo_qref_table_vaddr,
  3173. REO_QUEUE_REF_NON_ML_TABLE_SIZE);
  3174. }
  3175. /* LUT_BASE0 and BASE1 registers expect upper 32bits of LUT base address
  3176. * and lower 8 bits to be 0. Shift the physical address by 8 to plug
  3177. * upper 32bits only
  3178. */
  3179. HAL_REG_WRITE(hal,
  3180. HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(REO_REG_REG_BASE),
  3181. hal->reo_qref.non_mlo_reo_qref_table_paddr >> 8);
  3182. HAL_REG_WRITE(hal,
  3183. HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(REO_REG_REG_BASE),
  3184. hal->reo_qref.mlo_reo_qref_table_paddr >> 8);
  3185. hal_reo_shared_qaddr_enable(hal);
  3186. HAL_REG_WRITE(hal,
  3187. HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(REO_REG_REG_BASE),
  3188. HAL_MS(HWIO_REO_R0_QDESC, MAX_SW_PEER_ID_MAX_SUPPORTED,
  3189. 0x1fff));
  3190. }
  3191. /**
  3192. * hal_reo_shared_qaddr_detach_be() - Free MLO and Non MLO reo queue
  3193. * reference table shared between SW and HW
  3194. *
  3195. * @hal_soc_hdl: HAL Soc handle
  3196. *
  3197. * Return: None
  3198. */
  3199. static void hal_reo_shared_qaddr_detach_be(hal_soc_handle_t hal_soc_hdl)
  3200. {
  3201. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  3202. HAL_REG_WRITE(hal,
  3203. HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(REO_REG_REG_BASE),
  3204. 0);
  3205. HAL_REG_WRITE(hal,
  3206. HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(REO_REG_REG_BASE),
  3207. 0);
  3208. }
  3209. #endif
  3210. /**
  3211. * hal_tx_vdev_mismatch_routing_set_generic_be() - set vdev mismatch exception routing
  3212. * @hal_soc_hdl: HAL SoC context
  3213. * @config: HAL_TX_VDEV_MISMATCH_TQM_NOTIFY - route via TQM
  3214. * HAL_TX_VDEV_MISMATCH_FW_NOTIFY - route via FW
  3215. *
  3216. * Return: void
  3217. */
  3218. #ifdef HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK
  3219. static inline void
  3220. hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl,
  3221. enum hal_tx_vdev_mismatch_notify
  3222. config)
  3223. {
  3224. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3225. uint32_t reg_addr, reg_val = 0;
  3226. uint32_t val = 0;
  3227. reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE);
  3228. val = HAL_REG_READ(hal_soc, reg_addr);
  3229. /* reset the corresponding bits in register */
  3230. val &= (~(HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK));
  3231. /* set config value */
  3232. reg_val = val | (config <<
  3233. HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_SHFT);
  3234. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  3235. }
  3236. #else
  3237. static inline void
  3238. hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl,
  3239. enum hal_tx_vdev_mismatch_notify
  3240. config)
  3241. {
  3242. }
  3243. #endif
  3244. /**
  3245. * hal_tx_mcast_mlo_reinject_routing_set_generic_be() - set MLO multicast reinject routing
  3246. * @hal_soc_hdl: HAL SoC context
  3247. * @config: HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY - route via FW
  3248. * HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY - route via TQM
  3249. *
  3250. * Return: void
  3251. */
  3252. #if defined(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK) && \
  3253. defined(WLAN_MCAST_MLO)
  3254. static inline void
  3255. hal_tx_mcast_mlo_reinject_routing_set_generic_be(
  3256. hal_soc_handle_t hal_soc_hdl,
  3257. enum hal_tx_mcast_mlo_reinject_notify config)
  3258. {
  3259. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3260. uint32_t reg_addr, reg_val = 0;
  3261. uint32_t val = 0;
  3262. reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE);
  3263. val = HAL_REG_READ(hal_soc, reg_addr);
  3264. /* reset the corresponding bits in register */
  3265. val &= (~(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK));
  3266. /* set config value */
  3267. reg_val = val | (config << HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_SHFT);
  3268. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  3269. }
  3270. #else
  3271. static inline void
  3272. hal_tx_mcast_mlo_reinject_routing_set_generic_be(
  3273. hal_soc_handle_t hal_soc_hdl,
  3274. enum hal_tx_mcast_mlo_reinject_notify config)
  3275. {
  3276. }
  3277. #endif
  3278. /**
  3279. * hal_get_ba_aging_timeout_be_generic() - Get BA Aging timeout
  3280. *
  3281. * @hal_soc_hdl: Opaque HAL SOC handle
  3282. * @ac: Access category
  3283. * @value: window size to get
  3284. */
  3285. static inline
  3286. void hal_get_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl,
  3287. uint8_t ac, uint32_t *value)
  3288. {
  3289. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  3290. switch (ac) {
  3291. case WME_AC_BE:
  3292. *value = HAL_REG_READ(soc,
  3293. HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
  3294. REO_REG_REG_BASE)) / 1000;
  3295. break;
  3296. case WME_AC_BK:
  3297. *value = HAL_REG_READ(soc,
  3298. HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
  3299. REO_REG_REG_BASE)) / 1000;
  3300. break;
  3301. case WME_AC_VI:
  3302. *value = HAL_REG_READ(soc,
  3303. HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
  3304. REO_REG_REG_BASE)) / 1000;
  3305. break;
  3306. case WME_AC_VO:
  3307. *value = HAL_REG_READ(soc,
  3308. HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
  3309. REO_REG_REG_BASE)) / 1000;
  3310. break;
  3311. default:
  3312. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3313. "Invalid AC: %d\n", ac);
  3314. }
  3315. }
  3316. /**
  3317. * hal_setup_link_idle_list_generic_be - Setup scattered idle list using the
  3318. * buffer list provided
  3319. *
  3320. * @soc: Opaque HAL SOC handle
  3321. * @scatter_bufs_base_paddr: Array of physical base addresses
  3322. * @scatter_bufs_base_vaddr: Array of virtual base addresses
  3323. * @num_scatter_bufs: Number of scatter buffers in the above lists
  3324. * @scatter_buf_size: Size of each scatter buffer
  3325. * @last_buf_end_offset: Offset to the last entry
  3326. * @num_entries: Total entries of all scatter bufs
  3327. *
  3328. * Return: None
  3329. */
  3330. static inline void
  3331. hal_setup_link_idle_list_generic_be(struct hal_soc *soc,
  3332. qdf_dma_addr_t scatter_bufs_base_paddr[],
  3333. void *scatter_bufs_base_vaddr[],
  3334. uint32_t num_scatter_bufs,
  3335. uint32_t scatter_buf_size,
  3336. uint32_t last_buf_end_offset,
  3337. uint32_t num_entries)
  3338. {
  3339. int i;
  3340. uint32_t *prev_buf_link_ptr = NULL;
  3341. uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size;
  3342. uint32_t val;
  3343. /* Link the scatter buffers */
  3344. for (i = 0; i < num_scatter_bufs; i++) {
  3345. if (i > 0) {
  3346. prev_buf_link_ptr[0] =
  3347. scatter_bufs_base_paddr[i] & 0xffffffff;
  3348. prev_buf_link_ptr[1] = HAL_SM(
  3349. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  3350. BASE_ADDRESS_39_32,
  3351. ((uint64_t)(scatter_bufs_base_paddr[i])
  3352. >> 32)) | HAL_SM(
  3353. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  3354. ADDRESS_MATCH_TAG,
  3355. ADDRESS_MATCH_TAG_VAL);
  3356. }
  3357. prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] +
  3358. scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE);
  3359. }
  3360. /* TBD: Register programming partly based on MLD & the rest based on
  3361. * inputs from HW team. Not complete yet.
  3362. */
  3363. reg_scatter_buf_size = (scatter_buf_size -
  3364. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) / 64;
  3365. reg_tot_scatter_buf_size = ((scatter_buf_size -
  3366. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs) / 64;
  3367. HAL_REG_WRITE(soc,
  3368. HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(
  3369. WBM_REG_REG_BASE),
  3370. HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, SCATTER_BUFFER_SIZE,
  3371. reg_scatter_buf_size) |
  3372. HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, LINK_DESC_IDLE_LIST_MODE,
  3373. 0x1));
  3374. HAL_REG_WRITE(soc,
  3375. HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(
  3376. WBM_REG_REG_BASE),
  3377. HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE,
  3378. SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST,
  3379. reg_tot_scatter_buf_size));
  3380. HAL_REG_WRITE(soc,
  3381. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(
  3382. WBM_REG_REG_BASE),
  3383. scatter_bufs_base_paddr[0] & 0xffffffff);
  3384. HAL_REG_WRITE(soc,
  3385. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(
  3386. WBM_REG_REG_BASE),
  3387. ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) &
  3388. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK);
  3389. HAL_REG_WRITE(soc,
  3390. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(
  3391. WBM_REG_REG_BASE),
  3392. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  3393. BASE_ADDRESS_39_32, ((uint64_t)(scatter_bufs_base_paddr[0])
  3394. >> 32)) |
  3395. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  3396. ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL));
  3397. /* ADDRESS_MATCH_TAG field in the above register is expected to match
  3398. * with the upper bits of link pointer. The above write sets this field
  3399. * to zero and we are also setting the upper bits of link pointers to
  3400. * zero while setting up the link list of scatter buffers above
  3401. */
  3402. /* Setup head and tail pointers for the idle list */
  3403. HAL_REG_WRITE(soc,
  3404. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(
  3405. WBM_REG_REG_BASE),
  3406. scatter_bufs_base_paddr[num_scatter_bufs - 1] & 0xffffffff);
  3407. HAL_REG_WRITE(soc,
  3408. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(
  3409. WBM_REG_REG_BASE),
  3410. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
  3411. BUFFER_ADDRESS_39_32,
  3412. ((uint64_t)(scatter_bufs_base_paddr[num_scatter_bufs - 1])
  3413. >> 32)) |
  3414. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
  3415. HEAD_POINTER_OFFSET, last_buf_end_offset >> 2));
  3416. HAL_REG_WRITE(soc,
  3417. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(
  3418. WBM_REG_REG_BASE),
  3419. scatter_bufs_base_paddr[0] & 0xffffffff);
  3420. HAL_REG_WRITE(soc,
  3421. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(
  3422. WBM_REG_REG_BASE),
  3423. scatter_bufs_base_paddr[0] & 0xffffffff);
  3424. HAL_REG_WRITE(soc,
  3425. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(
  3426. WBM_REG_REG_BASE),
  3427. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
  3428. BUFFER_ADDRESS_39_32,
  3429. ((uint64_t)(scatter_bufs_base_paddr[0]) >>
  3430. 32)) | HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
  3431. TAIL_POINTER_OFFSET, 0));
  3432. HAL_REG_WRITE(soc,
  3433. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(
  3434. WBM_REG_REG_BASE),
  3435. 2 * num_entries);
  3436. /* Set RING_ID_DISABLE */
  3437. val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1);
  3438. /*
  3439. * SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence
  3440. * check the presence of the bit before toggling it.
  3441. */
  3442. #ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK
  3443. val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1);
  3444. #endif
  3445. HAL_REG_WRITE(soc,
  3446. HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(WBM_REG_REG_BASE),
  3447. val);
  3448. }
  3449. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  3450. #define HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15 0x8000
  3451. #endif
  3452. /**
  3453. * hal_cookie_conversion_reg_cfg_generic_be() - set cookie conversion relevant register
  3454. * for REO/WBM
  3455. * @hal_soc_hdl: HAL soc handle
  3456. * @cc_cfg: structure pointer for HW cookie conversion configuration
  3457. *
  3458. * Return: None
  3459. */
  3460. static inline
  3461. void hal_cookie_conversion_reg_cfg_generic_be(hal_soc_handle_t hal_soc_hdl,
  3462. struct hal_hw_cc_config *cc_cfg)
  3463. {
  3464. uint32_t reg_addr, reg_val = 0;
  3465. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  3466. /* REO CFG */
  3467. reg_addr = HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(REO_REG_REG_BASE);
  3468. reg_val = cc_cfg->lut_base_addr_31_0;
  3469. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3470. reg_addr = HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(REO_REG_REG_BASE);
  3471. reg_val = 0;
  3472. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3473. SW_COOKIE_CONVERT_GLOBAL_ENABLE,
  3474. cc_cfg->cc_global_en);
  3475. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3476. SW_COOKIE_CONVERT_ENABLE,
  3477. cc_cfg->cc_global_en);
  3478. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3479. PAGE_ALIGNMENT,
  3480. cc_cfg->page_4k_align);
  3481. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3482. COOKIE_OFFSET_MSB,
  3483. cc_cfg->cookie_offset_msb);
  3484. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3485. COOKIE_PAGE_MSB,
  3486. cc_cfg->cookie_page_msb);
  3487. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3488. CMEM_LUT_BASE_ADDR_39_32,
  3489. cc_cfg->lut_base_addr_39_32);
  3490. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3491. /* WBM CFG */
  3492. reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(WBM_REG_REG_BASE);
  3493. reg_val = cc_cfg->lut_base_addr_31_0;
  3494. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3495. reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(WBM_REG_REG_BASE);
  3496. reg_val = 0;
  3497. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  3498. PAGE_ALIGNMENT,
  3499. cc_cfg->page_4k_align);
  3500. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  3501. COOKIE_OFFSET_MSB,
  3502. cc_cfg->cookie_offset_msb);
  3503. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  3504. COOKIE_PAGE_MSB,
  3505. cc_cfg->cookie_page_msb);
  3506. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  3507. CMEM_LUT_BASE_ADDR_39_32,
  3508. cc_cfg->lut_base_addr_39_32);
  3509. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3510. /*
  3511. * WCSS_UMAC_WBM_R0_SW_COOKIE_CONVERT_CFG default value is 0x1FE,
  3512. */
  3513. reg_addr = HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(WBM_REG_REG_BASE);
  3514. reg_val = 0;
  3515. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3516. WBM_COOKIE_CONV_GLOBAL_ENABLE,
  3517. cc_cfg->cc_global_en);
  3518. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3519. WBM2SW6_COOKIE_CONVERSION_EN,
  3520. cc_cfg->wbm2sw6_cc_en);
  3521. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3522. WBM2SW5_COOKIE_CONVERSION_EN,
  3523. cc_cfg->wbm2sw5_cc_en);
  3524. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3525. WBM2SW4_COOKIE_CONVERSION_EN,
  3526. cc_cfg->wbm2sw4_cc_en);
  3527. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3528. WBM2SW3_COOKIE_CONVERSION_EN,
  3529. cc_cfg->wbm2sw3_cc_en);
  3530. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3531. WBM2SW2_COOKIE_CONVERSION_EN,
  3532. cc_cfg->wbm2sw2_cc_en);
  3533. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3534. WBM2SW1_COOKIE_CONVERSION_EN,
  3535. cc_cfg->wbm2sw1_cc_en);
  3536. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3537. WBM2SW0_COOKIE_CONVERSION_EN,
  3538. cc_cfg->wbm2sw0_cc_en);
  3539. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3540. WBM2FW_COOKIE_CONVERSION_EN,
  3541. cc_cfg->wbm2fw_cc_en);
  3542. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3543. #ifdef HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK
  3544. reg_addr = HWIO_WBM_R0_WBM_CFG_2_ADDR(WBM_REG_REG_BASE);
  3545. reg_val = 0;
  3546. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  3547. COOKIE_DEBUG_SEL,
  3548. cc_cfg->cc_global_en);
  3549. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  3550. COOKIE_CONV_INDICATION_EN,
  3551. cc_cfg->cc_global_en);
  3552. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  3553. ERROR_PATH_COOKIE_CONV_EN,
  3554. cc_cfg->error_path_cookie_conv_en);
  3555. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  3556. RELEASE_PATH_COOKIE_CONV_EN,
  3557. cc_cfg->release_path_cookie_conv_en);
  3558. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3559. #endif
  3560. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  3561. /*
  3562. * To enable indication for HW cookie conversion done or not for
  3563. * WBM, WCSS_UMAC_WBM_R0_MISC_CONTROL spare_control field 15th
  3564. * bit spare_control[15] should be set.
  3565. */
  3566. reg_addr = HWIO_WBM_R0_MISC_CONTROL_ADDR(WBM_REG_REG_BASE);
  3567. reg_val = HAL_REG_READ(soc, reg_addr);
  3568. reg_val |= HAL_SM(HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL,
  3569. SPARE_CONTROL,
  3570. HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15);
  3571. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3572. #endif
  3573. }
  3574. /**
  3575. * hal_set_ba_aging_timeout_be_generic() - Set BA Aging timeout
  3576. * @hal_soc_hdl: Opaque HAL SOC handle
  3577. * @ac: Access category
  3578. * ac: 0 - Background, 1 - Best Effort, 2 - Video, 3 - Voice
  3579. * @value: Input value to set
  3580. */
  3581. static inline
  3582. void hal_set_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl,
  3583. uint8_t ac, uint32_t value)
  3584. {
  3585. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  3586. switch (ac) {
  3587. case WME_AC_BE:
  3588. HAL_REG_WRITE(soc,
  3589. HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
  3590. REO_REG_REG_BASE),
  3591. value * 1000);
  3592. break;
  3593. case WME_AC_BK:
  3594. HAL_REG_WRITE(soc,
  3595. HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
  3596. REO_REG_REG_BASE),
  3597. value * 1000);
  3598. break;
  3599. case WME_AC_VI:
  3600. HAL_REG_WRITE(soc,
  3601. HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
  3602. REO_REG_REG_BASE),
  3603. value * 1000);
  3604. break;
  3605. case WME_AC_VO:
  3606. HAL_REG_WRITE(soc,
  3607. HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
  3608. REO_REG_REG_BASE),
  3609. value * 1000);
  3610. break;
  3611. default:
  3612. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3613. "Invalid AC: %d\n", ac);
  3614. }
  3615. }
  3616. /**
  3617. * hal_tx_populate_bank_register_be() - populate the bank register with
  3618. * the software configs.
  3619. * @hal_soc_hdl: HAL soc handle
  3620. * @config: bank config
  3621. * @bank_id: bank id to be configured
  3622. *
  3623. * Returns: None
  3624. */
  3625. #ifdef HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT
  3626. static inline void
  3627. hal_tx_populate_bank_register_be(hal_soc_handle_t hal_soc_hdl,
  3628. union hal_tx_bank_config *config,
  3629. uint8_t bank_id)
  3630. {
  3631. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3632. uint32_t reg_addr, reg_val = 0;
  3633. reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE,
  3634. bank_id);
  3635. reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT);
  3636. reg_val |= (config->encap_type <<
  3637. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT);
  3638. reg_val |= (config->encrypt_type <<
  3639. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT);
  3640. reg_val |= (config->src_buffer_swap <<
  3641. HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT);
  3642. reg_val |= (config->link_meta_swap <<
  3643. HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT);
  3644. reg_val |= (config->index_lookup_enable <<
  3645. HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT);
  3646. reg_val |= (config->addrx_en <<
  3647. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT);
  3648. reg_val |= (config->addry_en <<
  3649. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT);
  3650. reg_val |= (config->mesh_enable <<
  3651. HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT);
  3652. reg_val |= (config->vdev_id_check_en <<
  3653. HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT);
  3654. reg_val |= (config->pmac_id <<
  3655. HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT);
  3656. reg_val |= (config->mcast_pkt_ctrl <<
  3657. HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT);
  3658. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  3659. }
  3660. #else
  3661. static inline void
  3662. hal_tx_populate_bank_register_be(hal_soc_handle_t hal_soc_hdl,
  3663. union hal_tx_bank_config *config,
  3664. uint8_t bank_id)
  3665. {
  3666. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3667. uint32_t reg_addr, reg_val = 0;
  3668. reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE,
  3669. bank_id);
  3670. reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT);
  3671. reg_val |= (config->encap_type <<
  3672. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT);
  3673. reg_val |= (config->encrypt_type <<
  3674. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT);
  3675. reg_val |= (config->src_buffer_swap <<
  3676. HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT);
  3677. reg_val |= (config->link_meta_swap <<
  3678. HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT);
  3679. reg_val |= (config->index_lookup_enable <<
  3680. HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT);
  3681. reg_val |= (config->addrx_en <<
  3682. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT);
  3683. reg_val |= (config->addry_en <<
  3684. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT);
  3685. reg_val |= (config->mesh_enable <<
  3686. HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT);
  3687. reg_val |= (config->vdev_id_check_en <<
  3688. HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT);
  3689. reg_val |= (config->pmac_id <<
  3690. HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT);
  3691. reg_val |= (config->dscp_tid_map_id <<
  3692. HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT);
  3693. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  3694. }
  3695. #endif
  3696. #ifdef HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_SHFT
  3697. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id) (vdev_id >> 0x4)
  3698. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id) (vdev_id & 0xF)
  3699. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK 0x3
  3700. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT 0x2
  3701. /**
  3702. * hal_tx_vdev_mcast_ctrl_set_be() - set mcast_ctrl value
  3703. * @hal_soc_hdl: HAL SoC context
  3704. * @vdev_id: vdev identifier
  3705. * @mcast_ctrl_val: mcast ctrl value for this VAP
  3706. *
  3707. * Return: void
  3708. */
  3709. static inline void
  3710. hal_tx_vdev_mcast_ctrl_set_be(hal_soc_handle_t hal_soc_hdl,
  3711. uint8_t vdev_id, uint8_t mcast_ctrl_val)
  3712. {
  3713. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3714. uint32_t reg_addr, reg_val = 0;
  3715. uint32_t val;
  3716. uint8_t reg_idx = HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id);
  3717. uint8_t index_in_reg =
  3718. HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id);
  3719. reg_addr =
  3720. HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(MAC_TCL_REG_REG_BASE,
  3721. reg_idx);
  3722. val = HAL_REG_READ(hal_soc, reg_addr);
  3723. /* mask out other stored value */
  3724. val &= (~(HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK <<
  3725. (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg)));
  3726. reg_val = val |
  3727. ((HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK & mcast_ctrl_val) <<
  3728. (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg));
  3729. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  3730. }
  3731. #else
  3732. static inline void
  3733. hal_tx_vdev_mcast_ctrl_set_be(hal_soc_handle_t hal_soc_hdl,
  3734. uint8_t vdev_id, uint8_t mcast_ctrl_val)
  3735. {
  3736. }
  3737. #endif
  3738. #endif /* _HAL_BE_GENERIC_API_H_ */