dp_li_tx.c 18 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "cdp_txrx_cmn_struct.h"
  20. #include "dp_types.h"
  21. #include "dp_tx.h"
  22. #include "dp_li_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include <dp_internal.h>
  25. #include <dp_htt.h>
  26. #include <hal_li_api.h>
  27. #include <hal_li_tx.h>
  28. #include "dp_peer.h"
  29. #ifdef FEATURE_WDS
  30. #include "dp_txrx_wds.h"
  31. #endif
  32. #include "dp_li.h"
  33. extern uint8_t sec_type_map[MAX_CDP_SEC_TYPE];
  34. QDF_STATUS
  35. dp_tx_comp_get_params_from_hal_desc_li(struct dp_soc *soc,
  36. void *tx_comp_hal_desc,
  37. struct dp_tx_desc_s **r_tx_desc)
  38. {
  39. uint8_t pool_id;
  40. uint32_t tx_desc_id;
  41. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  42. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  43. DP_TX_DESC_ID_POOL_OS;
  44. /* Find Tx descriptor */
  45. *r_tx_desc = dp_tx_desc_find(soc, pool_id,
  46. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  47. DP_TX_DESC_ID_PAGE_OS,
  48. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  49. DP_TX_DESC_ID_OFFSET_OS,
  50. (tx_desc_id & DP_TX_DESC_ID_SPCL_MASK));
  51. /* Pool id is not matching. Error */
  52. if ((*r_tx_desc)->pool_id != pool_id) {
  53. dp_tx_comp_alert("Tx Comp pool id %d not matched %d",
  54. pool_id, (*r_tx_desc)->pool_id);
  55. qdf_assert_always(0);
  56. }
  57. (*r_tx_desc)->peer_id = hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  58. return QDF_STATUS_SUCCESS;
  59. }
  60. static inline
  61. void dp_tx_process_mec_notify_li(struct dp_soc *soc, uint8_t *status)
  62. {
  63. struct dp_vdev *vdev;
  64. uint8_t vdev_id;
  65. uint32_t *htt_desc = (uint32_t *)status;
  66. /*
  67. * Get vdev id from HTT status word in case of MEC
  68. * notification
  69. */
  70. vdev_id = HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(htt_desc[3]);
  71. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  72. return;
  73. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  74. DP_MOD_ID_HTT_COMP);
  75. if (!vdev)
  76. return;
  77. dp_tx_mec_handler(vdev, status);
  78. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  79. }
  80. void dp_tx_process_htt_completion_li(struct dp_soc *soc,
  81. struct dp_tx_desc_s *tx_desc,
  82. uint8_t *status,
  83. uint8_t ring_id)
  84. {
  85. uint8_t tx_status;
  86. struct dp_pdev *pdev;
  87. struct dp_vdev *vdev = NULL;
  88. struct hal_tx_completion_status ts = {0};
  89. uint32_t *htt_desc = (uint32_t *)status;
  90. struct dp_txrx_peer *txrx_peer;
  91. dp_txrx_ref_handle txrx_ref_handle = NULL;
  92. struct cdp_tid_tx_stats *tid_stats = NULL;
  93. struct htt_soc *htt_handle;
  94. uint8_t vdev_id;
  95. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  96. htt_handle = (struct htt_soc *)soc->htt_handle;
  97. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  98. /*
  99. * There can be scenario where WBM consuming descriptor enqueued
  100. * from TQM2WBM first and TQM completion can happen before MEC
  101. * notification comes from FW2WBM. Avoid access any field of tx
  102. * descriptor in case of MEC notify.
  103. */
  104. if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY)
  105. return dp_tx_process_mec_notify_li(soc, status);
  106. /*
  107. * If the descriptor is already freed in vdev_detach,
  108. * continue to next descriptor
  109. */
  110. if (qdf_unlikely(!tx_desc->flags)) {
  111. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  112. tx_desc->id);
  113. return;
  114. }
  115. if (qdf_unlikely(tx_desc->vdev_id == DP_INVALID_VDEV_ID)) {
  116. dp_tx_comp_info_rl("Invalid vdev_id %d", tx_desc->id);
  117. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  118. goto release_tx_desc;
  119. }
  120. pdev = tx_desc->pdev;
  121. if (qdf_unlikely(!pdev)) {
  122. dp_tx_comp_warn("The pdev in TX desc is NULL, dropped.");
  123. dp_tx_comp_warn("tx_status: %u", tx_status);
  124. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  125. goto release_tx_desc;
  126. }
  127. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  128. dp_tx_comp_info_rl("pdev in down state %d", tx_desc->id);
  129. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  130. goto release_tx_desc;
  131. }
  132. qdf_assert(tx_desc->pdev);
  133. vdev_id = tx_desc->vdev_id;
  134. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  135. DP_MOD_ID_HTT_COMP);
  136. if (qdf_unlikely(!vdev)) {
  137. dp_tx_comp_info_rl("Unable to get vdev ref %d", tx_desc->id);
  138. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  139. goto release_tx_desc;
  140. }
  141. switch (tx_status) {
  142. case HTT_TX_FW2WBM_TX_STATUS_OK:
  143. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  144. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  145. {
  146. uint8_t tid;
  147. uint8_t transmit_cnt_valid = 0;
  148. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  149. ts.peer_id =
  150. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  151. htt_desc[2]);
  152. ts.tid =
  153. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  154. htt_desc[2]);
  155. } else {
  156. ts.peer_id = HTT_INVALID_PEER;
  157. ts.tid = HTT_INVALID_TID;
  158. }
  159. ts.release_src = HAL_TX_COMP_RELEASE_SOURCE_FW;
  160. ts.ppdu_id =
  161. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  162. htt_desc[1]);
  163. ts.ack_frame_rssi =
  164. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  165. htt_desc[1]);
  166. transmit_cnt_valid =
  167. HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_GET(
  168. htt_desc[2]);
  169. if (transmit_cnt_valid)
  170. ts.transmit_cnt =
  171. HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_GET(
  172. htt_desc[0]);
  173. ts.tsf = htt_desc[3];
  174. ts.first_msdu = 1;
  175. ts.last_msdu = 1;
  176. switch (tx_status) {
  177. case HTT_TX_FW2WBM_TX_STATUS_OK:
  178. ts.status = HAL_TX_TQM_RR_FRAME_ACKED;
  179. break;
  180. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  181. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  182. break;
  183. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  184. ts.status = HAL_TX_TQM_RR_REM_CMD_TX;
  185. break;
  186. }
  187. tid = ts.tid;
  188. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  189. tid = CDP_MAX_DATA_TIDS - 1;
  190. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  191. if (qdf_unlikely(pdev->delay_stats_flag) ||
  192. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(vdev)))
  193. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  194. if (tx_status < CDP_MAX_TX_HTT_STATUS)
  195. tid_stats->htt_status_cnt[tx_status]++;
  196. txrx_peer = dp_txrx_peer_get_ref_by_id(soc, ts.peer_id,
  197. &txrx_ref_handle,
  198. DP_MOD_ID_HTT_COMP);
  199. if (qdf_likely(txrx_peer)) {
  200. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1,
  201. qdf_nbuf_len(tx_desc->nbuf));
  202. if (tx_status != HTT_TX_FW2WBM_TX_STATUS_OK)
  203. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  204. }
  205. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, txrx_peer,
  206. ring_id);
  207. dp_tx_comp_process_desc(soc, tx_desc, &ts, txrx_peer);
  208. dp_tx_desc_release(soc, tx_desc, tx_desc->pool_id);
  209. if (qdf_likely(txrx_peer))
  210. dp_txrx_peer_unref_delete(txrx_ref_handle,
  211. DP_MOD_ID_HTT_COMP);
  212. break;
  213. }
  214. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  215. {
  216. uint8_t reinject_reason;
  217. reinject_reason =
  218. HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_GET(
  219. htt_desc[0]);
  220. dp_tx_reinject_handler(soc, vdev, tx_desc,
  221. status, reinject_reason);
  222. break;
  223. }
  224. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  225. {
  226. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  227. break;
  228. }
  229. case HTT_TX_FW2WBM_TX_STATUS_VDEVID_MISMATCH:
  230. {
  231. DP_STATS_INC(vdev,
  232. tx_i[DP_XMIT_LINK].dropped.fail_per_pkt_vdev_id_check,
  233. 1);
  234. goto release_tx_desc;
  235. }
  236. default:
  237. dp_tx_comp_err("Invalid HTT tx_status %d\n",
  238. tx_status);
  239. goto release_tx_desc;
  240. }
  241. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  242. return;
  243. release_tx_desc:
  244. dp_tx_comp_free_buf(soc, tx_desc, false);
  245. dp_tx_desc_release(soc, tx_desc, tx_desc->pool_id);
  246. if (vdev)
  247. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  248. }
  249. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  250. /**
  251. * dp_tx_get_rbm_id_li() - Get the RBM ID for data transmission completion.
  252. * @soc: DP soc structure pointer
  253. * @ring_id: Transmit Queue/ring_id to be used when XPS is enabled
  254. *
  255. * Return: HAL ring handle
  256. */
  257. #ifdef IPA_OFFLOAD
  258. static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
  259. uint8_t ring_id)
  260. {
  261. return (ring_id + soc->wbm_sw0_bm_id);
  262. }
  263. #else
  264. #ifndef QCA_DP_ENABLE_TX_COMP_RING4
  265. static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
  266. uint8_t ring_id)
  267. {
  268. return (ring_id ? HAL_WBM_SW0_BM_ID + (ring_id - 1) :
  269. HAL_WBM_SW2_BM_ID);
  270. }
  271. #else
  272. static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
  273. uint8_t ring_id)
  274. {
  275. if (ring_id == soc->num_tcl_data_rings)
  276. return HAL_WBM_SW4_BM_ID(soc->wbm_sw0_bm_id);
  277. return (ring_id + HAL_WBM_SW0_BM_ID(soc->wbm_sw0_bm_id));
  278. }
  279. #endif
  280. #endif
  281. #else
  282. #ifdef TX_MULTI_TCL
  283. #ifdef IPA_OFFLOAD
  284. static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
  285. uint8_t ring_id)
  286. {
  287. if (soc->wlan_cfg_ctx->ipa_enabled)
  288. return (ring_id + soc->wbm_sw0_bm_id);
  289. return soc->wlan_cfg_ctx->tcl_wbm_map_array[ring_id].wbm_rbm_id;
  290. }
  291. #else
  292. static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
  293. uint8_t ring_id)
  294. {
  295. return soc->wlan_cfg_ctx->tcl_wbm_map_array[ring_id].wbm_rbm_id;
  296. }
  297. #endif
  298. #else
  299. static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
  300. uint8_t ring_id)
  301. {
  302. return (ring_id + soc->wbm_sw0_bm_id);
  303. }
  304. #endif
  305. #endif
  306. #if defined(CLEAR_SW2TCL_CONSUMED_DESC)
  307. /**
  308. * dp_tx_clear_consumed_hw_descs - Reset all the consumed Tx ring descs to 0
  309. *
  310. * @soc: DP soc handle
  311. * @hal_ring_hdl: Source ring pointer
  312. *
  313. * Return: void
  314. */
  315. static inline
  316. void dp_tx_clear_consumed_hw_descs(struct dp_soc *soc,
  317. hal_ring_handle_t hal_ring_hdl)
  318. {
  319. void *desc = hal_srng_src_get_next_consumed(soc->hal_soc, hal_ring_hdl);
  320. while (desc) {
  321. hal_tx_desc_clear(desc);
  322. desc = hal_srng_src_get_next_consumed(soc->hal_soc,
  323. hal_ring_hdl);
  324. }
  325. }
  326. #else
  327. static inline
  328. void dp_tx_clear_consumed_hw_descs(struct dp_soc *soc,
  329. hal_ring_handle_t hal_ring_hdl)
  330. {
  331. }
  332. #endif /* CLEAR_SW2TCL_CONSUMED_DESC */
  333. #ifdef WLAN_CONFIG_TX_DELAY
  334. static inline
  335. QDF_STATUS dp_tx_compute_hw_delay_li(struct dp_soc *soc,
  336. struct dp_vdev *vdev,
  337. struct hal_tx_completion_status *ts,
  338. uint32_t *delay_us)
  339. {
  340. return dp_tx_compute_hw_delay_us(ts, vdev->delta_tsf, delay_us);
  341. }
  342. #else
  343. static inline
  344. QDF_STATUS dp_tx_compute_hw_delay_li(struct dp_soc *soc,
  345. struct dp_vdev *vdev,
  346. struct hal_tx_completion_status *ts,
  347. uint32_t *delay_us)
  348. {
  349. return QDF_STATUS_SUCCESS;
  350. }
  351. #endif
  352. #ifdef CONFIG_SAWF
  353. /**
  354. * dp_sawf_config_li - Configure sawf specific fields in tcl
  355. *
  356. * @soc: DP soc handle
  357. * @hal_tx_desc_cached: tx descriptor
  358. * @fw_metadata: firmware metadata
  359. * @vdev_id: vdev id
  360. * @nbuf: skb buffer
  361. * @msdu_info: msdu info
  362. *
  363. * Return: void
  364. */
  365. static inline
  366. void dp_sawf_config_li(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  367. uint16_t *fw_metadata, uint16_t vdev_id,
  368. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  369. {
  370. uint8_t q_id = 0;
  371. uint32_t flow_idx = 0;
  372. q_id = dp_sawf_queue_id_get(nbuf);
  373. if (q_id == DP_SAWF_DEFAULT_Q_INVALID)
  374. return;
  375. msdu_info->tid = (q_id & (CDP_DATA_TID_MAX - 1));
  376. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached,
  377. (q_id & (CDP_DATA_TID_MAX - 1)));
  378. if ((q_id >= DP_SAWF_DEFAULT_QUEUE_MIN) &&
  379. (q_id < DP_SAWF_DEFAULT_QUEUE_MAX))
  380. return;
  381. if (!wlan_cfg_get_sawf_config(soc->wlan_cfg_ctx))
  382. return;
  383. dp_sawf_tcl_cmd(fw_metadata, nbuf);
  384. /* For SAWF, q_id starts from DP_SAWF_Q_MAX */
  385. if (!dp_sawf_get_search_index(soc, nbuf, vdev_id,
  386. q_id, &flow_idx))
  387. hal_tx_desc_set_to_fw(hal_tx_desc_cached, true);
  388. hal_tx_desc_set_search_type_li(soc->hal_soc, hal_tx_desc_cached,
  389. HAL_TX_ADDR_INDEX_SEARCH);
  390. hal_tx_desc_set_search_index_li(soc->hal_soc, hal_tx_desc_cached,
  391. flow_idx);
  392. }
  393. #else
  394. static inline
  395. void dp_sawf_config_li(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  396. uint16_t *fw_metadata, uint16_t vdev_id,
  397. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  398. {
  399. }
  400. #define dp_sawf_tx_enqueue_peer_stats(soc, tx_desc)
  401. #define dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc)
  402. #endif
  403. QDF_STATUS
  404. dp_tx_hw_enqueue_li(struct dp_soc *soc, struct dp_vdev *vdev,
  405. struct dp_tx_desc_s *tx_desc, uint16_t fw_metadata,
  406. struct cdp_tx_exception_metadata *tx_exc_metadata,
  407. struct dp_tx_msdu_info_s *msdu_info)
  408. {
  409. void *hal_tx_desc;
  410. uint32_t *hal_tx_desc_cached;
  411. int coalesce = 0;
  412. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  413. uint8_t ring_id = tx_q->ring_id & DP_TX_QUEUE_MASK;
  414. uint8_t tid;
  415. /*
  416. * Setting it initialization statically here to avoid
  417. * a memset call jump with qdf_mem_set call
  418. */
  419. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  420. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  421. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  422. tx_exc_metadata->sec_type : vdev->sec_type);
  423. /* Return Buffer Manager ID */
  424. uint8_t bm_id = dp_tx_get_rbm_id_li(soc, ring_id);
  425. hal_ring_handle_t hal_ring_hdl = NULL;
  426. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  427. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  428. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  429. return QDF_STATUS_E_RESOURCES;
  430. }
  431. hal_tx_desc_cached = (void *)cached_desc;
  432. hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
  433. tx_desc->dma_addr, bm_id, tx_desc->id,
  434. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG));
  435. hal_tx_desc_set_lmac_id_li(soc->hal_soc, hal_tx_desc_cached,
  436. vdev->lmac_id);
  437. hal_tx_desc_set_search_type_li(soc->hal_soc, hal_tx_desc_cached,
  438. vdev->search_type);
  439. hal_tx_desc_set_search_index_li(soc->hal_soc, hal_tx_desc_cached,
  440. vdev->bss_ast_idx);
  441. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  442. vdev->dscp_tid_map_id);
  443. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  444. sec_type_map[sec_type]);
  445. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  446. (vdev->bss_ast_hash & 0xF));
  447. if (dp_sawf_tag_valid_get(tx_desc->nbuf)) {
  448. dp_sawf_config_li(soc, hal_tx_desc_cached, &fw_metadata,
  449. vdev->vdev_id, tx_desc->nbuf, msdu_info);
  450. dp_sawf_tx_enqueue_peer_stats(soc, tx_desc);
  451. }
  452. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  453. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  454. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  455. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  456. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  457. vdev->hal_desc_addr_search_flags);
  458. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  459. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  460. /* verify checksum offload configuration*/
  461. if ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) ==
  462. QDF_NBUF_TX_CKSUM_TCP_UDP) ||
  463. qdf_nbuf_is_tso(tx_desc->nbuf)) {
  464. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  465. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  466. }
  467. tid = msdu_info->tid;
  468. if (tid != HTT_TX_EXT_TID_INVALID)
  469. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  470. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  471. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  472. if (!dp_tx_desc_set_ktimestamp(vdev, tx_desc))
  473. dp_tx_desc_set_timestamp(tx_desc);
  474. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  475. tx_desc->length,
  476. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG),
  477. (uint64_t)tx_desc->dma_addr, tx_desc->pkt_offset,
  478. tx_desc->id);
  479. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  480. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  481. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  482. "%s %d : HAL RING Access Failed -- %pK",
  483. __func__, __LINE__, hal_ring_hdl);
  484. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  485. DP_STATS_INC(vdev, tx_i[DP_XMIT_LINK].dropped.enqueue_fail,
  486. 1);
  487. dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc);
  488. return status;
  489. }
  490. dp_tx_clear_consumed_hw_descs(soc, hal_ring_hdl);
  491. /* Sync cached descriptor with HW */
  492. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  493. if (qdf_unlikely(!hal_tx_desc)) {
  494. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  495. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  496. DP_STATS_INC(vdev, tx_i[DP_XMIT_LINK].dropped.enqueue_fail,
  497. 1);
  498. dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc);
  499. goto ring_access_fail;
  500. }
  501. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  502. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  503. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  504. coalesce = dp_tx_attempt_coalescing(soc, vdev, tx_desc, tid,
  505. msdu_info, ring_id);
  506. DP_STATS_INC_PKT(vdev, tx_i[DP_XMIT_LINK].processed, 1,
  507. tx_desc->length);
  508. DP_STATS_INC(soc, tx.tcl_enq[ring_id], 1);
  509. dp_tx_update_stats(soc, tx_desc, ring_id);
  510. status = QDF_STATUS_SUCCESS;
  511. dp_tx_hw_desc_update_evt((uint8_t *)hal_tx_desc_cached,
  512. hal_ring_hdl, soc, ring_id);
  513. ring_access_fail:
  514. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, coalesce);
  515. dp_pkt_add_timestamp(vdev, QDF_PKT_TX_DRIVER_EXIT,
  516. qdf_get_log_timestamp(), tx_desc->nbuf);
  517. return status;
  518. }
  519. QDF_STATUS dp_tx_desc_pool_init_li(struct dp_soc *soc,
  520. uint32_t num_elem,
  521. uint8_t pool_id,
  522. bool spcl_tx_desc)
  523. {
  524. uint32_t id, count, page_id, offset, pool_id_32;
  525. struct dp_tx_desc_s *tx_desc;
  526. struct dp_tx_desc_pool_s *tx_desc_pool;
  527. uint16_t num_desc_per_page;
  528. if (spcl_tx_desc)
  529. tx_desc_pool = dp_get_spcl_tx_desc_pool(soc, pool_id);
  530. else
  531. tx_desc_pool = dp_get_tx_desc_pool(soc, pool_id);
  532. tx_desc = tx_desc_pool->freelist;
  533. count = 0;
  534. pool_id_32 = (uint32_t)pool_id;
  535. num_desc_per_page = tx_desc_pool->desc_pages.num_element_per_page;
  536. while (tx_desc) {
  537. page_id = count / num_desc_per_page;
  538. offset = count % num_desc_per_page;
  539. id = ((!!spcl_tx_desc) << DP_TX_DESC_ID_SPCL_OS |
  540. (pool_id_32 << DP_TX_DESC_ID_POOL_OS) |
  541. (page_id << DP_TX_DESC_ID_PAGE_OS) | offset);
  542. tx_desc->id = id;
  543. tx_desc->pool_id = pool_id;
  544. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  545. dp_tx_desc_set_magic(tx_desc, DP_TX_MAGIC_PATTERN_FREE);
  546. tx_desc = tx_desc->next;
  547. count++;
  548. }
  549. return QDF_STATUS_SUCCESS;
  550. }
  551. void dp_tx_desc_pool_deinit_li(struct dp_soc *soc,
  552. struct dp_tx_desc_pool_s *tx_desc_pool,
  553. uint8_t pool_id, bool spcl_tx_desc)
  554. {
  555. }
  556. QDF_STATUS dp_tx_compute_tx_delay_li(struct dp_soc *soc,
  557. struct dp_vdev *vdev,
  558. struct hal_tx_completion_status *ts,
  559. uint32_t *delay_us)
  560. {
  561. return dp_tx_compute_hw_delay_li(soc, vdev, ts, delay_us);
  562. }
  563. QDF_STATUS dp_tx_desc_pool_alloc_li(struct dp_soc *soc, uint32_t num_elem,
  564. uint8_t pool_id)
  565. {
  566. return QDF_STATUS_SUCCESS;
  567. }
  568. void dp_tx_desc_pool_free_li(struct dp_soc *soc, uint8_t pool_id)
  569. {
  570. }