dp_be.c 74 KB

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  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include <wlan_utility.h>
  20. #include <dp_internal.h>
  21. #include <dp_htt.h>
  22. #include "dp_be.h"
  23. #include "dp_be_tx.h"
  24. #include "dp_be_rx.h"
  25. #ifdef WIFI_MONITOR_SUPPORT
  26. #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT)
  27. #include "dp_mon_2.0.h"
  28. #endif
  29. #include "dp_mon.h"
  30. #endif
  31. #include <hal_be_api.h>
  32. #ifdef WLAN_SUPPORT_PPEDS
  33. #include "be/dp_ppeds.h"
  34. #include <ppe_vp_public.h>
  35. #include <ppe_drv_sc.h>
  36. #endif
  37. /* Generic AST entry aging timer value */
  38. #define DP_AST_AGING_TIMER_DEFAULT_MS 5000
  39. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  40. #define DP_TX_VDEV_ID_CHECK_ENABLE 0
  41. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  42. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  43. {1, 4, HAL_BE_WBM_SW4_BM_ID, 0},
  44. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  45. #ifdef QCA_WIFI_KIWI_V2
  46. {3, 5, HAL_BE_WBM_SW5_BM_ID, 0},
  47. {4, 6, HAL_BE_WBM_SW6_BM_ID, 0}
  48. #else
  49. {3, 6, HAL_BE_WBM_SW5_BM_ID, 0},
  50. {4, 7, HAL_BE_WBM_SW6_BM_ID, 0}
  51. #endif
  52. };
  53. #else
  54. #define DP_TX_VDEV_ID_CHECK_ENABLE 1
  55. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  56. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  57. {1, 1, HAL_BE_WBM_SW1_BM_ID, 0},
  58. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  59. {3, 3, HAL_BE_WBM_SW3_BM_ID, 0},
  60. {4, 4, HAL_BE_WBM_SW4_BM_ID, 0}
  61. };
  62. #endif
  63. #ifdef WLAN_SUPPORT_PPEDS
  64. static struct cdp_ppeds_txrx_ops dp_ops_ppeds_be = {
  65. .ppeds_entry_attach = dp_ppeds_attach_vdev_be,
  66. .ppeds_entry_detach = dp_ppeds_detach_vdev_be,
  67. .ppeds_set_int_pri2tid = dp_ppeds_set_int_pri2tid_be,
  68. .ppeds_update_int_pri2tid = dp_ppeds_update_int_pri2tid_be,
  69. .ppeds_entry_dump = dp_ppeds_dump_ppe_vp_tbl_be,
  70. .ppeds_enable_pri2tid = dp_ppeds_vdev_enable_pri2tid_be,
  71. .ppeds_vp_setup_recovery = dp_ppeds_vp_setup_on_fw_recovery,
  72. };
  73. static void dp_ppeds_rings_status(struct dp_soc *soc)
  74. {
  75. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  76. dp_print_ring_stat_from_hal(soc, &be_soc->reo2ppe_ring, REO2PPE);
  77. dp_print_ring_stat_from_hal(soc, &be_soc->ppe2tcl_ring, PPE2TCL);
  78. dp_print_ring_stat_from_hal(soc, &be_soc->ppeds_wbm_release_ring,
  79. WBM2SW_RELEASE);
  80. }
  81. static void dp_ppeds_inuse_desc(struct dp_soc *soc)
  82. {
  83. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  84. DP_PRINT_STATS("PPE-DS Tx Descriptors in Use = %u num_free %u",
  85. be_soc->ppeds_tx_desc.num_allocated,
  86. be_soc->ppeds_tx_desc.num_free);
  87. }
  88. #endif
  89. static void dp_soc_cfg_attach_be(struct dp_soc *soc)
  90. {
  91. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  92. wlan_cfg_set_rx_rel_ring_id(soc_cfg_ctx, WBM2SW_REL_ERR_RING_NUM);
  93. soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array;
  94. /* this is used only when dmac mode is enabled */
  95. soc->num_rx_refill_buf_rings = 1;
  96. soc->wlan_cfg_ctx->notify_frame_support =
  97. DP_MARK_NOTIFY_FRAME_SUPPORT;
  98. }
  99. qdf_size_t dp_get_context_size_be(enum dp_context_type context_type)
  100. {
  101. switch (context_type) {
  102. case DP_CONTEXT_TYPE_SOC:
  103. return sizeof(struct dp_soc_be);
  104. case DP_CONTEXT_TYPE_PDEV:
  105. return sizeof(struct dp_pdev_be);
  106. case DP_CONTEXT_TYPE_VDEV:
  107. return sizeof(struct dp_vdev_be);
  108. case DP_CONTEXT_TYPE_PEER:
  109. return sizeof(struct dp_peer_be);
  110. default:
  111. return 0;
  112. }
  113. }
  114. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  115. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  116. /**
  117. * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement
  118. * per wbm2sw ring
  119. *
  120. * @cc_cfg: HAL HW cookie conversion configuration structure pointer
  121. *
  122. * Return: None
  123. */
  124. static inline
  125. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  126. {
  127. cc_cfg->wbm2sw6_cc_en = 1;
  128. cc_cfg->wbm2sw5_cc_en = 1;
  129. cc_cfg->wbm2sw4_cc_en = 1;
  130. cc_cfg->wbm2sw3_cc_en = 1;
  131. cc_cfg->wbm2sw2_cc_en = 1;
  132. /* disable wbm2sw1 hw cc as it's for FW */
  133. cc_cfg->wbm2sw1_cc_en = 0;
  134. cc_cfg->wbm2sw0_cc_en = 1;
  135. cc_cfg->wbm2fw_cc_en = 0;
  136. }
  137. #else
  138. static inline
  139. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  140. {
  141. cc_cfg->wbm2sw6_cc_en = 1;
  142. cc_cfg->wbm2sw5_cc_en = 1;
  143. cc_cfg->wbm2sw4_cc_en = 1;
  144. cc_cfg->wbm2sw3_cc_en = 1;
  145. cc_cfg->wbm2sw2_cc_en = 1;
  146. cc_cfg->wbm2sw1_cc_en = 1;
  147. cc_cfg->wbm2sw0_cc_en = 1;
  148. cc_cfg->wbm2fw_cc_en = 0;
  149. }
  150. #endif
  151. #if defined(WLAN_SUPPORT_RX_FISA)
  152. static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
  153. {
  154. dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
  155. soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
  156. /* get CMEM for cookie conversion */
  157. if (soc->cmem_avail_size < DP_CMEM_FST_SIZE) {
  158. dp_err("cmem_size 0x%llx bytes < 16K", soc->cmem_avail_size);
  159. return QDF_STATUS_E_NOMEM;
  160. }
  161. soc->fst_cmem_size = DP_CMEM_FST_SIZE;
  162. soc->fst_cmem_base = soc->cmem_base +
  163. (soc->cmem_total_size - soc->cmem_avail_size);
  164. soc->cmem_avail_size -= soc->fst_cmem_size;
  165. dp_info("fst_cmem_base 0x%llx, fst_cmem_size 0x%llx",
  166. soc->fst_cmem_base, soc->fst_cmem_size);
  167. return QDF_STATUS_SUCCESS;
  168. }
  169. #else /* !WLAN_SUPPORT_RX_FISA */
  170. static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
  171. {
  172. return QDF_STATUS_SUCCESS;
  173. }
  174. #endif
  175. /**
  176. * dp_cc_reg_cfg_init() - initialize and configure HW cookie
  177. * conversion register
  178. *
  179. * @soc: SOC handle
  180. * @is_4k_align: page address 4k aligned
  181. *
  182. * Return: None
  183. */
  184. static void dp_cc_reg_cfg_init(struct dp_soc *soc,
  185. bool is_4k_align)
  186. {
  187. struct hal_hw_cc_config cc_cfg = { 0 };
  188. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  189. if (soc->cdp_soc.ol_ops->get_con_mode &&
  190. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  191. return;
  192. if (!soc->wlan_cfg_ctx->hw_cc_enabled) {
  193. dp_info("INI skip HW CC register setting");
  194. return;
  195. }
  196. cc_cfg.lut_base_addr_31_0 = be_soc->cc_cmem_base;
  197. cc_cfg.cc_global_en = true;
  198. cc_cfg.page_4k_align = is_4k_align;
  199. cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB;
  200. cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB;
  201. /* 36th bit should be 1 then HW know this is CMEM address */
  202. cc_cfg.lut_base_addr_39_32 = 0x10;
  203. cc_cfg.error_path_cookie_conv_en = true;
  204. cc_cfg.release_path_cookie_conv_en = true;
  205. dp_cc_wbm_sw_en_cfg(&cc_cfg);
  206. hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg);
  207. }
  208. /**
  209. * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing
  210. * @hal_soc_hdl: HAL SOC handle
  211. * @offset: CMEM address
  212. * @value: value to write
  213. *
  214. * Return: None.
  215. */
  216. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  217. uint32_t offset,
  218. uint32_t value)
  219. {
  220. hal_cmem_write(hal_soc_hdl, offset, value);
  221. }
  222. /**
  223. * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for
  224. * HW cookie conversion
  225. *
  226. * @soc: SOC handle
  227. *
  228. * Return: 0 in case of success, else error value
  229. */
  230. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  231. {
  232. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  233. dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
  234. soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
  235. /* get CMEM for cookie conversion */
  236. if (soc->cmem_avail_size < DP_CC_PPT_MEM_SIZE) {
  237. dp_err("cmem_size 0x%llx bytes < 4K", soc->cmem_avail_size);
  238. return QDF_STATUS_E_RESOURCES;
  239. }
  240. be_soc->cc_cmem_base = (uint32_t)(soc->cmem_base +
  241. DP_CC_MEM_OFFSET_IN_CMEM);
  242. soc->cmem_avail_size -= DP_CC_PPT_MEM_SIZE;
  243. dp_info("cc_cmem_base 0x%x, cmem_avail_size 0x%llx",
  244. be_soc->cc_cmem_base, soc->cmem_avail_size);
  245. return QDF_STATUS_SUCCESS;
  246. }
  247. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  248. uint8_t for_feature)
  249. {
  250. QDF_STATUS status = QDF_STATUS_E_NOMEM;
  251. switch (for_feature) {
  252. case COOKIE_CONVERSION:
  253. status = dp_hw_cc_cmem_addr_init(soc);
  254. break;
  255. case FISA_FST:
  256. status = dp_fisa_fst_cmem_addr_init(soc);
  257. break;
  258. default:
  259. dp_err("Invalid CMEM request");
  260. }
  261. return status;
  262. }
  263. #else
  264. static inline void dp_cc_reg_cfg_init(struct dp_soc *soc,
  265. bool is_4k_align) {}
  266. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  267. uint32_t offset,
  268. uint32_t value)
  269. { }
  270. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  271. {
  272. return QDF_STATUS_SUCCESS;
  273. }
  274. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  275. uint8_t for_feature)
  276. {
  277. return QDF_STATUS_SUCCESS;
  278. }
  279. #endif
  280. QDF_STATUS
  281. dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc,
  282. struct dp_hw_cookie_conversion_t *cc_ctx,
  283. uint32_t num_descs,
  284. enum dp_desc_type desc_type,
  285. uint8_t desc_pool_id)
  286. {
  287. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  288. uint32_t num_spt_pages, i = 0;
  289. struct dp_spt_page_desc *spt_desc;
  290. struct qdf_mem_dma_page_t *dma_page;
  291. uint8_t chip_id;
  292. /* estimate how many SPT DDR pages needed */
  293. num_spt_pages = num_descs / DP_CC_SPT_PAGE_MAX_ENTRIES;
  294. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  295. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  296. dp_info("num_spt_pages needed %d", num_spt_pages);
  297. dp_desc_multi_pages_mem_alloc(soc, DP_HW_CC_SPT_PAGE_TYPE,
  298. &cc_ctx->page_pool, qdf_page_size,
  299. num_spt_pages, 0, false);
  300. if (!cc_ctx->page_pool.dma_pages) {
  301. dp_err("spt ddr pages allocation failed");
  302. return QDF_STATUS_E_RESOURCES;
  303. }
  304. cc_ctx->page_desc_base = qdf_mem_malloc(
  305. num_spt_pages * sizeof(struct dp_spt_page_desc));
  306. if (!cc_ctx->page_desc_base) {
  307. dp_err("spt page descs allocation failed");
  308. goto fail_0;
  309. }
  310. chip_id = dp_mlo_get_chip_id(soc);
  311. cc_ctx->cmem_offset = dp_desc_pool_get_cmem_base(chip_id, desc_pool_id,
  312. desc_type);
  313. /* initial page desc */
  314. spt_desc = cc_ctx->page_desc_base;
  315. dma_page = cc_ctx->page_pool.dma_pages;
  316. while (i < num_spt_pages) {
  317. /* check if page address 4K aligned */
  318. if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) {
  319. dp_err("non-4k aligned pages addr %pK",
  320. (void *)dma_page[i].page_p_addr);
  321. goto fail_1;
  322. }
  323. spt_desc[i].page_v_addr =
  324. dma_page[i].page_v_addr_start;
  325. spt_desc[i].page_p_addr =
  326. dma_page[i].page_p_addr;
  327. i++;
  328. }
  329. cc_ctx->total_page_num = num_spt_pages;
  330. qdf_spinlock_create(&cc_ctx->cc_lock);
  331. return QDF_STATUS_SUCCESS;
  332. fail_1:
  333. qdf_mem_free(cc_ctx->page_desc_base);
  334. fail_0:
  335. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  336. &cc_ctx->page_pool, 0, false);
  337. return QDF_STATUS_E_FAILURE;
  338. }
  339. QDF_STATUS
  340. dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc,
  341. struct dp_hw_cookie_conversion_t *cc_ctx)
  342. {
  343. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  344. qdf_mem_free(cc_ctx->page_desc_base);
  345. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  346. &cc_ctx->page_pool, 0, false);
  347. qdf_spinlock_destroy(&cc_ctx->cc_lock);
  348. return QDF_STATUS_SUCCESS;
  349. }
  350. QDF_STATUS
  351. dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc,
  352. struct dp_hw_cookie_conversion_t *cc_ctx)
  353. {
  354. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  355. uint32_t i = 0;
  356. struct dp_spt_page_desc *spt_desc;
  357. uint32_t ppt_index;
  358. uint32_t ppt_id_start;
  359. if (!cc_ctx->total_page_num) {
  360. dp_err("total page num is 0");
  361. return QDF_STATUS_E_INVAL;
  362. }
  363. ppt_id_start = DP_CMEM_OFFSET_TO_PPT_ID(cc_ctx->cmem_offset);
  364. spt_desc = cc_ctx->page_desc_base;
  365. while (i < cc_ctx->total_page_num) {
  366. /* write page PA to CMEM */
  367. dp_hw_cc_cmem_write(soc->hal_soc,
  368. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  369. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  370. (spt_desc[i].page_p_addr >>
  371. DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED));
  372. ppt_index = ppt_id_start + i;
  373. if (ppt_index >= DP_CC_PPT_MAX_ENTRIES)
  374. qdf_assert_always(0);
  375. spt_desc[i].ppt_index = ppt_index;
  376. be_soc->page_desc_base[ppt_index].page_v_addr =
  377. spt_desc[i].page_v_addr;
  378. i++;
  379. }
  380. return QDF_STATUS_SUCCESS;
  381. }
  382. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  383. QDF_STATUS
  384. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  385. struct dp_hw_cookie_conversion_t *cc_ctx)
  386. {
  387. uint32_t ppt_index;
  388. struct dp_spt_page_desc *spt_desc;
  389. int i = 0;
  390. spt_desc = cc_ctx->page_desc_base;
  391. while (i < cc_ctx->total_page_num) {
  392. ppt_index = spt_desc[i].ppt_index;
  393. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  394. i++;
  395. }
  396. return QDF_STATUS_SUCCESS;
  397. }
  398. #else
  399. QDF_STATUS
  400. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  401. struct dp_hw_cookie_conversion_t *cc_ctx)
  402. {
  403. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  404. uint32_t ppt_index;
  405. struct dp_spt_page_desc *spt_desc;
  406. int i = 0;
  407. spt_desc = cc_ctx->page_desc_base;
  408. while (i < cc_ctx->total_page_num) {
  409. /* reset PA in CMEM to NULL */
  410. dp_hw_cc_cmem_write(soc->hal_soc,
  411. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  412. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  413. 0);
  414. ppt_index = spt_desc[i].ppt_index;
  415. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  416. i++;
  417. }
  418. return QDF_STATUS_SUCCESS;
  419. }
  420. #endif
  421. #ifdef WLAN_SUPPORT_PPEDS
  422. static QDF_STATUS dp_soc_ppeds_attach_be(struct dp_soc *soc)
  423. {
  424. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  425. struct cdp_ops *cdp_ops = soc->cdp_soc.ops;
  426. /*
  427. * Check if PPE DS is enabled.
  428. */
  429. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc->wlan_cfg_ctx))
  430. return QDF_STATUS_SUCCESS;
  431. if (dp_ppeds_attach_soc_be(be_soc) != QDF_STATUS_SUCCESS)
  432. return QDF_STATUS_SUCCESS;
  433. cdp_ops->ppeds_ops = &dp_ops_ppeds_be;
  434. return QDF_STATUS_SUCCESS;
  435. }
  436. static QDF_STATUS dp_soc_ppeds_detach_be(struct dp_soc *soc)
  437. {
  438. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  439. struct cdp_ops *cdp_ops = soc->cdp_soc.ops;
  440. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc->wlan_cfg_ctx))
  441. return QDF_STATUS_E_FAILURE;
  442. dp_ppeds_detach_soc_be(be_soc);
  443. cdp_ops->ppeds_ops = NULL;
  444. return QDF_STATUS_SUCCESS;
  445. }
  446. static QDF_STATUS dp_peer_ppeds_default_route_be(struct dp_soc *soc,
  447. struct dp_peer_be *be_peer,
  448. uint8_t vdev_id,
  449. uint16_t src_info)
  450. {
  451. uint16_t service_code;
  452. uint8_t priority_valid;
  453. uint8_t use_ppe_ds = PEER_ROUTING_USE_PPE;
  454. uint8_t peer_routing_enabled = PEER_ROUTING_ENABLED;
  455. QDF_STATUS status = QDF_STATUS_SUCCESS;
  456. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  457. struct dp_vdev_be *be_vdev;
  458. be_vdev = dp_get_be_vdev_from_dp_vdev(be_peer->peer.vdev);
  459. /*
  460. * Program service code bypass to avoid L2 new mac address
  461. * learning exception when fdb learning is disabled.
  462. */
  463. service_code = PPE_DRV_SC_SPF_BYPASS;
  464. priority_valid = be_peer->priority_valid;
  465. /*
  466. * if FST is enabled then let flow rule take the decision of
  467. * routing the pkt to DS or host
  468. */
  469. if (wlan_cfg_is_rx_flow_tag_enabled(cfg))
  470. use_ppe_ds = 0;
  471. if (soc->cdp_soc.ol_ops->peer_set_ppeds_default_routing) {
  472. status =
  473. soc->cdp_soc.ol_ops->peer_set_ppeds_default_routing
  474. (soc->ctrl_psoc,
  475. be_peer->peer.mac_addr.raw,
  476. service_code, priority_valid,
  477. src_info, vdev_id, use_ppe_ds,
  478. peer_routing_enabled);
  479. if (status != QDF_STATUS_SUCCESS) {
  480. dp_err("vdev_id: %d, PPE peer routing mac:"
  481. QDF_MAC_ADDR_FMT, vdev_id,
  482. QDF_MAC_ADDR_REF(be_peer->peer.mac_addr.raw));
  483. return QDF_STATUS_E_FAILURE;
  484. }
  485. }
  486. return QDF_STATUS_SUCCESS;
  487. }
  488. #ifdef WLAN_FEATURE_11BE_MLO
  489. QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc,
  490. struct dp_peer *peer,
  491. struct dp_vdev_be *be_vdev,
  492. void *args)
  493. {
  494. struct dp_peer *mld_peer;
  495. struct dp_soc *mld_soc;
  496. struct dp_soc_be *be_soc;
  497. struct cdp_soc_t *cdp_soc;
  498. struct dp_peer_be *be_peer = dp_get_be_peer_from_dp_peer(peer);
  499. struct cdp_ds_vp_params vp_params = {0};
  500. struct dp_ppe_vp_profile *ppe_vp_profile = (struct dp_ppe_vp_profile *)args;
  501. uint16_t src_info = ppe_vp_profile->vp_num;
  502. uint8_t vdev_id = be_vdev->vdev.vdev_id;
  503. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  504. if (!be_peer) {
  505. dp_err("BE peer is null");
  506. return QDF_STATUS_E_NULL_VALUE;
  507. }
  508. if (IS_DP_LEGACY_PEER(peer)) {
  509. qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer,
  510. vdev_id, src_info);
  511. } else if (IS_MLO_DP_MLD_PEER(peer)) {
  512. int i;
  513. struct dp_peer *link_peer = NULL;
  514. struct dp_mld_link_peers link_peers_info;
  515. /* get link peers with reference */
  516. dp_get_link_peers_ref_from_mld_peer(soc, peer, &link_peers_info,
  517. DP_MOD_ID_DS);
  518. for (i = 0; i < link_peers_info.num_links; i++) {
  519. link_peer = link_peers_info.link_peers[i];
  520. be_peer = dp_get_be_peer_from_dp_peer(link_peer);
  521. if (!be_peer) {
  522. dp_err("BE peer is null");
  523. continue;
  524. }
  525. be_vdev = dp_get_be_vdev_from_dp_vdev(link_peer->vdev);
  526. if (!be_vdev) {
  527. dp_err("BE vap is null for peer id %d ",
  528. link_peer->peer_id);
  529. continue;
  530. }
  531. vdev_id = be_vdev->vdev.vdev_id;
  532. qdf_status = dp_peer_ppeds_default_route_be(soc,
  533. be_peer,
  534. vdev_id,
  535. src_info);
  536. }
  537. dp_release_link_peers_ref(&link_peers_info, DP_MOD_ID_DS);
  538. } else {
  539. mld_peer = DP_GET_MLD_PEER_FROM_PEER(peer);
  540. if (!mld_peer)
  541. return qdf_status;
  542. /*
  543. * In case of MLO link peer,
  544. * 1. WDS EXT case : use the VP profile created for the
  545. * wds_ext netdev which is passed as an argument.
  546. * 2. Non WDS EXT case : Fetch the VP profile from the mld vdev.
  547. */
  548. if (!dp_peer_check_wds_ext_peer(mld_peer)) {
  549. be_vdev = dp_get_be_vdev_from_dp_vdev(mld_peer->vdev);
  550. if (!be_vdev) {
  551. dp_err("BE vap is null");
  552. return QDF_STATUS_E_NULL_VALUE;
  553. }
  554. /*
  555. * Extract the VP profile from the vap
  556. * in case of MLO peer, we have to get the profile form
  557. * the MLD vdev's osif handle and not the link peer.
  558. */
  559. mld_soc = mld_peer->vdev->pdev->soc;
  560. cdp_soc = &mld_soc->cdp_soc;
  561. if (!cdp_soc->ol_ops->get_ppeds_profile_info_for_vap) {
  562. qdf_err("%pK: Register PPEDS profile info API before use\n", cdp_soc);
  563. return QDF_STATUS_E_NULL_VALUE;
  564. }
  565. qdf_status = cdp_soc->ol_ops->get_ppeds_profile_info_for_vap(mld_soc->ctrl_psoc,
  566. mld_peer->vdev->vdev_id,
  567. &vp_params);
  568. if (qdf_status == QDF_STATUS_E_NULL_VALUE) {
  569. qdf_err("%pK: Failed to get ppeds profile for mld soc\n", mld_soc);
  570. return qdf_status;
  571. }
  572. /*
  573. * Check if PPE DS routing is enabled on
  574. * the associated vap.
  575. */
  576. if (vp_params.ppe_vp_type != PPE_VP_USER_TYPE_DS)
  577. return qdf_status;
  578. be_soc = dp_get_be_soc_from_dp_soc(mld_soc);
  579. ppe_vp_profile = &be_soc->ppe_vp_profile[vp_params.ppe_vp_profile_idx];
  580. src_info = ppe_vp_profile->vp_num;
  581. }
  582. qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer,
  583. vdev_id, src_info);
  584. }
  585. return qdf_status;
  586. }
  587. #else
  588. static QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc,
  589. struct dp_peer *peer,
  590. struct dp_vdev_be *be_vdev
  591. void *args)
  592. {
  593. struct dp_ppe_vp_profile *vp_profile = (struct dp_ppe_vp_profile *)args;
  594. struct dp_peer_be *be_peer = dp_get_be_peer_from_dp_peer(peer);
  595. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  596. if (!be_peer) {
  597. dp_err("BE peer is null");
  598. return QDF_STATUS_E_NULL_VALUE;
  599. }
  600. qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer,
  601. be_vdev->vdev.vdev_id,
  602. vp_profile->vp_num);
  603. return qdf_status;
  604. }
  605. #endif
  606. #else
  607. static QDF_STATUS dp_ppeds_init_soc_be(struct dp_soc *soc)
  608. {
  609. return QDF_STATUS_SUCCESS;
  610. }
  611. static QDF_STATUS dp_ppeds_deinit_soc_be(struct dp_soc *soc)
  612. {
  613. return QDF_STATUS_SUCCESS;
  614. }
  615. static inline QDF_STATUS dp_soc_ppeds_attach_be(struct dp_soc *soc)
  616. {
  617. return QDF_STATUS_SUCCESS;
  618. }
  619. static inline QDF_STATUS dp_soc_ppeds_detach_be(struct dp_soc *soc)
  620. {
  621. return QDF_STATUS_SUCCESS;
  622. }
  623. QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc, struct dp_peer *peer,
  624. struct dp_vdev_be *be_vdev,
  625. void *args)
  626. {
  627. return QDF_STATUS_SUCCESS;
  628. }
  629. #endif /* WLAN_SUPPORT_PPEDS */
  630. void dp_reo_shared_qaddr_detach(struct dp_soc *soc)
  631. {
  632. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  633. REO_QUEUE_REF_ML_TABLE_SIZE,
  634. soc->reo_qref.mlo_reo_qref_table_vaddr,
  635. soc->reo_qref.mlo_reo_qref_table_paddr, 0);
  636. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  637. REO_QUEUE_REF_NON_ML_TABLE_SIZE,
  638. soc->reo_qref.non_mlo_reo_qref_table_vaddr,
  639. soc->reo_qref.non_mlo_reo_qref_table_paddr, 0);
  640. }
  641. static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc)
  642. {
  643. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  644. int i = 0;
  645. dp_soc_ppeds_detach_be(soc);
  646. dp_reo_shared_qaddr_detach(soc);
  647. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  648. dp_hw_cookie_conversion_detach(be_soc,
  649. &be_soc->tx_cc_ctx[i]);
  650. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  651. dp_hw_cookie_conversion_detach(be_soc,
  652. &be_soc->rx_cc_ctx[i]);
  653. qdf_mem_free(be_soc->page_desc_base);
  654. be_soc->page_desc_base = NULL;
  655. return QDF_STATUS_SUCCESS;
  656. }
  657. #ifdef QCA_SUPPORT_DP_GLOBAL_CTX
  658. static void dp_set_rx_fst_be(struct dp_rx_fst *fst)
  659. {
  660. struct dp_global_context *dp_global = wlan_objmgr_get_global_ctx();
  661. if (dp_global)
  662. dp_global->fst_ctx = fst;
  663. }
  664. static struct dp_rx_fst *dp_get_rx_fst_be(void)
  665. {
  666. struct dp_global_context *dp_global = wlan_objmgr_get_global_ctx();
  667. if (dp_global)
  668. return dp_global->fst_ctx;
  669. return NULL;
  670. }
  671. static uint32_t dp_rx_fst_release_ref_be(void)
  672. {
  673. struct dp_global_context *dp_global = wlan_objmgr_get_global_ctx();
  674. uint32_t rx_fst_ref_cnt;
  675. if (dp_global) {
  676. rx_fst_ref_cnt = qdf_atomic_read(&dp_global->rx_fst_ref_cnt);
  677. qdf_atomic_dec(&dp_global->rx_fst_ref_cnt);
  678. return rx_fst_ref_cnt;
  679. }
  680. return 1;
  681. }
  682. static void dp_rx_fst_get_ref_be(void)
  683. {
  684. struct dp_global_context *dp_global = wlan_objmgr_get_global_ctx();
  685. if (dp_global)
  686. qdf_atomic_inc(&dp_global->rx_fst_ref_cnt);
  687. }
  688. #else
  689. static void dp_set_rx_fst_be(struct dp_rx_fst *fst)
  690. {
  691. }
  692. static struct dp_rx_fst *dp_get_rx_fst_be(void)
  693. {
  694. return NULL;
  695. }
  696. static uint32_t dp_rx_fst_release_ref_be(void)
  697. {
  698. return 1;
  699. }
  700. static void dp_rx_fst_get_ref_be(void)
  701. {
  702. }
  703. #endif
  704. #ifdef WLAN_MLO_MULTI_CHIP
  705. #ifdef WLAN_MCAST_MLO
  706. static inline void
  707. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  708. {
  709. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  710. be_vdev->mcast_primary = false;
  711. be_vdev->seq_num = 0;
  712. hal_tx_mcast_mlo_reinject_routing_set(
  713. soc->hal_soc,
  714. HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY);
  715. if (vdev->opmode == wlan_op_mode_ap) {
  716. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  717. vdev->vdev_id,
  718. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  719. }
  720. }
  721. static inline void
  722. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  723. {
  724. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  725. be_vdev->seq_num = 0;
  726. be_vdev->mcast_primary = false;
  727. vdev->mlo_vdev = false;
  728. }
  729. #else
  730. static inline void
  731. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  732. {
  733. }
  734. static inline void
  735. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  736. {
  737. }
  738. #endif
  739. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  740. {
  741. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  742. qdf_mem_set(be_vdev->partner_vdev_list,
  743. WLAN_MAX_MLO_CHIPS * WLAN_MAX_MLO_LINKS_PER_SOC,
  744. CDP_INVALID_VDEV_ID);
  745. }
  746. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  747. struct cdp_lro_hash_config *lro_hash)
  748. {
  749. dp_mlo_get_rx_hash_key(soc, lro_hash);
  750. }
  751. #else
  752. static inline void
  753. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  754. {
  755. }
  756. static inline void
  757. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  758. {
  759. }
  760. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  761. {
  762. }
  763. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  764. struct cdp_lro_hash_config *lro_hash)
  765. {
  766. dp_get_rx_hash_key_bytes(lro_hash);
  767. }
  768. #endif
  769. static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc,
  770. struct cdp_soc_attach_params *params)
  771. {
  772. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  773. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  774. uint32_t max_tx_rx_desc_num, num_spt_pages;
  775. uint32_t num_entries;
  776. int i = 0;
  777. max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS +
  778. WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS +
  779. WLAN_CFG_NUM_PPEDS_TX_DESC_MAX * MAX_PPE_TXDESC_POOLS;
  780. /* estimate how many SPT DDR pages needed */
  781. num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES;
  782. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  783. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  784. be_soc->page_desc_base = qdf_mem_malloc(
  785. DP_CC_PPT_MAX_ENTRIES * sizeof(struct dp_spt_page_desc));
  786. if (!be_soc->page_desc_base) {
  787. dp_err("spt page descs allocation failed");
  788. return QDF_STATUS_E_NOMEM;
  789. }
  790. soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id();
  791. qdf_status = dp_get_cmem_allocation(soc, COOKIE_CONVERSION);
  792. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  793. goto fail;
  794. dp_soc_mlo_fill_params(soc, params);
  795. qdf_status = dp_soc_ppeds_attach_be(soc);
  796. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  797. goto fail;
  798. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  799. num_entries = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  800. qdf_status =
  801. dp_hw_cookie_conversion_attach(be_soc,
  802. &be_soc->tx_cc_ctx[i],
  803. num_entries,
  804. DP_TX_DESC_TYPE, i);
  805. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  806. goto fail;
  807. }
  808. qdf_status = dp_get_cmem_allocation(soc, FISA_FST);
  809. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  810. goto fail;
  811. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  812. num_entries =
  813. wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx);
  814. qdf_status =
  815. dp_hw_cookie_conversion_attach(be_soc,
  816. &be_soc->rx_cc_ctx[i],
  817. num_entries,
  818. DP_RX_DESC_BUF_TYPE, i);
  819. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  820. goto fail;
  821. }
  822. return qdf_status;
  823. fail:
  824. dp_soc_detach_be(soc);
  825. return qdf_status;
  826. }
  827. static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc)
  828. {
  829. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  830. int i = 0;
  831. dp_tx_deinit_bank_profiles(be_soc);
  832. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  833. dp_hw_cookie_conversion_deinit(be_soc,
  834. &be_soc->tx_cc_ctx[i]);
  835. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  836. dp_hw_cookie_conversion_deinit(be_soc,
  837. &be_soc->rx_cc_ctx[i]);
  838. dp_ppeds_deinit_soc_be(soc);
  839. return QDF_STATUS_SUCCESS;
  840. }
  841. static QDF_STATUS dp_soc_init_be(struct dp_soc *soc)
  842. {
  843. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  844. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  845. int i = 0;
  846. dp_ppeds_init_soc_be(soc);
  847. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  848. qdf_status =
  849. dp_hw_cookie_conversion_init(be_soc,
  850. &be_soc->tx_cc_ctx[i]);
  851. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  852. goto fail;
  853. }
  854. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  855. qdf_status =
  856. dp_hw_cookie_conversion_init(be_soc,
  857. &be_soc->rx_cc_ctx[i]);
  858. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  859. goto fail;
  860. }
  861. /* route vdev_id mismatch notification via FW completion */
  862. hal_tx_vdev_mismatch_routing_set(soc->hal_soc,
  863. HAL_TX_VDEV_MISMATCH_FW_NOTIFY);
  864. qdf_status = dp_tx_init_bank_profiles(be_soc);
  865. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  866. goto fail;
  867. /* write WBM/REO cookie conversion CFG register */
  868. dp_cc_reg_cfg_init(soc, true);
  869. return qdf_status;
  870. fail:
  871. dp_soc_deinit_be(soc);
  872. return qdf_status;
  873. }
  874. static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev,
  875. struct cdp_pdev_attach_params *params)
  876. {
  877. dp_pdev_mlo_fill_params(pdev, params);
  878. return QDF_STATUS_SUCCESS;
  879. }
  880. static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev)
  881. {
  882. dp_mlo_update_link_to_pdev_unmap(pdev->soc, pdev);
  883. return QDF_STATUS_SUCCESS;
  884. }
  885. #ifdef INTRA_BSS_FWD_OFFLOAD
  886. static
  887. void dp_vdev_set_intra_bss(struct dp_soc *soc, uint16_t vdev_id, bool enable)
  888. {
  889. soc->cdp_soc.ol_ops->vdev_set_intra_bss(soc->ctrl_psoc, vdev_id,
  890. enable);
  891. }
  892. #else
  893. static
  894. void dp_vdev_set_intra_bss(struct dp_soc *soc, uint16_t vdev_id, bool enable)
  895. {
  896. }
  897. #endif
  898. static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  899. {
  900. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  901. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  902. struct dp_pdev *pdev = vdev->pdev;
  903. if (vdev->opmode == wlan_op_mode_monitor)
  904. return QDF_STATUS_SUCCESS;
  905. be_vdev->vdev_id_check_en = DP_TX_VDEV_ID_CHECK_ENABLE;
  906. be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
  907. vdev->bank_id = be_vdev->bank_id;
  908. if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) {
  909. QDF_BUG(0);
  910. return QDF_STATUS_E_FAULT;
  911. }
  912. if (vdev->opmode == wlan_op_mode_sta) {
  913. if (soc->cdp_soc.ol_ops->set_mec_timer)
  914. soc->cdp_soc.ol_ops->set_mec_timer(
  915. soc->ctrl_psoc,
  916. vdev->vdev_id,
  917. DP_AST_AGING_TIMER_DEFAULT_MS);
  918. if (pdev->isolation)
  919. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  920. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  921. else
  922. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  923. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  924. } else if (vdev->ap_bridge_enabled) {
  925. dp_vdev_set_intra_bss(soc, vdev->vdev_id, true);
  926. }
  927. dp_mlo_mcast_init(soc, vdev);
  928. dp_mlo_init_ptnr_list(vdev);
  929. return QDF_STATUS_SUCCESS;
  930. }
  931. static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  932. {
  933. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  934. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  935. if (vdev->opmode == wlan_op_mode_monitor)
  936. return QDF_STATUS_SUCCESS;
  937. if (vdev->opmode == wlan_op_mode_ap)
  938. dp_mlo_mcast_deinit(soc, vdev);
  939. dp_tx_put_bank_profile(be_soc, be_vdev);
  940. dp_clr_mlo_ptnr_list(soc, vdev);
  941. return QDF_STATUS_SUCCESS;
  942. }
  943. #ifdef WLAN_SUPPORT_PPEDS
  944. static QDF_STATUS dp_peer_setup_be(struct dp_soc *soc, struct dp_peer *peer)
  945. {
  946. struct dp_vdev_be *be_vdev;
  947. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  948. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  949. struct cdp_ds_vp_params vp_params = {0};
  950. struct cdp_soc_t *cdp_soc = &soc->cdp_soc;
  951. be_vdev = dp_get_be_vdev_from_dp_vdev(peer->vdev);
  952. if (!be_vdev) {
  953. qdf_err("BE vap is null");
  954. return QDF_STATUS_E_NULL_VALUE;
  955. }
  956. /*
  957. * Extract the VP profile from the VAP
  958. */
  959. if (!cdp_soc->ol_ops->get_ppeds_profile_info_for_vap) {
  960. dp_err("%pK: Register get ppeds profile info first\n", cdp_soc);
  961. return QDF_STATUS_E_NULL_VALUE;
  962. }
  963. /*
  964. * Check if PPE DS routing is enabled on the associated vap.
  965. */
  966. qdf_status = cdp_soc->ol_ops->get_ppeds_profile_info_for_vap(soc->ctrl_psoc,
  967. peer->vdev->vdev_id,
  968. &vp_params);
  969. if (qdf_status == QDF_STATUS_E_NULL_VALUE) {
  970. dp_err("%pK: Could not find ppeds profile info vdev\n", be_vdev);
  971. return QDF_STATUS_E_NULL_VALUE;
  972. }
  973. if (vp_params.ppe_vp_type == PPE_VP_USER_TYPE_DS) {
  974. qdf_status = dp_peer_setup_ppeds_be(soc, peer, be_vdev,
  975. (void *)&be_soc->ppe_vp_profile[vp_params.ppe_vp_profile_idx]);
  976. }
  977. return qdf_status;
  978. }
  979. #else
  980. static QDF_STATUS dp_peer_setup_be(struct dp_soc *soc, struct dp_peer *peer)
  981. {
  982. return QDF_STATUS_SUCCESS;
  983. }
  984. #endif
  985. qdf_size_t dp_get_soc_context_size_be(void)
  986. {
  987. return sizeof(struct dp_soc_be);
  988. }
  989. #ifdef CONFIG_WORD_BASED_TLV
  990. /**
  991. * dp_rxdma_ring_wmask_cfg_be() - Setup RXDMA ring word mask config
  992. * @soc: Common DP soc handle
  993. * @htt_tlv_filter: Rx SRNG TLV and filter setting
  994. *
  995. * Return: none
  996. */
  997. static inline void
  998. dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
  999. struct htt_rx_ring_tlv_filter *htt_tlv_filter)
  1000. {
  1001. htt_tlv_filter->rx_msdu_end_wmask =
  1002. hal_rx_msdu_end_wmask_get(soc->hal_soc);
  1003. htt_tlv_filter->rx_mpdu_start_wmask =
  1004. hal_rx_mpdu_start_wmask_get(soc->hal_soc);
  1005. }
  1006. #else
  1007. static inline void
  1008. dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
  1009. struct htt_rx_ring_tlv_filter *htt_tlv_filter)
  1010. {
  1011. }
  1012. #endif
  1013. #ifdef WLAN_SUPPORT_PPEDS
  1014. static
  1015. void dp_free_ppeds_interrupts(struct dp_soc *soc, struct dp_srng *srng,
  1016. int ring_type, int ring_num)
  1017. {
  1018. if (srng->irq >= 0) {
  1019. if (ring_type == WBM2SW_RELEASE &&
  1020. ring_num == WBM2_SW_PPE_REL_RING_ID)
  1021. pld_pfrm_free_irq(soc->osdev->dev, srng->irq, soc);
  1022. else if (ring_type == REO2PPE || ring_type == PPE2TCL)
  1023. pld_pfrm_free_irq(soc->osdev->dev, srng->irq,
  1024. dp_get_ppe_ds_ctxt(soc));
  1025. }
  1026. }
  1027. static
  1028. int dp_register_ppeds_interrupts(struct dp_soc *soc, struct dp_srng *srng,
  1029. int vector, int ring_type, int ring_num)
  1030. {
  1031. int irq = -1, ret = 0;
  1032. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1033. int pci_slot = pld_get_pci_slot(soc->osdev->dev);
  1034. srng->irq = -1;
  1035. irq = pld_get_msi_irq(soc->osdev->dev, vector);
  1036. if (ring_type == WBM2SW_RELEASE &&
  1037. ring_num == WBM2_SW_PPE_REL_RING_ID) {
  1038. snprintf(be_soc->irq_name[2], DP_PPE_INTR_STRNG_LEN,
  1039. "pci%d_ppe_wbm_rel", pci_slot);
  1040. ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
  1041. dp_ppeds_handle_tx_comp,
  1042. IRQF_SHARED | IRQF_NO_SUSPEND,
  1043. be_soc->irq_name[2], (void *)soc);
  1044. if (ret)
  1045. goto fail;
  1046. } else if (ring_type == REO2PPE && be_soc->ppeds_int_mode_enabled) {
  1047. snprintf(be_soc->irq_name[0], DP_PPE_INTR_STRNG_LEN,
  1048. "pci%d_reo2ppe", pci_slot);
  1049. ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
  1050. dp_ppe_ds_reo2ppe_irq_handler,
  1051. IRQF_SHARED | IRQF_NO_SUSPEND,
  1052. be_soc->irq_name[0],
  1053. dp_get_ppe_ds_ctxt(soc));
  1054. if (ret)
  1055. goto fail;
  1056. } else if (ring_type == PPE2TCL && be_soc->ppeds_int_mode_enabled) {
  1057. snprintf(be_soc->irq_name[1], DP_PPE_INTR_STRNG_LEN,
  1058. "pci%d_ppe2tcl", pci_slot);
  1059. ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
  1060. dp_ppe_ds_ppe2tcl_irq_handler,
  1061. IRQF_SHARED | IRQF_NO_SUSPEND,
  1062. be_soc->irq_name[1],
  1063. dp_get_ppe_ds_ctxt(soc));
  1064. if (ret)
  1065. goto fail;
  1066. pld_pfrm_disable_irq_nosync(soc->osdev->dev, irq);
  1067. } else {
  1068. return 0;
  1069. }
  1070. srng->irq = irq;
  1071. dp_info("Registered irq %d for soc %pK ring type %d",
  1072. irq, soc, ring_type);
  1073. return 0;
  1074. fail:
  1075. dp_err("Unable to config irq : ring type %d irq %d vector %d",
  1076. ring_type, irq, vector);
  1077. return ret;
  1078. }
  1079. void dp_ppeds_disable_irq(struct dp_soc *soc, struct dp_srng *srng)
  1080. {
  1081. if (srng->irq >= 0)
  1082. pld_pfrm_disable_irq_nosync(soc->osdev->dev, srng->irq);
  1083. }
  1084. void dp_ppeds_enable_irq(struct dp_soc *soc, struct dp_srng *srng)
  1085. {
  1086. if (srng->irq >= 0)
  1087. pld_pfrm_enable_irq(soc->osdev->dev, srng->irq);
  1088. }
  1089. #endif
  1090. #ifdef NO_RX_PKT_HDR_TLV
  1091. /**
  1092. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  1093. * @soc: Common DP soc handle
  1094. *
  1095. * Return: QDF_STATUS
  1096. */
  1097. static QDF_STATUS
  1098. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  1099. {
  1100. int i;
  1101. int mac_id;
  1102. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  1103. struct dp_srng *rx_mac_srng;
  1104. QDF_STATUS status = QDF_STATUS_SUCCESS;
  1105. /*
  1106. * In Beryllium chipset msdu_start, mpdu_end
  1107. * and rx_attn are part of msdu_end/mpdu_start
  1108. */
  1109. htt_tlv_filter.msdu_start = 0;
  1110. htt_tlv_filter.mpdu_end = 0;
  1111. htt_tlv_filter.attention = 0;
  1112. htt_tlv_filter.mpdu_start = 1;
  1113. htt_tlv_filter.msdu_end = 1;
  1114. htt_tlv_filter.packet = 1;
  1115. htt_tlv_filter.packet_header = 0;
  1116. htt_tlv_filter.ppdu_start = 0;
  1117. htt_tlv_filter.ppdu_end = 0;
  1118. htt_tlv_filter.ppdu_end_user_stats = 0;
  1119. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  1120. htt_tlv_filter.ppdu_end_status_done = 0;
  1121. htt_tlv_filter.enable_fp = 1;
  1122. htt_tlv_filter.enable_md = 0;
  1123. htt_tlv_filter.enable_md = 0;
  1124. htt_tlv_filter.enable_mo = 0;
  1125. htt_tlv_filter.fp_mgmt_filter = 0;
  1126. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  1127. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  1128. FILTER_DATA_MCAST |
  1129. FILTER_DATA_DATA);
  1130. htt_tlv_filter.mo_mgmt_filter = 0;
  1131. htt_tlv_filter.mo_ctrl_filter = 0;
  1132. htt_tlv_filter.mo_data_filter = 0;
  1133. htt_tlv_filter.md_data_filter = 0;
  1134. htt_tlv_filter.offset_valid = true;
  1135. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  1136. htt_tlv_filter.rx_mpdu_end_offset = 0;
  1137. htt_tlv_filter.rx_msdu_start_offset = 0;
  1138. htt_tlv_filter.rx_attn_offset = 0;
  1139. /*
  1140. * For monitor mode, the packet hdr tlv is enabled later during
  1141. * filter update
  1142. */
  1143. if (soc->cdp_soc.ol_ops->get_con_mode &&
  1144. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
  1145. htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
  1146. else
  1147. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  1148. /*Not subscribing rx_pkt_header*/
  1149. htt_tlv_filter.rx_header_offset = 0;
  1150. htt_tlv_filter.rx_mpdu_start_offset =
  1151. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  1152. htt_tlv_filter.rx_msdu_end_offset =
  1153. hal_rx_msdu_end_offset_get(soc->hal_soc);
  1154. dp_rxdma_ring_wmask_cfg_be(soc, &htt_tlv_filter);
  1155. for (i = 0; i < MAX_PDEV_CNT; i++) {
  1156. struct dp_pdev *pdev = soc->pdev_list[i];
  1157. if (!pdev)
  1158. continue;
  1159. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  1160. int mac_for_pdev =
  1161. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  1162. /*
  1163. * Obtain lmac id from pdev to access the LMAC ring
  1164. * in soc context
  1165. */
  1166. int lmac_id =
  1167. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  1168. pdev->pdev_id);
  1169. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  1170. if (!rx_mac_srng->hal_srng)
  1171. continue;
  1172. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  1173. rx_mac_srng->hal_srng,
  1174. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  1175. &htt_tlv_filter);
  1176. }
  1177. }
  1178. return status;
  1179. }
  1180. #else
  1181. /**
  1182. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  1183. * @soc: Common DP soc handle
  1184. *
  1185. * Return: QDF_STATUS
  1186. */
  1187. static QDF_STATUS
  1188. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  1189. {
  1190. int i;
  1191. int mac_id;
  1192. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  1193. struct dp_srng *rx_mac_srng;
  1194. QDF_STATUS status = QDF_STATUS_SUCCESS;
  1195. /*
  1196. * In Beryllium chipset msdu_start, mpdu_end
  1197. * and rx_attn are part of msdu_end/mpdu_start
  1198. */
  1199. htt_tlv_filter.msdu_start = 0;
  1200. htt_tlv_filter.mpdu_end = 0;
  1201. htt_tlv_filter.attention = 0;
  1202. htt_tlv_filter.mpdu_start = 1;
  1203. htt_tlv_filter.msdu_end = 1;
  1204. htt_tlv_filter.packet = 1;
  1205. htt_tlv_filter.packet_header = 1;
  1206. htt_tlv_filter.ppdu_start = 0;
  1207. htt_tlv_filter.ppdu_end = 0;
  1208. htt_tlv_filter.ppdu_end_user_stats = 0;
  1209. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  1210. htt_tlv_filter.ppdu_end_status_done = 0;
  1211. htt_tlv_filter.enable_fp = 1;
  1212. htt_tlv_filter.enable_md = 0;
  1213. htt_tlv_filter.enable_md = 0;
  1214. htt_tlv_filter.enable_mo = 0;
  1215. htt_tlv_filter.fp_mgmt_filter = 0;
  1216. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  1217. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  1218. FILTER_DATA_MCAST |
  1219. FILTER_DATA_DATA);
  1220. htt_tlv_filter.mo_mgmt_filter = 0;
  1221. htt_tlv_filter.mo_ctrl_filter = 0;
  1222. htt_tlv_filter.mo_data_filter = 0;
  1223. htt_tlv_filter.md_data_filter = 0;
  1224. htt_tlv_filter.offset_valid = true;
  1225. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  1226. htt_tlv_filter.rx_mpdu_end_offset = 0;
  1227. htt_tlv_filter.rx_msdu_start_offset = 0;
  1228. htt_tlv_filter.rx_attn_offset = 0;
  1229. /*
  1230. * For monitor mode, the packet hdr tlv is enabled later during
  1231. * filter update
  1232. */
  1233. if (soc->cdp_soc.ol_ops->get_con_mode &&
  1234. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
  1235. htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
  1236. else
  1237. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  1238. htt_tlv_filter.rx_header_offset =
  1239. hal_rx_pkt_tlv_offset_get(soc->hal_soc);
  1240. htt_tlv_filter.rx_mpdu_start_offset =
  1241. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  1242. htt_tlv_filter.rx_msdu_end_offset =
  1243. hal_rx_msdu_end_offset_get(soc->hal_soc);
  1244. dp_info("TLV subscription\n"
  1245. "msdu_start %d, mpdu_end %d, attention %d"
  1246. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n"
  1247. "TLV offsets\n"
  1248. "msdu_start %d, mpdu_end %d, attention %d"
  1249. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n",
  1250. htt_tlv_filter.msdu_start,
  1251. htt_tlv_filter.mpdu_end,
  1252. htt_tlv_filter.attention,
  1253. htt_tlv_filter.mpdu_start,
  1254. htt_tlv_filter.msdu_end,
  1255. htt_tlv_filter.packet_header,
  1256. htt_tlv_filter.packet,
  1257. htt_tlv_filter.rx_msdu_start_offset,
  1258. htt_tlv_filter.rx_mpdu_end_offset,
  1259. htt_tlv_filter.rx_attn_offset,
  1260. htt_tlv_filter.rx_mpdu_start_offset,
  1261. htt_tlv_filter.rx_msdu_end_offset,
  1262. htt_tlv_filter.rx_header_offset,
  1263. htt_tlv_filter.rx_packet_offset);
  1264. for (i = 0; i < MAX_PDEV_CNT; i++) {
  1265. struct dp_pdev *pdev = soc->pdev_list[i];
  1266. if (!pdev)
  1267. continue;
  1268. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  1269. int mac_for_pdev =
  1270. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  1271. /*
  1272. * Obtain lmac id from pdev to access the LMAC ring
  1273. * in soc context
  1274. */
  1275. int lmac_id =
  1276. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  1277. pdev->pdev_id);
  1278. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  1279. if (!rx_mac_srng->hal_srng)
  1280. continue;
  1281. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  1282. rx_mac_srng->hal_srng,
  1283. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  1284. &htt_tlv_filter);
  1285. }
  1286. }
  1287. return status;
  1288. }
  1289. #endif
  1290. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1291. /**
  1292. * dp_service_near_full_srngs_be() - Main bottom half callback for the
  1293. * near-full IRQs.
  1294. * @soc: Datapath SoC handle
  1295. * @int_ctx: Interrupt context
  1296. * @dp_budget: Budget of the work that can be done in the bottom half
  1297. *
  1298. * Return: work done in the handler
  1299. */
  1300. static uint32_t
  1301. dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx,
  1302. uint32_t dp_budget)
  1303. {
  1304. int ring = 0;
  1305. int budget = dp_budget;
  1306. uint32_t work_done = 0;
  1307. uint32_t remaining_quota = dp_budget;
  1308. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  1309. int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask;
  1310. int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask;
  1311. int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask;
  1312. int rx_near_full_mask = rx_near_full_grp_1_mask |
  1313. rx_near_full_grp_2_mask;
  1314. dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x",
  1315. rx_near_full_mask,
  1316. tx_ring_near_full_mask);
  1317. if (rx_near_full_mask) {
  1318. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  1319. if (!(rx_near_full_mask & (1 << ring)))
  1320. continue;
  1321. work_done = dp_rx_nf_process(int_ctx,
  1322. soc->reo_dest_ring[ring].hal_srng,
  1323. ring, remaining_quota);
  1324. if (work_done) {
  1325. intr_stats->num_rx_ring_near_full_masks[ring]++;
  1326. dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d",
  1327. rx_near_full_mask, ring,
  1328. work_done,
  1329. budget);
  1330. budget -= work_done;
  1331. if (budget <= 0)
  1332. goto budget_done;
  1333. remaining_quota = budget;
  1334. }
  1335. }
  1336. }
  1337. if (tx_ring_near_full_mask) {
  1338. for (ring = 0; ring < soc->num_tcl_data_rings; ring++) {
  1339. if (!(tx_ring_near_full_mask & (1 << ring)))
  1340. continue;
  1341. work_done = dp_tx_comp_nf_handler(int_ctx, soc,
  1342. soc->tx_comp_ring[ring].hal_srng,
  1343. ring, remaining_quota);
  1344. if (work_done) {
  1345. intr_stats->num_tx_comp_ring_near_full_masks[ring]++;
  1346. dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d",
  1347. tx_ring_near_full_mask, ring,
  1348. work_done, budget);
  1349. budget -= work_done;
  1350. if (budget <= 0)
  1351. break;
  1352. remaining_quota = budget;
  1353. }
  1354. }
  1355. }
  1356. intr_stats->num_near_full_masks++;
  1357. budget_done:
  1358. return dp_budget - budget;
  1359. }
  1360. /**
  1361. * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full
  1362. * state and set the reap_limit appropriately
  1363. * as per the near full state
  1364. * @soc: Datapath soc handle
  1365. * @dp_srng: Datapath handle for SRNG
  1366. * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per
  1367. * the srng near-full state
  1368. *
  1369. * Return: 1, if the srng is in near-full state
  1370. * 0, if the srng is not in near-full state
  1371. */
  1372. static int
  1373. dp_srng_test_and_update_nf_params_be(struct dp_soc *soc,
  1374. struct dp_srng *dp_srng,
  1375. int *max_reap_limit)
  1376. {
  1377. return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit);
  1378. }
  1379. /**
  1380. * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the
  1381. * near full IRQ handling operations.
  1382. * @arch_ops: arch ops handle
  1383. *
  1384. * Return: none
  1385. */
  1386. static inline void
  1387. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  1388. {
  1389. arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be;
  1390. arch_ops->dp_srng_test_and_update_nf_params =
  1391. dp_srng_test_and_update_nf_params_be;
  1392. }
  1393. #else
  1394. static inline void
  1395. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  1396. {
  1397. }
  1398. #endif
  1399. #ifdef WLAN_SUPPORT_PPEDS
  1400. static void dp_soc_ppeds_srng_deinit(struct dp_soc *soc)
  1401. {
  1402. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1403. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1404. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1405. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx))
  1406. return;
  1407. dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0);
  1408. wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  1409. be_soc->ppe2tcl_ring.alloc_size,
  1410. soc->ctrl_psoc,
  1411. WLAN_MD_DP_SRNG_PPE2TCL,
  1412. "ppe2tcl_ring");
  1413. dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0);
  1414. wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  1415. be_soc->reo2ppe_ring.alloc_size,
  1416. soc->ctrl_psoc,
  1417. WLAN_MD_DP_SRNG_REO2PPE,
  1418. "reo2ppe_ring");
  1419. dp_srng_deinit(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
  1420. WBM2_SW_PPE_REL_RING_ID);
  1421. wlan_minidump_remove(be_soc->ppeds_wbm_release_ring.base_vaddr_unaligned,
  1422. be_soc->ppeds_wbm_release_ring.alloc_size,
  1423. soc->ctrl_psoc,
  1424. WLAN_MD_DP_SRNG_PPE_WBM2SW_RELEASE,
  1425. "ppeds_wbm_release_ring");
  1426. }
  1427. static void dp_soc_ppeds_srng_free(struct dp_soc *soc)
  1428. {
  1429. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1430. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1431. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1432. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx))
  1433. return;
  1434. dp_srng_free(soc, &be_soc->ppeds_wbm_release_ring);
  1435. dp_srng_free(soc, &be_soc->ppe2tcl_ring);
  1436. dp_srng_free(soc, &be_soc->reo2ppe_ring);
  1437. }
  1438. static QDF_STATUS dp_soc_ppeds_srng_alloc(struct dp_soc *soc)
  1439. {
  1440. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1441. uint32_t entries;
  1442. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1443. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1444. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx))
  1445. return QDF_STATUS_SUCCESS;
  1446. entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx);
  1447. if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE,
  1448. entries, 0)) {
  1449. dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc);
  1450. goto fail;
  1451. }
  1452. entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx);
  1453. if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL,
  1454. entries, 0)) {
  1455. dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc);
  1456. goto fail;
  1457. }
  1458. entries = wlan_cfg_tx_comp_ring_size(soc_cfg_ctx);
  1459. if (dp_srng_alloc(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
  1460. entries, 1)) {
  1461. dp_err("%pK: dp_srng_alloc failed for ppeds_wbm_release_ring",
  1462. soc);
  1463. goto fail;
  1464. }
  1465. return QDF_STATUS_SUCCESS;
  1466. fail:
  1467. dp_soc_ppeds_srng_free(soc);
  1468. return QDF_STATUS_E_NOMEM;
  1469. }
  1470. static QDF_STATUS dp_soc_ppeds_srng_init(struct dp_soc *soc)
  1471. {
  1472. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1473. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1474. hal_soc_handle_t hal_soc = soc->hal_soc;
  1475. struct dp_ppe_ds_idxs idx = {0};
  1476. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1477. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx))
  1478. return QDF_STATUS_SUCCESS;
  1479. if (dp_ppeds_register_soc_be(be_soc, &idx)) {
  1480. dp_err("%pK: ppeds registration failed", soc);
  1481. goto fail;
  1482. }
  1483. if (dp_srng_init_idx(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0,
  1484. idx.reo2ppe_start_idx)) {
  1485. dp_err("%pK: dp_srng_init failed for reo2ppe", soc);
  1486. goto fail;
  1487. }
  1488. wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  1489. be_soc->reo2ppe_ring.alloc_size,
  1490. soc->ctrl_psoc,
  1491. WLAN_MD_DP_SRNG_REO2PPE,
  1492. "reo2ppe_ring");
  1493. hal_reo_config_reo2ppe_dest_info(hal_soc);
  1494. if (dp_srng_init_idx(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0,
  1495. idx.ppe2tcl_start_idx)) {
  1496. dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc);
  1497. goto fail;
  1498. }
  1499. wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  1500. be_soc->ppe2tcl_ring.alloc_size,
  1501. soc->ctrl_psoc,
  1502. WLAN_MD_DP_SRNG_PPE2TCL,
  1503. "ppe2tcl_ring");
  1504. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  1505. be_soc->ppe2tcl_ring.hal_srng,
  1506. WBM2_SW_PPE_REL_MAP_ID);
  1507. if (dp_srng_init(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
  1508. WBM2_SW_PPE_REL_RING_ID, 0)) {
  1509. dp_err("%pK: dp_srng_init failed for ppeds_wbm_release_ring",
  1510. soc);
  1511. goto fail;
  1512. }
  1513. wlan_minidump_log(be_soc->ppeds_wbm_release_ring.base_vaddr_unaligned,
  1514. be_soc->ppeds_wbm_release_ring.alloc_size,
  1515. soc->ctrl_psoc, WLAN_MD_DP_SRNG_PPE_WBM2SW_RELEASE,
  1516. "ppeds_wbm_release_ring");
  1517. return QDF_STATUS_SUCCESS;
  1518. fail:
  1519. dp_soc_ppeds_srng_deinit(soc);
  1520. return QDF_STATUS_E_NOMEM;
  1521. }
  1522. #else
  1523. static void dp_soc_ppeds_srng_deinit(struct dp_soc *soc)
  1524. {
  1525. }
  1526. static void dp_soc_ppeds_srng_free(struct dp_soc *soc)
  1527. {
  1528. }
  1529. static QDF_STATUS dp_soc_ppeds_srng_alloc(struct dp_soc *soc)
  1530. {
  1531. return QDF_STATUS_SUCCESS;
  1532. }
  1533. static QDF_STATUS dp_soc_ppeds_srng_init(struct dp_soc *soc)
  1534. {
  1535. return QDF_STATUS_SUCCESS;
  1536. }
  1537. #endif
  1538. static void dp_soc_srng_deinit_be(struct dp_soc *soc)
  1539. {
  1540. uint32_t i;
  1541. dp_soc_ppeds_srng_deinit(soc);
  1542. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1543. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1544. dp_srng_deinit(soc, &soc->rx_refill_buf_ring[i],
  1545. RXDMA_BUF, 0);
  1546. }
  1547. }
  1548. }
  1549. static void dp_soc_srng_free_be(struct dp_soc *soc)
  1550. {
  1551. uint32_t i;
  1552. dp_soc_ppeds_srng_free(soc);
  1553. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1554. for (i = 0; i < soc->num_rx_refill_buf_rings; i++)
  1555. dp_srng_free(soc, &soc->rx_refill_buf_ring[i]);
  1556. }
  1557. }
  1558. static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc)
  1559. {
  1560. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1561. uint32_t ring_size;
  1562. uint32_t i;
  1563. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1564. ring_size = wlan_cfg_get_dp_soc_rxdma_refill_ring_size(soc_cfg_ctx);
  1565. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1566. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1567. if (dp_srng_alloc(soc, &soc->rx_refill_buf_ring[i],
  1568. RXDMA_BUF, ring_size, 0)) {
  1569. dp_err("%pK: dp_srng_alloc failed refill ring",
  1570. soc);
  1571. goto fail;
  1572. }
  1573. }
  1574. }
  1575. if (dp_soc_ppeds_srng_alloc(soc)) {
  1576. dp_err("%pK: ppe rings alloc failed",
  1577. soc);
  1578. goto fail;
  1579. }
  1580. return QDF_STATUS_SUCCESS;
  1581. fail:
  1582. dp_soc_srng_free_be(soc);
  1583. return QDF_STATUS_E_NOMEM;
  1584. }
  1585. static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc)
  1586. {
  1587. int i = 0;
  1588. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1589. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1590. if (dp_srng_init(soc, &soc->rx_refill_buf_ring[i],
  1591. RXDMA_BUF, 0, 0)) {
  1592. dp_err("%pK: dp_srng_init failed refill ring",
  1593. soc);
  1594. goto fail;
  1595. }
  1596. }
  1597. }
  1598. if (dp_soc_ppeds_srng_init(soc)) {
  1599. dp_err("%pK: ppe ds rings init failed",
  1600. soc);
  1601. goto fail;
  1602. }
  1603. return QDF_STATUS_SUCCESS;
  1604. fail:
  1605. dp_soc_srng_deinit_be(soc);
  1606. return QDF_STATUS_E_NOMEM;
  1607. }
  1608. #ifdef WLAN_FEATURE_11BE_MLO
  1609. static inline unsigned
  1610. dp_mlo_peer_find_hash_index(dp_mld_peer_hash_obj_t mld_hash_obj,
  1611. union dp_align_mac_addr *mac_addr)
  1612. {
  1613. uint32_t index;
  1614. index =
  1615. mac_addr->align2.bytes_ab ^
  1616. mac_addr->align2.bytes_cd ^
  1617. mac_addr->align2.bytes_ef;
  1618. index ^= index >> mld_hash_obj->mld_peer_hash.idx_bits;
  1619. index &= mld_hash_obj->mld_peer_hash.mask;
  1620. return index;
  1621. }
  1622. QDF_STATUS
  1623. dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj,
  1624. int hash_elems)
  1625. {
  1626. int i, log2;
  1627. if (!mld_hash_obj)
  1628. return QDF_STATUS_E_FAILURE;
  1629. hash_elems *= DP_PEER_HASH_LOAD_MULT;
  1630. hash_elems >>= DP_PEER_HASH_LOAD_SHIFT;
  1631. log2 = dp_log2_ceil(hash_elems);
  1632. hash_elems = 1 << log2;
  1633. mld_hash_obj->mld_peer_hash.mask = hash_elems - 1;
  1634. mld_hash_obj->mld_peer_hash.idx_bits = log2;
  1635. /* allocate an array of TAILQ peer object lists */
  1636. mld_hash_obj->mld_peer_hash.bins = qdf_mem_malloc(
  1637. hash_elems * sizeof(TAILQ_HEAD(anonymous_tail_q, dp_peer)));
  1638. if (!mld_hash_obj->mld_peer_hash.bins)
  1639. return QDF_STATUS_E_NOMEM;
  1640. for (i = 0; i < hash_elems; i++)
  1641. TAILQ_INIT(&mld_hash_obj->mld_peer_hash.bins[i]);
  1642. qdf_spinlock_create(&mld_hash_obj->mld_peer_hash_lock);
  1643. return QDF_STATUS_SUCCESS;
  1644. }
  1645. void
  1646. dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj)
  1647. {
  1648. if (!mld_hash_obj)
  1649. return;
  1650. if (mld_hash_obj->mld_peer_hash.bins) {
  1651. qdf_mem_free(mld_hash_obj->mld_peer_hash.bins);
  1652. mld_hash_obj->mld_peer_hash.bins = NULL;
  1653. qdf_spinlock_destroy(&mld_hash_obj->mld_peer_hash_lock);
  1654. }
  1655. }
  1656. #ifdef WLAN_MLO_MULTI_CHIP
  1657. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1658. {
  1659. /* In case of MULTI chip MLO peer hash table when MLO global object
  1660. * is created, avoid from SOC attach path
  1661. */
  1662. return QDF_STATUS_SUCCESS;
  1663. }
  1664. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1665. {
  1666. }
  1667. #else
  1668. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1669. {
  1670. dp_mld_peer_hash_obj_t mld_hash_obj;
  1671. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1672. if (!mld_hash_obj)
  1673. return QDF_STATUS_E_FAILURE;
  1674. return dp_mlo_peer_find_hash_attach_be(mld_hash_obj, soc->max_peers);
  1675. }
  1676. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1677. {
  1678. dp_mld_peer_hash_obj_t mld_hash_obj;
  1679. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1680. if (!mld_hash_obj)
  1681. return;
  1682. return dp_mlo_peer_find_hash_detach_be(mld_hash_obj);
  1683. }
  1684. #endif
  1685. #ifdef DP_MLO_LINK_STATS_SUPPORT
  1686. static uint8_t
  1687. dp_get_hw_link_id_be(struct dp_pdev *pdev)
  1688. {
  1689. struct dp_pdev_be *be_pdev = dp_get_be_pdev_from_dp_pdev(pdev);
  1690. return ((be_pdev->mlo_link_id) + 1);
  1691. }
  1692. #else
  1693. static uint8_t
  1694. dp_get_hw_link_id_be(struct dp_pdev *pdev)
  1695. {
  1696. return 0;
  1697. }
  1698. #endif
  1699. static struct dp_peer *
  1700. dp_mlo_peer_find_hash_find_be(struct dp_soc *soc,
  1701. uint8_t *peer_mac_addr,
  1702. int mac_addr_is_aligned,
  1703. enum dp_mod_id mod_id,
  1704. uint8_t vdev_id)
  1705. {
  1706. union dp_align_mac_addr local_mac_addr_aligned, *mac_addr;
  1707. uint32_t index;
  1708. struct dp_peer *peer;
  1709. struct dp_vdev *vdev;
  1710. dp_mld_peer_hash_obj_t mld_hash_obj;
  1711. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1712. if (!mld_hash_obj)
  1713. return NULL;
  1714. if (!mld_hash_obj->mld_peer_hash.bins)
  1715. return NULL;
  1716. if (mac_addr_is_aligned) {
  1717. mac_addr = (union dp_align_mac_addr *)peer_mac_addr;
  1718. } else {
  1719. qdf_mem_copy(
  1720. &local_mac_addr_aligned.raw[0],
  1721. peer_mac_addr, QDF_MAC_ADDR_SIZE);
  1722. mac_addr = &local_mac_addr_aligned;
  1723. }
  1724. if (vdev_id != DP_VDEV_ALL) {
  1725. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, mod_id);
  1726. if (!vdev) {
  1727. dp_err("vdev is null\n");
  1728. return NULL;
  1729. }
  1730. } else {
  1731. vdev = NULL;
  1732. }
  1733. /* search mld peer table if no link peer for given mac address */
  1734. index = dp_mlo_peer_find_hash_index(mld_hash_obj, mac_addr);
  1735. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1736. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1737. hash_list_elem) {
  1738. if (dp_peer_find_mac_addr_cmp(mac_addr, &peer->mac_addr) == 0) {
  1739. if ((vdev_id == DP_VDEV_ALL) || (
  1740. dp_peer_find_mac_addr_cmp(
  1741. &peer->vdev->mld_mac_addr,
  1742. &vdev->mld_mac_addr) == 0)) {
  1743. /* take peer reference before returning */
  1744. if (dp_peer_get_ref(NULL, peer, mod_id) !=
  1745. QDF_STATUS_SUCCESS)
  1746. peer = NULL;
  1747. if (vdev)
  1748. dp_vdev_unref_delete(soc, vdev, mod_id);
  1749. qdf_spin_unlock_bh(
  1750. &mld_hash_obj->mld_peer_hash_lock);
  1751. return peer;
  1752. }
  1753. }
  1754. }
  1755. if (vdev)
  1756. dp_vdev_unref_delete(soc, vdev, mod_id);
  1757. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1758. return NULL; /* failure */
  1759. }
  1760. static void
  1761. dp_mlo_peer_find_hash_remove_be(struct dp_soc *soc, struct dp_peer *peer)
  1762. {
  1763. uint32_t index;
  1764. struct dp_peer *tmppeer = NULL;
  1765. int found = 0;
  1766. dp_mld_peer_hash_obj_t mld_hash_obj;
  1767. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1768. if (!mld_hash_obj)
  1769. return;
  1770. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1771. QDF_ASSERT(!TAILQ_EMPTY(&mld_hash_obj->mld_peer_hash.bins[index]));
  1772. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1773. TAILQ_FOREACH(tmppeer, &mld_hash_obj->mld_peer_hash.bins[index],
  1774. hash_list_elem) {
  1775. if (tmppeer == peer) {
  1776. found = 1;
  1777. break;
  1778. }
  1779. }
  1780. QDF_ASSERT(found);
  1781. TAILQ_REMOVE(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1782. hash_list_elem);
  1783. dp_info("Peer %pK (" QDF_MAC_ADDR_FMT ") removed. (found %u)",
  1784. peer, QDF_MAC_ADDR_REF(peer->mac_addr.raw), found);
  1785. dp_peer_unref_delete(peer, DP_MOD_ID_CONFIG);
  1786. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1787. }
  1788. static void
  1789. dp_mlo_peer_find_hash_add_be(struct dp_soc *soc, struct dp_peer *peer)
  1790. {
  1791. uint32_t index;
  1792. dp_mld_peer_hash_obj_t mld_hash_obj;
  1793. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1794. if (!mld_hash_obj)
  1795. return;
  1796. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1797. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1798. if (QDF_IS_STATUS_ERROR(dp_peer_get_ref(NULL, peer,
  1799. DP_MOD_ID_CONFIG))) {
  1800. dp_err("fail to get peer ref:" QDF_MAC_ADDR_FMT,
  1801. QDF_MAC_ADDR_REF(peer->mac_addr.raw));
  1802. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1803. return;
  1804. }
  1805. TAILQ_INSERT_TAIL(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1806. hash_list_elem);
  1807. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1808. dp_info("Peer %pK (" QDF_MAC_ADDR_FMT ") added",
  1809. peer, QDF_MAC_ADDR_REF(peer->mac_addr.raw));
  1810. }
  1811. void dp_print_mlo_ast_stats_be(struct dp_soc *soc)
  1812. {
  1813. uint32_t index;
  1814. struct dp_peer *peer;
  1815. dp_mld_peer_hash_obj_t mld_hash_obj;
  1816. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1817. if (!mld_hash_obj)
  1818. return;
  1819. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1820. for (index = 0; index < mld_hash_obj->mld_peer_hash.mask; index++) {
  1821. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1822. hash_list_elem) {
  1823. dp_print_peer_ast_entries(soc, peer, NULL);
  1824. }
  1825. }
  1826. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1827. }
  1828. #endif
  1829. #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
  1830. static void dp_reconfig_tx_vdev_mcast_ctrl_be(struct dp_soc *soc,
  1831. struct dp_vdev *vdev)
  1832. {
  1833. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1834. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1835. hal_soc_handle_t hal_soc = soc->hal_soc;
  1836. uint8_t vdev_id = vdev->vdev_id;
  1837. if (vdev->opmode == wlan_op_mode_sta) {
  1838. if (vdev->pdev->isolation)
  1839. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1840. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1841. else
  1842. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1843. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  1844. } else if (vdev->opmode == wlan_op_mode_ap) {
  1845. hal_tx_mcast_mlo_reinject_routing_set(
  1846. hal_soc,
  1847. HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY);
  1848. if (vdev->mlo_vdev) {
  1849. hal_tx_vdev_mcast_ctrl_set(
  1850. hal_soc,
  1851. vdev_id,
  1852. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  1853. } else {
  1854. hal_tx_vdev_mcast_ctrl_set(hal_soc,
  1855. vdev_id,
  1856. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1857. }
  1858. }
  1859. }
  1860. static void dp_bank_reconfig_be(struct dp_soc *soc, struct dp_vdev *vdev)
  1861. {
  1862. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1863. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1864. union hal_tx_bank_config *bank_config;
  1865. if (!be_vdev || be_vdev->bank_id == DP_BE_INVALID_BANK_ID)
  1866. return;
  1867. bank_config = &be_soc->bank_profiles[be_vdev->bank_id].bank_config;
  1868. hal_tx_populate_bank_register(be_soc->soc.hal_soc, bank_config,
  1869. be_vdev->bank_id);
  1870. }
  1871. #endif
  1872. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1873. defined(WLAN_MCAST_MLO)
  1874. static void dp_mlo_mcast_reset_pri_mcast(struct dp_vdev_be *be_vdev,
  1875. struct dp_vdev *ptnr_vdev,
  1876. void *arg)
  1877. {
  1878. struct dp_vdev_be *be_ptnr_vdev =
  1879. dp_get_be_vdev_from_dp_vdev(ptnr_vdev);
  1880. be_ptnr_vdev->mcast_primary = false;
  1881. }
  1882. #if defined(CONFIG_MLO_SINGLE_DEV)
  1883. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1884. struct dp_vdev *vdev,
  1885. cdp_config_param_type val)
  1886. {
  1887. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1888. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(
  1889. be_vdev->vdev.pdev->soc);
  1890. be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev;
  1891. vdev->mlo_vdev = true;
  1892. if (be_vdev->mcast_primary) {
  1893. struct cdp_txrx_peer_params_update params = {0};
  1894. params.chip_id = be_soc->mlo_chip_id;
  1895. params.pdev_id = be_vdev->vdev.pdev->pdev_id;
  1896. params.osif_vdev = be_vdev->vdev.osif_vdev;
  1897. dp_wdi_event_handler(
  1898. WDI_EVENT_MCAST_PRIMARY_UPDATE,
  1899. be_vdev->vdev.pdev->soc,
  1900. (void *)&params, CDP_INVALID_PEER,
  1901. WDI_NO_VAL, params.pdev_id);
  1902. }
  1903. }
  1904. #else
  1905. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1906. struct dp_vdev *vdev,
  1907. cdp_config_param_type val)
  1908. {
  1909. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1910. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(
  1911. be_vdev->vdev.pdev->soc);
  1912. be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev;
  1913. vdev->mlo_vdev = true;
  1914. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  1915. vdev->vdev_id,
  1916. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  1917. if (be_vdev->mcast_primary) {
  1918. struct cdp_txrx_peer_params_update params = {0};
  1919. dp_mcast_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  1920. dp_mlo_mcast_reset_pri_mcast,
  1921. (void *)&be_vdev->mcast_primary,
  1922. DP_MOD_ID_TX_MCAST);
  1923. params.chip_id = be_soc->mlo_chip_id;
  1924. params.pdev_id = vdev->pdev->pdev_id;
  1925. params.osif_vdev = vdev->osif_vdev;
  1926. dp_wdi_event_handler(
  1927. WDI_EVENT_MCAST_PRIMARY_UPDATE,
  1928. vdev->pdev->soc,
  1929. (void *)&params, CDP_INVALID_PEER,
  1930. WDI_NO_VAL, params.pdev_id);
  1931. }
  1932. }
  1933. #endif
  1934. static void dp_txrx_reset_mlo_mcast_primary_vdev_param_be(
  1935. struct dp_vdev *vdev,
  1936. cdp_config_param_type val)
  1937. {
  1938. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1939. be_vdev->mcast_primary = false;
  1940. vdev->mlo_vdev = false;
  1941. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  1942. vdev->vdev_id,
  1943. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1944. }
  1945. /**
  1946. * dp_txrx_get_vdev_mcast_param_be() - Target specific ops for getting vdev
  1947. * params related to multicast
  1948. * @soc: DP soc handle
  1949. * @vdev: pointer to vdev structure
  1950. * @val: buffer address
  1951. *
  1952. * Return: QDF_STATUS
  1953. */
  1954. static
  1955. QDF_STATUS dp_txrx_get_vdev_mcast_param_be(struct dp_soc *soc,
  1956. struct dp_vdev *vdev,
  1957. cdp_config_param_type *val)
  1958. {
  1959. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1960. if (be_vdev->mcast_primary)
  1961. val->cdp_vdev_param_mcast_vdev = true;
  1962. else
  1963. val->cdp_vdev_param_mcast_vdev = false;
  1964. return QDF_STATUS_SUCCESS;
  1965. }
  1966. #else
  1967. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1968. struct dp_vdev *vdev,
  1969. cdp_config_param_type val)
  1970. {
  1971. }
  1972. static void dp_txrx_reset_mlo_mcast_primary_vdev_param_be(
  1973. struct dp_vdev *vdev,
  1974. cdp_config_param_type val)
  1975. {
  1976. }
  1977. static
  1978. QDF_STATUS dp_txrx_get_vdev_mcast_param_be(struct dp_soc *soc,
  1979. struct dp_vdev *vdev,
  1980. cdp_config_param_type *val)
  1981. {
  1982. return QDF_STATUS_SUCCESS;
  1983. }
  1984. #endif
  1985. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  1986. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1987. uint8_t tx_ring_id,
  1988. uint8_t bm_id)
  1989. {
  1990. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  1991. soc->tcl_data_ring[tx_ring_id].hal_srng,
  1992. bm_id);
  1993. }
  1994. #else
  1995. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1996. uint8_t tx_ring_id,
  1997. uint8_t bm_id)
  1998. {
  1999. }
  2000. #endif
  2001. /**
  2002. * dp_txrx_set_vdev_param_be() - Target specific ops while setting vdev params
  2003. * @soc: DP soc handle
  2004. * @vdev: pointer to vdev structure
  2005. * @param: parameter type to get value
  2006. * @val: value
  2007. *
  2008. * Return: QDF_STATUS
  2009. */
  2010. static
  2011. QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc,
  2012. struct dp_vdev *vdev,
  2013. enum cdp_vdev_param_type param,
  2014. cdp_config_param_type val)
  2015. {
  2016. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2017. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  2018. switch (param) {
  2019. case CDP_TX_ENCAP_TYPE:
  2020. case CDP_UPDATE_DSCP_TO_TID_MAP:
  2021. case CDP_UPDATE_TDLS_FLAGS:
  2022. dp_tx_update_bank_profile(be_soc, be_vdev);
  2023. break;
  2024. case CDP_ENABLE_CIPHER:
  2025. if (vdev->tx_encap_type == htt_cmn_pkt_type_raw)
  2026. dp_tx_update_bank_profile(be_soc, be_vdev);
  2027. break;
  2028. case CDP_SET_MCAST_VDEV:
  2029. dp_txrx_set_mlo_mcast_primary_vdev_param_be(vdev, val);
  2030. break;
  2031. case CDP_RESET_MLO_MCAST_VDEV:
  2032. dp_txrx_reset_mlo_mcast_primary_vdev_param_be(vdev, val);
  2033. break;
  2034. default:
  2035. dp_warn("invalid param %d", param);
  2036. break;
  2037. }
  2038. return QDF_STATUS_SUCCESS;
  2039. }
  2040. #ifdef WLAN_FEATURE_11BE_MLO
  2041. #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH
  2042. static inline void
  2043. dp_soc_max_peer_id_set(struct dp_soc *soc)
  2044. {
  2045. soc->peer_id_shift = dp_log2_ceil(soc->max_peers);
  2046. soc->peer_id_mask = (1 << soc->peer_id_shift) - 1;
  2047. /*
  2048. * Double the peers since we use ML indication bit
  2049. * alongwith peer_id to find peers.
  2050. */
  2051. soc->max_peer_id = 1 << (soc->peer_id_shift + 1);
  2052. }
  2053. #else
  2054. static inline void
  2055. dp_soc_max_peer_id_set(struct dp_soc *soc)
  2056. {
  2057. soc->max_peer_id =
  2058. (1 << (HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S + 1)) - 1;
  2059. }
  2060. #endif /* DP_USE_REDUCED_PEER_ID_FIELD_WIDTH */
  2061. #else
  2062. static inline void
  2063. dp_soc_max_peer_id_set(struct dp_soc *soc)
  2064. {
  2065. soc->max_peer_id = soc->max_peers;
  2066. }
  2067. #endif /* WLAN_FEATURE_11BE_MLO */
  2068. static void dp_peer_map_detach_be(struct dp_soc *soc)
  2069. {
  2070. if (soc->host_ast_db_enable)
  2071. dp_peer_ast_hash_detach(soc);
  2072. }
  2073. static QDF_STATUS dp_peer_map_attach_be(struct dp_soc *soc)
  2074. {
  2075. QDF_STATUS status;
  2076. if (soc->host_ast_db_enable) {
  2077. status = dp_peer_ast_hash_attach(soc);
  2078. if (QDF_IS_STATUS_ERROR(status))
  2079. return status;
  2080. }
  2081. dp_soc_max_peer_id_set(soc);
  2082. return QDF_STATUS_SUCCESS;
  2083. }
  2084. static struct dp_peer *dp_find_peer_by_destmac_be(struct dp_soc *soc,
  2085. uint8_t *dest_mac,
  2086. uint8_t vdev_id)
  2087. {
  2088. struct dp_peer *peer = NULL;
  2089. struct dp_peer *tgt_peer = NULL;
  2090. struct dp_ast_entry *ast_entry = NULL;
  2091. uint16_t peer_id;
  2092. qdf_spin_lock_bh(&soc->ast_lock);
  2093. ast_entry = dp_peer_ast_hash_find_soc(soc, dest_mac);
  2094. if (!ast_entry) {
  2095. qdf_spin_unlock_bh(&soc->ast_lock);
  2096. dp_err("NULL ast entry");
  2097. return NULL;
  2098. }
  2099. peer_id = ast_entry->peer_id;
  2100. qdf_spin_unlock_bh(&soc->ast_lock);
  2101. if (peer_id == HTT_INVALID_PEER)
  2102. return NULL;
  2103. peer = dp_peer_get_ref_by_id(soc, peer_id, DP_MOD_ID_SAWF);
  2104. if (!peer) {
  2105. dp_err("NULL peer for peer_id:%d", peer_id);
  2106. return NULL;
  2107. }
  2108. tgt_peer = dp_get_tgt_peer_from_peer(peer);
  2109. /*
  2110. * Once tgt_peer is obtained,
  2111. * release the ref taken for original peer.
  2112. */
  2113. dp_peer_get_ref(NULL, tgt_peer, DP_MOD_ID_SAWF);
  2114. dp_peer_unref_delete(peer, DP_MOD_ID_SAWF);
  2115. return tgt_peer;
  2116. }
  2117. #ifdef WLAN_FEATURE_11BE_MLO
  2118. #ifdef WLAN_MCAST_MLO
  2119. static inline void
  2120. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  2121. {
  2122. arch_ops->dp_tx_mcast_handler = dp_tx_mlo_mcast_handler_be;
  2123. arch_ops->dp_rx_mcast_handler = dp_rx_mlo_igmp_handler;
  2124. arch_ops->dp_tx_is_mcast_primary = dp_tx_mlo_is_mcast_primary_be;
  2125. }
  2126. #else /* WLAN_MCAST_MLO */
  2127. static inline void
  2128. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  2129. {
  2130. }
  2131. #endif /* WLAN_MCAST_MLO */
  2132. #ifdef WLAN_MLO_MULTI_CHIP
  2133. static inline void
  2134. dp_initialize_arch_ops_be_mlo_multi_chip(struct dp_arch_ops *arch_ops)
  2135. {
  2136. arch_ops->dp_partner_chips_map = dp_mlo_partner_chips_map;
  2137. arch_ops->dp_partner_chips_unmap = dp_mlo_partner_chips_unmap;
  2138. arch_ops->dp_soc_get_by_idle_bm_id = dp_soc_get_by_idle_bm_id;
  2139. }
  2140. #else
  2141. static inline void
  2142. dp_initialize_arch_ops_be_mlo_multi_chip(struct dp_arch_ops *arch_ops)
  2143. {
  2144. }
  2145. #endif
  2146. static inline void
  2147. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  2148. {
  2149. dp_initialize_arch_ops_be_mcast_mlo(arch_ops);
  2150. dp_initialize_arch_ops_be_mlo_multi_chip(arch_ops);
  2151. arch_ops->mlo_peer_find_hash_detach =
  2152. dp_mlo_peer_find_hash_detach_wrapper;
  2153. arch_ops->mlo_peer_find_hash_attach =
  2154. dp_mlo_peer_find_hash_attach_wrapper;
  2155. arch_ops->mlo_peer_find_hash_add = dp_mlo_peer_find_hash_add_be;
  2156. arch_ops->mlo_peer_find_hash_remove = dp_mlo_peer_find_hash_remove_be;
  2157. arch_ops->mlo_peer_find_hash_find = dp_mlo_peer_find_hash_find_be;
  2158. arch_ops->get_hw_link_id = dp_get_hw_link_id_be;
  2159. }
  2160. #else /* WLAN_FEATURE_11BE_MLO */
  2161. static inline void
  2162. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  2163. {
  2164. }
  2165. #endif /* WLAN_FEATURE_11BE_MLO */
  2166. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  2167. #define DP_LMAC_PEER_ID_MSB_LEGACY 2
  2168. #define DP_LMAC_PEER_ID_MSB_MLO 3
  2169. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  2170. struct cdp_peer_setup_info *setup_info,
  2171. enum cdp_host_reo_dest_ring *reo_dest,
  2172. bool *hash_based,
  2173. uint8_t *lmac_peer_id_msb)
  2174. {
  2175. struct dp_soc *soc = vdev->pdev->soc;
  2176. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2177. if (!be_soc->mlo_enabled)
  2178. return dp_vdev_get_default_reo_hash(vdev, reo_dest,
  2179. hash_based);
  2180. *hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  2181. *reo_dest = vdev->pdev->reo_dest;
  2182. /* Not a ML link peer use non-mlo */
  2183. if (!setup_info) {
  2184. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
  2185. return;
  2186. }
  2187. /* For STA ML VAP we do not have num links info at this point
  2188. * use MLO case always
  2189. */
  2190. if (vdev->opmode == wlan_op_mode_sta) {
  2191. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
  2192. return;
  2193. }
  2194. /* For AP ML VAP consider the peer as ML only it associates with
  2195. * multiple links
  2196. */
  2197. if (setup_info->num_links == 1) {
  2198. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
  2199. return;
  2200. }
  2201. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
  2202. }
  2203. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  2204. uint32_t *remap0,
  2205. uint32_t *remap1,
  2206. uint32_t *remap2)
  2207. {
  2208. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2209. uint32_t reo_config = wlan_cfg_get_reo_rings_mapping(soc->wlan_cfg_ctx);
  2210. uint32_t reo_mlo_config =
  2211. wlan_cfg_mlo_rx_ring_map_get(soc->wlan_cfg_ctx);
  2212. if (!be_soc->mlo_enabled)
  2213. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  2214. *remap0 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
  2215. *remap1 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_config);
  2216. *remap2 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
  2217. return true;
  2218. }
  2219. #else
  2220. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  2221. struct cdp_peer_setup_info *setup_info,
  2222. enum cdp_host_reo_dest_ring *reo_dest,
  2223. bool *hash_based,
  2224. uint8_t *lmac_peer_id_msb)
  2225. {
  2226. dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based);
  2227. }
  2228. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  2229. uint32_t *remap0,
  2230. uint32_t *remap1,
  2231. uint32_t *remap2)
  2232. {
  2233. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  2234. }
  2235. #endif
  2236. #ifdef CONFIG_MLO_SINGLE_DEV
  2237. static inline
  2238. void dp_initialize_arch_ops_be_single_dev(struct dp_arch_ops *arch_ops)
  2239. {
  2240. arch_ops->dp_tx_mlo_mcast_send = dp_tx_mlo_mcast_send_be;
  2241. }
  2242. #else
  2243. static inline
  2244. void dp_initialize_arch_ops_be_single_dev(struct dp_arch_ops *arch_ops)
  2245. {
  2246. }
  2247. #endif
  2248. #ifdef IPA_OFFLOAD
  2249. static int8_t dp_ipa_get_bank_id_be(struct dp_soc *soc)
  2250. {
  2251. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2252. return be_soc->ipa_bank_id;
  2253. }
  2254. static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
  2255. {
  2256. arch_ops->ipa_get_bank_id = dp_ipa_get_bank_id_be;
  2257. }
  2258. #else /* !IPA_OFFLOAD */
  2259. static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
  2260. {
  2261. }
  2262. #endif /* IPA_OFFLOAD */
  2263. void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
  2264. {
  2265. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  2266. arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be;
  2267. arch_ops->dp_rx_process = dp_rx_process_be;
  2268. arch_ops->dp_tx_send_fast = dp_tx_fast_send_be;
  2269. arch_ops->tx_comp_get_params_from_hal_desc =
  2270. dp_tx_comp_get_params_from_hal_desc_be;
  2271. arch_ops->dp_tx_process_htt_completion =
  2272. dp_tx_process_htt_completion_be;
  2273. arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be;
  2274. arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be;
  2275. arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be;
  2276. arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be;
  2277. arch_ops->dp_wbm_get_rx_desc_from_hal_desc =
  2278. dp_wbm_get_rx_desc_from_hal_desc_be;
  2279. arch_ops->dp_tx_compute_hw_delay = dp_tx_compute_tx_delay_be;
  2280. arch_ops->dp_rx_chain_msdus = dp_rx_chain_msdus_be;
  2281. arch_ops->dp_rx_wbm_err_reap_desc = dp_rx_wbm_err_reap_desc_be;
  2282. arch_ops->dp_rx_null_q_desc_handle = dp_rx_null_q_desc_handle_be;
  2283. #endif
  2284. arch_ops->txrx_get_context_size = dp_get_context_size_be;
  2285. #ifdef WIFI_MONITOR_SUPPORT
  2286. arch_ops->txrx_get_mon_context_size = dp_mon_get_context_size_be;
  2287. #endif
  2288. arch_ops->dp_rx_desc_cookie_2_va =
  2289. dp_rx_desc_cookie_2_va_be;
  2290. arch_ops->dp_rx_intrabss_mcast_handler =
  2291. dp_rx_intrabss_mcast_handler_be;
  2292. arch_ops->dp_rx_word_mask_subscribe = dp_rx_word_mask_subscribe_be;
  2293. arch_ops->txrx_soc_attach = dp_soc_attach_be;
  2294. arch_ops->txrx_soc_detach = dp_soc_detach_be;
  2295. arch_ops->txrx_soc_init = dp_soc_init_be;
  2296. arch_ops->txrx_soc_deinit = dp_soc_deinit_be;
  2297. arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be;
  2298. arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be;
  2299. arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be;
  2300. arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be;
  2301. arch_ops->txrx_pdev_attach = dp_pdev_attach_be;
  2302. arch_ops->txrx_pdev_detach = dp_pdev_detach_be;
  2303. arch_ops->txrx_vdev_attach = dp_vdev_attach_be;
  2304. arch_ops->txrx_vdev_detach = dp_vdev_detach_be;
  2305. arch_ops->txrx_peer_setup = dp_peer_setup_be;
  2306. arch_ops->txrx_peer_map_attach = dp_peer_map_attach_be;
  2307. arch_ops->txrx_peer_map_detach = dp_peer_map_detach_be;
  2308. arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be;
  2309. arch_ops->dp_rx_peer_metadata_peer_id_get =
  2310. dp_rx_peer_metadata_peer_id_get_be;
  2311. arch_ops->dp_rx_peer_mdata_link_id_get =
  2312. dp_rx_peer_mdata_link_id_get_be;
  2313. arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be;
  2314. arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be;
  2315. arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be;
  2316. dp_initialize_arch_ops_be_mlo(arch_ops);
  2317. arch_ops->dp_rx_replenish_soc_get = dp_rx_replensih_soc_get;
  2318. arch_ops->dp_soc_get_num_soc = dp_soc_get_num_soc_be;
  2319. arch_ops->dp_peer_rx_reorder_queue_setup =
  2320. dp_peer_rx_reorder_queue_setup_be;
  2321. arch_ops->txrx_print_peer_stats = dp_print_peer_txrx_stats_be;
  2322. arch_ops->dp_find_peer_by_destmac = dp_find_peer_by_destmac_be;
  2323. #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
  2324. arch_ops->dp_bank_reconfig = dp_bank_reconfig_be;
  2325. arch_ops->dp_reconfig_tx_vdev_mcast_ctrl =
  2326. dp_reconfig_tx_vdev_mcast_ctrl_be;
  2327. arch_ops->dp_cc_reg_cfg_init = dp_cc_reg_cfg_init;
  2328. #endif
  2329. #ifdef WLAN_SUPPORT_PPEDS
  2330. arch_ops->dp_txrx_ppeds_rings_status = dp_ppeds_rings_status;
  2331. arch_ops->txrx_soc_ppeds_start = dp_ppeds_start_soc_be;
  2332. arch_ops->txrx_soc_ppeds_stop = dp_ppeds_stop_soc_be;
  2333. arch_ops->dp_register_ppeds_interrupts = dp_register_ppeds_interrupts;
  2334. arch_ops->dp_free_ppeds_interrupts = dp_free_ppeds_interrupts;
  2335. arch_ops->dp_tx_ppeds_inuse_desc = dp_ppeds_inuse_desc;
  2336. arch_ops->dp_tx_ppeds_cfg_astidx_cache_mapping =
  2337. dp_tx_ppeds_cfg_astidx_cache_mapping;
  2338. #endif
  2339. dp_init_near_full_arch_ops_be(arch_ops);
  2340. arch_ops->get_reo_qdesc_addr = dp_rx_get_reo_qdesc_addr_be;
  2341. arch_ops->get_rx_hash_key = dp_get_rx_hash_key_be;
  2342. arch_ops->dp_set_rx_fst = dp_set_rx_fst_be;
  2343. arch_ops->dp_get_rx_fst = dp_get_rx_fst_be;
  2344. arch_ops->dp_rx_fst_deref = dp_rx_fst_release_ref_be;
  2345. arch_ops->dp_rx_fst_ref = dp_rx_fst_get_ref_be;
  2346. arch_ops->print_mlo_ast_stats = dp_print_mlo_ast_stats_be;
  2347. arch_ops->peer_get_reo_hash = dp_peer_get_reo_hash_be;
  2348. arch_ops->reo_remap_config = dp_reo_remap_config_be;
  2349. arch_ops->txrx_get_vdev_mcast_param = dp_txrx_get_vdev_mcast_param_be;
  2350. dp_initialize_arch_ops_be_ipa(arch_ops);
  2351. dp_initialize_arch_ops_be_single_dev(arch_ops);
  2352. }