sde_crtc.c 176 KB

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  1. /*
  2. * Copyright (c) 2014-2020 The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/sort.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/ktime.h>
  22. #include <drm/sde_drm.h>
  23. #include <drm/drm_mode.h>
  24. #include <drm/drm_crtc.h>
  25. #include <drm/drm_probe_helper.h>
  26. #include <drm/drm_flip_work.h>
  27. #include "sde_kms.h"
  28. #include "sde_hw_lm.h"
  29. #include "sde_hw_ctl.h"
  30. #include "sde_crtc.h"
  31. #include "sde_plane.h"
  32. #include "sde_hw_util.h"
  33. #include "sde_hw_catalog.h"
  34. #include "sde_color_processing.h"
  35. #include "sde_encoder.h"
  36. #include "sde_connector.h"
  37. #include "sde_vbif.h"
  38. #include "sde_power_handle.h"
  39. #include "sde_core_perf.h"
  40. #include "sde_trace.h"
  41. #define SDE_PSTATES_MAX (SDE_STAGE_MAX * 4)
  42. #define SDE_MULTIRECT_PLANE_MAX (SDE_STAGE_MAX * 2)
  43. struct sde_crtc_custom_events {
  44. u32 event;
  45. int (*func)(struct drm_crtc *crtc, bool en,
  46. struct sde_irq_callback *irq);
  47. };
  48. static int sde_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
  49. bool en, struct sde_irq_callback *ad_irq);
  50. static int sde_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
  51. bool en, struct sde_irq_callback *idle_irq);
  52. static int sde_crtc_pm_event_handler(struct drm_crtc *crtc, bool en,
  53. struct sde_irq_callback *noirq);
  54. static struct sde_crtc_custom_events custom_events[] = {
  55. {DRM_EVENT_AD_BACKLIGHT, sde_cp_ad_interrupt},
  56. {DRM_EVENT_CRTC_POWER, sde_crtc_power_interrupt_handler},
  57. {DRM_EVENT_IDLE_NOTIFY, sde_crtc_idle_interrupt_handler},
  58. {DRM_EVENT_HISTOGRAM, sde_cp_hist_interrupt},
  59. {DRM_EVENT_SDE_POWER, sde_crtc_pm_event_handler},
  60. {DRM_EVENT_LTM_HIST, sde_cp_ltm_hist_interrupt},
  61. {DRM_EVENT_LTM_WB_PB, sde_cp_ltm_wb_pb_interrupt},
  62. {DRM_EVENT_LTM_OFF, sde_cp_ltm_off_event_handler},
  63. };
  64. /* default input fence timeout, in ms */
  65. #define SDE_CRTC_INPUT_FENCE_TIMEOUT 10000
  66. /*
  67. * The default input fence timeout is 2 seconds while max allowed
  68. * range is 10 seconds. Any value above 10 seconds adds glitches beyond
  69. * tolerance limit.
  70. */
  71. #define SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT 10000
  72. /* layer mixer index on sde_crtc */
  73. #define LEFT_MIXER 0
  74. #define RIGHT_MIXER 1
  75. #define MISR_BUFF_SIZE 256
  76. /*
  77. * Time period for fps calculation in micro seconds.
  78. * Default value is set to 1 sec.
  79. */
  80. #define DEFAULT_FPS_PERIOD_1_SEC 1000000
  81. #define MAX_FPS_PERIOD_5_SECONDS 5000000
  82. #define MAX_FRAME_COUNT 1000
  83. #define MILI_TO_MICRO 1000
  84. #define SKIP_STAGING_PIPE_ZPOS 255
  85. static inline struct sde_kms *_sde_crtc_get_kms(struct drm_crtc *crtc)
  86. {
  87. struct msm_drm_private *priv;
  88. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  89. SDE_ERROR("invalid crtc\n");
  90. return NULL;
  91. }
  92. priv = crtc->dev->dev_private;
  93. if (!priv || !priv->kms) {
  94. SDE_ERROR("invalid kms\n");
  95. return NULL;
  96. }
  97. return to_sde_kms(priv->kms);
  98. }
  99. /**
  100. * sde_crtc_calc_fps() - Calculates fps value.
  101. * @sde_crtc : CRTC structure
  102. *
  103. * This function is called at frame done. It counts the number
  104. * of frames done for every 1 sec. Stores the value in measured_fps.
  105. * measured_fps value is 10 times the calculated fps value.
  106. * For example, measured_fps= 594 for calculated fps of 59.4
  107. */
  108. static void sde_crtc_calc_fps(struct sde_crtc *sde_crtc)
  109. {
  110. ktime_t current_time_us;
  111. u64 fps, diff_us;
  112. current_time_us = ktime_get();
  113. diff_us = (u64)ktime_us_delta(current_time_us,
  114. sde_crtc->fps_info.last_sampled_time_us);
  115. sde_crtc->fps_info.frame_count++;
  116. if (diff_us >= DEFAULT_FPS_PERIOD_1_SEC) {
  117. /* Multiplying with 10 to get fps in floating point */
  118. fps = ((u64)sde_crtc->fps_info.frame_count)
  119. * DEFAULT_FPS_PERIOD_1_SEC * 10;
  120. do_div(fps, diff_us);
  121. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  122. SDE_DEBUG(" FPS for crtc%d is %d.%d\n",
  123. sde_crtc->base.base.id, (unsigned int)fps/10,
  124. (unsigned int)fps%10);
  125. sde_crtc->fps_info.last_sampled_time_us = current_time_us;
  126. sde_crtc->fps_info.frame_count = 0;
  127. }
  128. if (!sde_crtc->fps_info.time_buf)
  129. return;
  130. /**
  131. * Array indexing is based on sliding window algorithm.
  132. * sde_crtc->time_buf has a maximum capacity of MAX_FRAME_COUNT
  133. * time slots. As the count increases to MAX_FRAME_COUNT + 1, the
  134. * counter loops around and comes back to the first index to store
  135. * the next ktime.
  136. */
  137. sde_crtc->fps_info.time_buf[sde_crtc->fps_info.next_time_index++] =
  138. ktime_get();
  139. sde_crtc->fps_info.next_time_index %= MAX_FRAME_COUNT;
  140. }
  141. static void _sde_crtc_deinit_events(struct sde_crtc *sde_crtc)
  142. {
  143. if (!sde_crtc)
  144. return;
  145. }
  146. #ifdef CONFIG_DEBUG_FS
  147. static int _sde_debugfs_fps_status_show(struct seq_file *s, void *data)
  148. {
  149. struct sde_crtc *sde_crtc;
  150. u64 fps_int, fps_float;
  151. ktime_t current_time_us;
  152. u64 fps, diff_us;
  153. if (!s || !s->private) {
  154. SDE_ERROR("invalid input param(s)\n");
  155. return -EAGAIN;
  156. }
  157. sde_crtc = s->private;
  158. current_time_us = ktime_get();
  159. diff_us = (u64)ktime_us_delta(current_time_us,
  160. sde_crtc->fps_info.last_sampled_time_us);
  161. if (diff_us >= DEFAULT_FPS_PERIOD_1_SEC) {
  162. /* Multiplying with 10 to get fps in floating point */
  163. fps = ((u64)sde_crtc->fps_info.frame_count)
  164. * DEFAULT_FPS_PERIOD_1_SEC * 10;
  165. do_div(fps, diff_us);
  166. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  167. sde_crtc->fps_info.last_sampled_time_us = current_time_us;
  168. sde_crtc->fps_info.frame_count = 0;
  169. SDE_DEBUG("Measured FPS for crtc%d is %d.%d\n",
  170. sde_crtc->base.base.id, (unsigned int)fps/10,
  171. (unsigned int)fps%10);
  172. }
  173. fps_int = (unsigned int) sde_crtc->fps_info.measured_fps;
  174. fps_float = do_div(fps_int, 10);
  175. seq_printf(s, "fps: %llu.%llu\n", fps_int, fps_float);
  176. return 0;
  177. }
  178. static int _sde_debugfs_fps_status(struct inode *inode, struct file *file)
  179. {
  180. return single_open(file, _sde_debugfs_fps_status_show,
  181. inode->i_private);
  182. }
  183. #endif
  184. static ssize_t fps_periodicity_ms_store(struct device *device,
  185. struct device_attribute *attr, const char *buf, size_t count)
  186. {
  187. struct drm_crtc *crtc;
  188. struct sde_crtc *sde_crtc;
  189. int res;
  190. /* Base of the input */
  191. int cnt = 10;
  192. if (!device || !buf) {
  193. SDE_ERROR("invalid input param(s)\n");
  194. return -EAGAIN;
  195. }
  196. crtc = dev_get_drvdata(device);
  197. if (!crtc)
  198. return -EINVAL;
  199. sde_crtc = to_sde_crtc(crtc);
  200. res = kstrtou32(buf, cnt, &sde_crtc->fps_info.fps_periodic_duration);
  201. if (res < 0)
  202. return res;
  203. if (sde_crtc->fps_info.fps_periodic_duration <= 0)
  204. sde_crtc->fps_info.fps_periodic_duration =
  205. DEFAULT_FPS_PERIOD_1_SEC;
  206. else if ((sde_crtc->fps_info.fps_periodic_duration) * MILI_TO_MICRO >
  207. MAX_FPS_PERIOD_5_SECONDS)
  208. sde_crtc->fps_info.fps_periodic_duration =
  209. MAX_FPS_PERIOD_5_SECONDS;
  210. else
  211. sde_crtc->fps_info.fps_periodic_duration *= MILI_TO_MICRO;
  212. return count;
  213. }
  214. static ssize_t fps_periodicity_ms_show(struct device *device,
  215. struct device_attribute *attr, char *buf)
  216. {
  217. struct drm_crtc *crtc;
  218. struct sde_crtc *sde_crtc;
  219. if (!device || !buf) {
  220. SDE_ERROR("invalid input param(s)\n");
  221. return -EAGAIN;
  222. }
  223. crtc = dev_get_drvdata(device);
  224. if (!crtc)
  225. return -EINVAL;
  226. sde_crtc = to_sde_crtc(crtc);
  227. return scnprintf(buf, PAGE_SIZE, "%d\n",
  228. (sde_crtc->fps_info.fps_periodic_duration)/MILI_TO_MICRO);
  229. }
  230. static ssize_t measured_fps_show(struct device *device,
  231. struct device_attribute *attr, char *buf)
  232. {
  233. struct drm_crtc *crtc;
  234. struct sde_crtc *sde_crtc;
  235. uint64_t fps_int, fps_decimal;
  236. u64 fps = 0, frame_count = 0;
  237. ktime_t current_time;
  238. int i = 0, current_time_index;
  239. u64 diff_us;
  240. if (!device || !buf) {
  241. SDE_ERROR("invalid input param(s)\n");
  242. return -EAGAIN;
  243. }
  244. crtc = dev_get_drvdata(device);
  245. if (!crtc) {
  246. scnprintf(buf, PAGE_SIZE, "fps information not available");
  247. return -EINVAL;
  248. }
  249. sde_crtc = to_sde_crtc(crtc);
  250. if (!sde_crtc->fps_info.time_buf) {
  251. scnprintf(buf, PAGE_SIZE,
  252. "timebuf null - fps information not available");
  253. return -EINVAL;
  254. }
  255. /**
  256. * Whenever the time_index counter comes to zero upon decrementing,
  257. * it is set to the last index since it is the next index that we
  258. * should check for calculating the buftime.
  259. */
  260. current_time_index = (sde_crtc->fps_info.next_time_index == 0) ?
  261. MAX_FRAME_COUNT - 1 : (sde_crtc->fps_info.next_time_index - 1);
  262. current_time = ktime_get();
  263. for (i = 0; i < MAX_FRAME_COUNT; i++) {
  264. u64 ptime = (u64)ktime_to_us(current_time);
  265. u64 buftime = (u64)ktime_to_us(
  266. sde_crtc->fps_info.time_buf[current_time_index]);
  267. diff_us = (u64)ktime_us_delta(current_time,
  268. sde_crtc->fps_info.time_buf[current_time_index]);
  269. if (ptime > buftime && diff_us >= (u64)
  270. sde_crtc->fps_info.fps_periodic_duration) {
  271. /* Multiplying with 10 to get fps in floating point */
  272. fps = frame_count * DEFAULT_FPS_PERIOD_1_SEC * 10;
  273. do_div(fps, diff_us);
  274. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  275. SDE_DEBUG("measured fps: %d\n",
  276. sde_crtc->fps_info.measured_fps);
  277. break;
  278. }
  279. current_time_index = (current_time_index == 0) ?
  280. (MAX_FRAME_COUNT - 1) : (current_time_index - 1);
  281. SDE_DEBUG("current time index: %d\n", current_time_index);
  282. frame_count++;
  283. }
  284. if (i == MAX_FRAME_COUNT) {
  285. current_time_index = (sde_crtc->fps_info.next_time_index == 0) ?
  286. MAX_FRAME_COUNT - 1 : (sde_crtc->fps_info.next_time_index - 1);
  287. diff_us = (u64)ktime_us_delta(current_time,
  288. sde_crtc->fps_info.time_buf[current_time_index]);
  289. if (diff_us >= sde_crtc->fps_info.fps_periodic_duration) {
  290. /* Multiplying with 10 to get fps in floating point */
  291. fps = (frame_count) * DEFAULT_FPS_PERIOD_1_SEC * 10;
  292. do_div(fps, diff_us);
  293. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  294. }
  295. }
  296. fps_int = (uint64_t) sde_crtc->fps_info.measured_fps;
  297. fps_decimal = do_div(fps_int, 10);
  298. return scnprintf(buf, PAGE_SIZE,
  299. "fps: %d.%d duration:%d frame_count:%lld\n", fps_int, fps_decimal,
  300. sde_crtc->fps_info.fps_periodic_duration, frame_count);
  301. }
  302. static ssize_t vsync_event_show(struct device *device,
  303. struct device_attribute *attr, char *buf)
  304. {
  305. struct drm_crtc *crtc;
  306. struct sde_crtc *sde_crtc;
  307. if (!device || !buf) {
  308. SDE_ERROR("invalid input param(s)\n");
  309. return -EAGAIN;
  310. }
  311. crtc = dev_get_drvdata(device);
  312. sde_crtc = to_sde_crtc(crtc);
  313. return scnprintf(buf, PAGE_SIZE, "VSYNC=%llu\n",
  314. ktime_to_ns(sde_crtc->vblank_last_cb_time));
  315. }
  316. static DEVICE_ATTR_RO(vsync_event);
  317. static DEVICE_ATTR_RO(measured_fps);
  318. static DEVICE_ATTR_RW(fps_periodicity_ms);
  319. static struct attribute *sde_crtc_dev_attrs[] = {
  320. &dev_attr_vsync_event.attr,
  321. &dev_attr_measured_fps.attr,
  322. &dev_attr_fps_periodicity_ms.attr,
  323. NULL
  324. };
  325. static const struct attribute_group sde_crtc_attr_group = {
  326. .attrs = sde_crtc_dev_attrs,
  327. };
  328. static const struct attribute_group *sde_crtc_attr_groups[] = {
  329. &sde_crtc_attr_group,
  330. NULL,
  331. };
  332. static void sde_crtc_destroy(struct drm_crtc *crtc)
  333. {
  334. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  335. SDE_DEBUG("\n");
  336. if (!crtc)
  337. return;
  338. if (sde_crtc->vsync_event_sf)
  339. sysfs_put(sde_crtc->vsync_event_sf);
  340. if (sde_crtc->sysfs_dev)
  341. device_unregister(sde_crtc->sysfs_dev);
  342. if (sde_crtc->blob_info)
  343. drm_property_blob_put(sde_crtc->blob_info);
  344. msm_property_destroy(&sde_crtc->property_info);
  345. sde_cp_crtc_destroy_properties(crtc);
  346. sde_fence_deinit(sde_crtc->output_fence);
  347. _sde_crtc_deinit_events(sde_crtc);
  348. drm_crtc_cleanup(crtc);
  349. mutex_destroy(&sde_crtc->crtc_lock);
  350. kfree(sde_crtc);
  351. }
  352. static bool sde_crtc_mode_fixup(struct drm_crtc *crtc,
  353. const struct drm_display_mode *mode,
  354. struct drm_display_mode *adjusted_mode)
  355. {
  356. SDE_DEBUG("\n");
  357. sde_cp_mode_switch_prop_dirty(crtc);
  358. if ((msm_is_mode_seamless(adjusted_mode) ||
  359. (msm_is_mode_seamless_vrr(adjusted_mode) ||
  360. msm_is_mode_seamless_dyn_clk(adjusted_mode))) &&
  361. (!crtc->enabled)) {
  362. SDE_ERROR("crtc state prevents seamless transition\n");
  363. return false;
  364. }
  365. return true;
  366. }
  367. static void _sde_crtc_setup_blend_cfg(struct sde_crtc_mixer *mixer,
  368. struct sde_plane_state *pstate, struct sde_format *format)
  369. {
  370. uint32_t blend_op, fg_alpha, bg_alpha;
  371. uint32_t blend_type;
  372. struct sde_hw_mixer *lm = mixer->hw_lm;
  373. /* default to opaque blending */
  374. fg_alpha = sde_plane_get_property(pstate, PLANE_PROP_ALPHA);
  375. bg_alpha = 0xFF - fg_alpha;
  376. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST | SDE_BLEND_BG_ALPHA_BG_CONST;
  377. blend_type = sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP);
  378. SDE_DEBUG("blend type:0x%x blend alpha:0x%x\n", blend_type, fg_alpha);
  379. switch (blend_type) {
  380. case SDE_DRM_BLEND_OP_OPAQUE:
  381. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST |
  382. SDE_BLEND_BG_ALPHA_BG_CONST;
  383. break;
  384. case SDE_DRM_BLEND_OP_PREMULTIPLIED:
  385. if (format->alpha_enable) {
  386. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST |
  387. SDE_BLEND_BG_ALPHA_FG_PIXEL;
  388. if (fg_alpha != 0xff) {
  389. bg_alpha = fg_alpha;
  390. blend_op |= SDE_BLEND_BG_MOD_ALPHA |
  391. SDE_BLEND_BG_INV_MOD_ALPHA;
  392. } else {
  393. blend_op |= SDE_BLEND_BG_INV_ALPHA;
  394. }
  395. }
  396. break;
  397. case SDE_DRM_BLEND_OP_COVERAGE:
  398. if (format->alpha_enable) {
  399. blend_op = SDE_BLEND_FG_ALPHA_FG_PIXEL |
  400. SDE_BLEND_BG_ALPHA_FG_PIXEL;
  401. if (fg_alpha != 0xff) {
  402. bg_alpha = fg_alpha;
  403. blend_op |= SDE_BLEND_FG_MOD_ALPHA |
  404. SDE_BLEND_BG_MOD_ALPHA |
  405. SDE_BLEND_BG_INV_MOD_ALPHA;
  406. } else {
  407. blend_op |= SDE_BLEND_BG_INV_ALPHA;
  408. }
  409. }
  410. break;
  411. default:
  412. /* do nothing */
  413. break;
  414. }
  415. lm->ops.setup_blend_config(lm, pstate->stage, fg_alpha,
  416. bg_alpha, blend_op);
  417. SDE_DEBUG(
  418. "format: %4.4s, alpha_enable %u fg alpha:0x%x bg alpha:0x%x blend_op:0x%x\n",
  419. (char *) &format->base.pixel_format,
  420. format->alpha_enable, fg_alpha, bg_alpha, blend_op);
  421. }
  422. static void _sde_crtc_setup_dim_layer_cfg(struct drm_crtc *crtc,
  423. struct sde_crtc *sde_crtc, struct sde_crtc_mixer *mixer,
  424. struct sde_hw_dim_layer *dim_layer)
  425. {
  426. struct sde_crtc_state *cstate;
  427. struct sde_hw_mixer *lm;
  428. struct sde_hw_dim_layer split_dim_layer;
  429. int i;
  430. if (!dim_layer->rect.w || !dim_layer->rect.h) {
  431. SDE_DEBUG("empty dim_layer\n");
  432. return;
  433. }
  434. cstate = to_sde_crtc_state(crtc->state);
  435. SDE_DEBUG("dim_layer - flags:%d, stage:%d\n",
  436. dim_layer->flags, dim_layer->stage);
  437. split_dim_layer.stage = dim_layer->stage;
  438. split_dim_layer.color_fill = dim_layer->color_fill;
  439. /*
  440. * traverse through the layer mixers attached to crtc and find the
  441. * intersecting dim layer rect in each LM and program accordingly.
  442. */
  443. for (i = 0; i < sde_crtc->num_mixers; i++) {
  444. split_dim_layer.flags = dim_layer->flags;
  445. sde_kms_rect_intersect(&cstate->lm_roi[i], &dim_layer->rect,
  446. &split_dim_layer.rect);
  447. if (sde_kms_rect_is_null(&split_dim_layer.rect)) {
  448. /*
  449. * no extra programming required for non-intersecting
  450. * layer mixers with INCLUSIVE dim layer
  451. */
  452. if (split_dim_layer.flags & SDE_DRM_DIM_LAYER_INCLUSIVE)
  453. continue;
  454. /*
  455. * program the other non-intersecting layer mixers with
  456. * INCLUSIVE dim layer of full size for uniformity
  457. * with EXCLUSIVE dim layer config.
  458. */
  459. split_dim_layer.flags &= ~SDE_DRM_DIM_LAYER_EXCLUSIVE;
  460. split_dim_layer.flags |= SDE_DRM_DIM_LAYER_INCLUSIVE;
  461. memcpy(&split_dim_layer.rect, &cstate->lm_bounds[i],
  462. sizeof(split_dim_layer.rect));
  463. } else {
  464. split_dim_layer.rect.x =
  465. split_dim_layer.rect.x -
  466. cstate->lm_roi[i].x;
  467. split_dim_layer.rect.y =
  468. split_dim_layer.rect.y -
  469. cstate->lm_roi[i].y;
  470. }
  471. SDE_EVT32_VERBOSE(DRMID(crtc),
  472. cstate->lm_roi[i].x,
  473. cstate->lm_roi[i].y,
  474. cstate->lm_roi[i].w,
  475. cstate->lm_roi[i].h,
  476. dim_layer->rect.x,
  477. dim_layer->rect.y,
  478. dim_layer->rect.w,
  479. dim_layer->rect.h,
  480. split_dim_layer.rect.x,
  481. split_dim_layer.rect.y,
  482. split_dim_layer.rect.w,
  483. split_dim_layer.rect.h);
  484. SDE_DEBUG("split_dim_layer - LM:%d, rect:{%d,%d,%d,%d}}\n",
  485. i, split_dim_layer.rect.x, split_dim_layer.rect.y,
  486. split_dim_layer.rect.w, split_dim_layer.rect.h);
  487. lm = mixer[i].hw_lm;
  488. mixer[i].mixer_op_mode |= 1 << split_dim_layer.stage;
  489. lm->ops.setup_dim_layer(lm, &split_dim_layer);
  490. }
  491. }
  492. void sde_crtc_get_crtc_roi(struct drm_crtc_state *state,
  493. const struct sde_rect **crtc_roi)
  494. {
  495. struct sde_crtc_state *crtc_state;
  496. if (!state || !crtc_roi)
  497. return;
  498. crtc_state = to_sde_crtc_state(state);
  499. *crtc_roi = &crtc_state->crtc_roi;
  500. }
  501. bool sde_crtc_is_crtc_roi_dirty(struct drm_crtc_state *state)
  502. {
  503. struct sde_crtc_state *cstate;
  504. struct sde_crtc *sde_crtc;
  505. if (!state || !state->crtc)
  506. return false;
  507. sde_crtc = to_sde_crtc(state->crtc);
  508. cstate = to_sde_crtc_state(state);
  509. return msm_property_is_dirty(&sde_crtc->property_info,
  510. &cstate->property_state, CRTC_PROP_ROI_V1);
  511. }
  512. static int _sde_crtc_set_roi_v1(struct drm_crtc_state *state,
  513. void __user *usr_ptr)
  514. {
  515. struct drm_crtc *crtc;
  516. struct sde_crtc_state *cstate;
  517. struct sde_drm_roi_v1 roi_v1;
  518. int i;
  519. if (!state) {
  520. SDE_ERROR("invalid args\n");
  521. return -EINVAL;
  522. }
  523. cstate = to_sde_crtc_state(state);
  524. crtc = cstate->base.crtc;
  525. memset(&cstate->user_roi_list, 0, sizeof(cstate->user_roi_list));
  526. if (!usr_ptr) {
  527. SDE_DEBUG("crtc%d: rois cleared\n", DRMID(crtc));
  528. return 0;
  529. }
  530. if (copy_from_user(&roi_v1, usr_ptr, sizeof(roi_v1))) {
  531. SDE_ERROR("crtc%d: failed to copy roi_v1 data\n", DRMID(crtc));
  532. return -EINVAL;
  533. }
  534. SDE_DEBUG("crtc%d: num_rects %d\n", DRMID(crtc), roi_v1.num_rects);
  535. if (roi_v1.num_rects == 0) {
  536. SDE_DEBUG("crtc%d: rois cleared\n", DRMID(crtc));
  537. return 0;
  538. }
  539. if (roi_v1.num_rects > SDE_MAX_ROI_V1) {
  540. SDE_ERROR("crtc%d: too many rects specified: %d\n", DRMID(crtc),
  541. roi_v1.num_rects);
  542. return -EINVAL;
  543. }
  544. cstate->user_roi_list.num_rects = roi_v1.num_rects;
  545. for (i = 0; i < roi_v1.num_rects; ++i) {
  546. cstate->user_roi_list.roi[i] = roi_v1.roi[i];
  547. SDE_DEBUG("crtc%d: roi%d: roi (%d,%d) (%d,%d)\n",
  548. DRMID(crtc), i,
  549. cstate->user_roi_list.roi[i].x1,
  550. cstate->user_roi_list.roi[i].y1,
  551. cstate->user_roi_list.roi[i].x2,
  552. cstate->user_roi_list.roi[i].y2);
  553. SDE_EVT32_VERBOSE(DRMID(crtc),
  554. cstate->user_roi_list.roi[i].x1,
  555. cstate->user_roi_list.roi[i].y1,
  556. cstate->user_roi_list.roi[i].x2,
  557. cstate->user_roi_list.roi[i].y2);
  558. }
  559. return 0;
  560. }
  561. static bool _sde_crtc_setup_is_3dmux_dsc(struct drm_crtc_state *state)
  562. {
  563. int i;
  564. struct sde_crtc_state *cstate;
  565. bool is_3dmux_dsc = false;
  566. cstate = to_sde_crtc_state(state);
  567. for (i = 0; i < cstate->num_connectors; i++) {
  568. struct drm_connector *conn = cstate->connectors[i];
  569. if (sde_connector_get_topology_name(conn) ==
  570. SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC)
  571. is_3dmux_dsc = true;
  572. }
  573. return is_3dmux_dsc;
  574. }
  575. static int _sde_crtc_set_crtc_roi(struct drm_crtc *crtc,
  576. struct drm_crtc_state *state)
  577. {
  578. struct drm_connector *conn;
  579. struct drm_connector_state *conn_state;
  580. struct sde_crtc *sde_crtc;
  581. struct sde_crtc_state *crtc_state;
  582. struct sde_rect *crtc_roi;
  583. struct msm_mode_info mode_info;
  584. int i = 0;
  585. int rc;
  586. bool is_crtc_roi_dirty;
  587. bool is_any_conn_roi_dirty;
  588. if (!crtc || !state)
  589. return -EINVAL;
  590. sde_crtc = to_sde_crtc(crtc);
  591. crtc_state = to_sde_crtc_state(state);
  592. crtc_roi = &crtc_state->crtc_roi;
  593. is_crtc_roi_dirty = sde_crtc_is_crtc_roi_dirty(state);
  594. is_any_conn_roi_dirty = false;
  595. for_each_new_connector_in_state(state->state, conn, conn_state, i) {
  596. struct sde_connector *sde_conn;
  597. struct sde_connector_state *sde_conn_state;
  598. struct sde_rect conn_roi;
  599. if (!conn_state || conn_state->crtc != crtc)
  600. continue;
  601. rc = sde_connector_state_get_mode_info(conn_state, &mode_info);
  602. if (rc) {
  603. SDE_ERROR("failed to get mode info\n");
  604. return -EINVAL;
  605. }
  606. sde_conn = to_sde_connector(conn_state->connector);
  607. sde_conn_state = to_sde_connector_state(conn_state);
  608. is_any_conn_roi_dirty = is_any_conn_roi_dirty ||
  609. msm_property_is_dirty(
  610. &sde_conn->property_info,
  611. &sde_conn_state->property_state,
  612. CONNECTOR_PROP_ROI_V1);
  613. if (!mode_info.roi_caps.enabled)
  614. continue;
  615. /*
  616. * current driver only supports same connector and crtc size,
  617. * but if support for different sizes is added, driver needs
  618. * to check the connector roi here to make sure is full screen
  619. * for dsc 3d-mux topology that doesn't support partial update.
  620. */
  621. if (memcmp(&sde_conn_state->rois, &crtc_state->user_roi_list,
  622. sizeof(crtc_state->user_roi_list))) {
  623. SDE_ERROR("%s: crtc -> conn roi scaling unsupported\n",
  624. sde_crtc->name);
  625. return -EINVAL;
  626. }
  627. sde_kms_rect_merge_rectangles(&sde_conn_state->rois, &conn_roi);
  628. SDE_DEBUG("conn_roi x:%u, y:%u, w:%u, h:%u\n",
  629. conn_roi.x, conn_roi.y,
  630. conn_roi.w, conn_roi.h);
  631. SDE_EVT32_VERBOSE(DRMID(crtc), DRMID(conn),
  632. conn_roi.x, conn_roi.y,
  633. conn_roi.w, conn_roi.h);
  634. }
  635. /*
  636. * Check against CRTC ROI and Connector ROI not being updated together.
  637. * This restriction should be relaxed when Connector ROI scaling is
  638. * supported.
  639. */
  640. if (is_any_conn_roi_dirty != is_crtc_roi_dirty) {
  641. SDE_ERROR("connector/crtc rois not updated together\n");
  642. return -EINVAL;
  643. }
  644. sde_kms_rect_merge_rectangles(&crtc_state->user_roi_list, crtc_roi);
  645. /* clear the ROI to null if it matches full screen anyways */
  646. if (crtc_roi->x == 0 && crtc_roi->y == 0 &&
  647. crtc_roi->w == state->adjusted_mode.hdisplay &&
  648. crtc_roi->h == state->adjusted_mode.vdisplay)
  649. memset(crtc_roi, 0, sizeof(*crtc_roi));
  650. SDE_DEBUG("%s: crtc roi (%d,%d,%d,%d)\n", sde_crtc->name,
  651. crtc_roi->x, crtc_roi->y, crtc_roi->w, crtc_roi->h);
  652. SDE_EVT32_VERBOSE(DRMID(crtc), crtc_roi->x, crtc_roi->y, crtc_roi->w,
  653. crtc_roi->h);
  654. return 0;
  655. }
  656. static int _sde_crtc_check_autorefresh(struct drm_crtc *crtc,
  657. struct drm_crtc_state *state)
  658. {
  659. struct sde_crtc *sde_crtc;
  660. struct sde_crtc_state *crtc_state;
  661. struct drm_connector *conn;
  662. struct drm_connector_state *conn_state;
  663. int i;
  664. if (!crtc || !state)
  665. return -EINVAL;
  666. sde_crtc = to_sde_crtc(crtc);
  667. crtc_state = to_sde_crtc_state(state);
  668. if (sde_kms_rect_is_null(&crtc_state->crtc_roi))
  669. return 0;
  670. /* partial update active, check if autorefresh is also requested */
  671. for_each_new_connector_in_state(state->state, conn, conn_state, i) {
  672. uint64_t autorefresh;
  673. if (!conn_state || conn_state->crtc != crtc)
  674. continue;
  675. autorefresh = sde_connector_get_property(conn_state,
  676. CONNECTOR_PROP_AUTOREFRESH);
  677. if (autorefresh) {
  678. SDE_ERROR(
  679. "%s: autorefresh & partial crtc roi incompatible %llu\n",
  680. sde_crtc->name, autorefresh);
  681. return -EINVAL;
  682. }
  683. }
  684. return 0;
  685. }
  686. static int _sde_crtc_set_lm_roi(struct drm_crtc *crtc,
  687. struct drm_crtc_state *state, int lm_idx)
  688. {
  689. struct sde_crtc *sde_crtc;
  690. struct sde_crtc_state *crtc_state;
  691. const struct sde_rect *crtc_roi;
  692. const struct sde_rect *lm_bounds;
  693. struct sde_rect *lm_roi;
  694. if (!crtc || !state || lm_idx >= ARRAY_SIZE(crtc_state->lm_bounds))
  695. return -EINVAL;
  696. sde_crtc = to_sde_crtc(crtc);
  697. crtc_state = to_sde_crtc_state(state);
  698. crtc_roi = &crtc_state->crtc_roi;
  699. lm_bounds = &crtc_state->lm_bounds[lm_idx];
  700. lm_roi = &crtc_state->lm_roi[lm_idx];
  701. if (sde_kms_rect_is_null(crtc_roi))
  702. memcpy(lm_roi, lm_bounds, sizeof(*lm_roi));
  703. else
  704. sde_kms_rect_intersect(crtc_roi, lm_bounds, lm_roi);
  705. SDE_DEBUG("%s: lm%d roi (%d,%d,%d,%d)\n", sde_crtc->name, lm_idx,
  706. lm_roi->x, lm_roi->y, lm_roi->w, lm_roi->h);
  707. /*
  708. * partial update is not supported with 3dmux dsc or dest scaler.
  709. * hence, crtc roi must match the mixer dimensions.
  710. */
  711. if (crtc_state->num_ds_enabled ||
  712. _sde_crtc_setup_is_3dmux_dsc(state)) {
  713. if (memcmp(lm_roi, lm_bounds, sizeof(struct sde_rect))) {
  714. SDE_ERROR("Unsupported: Dest scaler/3d mux DSC + PU\n");
  715. return -EINVAL;
  716. }
  717. }
  718. /* if any dimension is zero, clear all dimensions for clarity */
  719. if (sde_kms_rect_is_null(lm_roi))
  720. memset(lm_roi, 0, sizeof(*lm_roi));
  721. return 0;
  722. }
  723. static u32 _sde_crtc_get_displays_affected(struct drm_crtc *crtc,
  724. struct drm_crtc_state *state)
  725. {
  726. struct sde_crtc *sde_crtc;
  727. struct sde_crtc_state *crtc_state;
  728. u32 disp_bitmask = 0;
  729. int i;
  730. if (!crtc || !state) {
  731. pr_err("Invalid crtc or state\n");
  732. return 0;
  733. }
  734. sde_crtc = to_sde_crtc(crtc);
  735. crtc_state = to_sde_crtc_state(state);
  736. /* pingpong split: one ROI, one LM, two physical displays */
  737. if (crtc_state->is_ppsplit) {
  738. u32 lm_split_width = crtc_state->lm_bounds[0].w / 2;
  739. struct sde_rect *roi = &crtc_state->lm_roi[0];
  740. if (sde_kms_rect_is_null(roi))
  741. disp_bitmask = 0;
  742. else if ((u32)roi->x + (u32)roi->w <= lm_split_width)
  743. disp_bitmask = BIT(0); /* left only */
  744. else if (roi->x >= lm_split_width)
  745. disp_bitmask = BIT(1); /* right only */
  746. else
  747. disp_bitmask = BIT(0) | BIT(1); /* left and right */
  748. } else {
  749. for (i = 0; i < sde_crtc->num_mixers; i++) {
  750. if (!sde_kms_rect_is_null(&crtc_state->lm_roi[i]))
  751. disp_bitmask |= BIT(i);
  752. }
  753. }
  754. SDE_DEBUG("affected displays 0x%x\n", disp_bitmask);
  755. return disp_bitmask;
  756. }
  757. static int _sde_crtc_check_rois_centered_and_symmetric(struct drm_crtc *crtc,
  758. struct drm_crtc_state *state)
  759. {
  760. struct sde_crtc *sde_crtc;
  761. struct sde_crtc_state *crtc_state;
  762. const struct sde_rect *roi[CRTC_DUAL_MIXERS];
  763. if (!crtc || !state)
  764. return -EINVAL;
  765. sde_crtc = to_sde_crtc(crtc);
  766. crtc_state = to_sde_crtc_state(state);
  767. if (sde_crtc->num_mixers > CRTC_DUAL_MIXERS) {
  768. SDE_ERROR("%s: unsupported number of mixers: %d\n",
  769. sde_crtc->name, sde_crtc->num_mixers);
  770. return -EINVAL;
  771. }
  772. /*
  773. * If using pingpong split: one ROI, one LM, two physical displays
  774. * then the ROI must be centered on the panel split boundary and
  775. * be of equal width across the split.
  776. */
  777. if (crtc_state->is_ppsplit) {
  778. u16 panel_split_width;
  779. u32 display_mask;
  780. roi[0] = &crtc_state->lm_roi[0];
  781. if (sde_kms_rect_is_null(roi[0]))
  782. return 0;
  783. display_mask = _sde_crtc_get_displays_affected(crtc, state);
  784. if (display_mask != (BIT(0) | BIT(1)))
  785. return 0;
  786. panel_split_width = crtc_state->lm_bounds[0].w / 2;
  787. if (roi[0]->x + roi[0]->w / 2 != panel_split_width) {
  788. SDE_ERROR("%s: roi x %d w %d split %d\n",
  789. sde_crtc->name, roi[0]->x, roi[0]->w,
  790. panel_split_width);
  791. return -EINVAL;
  792. }
  793. return 0;
  794. }
  795. /*
  796. * On certain HW, if using 2 LM, ROIs must be split evenly between the
  797. * LMs and be of equal width.
  798. */
  799. if (sde_crtc->num_mixers < 2)
  800. return 0;
  801. roi[0] = &crtc_state->lm_roi[0];
  802. roi[1] = &crtc_state->lm_roi[1];
  803. /* if one of the roi is null it's a left/right-only update */
  804. if (sde_kms_rect_is_null(roi[0]) || sde_kms_rect_is_null(roi[1]))
  805. return 0;
  806. /* check lm rois are equal width & first roi ends at 2nd roi */
  807. if (roi[0]->x + roi[0]->w != roi[1]->x || roi[0]->w != roi[1]->w) {
  808. SDE_ERROR(
  809. "%s: rois not centered and symmetric: roi0 x %d w %d roi1 x %d w %d\n",
  810. sde_crtc->name, roi[0]->x, roi[0]->w,
  811. roi[1]->x, roi[1]->w);
  812. return -EINVAL;
  813. }
  814. return 0;
  815. }
  816. static int _sde_crtc_check_planes_within_crtc_roi(struct drm_crtc *crtc,
  817. struct drm_crtc_state *state)
  818. {
  819. struct sde_crtc *sde_crtc;
  820. struct sde_crtc_state *crtc_state;
  821. const struct sde_rect *crtc_roi;
  822. const struct drm_plane_state *pstate;
  823. struct drm_plane *plane;
  824. if (!crtc || !state)
  825. return -EINVAL;
  826. /*
  827. * Reject commit if a Plane CRTC destination coordinates fall outside
  828. * the partial CRTC ROI. LM output is determined via connector ROIs,
  829. * if they are specified, not Plane CRTC ROIs.
  830. */
  831. sde_crtc = to_sde_crtc(crtc);
  832. crtc_state = to_sde_crtc_state(state);
  833. crtc_roi = &crtc_state->crtc_roi;
  834. if (sde_kms_rect_is_null(crtc_roi))
  835. return 0;
  836. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  837. struct sde_rect plane_roi, intersection;
  838. if (IS_ERR_OR_NULL(pstate)) {
  839. int rc = PTR_ERR(pstate);
  840. SDE_ERROR("%s: failed to get plane%d state, %d\n",
  841. sde_crtc->name, plane->base.id, rc);
  842. return rc;
  843. }
  844. plane_roi.x = pstate->crtc_x;
  845. plane_roi.y = pstate->crtc_y;
  846. plane_roi.w = pstate->crtc_w;
  847. plane_roi.h = pstate->crtc_h;
  848. sde_kms_rect_intersect(crtc_roi, &plane_roi, &intersection);
  849. if (!sde_kms_rect_is_equal(&plane_roi, &intersection)) {
  850. SDE_ERROR(
  851. "%s: plane%d crtc roi (%d,%d,%d,%d) outside crtc roi (%d,%d,%d,%d)\n",
  852. sde_crtc->name, plane->base.id,
  853. plane_roi.x, plane_roi.y,
  854. plane_roi.w, plane_roi.h,
  855. crtc_roi->x, crtc_roi->y,
  856. crtc_roi->w, crtc_roi->h);
  857. return -E2BIG;
  858. }
  859. }
  860. return 0;
  861. }
  862. static int _sde_crtc_check_rois(struct drm_crtc *crtc,
  863. struct drm_crtc_state *state)
  864. {
  865. struct sde_crtc *sde_crtc;
  866. struct sde_crtc_state *sde_crtc_state;
  867. struct msm_mode_info mode_info;
  868. int rc, lm_idx, i;
  869. if (!crtc || !state)
  870. return -EINVAL;
  871. memset(&mode_info, 0, sizeof(mode_info));
  872. sde_crtc = to_sde_crtc(crtc);
  873. sde_crtc_state = to_sde_crtc_state(state);
  874. /*
  875. * check connector array cached at modeset time since incoming atomic
  876. * state may not include any connectors if they aren't modified
  877. */
  878. for (i = 0; i < sde_crtc_state->num_connectors; i++) {
  879. struct drm_connector *conn = sde_crtc_state->connectors[i];
  880. if (!conn || !conn->state)
  881. continue;
  882. rc = sde_connector_state_get_mode_info(conn->state, &mode_info);
  883. if (rc) {
  884. SDE_ERROR("failed to get mode info\n");
  885. return -EINVAL;
  886. }
  887. if (!mode_info.roi_caps.enabled)
  888. continue;
  889. if (sde_crtc_state->user_roi_list.num_rects >
  890. mode_info.roi_caps.num_roi) {
  891. SDE_ERROR("roi count is exceeding limit, %d > %d\n",
  892. sde_crtc_state->user_roi_list.num_rects,
  893. mode_info.roi_caps.num_roi);
  894. return -E2BIG;
  895. }
  896. rc = _sde_crtc_set_crtc_roi(crtc, state);
  897. if (rc)
  898. return rc;
  899. rc = _sde_crtc_check_autorefresh(crtc, state);
  900. if (rc)
  901. return rc;
  902. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) {
  903. rc = _sde_crtc_set_lm_roi(crtc, state, lm_idx);
  904. if (rc)
  905. return rc;
  906. }
  907. rc = _sde_crtc_check_rois_centered_and_symmetric(crtc, state);
  908. if (rc)
  909. return rc;
  910. rc = _sde_crtc_check_planes_within_crtc_roi(crtc, state);
  911. if (rc)
  912. return rc;
  913. }
  914. return 0;
  915. }
  916. static void _sde_crtc_program_lm_output_roi(struct drm_crtc *crtc)
  917. {
  918. struct sde_crtc *sde_crtc;
  919. struct sde_crtc_state *crtc_state;
  920. const struct sde_rect *lm_roi;
  921. struct sde_hw_mixer *hw_lm;
  922. int lm_idx, lm_horiz_position;
  923. if (!crtc)
  924. return;
  925. sde_crtc = to_sde_crtc(crtc);
  926. crtc_state = to_sde_crtc_state(crtc->state);
  927. lm_horiz_position = 0;
  928. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) {
  929. struct sde_hw_mixer_cfg cfg;
  930. lm_roi = &crtc_state->lm_roi[lm_idx];
  931. hw_lm = sde_crtc->mixers[lm_idx].hw_lm;
  932. SDE_EVT32(DRMID(crtc_state->base.crtc), lm_idx,
  933. lm_roi->x, lm_roi->y, lm_roi->w, lm_roi->h);
  934. if (sde_kms_rect_is_null(lm_roi))
  935. continue;
  936. hw_lm->cfg.out_width = lm_roi->w;
  937. hw_lm->cfg.out_height = lm_roi->h;
  938. hw_lm->cfg.right_mixer = lm_horiz_position;
  939. cfg.out_width = lm_roi->w;
  940. cfg.out_height = lm_roi->h;
  941. cfg.right_mixer = lm_horiz_position++;
  942. cfg.flags = 0;
  943. hw_lm->ops.setup_mixer_out(hw_lm, &cfg);
  944. }
  945. }
  946. struct plane_state {
  947. struct sde_plane_state *sde_pstate;
  948. const struct drm_plane_state *drm_pstate;
  949. int stage;
  950. u32 pipe_id;
  951. };
  952. static int pstate_cmp(const void *a, const void *b)
  953. {
  954. struct plane_state *pa = (struct plane_state *)a;
  955. struct plane_state *pb = (struct plane_state *)b;
  956. int rc = 0;
  957. int pa_zpos, pb_zpos;
  958. pa_zpos = sde_plane_get_property(pa->sde_pstate, PLANE_PROP_ZPOS);
  959. pb_zpos = sde_plane_get_property(pb->sde_pstate, PLANE_PROP_ZPOS);
  960. if (pa_zpos != pb_zpos)
  961. rc = pa_zpos - pb_zpos;
  962. else
  963. rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x;
  964. return rc;
  965. }
  966. /*
  967. * validate and set source split:
  968. * use pstates sorted by stage to check planes on same stage
  969. * we assume that all pipes are in source split so its valid to compare
  970. * without taking into account left/right mixer placement
  971. */
  972. static int _sde_crtc_validate_src_split_order(struct drm_crtc *crtc,
  973. struct plane_state *pstates, int cnt)
  974. {
  975. struct plane_state *prv_pstate, *cur_pstate;
  976. struct sde_rect left_rect, right_rect;
  977. struct sde_kms *sde_kms;
  978. int32_t left_pid, right_pid;
  979. int32_t stage;
  980. int i, rc = 0;
  981. sde_kms = _sde_crtc_get_kms(crtc);
  982. if (!sde_kms || !sde_kms->catalog) {
  983. SDE_ERROR("invalid parameters\n");
  984. return -EINVAL;
  985. }
  986. for (i = 1; i < cnt; i++) {
  987. prv_pstate = &pstates[i - 1];
  988. cur_pstate = &pstates[i];
  989. if (prv_pstate->stage != cur_pstate->stage)
  990. continue;
  991. stage = cur_pstate->stage;
  992. left_pid = prv_pstate->sde_pstate->base.plane->base.id;
  993. POPULATE_RECT(&left_rect, prv_pstate->drm_pstate->crtc_x,
  994. prv_pstate->drm_pstate->crtc_y,
  995. prv_pstate->drm_pstate->crtc_w,
  996. prv_pstate->drm_pstate->crtc_h, false);
  997. right_pid = cur_pstate->sde_pstate->base.plane->base.id;
  998. POPULATE_RECT(&right_rect, cur_pstate->drm_pstate->crtc_x,
  999. cur_pstate->drm_pstate->crtc_y,
  1000. cur_pstate->drm_pstate->crtc_w,
  1001. cur_pstate->drm_pstate->crtc_h, false);
  1002. if (right_rect.x < left_rect.x) {
  1003. swap(left_pid, right_pid);
  1004. swap(left_rect, right_rect);
  1005. swap(prv_pstate, cur_pstate);
  1006. }
  1007. /*
  1008. * - planes are enumerated in pipe-priority order such that
  1009. * planes with lower drm_id must be left-most in a shared
  1010. * blend-stage when using source split.
  1011. * - planes in source split must be contiguous in width
  1012. * - planes in source split must have same dest yoff and height
  1013. */
  1014. if ((right_pid < left_pid) &&
  1015. !sde_kms->catalog->pipe_order_type) {
  1016. SDE_ERROR(
  1017. "invalid src split cfg, stage:%d left:%d right:%d\n",
  1018. stage, left_pid, right_pid);
  1019. return -EINVAL;
  1020. } else if (right_rect.x != (left_rect.x + left_rect.w)) {
  1021. SDE_ERROR(
  1022. "invalid coordinates, stage:%d l:%d-%d r:%d-%d\n",
  1023. stage, left_rect.x, left_rect.w,
  1024. right_rect.x, right_rect.w);
  1025. return -EINVAL;
  1026. } else if ((left_rect.y != right_rect.y) ||
  1027. (left_rect.h != right_rect.h)) {
  1028. SDE_ERROR(
  1029. "stage:%d invalid yoff/ht: l_yxh:%dx%d r_yxh:%dx%d\n",
  1030. stage, left_rect.y, left_rect.h,
  1031. right_rect.y, right_rect.h);
  1032. return -EINVAL;
  1033. }
  1034. }
  1035. return rc;
  1036. }
  1037. static void _sde_crtc_set_src_split_order(struct drm_crtc *crtc,
  1038. struct plane_state *pstates, int cnt)
  1039. {
  1040. struct plane_state *prv_pstate, *cur_pstate, *nxt_pstate;
  1041. struct sde_kms *sde_kms;
  1042. struct sde_rect left_rect, right_rect;
  1043. int32_t left_pid, right_pid;
  1044. int32_t stage;
  1045. int i;
  1046. sde_kms = _sde_crtc_get_kms(crtc);
  1047. if (!sde_kms || !sde_kms->catalog) {
  1048. SDE_ERROR("invalid parameters\n");
  1049. return;
  1050. }
  1051. if (!sde_kms->catalog->pipe_order_type)
  1052. return;
  1053. for (i = 0; i < cnt; i++) {
  1054. prv_pstate = (i > 0) ? &pstates[i - 1] : NULL;
  1055. cur_pstate = &pstates[i];
  1056. nxt_pstate = ((i + 1) < cnt) ? &pstates[i + 1] : NULL;
  1057. if ((!prv_pstate) || (prv_pstate->stage != cur_pstate->stage)) {
  1058. /*
  1059. * reset if prv or nxt pipes are not in the same stage
  1060. * as the cur pipe
  1061. */
  1062. if ((!nxt_pstate)
  1063. || (nxt_pstate->stage != cur_pstate->stage))
  1064. cur_pstate->sde_pstate->pipe_order_flags = 0;
  1065. continue;
  1066. }
  1067. stage = cur_pstate->stage;
  1068. left_pid = prv_pstate->sde_pstate->base.plane->base.id;
  1069. POPULATE_RECT(&left_rect, prv_pstate->drm_pstate->crtc_x,
  1070. prv_pstate->drm_pstate->crtc_y,
  1071. prv_pstate->drm_pstate->crtc_w,
  1072. prv_pstate->drm_pstate->crtc_h, false);
  1073. right_pid = cur_pstate->sde_pstate->base.plane->base.id;
  1074. POPULATE_RECT(&right_rect, cur_pstate->drm_pstate->crtc_x,
  1075. cur_pstate->drm_pstate->crtc_y,
  1076. cur_pstate->drm_pstate->crtc_w,
  1077. cur_pstate->drm_pstate->crtc_h, false);
  1078. if (right_rect.x < left_rect.x) {
  1079. swap(left_pid, right_pid);
  1080. swap(left_rect, right_rect);
  1081. swap(prv_pstate, cur_pstate);
  1082. }
  1083. cur_pstate->sde_pstate->pipe_order_flags = SDE_SSPP_RIGHT;
  1084. prv_pstate->sde_pstate->pipe_order_flags = 0;
  1085. }
  1086. for (i = 0; i < cnt; i++) {
  1087. cur_pstate = &pstates[i];
  1088. sde_plane_setup_src_split_order(
  1089. cur_pstate->drm_pstate->plane,
  1090. cur_pstate->sde_pstate->multirect_index,
  1091. cur_pstate->sde_pstate->pipe_order_flags);
  1092. }
  1093. }
  1094. static void _sde_crtc_setup_blend_cfg_by_stage(struct sde_crtc_mixer *mixer,
  1095. int num_mixers, struct plane_state *pstates, int cnt)
  1096. {
  1097. int i, lm_idx;
  1098. struct sde_format *format;
  1099. bool blend_stage[SDE_STAGE_MAX] = { false };
  1100. u32 blend_type;
  1101. for (i = cnt - 1; i >= 0; i--) {
  1102. blend_type = sde_plane_get_property(pstates[i].sde_pstate,
  1103. PLANE_PROP_BLEND_OP);
  1104. /* stage has already been programmed or BLEND_OP_SKIP type */
  1105. if (blend_stage[pstates[i].sde_pstate->stage] ||
  1106. blend_type == SDE_DRM_BLEND_OP_SKIP)
  1107. continue;
  1108. for (lm_idx = 0; lm_idx < num_mixers; lm_idx++) {
  1109. format = to_sde_format(msm_framebuffer_format(
  1110. pstates[i].sde_pstate->base.fb));
  1111. if (!format) {
  1112. SDE_ERROR("invalid format\n");
  1113. return;
  1114. }
  1115. _sde_crtc_setup_blend_cfg(mixer + lm_idx,
  1116. pstates[i].sde_pstate, format);
  1117. blend_stage[pstates[i].sde_pstate->stage] = true;
  1118. }
  1119. }
  1120. }
  1121. static void _sde_crtc_blend_setup_mixer(struct drm_crtc *crtc,
  1122. struct drm_crtc_state *old_state, struct sde_crtc *sde_crtc,
  1123. struct sde_crtc_mixer *mixer)
  1124. {
  1125. struct drm_plane *plane;
  1126. struct drm_framebuffer *fb;
  1127. struct drm_plane_state *state;
  1128. struct sde_crtc_state *cstate;
  1129. struct sde_plane_state *pstate = NULL;
  1130. struct plane_state *pstates = NULL;
  1131. struct sde_format *format;
  1132. struct sde_hw_ctl *ctl;
  1133. struct sde_hw_mixer *lm;
  1134. struct sde_hw_stage_cfg *stage_cfg;
  1135. struct sde_rect plane_crtc_roi;
  1136. uint32_t stage_idx, lm_idx;
  1137. int zpos_cnt[SDE_STAGE_MAX + 1] = { 0 };
  1138. int i, mode, cnt = 0;
  1139. bool bg_alpha_enable = false, is_secure = false;
  1140. u32 blend_type;
  1141. DECLARE_BITMAP(fetch_active, SSPP_MAX);
  1142. if (!sde_crtc || !crtc->state || !mixer) {
  1143. SDE_ERROR("invalid sde_crtc or mixer\n");
  1144. return;
  1145. }
  1146. ctl = mixer->hw_ctl;
  1147. lm = mixer->hw_lm;
  1148. stage_cfg = &sde_crtc->stage_cfg;
  1149. cstate = to_sde_crtc_state(crtc->state);
  1150. pstates = kcalloc(SDE_PSTATES_MAX,
  1151. sizeof(struct plane_state), GFP_KERNEL);
  1152. if (!pstates)
  1153. return;
  1154. memset(fetch_active, 0, sizeof(fetch_active));
  1155. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1156. state = plane->state;
  1157. if (!state)
  1158. continue;
  1159. plane_crtc_roi.x = state->crtc_x;
  1160. plane_crtc_roi.y = state->crtc_y;
  1161. plane_crtc_roi.w = state->crtc_w;
  1162. plane_crtc_roi.h = state->crtc_h;
  1163. pstate = to_sde_plane_state(state);
  1164. fb = state->fb;
  1165. mode = sde_plane_get_property(pstate,
  1166. PLANE_PROP_FB_TRANSLATION_MODE);
  1167. is_secure = ((mode == SDE_DRM_FB_SEC) ||
  1168. (mode == SDE_DRM_FB_SEC_DIR_TRANS)) ?
  1169. true : false;
  1170. set_bit(sde_plane_pipe(plane), fetch_active);
  1171. sde_plane_ctl_flush(plane, ctl, true);
  1172. SDE_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n",
  1173. crtc->base.id,
  1174. pstate->stage,
  1175. plane->base.id,
  1176. sde_plane_pipe(plane) - SSPP_VIG0,
  1177. state->fb ? state->fb->base.id : -1);
  1178. format = to_sde_format(msm_framebuffer_format(pstate->base.fb));
  1179. if (!format) {
  1180. SDE_ERROR("invalid format\n");
  1181. goto end;
  1182. }
  1183. blend_type = sde_plane_get_property(pstate,
  1184. PLANE_PROP_BLEND_OP);
  1185. if (blend_type != SDE_DRM_BLEND_OP_SKIP) {
  1186. if (pstate->stage == SDE_STAGE_BASE &&
  1187. format->alpha_enable)
  1188. bg_alpha_enable = true;
  1189. SDE_EVT32(DRMID(crtc), DRMID(plane),
  1190. state->fb ? state->fb->base.id : -1,
  1191. state->src_x >> 16, state->src_y >> 16,
  1192. state->src_w >> 16, state->src_h >> 16,
  1193. state->crtc_x, state->crtc_y,
  1194. state->crtc_w, state->crtc_h,
  1195. pstate->rotation, is_secure);
  1196. stage_idx = zpos_cnt[pstate->stage]++;
  1197. stage_cfg->stage[pstate->stage][stage_idx] =
  1198. sde_plane_pipe(plane);
  1199. stage_cfg->multirect_index[pstate->stage][stage_idx] =
  1200. pstate->multirect_index;
  1201. SDE_EVT32(DRMID(crtc), DRMID(plane), stage_idx,
  1202. sde_plane_pipe(plane) - SSPP_VIG0,
  1203. pstate->stage,
  1204. pstate->multirect_index,
  1205. pstate->multirect_mode,
  1206. format->base.pixel_format,
  1207. fb ? fb->modifier : 0);
  1208. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers;
  1209. lm_idx++) {
  1210. if (bg_alpha_enable && !format->alpha_enable)
  1211. mixer[lm_idx].mixer_op_mode = 0;
  1212. else
  1213. mixer[lm_idx].mixer_op_mode |=
  1214. 1 << pstate->stage;
  1215. }
  1216. }
  1217. if (cnt >= SDE_PSTATES_MAX)
  1218. continue;
  1219. pstates[cnt].sde_pstate = pstate;
  1220. pstates[cnt].drm_pstate = state;
  1221. if (blend_type == SDE_DRM_BLEND_OP_SKIP)
  1222. pstates[cnt].stage = SKIP_STAGING_PIPE_ZPOS;
  1223. else
  1224. pstates[cnt].stage = sde_plane_get_property(
  1225. pstates[cnt].sde_pstate, PLANE_PROP_ZPOS);
  1226. pstates[cnt].pipe_id = sde_plane_pipe(plane);
  1227. cnt++;
  1228. }
  1229. /* blend config update */
  1230. _sde_crtc_setup_blend_cfg_by_stage(mixer, sde_crtc->num_mixers,
  1231. pstates, cnt);
  1232. if (ctl->ops.set_active_pipes)
  1233. ctl->ops.set_active_pipes(ctl, fetch_active);
  1234. sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
  1235. _sde_crtc_set_src_split_order(crtc, pstates, cnt);
  1236. if (lm && lm->ops.setup_dim_layer) {
  1237. cstate = to_sde_crtc_state(crtc->state);
  1238. if (test_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty)) {
  1239. for (i = 0; i < cstate->num_dim_layers; i++)
  1240. _sde_crtc_setup_dim_layer_cfg(crtc, sde_crtc,
  1241. mixer, &cstate->dim_layer[i]);
  1242. clear_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty);
  1243. }
  1244. }
  1245. _sde_crtc_program_lm_output_roi(crtc);
  1246. end:
  1247. kfree(pstates);
  1248. }
  1249. static void _sde_crtc_swap_mixers_for_right_partial_update(
  1250. struct drm_crtc *crtc)
  1251. {
  1252. struct sde_crtc *sde_crtc;
  1253. struct sde_crtc_state *cstate;
  1254. struct drm_encoder *drm_enc;
  1255. bool is_right_only;
  1256. bool encoder_in_dsc_merge = false;
  1257. if (!crtc || !crtc->state)
  1258. return;
  1259. sde_crtc = to_sde_crtc(crtc);
  1260. cstate = to_sde_crtc_state(crtc->state);
  1261. if (sde_crtc->num_mixers != CRTC_DUAL_MIXERS)
  1262. return;
  1263. drm_for_each_encoder_mask(drm_enc, crtc->dev,
  1264. crtc->state->encoder_mask) {
  1265. if (sde_encoder_is_dsc_merge(drm_enc)) {
  1266. encoder_in_dsc_merge = true;
  1267. break;
  1268. }
  1269. }
  1270. /**
  1271. * For right-only partial update with DSC merge, we swap LM0 & LM1.
  1272. * This is due to two reasons:
  1273. * - On 8996, there is a DSC HW requirement that in DSC Merge Mode,
  1274. * the left DSC must be used, right DSC cannot be used alone.
  1275. * For right-only partial update, this means swap layer mixers to map
  1276. * Left LM to Right INTF. On later HW this was relaxed.
  1277. * - In DSC Merge mode, the physical encoder has already registered
  1278. * PP0 as the master, to switch to right-only we would have to
  1279. * reprogram to be driven by PP1 instead.
  1280. * To support both cases, we prefer to support the mixer swap solution.
  1281. */
  1282. if (!encoder_in_dsc_merge)
  1283. return;
  1284. is_right_only = sde_kms_rect_is_null(&cstate->lm_roi[0]) &&
  1285. !sde_kms_rect_is_null(&cstate->lm_roi[1]);
  1286. if (is_right_only && !sde_crtc->mixers_swapped) {
  1287. /* right-only update swap mixers */
  1288. swap(sde_crtc->mixers[0], sde_crtc->mixers[1]);
  1289. sde_crtc->mixers_swapped = true;
  1290. } else if (!is_right_only && sde_crtc->mixers_swapped) {
  1291. /* left-only or full update, swap back */
  1292. swap(sde_crtc->mixers[0], sde_crtc->mixers[1]);
  1293. sde_crtc->mixers_swapped = false;
  1294. }
  1295. SDE_DEBUG("%s: right_only %d swapped %d, mix0->lm%d, mix1->lm%d\n",
  1296. sde_crtc->name, is_right_only, sde_crtc->mixers_swapped,
  1297. sde_crtc->mixers[0].hw_lm->idx - LM_0,
  1298. sde_crtc->mixers[1].hw_lm->idx - LM_0);
  1299. SDE_EVT32(DRMID(crtc), is_right_only, sde_crtc->mixers_swapped,
  1300. sde_crtc->mixers[0].hw_lm->idx - LM_0,
  1301. sde_crtc->mixers[1].hw_lm->idx - LM_0);
  1302. }
  1303. /**
  1304. * _sde_crtc_blend_setup - configure crtc mixers
  1305. * @crtc: Pointer to drm crtc structure
  1306. * @old_state: Pointer to old crtc state
  1307. * @add_planes: Whether or not to add planes to mixers
  1308. */
  1309. static void _sde_crtc_blend_setup(struct drm_crtc *crtc,
  1310. struct drm_crtc_state *old_state, bool add_planes)
  1311. {
  1312. struct sde_crtc *sde_crtc;
  1313. struct sde_crtc_state *sde_crtc_state;
  1314. struct sde_crtc_mixer *mixer;
  1315. struct sde_hw_ctl *ctl;
  1316. struct sde_hw_mixer *lm;
  1317. struct sde_ctl_flush_cfg cfg = {0,};
  1318. int i;
  1319. if (!crtc)
  1320. return;
  1321. sde_crtc = to_sde_crtc(crtc);
  1322. sde_crtc_state = to_sde_crtc_state(crtc->state);
  1323. mixer = sde_crtc->mixers;
  1324. SDE_DEBUG("%s\n", sde_crtc->name);
  1325. if (sde_crtc->num_mixers > CRTC_DUAL_MIXERS) {
  1326. SDE_ERROR("invalid number mixers: %d\n", sde_crtc->num_mixers);
  1327. return;
  1328. }
  1329. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1330. if (!mixer[i].hw_lm) {
  1331. SDE_ERROR("invalid lm or ctl assigned to mixer\n");
  1332. return;
  1333. }
  1334. mixer[i].mixer_op_mode = 0;
  1335. if (test_bit(SDE_CRTC_DIRTY_DIM_LAYERS,
  1336. sde_crtc_state->dirty)) {
  1337. /* clear dim_layer settings */
  1338. lm = mixer[i].hw_lm;
  1339. if (lm->ops.clear_dim_layer)
  1340. lm->ops.clear_dim_layer(lm);
  1341. }
  1342. }
  1343. _sde_crtc_swap_mixers_for_right_partial_update(crtc);
  1344. /* initialize stage cfg */
  1345. memset(&sde_crtc->stage_cfg, 0, sizeof(struct sde_hw_stage_cfg));
  1346. if (add_planes)
  1347. _sde_crtc_blend_setup_mixer(crtc, old_state, sde_crtc, mixer);
  1348. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1349. const struct sde_rect *lm_roi = &sde_crtc_state->lm_roi[i];
  1350. ctl = mixer[i].hw_ctl;
  1351. lm = mixer[i].hw_lm;
  1352. if (sde_kms_rect_is_null(lm_roi)) {
  1353. SDE_DEBUG(
  1354. "%s: lm%d leave ctl%d mask 0 since null roi\n",
  1355. sde_crtc->name, lm->idx - LM_0,
  1356. ctl->idx - CTL_0);
  1357. continue;
  1358. }
  1359. lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode);
  1360. /* stage config flush mask */
  1361. ctl->ops.update_bitmask_mixer(ctl, mixer[i].hw_lm->idx, 1);
  1362. ctl->ops.get_pending_flush(ctl, &cfg);
  1363. SDE_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n",
  1364. mixer[i].hw_lm->idx - LM_0,
  1365. mixer[i].mixer_op_mode,
  1366. ctl->idx - CTL_0,
  1367. cfg.pending_flush_mask);
  1368. ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
  1369. &sde_crtc->stage_cfg);
  1370. }
  1371. _sde_crtc_program_lm_output_roi(crtc);
  1372. }
  1373. int sde_crtc_find_plane_fb_modes(struct drm_crtc *crtc,
  1374. uint32_t *fb_ns, uint32_t *fb_sec, uint32_t *fb_sec_dir)
  1375. {
  1376. struct drm_plane *plane;
  1377. struct sde_plane_state *sde_pstate;
  1378. uint32_t mode = 0;
  1379. int rc;
  1380. if (!crtc) {
  1381. SDE_ERROR("invalid state\n");
  1382. return -EINVAL;
  1383. }
  1384. *fb_ns = 0;
  1385. *fb_sec = 0;
  1386. *fb_sec_dir = 0;
  1387. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1388. if (IS_ERR_OR_NULL(plane) || IS_ERR_OR_NULL(plane->state)) {
  1389. rc = PTR_ERR(plane);
  1390. SDE_ERROR("crtc%d failed to get plane%d state%d\n",
  1391. DRMID(crtc), DRMID(plane), rc);
  1392. return rc;
  1393. }
  1394. sde_pstate = to_sde_plane_state(plane->state);
  1395. mode = sde_plane_get_property(sde_pstate,
  1396. PLANE_PROP_FB_TRANSLATION_MODE);
  1397. switch (mode) {
  1398. case SDE_DRM_FB_NON_SEC:
  1399. (*fb_ns)++;
  1400. break;
  1401. case SDE_DRM_FB_SEC:
  1402. (*fb_sec)++;
  1403. break;
  1404. case SDE_DRM_FB_SEC_DIR_TRANS:
  1405. (*fb_sec_dir)++;
  1406. break;
  1407. default:
  1408. SDE_ERROR("Error: Plane[%d], fb_trans_mode:%d",
  1409. DRMID(plane), mode);
  1410. return -EINVAL;
  1411. }
  1412. }
  1413. return 0;
  1414. }
  1415. int sde_crtc_state_find_plane_fb_modes(struct drm_crtc_state *state,
  1416. uint32_t *fb_ns, uint32_t *fb_sec, uint32_t *fb_sec_dir)
  1417. {
  1418. struct drm_plane *plane;
  1419. const struct drm_plane_state *pstate;
  1420. struct sde_plane_state *sde_pstate;
  1421. uint32_t mode = 0;
  1422. int rc;
  1423. if (!state) {
  1424. SDE_ERROR("invalid state\n");
  1425. return -EINVAL;
  1426. }
  1427. *fb_ns = 0;
  1428. *fb_sec = 0;
  1429. *fb_sec_dir = 0;
  1430. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  1431. if (IS_ERR_OR_NULL(pstate)) {
  1432. rc = PTR_ERR(pstate);
  1433. SDE_ERROR("crtc%d failed to get plane%d state%d\n",
  1434. DRMID(state->crtc), DRMID(plane), rc);
  1435. return rc;
  1436. }
  1437. sde_pstate = to_sde_plane_state(pstate);
  1438. mode = sde_plane_get_property(sde_pstate,
  1439. PLANE_PROP_FB_TRANSLATION_MODE);
  1440. switch (mode) {
  1441. case SDE_DRM_FB_NON_SEC:
  1442. (*fb_ns)++;
  1443. break;
  1444. case SDE_DRM_FB_SEC:
  1445. (*fb_sec)++;
  1446. break;
  1447. case SDE_DRM_FB_SEC_DIR_TRANS:
  1448. (*fb_sec_dir)++;
  1449. break;
  1450. default:
  1451. SDE_ERROR("Error: Plane[%d], fb_trans_mode:%d",
  1452. DRMID(plane), mode);
  1453. return -EINVAL;
  1454. }
  1455. }
  1456. return 0;
  1457. }
  1458. static void _sde_drm_fb_sec_dir_trans(
  1459. struct sde_kms_smmu_state_data *smmu_state, uint32_t secure_level,
  1460. struct sde_mdss_cfg *catalog, bool old_valid_fb, int *ops)
  1461. {
  1462. /* secure display usecase */
  1463. if ((smmu_state->state == ATTACHED)
  1464. && (secure_level == SDE_DRM_SEC_ONLY)) {
  1465. smmu_state->state = catalog->sui_ns_allowed ?
  1466. DETACH_SEC_REQ : DETACH_ALL_REQ;
  1467. smmu_state->secure_level = secure_level;
  1468. smmu_state->transition_type = PRE_COMMIT;
  1469. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1470. if (old_valid_fb)
  1471. *ops |= (SDE_KMS_OPS_WAIT_FOR_TX_DONE |
  1472. SDE_KMS_OPS_CLEANUP_PLANE_FB);
  1473. if (catalog->sui_misr_supported)
  1474. smmu_state->sui_misr_state =
  1475. SUI_MISR_ENABLE_REQ;
  1476. /* secure camera usecase */
  1477. } else if (smmu_state->state == ATTACHED) {
  1478. smmu_state->state = DETACH_SEC_REQ;
  1479. smmu_state->secure_level = secure_level;
  1480. smmu_state->transition_type = PRE_COMMIT;
  1481. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1482. }
  1483. }
  1484. static void _sde_drm_fb_transactions(
  1485. struct sde_kms_smmu_state_data *smmu_state,
  1486. struct sde_mdss_cfg *catalog, bool old_valid_fb, bool post_commit,
  1487. int *ops)
  1488. {
  1489. if (((smmu_state->state == DETACHED)
  1490. || (smmu_state->state == DETACH_ALL_REQ))
  1491. || ((smmu_state->secure_level == SDE_DRM_SEC_ONLY)
  1492. && ((smmu_state->state == DETACHED_SEC)
  1493. || (smmu_state->state == DETACH_SEC_REQ)))) {
  1494. smmu_state->state = catalog->sui_ns_allowed ?
  1495. ATTACH_SEC_REQ : ATTACH_ALL_REQ;
  1496. smmu_state->transition_type = post_commit ?
  1497. POST_COMMIT : PRE_COMMIT;
  1498. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1499. if (old_valid_fb)
  1500. *ops |= SDE_KMS_OPS_WAIT_FOR_TX_DONE;
  1501. if (catalog->sui_misr_supported)
  1502. smmu_state->sui_misr_state =
  1503. SUI_MISR_DISABLE_REQ;
  1504. } else if ((smmu_state->state == DETACHED_SEC)
  1505. || (smmu_state->state == DETACH_SEC_REQ)) {
  1506. smmu_state->state = ATTACH_SEC_REQ;
  1507. smmu_state->transition_type = post_commit ?
  1508. POST_COMMIT : PRE_COMMIT;
  1509. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1510. if (old_valid_fb)
  1511. *ops |= SDE_KMS_OPS_WAIT_FOR_TX_DONE;
  1512. }
  1513. }
  1514. /**
  1515. * sde_crtc_get_secure_transition_ops - determines the operations that
  1516. * need to be performed before transitioning to secure state
  1517. * This function should be called after swapping the new state
  1518. * @crtc: Pointer to drm crtc structure
  1519. * Returns the bitmask of operations need to be performed, -Error in
  1520. * case of error cases
  1521. */
  1522. int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc,
  1523. struct drm_crtc_state *old_crtc_state,
  1524. bool old_valid_fb)
  1525. {
  1526. struct drm_plane *plane;
  1527. struct drm_encoder *encoder;
  1528. struct sde_crtc *sde_crtc;
  1529. struct sde_kms *sde_kms;
  1530. struct sde_mdss_cfg *catalog;
  1531. struct sde_kms_smmu_state_data *smmu_state;
  1532. uint32_t translation_mode = 0, secure_level;
  1533. int ops = 0;
  1534. bool post_commit = false;
  1535. if (!crtc || !crtc->state) {
  1536. SDE_ERROR("invalid crtc\n");
  1537. return -EINVAL;
  1538. }
  1539. sde_kms = _sde_crtc_get_kms(crtc);
  1540. if (!sde_kms)
  1541. return -EINVAL;
  1542. smmu_state = &sde_kms->smmu_state;
  1543. smmu_state->prev_state = smmu_state->state;
  1544. smmu_state->prev_secure_level = smmu_state->secure_level;
  1545. sde_crtc = to_sde_crtc(crtc);
  1546. secure_level = sde_crtc_get_secure_level(crtc, crtc->state);
  1547. catalog = sde_kms->catalog;
  1548. /*
  1549. * SMMU operations need to be delayed in case of video mode panels
  1550. * when switching back to non_secure mode
  1551. */
  1552. drm_for_each_encoder_mask(encoder, crtc->dev,
  1553. crtc->state->encoder_mask) {
  1554. if (sde_encoder_is_dsi_display(encoder))
  1555. post_commit |= sde_encoder_check_curr_mode(encoder,
  1556. MSM_DISPLAY_VIDEO_MODE);
  1557. }
  1558. SDE_DEBUG("crtc%d: secure_level %d old_valid_fb %d post_commit %d\n",
  1559. DRMID(crtc), secure_level, old_valid_fb, post_commit);
  1560. SDE_EVT32_VERBOSE(DRMID(crtc), secure_level, smmu_state->state,
  1561. old_valid_fb, post_commit, SDE_EVTLOG_FUNC_ENTRY);
  1562. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1563. if (!plane->state)
  1564. continue;
  1565. translation_mode = sde_plane_get_property(
  1566. to_sde_plane_state(plane->state),
  1567. PLANE_PROP_FB_TRANSLATION_MODE);
  1568. if (translation_mode > SDE_DRM_FB_SEC_DIR_TRANS) {
  1569. SDE_ERROR("crtc%d: invalid translation_mode %d\n",
  1570. DRMID(crtc), translation_mode);
  1571. return -EINVAL;
  1572. }
  1573. /* we can break if we find sec_dir plane */
  1574. if (translation_mode == SDE_DRM_FB_SEC_DIR_TRANS)
  1575. break;
  1576. }
  1577. mutex_lock(&sde_kms->secure_transition_lock);
  1578. switch (translation_mode) {
  1579. case SDE_DRM_FB_SEC_DIR_TRANS:
  1580. _sde_drm_fb_sec_dir_trans(smmu_state, secure_level,
  1581. catalog, old_valid_fb, &ops);
  1582. break;
  1583. case SDE_DRM_FB_SEC:
  1584. case SDE_DRM_FB_NON_SEC:
  1585. _sde_drm_fb_transactions(smmu_state, catalog,
  1586. old_valid_fb, post_commit, &ops);
  1587. break;
  1588. default:
  1589. SDE_ERROR("crtc%d: invalid plane fb_mode %d\n",
  1590. DRMID(crtc), translation_mode);
  1591. ops = -EINVAL;
  1592. }
  1593. /* log only during actual transition times */
  1594. if (ops) {
  1595. SDE_DEBUG("crtc%d: state%d sec%d sec_lvl%d type%d ops%x\n",
  1596. DRMID(crtc), smmu_state->state,
  1597. secure_level, smmu_state->secure_level,
  1598. smmu_state->transition_type, ops);
  1599. SDE_EVT32(DRMID(crtc), secure_level, translation_mode,
  1600. smmu_state->state, smmu_state->transition_type,
  1601. smmu_state->secure_level, old_valid_fb,
  1602. post_commit, ops, SDE_EVTLOG_FUNC_EXIT);
  1603. }
  1604. mutex_unlock(&sde_kms->secure_transition_lock);
  1605. return ops;
  1606. }
  1607. /**
  1608. * _sde_crtc_setup_scaler3_lut - Set up scaler lut
  1609. * LUTs are configured only once during boot
  1610. * @sde_crtc: Pointer to sde crtc
  1611. * @cstate: Pointer to sde crtc state
  1612. */
  1613. static int _sde_crtc_set_dest_scaler_lut(struct sde_crtc *sde_crtc,
  1614. struct sde_crtc_state *cstate, uint32_t lut_idx)
  1615. {
  1616. struct sde_hw_scaler3_lut_cfg *cfg;
  1617. struct sde_kms *sde_kms;
  1618. u32 *lut_data = NULL;
  1619. size_t len = 0;
  1620. int ret = 0;
  1621. if (!sde_crtc || !cstate) {
  1622. SDE_ERROR("invalid args\n");
  1623. return -EINVAL;
  1624. }
  1625. sde_kms = _sde_crtc_get_kms(&sde_crtc->base);
  1626. if (!sde_kms)
  1627. return -EINVAL;
  1628. if (is_qseed3_rev_qseed3lite(sde_kms->catalog))
  1629. return 0;
  1630. lut_data = msm_property_get_blob(&sde_crtc->property_info,
  1631. &cstate->property_state, &len, lut_idx);
  1632. if (!lut_data || !len) {
  1633. SDE_DEBUG("%s: lut(%d): cleared: %pK, %zu\n", sde_crtc->name,
  1634. lut_idx, lut_data, len);
  1635. lut_data = NULL;
  1636. len = 0;
  1637. }
  1638. cfg = &cstate->scl3_lut_cfg;
  1639. switch (lut_idx) {
  1640. case CRTC_PROP_DEST_SCALER_LUT_ED:
  1641. cfg->dir_lut = lut_data;
  1642. cfg->dir_len = len;
  1643. break;
  1644. case CRTC_PROP_DEST_SCALER_LUT_CIR:
  1645. cfg->cir_lut = lut_data;
  1646. cfg->cir_len = len;
  1647. break;
  1648. case CRTC_PROP_DEST_SCALER_LUT_SEP:
  1649. cfg->sep_lut = lut_data;
  1650. cfg->sep_len = len;
  1651. break;
  1652. default:
  1653. ret = -EINVAL;
  1654. SDE_ERROR("%s:invalid LUT idx(%d)\n", sde_crtc->name, lut_idx);
  1655. SDE_EVT32(DRMID(&sde_crtc->base), lut_idx, SDE_EVTLOG_ERROR);
  1656. break;
  1657. }
  1658. cfg->is_configured = cfg->dir_lut && cfg->cir_lut && cfg->sep_lut;
  1659. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), ret, lut_idx, len,
  1660. cfg->is_configured);
  1661. return ret;
  1662. }
  1663. void sde_crtc_timeline_status(struct drm_crtc *crtc)
  1664. {
  1665. struct sde_crtc *sde_crtc;
  1666. if (!crtc) {
  1667. SDE_ERROR("invalid crtc\n");
  1668. return;
  1669. }
  1670. sde_crtc = to_sde_crtc(crtc);
  1671. sde_fence_timeline_status(sde_crtc->output_fence, &crtc->base);
  1672. }
  1673. static int _sde_validate_hw_resources(struct sde_crtc *sde_crtc)
  1674. {
  1675. int i;
  1676. /**
  1677. * Check if sufficient hw resources are
  1678. * available as per target caps & topology
  1679. */
  1680. if (!sde_crtc) {
  1681. SDE_ERROR("invalid argument\n");
  1682. return -EINVAL;
  1683. }
  1684. if (!sde_crtc->num_mixers ||
  1685. sde_crtc->num_mixers > CRTC_DUAL_MIXERS) {
  1686. SDE_ERROR("%s: invalid number mixers: %d\n",
  1687. sde_crtc->name, sde_crtc->num_mixers);
  1688. SDE_EVT32(DRMID(&sde_crtc->base), sde_crtc->num_mixers,
  1689. SDE_EVTLOG_ERROR);
  1690. return -EINVAL;
  1691. }
  1692. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1693. if (!sde_crtc->mixers[i].hw_lm || !sde_crtc->mixers[i].hw_ctl
  1694. || !sde_crtc->mixers[i].hw_ds) {
  1695. SDE_ERROR("%s:insufficient resources for mixer(%d)\n",
  1696. sde_crtc->name, i);
  1697. SDE_EVT32(DRMID(&sde_crtc->base), sde_crtc->num_mixers,
  1698. i, sde_crtc->mixers[i].hw_lm,
  1699. sde_crtc->mixers[i].hw_ctl,
  1700. sde_crtc->mixers[i].hw_ds, SDE_EVTLOG_ERROR);
  1701. return -EINVAL;
  1702. }
  1703. }
  1704. return 0;
  1705. }
  1706. /**
  1707. * _sde_crtc_dest_scaler_setup - Set up dest scaler block
  1708. * @crtc: Pointer to drm crtc
  1709. */
  1710. static void _sde_crtc_dest_scaler_setup(struct drm_crtc *crtc)
  1711. {
  1712. struct sde_crtc *sde_crtc;
  1713. struct sde_crtc_state *cstate;
  1714. struct sde_hw_mixer *hw_lm;
  1715. struct sde_hw_ctl *hw_ctl;
  1716. struct sde_hw_ds *hw_ds;
  1717. struct sde_hw_ds_cfg *cfg;
  1718. struct sde_kms *kms;
  1719. u32 op_mode = 0;
  1720. u32 lm_idx = 0, num_mixers = 0;
  1721. int i, count = 0;
  1722. if (!crtc)
  1723. return;
  1724. sde_crtc = to_sde_crtc(crtc);
  1725. cstate = to_sde_crtc_state(crtc->state);
  1726. kms = _sde_crtc_get_kms(crtc);
  1727. num_mixers = sde_crtc->num_mixers;
  1728. count = cstate->num_ds;
  1729. SDE_DEBUG("crtc%d\n", crtc->base.id);
  1730. SDE_EVT32(DRMID(crtc), num_mixers, count, cstate->dirty[0],
  1731. cstate->num_ds_enabled);
  1732. if (!test_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty)) {
  1733. SDE_DEBUG("no change in settings, skip commit\n");
  1734. } else if (!kms || !kms->catalog) {
  1735. SDE_ERROR("crtc%d:invalid parameters\n", crtc->base.id);
  1736. } else if (!kms->catalog->mdp[0].has_dest_scaler) {
  1737. SDE_DEBUG("dest scaler feature not supported\n");
  1738. } else if (_sde_validate_hw_resources(sde_crtc)) {
  1739. //do nothing
  1740. } else if ((!cstate->scl3_lut_cfg.is_configured) &&
  1741. (!is_qseed3_rev_qseed3lite(kms->catalog))) {
  1742. SDE_ERROR("crtc%d:no LUT data available\n", crtc->base.id);
  1743. } else {
  1744. for (i = 0; i < count; i++) {
  1745. cfg = &cstate->ds_cfg[i];
  1746. if (!cfg->flags)
  1747. continue;
  1748. lm_idx = cfg->idx;
  1749. hw_lm = sde_crtc->mixers[lm_idx].hw_lm;
  1750. hw_ctl = sde_crtc->mixers[lm_idx].hw_ctl;
  1751. hw_ds = sde_crtc->mixers[lm_idx].hw_ds;
  1752. /* Setup op mode - Dual/single */
  1753. if (cfg->flags & SDE_DRM_DESTSCALER_ENABLE)
  1754. op_mode |= BIT(hw_ds->idx - DS_0);
  1755. if ((i == count-1) && hw_ds->ops.setup_opmode) {
  1756. op_mode |= (cstate->num_ds_enabled ==
  1757. CRTC_DUAL_MIXERS) ?
  1758. SDE_DS_OP_MODE_DUAL : 0;
  1759. hw_ds->ops.setup_opmode(hw_ds, op_mode);
  1760. SDE_EVT32_VERBOSE(DRMID(crtc), op_mode);
  1761. }
  1762. /* Setup scaler */
  1763. if ((cfg->flags & SDE_DRM_DESTSCALER_SCALE_UPDATE) ||
  1764. (cfg->flags &
  1765. SDE_DRM_DESTSCALER_ENHANCER_UPDATE)) {
  1766. if (hw_ds->ops.setup_scaler)
  1767. hw_ds->ops.setup_scaler(hw_ds,
  1768. &cfg->scl3_cfg,
  1769. &cstate->scl3_lut_cfg);
  1770. }
  1771. /*
  1772. * Dest scaler shares the flush bit of the LM in control
  1773. */
  1774. if (hw_ctl && hw_ctl->ops.update_bitmask_mixer)
  1775. hw_ctl->ops.update_bitmask_mixer(
  1776. hw_ctl, hw_lm->idx, 1);
  1777. }
  1778. }
  1779. }
  1780. static void sde_crtc_frame_event_cb(void *data, u32 event)
  1781. {
  1782. struct drm_crtc *crtc = (struct drm_crtc *)data;
  1783. struct sde_crtc *sde_crtc;
  1784. struct msm_drm_private *priv;
  1785. struct sde_crtc_frame_event *fevent;
  1786. struct sde_kms_frame_event_cb_data *cb_data;
  1787. struct drm_plane *plane;
  1788. u32 ubwc_error;
  1789. unsigned long flags;
  1790. u32 crtc_id;
  1791. cb_data = (struct sde_kms_frame_event_cb_data *)data;
  1792. if (!data) {
  1793. SDE_ERROR("invalid parameters\n");
  1794. return;
  1795. }
  1796. crtc = cb_data->crtc;
  1797. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  1798. SDE_ERROR("invalid parameters\n");
  1799. return;
  1800. }
  1801. sde_crtc = to_sde_crtc(crtc);
  1802. priv = crtc->dev->dev_private;
  1803. crtc_id = drm_crtc_index(crtc);
  1804. SDE_DEBUG("crtc%d\n", crtc->base.id);
  1805. SDE_EVT32_VERBOSE(DRMID(crtc), event);
  1806. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  1807. fevent = list_first_entry_or_null(&sde_crtc->frame_event_list,
  1808. struct sde_crtc_frame_event, list);
  1809. if (fevent)
  1810. list_del_init(&fevent->list);
  1811. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  1812. if (!fevent) {
  1813. SDE_ERROR("crtc%d event %d overflow\n",
  1814. crtc->base.id, event);
  1815. SDE_EVT32(DRMID(crtc), event);
  1816. return;
  1817. }
  1818. /* log and clear plane ubwc errors if any */
  1819. if (event & (SDE_ENCODER_FRAME_EVENT_ERROR
  1820. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD
  1821. | SDE_ENCODER_FRAME_EVENT_DONE)) {
  1822. drm_for_each_plane_mask(plane, crtc->dev,
  1823. sde_crtc->plane_mask_old) {
  1824. ubwc_error = sde_plane_get_ubwc_error(plane);
  1825. if (ubwc_error) {
  1826. SDE_EVT32(DRMID(crtc), DRMID(plane),
  1827. ubwc_error, SDE_EVTLOG_ERROR);
  1828. SDE_DEBUG("crtc%d plane %d ubwc_error %d\n",
  1829. DRMID(crtc), DRMID(plane),
  1830. ubwc_error);
  1831. sde_plane_clear_ubwc_error(plane);
  1832. }
  1833. }
  1834. }
  1835. fevent->event = event;
  1836. fevent->crtc = crtc;
  1837. fevent->connector = cb_data->connector;
  1838. fevent->ts = ktime_get();
  1839. kthread_queue_work(&priv->event_thread[crtc_id].worker, &fevent->work);
  1840. }
  1841. void sde_crtc_prepare_commit(struct drm_crtc *crtc,
  1842. struct drm_crtc_state *old_state)
  1843. {
  1844. struct drm_device *dev;
  1845. struct sde_crtc *sde_crtc;
  1846. struct sde_crtc_state *cstate;
  1847. struct drm_connector *conn;
  1848. struct drm_encoder *encoder;
  1849. struct drm_connector_list_iter conn_iter;
  1850. if (!crtc || !crtc->state) {
  1851. SDE_ERROR("invalid crtc\n");
  1852. return;
  1853. }
  1854. dev = crtc->dev;
  1855. sde_crtc = to_sde_crtc(crtc);
  1856. cstate = to_sde_crtc_state(crtc->state);
  1857. SDE_EVT32_VERBOSE(DRMID(crtc));
  1858. SDE_ATRACE_BEGIN("sde_crtc_prepare_commit");
  1859. /* identify connectors attached to this crtc */
  1860. cstate->num_connectors = 0;
  1861. drm_connector_list_iter_begin(dev, &conn_iter);
  1862. drm_for_each_connector_iter(conn, &conn_iter)
  1863. if (conn->state && conn->state->crtc == crtc &&
  1864. cstate->num_connectors < MAX_CONNECTORS) {
  1865. encoder = conn->state->best_encoder;
  1866. if (encoder)
  1867. sde_encoder_register_frame_event_callback(
  1868. encoder,
  1869. sde_crtc_frame_event_cb,
  1870. crtc);
  1871. cstate->connectors[cstate->num_connectors++] = conn;
  1872. sde_connector_prepare_fence(conn);
  1873. }
  1874. drm_connector_list_iter_end(&conn_iter);
  1875. /* prepare main output fence */
  1876. sde_fence_prepare(sde_crtc->output_fence);
  1877. SDE_ATRACE_END("sde_crtc_prepare_commit");
  1878. }
  1879. /**
  1880. * sde_crtc_complete_flip - signal pending page_flip events
  1881. * Any pending vblank events are added to the vblank_event_list
  1882. * so that the next vblank interrupt shall signal them.
  1883. * However PAGE_FLIP events are not handled through the vblank_event_list.
  1884. * This API signals any pending PAGE_FLIP events requested through
  1885. * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the sde_crtc->event.
  1886. * if file!=NULL, this is preclose potential cancel-flip path
  1887. * @crtc: Pointer to drm crtc structure
  1888. * @file: Pointer to drm file
  1889. */
  1890. void sde_crtc_complete_flip(struct drm_crtc *crtc,
  1891. struct drm_file *file)
  1892. {
  1893. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  1894. struct drm_device *dev = crtc->dev;
  1895. struct drm_pending_vblank_event *event;
  1896. unsigned long flags;
  1897. spin_lock_irqsave(&dev->event_lock, flags);
  1898. event = sde_crtc->event;
  1899. if (!event)
  1900. goto end;
  1901. /*
  1902. * if regular vblank case (!file) or if cancel-flip from
  1903. * preclose on file that requested flip, then send the
  1904. * event:
  1905. */
  1906. if (!file || (event->base.file_priv == file)) {
  1907. sde_crtc->event = NULL;
  1908. DRM_DEBUG_VBL("%s: send event: %pK\n",
  1909. sde_crtc->name, event);
  1910. SDE_EVT32_VERBOSE(DRMID(crtc));
  1911. drm_crtc_send_vblank_event(crtc, event);
  1912. }
  1913. end:
  1914. spin_unlock_irqrestore(&dev->event_lock, flags);
  1915. }
  1916. enum sde_intf_mode sde_crtc_get_intf_mode(struct drm_crtc *crtc,
  1917. struct drm_crtc_state *cstate)
  1918. {
  1919. struct drm_encoder *encoder;
  1920. if (!crtc || !crtc->dev || !cstate) {
  1921. SDE_ERROR("invalid crtc\n");
  1922. return INTF_MODE_NONE;
  1923. }
  1924. drm_for_each_encoder_mask(encoder, crtc->dev,
  1925. cstate->encoder_mask) {
  1926. /* continue if copy encoder is encountered */
  1927. if (sde_encoder_in_clone_mode(encoder))
  1928. continue;
  1929. return sde_encoder_get_intf_mode(encoder);
  1930. }
  1931. return INTF_MODE_NONE;
  1932. }
  1933. u32 sde_crtc_get_fps_mode(struct drm_crtc *crtc)
  1934. {
  1935. struct drm_encoder *encoder;
  1936. if (!crtc || !crtc->dev) {
  1937. SDE_ERROR("invalid crtc\n");
  1938. return INTF_MODE_NONE;
  1939. }
  1940. drm_for_each_encoder(encoder, crtc->dev)
  1941. if ((encoder->crtc == crtc)
  1942. && !sde_encoder_in_cont_splash(encoder))
  1943. return sde_encoder_get_fps(encoder);
  1944. return 0;
  1945. }
  1946. static void sde_crtc_vblank_cb(void *data)
  1947. {
  1948. struct drm_crtc *crtc = (struct drm_crtc *)data;
  1949. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  1950. /* keep statistics on vblank callback - with auto reset via debugfs */
  1951. if (ktime_compare(sde_crtc->vblank_cb_time, ktime_set(0, 0)) == 0)
  1952. sde_crtc->vblank_cb_time = ktime_get();
  1953. else
  1954. sde_crtc->vblank_cb_count++;
  1955. sde_crtc->vblank_last_cb_time = ktime_get();
  1956. sysfs_notify_dirent(sde_crtc->vsync_event_sf);
  1957. drm_crtc_handle_vblank(crtc);
  1958. DRM_DEBUG_VBL("crtc%d\n", crtc->base.id);
  1959. SDE_EVT32_VERBOSE(DRMID(crtc));
  1960. }
  1961. static void _sde_crtc_retire_event(struct drm_connector *connector,
  1962. ktime_t ts, enum sde_fence_event fence_event)
  1963. {
  1964. if (!connector) {
  1965. SDE_ERROR("invalid param\n");
  1966. return;
  1967. }
  1968. SDE_ATRACE_BEGIN("signal_retire_fence");
  1969. sde_connector_complete_commit(connector, ts, fence_event);
  1970. SDE_ATRACE_END("signal_retire_fence");
  1971. }
  1972. static void sde_crtc_frame_event_work(struct kthread_work *work)
  1973. {
  1974. struct msm_drm_private *priv;
  1975. struct sde_crtc_frame_event *fevent;
  1976. struct drm_crtc *crtc;
  1977. struct sde_crtc *sde_crtc;
  1978. struct sde_kms *sde_kms;
  1979. unsigned long flags;
  1980. bool in_clone_mode = false;
  1981. if (!work) {
  1982. SDE_ERROR("invalid work handle\n");
  1983. return;
  1984. }
  1985. fevent = container_of(work, struct sde_crtc_frame_event, work);
  1986. if (!fevent->crtc || !fevent->crtc->state) {
  1987. SDE_ERROR("invalid crtc\n");
  1988. return;
  1989. }
  1990. crtc = fevent->crtc;
  1991. sde_crtc = to_sde_crtc(crtc);
  1992. sde_kms = _sde_crtc_get_kms(crtc);
  1993. if (!sde_kms) {
  1994. SDE_ERROR("invalid kms handle\n");
  1995. return;
  1996. }
  1997. priv = sde_kms->dev->dev_private;
  1998. SDE_ATRACE_BEGIN("crtc_frame_event");
  1999. SDE_DEBUG("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
  2000. ktime_to_ns(fevent->ts));
  2001. SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event, SDE_EVTLOG_FUNC_ENTRY);
  2002. in_clone_mode = (fevent->event & SDE_ENCODER_FRAME_EVENT_CWB_DONE) ?
  2003. true : false;
  2004. if (!in_clone_mode && (fevent->event & (SDE_ENCODER_FRAME_EVENT_ERROR
  2005. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD
  2006. | SDE_ENCODER_FRAME_EVENT_DONE))) {
  2007. if (atomic_read(&sde_crtc->frame_pending) < 1) {
  2008. /* this should not happen */
  2009. SDE_ERROR("crtc%d ts:%lld invalid frame_pending:%d\n",
  2010. crtc->base.id,
  2011. ktime_to_ns(fevent->ts),
  2012. atomic_read(&sde_crtc->frame_pending));
  2013. SDE_EVT32(DRMID(crtc), fevent->event,
  2014. SDE_EVTLOG_FUNC_CASE1);
  2015. } else if (atomic_dec_return(&sde_crtc->frame_pending) == 0) {
  2016. /* release bandwidth and other resources */
  2017. SDE_DEBUG("crtc%d ts:%lld last pending\n",
  2018. crtc->base.id,
  2019. ktime_to_ns(fevent->ts));
  2020. SDE_EVT32(DRMID(crtc), fevent->event,
  2021. SDE_EVTLOG_FUNC_CASE2);
  2022. sde_core_perf_crtc_release_bw(crtc);
  2023. } else {
  2024. SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event,
  2025. SDE_EVTLOG_FUNC_CASE3);
  2026. }
  2027. }
  2028. if (fevent->event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE) {
  2029. SDE_ATRACE_BEGIN("signal_release_fence");
  2030. sde_fence_signal(sde_crtc->output_fence, fevent->ts,
  2031. (fevent->event & SDE_ENCODER_FRAME_EVENT_ERROR)
  2032. ? SDE_FENCE_SIGNAL_ERROR : SDE_FENCE_SIGNAL);
  2033. SDE_ATRACE_END("signal_release_fence");
  2034. }
  2035. if (fevent->event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE)
  2036. /* this api should be called without spin_lock */
  2037. _sde_crtc_retire_event(fevent->connector, fevent->ts,
  2038. (fevent->event & SDE_ENCODER_FRAME_EVENT_ERROR)
  2039. ? SDE_FENCE_SIGNAL_ERROR : SDE_FENCE_SIGNAL);
  2040. if (fevent->event & SDE_ENCODER_FRAME_EVENT_PANEL_DEAD)
  2041. SDE_ERROR("crtc%d ts:%lld received panel dead event\n",
  2042. crtc->base.id, ktime_to_ns(fevent->ts));
  2043. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  2044. list_add_tail(&fevent->list, &sde_crtc->frame_event_list);
  2045. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  2046. SDE_ATRACE_END("crtc_frame_event");
  2047. }
  2048. void sde_crtc_complete_commit(struct drm_crtc *crtc,
  2049. struct drm_crtc_state *old_state)
  2050. {
  2051. struct sde_crtc *sde_crtc;
  2052. if (!crtc || !crtc->state) {
  2053. SDE_ERROR("invalid crtc\n");
  2054. return;
  2055. }
  2056. sde_crtc = to_sde_crtc(crtc);
  2057. SDE_EVT32_VERBOSE(DRMID(crtc));
  2058. sde_core_perf_crtc_update(crtc, 0, false);
  2059. }
  2060. /**
  2061. * _sde_crtc_set_input_fence_timeout - update ns version of in fence timeout
  2062. * @cstate: Pointer to sde crtc state
  2063. */
  2064. static void _sde_crtc_set_input_fence_timeout(struct sde_crtc_state *cstate)
  2065. {
  2066. if (!cstate) {
  2067. SDE_ERROR("invalid cstate\n");
  2068. return;
  2069. }
  2070. cstate->input_fence_timeout_ns =
  2071. sde_crtc_get_property(cstate, CRTC_PROP_INPUT_FENCE_TIMEOUT);
  2072. cstate->input_fence_timeout_ns *= NSEC_PER_MSEC;
  2073. }
  2074. /**
  2075. * _sde_crtc_clear_dim_layers_v1 - clear all dim layer settings
  2076. * @cstate: Pointer to sde crtc state
  2077. */
  2078. static void _sde_crtc_clear_dim_layers_v1(struct sde_crtc_state *cstate)
  2079. {
  2080. u32 i;
  2081. if (!cstate)
  2082. return;
  2083. for (i = 0; i < cstate->num_dim_layers; i++)
  2084. memset(&cstate->dim_layer[i], 0, sizeof(cstate->dim_layer[i]));
  2085. cstate->num_dim_layers = 0;
  2086. }
  2087. /**
  2088. * _sde_crtc_set_dim_layer_v1 - copy dim layer settings from userspace
  2089. * @cstate: Pointer to sde crtc state
  2090. * @user_ptr: User ptr for sde_drm_dim_layer_v1 struct
  2091. */
  2092. static void _sde_crtc_set_dim_layer_v1(struct drm_crtc *crtc,
  2093. struct sde_crtc_state *cstate, void __user *usr_ptr)
  2094. {
  2095. struct sde_drm_dim_layer_v1 dim_layer_v1;
  2096. struct sde_drm_dim_layer_cfg *user_cfg;
  2097. struct sde_hw_dim_layer *dim_layer;
  2098. u32 count, i;
  2099. struct sde_kms *kms;
  2100. if (!crtc || !cstate) {
  2101. SDE_ERROR("invalid crtc or cstate\n");
  2102. return;
  2103. }
  2104. dim_layer = cstate->dim_layer;
  2105. if (!usr_ptr) {
  2106. /* usr_ptr is null when setting the default property value */
  2107. _sde_crtc_clear_dim_layers_v1(cstate);
  2108. SDE_DEBUG("dim_layer data removed\n");
  2109. goto clear;
  2110. }
  2111. kms = _sde_crtc_get_kms(crtc);
  2112. if (!kms || !kms->catalog) {
  2113. SDE_ERROR("invalid kms\n");
  2114. return;
  2115. }
  2116. if (copy_from_user(&dim_layer_v1, usr_ptr, sizeof(dim_layer_v1))) {
  2117. SDE_ERROR("failed to copy dim_layer data\n");
  2118. return;
  2119. }
  2120. count = dim_layer_v1.num_layers;
  2121. if (count > SDE_MAX_DIM_LAYERS) {
  2122. SDE_ERROR("invalid number of dim_layers:%d", count);
  2123. return;
  2124. }
  2125. /* populate from user space */
  2126. cstate->num_dim_layers = count;
  2127. for (i = 0; i < count; i++) {
  2128. user_cfg = &dim_layer_v1.layer_cfg[i];
  2129. dim_layer[i].flags = user_cfg->flags;
  2130. dim_layer[i].stage = (kms->catalog->has_base_layer) ?
  2131. user_cfg->stage : user_cfg->stage +
  2132. SDE_STAGE_0;
  2133. dim_layer[i].rect.x = user_cfg->rect.x1;
  2134. dim_layer[i].rect.y = user_cfg->rect.y1;
  2135. dim_layer[i].rect.w = user_cfg->rect.x2 - user_cfg->rect.x1;
  2136. dim_layer[i].rect.h = user_cfg->rect.y2 - user_cfg->rect.y1;
  2137. dim_layer[i].color_fill = (struct sde_mdss_color) {
  2138. user_cfg->color_fill.color_0,
  2139. user_cfg->color_fill.color_1,
  2140. user_cfg->color_fill.color_2,
  2141. user_cfg->color_fill.color_3,
  2142. };
  2143. SDE_DEBUG("dim_layer[%d] - flags:%d, stage:%d\n",
  2144. i, dim_layer[i].flags, dim_layer[i].stage);
  2145. SDE_DEBUG(" rect:{%d,%d,%d,%d}, color:{%d,%d,%d,%d}\n",
  2146. dim_layer[i].rect.x, dim_layer[i].rect.y,
  2147. dim_layer[i].rect.w, dim_layer[i].rect.h,
  2148. dim_layer[i].color_fill.color_0,
  2149. dim_layer[i].color_fill.color_1,
  2150. dim_layer[i].color_fill.color_2,
  2151. dim_layer[i].color_fill.color_3);
  2152. }
  2153. clear:
  2154. set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty);
  2155. }
  2156. /**
  2157. * _sde_crtc_set_dest_scaler - copy dest scaler settings from userspace
  2158. * @sde_crtc : Pointer to sde crtc
  2159. * @cstate : Pointer to sde crtc state
  2160. * @usr_ptr: User ptr for sde_drm_dest_scaler_data struct
  2161. */
  2162. static int _sde_crtc_set_dest_scaler(struct sde_crtc *sde_crtc,
  2163. struct sde_crtc_state *cstate,
  2164. void __user *usr_ptr)
  2165. {
  2166. struct sde_drm_dest_scaler_data ds_data;
  2167. struct sde_drm_dest_scaler_cfg *ds_cfg_usr;
  2168. struct sde_drm_scaler_v2 scaler_v2;
  2169. void __user *scaler_v2_usr;
  2170. int i, count;
  2171. if (!sde_crtc || !cstate) {
  2172. SDE_ERROR("invalid sde_crtc/state\n");
  2173. return -EINVAL;
  2174. }
  2175. SDE_DEBUG("crtc %s\n", sde_crtc->name);
  2176. if (!usr_ptr) {
  2177. SDE_DEBUG("ds data removed\n");
  2178. return 0;
  2179. }
  2180. if (copy_from_user(&ds_data, usr_ptr, sizeof(ds_data))) {
  2181. SDE_ERROR("%s:failed to copy dest scaler data from user\n",
  2182. sde_crtc->name);
  2183. return -EINVAL;
  2184. }
  2185. count = ds_data.num_dest_scaler;
  2186. if (!count) {
  2187. SDE_DEBUG("no ds data available\n");
  2188. return 0;
  2189. }
  2190. if (count > SDE_MAX_DS_COUNT) {
  2191. SDE_ERROR("%s: invalid config: num_ds(%d) max(%d)\n",
  2192. sde_crtc->name, count, SDE_MAX_DS_COUNT);
  2193. SDE_EVT32(DRMID(&sde_crtc->base), count, SDE_EVTLOG_ERROR);
  2194. return -EINVAL;
  2195. }
  2196. /* Populate from user space */
  2197. for (i = 0; i < count; i++) {
  2198. ds_cfg_usr = &ds_data.ds_cfg[i];
  2199. cstate->ds_cfg[i].idx = ds_cfg_usr->index;
  2200. cstate->ds_cfg[i].flags = ds_cfg_usr->flags;
  2201. cstate->ds_cfg[i].lm_width = ds_cfg_usr->lm_width;
  2202. cstate->ds_cfg[i].lm_height = ds_cfg_usr->lm_height;
  2203. memset(&scaler_v2, 0, sizeof(scaler_v2));
  2204. if (ds_cfg_usr->scaler_cfg) {
  2205. scaler_v2_usr =
  2206. (void __user *)((uintptr_t)ds_cfg_usr->scaler_cfg);
  2207. if (copy_from_user(&scaler_v2, scaler_v2_usr,
  2208. sizeof(scaler_v2))) {
  2209. SDE_ERROR("%s:scaler: copy from user failed\n",
  2210. sde_crtc->name);
  2211. return -EINVAL;
  2212. }
  2213. }
  2214. sde_set_scaler_v2(&cstate->ds_cfg[i].scl3_cfg, &scaler_v2);
  2215. SDE_DEBUG("en(%d)dir(%d)de(%d) src(%dx%d) dst(%dx%d)\n",
  2216. scaler_v2.enable, scaler_v2.dir_en, scaler_v2.de.enable,
  2217. scaler_v2.src_width[0], scaler_v2.src_height[0],
  2218. scaler_v2.dst_width, scaler_v2.dst_height);
  2219. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base),
  2220. scaler_v2.enable, scaler_v2.dir_en, scaler_v2.de.enable,
  2221. scaler_v2.src_width[0], scaler_v2.src_height[0],
  2222. scaler_v2.dst_width, scaler_v2.dst_height);
  2223. SDE_DEBUG("ds cfg[%d]-ndx(%d) flags(%d) lm(%dx%d)\n",
  2224. i, ds_cfg_usr->index, ds_cfg_usr->flags,
  2225. ds_cfg_usr->lm_width, ds_cfg_usr->lm_height);
  2226. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), i, ds_cfg_usr->index,
  2227. ds_cfg_usr->flags, ds_cfg_usr->lm_width,
  2228. ds_cfg_usr->lm_height);
  2229. }
  2230. cstate->num_ds = count;
  2231. set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2232. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), count);
  2233. return 0;
  2234. }
  2235. static int _sde_crtc_check_dest_scaler_lm(struct drm_crtc *crtc,
  2236. struct drm_display_mode *mode, struct sde_hw_ds_cfg *cfg, u32 hdisplay,
  2237. u32 prev_lm_width, u32 prev_lm_height)
  2238. {
  2239. if (cfg->lm_width > hdisplay || cfg->lm_height > mode->vdisplay
  2240. || !cfg->lm_width || !cfg->lm_height) {
  2241. SDE_ERROR("crtc%d: lm size[%d,%d] display [%d,%d]\n",
  2242. crtc->base.id, cfg->lm_width, cfg->lm_height,
  2243. hdisplay, mode->vdisplay);
  2244. SDE_EVT32(DRMID(crtc), cfg->lm_width, cfg->lm_height,
  2245. hdisplay, mode->vdisplay, SDE_EVTLOG_ERROR);
  2246. return -E2BIG;
  2247. }
  2248. if (!prev_lm_width && !prev_lm_height) {
  2249. prev_lm_width = cfg->lm_width;
  2250. prev_lm_height = cfg->lm_height;
  2251. } else {
  2252. if (cfg->lm_width != prev_lm_width ||
  2253. cfg->lm_height != prev_lm_height) {
  2254. SDE_ERROR("crtc%d:lm left[%d,%d]right[%d %d]\n",
  2255. crtc->base.id, cfg->lm_width,
  2256. cfg->lm_height, prev_lm_width,
  2257. prev_lm_height);
  2258. SDE_EVT32(DRMID(crtc), cfg->lm_width,
  2259. cfg->lm_height, prev_lm_width,
  2260. prev_lm_height, SDE_EVTLOG_ERROR);
  2261. return -EINVAL;
  2262. }
  2263. }
  2264. return 0;
  2265. }
  2266. static int _sde_crtc_check_dest_scaler_cfg(struct drm_crtc *crtc,
  2267. struct sde_crtc *sde_crtc, struct drm_display_mode *mode,
  2268. struct sde_hw_ds *hw_ds, struct sde_hw_ds_cfg *cfg, u32 hdisplay,
  2269. u32 max_in_width, u32 max_out_width)
  2270. {
  2271. if (cfg->flags & SDE_DRM_DESTSCALER_SCALE_UPDATE ||
  2272. cfg->flags & SDE_DRM_DESTSCALER_ENHANCER_UPDATE) {
  2273. /**
  2274. * Scaler src and dst width shouldn't exceed the maximum
  2275. * width limitation. Also, if there is no partial update
  2276. * dst width and height must match display resolution.
  2277. */
  2278. if (cfg->scl3_cfg.src_width[0] > max_in_width ||
  2279. cfg->scl3_cfg.dst_width > max_out_width ||
  2280. !cfg->scl3_cfg.src_width[0] ||
  2281. !cfg->scl3_cfg.dst_width ||
  2282. (!(cfg->flags & SDE_DRM_DESTSCALER_PU_ENABLE)
  2283. && (cfg->scl3_cfg.dst_width != hdisplay ||
  2284. cfg->scl3_cfg.dst_height != mode->vdisplay))) {
  2285. SDE_ERROR("crtc%d: ", crtc->base.id);
  2286. SDE_ERROR("src_w(%d) dst(%dx%d) display(%dx%d)",
  2287. cfg->scl3_cfg.src_width[0],
  2288. cfg->scl3_cfg.dst_width,
  2289. cfg->scl3_cfg.dst_height,
  2290. hdisplay, mode->vdisplay);
  2291. SDE_ERROR("num_mixers(%d) flags(%d) ds-%d:\n",
  2292. sde_crtc->num_mixers, cfg->flags,
  2293. hw_ds->idx - DS_0);
  2294. SDE_ERROR("scale_en = %d, DE_en =%d\n",
  2295. cfg->scl3_cfg.enable,
  2296. cfg->scl3_cfg.de.enable);
  2297. SDE_EVT32(DRMID(crtc), cfg->scl3_cfg.enable,
  2298. cfg->scl3_cfg.de.enable, cfg->flags,
  2299. max_in_width, max_out_width,
  2300. cfg->scl3_cfg.src_width[0],
  2301. cfg->scl3_cfg.dst_width,
  2302. cfg->scl3_cfg.dst_height, hdisplay,
  2303. mode->vdisplay, sde_crtc->num_mixers,
  2304. SDE_EVTLOG_ERROR);
  2305. cfg->flags &=
  2306. ~SDE_DRM_DESTSCALER_SCALE_UPDATE;
  2307. cfg->flags &=
  2308. ~SDE_DRM_DESTSCALER_ENHANCER_UPDATE;
  2309. return -EINVAL;
  2310. }
  2311. }
  2312. return 0;
  2313. }
  2314. static int _sde_crtc_check_dest_scaler_validate_ds(struct drm_crtc *crtc,
  2315. struct sde_crtc *sde_crtc, struct sde_crtc_state *cstate,
  2316. struct drm_display_mode *mode, struct sde_hw_ds *hw_ds,
  2317. struct sde_hw_ds_cfg *cfg, u32 hdisplay, u32 *num_ds_enable,
  2318. u32 prev_lm_width, u32 prev_lm_height, u32 max_in_width,
  2319. u32 max_out_width)
  2320. {
  2321. int i, ret;
  2322. u32 lm_idx;
  2323. for (i = 0; i < cstate->num_ds; i++) {
  2324. cfg = &cstate->ds_cfg[i];
  2325. lm_idx = cfg->idx;
  2326. /**
  2327. * Validate against topology
  2328. * No of dest scalers should match the num of mixers
  2329. * unless it is partial update left only/right only use case
  2330. */
  2331. if (lm_idx >= sde_crtc->num_mixers || (i != lm_idx &&
  2332. !(cfg->flags & SDE_DRM_DESTSCALER_PU_ENABLE))) {
  2333. SDE_ERROR("crtc%d: ds_cfg id(%d):idx(%d), flags(%d)\n",
  2334. crtc->base.id, i, lm_idx, cfg->flags);
  2335. SDE_EVT32(DRMID(crtc), i, lm_idx, cfg->flags,
  2336. SDE_EVTLOG_ERROR);
  2337. return -EINVAL;
  2338. }
  2339. hw_ds = sde_crtc->mixers[lm_idx].hw_ds;
  2340. if (!max_in_width && !max_out_width) {
  2341. max_in_width = hw_ds->scl->top->maxinputwidth;
  2342. max_out_width = hw_ds->scl->top->maxoutputwidth;
  2343. if (cstate->num_ds == CRTC_DUAL_MIXERS)
  2344. max_in_width -= SDE_DS_OVERFETCH_SIZE;
  2345. SDE_DEBUG("max DS width [%d,%d] for num_ds = %d\n",
  2346. max_in_width, max_out_width, cstate->num_ds);
  2347. }
  2348. /* Check LM width and height */
  2349. ret = _sde_crtc_check_dest_scaler_lm(crtc, mode, cfg, hdisplay,
  2350. prev_lm_width, prev_lm_height);
  2351. if (ret)
  2352. return ret;
  2353. /* Check scaler data */
  2354. ret = _sde_crtc_check_dest_scaler_cfg(crtc, sde_crtc, mode,
  2355. hw_ds, cfg, hdisplay,
  2356. max_in_width, max_out_width);
  2357. if (ret)
  2358. return ret;
  2359. if (cfg->flags & SDE_DRM_DESTSCALER_ENABLE)
  2360. (*num_ds_enable)++;
  2361. SDE_DEBUG("ds[%d]: flags[0x%X]\n",
  2362. hw_ds->idx - DS_0, cfg->flags);
  2363. SDE_EVT32_VERBOSE(DRMID(crtc), hw_ds->idx - DS_0, cfg->flags);
  2364. }
  2365. return 0;
  2366. }
  2367. static void _sde_crtc_check_dest_scaler_data_disable(struct drm_crtc *crtc,
  2368. struct sde_crtc_state *cstate, struct sde_hw_ds_cfg *cfg,
  2369. u32 num_ds_enable)
  2370. {
  2371. int i;
  2372. SDE_DEBUG("dest scaler status : %d -> %d\n",
  2373. cstate->num_ds_enabled, num_ds_enable);
  2374. SDE_EVT32_VERBOSE(DRMID(crtc), cstate->num_ds_enabled, num_ds_enable,
  2375. cstate->num_ds, cstate->dirty[0]);
  2376. if (cstate->num_ds_enabled != num_ds_enable) {
  2377. /* Disabling destination scaler */
  2378. if (!num_ds_enable) {
  2379. for (i = 0; i < cstate->num_ds; i++) {
  2380. cfg = &cstate->ds_cfg[i];
  2381. cfg->idx = i;
  2382. /* Update scaler settings in disable case */
  2383. cfg->flags = SDE_DRM_DESTSCALER_SCALE_UPDATE;
  2384. cfg->scl3_cfg.enable = 0;
  2385. cfg->scl3_cfg.de.enable = 0;
  2386. }
  2387. }
  2388. cstate->num_ds_enabled = num_ds_enable;
  2389. set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2390. } else {
  2391. if (!cstate->num_ds_enabled)
  2392. clear_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2393. }
  2394. }
  2395. /**
  2396. * _sde_crtc_check_dest_scaler_data - validate the dest scaler data
  2397. * @crtc : Pointer to drm crtc
  2398. * @state : Pointer to drm crtc state
  2399. */
  2400. static int _sde_crtc_check_dest_scaler_data(struct drm_crtc *crtc,
  2401. struct drm_crtc_state *state)
  2402. {
  2403. struct sde_crtc *sde_crtc;
  2404. struct sde_crtc_state *cstate;
  2405. struct drm_display_mode *mode;
  2406. struct sde_kms *kms;
  2407. struct sde_hw_ds *hw_ds = NULL;
  2408. struct sde_hw_ds_cfg *cfg = NULL;
  2409. u32 ret = 0;
  2410. u32 num_ds_enable = 0, hdisplay = 0;
  2411. u32 max_in_width = 0, max_out_width = 0;
  2412. u32 prev_lm_width = 0, prev_lm_height = 0;
  2413. if (!crtc || !state)
  2414. return -EINVAL;
  2415. sde_crtc = to_sde_crtc(crtc);
  2416. cstate = to_sde_crtc_state(state);
  2417. kms = _sde_crtc_get_kms(crtc);
  2418. mode = &state->adjusted_mode;
  2419. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2420. if (!test_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty)) {
  2421. SDE_DEBUG("dest scaler property not set, skip validation\n");
  2422. return 0;
  2423. }
  2424. if (!kms || !kms->catalog) {
  2425. SDE_ERROR("crtc%d: invalid parameters\n", crtc->base.id);
  2426. return -EINVAL;
  2427. }
  2428. if (!kms->catalog->mdp[0].has_dest_scaler) {
  2429. SDE_DEBUG("dest scaler feature not supported\n");
  2430. return 0;
  2431. }
  2432. if (!sde_crtc->num_mixers) {
  2433. SDE_DEBUG("mixers not allocated\n");
  2434. return 0;
  2435. }
  2436. ret = _sde_validate_hw_resources(sde_crtc);
  2437. if (ret)
  2438. goto err;
  2439. /**
  2440. * No of dest scalers shouldn't exceed hw ds block count and
  2441. * also, match the num of mixers unless it is partial update
  2442. * left only/right only use case - currently PU + DS is not supported
  2443. */
  2444. if (cstate->num_ds > kms->catalog->ds_count ||
  2445. ((cstate->num_ds != sde_crtc->num_mixers) &&
  2446. !(cstate->ds_cfg[0].flags & SDE_DRM_DESTSCALER_PU_ENABLE))) {
  2447. SDE_ERROR("crtc%d: num_ds(%d), hw_ds_cnt(%d) flags(%d)\n",
  2448. crtc->base.id, cstate->num_ds, kms->catalog->ds_count,
  2449. cstate->ds_cfg[0].flags);
  2450. ret = -EINVAL;
  2451. goto err;
  2452. }
  2453. /**
  2454. * Check if DS needs to be enabled or disabled
  2455. * In case of enable, validate the data
  2456. */
  2457. if (!(cstate->ds_cfg[0].flags & SDE_DRM_DESTSCALER_ENABLE)) {
  2458. SDE_DEBUG("disable dest scaler, num(%d) flags(%d)\n",
  2459. cstate->num_ds, cstate->ds_cfg[0].flags);
  2460. goto disable;
  2461. }
  2462. /* Display resolution */
  2463. hdisplay = mode->hdisplay/sde_crtc->num_mixers;
  2464. /* Validate the DS data */
  2465. ret = _sde_crtc_check_dest_scaler_validate_ds(crtc, sde_crtc, cstate,
  2466. mode, hw_ds, cfg, hdisplay, &num_ds_enable,
  2467. prev_lm_width, prev_lm_height,
  2468. max_in_width, max_out_width);
  2469. if (ret)
  2470. goto err;
  2471. disable:
  2472. _sde_crtc_check_dest_scaler_data_disable(crtc, cstate, cfg,
  2473. num_ds_enable);
  2474. return 0;
  2475. err:
  2476. clear_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2477. return ret;
  2478. }
  2479. /**
  2480. * _sde_crtc_wait_for_fences - wait for incoming framebuffer sync fences
  2481. * @crtc: Pointer to CRTC object
  2482. */
  2483. static void _sde_crtc_wait_for_fences(struct drm_crtc *crtc)
  2484. {
  2485. struct drm_plane *plane = NULL;
  2486. uint32_t wait_ms = 1;
  2487. ktime_t kt_end, kt_wait;
  2488. int rc = 0;
  2489. SDE_DEBUG("\n");
  2490. if (!crtc || !crtc->state) {
  2491. SDE_ERROR("invalid crtc/state %pK\n", crtc);
  2492. return;
  2493. }
  2494. /* use monotonic timer to limit total fence wait time */
  2495. kt_end = ktime_add_ns(ktime_get(),
  2496. to_sde_crtc_state(crtc->state)->input_fence_timeout_ns);
  2497. /*
  2498. * Wait for fences sequentially, as all of them need to be signalled
  2499. * before we can proceed.
  2500. *
  2501. * Limit total wait time to INPUT_FENCE_TIMEOUT, but still call
  2502. * sde_plane_wait_input_fence with wait_ms == 0 after the timeout so
  2503. * that each plane can check its fence status and react appropriately
  2504. * if its fence has timed out. Call input fence wait multiple times if
  2505. * fence wait is interrupted due to interrupt call.
  2506. */
  2507. SDE_ATRACE_BEGIN("plane_wait_input_fence");
  2508. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2509. do {
  2510. kt_wait = ktime_sub(kt_end, ktime_get());
  2511. if (ktime_compare(kt_wait, ktime_set(0, 0)) >= 0)
  2512. wait_ms = ktime_to_ms(kt_wait);
  2513. else
  2514. wait_ms = 0;
  2515. rc = sde_plane_wait_input_fence(plane, wait_ms);
  2516. } while (wait_ms && rc == -ERESTARTSYS);
  2517. }
  2518. SDE_ATRACE_END("plane_wait_input_fence");
  2519. }
  2520. static void _sde_crtc_setup_mixer_for_encoder(
  2521. struct drm_crtc *crtc,
  2522. struct drm_encoder *enc)
  2523. {
  2524. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2525. struct sde_kms *sde_kms = _sde_crtc_get_kms(crtc);
  2526. struct sde_rm *rm = &sde_kms->rm;
  2527. struct sde_crtc_mixer *mixer;
  2528. struct sde_hw_ctl *last_valid_ctl = NULL;
  2529. int i;
  2530. struct sde_rm_hw_iter lm_iter, ctl_iter, dspp_iter, ds_iter;
  2531. sde_rm_init_hw_iter(&lm_iter, enc->base.id, SDE_HW_BLK_LM);
  2532. sde_rm_init_hw_iter(&ctl_iter, enc->base.id, SDE_HW_BLK_CTL);
  2533. sde_rm_init_hw_iter(&dspp_iter, enc->base.id, SDE_HW_BLK_DSPP);
  2534. sde_rm_init_hw_iter(&ds_iter, enc->base.id, SDE_HW_BLK_DS);
  2535. /* Set up all the mixers and ctls reserved by this encoder */
  2536. for (i = sde_crtc->num_mixers; i < ARRAY_SIZE(sde_crtc->mixers); i++) {
  2537. mixer = &sde_crtc->mixers[i];
  2538. if (!sde_rm_get_hw(rm, &lm_iter))
  2539. break;
  2540. mixer->hw_lm = (struct sde_hw_mixer *)lm_iter.hw;
  2541. /* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */
  2542. if (!sde_rm_get_hw(rm, &ctl_iter)) {
  2543. SDE_DEBUG("no ctl assigned to lm %d, using previous\n",
  2544. mixer->hw_lm->idx - LM_0);
  2545. mixer->hw_ctl = last_valid_ctl;
  2546. } else {
  2547. mixer->hw_ctl = (struct sde_hw_ctl *)ctl_iter.hw;
  2548. last_valid_ctl = mixer->hw_ctl;
  2549. sde_crtc->num_ctls++;
  2550. }
  2551. /* Shouldn't happen, mixers are always >= ctls */
  2552. if (!mixer->hw_ctl) {
  2553. SDE_ERROR("no valid ctls found for lm %d\n",
  2554. mixer->hw_lm->idx - LM_0);
  2555. return;
  2556. }
  2557. /* Dspp may be null */
  2558. (void) sde_rm_get_hw(rm, &dspp_iter);
  2559. mixer->hw_dspp = (struct sde_hw_dspp *)dspp_iter.hw;
  2560. /* DS may be null */
  2561. (void) sde_rm_get_hw(rm, &ds_iter);
  2562. mixer->hw_ds = (struct sde_hw_ds *)ds_iter.hw;
  2563. mixer->encoder = enc;
  2564. sde_crtc->num_mixers++;
  2565. SDE_DEBUG("setup mixer %d: lm %d\n",
  2566. i, mixer->hw_lm->idx - LM_0);
  2567. SDE_DEBUG("setup mixer %d: ctl %d\n",
  2568. i, mixer->hw_ctl->idx - CTL_0);
  2569. if (mixer->hw_ds)
  2570. SDE_DEBUG("setup mixer %d: ds %d\n",
  2571. i, mixer->hw_ds->idx - DS_0);
  2572. }
  2573. }
  2574. static void _sde_crtc_setup_mixers(struct drm_crtc *crtc)
  2575. {
  2576. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2577. struct drm_encoder *enc;
  2578. sde_crtc->num_ctls = 0;
  2579. sde_crtc->num_mixers = 0;
  2580. sde_crtc->mixers_swapped = false;
  2581. memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers));
  2582. mutex_lock(&sde_crtc->crtc_lock);
  2583. /* Check for mixers on all encoders attached to this crtc */
  2584. list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) {
  2585. if (enc->crtc != crtc)
  2586. continue;
  2587. /* avoid overwriting mixers info from a copy encoder */
  2588. if (sde_encoder_in_clone_mode(enc))
  2589. continue;
  2590. _sde_crtc_setup_mixer_for_encoder(crtc, enc);
  2591. }
  2592. mutex_unlock(&sde_crtc->crtc_lock);
  2593. _sde_crtc_check_dest_scaler_data(crtc, crtc->state);
  2594. }
  2595. static void _sde_crtc_setup_is_ppsplit(struct drm_crtc_state *state)
  2596. {
  2597. int i;
  2598. struct sde_crtc_state *cstate;
  2599. cstate = to_sde_crtc_state(state);
  2600. cstate->is_ppsplit = false;
  2601. for (i = 0; i < cstate->num_connectors; i++) {
  2602. struct drm_connector *conn = cstate->connectors[i];
  2603. if (sde_connector_get_topology_name(conn) ==
  2604. SDE_RM_TOPOLOGY_PPSPLIT)
  2605. cstate->is_ppsplit = true;
  2606. }
  2607. }
  2608. static void _sde_crtc_setup_lm_bounds(struct drm_crtc *crtc,
  2609. struct drm_crtc_state *state)
  2610. {
  2611. struct sde_crtc *sde_crtc;
  2612. struct sde_crtc_state *cstate;
  2613. struct drm_display_mode *adj_mode;
  2614. u32 crtc_split_width;
  2615. int i;
  2616. if (!crtc || !state) {
  2617. SDE_ERROR("invalid args\n");
  2618. return;
  2619. }
  2620. sde_crtc = to_sde_crtc(crtc);
  2621. cstate = to_sde_crtc_state(state);
  2622. adj_mode = &state->adjusted_mode;
  2623. crtc_split_width = sde_crtc_get_mixer_width(sde_crtc, cstate, adj_mode);
  2624. for (i = 0; i < sde_crtc->num_mixers; i++) {
  2625. cstate->lm_bounds[i].x = crtc_split_width * i;
  2626. cstate->lm_bounds[i].y = 0;
  2627. cstate->lm_bounds[i].w = crtc_split_width;
  2628. cstate->lm_bounds[i].h =
  2629. sde_crtc_get_mixer_height(sde_crtc, cstate, adj_mode);
  2630. memcpy(&cstate->lm_roi[i], &cstate->lm_bounds[i],
  2631. sizeof(cstate->lm_roi[i]));
  2632. SDE_EVT32_VERBOSE(DRMID(crtc), i,
  2633. cstate->lm_bounds[i].x, cstate->lm_bounds[i].y,
  2634. cstate->lm_bounds[i].w, cstate->lm_bounds[i].h);
  2635. SDE_DEBUG("%s: lm%d bnd&roi (%d,%d,%d,%d)\n", sde_crtc->name, i,
  2636. cstate->lm_roi[i].x, cstate->lm_roi[i].y,
  2637. cstate->lm_roi[i].w, cstate->lm_roi[i].h);
  2638. }
  2639. drm_mode_debug_printmodeline(adj_mode);
  2640. }
  2641. static void _sde_crtc_clear_all_blend_stages(struct sde_crtc *sde_crtc)
  2642. {
  2643. struct sde_crtc_mixer mixer;
  2644. /*
  2645. * Use mixer[0] to get hw_ctl which will use ops to clear
  2646. * all blendstages. Clear all blendstages will iterate through
  2647. * all mixers.
  2648. */
  2649. if (sde_crtc->num_mixers) {
  2650. mixer = sde_crtc->mixers[0];
  2651. if (mixer.hw_ctl && mixer.hw_ctl->ops.clear_all_blendstages)
  2652. mixer.hw_ctl->ops.clear_all_blendstages(mixer.hw_ctl);
  2653. if (mixer.hw_ctl && mixer.hw_ctl->ops.set_active_pipes)
  2654. mixer.hw_ctl->ops.set_active_pipes(mixer.hw_ctl, NULL);
  2655. }
  2656. }
  2657. static void sde_crtc_atomic_begin(struct drm_crtc *crtc,
  2658. struct drm_crtc_state *old_state)
  2659. {
  2660. struct sde_crtc *sde_crtc;
  2661. struct drm_encoder *encoder;
  2662. struct drm_device *dev;
  2663. struct sde_kms *sde_kms;
  2664. struct sde_splash_display *splash_display;
  2665. bool cont_splash_enabled = false;
  2666. size_t i;
  2667. if (!crtc) {
  2668. SDE_ERROR("invalid crtc\n");
  2669. return;
  2670. }
  2671. if (!crtc->state->enable) {
  2672. SDE_DEBUG("crtc%d -> enable %d, skip atomic_begin\n",
  2673. crtc->base.id, crtc->state->enable);
  2674. return;
  2675. }
  2676. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  2677. SDE_ERROR("power resource is not enabled\n");
  2678. return;
  2679. }
  2680. sde_kms = _sde_crtc_get_kms(crtc);
  2681. if (!sde_kms)
  2682. return;
  2683. SDE_ATRACE_BEGIN("crtc_atomic_begin");
  2684. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2685. sde_crtc = to_sde_crtc(crtc);
  2686. dev = crtc->dev;
  2687. if (!sde_crtc->num_mixers) {
  2688. _sde_crtc_setup_mixers(crtc);
  2689. _sde_crtc_setup_is_ppsplit(crtc->state);
  2690. _sde_crtc_setup_lm_bounds(crtc, crtc->state);
  2691. _sde_crtc_clear_all_blend_stages(sde_crtc);
  2692. }
  2693. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  2694. if (encoder->crtc != crtc)
  2695. continue;
  2696. /* encoder will trigger pending mask now */
  2697. sde_encoder_trigger_kickoff_pending(encoder);
  2698. }
  2699. /* update performance setting */
  2700. sde_core_perf_crtc_update(crtc, 1, false);
  2701. /*
  2702. * If no mixers have been allocated in sde_crtc_atomic_check(),
  2703. * it means we are trying to flush a CRTC whose state is disabled:
  2704. * nothing else needs to be done.
  2705. */
  2706. if (unlikely(!sde_crtc->num_mixers))
  2707. goto end;
  2708. _sde_crtc_blend_setup(crtc, old_state, true);
  2709. _sde_crtc_dest_scaler_setup(crtc);
  2710. /* cancel the idle notify delayed work */
  2711. if (sde_encoder_check_curr_mode(sde_crtc->mixers[0].encoder,
  2712. MSM_DISPLAY_VIDEO_MODE) &&
  2713. kthread_cancel_delayed_work_sync(&sde_crtc->idle_notify_work))
  2714. SDE_DEBUG("idle notify work cancelled\n");
  2715. /*
  2716. * Since CP properties use AXI buffer to program the
  2717. * HW, check if context bank is in attached state,
  2718. * apply color processing properties only if
  2719. * smmu state is attached,
  2720. */
  2721. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2722. splash_display = &sde_kms->splash_data.splash_display[i];
  2723. if (splash_display->cont_splash_enabled &&
  2724. splash_display->encoder &&
  2725. crtc == splash_display->encoder->crtc)
  2726. cont_splash_enabled = true;
  2727. }
  2728. if (sde_kms_is_cp_operation_allowed(sde_kms) &&
  2729. (cont_splash_enabled || sde_crtc->enabled))
  2730. sde_cp_crtc_apply_properties(crtc);
  2731. /*
  2732. * PP_DONE irq is only used by command mode for now.
  2733. * It is better to request pending before FLUSH and START trigger
  2734. * to make sure no pp_done irq missed.
  2735. * This is safe because no pp_done will happen before SW trigger
  2736. * in command mode.
  2737. */
  2738. end:
  2739. SDE_ATRACE_END("crtc_atomic_begin");
  2740. }
  2741. static void sde_crtc_atomic_flush(struct drm_crtc *crtc,
  2742. struct drm_crtc_state *old_crtc_state)
  2743. {
  2744. struct drm_encoder *encoder;
  2745. struct sde_crtc *sde_crtc;
  2746. struct drm_device *dev;
  2747. struct drm_plane *plane;
  2748. struct msm_drm_private *priv;
  2749. struct msm_drm_thread *event_thread;
  2750. struct sde_crtc_state *cstate;
  2751. struct sde_kms *sde_kms;
  2752. int idle_time = 0, i;
  2753. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  2754. SDE_ERROR("invalid crtc\n");
  2755. return;
  2756. }
  2757. if (!crtc->state->enable) {
  2758. SDE_DEBUG("crtc%d -> enable %d, skip atomic_flush\n",
  2759. crtc->base.id, crtc->state->enable);
  2760. return;
  2761. }
  2762. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  2763. SDE_ERROR("power resource is not enabled\n");
  2764. return;
  2765. }
  2766. sde_kms = _sde_crtc_get_kms(crtc);
  2767. if (!sde_kms) {
  2768. SDE_ERROR("invalid kms\n");
  2769. return;
  2770. }
  2771. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2772. sde_crtc = to_sde_crtc(crtc);
  2773. cstate = to_sde_crtc_state(crtc->state);
  2774. dev = crtc->dev;
  2775. priv = dev->dev_private;
  2776. if (crtc->index >= ARRAY_SIZE(priv->event_thread)) {
  2777. SDE_ERROR("invalid crtc index[%d]\n", crtc->index);
  2778. return;
  2779. }
  2780. event_thread = &priv->event_thread[crtc->index];
  2781. idle_time = sde_crtc_get_property(cstate, CRTC_PROP_IDLE_TIMEOUT);
  2782. if (sde_crtc_get_property(cstate, CRTC_PROP_CACHE_STATE))
  2783. sde_crtc_static_img_control(crtc, CACHE_STATE_FRAME_WRITE,
  2784. false);
  2785. else
  2786. sde_crtc_static_img_control(crtc, CACHE_STATE_NORMAL, false);
  2787. /*
  2788. * If no mixers has been allocated in sde_crtc_atomic_check(),
  2789. * it means we are trying to flush a CRTC whose state is disabled:
  2790. * nothing else needs to be done.
  2791. */
  2792. if (unlikely(!sde_crtc->num_mixers))
  2793. return;
  2794. SDE_ATRACE_BEGIN("sde_crtc_atomic_flush");
  2795. /*
  2796. * For planes without commit update, drm framework will not add
  2797. * those planes to current state since hardware update is not
  2798. * required. However, if those planes were power collapsed since
  2799. * last commit cycle, driver has to restore the hardware state
  2800. * of those planes explicitly here prior to plane flush.
  2801. * Also use this iteration to see if any plane requires cache,
  2802. * so during the perf update driver can activate/deactivate
  2803. * the cache accordingly.
  2804. */
  2805. for (i = 0; i < SDE_SYS_CACHE_MAX; i++)
  2806. sde_crtc->new_perf.llcc_active[i] = false;
  2807. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2808. sde_plane_restore(plane);
  2809. for (i = 0; i < SDE_SYS_CACHE_MAX; i++) {
  2810. if (sde_plane_is_cache_required(plane, i))
  2811. sde_crtc->new_perf.llcc_active[i] = true;
  2812. }
  2813. }
  2814. sde_core_perf_crtc_update_llcc(crtc);
  2815. /* wait for acquire fences before anything else is done */
  2816. _sde_crtc_wait_for_fences(crtc);
  2817. /* schedule the idle notify delayed work */
  2818. if (idle_time && sde_encoder_check_curr_mode(
  2819. sde_crtc->mixers[0].encoder,
  2820. MSM_DISPLAY_VIDEO_MODE)) {
  2821. kthread_queue_delayed_work(&event_thread->worker,
  2822. &sde_crtc->idle_notify_work,
  2823. msecs_to_jiffies(idle_time));
  2824. SDE_DEBUG("schedule idle notify work in %dms\n", idle_time);
  2825. }
  2826. if (!cstate->rsc_update) {
  2827. drm_for_each_encoder_mask(encoder, dev,
  2828. crtc->state->encoder_mask) {
  2829. cstate->rsc_client =
  2830. sde_encoder_get_rsc_client(encoder);
  2831. }
  2832. cstate->rsc_update = true;
  2833. }
  2834. /*
  2835. * Final plane updates: Give each plane a chance to complete all
  2836. * required writes/flushing before crtc's "flush
  2837. * everything" call below.
  2838. */
  2839. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2840. if (sde_kms->smmu_state.transition_error)
  2841. sde_plane_set_error(plane, true);
  2842. sde_plane_flush(plane);
  2843. }
  2844. /* Kickoff will be scheduled by outer layer */
  2845. SDE_ATRACE_END("sde_crtc_atomic_flush");
  2846. }
  2847. /**
  2848. * sde_crtc_destroy_state - state destroy hook
  2849. * @crtc: drm CRTC
  2850. * @state: CRTC state object to release
  2851. */
  2852. static void sde_crtc_destroy_state(struct drm_crtc *crtc,
  2853. struct drm_crtc_state *state)
  2854. {
  2855. struct sde_crtc *sde_crtc;
  2856. struct sde_crtc_state *cstate;
  2857. struct drm_encoder *enc;
  2858. struct sde_kms *sde_kms;
  2859. if (!crtc || !state) {
  2860. SDE_ERROR("invalid argument(s)\n");
  2861. return;
  2862. }
  2863. sde_crtc = to_sde_crtc(crtc);
  2864. cstate = to_sde_crtc_state(state);
  2865. sde_kms = _sde_crtc_get_kms(crtc);
  2866. if (!sde_kms) {
  2867. SDE_ERROR("invalid sde_kms\n");
  2868. return;
  2869. }
  2870. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2871. drm_for_each_encoder_mask(enc, crtc->dev, state->encoder_mask)
  2872. sde_rm_release(&sde_kms->rm, enc, true);
  2873. __drm_atomic_helper_crtc_destroy_state(state);
  2874. /* destroy value helper */
  2875. msm_property_destroy_state(&sde_crtc->property_info, cstate,
  2876. &cstate->property_state);
  2877. }
  2878. static int _sde_crtc_flush_event_thread(struct drm_crtc *crtc)
  2879. {
  2880. struct sde_crtc *sde_crtc;
  2881. int i;
  2882. if (!crtc) {
  2883. SDE_ERROR("invalid argument\n");
  2884. return -EINVAL;
  2885. }
  2886. sde_crtc = to_sde_crtc(crtc);
  2887. if (!atomic_read(&sde_crtc->frame_pending)) {
  2888. SDE_DEBUG("no frames pending\n");
  2889. return 0;
  2890. }
  2891. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_ENTRY);
  2892. /*
  2893. * flush all the event thread work to make sure all the
  2894. * FRAME_EVENTS from encoder are propagated to crtc
  2895. */
  2896. for (i = 0; i < ARRAY_SIZE(sde_crtc->frame_events); i++) {
  2897. if (list_empty(&sde_crtc->frame_events[i].list))
  2898. kthread_flush_work(&sde_crtc->frame_events[i].work);
  2899. }
  2900. SDE_EVT32_VERBOSE(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  2901. return 0;
  2902. }
  2903. /**
  2904. * _sde_crtc_remove_pipe_flush - remove staged pipes from flush mask
  2905. * @crtc: Pointer to crtc structure
  2906. */
  2907. static void _sde_crtc_remove_pipe_flush(struct drm_crtc *crtc)
  2908. {
  2909. struct drm_plane *plane;
  2910. struct drm_plane_state *state;
  2911. struct sde_crtc *sde_crtc;
  2912. struct sde_crtc_mixer *mixer;
  2913. struct sde_hw_ctl *ctl;
  2914. if (!crtc)
  2915. return;
  2916. sde_crtc = to_sde_crtc(crtc);
  2917. mixer = sde_crtc->mixers;
  2918. if (!mixer)
  2919. return;
  2920. ctl = mixer->hw_ctl;
  2921. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2922. state = plane->state;
  2923. if (!state)
  2924. continue;
  2925. /* clear plane flush bitmask */
  2926. sde_plane_ctl_flush(plane, ctl, false);
  2927. }
  2928. }
  2929. /**
  2930. * sde_crtc_reset_hw - attempt hardware reset on errors
  2931. * @crtc: Pointer to DRM crtc instance
  2932. * @old_state: Pointer to crtc state for previous commit
  2933. * @recovery_events: Whether or not recovery events are enabled
  2934. * Returns: Zero if current commit should still be attempted
  2935. */
  2936. int sde_crtc_reset_hw(struct drm_crtc *crtc, struct drm_crtc_state *old_state,
  2937. bool recovery_events)
  2938. {
  2939. struct drm_plane *plane_halt[MAX_PLANES];
  2940. struct drm_plane *plane;
  2941. struct drm_encoder *encoder;
  2942. struct sde_crtc *sde_crtc;
  2943. struct sde_crtc_state *cstate;
  2944. struct sde_hw_ctl *ctl;
  2945. signed int i, plane_count;
  2946. int rc;
  2947. if (!crtc || !crtc->dev || !old_state || !crtc->state)
  2948. return -EINVAL;
  2949. sde_crtc = to_sde_crtc(crtc);
  2950. cstate = to_sde_crtc_state(crtc->state);
  2951. SDE_EVT32(DRMID(crtc), recovery_events, SDE_EVTLOG_FUNC_ENTRY);
  2952. /* optionally generate a panic instead of performing a h/w reset */
  2953. SDE_DBG_CTRL("stop_ftrace", "reset_hw_panic");
  2954. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  2955. ctl = sde_crtc->mixers[i].hw_ctl;
  2956. if (!ctl || !ctl->ops.reset)
  2957. continue;
  2958. rc = ctl->ops.reset(ctl);
  2959. if (rc) {
  2960. SDE_DEBUG("crtc%d: ctl%d reset failure\n",
  2961. crtc->base.id, ctl->idx - CTL_0);
  2962. SDE_EVT32(DRMID(crtc), ctl->idx - CTL_0,
  2963. SDE_EVTLOG_ERROR);
  2964. break;
  2965. }
  2966. }
  2967. /* Early out if simple ctl reset succeeded */
  2968. if (i == sde_crtc->num_ctls)
  2969. return 0;
  2970. SDE_DEBUG("crtc%d: issuing hard reset\n", DRMID(crtc));
  2971. /* force all components in the system into reset at the same time */
  2972. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  2973. ctl = sde_crtc->mixers[i].hw_ctl;
  2974. if (!ctl || !ctl->ops.hard_reset)
  2975. continue;
  2976. SDE_EVT32(DRMID(crtc), ctl->idx - CTL_0);
  2977. ctl->ops.hard_reset(ctl, true);
  2978. }
  2979. plane_count = 0;
  2980. drm_atomic_crtc_state_for_each_plane(plane, old_state) {
  2981. if (plane_count >= ARRAY_SIZE(plane_halt))
  2982. break;
  2983. plane_halt[plane_count++] = plane;
  2984. sde_plane_halt_requests(plane, true);
  2985. sde_plane_set_revalidate(plane, true);
  2986. }
  2987. /* provide safe "border color only" commit configuration for later */
  2988. _sde_crtc_remove_pipe_flush(crtc);
  2989. _sde_crtc_blend_setup(crtc, old_state, false);
  2990. /* take h/w components out of reset */
  2991. for (i = plane_count - 1; i >= 0; --i)
  2992. sde_plane_halt_requests(plane_halt[i], false);
  2993. /* attempt to poll for start of frame cycle before reset release */
  2994. list_for_each_entry(encoder,
  2995. &crtc->dev->mode_config.encoder_list, head) {
  2996. if (encoder->crtc != crtc)
  2997. continue;
  2998. if (sde_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
  2999. sde_encoder_poll_line_counts(encoder);
  3000. }
  3001. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  3002. ctl = sde_crtc->mixers[i].hw_ctl;
  3003. if (!ctl || !ctl->ops.hard_reset)
  3004. continue;
  3005. ctl->ops.hard_reset(ctl, false);
  3006. }
  3007. list_for_each_entry(encoder,
  3008. &crtc->dev->mode_config.encoder_list, head) {
  3009. if (encoder->crtc != crtc)
  3010. continue;
  3011. if (sde_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
  3012. sde_encoder_kickoff(encoder, false);
  3013. }
  3014. /* panic the device if VBIF is not in good state */
  3015. return !recovery_events ? 0 : -EAGAIN;
  3016. }
  3017. void sde_crtc_commit_kickoff(struct drm_crtc *crtc,
  3018. struct drm_crtc_state *old_state)
  3019. {
  3020. struct drm_encoder *encoder;
  3021. struct drm_device *dev;
  3022. struct sde_crtc *sde_crtc;
  3023. struct msm_drm_private *priv;
  3024. struct sde_kms *sde_kms;
  3025. struct sde_crtc_state *cstate;
  3026. bool is_error = false;
  3027. unsigned long flags;
  3028. enum sde_crtc_idle_pc_state idle_pc_state;
  3029. struct sde_encoder_kickoff_params params = { 0 };
  3030. if (!crtc) {
  3031. SDE_ERROR("invalid argument\n");
  3032. return;
  3033. }
  3034. dev = crtc->dev;
  3035. sde_crtc = to_sde_crtc(crtc);
  3036. sde_kms = _sde_crtc_get_kms(crtc);
  3037. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) {
  3038. SDE_ERROR("invalid argument\n");
  3039. return;
  3040. }
  3041. priv = sde_kms->dev->dev_private;
  3042. cstate = to_sde_crtc_state(crtc->state);
  3043. /*
  3044. * If no mixers has been allocated in sde_crtc_atomic_check(),
  3045. * it means we are trying to start a CRTC whose state is disabled:
  3046. * nothing else needs to be done.
  3047. */
  3048. if (unlikely(!sde_crtc->num_mixers))
  3049. return;
  3050. SDE_ATRACE_BEGIN("crtc_commit");
  3051. idle_pc_state = sde_crtc_get_property(cstate, CRTC_PROP_IDLE_PC_STATE);
  3052. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  3053. if (encoder->crtc != crtc)
  3054. continue;
  3055. /*
  3056. * Encoder will flush/start now, unless it has a tx pending.
  3057. * If so, it may delay and flush at an irq event (e.g. ppdone)
  3058. */
  3059. params.affected_displays = _sde_crtc_get_displays_affected(crtc,
  3060. crtc->state);
  3061. if (sde_encoder_prepare_for_kickoff(encoder, &params))
  3062. sde_crtc->needs_hw_reset = true;
  3063. if (idle_pc_state != IDLE_PC_NONE)
  3064. sde_encoder_control_idle_pc(encoder,
  3065. (idle_pc_state == IDLE_PC_ENABLE) ? true : false);
  3066. }
  3067. /*
  3068. * Optionally attempt h/w recovery if any errors were detected while
  3069. * preparing for the kickoff
  3070. */
  3071. if (sde_crtc->needs_hw_reset) {
  3072. sde_crtc->frame_trigger_mode = params.frame_trigger_mode;
  3073. if (sde_crtc->frame_trigger_mode
  3074. != FRAME_DONE_WAIT_POSTED_START &&
  3075. sde_crtc_reset_hw(crtc, old_state,
  3076. params.recovery_events_enabled))
  3077. is_error = true;
  3078. sde_crtc->needs_hw_reset = false;
  3079. }
  3080. sde_crtc_calc_fps(sde_crtc);
  3081. SDE_ATRACE_BEGIN("flush_event_thread");
  3082. _sde_crtc_flush_event_thread(crtc);
  3083. SDE_ATRACE_END("flush_event_thread");
  3084. sde_crtc->plane_mask_old = crtc->state->plane_mask;
  3085. if (atomic_inc_return(&sde_crtc->frame_pending) == 1) {
  3086. /* acquire bandwidth and other resources */
  3087. SDE_DEBUG("crtc%d first commit\n", crtc->base.id);
  3088. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_CASE1);
  3089. } else {
  3090. SDE_DEBUG("crtc%d commit\n", crtc->base.id);
  3091. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_CASE2);
  3092. }
  3093. sde_crtc->play_count++;
  3094. sde_vbif_clear_errors(sde_kms);
  3095. if (is_error) {
  3096. _sde_crtc_remove_pipe_flush(crtc);
  3097. _sde_crtc_blend_setup(crtc, old_state, false);
  3098. }
  3099. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  3100. if (encoder->crtc != crtc)
  3101. continue;
  3102. sde_encoder_kickoff(encoder, false);
  3103. }
  3104. /* store the event after frame trigger */
  3105. if (sde_crtc->event) {
  3106. WARN_ON(sde_crtc->event);
  3107. } else {
  3108. spin_lock_irqsave(&dev->event_lock, flags);
  3109. sde_crtc->event = crtc->state->event;
  3110. spin_unlock_irqrestore(&dev->event_lock, flags);
  3111. }
  3112. SDE_ATRACE_END("crtc_commit");
  3113. }
  3114. /**
  3115. * _sde_crtc_vblank_enable_no_lock - update power resource and vblank request
  3116. * @sde_crtc: Pointer to sde crtc structure
  3117. * @enable: Whether to enable/disable vblanks
  3118. *
  3119. * @Return: error code
  3120. */
  3121. static int _sde_crtc_vblank_enable_no_lock(
  3122. struct sde_crtc *sde_crtc, bool enable)
  3123. {
  3124. struct drm_crtc *crtc;
  3125. struct drm_encoder *enc;
  3126. if (!sde_crtc) {
  3127. SDE_ERROR("invalid crtc\n");
  3128. return -EINVAL;
  3129. }
  3130. crtc = &sde_crtc->base;
  3131. if (enable) {
  3132. int ret;
  3133. /* drop lock since power crtc cb may try to re-acquire lock */
  3134. mutex_unlock(&sde_crtc->crtc_lock);
  3135. ret = pm_runtime_get_sync(crtc->dev->dev);
  3136. mutex_lock(&sde_crtc->crtc_lock);
  3137. if (ret < 0)
  3138. return ret;
  3139. drm_for_each_encoder_mask(enc, crtc->dev,
  3140. crtc->state->encoder_mask) {
  3141. SDE_EVT32(DRMID(&sde_crtc->base), DRMID(enc), enable,
  3142. sde_crtc->enabled);
  3143. sde_encoder_register_vblank_callback(enc,
  3144. sde_crtc_vblank_cb, (void *)crtc);
  3145. }
  3146. } else {
  3147. drm_for_each_encoder_mask(enc, crtc->dev,
  3148. crtc->state->encoder_mask) {
  3149. SDE_EVT32(DRMID(&sde_crtc->base), DRMID(enc), enable,
  3150. sde_crtc->enabled);
  3151. sde_encoder_register_vblank_callback(enc, NULL, NULL);
  3152. }
  3153. /* drop lock since power crtc cb may try to re-acquire lock */
  3154. mutex_unlock(&sde_crtc->crtc_lock);
  3155. pm_runtime_put_sync(crtc->dev->dev);
  3156. mutex_lock(&sde_crtc->crtc_lock);
  3157. }
  3158. return 0;
  3159. }
  3160. /**
  3161. * sde_crtc_duplicate_state - state duplicate hook
  3162. * @crtc: Pointer to drm crtc structure
  3163. * @Returns: Pointer to new drm_crtc_state structure
  3164. */
  3165. static struct drm_crtc_state *sde_crtc_duplicate_state(struct drm_crtc *crtc)
  3166. {
  3167. struct sde_crtc *sde_crtc;
  3168. struct sde_crtc_state *cstate, *old_cstate;
  3169. if (!crtc || !crtc->state) {
  3170. SDE_ERROR("invalid argument(s)\n");
  3171. return NULL;
  3172. }
  3173. sde_crtc = to_sde_crtc(crtc);
  3174. old_cstate = to_sde_crtc_state(crtc->state);
  3175. cstate = msm_property_alloc_state(&sde_crtc->property_info);
  3176. if (!cstate) {
  3177. SDE_ERROR("failed to allocate state\n");
  3178. return NULL;
  3179. }
  3180. /* duplicate value helper */
  3181. msm_property_duplicate_state(&sde_crtc->property_info,
  3182. old_cstate, cstate,
  3183. &cstate->property_state, cstate->property_values);
  3184. /* clear destination scaler dirty bit */
  3185. clear_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  3186. /* duplicate base helper */
  3187. __drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base);
  3188. return &cstate->base;
  3189. }
  3190. /**
  3191. * sde_crtc_reset - reset hook for CRTCs
  3192. * Resets the atomic state for @crtc by freeing the state pointer (which might
  3193. * be NULL, e.g. at driver load time) and allocating a new empty state object.
  3194. * @crtc: Pointer to drm crtc structure
  3195. */
  3196. static void sde_crtc_reset(struct drm_crtc *crtc)
  3197. {
  3198. struct sde_crtc *sde_crtc;
  3199. struct sde_crtc_state *cstate;
  3200. if (!crtc) {
  3201. SDE_ERROR("invalid crtc\n");
  3202. return;
  3203. }
  3204. /* revert suspend actions, if necessary */
  3205. if (!sde_crtc_is_reset_required(crtc)) {
  3206. SDE_DEBUG("avoiding reset for crtc:%d\n", crtc->base.id);
  3207. return;
  3208. }
  3209. /* remove previous state, if present */
  3210. if (crtc->state) {
  3211. sde_crtc_destroy_state(crtc, crtc->state);
  3212. crtc->state = 0;
  3213. }
  3214. sde_crtc = to_sde_crtc(crtc);
  3215. cstate = msm_property_alloc_state(&sde_crtc->property_info);
  3216. if (!cstate) {
  3217. SDE_ERROR("failed to allocate state\n");
  3218. return;
  3219. }
  3220. /* reset value helper */
  3221. msm_property_reset_state(&sde_crtc->property_info, cstate,
  3222. &cstate->property_state,
  3223. cstate->property_values);
  3224. _sde_crtc_set_input_fence_timeout(cstate);
  3225. cstate->base.crtc = crtc;
  3226. crtc->state = &cstate->base;
  3227. }
  3228. static void sde_crtc_handle_power_event(u32 event_type, void *arg)
  3229. {
  3230. struct drm_crtc *crtc = arg;
  3231. struct sde_crtc *sde_crtc;
  3232. struct sde_crtc_state *cstate;
  3233. struct drm_plane *plane;
  3234. struct drm_encoder *encoder;
  3235. u32 power_on;
  3236. unsigned long flags;
  3237. struct sde_crtc_irq_info *node = NULL;
  3238. int ret = 0;
  3239. struct drm_event event;
  3240. if (!crtc) {
  3241. SDE_ERROR("invalid crtc\n");
  3242. return;
  3243. }
  3244. sde_crtc = to_sde_crtc(crtc);
  3245. cstate = to_sde_crtc_state(crtc->state);
  3246. mutex_lock(&sde_crtc->crtc_lock);
  3247. SDE_EVT32(DRMID(crtc), event_type);
  3248. switch (event_type) {
  3249. case SDE_POWER_EVENT_POST_ENABLE:
  3250. /* restore encoder; crtc will be programmed during commit */
  3251. drm_for_each_encoder_mask(encoder, crtc->dev,
  3252. crtc->state->encoder_mask) {
  3253. sde_encoder_virt_restore(encoder);
  3254. }
  3255. /* restore UIDLE */
  3256. sde_core_perf_crtc_update_uidle(crtc, true);
  3257. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3258. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3259. ret = 0;
  3260. if (node->func)
  3261. ret = node->func(crtc, true, &node->irq);
  3262. if (ret)
  3263. SDE_ERROR("%s failed to enable event %x\n",
  3264. sde_crtc->name, node->event);
  3265. }
  3266. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3267. sde_cp_crtc_post_ipc(crtc);
  3268. break;
  3269. case SDE_POWER_EVENT_PRE_DISABLE:
  3270. drm_for_each_encoder_mask(encoder, crtc->dev,
  3271. crtc->state->encoder_mask) {
  3272. /*
  3273. * disable the vsync source after updating the
  3274. * rsc state. rsc state update might have vsync wait
  3275. * and vsync source must be disabled after it.
  3276. * It will avoid generating any vsync from this point
  3277. * till mode-2 entry. It is SW workaround for HW
  3278. * limitation and should not be removed without
  3279. * checking the updated design.
  3280. */
  3281. sde_encoder_control_te(encoder, false);
  3282. }
  3283. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3284. node = NULL;
  3285. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3286. ret = 0;
  3287. if (node->func)
  3288. ret = node->func(crtc, false, &node->irq);
  3289. if (ret)
  3290. SDE_ERROR("%s failed to disable event %x\n",
  3291. sde_crtc->name, node->event);
  3292. }
  3293. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3294. sde_cp_crtc_pre_ipc(crtc);
  3295. break;
  3296. case SDE_POWER_EVENT_POST_DISABLE:
  3297. /*
  3298. * set revalidate flag in planes, so it will be re-programmed
  3299. * in the next frame update
  3300. */
  3301. drm_atomic_crtc_for_each_plane(plane, crtc)
  3302. sde_plane_set_revalidate(plane, true);
  3303. sde_cp_crtc_suspend(crtc);
  3304. /* reconfigure everything on next frame update */
  3305. bitmap_fill(cstate->dirty, SDE_CRTC_DIRTY_MAX);
  3306. event.type = DRM_EVENT_SDE_POWER;
  3307. event.length = sizeof(power_on);
  3308. power_on = 0;
  3309. msm_mode_object_event_notify(&crtc->base, crtc->dev, &event,
  3310. (u8 *)&power_on);
  3311. break;
  3312. default:
  3313. SDE_DEBUG("event:%d not handled\n", event_type);
  3314. break;
  3315. }
  3316. mutex_unlock(&sde_crtc->crtc_lock);
  3317. }
  3318. static void _sde_crtc_reset(struct drm_crtc *crtc)
  3319. {
  3320. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  3321. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
  3322. memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers));
  3323. sde_crtc->num_mixers = 0;
  3324. sde_crtc->mixers_swapped = false;
  3325. /* disable clk & bw control until clk & bw properties are set */
  3326. cstate->bw_control = false;
  3327. cstate->bw_split_vote = false;
  3328. sde_crtc_static_img_control(crtc, CACHE_STATE_DISABLED, false);
  3329. }
  3330. static void sde_crtc_disable(struct drm_crtc *crtc)
  3331. {
  3332. struct sde_kms *sde_kms;
  3333. struct sde_crtc *sde_crtc;
  3334. struct sde_crtc_state *cstate;
  3335. struct drm_encoder *encoder;
  3336. struct msm_drm_private *priv;
  3337. unsigned long flags;
  3338. struct sde_crtc_irq_info *node = NULL;
  3339. struct drm_event event;
  3340. u32 power_on;
  3341. bool in_cont_splash = false;
  3342. int ret, i;
  3343. if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) {
  3344. SDE_ERROR("invalid crtc\n");
  3345. return;
  3346. }
  3347. sde_kms = _sde_crtc_get_kms(crtc);
  3348. if (!sde_kms) {
  3349. SDE_ERROR("invalid kms\n");
  3350. return;
  3351. }
  3352. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  3353. SDE_ERROR("power resource is not enabled\n");
  3354. return;
  3355. }
  3356. sde_crtc = to_sde_crtc(crtc);
  3357. cstate = to_sde_crtc_state(crtc->state);
  3358. priv = crtc->dev->dev_private;
  3359. SDE_DEBUG("crtc%d\n", crtc->base.id);
  3360. drm_crtc_vblank_off(crtc);
  3361. mutex_lock(&sde_crtc->crtc_lock);
  3362. SDE_EVT32_VERBOSE(DRMID(crtc));
  3363. /* update color processing on suspend */
  3364. event.type = DRM_EVENT_CRTC_POWER;
  3365. event.length = sizeof(u32);
  3366. sde_cp_crtc_suspend(crtc);
  3367. power_on = 0;
  3368. msm_mode_object_event_notify(&crtc->base, crtc->dev, &event,
  3369. (u8 *)&power_on);
  3370. bitmap_fill(cstate->dirty, SDE_CRTC_DIRTY_MAX);
  3371. _sde_crtc_flush_event_thread(crtc);
  3372. SDE_EVT32(DRMID(crtc), sde_crtc->enabled,
  3373. crtc->state->active, crtc->state->enable);
  3374. sde_crtc->enabled = false;
  3375. /* Try to disable uidle */
  3376. sde_core_perf_crtc_update_uidle(crtc, false);
  3377. if (atomic_read(&sde_crtc->frame_pending)) {
  3378. SDE_ERROR("crtc%d frame_pending%d\n", crtc->base.id,
  3379. atomic_read(&sde_crtc->frame_pending));
  3380. SDE_EVT32(DRMID(crtc), atomic_read(&sde_crtc->frame_pending),
  3381. SDE_EVTLOG_FUNC_CASE2);
  3382. sde_core_perf_crtc_release_bw(crtc);
  3383. atomic_set(&sde_crtc->frame_pending, 0);
  3384. }
  3385. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3386. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3387. ret = 0;
  3388. if (node->func)
  3389. ret = node->func(crtc, false, &node->irq);
  3390. if (ret)
  3391. SDE_ERROR("%s failed to disable event %x\n",
  3392. sde_crtc->name, node->event);
  3393. }
  3394. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3395. drm_for_each_encoder_mask(encoder, crtc->dev,
  3396. crtc->state->encoder_mask) {
  3397. if (sde_encoder_in_cont_splash(encoder)) {
  3398. in_cont_splash = true;
  3399. break;
  3400. }
  3401. }
  3402. /* avoid clk/bw downvote if cont-splash is enabled */
  3403. if (!in_cont_splash)
  3404. sde_core_perf_crtc_update(crtc, 0, true);
  3405. drm_for_each_encoder_mask(encoder, crtc->dev,
  3406. crtc->state->encoder_mask) {
  3407. sde_encoder_register_frame_event_callback(encoder, NULL, NULL);
  3408. cstate->rsc_client = NULL;
  3409. cstate->rsc_update = false;
  3410. /*
  3411. * reset idle power-collapse to original state during suspend;
  3412. * user-mode will change the state on resume, if required
  3413. */
  3414. if (sde_kms->catalog->has_idle_pc)
  3415. sde_encoder_control_idle_pc(encoder, true);
  3416. }
  3417. if (sde_crtc->power_event)
  3418. sde_power_handle_unregister_event(&priv->phandle,
  3419. sde_crtc->power_event);
  3420. /**
  3421. * All callbacks are unregistered and frame done waits are complete
  3422. * at this point. No buffers are accessed by hardware.
  3423. * reset the fence timeline if crtc will not be enabled for this commit
  3424. */
  3425. if (!crtc->state->active || !crtc->state->enable) {
  3426. sde_fence_signal(sde_crtc->output_fence,
  3427. ktime_get(), SDE_FENCE_RESET_TIMELINE);
  3428. for (i = 0; i < cstate->num_connectors; ++i)
  3429. sde_connector_commit_reset(cstate->connectors[i],
  3430. ktime_get());
  3431. }
  3432. _sde_crtc_reset(crtc);
  3433. mutex_unlock(&sde_crtc->crtc_lock);
  3434. }
  3435. static void sde_crtc_enable(struct drm_crtc *crtc,
  3436. struct drm_crtc_state *old_crtc_state)
  3437. {
  3438. struct sde_crtc *sde_crtc;
  3439. struct drm_encoder *encoder;
  3440. struct msm_drm_private *priv;
  3441. unsigned long flags;
  3442. struct sde_crtc_irq_info *node = NULL;
  3443. struct drm_event event;
  3444. u32 power_on;
  3445. int ret, i;
  3446. struct sde_crtc_state *cstate;
  3447. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  3448. SDE_ERROR("invalid crtc\n");
  3449. return;
  3450. }
  3451. priv = crtc->dev->dev_private;
  3452. cstate = to_sde_crtc_state(crtc->state);
  3453. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  3454. SDE_ERROR("power resource is not enabled\n");
  3455. return;
  3456. }
  3457. SDE_DEBUG("crtc%d\n", crtc->base.id);
  3458. SDE_EVT32_VERBOSE(DRMID(crtc));
  3459. sde_crtc = to_sde_crtc(crtc);
  3460. /*
  3461. * Avoid drm_crtc_vblank_on during seamless DMS case
  3462. * when CRTC is already in enabled state
  3463. */
  3464. if (!sde_crtc->enabled)
  3465. drm_crtc_vblank_on(crtc);
  3466. mutex_lock(&sde_crtc->crtc_lock);
  3467. SDE_EVT32(DRMID(crtc), sde_crtc->enabled);
  3468. /*
  3469. * Try to enable uidle (if possible), we do this before the call
  3470. * to return early during seamless dms mode, so any fps
  3471. * change is also consider to enable/disable UIDLE
  3472. */
  3473. sde_core_perf_crtc_update_uidle(crtc, true);
  3474. /* return early if crtc is already enabled, do this after UIDLE check */
  3475. if (sde_crtc->enabled) {
  3476. if (msm_is_mode_seamless_dms(&crtc->state->adjusted_mode) ||
  3477. msm_is_mode_seamless_dyn_clk(&crtc->state->adjusted_mode))
  3478. SDE_DEBUG("%s extra crtc enable expected during DMS\n",
  3479. sde_crtc->name);
  3480. else
  3481. WARN(1, "%s unexpected crtc enable\n", sde_crtc->name);
  3482. mutex_unlock(&sde_crtc->crtc_lock);
  3483. return;
  3484. }
  3485. drm_for_each_encoder_mask(encoder, crtc->dev,
  3486. crtc->state->encoder_mask) {
  3487. sde_encoder_register_frame_event_callback(encoder,
  3488. sde_crtc_frame_event_cb, crtc);
  3489. sde_crtc_static_img_control(crtc, CACHE_STATE_NORMAL,
  3490. sde_encoder_check_curr_mode(encoder,
  3491. MSM_DISPLAY_VIDEO_MODE));
  3492. }
  3493. sde_crtc->enabled = true;
  3494. /* update color processing on resume */
  3495. event.type = DRM_EVENT_CRTC_POWER;
  3496. event.length = sizeof(u32);
  3497. sde_cp_crtc_resume(crtc);
  3498. power_on = 1;
  3499. msm_mode_object_event_notify(&crtc->base, crtc->dev, &event,
  3500. (u8 *)&power_on);
  3501. mutex_unlock(&sde_crtc->crtc_lock);
  3502. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3503. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3504. ret = 0;
  3505. if (node->func)
  3506. ret = node->func(crtc, true, &node->irq);
  3507. if (ret)
  3508. SDE_ERROR("%s failed to enable event %x\n",
  3509. sde_crtc->name, node->event);
  3510. }
  3511. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3512. sde_crtc->power_event = sde_power_handle_register_event(
  3513. &priv->phandle,
  3514. SDE_POWER_EVENT_POST_ENABLE | SDE_POWER_EVENT_POST_DISABLE |
  3515. SDE_POWER_EVENT_PRE_DISABLE,
  3516. sde_crtc_handle_power_event, crtc, sde_crtc->name);
  3517. /* Enable ESD thread */
  3518. for (i = 0; i < cstate->num_connectors; i++)
  3519. sde_connector_schedule_status_work(cstate->connectors[i], true);
  3520. }
  3521. /* no input validation - caller API has all the checks */
  3522. static int _sde_crtc_excl_dim_layer_check(struct drm_crtc_state *state,
  3523. struct plane_state pstates[], int cnt)
  3524. {
  3525. struct sde_crtc_state *cstate = to_sde_crtc_state(state);
  3526. struct drm_display_mode *mode = &state->adjusted_mode;
  3527. const struct drm_plane_state *pstate;
  3528. struct sde_plane_state *sde_pstate;
  3529. int rc = 0, i;
  3530. /* Check dim layer rect bounds and stage */
  3531. for (i = 0; i < cstate->num_dim_layers; i++) {
  3532. if ((CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.y,
  3533. cstate->dim_layer[i].rect.h, mode->vdisplay)) ||
  3534. (CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.x,
  3535. cstate->dim_layer[i].rect.w, mode->hdisplay)) ||
  3536. (cstate->dim_layer[i].stage >= SDE_STAGE_MAX) ||
  3537. (!cstate->dim_layer[i].rect.w) ||
  3538. (!cstate->dim_layer[i].rect.h)) {
  3539. SDE_ERROR("invalid dim_layer:{%d,%d,%d,%d}, stage:%d\n",
  3540. cstate->dim_layer[i].rect.x,
  3541. cstate->dim_layer[i].rect.y,
  3542. cstate->dim_layer[i].rect.w,
  3543. cstate->dim_layer[i].rect.h,
  3544. cstate->dim_layer[i].stage);
  3545. SDE_ERROR("display: %dx%d\n", mode->hdisplay,
  3546. mode->vdisplay);
  3547. rc = -E2BIG;
  3548. goto end;
  3549. }
  3550. }
  3551. /* log all src and excl_rect, useful for debugging */
  3552. for (i = 0; i < cnt; i++) {
  3553. pstate = pstates[i].drm_pstate;
  3554. sde_pstate = to_sde_plane_state(pstate);
  3555. SDE_DEBUG("p %d z %d src{%d,%d,%d,%d} excl_rect{%d,%d,%d,%d}\n",
  3556. pstate->plane->base.id, pstates[i].stage,
  3557. pstate->crtc_x, pstate->crtc_y,
  3558. pstate->crtc_w, pstate->crtc_h,
  3559. sde_pstate->excl_rect.x, sde_pstate->excl_rect.y,
  3560. sde_pstate->excl_rect.w, sde_pstate->excl_rect.h);
  3561. }
  3562. end:
  3563. return rc;
  3564. }
  3565. static int _sde_crtc_check_secure_blend_config(struct drm_crtc *crtc,
  3566. struct drm_crtc_state *state, struct plane_state pstates[],
  3567. struct sde_crtc_state *cstate, struct sde_kms *sde_kms,
  3568. int cnt, int secure, int fb_ns, int fb_sec, int fb_sec_dir)
  3569. {
  3570. struct drm_plane *plane;
  3571. int i;
  3572. if (secure == SDE_DRM_SEC_ONLY) {
  3573. /*
  3574. * validate planes - only fb_sec_dir is allowed during sec_crtc
  3575. * - fb_sec_dir is for secure camera preview and
  3576. * secure display use case
  3577. * - fb_sec is for secure video playback
  3578. * - fb_ns is for normal non secure use cases
  3579. */
  3580. if (fb_ns || fb_sec) {
  3581. SDE_ERROR(
  3582. "crtc%d: invalid fb_modes Sec:%d, NS:%d, Sec_Dir:%d\n",
  3583. DRMID(crtc), fb_sec, fb_ns, fb_sec_dir);
  3584. return -EINVAL;
  3585. }
  3586. /*
  3587. * - only one blending stage is allowed in sec_crtc
  3588. * - validate if pipe is allowed for sec-ui updates
  3589. */
  3590. for (i = 1; i < cnt; i++) {
  3591. if (!pstates[i].drm_pstate
  3592. || !pstates[i].drm_pstate->plane) {
  3593. SDE_ERROR("crtc%d: invalid pstate at i:%d\n",
  3594. DRMID(crtc), i);
  3595. return -EINVAL;
  3596. }
  3597. plane = pstates[i].drm_pstate->plane;
  3598. if (!sde_plane_is_sec_ui_allowed(plane)) {
  3599. SDE_ERROR("crtc%d: sec-ui not allowed in p%d\n",
  3600. DRMID(crtc), plane->base.id);
  3601. return -EINVAL;
  3602. } else if (pstates[i].stage != pstates[i-1].stage) {
  3603. SDE_ERROR(
  3604. "crtc%d: invalid blend stages %d:%d, %d:%d\n",
  3605. DRMID(crtc), i, pstates[i].stage,
  3606. i-1, pstates[i-1].stage);
  3607. return -EINVAL;
  3608. }
  3609. }
  3610. /* check if all the dim_layers are in the same stage */
  3611. for (i = 1; i < cstate->num_dim_layers; i++) {
  3612. if (cstate->dim_layer[i].stage !=
  3613. cstate->dim_layer[i-1].stage) {
  3614. SDE_ERROR(
  3615. "crtc%d: invalid dimlayer stage %d:%d, %d:%d\n",
  3616. DRMID(crtc),
  3617. i, cstate->dim_layer[i].stage,
  3618. i-1, cstate->dim_layer[i-1].stage);
  3619. return -EINVAL;
  3620. }
  3621. }
  3622. /*
  3623. * if secure-ui supported blendstage is specified,
  3624. * - fail empty commit
  3625. * - validate dim_layer or plane is staged in the supported
  3626. * blendstage
  3627. */
  3628. if (sde_kms->catalog->sui_supported_blendstage) {
  3629. int sec_stage = cnt ? pstates[0].sde_pstate->stage :
  3630. cstate->dim_layer[0].stage;
  3631. if (!sde_kms->catalog->has_base_layer)
  3632. sec_stage -= SDE_STAGE_0;
  3633. if ((!cnt && !cstate->num_dim_layers) ||
  3634. (sde_kms->catalog->sui_supported_blendstage
  3635. != sec_stage)) {
  3636. SDE_ERROR(
  3637. "crtc%d: empty cnt%d/dim%d or bad stage%d\n",
  3638. DRMID(crtc), cnt,
  3639. cstate->num_dim_layers, sec_stage);
  3640. return -EINVAL;
  3641. }
  3642. }
  3643. }
  3644. return 0;
  3645. }
  3646. static int _sde_crtc_check_secure_single_encoder(struct drm_crtc *crtc,
  3647. struct drm_crtc_state *state, int fb_sec_dir)
  3648. {
  3649. struct drm_encoder *encoder;
  3650. int encoder_cnt = 0;
  3651. if (fb_sec_dir) {
  3652. drm_for_each_encoder_mask(encoder, crtc->dev,
  3653. state->encoder_mask)
  3654. encoder_cnt++;
  3655. if (encoder_cnt > MAX_ALLOWED_ENCODER_CNT_PER_SECURE_CRTC) {
  3656. SDE_ERROR("crtc:%d invalid number of encoders:%d\n",
  3657. DRMID(crtc), encoder_cnt);
  3658. return -EINVAL;
  3659. }
  3660. }
  3661. return 0;
  3662. }
  3663. static int _sde_crtc_check_secure_state_smmu_translation(struct drm_crtc *crtc,
  3664. struct drm_crtc_state *state, struct sde_kms *sde_kms, int secure,
  3665. int fb_ns, int fb_sec, int fb_sec_dir)
  3666. {
  3667. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  3668. struct drm_encoder *encoder;
  3669. int is_video_mode = false;
  3670. drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) {
  3671. if (sde_encoder_is_dsi_display(encoder))
  3672. is_video_mode |= sde_encoder_check_curr_mode(encoder,
  3673. MSM_DISPLAY_VIDEO_MODE);
  3674. }
  3675. /*
  3676. * Secure display to secure camera needs without direct
  3677. * transition is currently not allowed
  3678. */
  3679. if (fb_sec_dir && secure == SDE_DRM_SEC_NON_SEC &&
  3680. smmu_state->state != ATTACHED &&
  3681. smmu_state->secure_level == SDE_DRM_SEC_ONLY) {
  3682. SDE_EVT32(DRMID(crtc), fb_ns, fb_sec_dir,
  3683. smmu_state->state, smmu_state->secure_level,
  3684. secure);
  3685. goto sec_err;
  3686. }
  3687. /*
  3688. * In video mode check for null commit before transition
  3689. * from secure to non secure and vice versa
  3690. */
  3691. if (is_video_mode && smmu_state &&
  3692. state->plane_mask && crtc->state->plane_mask &&
  3693. ((fb_sec_dir && ((smmu_state->state == ATTACHED) &&
  3694. (secure == SDE_DRM_SEC_ONLY))) ||
  3695. (fb_ns && ((smmu_state->state == DETACHED) ||
  3696. (smmu_state->state == DETACH_ALL_REQ))) ||
  3697. (fb_ns && ((smmu_state->state == DETACHED_SEC) ||
  3698. (smmu_state->state == DETACH_SEC_REQ)) &&
  3699. (smmu_state->secure_level == SDE_DRM_SEC_ONLY)))) {
  3700. SDE_EVT32(DRMID(crtc), fb_ns, fb_sec_dir,
  3701. smmu_state->state, smmu_state->secure_level,
  3702. secure, crtc->state->plane_mask, state->plane_mask);
  3703. goto sec_err;
  3704. }
  3705. return 0;
  3706. sec_err:
  3707. SDE_ERROR(
  3708. "crtc%d Invalid transition;sec%d state%d slvl%d ns%d sdir%d\n",
  3709. DRMID(crtc), secure, smmu_state->state,
  3710. smmu_state->secure_level, fb_ns, fb_sec_dir);
  3711. return -EINVAL;
  3712. }
  3713. static int _sde_crtc_check_secure_conn(struct drm_crtc *crtc,
  3714. struct drm_crtc_state *state, uint32_t fb_sec)
  3715. {
  3716. bool conn_secure = false, is_wb = false;
  3717. struct drm_connector *conn;
  3718. struct drm_connector_state *conn_state;
  3719. int i;
  3720. for_each_new_connector_in_state(state->state, conn, conn_state, i) {
  3721. if (conn_state && conn_state->crtc == crtc) {
  3722. if (conn->connector_type ==
  3723. DRM_MODE_CONNECTOR_VIRTUAL)
  3724. is_wb = true;
  3725. if (sde_connector_get_property(conn_state,
  3726. CONNECTOR_PROP_FB_TRANSLATION_MODE) ==
  3727. SDE_DRM_FB_SEC)
  3728. conn_secure = true;
  3729. }
  3730. }
  3731. /*
  3732. * If any input buffers are secure for wb,
  3733. * the output buffer must also be secure.
  3734. */
  3735. if (is_wb && fb_sec && !conn_secure) {
  3736. SDE_ERROR("crtc%d: input fb sec %d, output fb secure %d\n",
  3737. DRMID(crtc), fb_sec, conn_secure);
  3738. return -EINVAL;
  3739. }
  3740. return 0;
  3741. }
  3742. static int _sde_crtc_check_secure_state(struct drm_crtc *crtc,
  3743. struct drm_crtc_state *state, struct plane_state pstates[],
  3744. int cnt)
  3745. {
  3746. struct sde_crtc_state *cstate;
  3747. struct sde_kms *sde_kms;
  3748. uint32_t secure;
  3749. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  3750. int rc;
  3751. if (!crtc || !state) {
  3752. SDE_ERROR("invalid arguments\n");
  3753. return -EINVAL;
  3754. }
  3755. sde_kms = _sde_crtc_get_kms(crtc);
  3756. if (!sde_kms || !sde_kms->catalog) {
  3757. SDE_ERROR("invalid kms\n");
  3758. return -EINVAL;
  3759. }
  3760. cstate = to_sde_crtc_state(state);
  3761. secure = sde_crtc_get_property(cstate, CRTC_PROP_SECURITY_LEVEL);
  3762. rc = sde_crtc_state_find_plane_fb_modes(state, &fb_ns,
  3763. &fb_sec, &fb_sec_dir);
  3764. if (rc)
  3765. return rc;
  3766. rc = _sde_crtc_check_secure_blend_config(crtc, state, pstates, cstate,
  3767. sde_kms, cnt, secure, fb_ns, fb_sec, fb_sec_dir);
  3768. if (rc)
  3769. return rc;
  3770. rc = _sde_crtc_check_secure_conn(crtc, state, fb_sec);
  3771. if (rc)
  3772. return rc;
  3773. /*
  3774. * secure_crtc is not allowed in a shared toppolgy
  3775. * across different encoders.
  3776. */
  3777. rc = _sde_crtc_check_secure_single_encoder(crtc, state, fb_sec_dir);
  3778. if (rc)
  3779. return rc;
  3780. rc = _sde_crtc_check_secure_state_smmu_translation(crtc, state, sde_kms,
  3781. secure, fb_ns, fb_sec, fb_sec_dir);
  3782. if (rc)
  3783. return rc;
  3784. SDE_DEBUG("crtc:%d Secure validation successful\n", DRMID(crtc));
  3785. return 0;
  3786. }
  3787. static int _sde_crtc_check_get_pstates(struct drm_crtc *crtc,
  3788. struct drm_crtc_state *state,
  3789. struct drm_display_mode *mode,
  3790. struct plane_state *pstates,
  3791. struct drm_plane *plane,
  3792. struct sde_multirect_plane_states *multirect_plane,
  3793. int *cnt)
  3794. {
  3795. struct sde_crtc *sde_crtc;
  3796. struct sde_crtc_state *cstate;
  3797. const struct drm_plane_state *pstate;
  3798. const struct drm_plane_state *pipe_staged[SSPP_MAX];
  3799. int rc = 0, multirect_count = 0, i, mixer_width, mixer_height;
  3800. int inc_sde_stage = 0;
  3801. struct sde_kms *kms;
  3802. sde_crtc = to_sde_crtc(crtc);
  3803. cstate = to_sde_crtc_state(state);
  3804. kms = _sde_crtc_get_kms(crtc);
  3805. if (!kms || !kms->catalog) {
  3806. SDE_ERROR("invalid kms\n");
  3807. return -EINVAL;
  3808. }
  3809. memset(pipe_staged, 0, sizeof(pipe_staged));
  3810. mixer_width = sde_crtc_get_mixer_width(sde_crtc, cstate, mode);
  3811. mixer_height = sde_crtc_get_mixer_height(sde_crtc, cstate, mode);
  3812. if (cstate->num_ds_enabled)
  3813. mixer_width = mixer_width * cstate->num_ds_enabled;
  3814. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  3815. if (IS_ERR_OR_NULL(pstate)) {
  3816. rc = PTR_ERR(pstate);
  3817. SDE_ERROR("%s: failed to get plane%d state, %d\n",
  3818. sde_crtc->name, plane->base.id, rc);
  3819. return rc;
  3820. }
  3821. if (*cnt >= SDE_PSTATES_MAX)
  3822. continue;
  3823. pstates[*cnt].sde_pstate = to_sde_plane_state(pstate);
  3824. pstates[*cnt].drm_pstate = pstate;
  3825. pstates[*cnt].stage = sde_plane_get_property(
  3826. pstates[*cnt].sde_pstate, PLANE_PROP_ZPOS);
  3827. pstates[*cnt].pipe_id = sde_plane_pipe(plane);
  3828. if (!kms->catalog->has_base_layer)
  3829. inc_sde_stage = SDE_STAGE_0;
  3830. /* check dim layer stage with every plane */
  3831. for (i = 0; i < cstate->num_dim_layers; i++) {
  3832. if (cstate->dim_layer[i].stage ==
  3833. (pstates[*cnt].stage + inc_sde_stage)) {
  3834. SDE_ERROR(
  3835. "plane:%d/dim_layer:%i-same stage:%d\n",
  3836. plane->base.id, i,
  3837. cstate->dim_layer[i].stage);
  3838. return -EINVAL;
  3839. }
  3840. }
  3841. if (pipe_staged[pstates[*cnt].pipe_id]) {
  3842. multirect_plane[multirect_count].r0 =
  3843. pipe_staged[pstates[*cnt].pipe_id];
  3844. multirect_plane[multirect_count].r1 = pstate;
  3845. multirect_count++;
  3846. pipe_staged[pstates[*cnt].pipe_id] = NULL;
  3847. } else {
  3848. pipe_staged[pstates[*cnt].pipe_id] = pstate;
  3849. }
  3850. (*cnt)++;
  3851. if (CHECK_LAYER_BOUNDS(pstate->crtc_y, pstate->crtc_h,
  3852. mode->vdisplay) ||
  3853. CHECK_LAYER_BOUNDS(pstate->crtc_x, pstate->crtc_w,
  3854. mode->hdisplay)) {
  3855. SDE_ERROR("invalid vertical/horizontal destination\n");
  3856. SDE_ERROR("y:%d h:%d vdisp:%d x:%d w:%d hdisp:%d\n",
  3857. pstate->crtc_y, pstate->crtc_h, mode->vdisplay,
  3858. pstate->crtc_x, pstate->crtc_w, mode->hdisplay);
  3859. return -E2BIG;
  3860. }
  3861. if (cstate->num_ds_enabled &&
  3862. ((pstate->crtc_h > mixer_height) ||
  3863. (pstate->crtc_w > mixer_width))) {
  3864. SDE_ERROR("plane w/h:%x*%x > mixer w/h:%x*%x\n",
  3865. pstate->crtc_w, pstate->crtc_h,
  3866. mixer_width, mixer_height);
  3867. return -E2BIG;
  3868. }
  3869. }
  3870. for (i = 1; i < SSPP_MAX; i++) {
  3871. if (pipe_staged[i]) {
  3872. if (is_sde_plane_virtual(pipe_staged[i]->plane)) {
  3873. SDE_ERROR(
  3874. "r1 only virt plane:%d not supported\n",
  3875. pipe_staged[i]->plane->base.id);
  3876. return -EINVAL;
  3877. }
  3878. sde_plane_clear_multirect(pipe_staged[i]);
  3879. }
  3880. }
  3881. for (i = 0; i < multirect_count; i++) {
  3882. if (sde_plane_validate_multirect_v2(&multirect_plane[i])) {
  3883. SDE_ERROR(
  3884. "multirect validation failed for planes (%d - %d)\n",
  3885. multirect_plane[i].r0->plane->base.id,
  3886. multirect_plane[i].r1->plane->base.id);
  3887. return -EINVAL;
  3888. }
  3889. }
  3890. return rc;
  3891. }
  3892. static int _sde_crtc_check_zpos(struct drm_crtc_state *state,
  3893. struct sde_crtc *sde_crtc,
  3894. struct plane_state *pstates,
  3895. struct sde_crtc_state *cstate,
  3896. struct drm_display_mode *mode,
  3897. int cnt)
  3898. {
  3899. int rc = 0, i, z_pos;
  3900. u32 zpos_cnt = 0;
  3901. struct drm_crtc *crtc;
  3902. struct sde_kms *kms;
  3903. crtc = &sde_crtc->base;
  3904. kms = _sde_crtc_get_kms(crtc);
  3905. if (!kms || !kms->catalog) {
  3906. SDE_ERROR("Invalid kms\n");
  3907. return -EINVAL;
  3908. }
  3909. sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
  3910. rc = _sde_crtc_excl_dim_layer_check(state, pstates, cnt);
  3911. if (rc)
  3912. return rc;
  3913. if (!sde_is_custom_client()) {
  3914. int stage_old = pstates[0].stage;
  3915. z_pos = 0;
  3916. for (i = 0; i < cnt; i++) {
  3917. if (stage_old != pstates[i].stage)
  3918. ++z_pos;
  3919. stage_old = pstates[i].stage;
  3920. pstates[i].stage = z_pos;
  3921. }
  3922. }
  3923. z_pos = -1;
  3924. for (i = 0; i < cnt; i++) {
  3925. /* reset counts at every new blend stage */
  3926. if (pstates[i].stage != z_pos) {
  3927. zpos_cnt = 0;
  3928. z_pos = pstates[i].stage;
  3929. }
  3930. /* verify z_pos setting before using it */
  3931. if (z_pos >= SDE_STAGE_MAX - SDE_STAGE_0) {
  3932. SDE_ERROR("> %d plane stages assigned\n",
  3933. SDE_STAGE_MAX - SDE_STAGE_0);
  3934. return -EINVAL;
  3935. } else if (zpos_cnt == 2) {
  3936. SDE_ERROR("> 2 planes @ stage %d\n", z_pos);
  3937. return -EINVAL;
  3938. } else {
  3939. zpos_cnt++;
  3940. }
  3941. if (!kms->catalog->has_base_layer)
  3942. pstates[i].sde_pstate->stage = z_pos + SDE_STAGE_0;
  3943. else
  3944. pstates[i].sde_pstate->stage = z_pos;
  3945. SDE_DEBUG("%s: zpos %d", sde_crtc->name, z_pos);
  3946. }
  3947. return rc;
  3948. }
  3949. static int _sde_crtc_atomic_check_pstates(struct drm_crtc *crtc,
  3950. struct drm_crtc_state *state,
  3951. struct plane_state *pstates,
  3952. struct sde_multirect_plane_states *multirect_plane)
  3953. {
  3954. struct sde_crtc *sde_crtc;
  3955. struct sde_crtc_state *cstate;
  3956. struct sde_kms *kms;
  3957. struct drm_plane *plane = NULL;
  3958. struct drm_display_mode *mode;
  3959. int rc = 0, cnt = 0;
  3960. kms = _sde_crtc_get_kms(crtc);
  3961. if (!kms || !kms->catalog) {
  3962. SDE_ERROR("invalid parameters\n");
  3963. return -EINVAL;
  3964. }
  3965. sde_crtc = to_sde_crtc(crtc);
  3966. cstate = to_sde_crtc_state(state);
  3967. mode = &state->adjusted_mode;
  3968. /* get plane state for all drm planes associated with crtc state */
  3969. rc = _sde_crtc_check_get_pstates(crtc, state, mode, pstates,
  3970. plane, multirect_plane, &cnt);
  3971. if (rc)
  3972. return rc;
  3973. /* assign mixer stages based on sorted zpos property */
  3974. rc = _sde_crtc_check_zpos(state, sde_crtc, pstates, cstate, mode, cnt);
  3975. if (rc)
  3976. return rc;
  3977. rc = _sde_crtc_check_secure_state(crtc, state, pstates, cnt);
  3978. if (rc)
  3979. return rc;
  3980. /*
  3981. * validate and set source split:
  3982. * use pstates sorted by stage to check planes on same stage
  3983. * we assume that all pipes are in source split so its valid to compare
  3984. * without taking into account left/right mixer placement
  3985. */
  3986. rc = _sde_crtc_validate_src_split_order(crtc, pstates, cnt);
  3987. if (rc)
  3988. return rc;
  3989. return 0;
  3990. }
  3991. static int sde_crtc_atomic_check(struct drm_crtc *crtc,
  3992. struct drm_crtc_state *state)
  3993. {
  3994. struct drm_device *dev;
  3995. struct sde_crtc *sde_crtc;
  3996. struct plane_state *pstates = NULL;
  3997. struct sde_crtc_state *cstate;
  3998. struct drm_display_mode *mode;
  3999. int rc = 0;
  4000. struct sde_multirect_plane_states *multirect_plane = NULL;
  4001. struct drm_connector *conn;
  4002. struct drm_connector_list_iter conn_iter;
  4003. if (!crtc) {
  4004. SDE_ERROR("invalid crtc\n");
  4005. return -EINVAL;
  4006. }
  4007. dev = crtc->dev;
  4008. sde_crtc = to_sde_crtc(crtc);
  4009. cstate = to_sde_crtc_state(state);
  4010. if (!state->enable || !state->active) {
  4011. SDE_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n",
  4012. crtc->base.id, state->enable, state->active);
  4013. goto end;
  4014. }
  4015. pstates = kcalloc(SDE_PSTATES_MAX,
  4016. sizeof(struct plane_state), GFP_KERNEL);
  4017. multirect_plane = kcalloc(SDE_MULTIRECT_PLANE_MAX,
  4018. sizeof(struct sde_multirect_plane_states),
  4019. GFP_KERNEL);
  4020. if (!pstates || !multirect_plane) {
  4021. rc = -ENOMEM;
  4022. goto end;
  4023. }
  4024. mode = &state->adjusted_mode;
  4025. SDE_DEBUG("%s: check", sde_crtc->name);
  4026. /* force a full mode set if active state changed */
  4027. if (state->active_changed)
  4028. state->mode_changed = true;
  4029. rc = _sde_crtc_check_dest_scaler_data(crtc, state);
  4030. if (rc) {
  4031. SDE_ERROR("crtc%d failed dest scaler check %d\n",
  4032. crtc->base.id, rc);
  4033. goto end;
  4034. }
  4035. /* identify connectors attached to this crtc */
  4036. cstate->num_connectors = 0;
  4037. drm_connector_list_iter_begin(dev, &conn_iter);
  4038. drm_for_each_connector_iter(conn, &conn_iter)
  4039. if (conn->state && conn->state->crtc == crtc &&
  4040. cstate->num_connectors < MAX_CONNECTORS) {
  4041. cstate->connectors[cstate->num_connectors++] = conn;
  4042. }
  4043. drm_connector_list_iter_end(&conn_iter);
  4044. _sde_crtc_setup_is_ppsplit(state);
  4045. _sde_crtc_setup_lm_bounds(crtc, state);
  4046. rc = _sde_crtc_atomic_check_pstates(crtc, state, pstates,
  4047. multirect_plane);
  4048. if (rc) {
  4049. SDE_ERROR("crtc%d failed pstate check %d\n", crtc->base.id, rc);
  4050. goto end;
  4051. }
  4052. rc = sde_core_perf_crtc_check(crtc, state);
  4053. if (rc) {
  4054. SDE_ERROR("crtc%d failed performance check %d\n",
  4055. crtc->base.id, rc);
  4056. goto end;
  4057. }
  4058. rc = _sde_crtc_check_rois(crtc, state);
  4059. if (rc) {
  4060. SDE_ERROR("crtc%d failed roi check %d\n", crtc->base.id, rc);
  4061. goto end;
  4062. }
  4063. rc = sde_cp_crtc_check_properties(crtc, state);
  4064. if (rc) {
  4065. SDE_ERROR("crtc%d failed cp properties check %d\n",
  4066. crtc->base.id, rc);
  4067. goto end;
  4068. }
  4069. end:
  4070. kfree(pstates);
  4071. kfree(multirect_plane);
  4072. return rc;
  4073. }
  4074. int sde_crtc_vblank(struct drm_crtc *crtc, bool en)
  4075. {
  4076. struct sde_crtc *sde_crtc;
  4077. int ret;
  4078. if (!crtc) {
  4079. SDE_ERROR("invalid crtc\n");
  4080. return -EINVAL;
  4081. }
  4082. sde_crtc = to_sde_crtc(crtc);
  4083. mutex_lock(&sde_crtc->crtc_lock);
  4084. SDE_EVT32(DRMID(&sde_crtc->base), en, sde_crtc->enabled);
  4085. ret = _sde_crtc_vblank_enable_no_lock(sde_crtc, en);
  4086. if (ret)
  4087. SDE_ERROR("%s vblank enable failed: %d\n",
  4088. sde_crtc->name, ret);
  4089. mutex_unlock(&sde_crtc->crtc_lock);
  4090. return 0;
  4091. }
  4092. static void sde_crtc_install_dest_scale_properties(struct sde_crtc *sde_crtc,
  4093. struct sde_mdss_cfg *catalog, struct sde_kms_info *info)
  4094. {
  4095. sde_kms_info_add_keyint(info, "has_dest_scaler",
  4096. catalog->mdp[0].has_dest_scaler);
  4097. sde_kms_info_add_keyint(info, "dest_scaler_count",
  4098. catalog->ds_count);
  4099. if (catalog->ds[0].top) {
  4100. sde_kms_info_add_keyint(info,
  4101. "max_dest_scaler_input_width",
  4102. catalog->ds[0].top->maxinputwidth);
  4103. sde_kms_info_add_keyint(info,
  4104. "max_dest_scaler_output_width",
  4105. catalog->ds[0].top->maxoutputwidth);
  4106. sde_kms_info_add_keyint(info, "max_dest_scale_up",
  4107. catalog->ds[0].top->maxupscale);
  4108. }
  4109. if (catalog->ds[0].features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  4110. msm_property_install_volatile_range(
  4111. &sde_crtc->property_info, "dest_scaler",
  4112. 0x0, 0, ~0, 0, CRTC_PROP_DEST_SCALER);
  4113. msm_property_install_blob(&sde_crtc->property_info,
  4114. "ds_lut_ed", 0,
  4115. CRTC_PROP_DEST_SCALER_LUT_ED);
  4116. msm_property_install_blob(&sde_crtc->property_info,
  4117. "ds_lut_cir", 0,
  4118. CRTC_PROP_DEST_SCALER_LUT_CIR);
  4119. msm_property_install_blob(&sde_crtc->property_info,
  4120. "ds_lut_sep", 0,
  4121. CRTC_PROP_DEST_SCALER_LUT_SEP);
  4122. } else if (catalog->ds[0].features
  4123. & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  4124. msm_property_install_volatile_range(
  4125. &sde_crtc->property_info, "dest_scaler",
  4126. 0x0, 0, ~0, 0, CRTC_PROP_DEST_SCALER);
  4127. }
  4128. }
  4129. static void sde_crtc_install_perf_properties(struct sde_crtc *sde_crtc,
  4130. struct sde_kms *sde_kms, struct sde_mdss_cfg *catalog,
  4131. struct sde_kms_info *info)
  4132. {
  4133. msm_property_install_range(&sde_crtc->property_info,
  4134. "core_clk", 0x0, 0, U64_MAX,
  4135. sde_kms->perf.max_core_clk_rate,
  4136. CRTC_PROP_CORE_CLK);
  4137. msm_property_install_range(&sde_crtc->property_info,
  4138. "core_ab", 0x0, 0, U64_MAX,
  4139. catalog->perf.max_bw_high * 1000ULL,
  4140. CRTC_PROP_CORE_AB);
  4141. msm_property_install_range(&sde_crtc->property_info,
  4142. "core_ib", 0x0, 0, U64_MAX,
  4143. catalog->perf.max_bw_high * 1000ULL,
  4144. CRTC_PROP_CORE_IB);
  4145. msm_property_install_range(&sde_crtc->property_info,
  4146. "llcc_ab", 0x0, 0, U64_MAX,
  4147. catalog->perf.max_bw_high * 1000ULL,
  4148. CRTC_PROP_LLCC_AB);
  4149. msm_property_install_range(&sde_crtc->property_info,
  4150. "llcc_ib", 0x0, 0, U64_MAX,
  4151. catalog->perf.max_bw_high * 1000ULL,
  4152. CRTC_PROP_LLCC_IB);
  4153. msm_property_install_range(&sde_crtc->property_info,
  4154. "dram_ab", 0x0, 0, U64_MAX,
  4155. catalog->perf.max_bw_high * 1000ULL,
  4156. CRTC_PROP_DRAM_AB);
  4157. msm_property_install_range(&sde_crtc->property_info,
  4158. "dram_ib", 0x0, 0, U64_MAX,
  4159. catalog->perf.max_bw_high * 1000ULL,
  4160. CRTC_PROP_DRAM_IB);
  4161. msm_property_install_range(&sde_crtc->property_info,
  4162. "rot_prefill_bw", 0, 0, U64_MAX,
  4163. catalog->perf.max_bw_high * 1000ULL,
  4164. CRTC_PROP_ROT_PREFILL_BW);
  4165. msm_property_install_range(&sde_crtc->property_info,
  4166. "rot_clk", 0, 0, U64_MAX,
  4167. sde_kms->perf.max_core_clk_rate,
  4168. CRTC_PROP_ROT_CLK);
  4169. if (catalog->perf.max_bw_low)
  4170. sde_kms_info_add_keyint(info, "max_bandwidth_low",
  4171. catalog->perf.max_bw_low * 1000LL);
  4172. if (catalog->perf.max_bw_high)
  4173. sde_kms_info_add_keyint(info, "max_bandwidth_high",
  4174. catalog->perf.max_bw_high * 1000LL);
  4175. if (catalog->perf.min_core_ib)
  4176. sde_kms_info_add_keyint(info, "min_core_ib",
  4177. catalog->perf.min_core_ib * 1000LL);
  4178. if (catalog->perf.min_llcc_ib)
  4179. sde_kms_info_add_keyint(info, "min_llcc_ib",
  4180. catalog->perf.min_llcc_ib * 1000LL);
  4181. if (catalog->perf.min_dram_ib)
  4182. sde_kms_info_add_keyint(info, "min_dram_ib",
  4183. catalog->perf.min_dram_ib * 1000LL);
  4184. if (sde_kms->perf.max_core_clk_rate)
  4185. sde_kms_info_add_keyint(info, "max_mdp_clk",
  4186. sde_kms->perf.max_core_clk_rate);
  4187. }
  4188. static void sde_crtc_setup_capabilities_blob(struct sde_kms_info *info,
  4189. struct sde_mdss_cfg *catalog)
  4190. {
  4191. sde_kms_info_reset(info);
  4192. sde_kms_info_add_keyint(info, "hw_version", catalog->hwversion);
  4193. sde_kms_info_add_keyint(info, "max_linewidth",
  4194. catalog->max_mixer_width);
  4195. sde_kms_info_add_keyint(info, "max_blendstages",
  4196. catalog->max_mixer_blendstages);
  4197. if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED2)
  4198. sde_kms_info_add_keystr(info, "qseed_type", "qseed2");
  4199. if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED3)
  4200. sde_kms_info_add_keystr(info, "qseed_type", "qseed3");
  4201. if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED3LITE)
  4202. sde_kms_info_add_keystr(info, "qseed_type", "qseed3lite");
  4203. sde_kms_info_add_keyint(info, "UBWC version", catalog->ubwc_version);
  4204. sde_kms_info_add_keyint(info, "UBWC macrotile_mode",
  4205. catalog->macrotile_mode);
  4206. sde_kms_info_add_keyint(info, "UBWC highest banking bit",
  4207. catalog->mdp[0].highest_bank_bit);
  4208. sde_kms_info_add_keyint(info, "UBWC swizzle",
  4209. catalog->mdp[0].ubwc_swizzle);
  4210. if (of_fdt_get_ddrtype() == LP_DDR4_TYPE)
  4211. sde_kms_info_add_keystr(info, "DDR version", "DDR4");
  4212. else
  4213. sde_kms_info_add_keystr(info, "DDR version", "DDR5");
  4214. if (sde_is_custom_client()) {
  4215. /* No support for SMART_DMA_V1 yet */
  4216. if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V2)
  4217. sde_kms_info_add_keystr(info,
  4218. "smart_dma_rev", "smart_dma_v2");
  4219. else if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V2p5)
  4220. sde_kms_info_add_keystr(info,
  4221. "smart_dma_rev", "smart_dma_v2p5");
  4222. }
  4223. sde_kms_info_add_keyint(info, "has_src_split", catalog->has_src_split);
  4224. sde_kms_info_add_keyint(info, "has_hdr", catalog->has_hdr);
  4225. sde_kms_info_add_keyint(info, "has_hdr_plus", catalog->has_hdr_plus);
  4226. if (catalog->uidle_cfg.uidle_rev)
  4227. sde_kms_info_add_keyint(info, "has_uidle",
  4228. true);
  4229. sde_kms_info_add_keystr(info, "core_ib_ff",
  4230. catalog->perf.core_ib_ff);
  4231. sde_kms_info_add_keystr(info, "core_clk_ff",
  4232. catalog->perf.core_clk_ff);
  4233. sde_kms_info_add_keystr(info, "comp_ratio_rt",
  4234. catalog->perf.comp_ratio_rt);
  4235. sde_kms_info_add_keystr(info, "comp_ratio_nrt",
  4236. catalog->perf.comp_ratio_nrt);
  4237. sde_kms_info_add_keyint(info, "dest_scale_prefill_lines",
  4238. catalog->perf.dest_scale_prefill_lines);
  4239. sde_kms_info_add_keyint(info, "undersized_prefill_lines",
  4240. catalog->perf.undersized_prefill_lines);
  4241. sde_kms_info_add_keyint(info, "macrotile_prefill_lines",
  4242. catalog->perf.macrotile_prefill_lines);
  4243. sde_kms_info_add_keyint(info, "yuv_nv12_prefill_lines",
  4244. catalog->perf.yuv_nv12_prefill_lines);
  4245. sde_kms_info_add_keyint(info, "linear_prefill_lines",
  4246. catalog->perf.linear_prefill_lines);
  4247. sde_kms_info_add_keyint(info, "downscaling_prefill_lines",
  4248. catalog->perf.downscaling_prefill_lines);
  4249. sde_kms_info_add_keyint(info, "xtra_prefill_lines",
  4250. catalog->perf.xtra_prefill_lines);
  4251. sde_kms_info_add_keyint(info, "amortizable_threshold",
  4252. catalog->perf.amortizable_threshold);
  4253. sde_kms_info_add_keyint(info, "min_prefill_lines",
  4254. catalog->perf.min_prefill_lines);
  4255. sde_kms_info_add_keyint(info, "num_mnoc_ports",
  4256. catalog->perf.num_mnoc_ports);
  4257. sde_kms_info_add_keyint(info, "axi_bus_width",
  4258. catalog->perf.axi_bus_width);
  4259. sde_kms_info_add_keyint(info, "sec_ui_blendstage",
  4260. catalog->sui_supported_blendstage);
  4261. if (catalog->ubwc_bw_calc_version)
  4262. sde_kms_info_add_keyint(info, "ubwc_bw_calc_ver",
  4263. catalog->ubwc_bw_calc_version);
  4264. }
  4265. /**
  4266. * sde_crtc_install_properties - install all drm properties for crtc
  4267. * @crtc: Pointer to drm crtc structure
  4268. */
  4269. static void sde_crtc_install_properties(struct drm_crtc *crtc,
  4270. struct sde_mdss_cfg *catalog)
  4271. {
  4272. struct sde_crtc *sde_crtc;
  4273. struct sde_kms_info *info;
  4274. struct sde_kms *sde_kms;
  4275. static const struct drm_prop_enum_list e_secure_level[] = {
  4276. {SDE_DRM_SEC_NON_SEC, "sec_and_non_sec"},
  4277. {SDE_DRM_SEC_ONLY, "sec_only"},
  4278. };
  4279. static const struct drm_prop_enum_list e_cwb_data_points[] = {
  4280. {CAPTURE_MIXER_OUT, "capture_mixer_out"},
  4281. {CAPTURE_DSPP_OUT, "capture_pp_out"},
  4282. };
  4283. static const struct drm_prop_enum_list e_idle_pc_state[] = {
  4284. {IDLE_PC_NONE, "idle_pc_none"},
  4285. {IDLE_PC_ENABLE, "idle_pc_enable"},
  4286. {IDLE_PC_DISABLE, "idle_pc_disable"},
  4287. };
  4288. static const struct drm_prop_enum_list e_cache_state[] = {
  4289. {CACHE_STATE_DISABLED, "cache_state_disabled"},
  4290. {CACHE_STATE_ENABLED, "cache_state_enabled"},
  4291. };
  4292. SDE_DEBUG("\n");
  4293. if (!crtc || !catalog) {
  4294. SDE_ERROR("invalid crtc or catalog\n");
  4295. return;
  4296. }
  4297. sde_crtc = to_sde_crtc(crtc);
  4298. sde_kms = _sde_crtc_get_kms(crtc);
  4299. if (!sde_kms) {
  4300. SDE_ERROR("invalid argument\n");
  4301. return;
  4302. }
  4303. info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
  4304. if (!info) {
  4305. SDE_ERROR("failed to allocate info memory\n");
  4306. return;
  4307. }
  4308. sde_crtc_setup_capabilities_blob(info, catalog);
  4309. msm_property_install_range(&sde_crtc->property_info,
  4310. "input_fence_timeout", 0x0, 0,
  4311. SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT, SDE_CRTC_INPUT_FENCE_TIMEOUT,
  4312. CRTC_PROP_INPUT_FENCE_TIMEOUT);
  4313. msm_property_install_volatile_range(&sde_crtc->property_info,
  4314. "output_fence", 0x0, 0, ~0, 0, CRTC_PROP_OUTPUT_FENCE);
  4315. msm_property_install_range(&sde_crtc->property_info,
  4316. "output_fence_offset", 0x0, 0, 1, 0,
  4317. CRTC_PROP_OUTPUT_FENCE_OFFSET);
  4318. sde_crtc_install_perf_properties(sde_crtc, sde_kms, catalog, info);
  4319. msm_property_install_range(&sde_crtc->property_info,
  4320. "idle_time", 0, 0, U64_MAX, 0,
  4321. CRTC_PROP_IDLE_TIMEOUT);
  4322. if (catalog->has_idle_pc)
  4323. msm_property_install_enum(&sde_crtc->property_info,
  4324. "idle_pc_state", 0x0, 0, e_idle_pc_state,
  4325. ARRAY_SIZE(e_idle_pc_state),
  4326. CRTC_PROP_IDLE_PC_STATE);
  4327. if (catalog->has_cwb_support)
  4328. msm_property_install_enum(&sde_crtc->property_info,
  4329. "capture_mode", 0, 0, e_cwb_data_points,
  4330. ARRAY_SIZE(e_cwb_data_points),
  4331. CRTC_PROP_CAPTURE_OUTPUT);
  4332. msm_property_install_volatile_range(&sde_crtc->property_info,
  4333. "sde_drm_roi_v1", 0x0, 0, ~0, 0, CRTC_PROP_ROI_V1);
  4334. msm_property_install_enum(&sde_crtc->property_info, "security_level",
  4335. 0x0, 0, e_secure_level,
  4336. ARRAY_SIZE(e_secure_level),
  4337. CRTC_PROP_SECURITY_LEVEL);
  4338. msm_property_install_enum(&sde_crtc->property_info, "cache_state",
  4339. 0x0, 0, e_cache_state,
  4340. ARRAY_SIZE(e_cache_state),
  4341. CRTC_PROP_CACHE_STATE);
  4342. if (catalog->has_dim_layer) {
  4343. msm_property_install_volatile_range(&sde_crtc->property_info,
  4344. "dim_layer_v1", 0x0, 0, ~0, 0, CRTC_PROP_DIM_LAYER_V1);
  4345. sde_kms_info_add_keyint(info, "dim_layer_v1_max_layers",
  4346. SDE_MAX_DIM_LAYERS);
  4347. }
  4348. if (catalog->mdp[0].has_dest_scaler)
  4349. sde_crtc_install_dest_scale_properties(sde_crtc, catalog,
  4350. info);
  4351. if (catalog->dspp_count && catalog->rc_count)
  4352. sde_kms_info_add_keyint(info, "rc_mem_size",
  4353. catalog->dspp[0].sblk->rc.mem_total_size);
  4354. msm_property_install_blob(&sde_crtc->property_info, "capabilities",
  4355. DRM_MODE_PROP_IMMUTABLE, CRTC_PROP_INFO);
  4356. sde_kms_info_add_keyint(info, "use_baselayer_for_stage",
  4357. catalog->has_base_layer);
  4358. msm_property_set_blob(&sde_crtc->property_info, &sde_crtc->blob_info,
  4359. info->data, SDE_KMS_INFO_DATALEN(info),
  4360. CRTC_PROP_INFO);
  4361. kfree(info);
  4362. }
  4363. static int _sde_crtc_get_output_fence(struct drm_crtc *crtc,
  4364. const struct drm_crtc_state *state, uint64_t *val)
  4365. {
  4366. struct sde_crtc *sde_crtc;
  4367. struct sde_crtc_state *cstate;
  4368. uint32_t offset;
  4369. bool is_vid = false;
  4370. struct drm_encoder *encoder;
  4371. sde_crtc = to_sde_crtc(crtc);
  4372. cstate = to_sde_crtc_state(state);
  4373. drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) {
  4374. if (sde_encoder_check_curr_mode(encoder,
  4375. MSM_DISPLAY_VIDEO_MODE))
  4376. is_vid = true;
  4377. if (is_vid)
  4378. break;
  4379. }
  4380. offset = sde_crtc_get_property(cstate, CRTC_PROP_OUTPUT_FENCE_OFFSET);
  4381. /*
  4382. * Increment trigger offset for vidoe mode alone as its release fence
  4383. * can be triggered only after the next frame-update. For cmd mode &
  4384. * virtual displays the release fence for the current frame can be
  4385. * triggered right after PP_DONE/WB_DONE interrupt
  4386. */
  4387. if (is_vid)
  4388. offset++;
  4389. /*
  4390. * Hwcomposer now queries the fences using the commit list in atomic
  4391. * commit ioctl. The offset should be set to next timeline
  4392. * which will be incremented during the prepare commit phase
  4393. */
  4394. offset++;
  4395. return sde_fence_create(sde_crtc->output_fence, val, offset);
  4396. }
  4397. /**
  4398. * sde_crtc_atomic_set_property - atomically set a crtc drm property
  4399. * @crtc: Pointer to drm crtc structure
  4400. * @state: Pointer to drm crtc state structure
  4401. * @property: Pointer to targeted drm property
  4402. * @val: Updated property value
  4403. * @Returns: Zero on success
  4404. */
  4405. static int sde_crtc_atomic_set_property(struct drm_crtc *crtc,
  4406. struct drm_crtc_state *state,
  4407. struct drm_property *property,
  4408. uint64_t val)
  4409. {
  4410. struct sde_crtc *sde_crtc;
  4411. struct sde_crtc_state *cstate;
  4412. int idx, ret;
  4413. uint64_t fence_user_fd;
  4414. uint64_t __user prev_user_fd;
  4415. if (!crtc || !state || !property) {
  4416. SDE_ERROR("invalid argument(s)\n");
  4417. return -EINVAL;
  4418. }
  4419. sde_crtc = to_sde_crtc(crtc);
  4420. cstate = to_sde_crtc_state(state);
  4421. SDE_ATRACE_BEGIN("sde_crtc_atomic_set_property");
  4422. /* check with cp property system first */
  4423. ret = sde_cp_crtc_set_property(crtc, property, val);
  4424. if (ret != -ENOENT)
  4425. goto exit;
  4426. /* if not handled by cp, check msm_property system */
  4427. ret = msm_property_atomic_set(&sde_crtc->property_info,
  4428. &cstate->property_state, property, val);
  4429. if (ret)
  4430. goto exit;
  4431. idx = msm_property_index(&sde_crtc->property_info, property);
  4432. switch (idx) {
  4433. case CRTC_PROP_INPUT_FENCE_TIMEOUT:
  4434. _sde_crtc_set_input_fence_timeout(cstate);
  4435. break;
  4436. case CRTC_PROP_DIM_LAYER_V1:
  4437. _sde_crtc_set_dim_layer_v1(crtc, cstate,
  4438. (void __user *)(uintptr_t)val);
  4439. break;
  4440. case CRTC_PROP_ROI_V1:
  4441. ret = _sde_crtc_set_roi_v1(state,
  4442. (void __user *)(uintptr_t)val);
  4443. break;
  4444. case CRTC_PROP_DEST_SCALER:
  4445. ret = _sde_crtc_set_dest_scaler(sde_crtc, cstate,
  4446. (void __user *)(uintptr_t)val);
  4447. break;
  4448. case CRTC_PROP_DEST_SCALER_LUT_ED:
  4449. case CRTC_PROP_DEST_SCALER_LUT_CIR:
  4450. case CRTC_PROP_DEST_SCALER_LUT_SEP:
  4451. ret = _sde_crtc_set_dest_scaler_lut(sde_crtc, cstate, idx);
  4452. break;
  4453. case CRTC_PROP_CORE_CLK:
  4454. case CRTC_PROP_CORE_AB:
  4455. case CRTC_PROP_CORE_IB:
  4456. cstate->bw_control = true;
  4457. break;
  4458. case CRTC_PROP_LLCC_AB:
  4459. case CRTC_PROP_LLCC_IB:
  4460. case CRTC_PROP_DRAM_AB:
  4461. case CRTC_PROP_DRAM_IB:
  4462. cstate->bw_control = true;
  4463. cstate->bw_split_vote = true;
  4464. break;
  4465. case CRTC_PROP_OUTPUT_FENCE:
  4466. if (!val)
  4467. goto exit;
  4468. ret = copy_from_user(&prev_user_fd, (void __user *)val,
  4469. sizeof(uint64_t));
  4470. if (ret) {
  4471. SDE_ERROR("copy from user failed rc:%d\n", ret);
  4472. ret = -EFAULT;
  4473. goto exit;
  4474. }
  4475. /*
  4476. * client is expected to reset the property to -1 before
  4477. * requesting for the release fence
  4478. */
  4479. if (prev_user_fd == -1) {
  4480. ret = _sde_crtc_get_output_fence(crtc, state,
  4481. &fence_user_fd);
  4482. if (ret) {
  4483. SDE_ERROR("fence create failed rc:%d\n", ret);
  4484. goto exit;
  4485. }
  4486. ret = copy_to_user((uint64_t __user *)(uintptr_t)val,
  4487. &fence_user_fd, sizeof(uint64_t));
  4488. if (ret) {
  4489. SDE_ERROR("copy to user failed rc:%d\n", ret);
  4490. put_unused_fd(fence_user_fd);
  4491. ret = -EFAULT;
  4492. goto exit;
  4493. }
  4494. }
  4495. break;
  4496. default:
  4497. /* nothing to do */
  4498. break;
  4499. }
  4500. exit:
  4501. if (ret) {
  4502. if (ret != -EPERM)
  4503. SDE_ERROR("%s: failed to set property%d %s: %d\n",
  4504. crtc->name, DRMID(property),
  4505. property->name, ret);
  4506. else
  4507. SDE_DEBUG("%s: failed to set property%d %s: %d\n",
  4508. crtc->name, DRMID(property),
  4509. property->name, ret);
  4510. } else {
  4511. SDE_DEBUG("%s: %s[%d] <= 0x%llx\n", crtc->name, property->name,
  4512. property->base.id, val);
  4513. }
  4514. SDE_ATRACE_END("sde_crtc_atomic_set_property");
  4515. return ret;
  4516. }
  4517. void sde_crtc_set_qos_dirty(struct drm_crtc *crtc)
  4518. {
  4519. struct drm_plane *plane;
  4520. struct drm_plane_state *state;
  4521. struct sde_plane_state *pstate;
  4522. drm_atomic_crtc_for_each_plane(plane, crtc) {
  4523. state = plane->state;
  4524. if (!state)
  4525. continue;
  4526. pstate = to_sde_plane_state(state);
  4527. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  4528. }
  4529. }
  4530. /**
  4531. * sde_crtc_atomic_get_property - retrieve a crtc drm property
  4532. * @crtc: Pointer to drm crtc structure
  4533. * @state: Pointer to drm crtc state structure
  4534. * @property: Pointer to targeted drm property
  4535. * @val: Pointer to variable for receiving property value
  4536. * @Returns: Zero on success
  4537. */
  4538. static int sde_crtc_atomic_get_property(struct drm_crtc *crtc,
  4539. const struct drm_crtc_state *state,
  4540. struct drm_property *property,
  4541. uint64_t *val)
  4542. {
  4543. struct sde_crtc *sde_crtc;
  4544. struct sde_crtc_state *cstate;
  4545. int ret = -EINVAL, i;
  4546. if (!crtc || !state) {
  4547. SDE_ERROR("invalid argument(s)\n");
  4548. goto end;
  4549. }
  4550. sde_crtc = to_sde_crtc(crtc);
  4551. cstate = to_sde_crtc_state(state);
  4552. i = msm_property_index(&sde_crtc->property_info, property);
  4553. if (i == CRTC_PROP_OUTPUT_FENCE) {
  4554. *val = ~0;
  4555. ret = 0;
  4556. } else {
  4557. ret = msm_property_atomic_get(&sde_crtc->property_info,
  4558. &cstate->property_state, property, val);
  4559. if (ret)
  4560. ret = sde_cp_crtc_get_property(crtc, property, val);
  4561. }
  4562. if (ret)
  4563. DRM_ERROR("get property failed\n");
  4564. end:
  4565. return ret;
  4566. }
  4567. int sde_crtc_helper_reset_custom_properties(struct drm_crtc *crtc,
  4568. struct drm_crtc_state *crtc_state)
  4569. {
  4570. struct sde_crtc *sde_crtc;
  4571. struct sde_crtc_state *cstate;
  4572. struct drm_property *drm_prop;
  4573. enum msm_mdp_crtc_property prop_idx;
  4574. if (!crtc || !crtc_state) {
  4575. SDE_ERROR("invalid params\n");
  4576. return -EINVAL;
  4577. }
  4578. sde_crtc = to_sde_crtc(crtc);
  4579. cstate = to_sde_crtc_state(crtc_state);
  4580. sde_cp_crtc_clear(crtc);
  4581. for (prop_idx = 0; prop_idx < CRTC_PROP_COUNT; prop_idx++) {
  4582. uint64_t val = cstate->property_values[prop_idx].value;
  4583. uint64_t def;
  4584. int ret;
  4585. drm_prop = msm_property_index_to_drm_property(
  4586. &sde_crtc->property_info, prop_idx);
  4587. if (!drm_prop) {
  4588. /* not all props will be installed, based on caps */
  4589. SDE_DEBUG("%s: invalid property index %d\n",
  4590. sde_crtc->name, prop_idx);
  4591. continue;
  4592. }
  4593. def = msm_property_get_default(&sde_crtc->property_info,
  4594. prop_idx);
  4595. if (val == def)
  4596. continue;
  4597. SDE_DEBUG("%s: set prop %s idx %d from %llu to %llu\n",
  4598. sde_crtc->name, drm_prop->name, prop_idx, val,
  4599. def);
  4600. ret = sde_crtc_atomic_set_property(crtc, crtc_state, drm_prop,
  4601. def);
  4602. if (ret) {
  4603. SDE_ERROR("%s: set property failed, idx %d ret %d\n",
  4604. sde_crtc->name, prop_idx, ret);
  4605. continue;
  4606. }
  4607. }
  4608. return 0;
  4609. }
  4610. void sde_crtc_misr_setup(struct drm_crtc *crtc, bool enable, u32 frame_count)
  4611. {
  4612. struct sde_crtc *sde_crtc;
  4613. struct sde_crtc_mixer *m;
  4614. int i;
  4615. if (!crtc) {
  4616. SDE_ERROR("invalid argument\n");
  4617. return;
  4618. }
  4619. sde_crtc = to_sde_crtc(crtc);
  4620. sde_crtc->misr_enable_sui = enable;
  4621. sde_crtc->misr_frame_count = frame_count;
  4622. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  4623. m = &sde_crtc->mixers[i];
  4624. if (!m->hw_lm || !m->hw_lm->ops.setup_misr)
  4625. continue;
  4626. m->hw_lm->ops.setup_misr(m->hw_lm, enable, frame_count);
  4627. }
  4628. }
  4629. void sde_crtc_get_misr_info(struct drm_crtc *crtc,
  4630. struct sde_crtc_misr_info *crtc_misr_info)
  4631. {
  4632. struct sde_crtc *sde_crtc;
  4633. struct sde_kms *sde_kms;
  4634. if (!crtc_misr_info) {
  4635. SDE_ERROR("invalid misr info\n");
  4636. return;
  4637. }
  4638. crtc_misr_info->misr_enable = false;
  4639. crtc_misr_info->misr_frame_count = 0;
  4640. if (!crtc) {
  4641. SDE_ERROR("invalid crtc\n");
  4642. return;
  4643. }
  4644. sde_kms = _sde_crtc_get_kms(crtc);
  4645. if (!sde_kms) {
  4646. SDE_ERROR("invalid sde_kms\n");
  4647. return;
  4648. }
  4649. if (sde_kms_is_secure_session_inprogress(sde_kms))
  4650. return;
  4651. sde_crtc = to_sde_crtc(crtc);
  4652. crtc_misr_info->misr_enable =
  4653. sde_crtc->misr_enable_debugfs ? true : false;
  4654. crtc_misr_info->misr_frame_count = sde_crtc->misr_frame_count;
  4655. }
  4656. #ifdef CONFIG_DEBUG_FS
  4657. static int _sde_debugfs_status_show(struct seq_file *s, void *data)
  4658. {
  4659. struct sde_crtc *sde_crtc;
  4660. struct sde_plane_state *pstate = NULL;
  4661. struct sde_crtc_mixer *m;
  4662. struct drm_crtc *crtc;
  4663. struct drm_plane *plane;
  4664. struct drm_display_mode *mode;
  4665. struct drm_framebuffer *fb;
  4666. struct drm_plane_state *state;
  4667. struct sde_crtc_state *cstate;
  4668. int i, out_width, out_height;
  4669. if (!s || !s->private)
  4670. return -EINVAL;
  4671. sde_crtc = s->private;
  4672. crtc = &sde_crtc->base;
  4673. cstate = to_sde_crtc_state(crtc->state);
  4674. mutex_lock(&sde_crtc->crtc_lock);
  4675. mode = &crtc->state->adjusted_mode;
  4676. out_width = sde_crtc_get_mixer_width(sde_crtc, cstate, mode);
  4677. out_height = sde_crtc_get_mixer_height(sde_crtc, cstate, mode);
  4678. seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id,
  4679. mode->hdisplay, mode->vdisplay);
  4680. seq_puts(s, "\n");
  4681. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  4682. m = &sde_crtc->mixers[i];
  4683. if (!m->hw_lm)
  4684. seq_printf(s, "\tmixer[%d] has no lm\n", i);
  4685. else if (!m->hw_ctl)
  4686. seq_printf(s, "\tmixer[%d] has no ctl\n", i);
  4687. else
  4688. seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n",
  4689. m->hw_lm->idx - LM_0, m->hw_ctl->idx - CTL_0,
  4690. out_width, out_height);
  4691. }
  4692. seq_puts(s, "\n");
  4693. for (i = 0; i < cstate->num_dim_layers; i++) {
  4694. struct sde_hw_dim_layer *dim_layer = &cstate->dim_layer[i];
  4695. seq_printf(s, "\tdim_layer:%d] stage:%d flags:%d\n",
  4696. i, dim_layer->stage, dim_layer->flags);
  4697. seq_printf(s, "\tdst_x:%d dst_y:%d dst_w:%d dst_h:%d\n",
  4698. dim_layer->rect.x, dim_layer->rect.y,
  4699. dim_layer->rect.w, dim_layer->rect.h);
  4700. seq_printf(s,
  4701. "\tcolor_0:%d color_1:%d color_2:%d color_3:%d\n",
  4702. dim_layer->color_fill.color_0,
  4703. dim_layer->color_fill.color_1,
  4704. dim_layer->color_fill.color_2,
  4705. dim_layer->color_fill.color_3);
  4706. seq_puts(s, "\n");
  4707. }
  4708. drm_atomic_crtc_for_each_plane(plane, crtc) {
  4709. pstate = to_sde_plane_state(plane->state);
  4710. state = plane->state;
  4711. if (!pstate || !state)
  4712. continue;
  4713. seq_printf(s, "\tplane:%u stage:%d rotation:%d\n",
  4714. plane->base.id, pstate->stage, pstate->rotation);
  4715. if (plane->state->fb) {
  4716. fb = plane->state->fb;
  4717. seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u ",
  4718. fb->base.id, (char *) &fb->format->format,
  4719. fb->width, fb->height);
  4720. for (i = 0; i < ARRAY_SIZE(fb->format->cpp); ++i)
  4721. seq_printf(s, "cpp[%d]:%u ",
  4722. i, fb->format->cpp[i]);
  4723. seq_puts(s, "\n\t");
  4724. seq_printf(s, "modifier:%8llu ", fb->modifier);
  4725. seq_puts(s, "\n");
  4726. seq_puts(s, "\t");
  4727. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++)
  4728. seq_printf(s, "pitches[%d]:%8u ", i,
  4729. fb->pitches[i]);
  4730. seq_puts(s, "\n");
  4731. seq_puts(s, "\t");
  4732. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++)
  4733. seq_printf(s, "offsets[%d]:%8u ", i,
  4734. fb->offsets[i]);
  4735. seq_puts(s, "\n");
  4736. }
  4737. seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n",
  4738. state->src_x >> 16, state->src_y >> 16,
  4739. state->src_w >> 16, state->src_h >> 16);
  4740. seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n",
  4741. state->crtc_x, state->crtc_y, state->crtc_w,
  4742. state->crtc_h);
  4743. seq_printf(s, "\tmultirect: mode: %d index: %d\n",
  4744. pstate->multirect_mode, pstate->multirect_index);
  4745. seq_printf(s, "\texcl_rect: x:%4d y:%4d w:%4d h:%4d\n",
  4746. pstate->excl_rect.x, pstate->excl_rect.y,
  4747. pstate->excl_rect.w, pstate->excl_rect.h);
  4748. seq_puts(s, "\n");
  4749. }
  4750. if (sde_crtc->vblank_cb_count) {
  4751. ktime_t diff = ktime_sub(ktime_get(), sde_crtc->vblank_cb_time);
  4752. u32 diff_ms = ktime_to_ms(diff);
  4753. u64 fps = diff_ms ? DIV_ROUND_CLOSEST(
  4754. sde_crtc->vblank_cb_count * 1000, diff_ms) : 0;
  4755. seq_printf(s,
  4756. "vblank fps:%lld count:%u total:%llums total_framecount:%llu\n",
  4757. fps, sde_crtc->vblank_cb_count,
  4758. ktime_to_ms(diff), sde_crtc->play_count);
  4759. /* reset time & count for next measurement */
  4760. sde_crtc->vblank_cb_count = 0;
  4761. sde_crtc->vblank_cb_time = ktime_set(0, 0);
  4762. }
  4763. mutex_unlock(&sde_crtc->crtc_lock);
  4764. return 0;
  4765. }
  4766. static int _sde_debugfs_status_open(struct inode *inode, struct file *file)
  4767. {
  4768. return single_open(file, _sde_debugfs_status_show, inode->i_private);
  4769. }
  4770. static ssize_t _sde_crtc_misr_setup(struct file *file,
  4771. const char __user *user_buf, size_t count, loff_t *ppos)
  4772. {
  4773. struct drm_crtc *crtc;
  4774. struct sde_crtc *sde_crtc;
  4775. int rc;
  4776. char buf[MISR_BUFF_SIZE + 1];
  4777. u32 frame_count, enable;
  4778. size_t buff_copy;
  4779. struct sde_kms *sde_kms;
  4780. if (!file || !file->private_data)
  4781. return -EINVAL;
  4782. sde_crtc = file->private_data;
  4783. crtc = &sde_crtc->base;
  4784. sde_kms = _sde_crtc_get_kms(crtc);
  4785. if (!sde_kms) {
  4786. SDE_ERROR("invalid sde_kms\n");
  4787. return -EINVAL;
  4788. }
  4789. buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
  4790. if (copy_from_user(buf, user_buf, buff_copy)) {
  4791. SDE_ERROR("buffer copy failed\n");
  4792. return -EINVAL;
  4793. }
  4794. buf[buff_copy] = 0; /* end of string */
  4795. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
  4796. return -EINVAL;
  4797. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  4798. SDE_DEBUG("crtc:%d misr enable/disable not allowed\n",
  4799. DRMID(crtc));
  4800. return -EINVAL;
  4801. }
  4802. rc = pm_runtime_get_sync(crtc->dev->dev);
  4803. if (rc < 0)
  4804. return rc;
  4805. sde_crtc->misr_enable_debugfs = enable;
  4806. sde_crtc_misr_setup(crtc, enable, frame_count);
  4807. pm_runtime_put_sync(crtc->dev->dev);
  4808. return count;
  4809. }
  4810. static ssize_t _sde_crtc_misr_read(struct file *file,
  4811. char __user *user_buff, size_t count, loff_t *ppos)
  4812. {
  4813. struct drm_crtc *crtc;
  4814. struct sde_crtc *sde_crtc;
  4815. struct sde_kms *sde_kms;
  4816. struct sde_crtc_mixer *m;
  4817. int i = 0, rc;
  4818. ssize_t len = 0;
  4819. char buf[MISR_BUFF_SIZE + 1] = {'\0'};
  4820. if (*ppos)
  4821. return 0;
  4822. if (!file || !file->private_data)
  4823. return -EINVAL;
  4824. sde_crtc = file->private_data;
  4825. crtc = &sde_crtc->base;
  4826. sde_kms = _sde_crtc_get_kms(crtc);
  4827. if (!sde_kms)
  4828. return -EINVAL;
  4829. rc = pm_runtime_get_sync(crtc->dev->dev);
  4830. if (rc < 0)
  4831. return rc;
  4832. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  4833. SDE_DEBUG("crtc:%d misr read not allowed\n", DRMID(crtc));
  4834. goto end;
  4835. }
  4836. if (!sde_crtc->misr_enable_debugfs) {
  4837. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4838. "disabled\n");
  4839. goto buff_check;
  4840. }
  4841. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  4842. u32 misr_value = 0;
  4843. m = &sde_crtc->mixers[i];
  4844. if (!m->hw_lm || !m->hw_lm->ops.collect_misr) {
  4845. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4846. "invalid\n");
  4847. SDE_ERROR("crtc:%d invalid misr ops\n", DRMID(crtc));
  4848. continue;
  4849. }
  4850. rc = m->hw_lm->ops.collect_misr(m->hw_lm, false, &misr_value);
  4851. if (rc) {
  4852. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4853. "invalid\n");
  4854. SDE_ERROR("crtc:%d failed to collect misr %d\n",
  4855. DRMID(crtc), rc);
  4856. continue;
  4857. } else {
  4858. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4859. "lm idx:%d\n", m->hw_lm->idx - LM_0);
  4860. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4861. "0x%x\n", misr_value);
  4862. }
  4863. }
  4864. buff_check:
  4865. if (count <= len) {
  4866. len = 0;
  4867. goto end;
  4868. }
  4869. if (copy_to_user(user_buff, buf, len)) {
  4870. len = -EFAULT;
  4871. goto end;
  4872. }
  4873. *ppos += len; /* increase offset */
  4874. end:
  4875. pm_runtime_put_sync(crtc->dev->dev);
  4876. return len;
  4877. }
  4878. #define DEFINE_SDE_DEBUGFS_SEQ_FOPS(__prefix) \
  4879. static int __prefix ## _open(struct inode *inode, struct file *file) \
  4880. { \
  4881. return single_open(file, __prefix ## _show, inode->i_private); \
  4882. } \
  4883. static const struct file_operations __prefix ## _fops = { \
  4884. .owner = THIS_MODULE, \
  4885. .open = __prefix ## _open, \
  4886. .release = single_release, \
  4887. .read = seq_read, \
  4888. .llseek = seq_lseek, \
  4889. }
  4890. static int sde_crtc_debugfs_state_show(struct seq_file *s, void *v)
  4891. {
  4892. struct drm_crtc *crtc = (struct drm_crtc *) s->private;
  4893. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  4894. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
  4895. int i;
  4896. seq_printf(s, "num_connectors: %d\n", cstate->num_connectors);
  4897. seq_printf(s, "client type: %d\n", sde_crtc_get_client_type(crtc));
  4898. seq_printf(s, "intf_mode: %d\n", sde_crtc_get_intf_mode(crtc,
  4899. crtc->state));
  4900. seq_printf(s, "core_clk_rate: %llu\n",
  4901. sde_crtc->cur_perf.core_clk_rate);
  4902. for (i = SDE_POWER_HANDLE_DBUS_ID_MNOC;
  4903. i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++) {
  4904. seq_printf(s, "bw_ctl[%s]: %llu\n",
  4905. sde_power_handle_get_dbus_name(i),
  4906. sde_crtc->cur_perf.bw_ctl[i]);
  4907. seq_printf(s, "max_per_pipe_ib[%s]: %llu\n",
  4908. sde_power_handle_get_dbus_name(i),
  4909. sde_crtc->cur_perf.max_per_pipe_ib[i]);
  4910. }
  4911. return 0;
  4912. }
  4913. DEFINE_SDE_DEBUGFS_SEQ_FOPS(sde_crtc_debugfs_state);
  4914. static int _sde_debugfs_fence_status_show(struct seq_file *s, void *data)
  4915. {
  4916. struct drm_crtc *crtc;
  4917. struct drm_plane *plane;
  4918. struct drm_connector *conn;
  4919. struct drm_mode_object *drm_obj;
  4920. struct sde_crtc *sde_crtc;
  4921. struct sde_crtc_state *cstate;
  4922. struct sde_fence_context *ctx;
  4923. struct drm_connector_list_iter conn_iter;
  4924. struct drm_device *dev;
  4925. if (!s || !s->private)
  4926. return -EINVAL;
  4927. sde_crtc = s->private;
  4928. crtc = &sde_crtc->base;
  4929. dev = crtc->dev;
  4930. cstate = to_sde_crtc_state(crtc->state);
  4931. /* Dump input fence info */
  4932. seq_puts(s, "===Input fence===\n");
  4933. drm_atomic_crtc_for_each_plane(plane, crtc) {
  4934. struct sde_plane_state *pstate;
  4935. struct dma_fence *fence;
  4936. pstate = to_sde_plane_state(plane->state);
  4937. if (!pstate)
  4938. continue;
  4939. seq_printf(s, "plane:%u stage:%d\n", plane->base.id,
  4940. pstate->stage);
  4941. fence = pstate->input_fence;
  4942. if (fence)
  4943. sde_fence_list_dump(fence, &s);
  4944. }
  4945. /* Dump release fence info */
  4946. seq_puts(s, "\n");
  4947. seq_puts(s, "===Release fence===\n");
  4948. ctx = sde_crtc->output_fence;
  4949. drm_obj = &crtc->base;
  4950. sde_debugfs_timeline_dump(ctx, drm_obj, &s);
  4951. seq_puts(s, "\n");
  4952. /* Dump retire fence info */
  4953. seq_puts(s, "===Retire fence===\n");
  4954. drm_connector_list_iter_begin(dev, &conn_iter);
  4955. drm_for_each_connector_iter(conn, &conn_iter)
  4956. if (conn->state && conn->state->crtc == crtc &&
  4957. cstate->num_connectors < MAX_CONNECTORS) {
  4958. struct sde_connector *c_conn;
  4959. c_conn = to_sde_connector(conn);
  4960. ctx = c_conn->retire_fence;
  4961. drm_obj = &conn->base;
  4962. sde_debugfs_timeline_dump(ctx, drm_obj, &s);
  4963. }
  4964. drm_connector_list_iter_end(&conn_iter);
  4965. seq_puts(s, "\n");
  4966. return 0;
  4967. }
  4968. static int _sde_debugfs_fence_status(struct inode *inode, struct file *file)
  4969. {
  4970. return single_open(file, _sde_debugfs_fence_status_show,
  4971. inode->i_private);
  4972. }
  4973. static int _sde_crtc_init_debugfs(struct drm_crtc *crtc)
  4974. {
  4975. struct sde_crtc *sde_crtc;
  4976. struct sde_kms *sde_kms;
  4977. static const struct file_operations debugfs_status_fops = {
  4978. .open = _sde_debugfs_status_open,
  4979. .read = seq_read,
  4980. .llseek = seq_lseek,
  4981. .release = single_release,
  4982. };
  4983. static const struct file_operations debugfs_misr_fops = {
  4984. .open = simple_open,
  4985. .read = _sde_crtc_misr_read,
  4986. .write = _sde_crtc_misr_setup,
  4987. };
  4988. static const struct file_operations debugfs_fps_fops = {
  4989. .open = _sde_debugfs_fps_status,
  4990. .read = seq_read,
  4991. };
  4992. static const struct file_operations debugfs_fence_fops = {
  4993. .open = _sde_debugfs_fence_status,
  4994. .read = seq_read,
  4995. };
  4996. if (!crtc)
  4997. return -EINVAL;
  4998. sde_crtc = to_sde_crtc(crtc);
  4999. sde_kms = _sde_crtc_get_kms(crtc);
  5000. if (!sde_kms)
  5001. return -EINVAL;
  5002. sde_crtc->debugfs_root = debugfs_create_dir(sde_crtc->name,
  5003. crtc->dev->primary->debugfs_root);
  5004. if (!sde_crtc->debugfs_root)
  5005. return -ENOMEM;
  5006. /* don't error check these */
  5007. debugfs_create_file("status", 0400,
  5008. sde_crtc->debugfs_root,
  5009. sde_crtc, &debugfs_status_fops);
  5010. debugfs_create_file("state", 0400,
  5011. sde_crtc->debugfs_root,
  5012. &sde_crtc->base,
  5013. &sde_crtc_debugfs_state_fops);
  5014. debugfs_create_file("misr_data", 0600, sde_crtc->debugfs_root,
  5015. sde_crtc, &debugfs_misr_fops);
  5016. debugfs_create_file("fps", 0400, sde_crtc->debugfs_root,
  5017. sde_crtc, &debugfs_fps_fops);
  5018. debugfs_create_file("fence_status", 0400, sde_crtc->debugfs_root,
  5019. sde_crtc, &debugfs_fence_fops);
  5020. return 0;
  5021. }
  5022. static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc)
  5023. {
  5024. struct sde_crtc *sde_crtc;
  5025. if (!crtc)
  5026. return;
  5027. sde_crtc = to_sde_crtc(crtc);
  5028. debugfs_remove_recursive(sde_crtc->debugfs_root);
  5029. }
  5030. #else
  5031. static int _sde_crtc_init_debugfs(struct drm_crtc *crtc)
  5032. {
  5033. return 0;
  5034. }
  5035. static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc)
  5036. {
  5037. }
  5038. #endif /* CONFIG_DEBUG_FS */
  5039. static int sde_crtc_late_register(struct drm_crtc *crtc)
  5040. {
  5041. return _sde_crtc_init_debugfs(crtc);
  5042. }
  5043. static void sde_crtc_early_unregister(struct drm_crtc *crtc)
  5044. {
  5045. _sde_crtc_destroy_debugfs(crtc);
  5046. }
  5047. static const struct drm_crtc_funcs sde_crtc_funcs = {
  5048. .set_config = drm_atomic_helper_set_config,
  5049. .destroy = sde_crtc_destroy,
  5050. .page_flip = drm_atomic_helper_page_flip,
  5051. .atomic_set_property = sde_crtc_atomic_set_property,
  5052. .atomic_get_property = sde_crtc_atomic_get_property,
  5053. .reset = sde_crtc_reset,
  5054. .atomic_duplicate_state = sde_crtc_duplicate_state,
  5055. .atomic_destroy_state = sde_crtc_destroy_state,
  5056. .late_register = sde_crtc_late_register,
  5057. .early_unregister = sde_crtc_early_unregister,
  5058. };
  5059. static const struct drm_crtc_helper_funcs sde_crtc_helper_funcs = {
  5060. .mode_fixup = sde_crtc_mode_fixup,
  5061. .disable = sde_crtc_disable,
  5062. .atomic_enable = sde_crtc_enable,
  5063. .atomic_check = sde_crtc_atomic_check,
  5064. .atomic_begin = sde_crtc_atomic_begin,
  5065. .atomic_flush = sde_crtc_atomic_flush,
  5066. };
  5067. static void _sde_crtc_event_cb(struct kthread_work *work)
  5068. {
  5069. struct sde_crtc_event *event;
  5070. struct sde_crtc *sde_crtc;
  5071. unsigned long irq_flags;
  5072. if (!work) {
  5073. SDE_ERROR("invalid work item\n");
  5074. return;
  5075. }
  5076. event = container_of(work, struct sde_crtc_event, kt_work);
  5077. /* set sde_crtc to NULL for static work structures */
  5078. sde_crtc = event->sde_crtc;
  5079. if (!sde_crtc)
  5080. return;
  5081. if (event->cb_func)
  5082. event->cb_func(&sde_crtc->base, event->usr);
  5083. spin_lock_irqsave(&sde_crtc->event_lock, irq_flags);
  5084. list_add_tail(&event->list, &sde_crtc->event_free_list);
  5085. spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags);
  5086. }
  5087. int sde_crtc_event_queue(struct drm_crtc *crtc,
  5088. void (*func)(struct drm_crtc *crtc, void *usr),
  5089. void *usr, bool color_processing_event)
  5090. {
  5091. unsigned long irq_flags;
  5092. struct sde_crtc *sde_crtc;
  5093. struct msm_drm_private *priv;
  5094. struct sde_crtc_event *event = NULL;
  5095. u32 crtc_id;
  5096. if (!crtc || !crtc->dev || !crtc->dev->dev_private || !func) {
  5097. SDE_ERROR("invalid parameters\n");
  5098. return -EINVAL;
  5099. }
  5100. sde_crtc = to_sde_crtc(crtc);
  5101. priv = crtc->dev->dev_private;
  5102. crtc_id = drm_crtc_index(crtc);
  5103. /*
  5104. * Obtain an event struct from the private cache. This event
  5105. * queue may be called from ISR contexts, so use a private
  5106. * cache to avoid calling any memory allocation functions.
  5107. */
  5108. spin_lock_irqsave(&sde_crtc->event_lock, irq_flags);
  5109. if (!list_empty(&sde_crtc->event_free_list)) {
  5110. event = list_first_entry(&sde_crtc->event_free_list,
  5111. struct sde_crtc_event, list);
  5112. list_del_init(&event->list);
  5113. }
  5114. spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags);
  5115. if (!event)
  5116. return -ENOMEM;
  5117. /* populate event node */
  5118. event->sde_crtc = sde_crtc;
  5119. event->cb_func = func;
  5120. event->usr = usr;
  5121. /* queue new event request */
  5122. kthread_init_work(&event->kt_work, _sde_crtc_event_cb);
  5123. if (color_processing_event)
  5124. kthread_queue_work(&priv->pp_event_worker,
  5125. &event->kt_work);
  5126. else
  5127. kthread_queue_work(&priv->event_thread[crtc_id].worker,
  5128. &event->kt_work);
  5129. return 0;
  5130. }
  5131. static int _sde_crtc_init_events(struct sde_crtc *sde_crtc)
  5132. {
  5133. int i, rc = 0;
  5134. if (!sde_crtc) {
  5135. SDE_ERROR("invalid crtc\n");
  5136. return -EINVAL;
  5137. }
  5138. spin_lock_init(&sde_crtc->event_lock);
  5139. INIT_LIST_HEAD(&sde_crtc->event_free_list);
  5140. for (i = 0; i < SDE_CRTC_MAX_EVENT_COUNT; ++i)
  5141. list_add_tail(&sde_crtc->event_cache[i].list,
  5142. &sde_crtc->event_free_list);
  5143. return rc;
  5144. }
  5145. void sde_crtc_static_img_control(struct drm_crtc *crtc,
  5146. enum sde_crtc_cache_state state,
  5147. bool is_vidmode)
  5148. {
  5149. struct drm_plane *plane;
  5150. struct sde_crtc *sde_crtc;
  5151. if (!crtc || !crtc->dev)
  5152. return;
  5153. sde_crtc = to_sde_crtc(crtc);
  5154. switch (state) {
  5155. case CACHE_STATE_NORMAL:
  5156. if (sde_crtc->cache_state == CACHE_STATE_DISABLED
  5157. && !is_vidmode)
  5158. return;
  5159. kthread_cancel_delayed_work_sync(
  5160. &sde_crtc->static_cache_read_work);
  5161. break;
  5162. case CACHE_STATE_PRE_CACHE:
  5163. if (sde_crtc->cache_state != CACHE_STATE_NORMAL)
  5164. return;
  5165. break;
  5166. case CACHE_STATE_FRAME_WRITE:
  5167. if (sde_crtc->cache_state != CACHE_STATE_PRE_CACHE)
  5168. return;
  5169. break;
  5170. case CACHE_STATE_FRAME_READ:
  5171. if (sde_crtc->cache_state != CACHE_STATE_FRAME_WRITE)
  5172. return;
  5173. break;
  5174. case CACHE_STATE_DISABLED:
  5175. break;
  5176. default:
  5177. return;
  5178. }
  5179. sde_crtc->cache_state = state;
  5180. drm_atomic_crtc_for_each_plane(plane, crtc)
  5181. sde_plane_static_img_control(plane, state);
  5182. }
  5183. /*
  5184. * __sde_crtc_static_cache_read_work - transition to cache read
  5185. */
  5186. void __sde_crtc_static_cache_read_work(struct kthread_work *work)
  5187. {
  5188. struct sde_crtc *sde_crtc = container_of(work, struct sde_crtc,
  5189. static_cache_read_work.work);
  5190. struct drm_crtc *crtc;
  5191. struct drm_plane *plane;
  5192. struct sde_crtc_mixer *mixer;
  5193. struct sde_hw_ctl *ctl;
  5194. if (!sde_crtc)
  5195. return;
  5196. crtc = &sde_crtc->base;
  5197. mixer = sde_crtc->mixers;
  5198. if (!mixer)
  5199. return;
  5200. ctl = mixer->hw_ctl;
  5201. if (sde_crtc->cache_state != CACHE_STATE_FRAME_WRITE ||
  5202. !ctl->ops.update_bitmask_ctl ||
  5203. !ctl->ops.trigger_flush)
  5204. return;
  5205. sde_crtc_static_img_control(crtc, CACHE_STATE_FRAME_READ, false);
  5206. drm_atomic_crtc_for_each_plane(plane, crtc) {
  5207. if (!plane->state)
  5208. continue;
  5209. sde_plane_ctl_flush(plane, ctl, true);
  5210. }
  5211. ctl->ops.update_bitmask_ctl(ctl, true);
  5212. ctl->ops.trigger_flush(ctl);
  5213. }
  5214. void sde_crtc_static_cache_read_kickoff(struct drm_crtc *crtc)
  5215. {
  5216. struct drm_device *dev;
  5217. struct msm_drm_private *priv;
  5218. struct msm_drm_thread *disp_thread;
  5219. struct sde_crtc *sde_crtc;
  5220. struct sde_crtc_state *cstate;
  5221. u32 msecs_fps = 0;
  5222. if (!crtc)
  5223. return;
  5224. dev = crtc->dev;
  5225. sde_crtc = to_sde_crtc(crtc);
  5226. cstate = to_sde_crtc_state(crtc->state);
  5227. if (!dev || !dev->dev_private || !sde_crtc)
  5228. return;
  5229. priv = dev->dev_private;
  5230. disp_thread = &priv->disp_thread[crtc->index];
  5231. if (sde_crtc->cache_state != CACHE_STATE_FRAME_WRITE)
  5232. return;
  5233. msecs_fps = DIV_ROUND_UP((1 * 1000), sde_crtc_get_fps_mode(crtc));
  5234. /* Kickoff transition to read state after next vblank */
  5235. kthread_queue_delayed_work(&disp_thread->worker,
  5236. &sde_crtc->static_cache_read_work,
  5237. msecs_to_jiffies(msecs_fps));
  5238. }
  5239. /*
  5240. * __sde_crtc_idle_notify_work - signal idle timeout to user space
  5241. */
  5242. static void __sde_crtc_idle_notify_work(struct kthread_work *work)
  5243. {
  5244. struct sde_crtc *sde_crtc = container_of(work, struct sde_crtc,
  5245. idle_notify_work.work);
  5246. struct drm_crtc *crtc;
  5247. struct drm_event event;
  5248. int ret = 0;
  5249. if (!sde_crtc) {
  5250. SDE_ERROR("invalid sde crtc\n");
  5251. } else {
  5252. crtc = &sde_crtc->base;
  5253. event.type = DRM_EVENT_IDLE_NOTIFY;
  5254. event.length = sizeof(u32);
  5255. msm_mode_object_event_notify(&crtc->base, crtc->dev,
  5256. &event, (u8 *)&ret);
  5257. SDE_DEBUG("crtc[%d]: idle timeout notified\n", crtc->base.id);
  5258. sde_crtc_static_img_control(crtc, CACHE_STATE_PRE_CACHE, false);
  5259. }
  5260. }
  5261. /* initialize crtc */
  5262. struct drm_crtc *sde_crtc_init(struct drm_device *dev, struct drm_plane *plane)
  5263. {
  5264. struct drm_crtc *crtc = NULL;
  5265. struct sde_crtc *sde_crtc = NULL;
  5266. struct msm_drm_private *priv = NULL;
  5267. struct sde_kms *kms = NULL;
  5268. int i, rc;
  5269. priv = dev->dev_private;
  5270. kms = to_sde_kms(priv->kms);
  5271. sde_crtc = kzalloc(sizeof(*sde_crtc), GFP_KERNEL);
  5272. if (!sde_crtc)
  5273. return ERR_PTR(-ENOMEM);
  5274. crtc = &sde_crtc->base;
  5275. crtc->dev = dev;
  5276. mutex_init(&sde_crtc->crtc_lock);
  5277. spin_lock_init(&sde_crtc->spin_lock);
  5278. atomic_set(&sde_crtc->frame_pending, 0);
  5279. sde_crtc->enabled = false;
  5280. /* Below parameters are for fps calculation for sysfs node */
  5281. sde_crtc->fps_info.fps_periodic_duration = DEFAULT_FPS_PERIOD_1_SEC;
  5282. sde_crtc->fps_info.time_buf = kmalloc_array(MAX_FRAME_COUNT,
  5283. sizeof(ktime_t), GFP_KERNEL);
  5284. if (!sde_crtc->fps_info.time_buf)
  5285. SDE_ERROR("invalid buffer\n");
  5286. else
  5287. memset(sde_crtc->fps_info.time_buf, 0,
  5288. sizeof(*(sde_crtc->fps_info.time_buf)));
  5289. INIT_LIST_HEAD(&sde_crtc->frame_event_list);
  5290. INIT_LIST_HEAD(&sde_crtc->user_event_list);
  5291. for (i = 0; i < ARRAY_SIZE(sde_crtc->frame_events); i++) {
  5292. INIT_LIST_HEAD(&sde_crtc->frame_events[i].list);
  5293. list_add(&sde_crtc->frame_events[i].list,
  5294. &sde_crtc->frame_event_list);
  5295. kthread_init_work(&sde_crtc->frame_events[i].work,
  5296. sde_crtc_frame_event_work);
  5297. }
  5298. drm_crtc_init_with_planes(dev, crtc, plane, NULL, &sde_crtc_funcs,
  5299. NULL);
  5300. drm_crtc_helper_add(crtc, &sde_crtc_helper_funcs);
  5301. /* save user friendly CRTC name for later */
  5302. snprintf(sde_crtc->name, SDE_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
  5303. /* initialize event handling */
  5304. rc = _sde_crtc_init_events(sde_crtc);
  5305. if (rc) {
  5306. drm_crtc_cleanup(crtc);
  5307. kfree(sde_crtc);
  5308. return ERR_PTR(rc);
  5309. }
  5310. /* initialize output fence support */
  5311. sde_crtc->output_fence = sde_fence_init(sde_crtc->name, crtc->base.id);
  5312. if (IS_ERR(sde_crtc->output_fence)) {
  5313. rc = PTR_ERR(sde_crtc->output_fence);
  5314. SDE_ERROR("failed to init fence, %d\n", rc);
  5315. drm_crtc_cleanup(crtc);
  5316. kfree(sde_crtc);
  5317. return ERR_PTR(rc);
  5318. }
  5319. /* create CRTC properties */
  5320. msm_property_init(&sde_crtc->property_info, &crtc->base, dev,
  5321. priv->crtc_property, sde_crtc->property_data,
  5322. CRTC_PROP_COUNT, CRTC_PROP_BLOBCOUNT,
  5323. sizeof(struct sde_crtc_state));
  5324. sde_crtc_install_properties(crtc, kms->catalog);
  5325. /* Install color processing properties */
  5326. sde_cp_crtc_init(crtc);
  5327. sde_cp_crtc_install_properties(crtc);
  5328. for (i = 0; i < SDE_SYS_CACHE_MAX; i++) {
  5329. sde_crtc->cur_perf.llcc_active[i] = false;
  5330. sde_crtc->new_perf.llcc_active[i] = false;
  5331. }
  5332. kthread_init_delayed_work(&sde_crtc->idle_notify_work,
  5333. __sde_crtc_idle_notify_work);
  5334. kthread_init_delayed_work(&sde_crtc->static_cache_read_work,
  5335. __sde_crtc_static_cache_read_work);
  5336. SDE_DEBUG("crtc=%d new_llcc=%d, old_llcc=%d\n",
  5337. crtc->base.id,
  5338. sde_crtc->new_perf.llcc_active,
  5339. sde_crtc->cur_perf.llcc_active);
  5340. SDE_DEBUG("%s: successfully initialized crtc\n", sde_crtc->name);
  5341. return crtc;
  5342. }
  5343. int sde_crtc_post_init(struct drm_device *dev, struct drm_crtc *crtc)
  5344. {
  5345. struct sde_crtc *sde_crtc;
  5346. int rc = 0;
  5347. if (!dev || !dev->primary || !dev->primary->kdev || !crtc) {
  5348. SDE_ERROR("invalid input param(s)\n");
  5349. rc = -EINVAL;
  5350. goto end;
  5351. }
  5352. sde_crtc = to_sde_crtc(crtc);
  5353. sde_crtc->sysfs_dev = device_create_with_groups(
  5354. dev->primary->kdev->class, dev->primary->kdev, 0, crtc,
  5355. sde_crtc_attr_groups, "sde-crtc-%d", crtc->index);
  5356. if (IS_ERR_OR_NULL(sde_crtc->sysfs_dev)) {
  5357. SDE_ERROR("crtc:%d sysfs create failed rc:%ld\n", crtc->index,
  5358. PTR_ERR(sde_crtc->sysfs_dev));
  5359. if (!sde_crtc->sysfs_dev)
  5360. rc = -EINVAL;
  5361. else
  5362. rc = PTR_ERR(sde_crtc->sysfs_dev);
  5363. goto end;
  5364. }
  5365. sde_crtc->vsync_event_sf = sysfs_get_dirent(
  5366. sde_crtc->sysfs_dev->kobj.sd, "vsync_event");
  5367. if (!sde_crtc->vsync_event_sf)
  5368. SDE_ERROR("crtc:%d vsync_event sysfs create failed\n",
  5369. crtc->base.id);
  5370. end:
  5371. return rc;
  5372. }
  5373. static int _sde_crtc_event_enable(struct sde_kms *kms,
  5374. struct drm_crtc *crtc_drm, u32 event)
  5375. {
  5376. struct sde_crtc *crtc = NULL;
  5377. struct sde_crtc_irq_info *node;
  5378. unsigned long flags;
  5379. bool found = false;
  5380. int ret, i = 0;
  5381. bool add_event = false;
  5382. crtc = to_sde_crtc(crtc_drm);
  5383. spin_lock_irqsave(&crtc->spin_lock, flags);
  5384. list_for_each_entry(node, &crtc->user_event_list, list) {
  5385. if (node->event == event) {
  5386. found = true;
  5387. break;
  5388. }
  5389. }
  5390. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5391. /* event already enabled */
  5392. if (found)
  5393. return 0;
  5394. node = NULL;
  5395. for (i = 0; i < ARRAY_SIZE(custom_events); i++) {
  5396. if (custom_events[i].event == event &&
  5397. custom_events[i].func) {
  5398. node = kzalloc(sizeof(*node), GFP_KERNEL);
  5399. if (!node)
  5400. return -ENOMEM;
  5401. INIT_LIST_HEAD(&node->list);
  5402. INIT_LIST_HEAD(&node->irq.list);
  5403. node->func = custom_events[i].func;
  5404. node->event = event;
  5405. node->state = IRQ_NOINIT;
  5406. spin_lock_init(&node->state_lock);
  5407. break;
  5408. }
  5409. }
  5410. if (!node) {
  5411. SDE_ERROR("unsupported event %x\n", event);
  5412. return -EINVAL;
  5413. }
  5414. ret = 0;
  5415. if (crtc_drm->enabled) {
  5416. ret = pm_runtime_get_sync(crtc_drm->dev->dev);
  5417. if (ret < 0) {
  5418. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  5419. kfree(node);
  5420. return ret;
  5421. }
  5422. INIT_LIST_HEAD(&node->irq.list);
  5423. mutex_lock(&crtc->crtc_lock);
  5424. ret = node->func(crtc_drm, true, &node->irq);
  5425. if (!ret) {
  5426. spin_lock_irqsave(&crtc->spin_lock, flags);
  5427. list_add_tail(&node->list, &crtc->user_event_list);
  5428. add_event = true;
  5429. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5430. }
  5431. mutex_unlock(&crtc->crtc_lock);
  5432. pm_runtime_put_sync(crtc_drm->dev->dev);
  5433. }
  5434. if (add_event)
  5435. return 0;
  5436. if (!ret) {
  5437. spin_lock_irqsave(&crtc->spin_lock, flags);
  5438. list_add_tail(&node->list, &crtc->user_event_list);
  5439. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5440. } else {
  5441. kfree(node);
  5442. }
  5443. return ret;
  5444. }
  5445. static int _sde_crtc_event_disable(struct sde_kms *kms,
  5446. struct drm_crtc *crtc_drm, u32 event)
  5447. {
  5448. struct sde_crtc *crtc = NULL;
  5449. struct sde_crtc_irq_info *node = NULL;
  5450. unsigned long flags;
  5451. bool found = false;
  5452. int ret;
  5453. crtc = to_sde_crtc(crtc_drm);
  5454. spin_lock_irqsave(&crtc->spin_lock, flags);
  5455. list_for_each_entry(node, &crtc->user_event_list, list) {
  5456. if (node->event == event) {
  5457. list_del_init(&node->list);
  5458. found = true;
  5459. break;
  5460. }
  5461. }
  5462. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5463. /* event already disabled */
  5464. if (!found)
  5465. return 0;
  5466. /**
  5467. * crtc is disabled interrupts are cleared remove from the list,
  5468. * no need to disable/de-register.
  5469. */
  5470. if (!crtc_drm->enabled) {
  5471. kfree(node);
  5472. return 0;
  5473. }
  5474. ret = pm_runtime_get_sync(crtc_drm->dev->dev);
  5475. if (ret < 0) {
  5476. SDE_ERROR("failed to enable power resource %d\n", ret);
  5477. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  5478. kfree(node);
  5479. return ret;
  5480. }
  5481. ret = node->func(crtc_drm, false, &node->irq);
  5482. if (ret) {
  5483. spin_lock_irqsave(&crtc->spin_lock, flags);
  5484. list_add_tail(&node->list, &crtc->user_event_list);
  5485. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5486. } else {
  5487. kfree(node);
  5488. }
  5489. pm_runtime_put_sync(crtc_drm->dev->dev);
  5490. return ret;
  5491. }
  5492. int sde_crtc_register_custom_event(struct sde_kms *kms,
  5493. struct drm_crtc *crtc_drm, u32 event, bool en)
  5494. {
  5495. struct sde_crtc *crtc = NULL;
  5496. int ret;
  5497. crtc = to_sde_crtc(crtc_drm);
  5498. if (!crtc || !kms || !kms->dev) {
  5499. DRM_ERROR("invalid sde_crtc %pK kms %pK dev %pK\n", crtc,
  5500. kms, ((kms) ? (kms->dev) : NULL));
  5501. return -EINVAL;
  5502. }
  5503. if (en)
  5504. ret = _sde_crtc_event_enable(kms, crtc_drm, event);
  5505. else
  5506. ret = _sde_crtc_event_disable(kms, crtc_drm, event);
  5507. return ret;
  5508. }
  5509. static int sde_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
  5510. bool en, struct sde_irq_callback *irq)
  5511. {
  5512. return 0;
  5513. }
  5514. static int sde_crtc_pm_event_handler(struct drm_crtc *crtc, bool en,
  5515. struct sde_irq_callback *noirq)
  5516. {
  5517. /*
  5518. * IRQ object noirq is not being used here since there is
  5519. * no crtc irq from pm event.
  5520. */
  5521. return 0;
  5522. }
  5523. static int sde_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
  5524. bool en, struct sde_irq_callback *irq)
  5525. {
  5526. return 0;
  5527. }
  5528. /**
  5529. * sde_crtc_update_cont_splash_settings - update mixer settings
  5530. * and initial clk during device bootup for cont_splash use case
  5531. * @crtc: Pointer to drm crtc structure
  5532. */
  5533. void sde_crtc_update_cont_splash_settings(struct drm_crtc *crtc)
  5534. {
  5535. struct sde_kms *kms = NULL;
  5536. struct msm_drm_private *priv;
  5537. struct sde_crtc *sde_crtc;
  5538. u64 rate;
  5539. if (!crtc || !crtc->state || !crtc->dev || !crtc->dev->dev_private) {
  5540. SDE_ERROR("invalid crtc\n");
  5541. return;
  5542. }
  5543. priv = crtc->dev->dev_private;
  5544. kms = to_sde_kms(priv->kms);
  5545. if (!kms || !kms->catalog) {
  5546. SDE_ERROR("invalid parameters\n");
  5547. return;
  5548. }
  5549. _sde_crtc_setup_mixers(crtc);
  5550. crtc->enabled = true;
  5551. /* update core clk value for initial state with cont-splash */
  5552. sde_crtc = to_sde_crtc(crtc);
  5553. rate = sde_power_clk_get_rate(&priv->phandle, kms->perf.clk_name);
  5554. sde_crtc->cur_perf.core_clk_rate = (rate > 0) ?
  5555. rate : kms->perf.max_core_clk_rate;
  5556. sde_crtc->cur_perf.core_clk_rate = kms->perf.max_core_clk_rate;
  5557. }