hal_6290.c 53 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "qdf_types.h"
  20. #include "qdf_util.h"
  21. #include "qdf_types.h"
  22. #include "qdf_lock.h"
  23. #include "qdf_mem.h"
  24. #include "qdf_nbuf.h"
  25. #include "hal_li_hw_headers.h"
  26. #include "hal_internal.h"
  27. #include "hal_api.h"
  28. #include "target_type.h"
  29. #include "wcss_version.h"
  30. #include "qdf_module.h"
  31. #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \
  32. RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET
  33. #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \
  34. RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK
  35. #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \
  36. RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB
  37. #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \
  38. PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET
  39. #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \
  40. PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET
  41. #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \
  42. PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET
  43. #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \
  44. PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET
  45. #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \
  46. PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET
  47. #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \
  48. PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET
  49. #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \
  50. PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET
  51. #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \
  52. PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET
  53. #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \
  54. PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET
  55. #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \
  56. PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET
  57. #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \
  58. PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET
  59. #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
  60. RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET
  61. #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
  62. RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
  63. #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
  64. RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
  65. #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
  66. RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
  67. #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
  68. REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
  69. #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
  70. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER
  71. #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
  72. RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
  73. #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
  74. RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
  75. #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
  76. TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET
  77. #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
  78. TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET
  79. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
  80. TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET
  81. #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
  82. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB
  83. #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
  84. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK
  85. #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
  86. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB
  87. #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
  88. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK
  89. #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
  90. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB
  91. #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
  92. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK
  93. #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
  94. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB
  95. #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
  96. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK
  97. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
  98. TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB
  99. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
  100. TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK
  101. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
  102. WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK
  103. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
  104. WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET
  105. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
  106. WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB
  107. #include "hal_6290_tx.h"
  108. #include "hal_6290_rx.h"
  109. #include <hal_generic_api.h>
  110. #include "hal_li_rx.h"
  111. #include "hal_li_api.h"
  112. #include "hal_li_generic_api.h"
  113. /**
  114. * hal_rx_get_rx_fragment_number_6290(): Function to retrieve rx fragment number
  115. *
  116. * @nbuf: Network buffer
  117. * Returns: rx fragment number
  118. */
  119. static
  120. uint8_t hal_rx_get_rx_fragment_number_6290(uint8_t *buf)
  121. {
  122. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  123. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  124. /* Return first 4 bits as fragment number */
  125. return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) &
  126. DOT11_SEQ_FRAG_MASK);
  127. }
  128. /**
  129. * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC
  130. * from rx_msdu_end TLV
  131. *
  132. * @ buf: pointer to the start of RX PKT TLV headers
  133. * Return: da_is_mcbc
  134. */
  135. static inline uint8_t
  136. hal_rx_msdu_end_da_is_mcbc_get_6290(uint8_t *buf)
  137. {
  138. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  139. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  140. return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
  141. }
  142. /**
  143. * hal_rx_msdu_end_sa_is_valid_get_6290(): API to get_6290 the
  144. * sa_is_valid bit from rx_msdu_end TLV
  145. *
  146. * @ buf: pointer to the start of RX PKT TLV headers
  147. * Return: sa_is_valid bit
  148. */
  149. static uint8_t
  150. hal_rx_msdu_end_sa_is_valid_get_6290(uint8_t *buf)
  151. {
  152. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  153. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  154. uint8_t sa_is_valid;
  155. sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end);
  156. return sa_is_valid;
  157. }
  158. /**
  159. * hal_rx_msdu_end_sa_idx_get_6290(): API to get_6290 the
  160. * sa_idx from rx_msdu_end TLV
  161. *
  162. * @ buf: pointer to the start of RX PKT TLV headers
  163. * Return: sa_idx (SA AST index)
  164. */
  165. static
  166. uint16_t hal_rx_msdu_end_sa_idx_get_6290(uint8_t *buf)
  167. {
  168. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  169. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  170. uint16_t sa_idx;
  171. sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end);
  172. return sa_idx;
  173. }
  174. /**
  175. * hal_rx_desc_is_first_msdu_6290() - Check if first msdu
  176. *
  177. * @hal_soc_hdl: hal_soc handle
  178. * @hw_desc_addr: hardware descriptor address
  179. *
  180. * Return: 0 - success/ non-zero failure
  181. */
  182. static uint32_t hal_rx_desc_is_first_msdu_6290(void *hw_desc_addr)
  183. {
  184. struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
  185. struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
  186. return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU);
  187. }
  188. /**
  189. * hal_rx_msdu_end_l3_hdr_padding_get_6290(): API to get_6290 the
  190. * l3_header padding from rx_msdu_end TLV
  191. *
  192. * @ buf: pointer to the start of RX PKT TLV headers
  193. * Return: number of l3 header padding bytes
  194. */
  195. static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6290(uint8_t *buf)
  196. {
  197. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  198. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  199. uint32_t l3_header_padding;
  200. l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
  201. return l3_header_padding;
  202. }
  203. /*
  204. * @ hal_rx_encryption_info_valid_6290: Returns encryption type.
  205. *
  206. * @ buf: rx_tlv_hdr of the received packet
  207. * @ Return: encryption type
  208. */
  209. static uint32_t hal_rx_encryption_info_valid_6290(uint8_t *buf)
  210. {
  211. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  212. struct rx_mpdu_start *mpdu_start =
  213. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  214. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  215. uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info);
  216. return encryption_info;
  217. }
  218. /*
  219. * hal_rx_print_pn_6290: Prints the PN of rx packet.
  220. * @buf: rx_tlv_hdr of the received packet
  221. *
  222. * Return: void
  223. */
  224. static void hal_rx_print_pn_6290(uint8_t *buf)
  225. {
  226. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  227. struct rx_mpdu_start *mpdu_start =
  228. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  229. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  230. uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info);
  231. uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info);
  232. uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info);
  233. uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info);
  234. hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ",
  235. pn_127_96, pn_95_64, pn_63_32, pn_31_0);
  236. }
  237. /**
  238. * hal_rx_msdu_end_first_msdu_get_6290: API to get first msdu status
  239. * from rx_msdu_end TLV
  240. *
  241. * @buf: pointer to the start of RX PKT TLV headers
  242. * Return: first_msdu
  243. */
  244. static uint8_t
  245. hal_rx_msdu_end_first_msdu_get_6290(uint8_t *buf)
  246. {
  247. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  248. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  249. uint8_t first_msdu;
  250. first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end);
  251. return first_msdu;
  252. }
  253. /**
  254. * hal_rx_msdu_end_da_is_valid_get_6290: API to check if da is valid
  255. * from rx_msdu_end TLV
  256. *
  257. * @ buf: pointer to the start of RX PKT TLV headers
  258. * Return: da_is_valid
  259. */
  260. static uint8_t hal_rx_msdu_end_da_is_valid_get_6290(uint8_t *buf)
  261. {
  262. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  263. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  264. uint8_t da_is_valid;
  265. da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end);
  266. return da_is_valid;
  267. }
  268. /**
  269. * hal_rx_msdu_end_last_msdu_get_6290: API to get last msdu status
  270. * from rx_msdu_end TLV
  271. *
  272. * @ buf: pointer to the start of RX PKT TLV headers
  273. * Return: last_msdu
  274. */
  275. static uint8_t hal_rx_msdu_end_last_msdu_get_6290(uint8_t *buf)
  276. {
  277. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  278. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  279. uint8_t last_msdu;
  280. last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end);
  281. return last_msdu;
  282. }
  283. /*
  284. * hal_rx_get_mpdu_mac_ad4_valid_6290(): Retrieves if mpdu 4th addr is valid
  285. *
  286. * @nbuf: Network buffer
  287. * Returns: value of mpdu 4th address valid field
  288. */
  289. static bool hal_rx_get_mpdu_mac_ad4_valid_6290(uint8_t *buf)
  290. {
  291. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  292. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  293. bool ad4_valid = 0;
  294. ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info);
  295. return ad4_valid;
  296. }
  297. /**
  298. * hal_rx_mpdu_start_sw_peer_id_get_6290: Retrieve sw peer_id
  299. * @buf: network buffer
  300. *
  301. * Return: sw peer_id:
  302. */
  303. static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6290(uint8_t *buf)
  304. {
  305. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  306. struct rx_mpdu_start *mpdu_start =
  307. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  308. return HAL_RX_MPDU_INFO_SW_PEER_ID_GET(
  309. &mpdu_start->rx_mpdu_info_details);
  310. }
  311. /*
  312. * hal_rx_mpdu_get_to_ds_6290(): API to get the tods info
  313. * from rx_mpdu_start
  314. *
  315. * @buf: pointer to the start of RX PKT TLV header
  316. * Return: uint32_t(to_ds)
  317. */
  318. static uint32_t hal_rx_mpdu_get_to_ds_6290(uint8_t *buf)
  319. {
  320. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  321. struct rx_mpdu_start *mpdu_start =
  322. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  323. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  324. return HAL_RX_MPDU_GET_TODS(mpdu_info);
  325. }
  326. /*
  327. * hal_rx_mpdu_get_fr_ds_6290(): API to get the from ds info
  328. * from rx_mpdu_start
  329. *
  330. * @buf: pointer to the start of RX PKT TLV header
  331. * Return: uint32_t(fr_ds)
  332. */
  333. static uint32_t hal_rx_mpdu_get_fr_ds_6290(uint8_t *buf)
  334. {
  335. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  336. struct rx_mpdu_start *mpdu_start =
  337. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  338. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  339. return HAL_RX_MPDU_GET_FROMDS(mpdu_info);
  340. }
  341. /*
  342. * hal_rx_get_mpdu_frame_control_valid_6290(): Retrieves mpdu frame
  343. * control valid
  344. *
  345. * @nbuf: Network buffer
  346. * Returns: value of frame control valid field
  347. */
  348. static uint8_t hal_rx_get_mpdu_frame_control_valid_6290(uint8_t *buf)
  349. {
  350. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  351. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  352. return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info);
  353. }
  354. /*
  355. * hal_rx_mpdu_get_addr1_6290(): API to check get address1 of the mpdu
  356. *
  357. * @buf: pointer to the start of RX PKT TLV headera
  358. * @mac_addr: pointer to mac address
  359. * Return: success/failure
  360. */
  361. static QDF_STATUS hal_rx_mpdu_get_addr1_6290(uint8_t *buf, uint8_t *mac_addr)
  362. {
  363. struct __attribute__((__packed__)) hal_addr1 {
  364. uint32_t ad1_31_0;
  365. uint16_t ad1_47_32;
  366. };
  367. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  368. struct rx_mpdu_start *mpdu_start =
  369. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  370. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  371. struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr;
  372. uint32_t mac_addr_ad1_valid;
  373. mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info);
  374. if (mac_addr_ad1_valid) {
  375. addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info);
  376. addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info);
  377. return QDF_STATUS_SUCCESS;
  378. }
  379. return QDF_STATUS_E_FAILURE;
  380. }
  381. /*
  382. * hal_rx_mpdu_get_addr2_6290(): API to check get address2 of the mpdu
  383. * in the packet
  384. *
  385. * @buf: pointer to the start of RX PKT TLV header
  386. * @mac_addr: pointer to mac address
  387. * Return: success/failure
  388. */
  389. static QDF_STATUS hal_rx_mpdu_get_addr2_6290(uint8_t *buf,
  390. uint8_t *mac_addr)
  391. {
  392. struct __attribute__((__packed__)) hal_addr2 {
  393. uint16_t ad2_15_0;
  394. uint32_t ad2_47_16;
  395. };
  396. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  397. struct rx_mpdu_start *mpdu_start =
  398. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  399. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  400. struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr;
  401. uint32_t mac_addr_ad2_valid;
  402. mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info);
  403. if (mac_addr_ad2_valid) {
  404. addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info);
  405. addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info);
  406. return QDF_STATUS_SUCCESS;
  407. }
  408. return QDF_STATUS_E_FAILURE;
  409. }
  410. /*
  411. * hal_rx_mpdu_get_addr3_6290(): API to get address3 of the mpdu
  412. * in the packet
  413. *
  414. * @buf: pointer to the start of RX PKT TLV header
  415. * @mac_addr: pointer to mac address
  416. * Return: success/failure
  417. */
  418. static QDF_STATUS hal_rx_mpdu_get_addr3_6290(uint8_t *buf, uint8_t *mac_addr)
  419. {
  420. struct __attribute__((__packed__)) hal_addr3 {
  421. uint32_t ad3_31_0;
  422. uint16_t ad3_47_32;
  423. };
  424. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  425. struct rx_mpdu_start *mpdu_start =
  426. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  427. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  428. struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr;
  429. uint32_t mac_addr_ad3_valid;
  430. mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info);
  431. if (mac_addr_ad3_valid) {
  432. addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info);
  433. addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info);
  434. return QDF_STATUS_SUCCESS;
  435. }
  436. return QDF_STATUS_E_FAILURE;
  437. }
  438. /*
  439. * hal_rx_mpdu_get_addr4_6290(): API to get address4 of the mpdu
  440. * in the packet
  441. *
  442. * @buf: pointer to the start of RX PKT TLV header
  443. * @mac_addr: pointer to mac address
  444. * Return: success/failure
  445. */
  446. static QDF_STATUS hal_rx_mpdu_get_addr4_6290(uint8_t *buf, uint8_t *mac_addr)
  447. {
  448. struct __attribute__((__packed__)) hal_addr4 {
  449. uint32_t ad4_31_0;
  450. uint16_t ad4_47_32;
  451. };
  452. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  453. struct rx_mpdu_start *mpdu_start =
  454. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  455. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  456. struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr;
  457. uint32_t mac_addr_ad4_valid;
  458. mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info);
  459. if (mac_addr_ad4_valid) {
  460. addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info);
  461. addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info);
  462. return QDF_STATUS_SUCCESS;
  463. }
  464. return QDF_STATUS_E_FAILURE;
  465. }
  466. /*
  467. * hal_rx_get_mpdu_sequence_control_valid_6290(): Get mpdu
  468. * sequence control valid
  469. *
  470. * @nbuf: Network buffer
  471. * Returns: value of sequence control valid field
  472. */
  473. static uint8_t hal_rx_get_mpdu_sequence_control_valid_6290(uint8_t *buf)
  474. {
  475. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  476. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  477. return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
  478. }
  479. /**
  480. * hal_rx_is_unicast_6290: check packet is unicast frame or not.
  481. *
  482. * @ buf: pointer to rx pkt TLV.
  483. *
  484. * Return: true on unicast.
  485. */
  486. static bool hal_rx_is_unicast_6290(uint8_t *buf)
  487. {
  488. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  489. struct rx_mpdu_start *mpdu_start =
  490. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  491. uint32_t grp_id;
  492. uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
  493. grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
  494. RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)),
  495. RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK,
  496. RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB));
  497. return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false;
  498. }
  499. /**
  500. * hal_rx_tid_get_6290: get tid based on qos control valid.
  501. * @hal_soc_hdl: hal soc handle
  502. * @ buf: pointer to rx pkt TLV.
  503. *
  504. * Return: tid
  505. */
  506. static uint32_t hal_rx_tid_get_6290(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  507. {
  508. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  509. struct rx_mpdu_start *mpdu_start =
  510. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  511. uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
  512. uint8_t qos_control_valid =
  513. (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
  514. RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)),
  515. RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK,
  516. RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB));
  517. if (qos_control_valid)
  518. return hal_rx_mpdu_start_tid_get_6290(buf);
  519. return HAL_RX_NON_QOS_TID;
  520. }
  521. /**
  522. * hal_rx_hw_desc_get_ppduid_get_6290(): retrieve ppdu id
  523. * @rx_tlv_hdr: start address of rx_pkt_tlvs
  524. * @rxdma_dst_ring_desc: Rx HW descriptor
  525. *
  526. * Return: ppdu id
  527. */
  528. static uint32_t hal_rx_hw_desc_get_ppduid_get_6290(void *rx_tlv_hdr,
  529. void *rxdma_dst_ring_desc)
  530. {
  531. struct rx_mpdu_info *rx_mpdu_info;
  532. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr;
  533. rx_mpdu_info =
  534. &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
  535. return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID);
  536. }
  537. /**
  538. * hal_reo_status_get_header_6290 - Process reo desc info
  539. * @ring_desc: REO status ring descriptor
  540. * @b - tlv type info
  541. * @h1 - Pointer to hal_reo_status_header where info to be stored
  542. *
  543. * Return - none.
  544. *
  545. */
  546. static void hal_reo_status_get_header_6290(hal_ring_desc_t ring_desc, int b,
  547. void *h1)
  548. {
  549. uint32_t *d = (uint32_t *)ring_desc;
  550. uint32_t val1 = 0;
  551. struct hal_reo_status_header *h =
  552. (struct hal_reo_status_header *)h1;
  553. /* Offsets of descriptor fields defined in HW headers start
  554. * from the field after TLV header
  555. */
  556. d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr));
  557. switch (b) {
  558. case HAL_REO_QUEUE_STATS_STATUS_TLV:
  559. val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0,
  560. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  561. break;
  562. case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
  563. val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0,
  564. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  565. break;
  566. case HAL_REO_FLUSH_CACHE_STATUS_TLV:
  567. val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0,
  568. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  569. break;
  570. case HAL_REO_UNBLK_CACHE_STATUS_TLV:
  571. val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0,
  572. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  573. break;
  574. case HAL_REO_TIMOUT_LIST_STATUS_TLV:
  575. val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0,
  576. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  577. break;
  578. case HAL_REO_DESC_THRES_STATUS_TLV:
  579. val1 =
  580. d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0,
  581. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  582. break;
  583. case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
  584. val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0,
  585. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  586. break;
  587. default:
  588. qdf_nofl_err("ERROR: Unknown tlv\n");
  589. break;
  590. }
  591. h->cmd_num =
  592. HAL_GET_FIELD(
  593. UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER,
  594. val1);
  595. h->exec_time =
  596. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
  597. CMD_EXECUTION_TIME, val1);
  598. h->status =
  599. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
  600. REO_CMD_EXECUTION_STATUS, val1);
  601. switch (b) {
  602. case HAL_REO_QUEUE_STATS_STATUS_TLV:
  603. val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1,
  604. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  605. break;
  606. case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
  607. val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1,
  608. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  609. break;
  610. case HAL_REO_FLUSH_CACHE_STATUS_TLV:
  611. val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1,
  612. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  613. break;
  614. case HAL_REO_UNBLK_CACHE_STATUS_TLV:
  615. val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1,
  616. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  617. break;
  618. case HAL_REO_TIMOUT_LIST_STATUS_TLV:
  619. val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1,
  620. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  621. break;
  622. case HAL_REO_DESC_THRES_STATUS_TLV:
  623. val1 =
  624. d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1,
  625. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  626. break;
  627. case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
  628. val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1,
  629. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  630. break;
  631. default:
  632. qdf_nofl_err("ERROR: Unknown tlv\n");
  633. break;
  634. }
  635. h->tstamp =
  636. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1);
  637. }
  638. /**
  639. * hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290():
  640. * Retrieve qos control valid bit from the tlv.
  641. * @buf: pointer to rx pkt TLV.
  642. *
  643. * Return: qos control value.
  644. */
  645. static inline uint32_t
  646. hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290(uint8_t *buf)
  647. {
  648. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  649. struct rx_mpdu_start *mpdu_start =
  650. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  651. return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(
  652. &mpdu_start->rx_mpdu_info_details);
  653. }
  654. /**
  655. * hal_rx_msdu_end_sa_sw_peer_id_get_6290(): API to get the
  656. * sa_sw_peer_id from rx_msdu_end TLV
  657. * @buf: pointer to the start of RX PKT TLV headers
  658. *
  659. * Return: sa_sw_peer_id index
  660. */
  661. static inline uint32_t
  662. hal_rx_msdu_end_sa_sw_peer_id_get_6290(uint8_t *buf)
  663. {
  664. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  665. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  666. return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
  667. }
  668. /**
  669. * hal_tx_desc_set_mesh_en_6290 - Set mesh_enable flag in Tx descriptor
  670. * @desc: Handle to Tx Descriptor
  671. * @en: For raw WiFi frames, this indicates transmission to a mesh STA,
  672. * enabling the interpretation of the 'Mesh Control Present' bit
  673. * (bit 8) of QoS Control (otherwise this bit is ignored),
  674. * For native WiFi frames, this indicates that a 'Mesh Control' field
  675. * is present between the header and the LLC.
  676. *
  677. * Return: void
  678. */
  679. static inline
  680. void hal_tx_desc_set_mesh_en_6290(void *desc, uint8_t en)
  681. {
  682. HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |=
  683. HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en);
  684. }
  685. static
  686. void *hal_rx_msdu0_buffer_addr_lsb_6290(void *link_desc_va)
  687. {
  688. return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
  689. }
  690. static
  691. void *hal_rx_msdu_desc_info_ptr_get_6290(void *msdu0)
  692. {
  693. return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
  694. }
  695. static
  696. void *hal_ent_mpdu_desc_info_6290(void *ent_ring_desc)
  697. {
  698. return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
  699. }
  700. static
  701. void *hal_dst_mpdu_desc_info_6290(void *dst_ring_desc)
  702. {
  703. return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
  704. }
  705. static
  706. uint8_t hal_rx_get_fc_valid_6290(uint8_t *buf)
  707. {
  708. return HAL_RX_GET_FC_VALID(buf);
  709. }
  710. static uint8_t hal_rx_get_to_ds_flag_6290(uint8_t *buf)
  711. {
  712. return HAL_RX_GET_TO_DS_FLAG(buf);
  713. }
  714. static uint8_t hal_rx_get_mac_addr2_valid_6290(uint8_t *buf)
  715. {
  716. return HAL_RX_GET_MAC_ADDR2_VALID(buf);
  717. }
  718. static uint8_t hal_rx_get_filter_category_6290(uint8_t *buf)
  719. {
  720. return HAL_RX_GET_FILTER_CATEGORY(buf);
  721. }
  722. static uint32_t
  723. hal_rx_get_ppdu_id_6290(uint8_t *buf)
  724. {
  725. return HAL_RX_GET_PPDU_ID(buf);
  726. }
  727. /**
  728. * hal_reo_config_6290(): Set reo config parameters
  729. * @soc: hal soc handle
  730. * @reg_val: value to be set
  731. * @reo_params: reo parameters
  732. *
  733. * Return: void
  734. */
  735. static
  736. void hal_reo_config_6290(struct hal_soc *soc,
  737. uint32_t reg_val,
  738. struct hal_reo_params *reo_params)
  739. {
  740. HAL_REO_R0_CONFIG(soc, reg_val, reo_params);
  741. }
  742. /**
  743. * hal_rx_msdu_desc_info_get_ptr_6290() - Get msdu desc info ptr
  744. * @msdu_details_ptr - Pointer to msdu_details_ptr
  745. *
  746. * Return - Pointer to rx_msdu_desc_info structure.
  747. *
  748. */
  749. static void *hal_rx_msdu_desc_info_get_ptr_6290(void *msdu_details_ptr)
  750. {
  751. return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr);
  752. }
  753. /**
  754. * hal_rx_link_desc_msdu0_ptr_6290 - Get pointer to rx_msdu details
  755. * @link_desc - Pointer to link desc
  756. *
  757. * Return - Pointer to rx_msdu_details structure
  758. *
  759. */
  760. static void *hal_rx_link_desc_msdu0_ptr_6290(void *link_desc)
  761. {
  762. return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc);
  763. }
  764. /**
  765. * hal_rx_msdu_flow_idx_get_6290: API to get flow index
  766. * from rx_msdu_end TLV
  767. * @buf: pointer to the start of RX PKT TLV headers
  768. *
  769. * Return: flow index value from MSDU END TLV
  770. */
  771. static inline uint32_t hal_rx_msdu_flow_idx_get_6290(uint8_t *buf)
  772. {
  773. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  774. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  775. return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
  776. }
  777. /**
  778. * hal_rx_msdu_flow_idx_invalid_6290: API to get flow index invalid
  779. * from rx_msdu_end TLV
  780. * @buf: pointer to the start of RX PKT TLV headers
  781. *
  782. * Return: flow index invalid value from MSDU END TLV
  783. */
  784. static bool hal_rx_msdu_flow_idx_invalid_6290(uint8_t *buf)
  785. {
  786. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  787. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  788. return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
  789. }
  790. /**
  791. * hal_rx_msdu_flow_idx_timeout_6290: API to get flow index timeout
  792. * from rx_msdu_end TLV
  793. * @buf: pointer to the start of RX PKT TLV headers
  794. *
  795. * Return: flow index timeout value from MSDU END TLV
  796. */
  797. static bool hal_rx_msdu_flow_idx_timeout_6290(uint8_t *buf)
  798. {
  799. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  800. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  801. return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
  802. }
  803. /**
  804. * hal_rx_msdu_fse_metadata_get_6290: API to get FSE metadata
  805. * from rx_msdu_end TLV
  806. * @buf: pointer to the start of RX PKT TLV headers
  807. *
  808. * Return: fse metadata value from MSDU END TLV
  809. */
  810. static uint32_t hal_rx_msdu_fse_metadata_get_6290(uint8_t *buf)
  811. {
  812. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  813. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  814. return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end);
  815. }
  816. /**
  817. * hal_rx_msdu_cce_metadata_get_6290: API to get CCE metadata
  818. * from rx_msdu_end TLV
  819. * @buf: pointer to the start of RX PKT TLV headers
  820. *
  821. * Return: cce_metadata
  822. */
  823. static uint16_t
  824. hal_rx_msdu_cce_metadata_get_6290(uint8_t *buf)
  825. {
  826. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  827. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  828. return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end);
  829. }
  830. /**
  831. * hal_rx_msdu_get_flow_params_6290: API to get flow index, flow index invalid
  832. * and flow index timeout from rx_msdu_end TLV
  833. * @buf: pointer to the start of RX PKT TLV headers
  834. * @flow_invalid: pointer to return value of flow_idx_valid
  835. * @flow_timeout: pointer to return value of flow_idx_timeout
  836. * @flow_index: pointer to return value of flow_idx
  837. *
  838. * Return: none
  839. */
  840. static inline void
  841. hal_rx_msdu_get_flow_params_6290(uint8_t *buf,
  842. bool *flow_invalid,
  843. bool *flow_timeout,
  844. uint32_t *flow_index)
  845. {
  846. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  847. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  848. *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
  849. *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
  850. *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
  851. }
  852. /**
  853. * hal_rx_tlv_get_tcp_chksum_6290() - API to get tcp checksum
  854. * @buf: rx_tlv_hdr
  855. *
  856. * Return: tcp checksum
  857. */
  858. static uint16_t
  859. hal_rx_tlv_get_tcp_chksum_6290(uint8_t *buf)
  860. {
  861. return HAL_RX_TLV_GET_TCP_CHKSUM(buf);
  862. }
  863. /**
  864. * hal_rx_get_rx_sequence_6290(): Function to retrieve rx sequence number
  865. * @nbuf: Network buffer
  866. *
  867. * Return: rx sequence number
  868. */
  869. static
  870. uint16_t hal_rx_get_rx_sequence_6290(uint8_t *buf)
  871. {
  872. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  873. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  874. return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info);
  875. }
  876. /**
  877. * hal_get_window_address_6290(): Function to get hp/tp address
  878. * @hal_soc: Pointer to hal_soc
  879. * @addr: address offset of register
  880. *
  881. * Return: modified address offset of register
  882. */
  883. static inline qdf_iomem_t hal_get_window_address_6290(struct hal_soc *hal_soc,
  884. qdf_iomem_t addr)
  885. {
  886. return addr;
  887. }
  888. static
  889. void hal_compute_reo_remap_ix2_ix3_6290(uint32_t *ring, uint32_t num_rings,
  890. uint32_t *remap1, uint32_t *remap2)
  891. {
  892. switch (num_rings) {
  893. case 3:
  894. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  895. HAL_REO_REMAP_IX2(ring[1], 17) |
  896. HAL_REO_REMAP_IX2(ring[2], 18) |
  897. HAL_REO_REMAP_IX2(ring[0], 19) |
  898. HAL_REO_REMAP_IX2(ring[1], 20) |
  899. HAL_REO_REMAP_IX2(ring[2], 21) |
  900. HAL_REO_REMAP_IX2(ring[0], 22) |
  901. HAL_REO_REMAP_IX2(ring[1], 23);
  902. *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) |
  903. HAL_REO_REMAP_IX3(ring[0], 25) |
  904. HAL_REO_REMAP_IX3(ring[1], 26) |
  905. HAL_REO_REMAP_IX3(ring[2], 27) |
  906. HAL_REO_REMAP_IX3(ring[0], 28) |
  907. HAL_REO_REMAP_IX3(ring[1], 29) |
  908. HAL_REO_REMAP_IX3(ring[2], 30) |
  909. HAL_REO_REMAP_IX3(ring[0], 31);
  910. break;
  911. case 4:
  912. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  913. HAL_REO_REMAP_IX2(ring[1], 17) |
  914. HAL_REO_REMAP_IX2(ring[2], 18) |
  915. HAL_REO_REMAP_IX2(ring[3], 19) |
  916. HAL_REO_REMAP_IX2(ring[0], 20) |
  917. HAL_REO_REMAP_IX2(ring[1], 21) |
  918. HAL_REO_REMAP_IX2(ring[2], 22) |
  919. HAL_REO_REMAP_IX2(ring[3], 23);
  920. *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
  921. HAL_REO_REMAP_IX3(ring[1], 25) |
  922. HAL_REO_REMAP_IX3(ring[2], 26) |
  923. HAL_REO_REMAP_IX3(ring[3], 27) |
  924. HAL_REO_REMAP_IX3(ring[0], 28) |
  925. HAL_REO_REMAP_IX3(ring[1], 29) |
  926. HAL_REO_REMAP_IX3(ring[2], 30) |
  927. HAL_REO_REMAP_IX3(ring[3], 31);
  928. break;
  929. }
  930. }
  931. #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET
  932. /**
  933. * hal_get_first_wow_wakeup_packet_6290(): Function to get if the buffer
  934. * is the first one that wakes up host from WoW.
  935. *
  936. * @buf: network buffer
  937. *
  938. * Dummy function for QCA6290
  939. *
  940. * Returns: 1 to indicate it is first packet received that wakes up host from
  941. * WoW. Otherwise 0
  942. */
  943. static inline uint8_t hal_get_first_wow_wakeup_packet_6290(uint8_t *buf)
  944. {
  945. return 0;
  946. }
  947. #endif
  948. static void hal_hw_txrx_ops_attach_6290(struct hal_soc *hal_soc)
  949. {
  950. /* init and setup */
  951. hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
  952. hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
  953. hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
  954. hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li;
  955. hal_soc->ops->hal_get_window_address = hal_get_window_address_6290;
  956. /* tx */
  957. hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
  958. hal_tx_desc_set_dscp_tid_table_id_6290;
  959. hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6290;
  960. hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6290;
  961. hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6290;
  962. hal_soc->ops->hal_tx_desc_set_buf_addr =
  963. hal_tx_desc_set_buf_addr_generic_li;
  964. hal_soc->ops->hal_tx_desc_set_search_type =
  965. hal_tx_desc_set_search_type_generic_li;
  966. hal_soc->ops->hal_tx_desc_set_search_index =
  967. hal_tx_desc_set_search_index_generic_li;
  968. hal_soc->ops->hal_tx_desc_set_cache_set_num =
  969. hal_tx_desc_set_cache_set_num_generic_li;
  970. hal_soc->ops->hal_tx_comp_get_status =
  971. hal_tx_comp_get_status_generic_li;
  972. hal_soc->ops->hal_tx_comp_get_release_reason =
  973. hal_tx_comp_get_release_reason_generic_li;
  974. hal_soc->ops->hal_get_wbm_internal_error =
  975. hal_get_wbm_internal_error_generic_li;
  976. hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6290;
  977. hal_soc->ops->hal_tx_init_cmd_credit_ring =
  978. hal_tx_init_cmd_credit_ring_6290;
  979. /* rx */
  980. hal_soc->ops->hal_rx_msdu_start_nss_get =
  981. hal_rx_msdu_start_nss_get_6290;
  982. hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
  983. hal_rx_mon_hw_desc_get_mpdu_status_6290;
  984. hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6290;
  985. hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
  986. hal_rx_proc_phyrx_other_receive_info_tlv_6290;
  987. hal_soc->ops->hal_rx_dump_msdu_start_tlv =
  988. hal_rx_dump_msdu_start_tlv_6290;
  989. hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6290;
  990. hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6290;
  991. hal_soc->ops->hal_rx_mpdu_start_tid_get =
  992. hal_rx_mpdu_start_tid_get_6290;
  993. hal_soc->ops->hal_rx_msdu_start_reception_type_get =
  994. hal_rx_msdu_start_reception_type_get_6290;
  995. hal_soc->ops->hal_rx_msdu_end_da_idx_get =
  996. hal_rx_msdu_end_da_idx_get_6290;
  997. hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
  998. hal_rx_msdu_desc_info_get_ptr_6290;
  999. hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
  1000. hal_rx_link_desc_msdu0_ptr_6290;
  1001. hal_soc->ops->hal_reo_status_get_header =
  1002. hal_reo_status_get_header_6290;
  1003. hal_soc->ops->hal_rx_status_get_tlv_info =
  1004. hal_rx_status_get_tlv_info_generic_li;
  1005. hal_soc->ops->hal_rx_wbm_err_info_get =
  1006. hal_rx_wbm_err_info_get_generic_li;
  1007. hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
  1008. hal_rx_dump_mpdu_start_tlv_generic_li;
  1009. hal_soc->ops->hal_tx_set_pcp_tid_map =
  1010. hal_tx_set_pcp_tid_map_generic_li;
  1011. hal_soc->ops->hal_tx_update_pcp_tid_map =
  1012. hal_tx_update_pcp_tid_generic_li;
  1013. hal_soc->ops->hal_tx_set_tidmap_prty =
  1014. hal_tx_update_tidmap_prty_generic_li;
  1015. hal_soc->ops->hal_rx_get_rx_fragment_number =
  1016. hal_rx_get_rx_fragment_number_6290;
  1017. hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
  1018. hal_rx_msdu_end_da_is_mcbc_get_6290;
  1019. hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
  1020. hal_rx_msdu_end_sa_is_valid_get_6290;
  1021. hal_soc->ops->hal_rx_msdu_end_sa_idx_get =
  1022. hal_rx_msdu_end_sa_idx_get_6290;
  1023. hal_soc->ops->hal_rx_desc_is_first_msdu =
  1024. hal_rx_desc_is_first_msdu_6290;
  1025. hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
  1026. hal_rx_msdu_end_l3_hdr_padding_get_6290;
  1027. hal_soc->ops->hal_rx_encryption_info_valid =
  1028. hal_rx_encryption_info_valid_6290;
  1029. hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6290;
  1030. hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
  1031. hal_rx_msdu_end_first_msdu_get_6290;
  1032. hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
  1033. hal_rx_msdu_end_da_is_valid_get_6290;
  1034. hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
  1035. hal_rx_msdu_end_last_msdu_get_6290;
  1036. hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
  1037. hal_rx_get_mpdu_mac_ad4_valid_6290;
  1038. hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
  1039. hal_rx_mpdu_start_sw_peer_id_get_6290;
  1040. hal_soc->ops->hal_rx_tlv_peer_meta_data_get =
  1041. hal_rx_mpdu_peer_meta_data_get_li;
  1042. hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6290;
  1043. hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6290;
  1044. hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
  1045. hal_rx_get_mpdu_frame_control_valid_6290;
  1046. hal_soc->ops->hal_rx_get_frame_ctrl_field =
  1047. hal_rx_get_frame_ctrl_field_li;
  1048. hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6290;
  1049. hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6290;
  1050. hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6290;
  1051. hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6290;
  1052. hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
  1053. hal_rx_get_mpdu_sequence_control_valid_6290;
  1054. hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6290;
  1055. hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6290;
  1056. hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
  1057. hal_rx_hw_desc_get_ppduid_get_6290;
  1058. hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
  1059. hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290;
  1060. hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
  1061. hal_rx_msdu_end_sa_sw_peer_id_get_6290;
  1062. hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
  1063. hal_rx_msdu0_buffer_addr_lsb_6290;
  1064. hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
  1065. hal_rx_msdu_desc_info_ptr_get_6290;
  1066. hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6290;
  1067. hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6290;
  1068. hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6290;
  1069. hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6290;
  1070. hal_soc->ops->hal_rx_get_mac_addr2_valid =
  1071. hal_rx_get_mac_addr2_valid_6290;
  1072. hal_soc->ops->hal_rx_get_filter_category =
  1073. hal_rx_get_filter_category_6290;
  1074. hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6290;
  1075. hal_soc->ops->hal_reo_config = hal_reo_config_6290;
  1076. hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6290;
  1077. hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
  1078. hal_rx_msdu_flow_idx_invalid_6290;
  1079. hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
  1080. hal_rx_msdu_flow_idx_timeout_6290;
  1081. hal_soc->ops->hal_rx_msdu_fse_metadata_get =
  1082. hal_rx_msdu_fse_metadata_get_6290;
  1083. hal_soc->ops->hal_rx_msdu_cce_match_get =
  1084. hal_rx_msdu_cce_match_get_li;
  1085. hal_soc->ops->hal_rx_msdu_cce_metadata_get =
  1086. hal_rx_msdu_cce_metadata_get_6290;
  1087. hal_soc->ops->hal_rx_msdu_get_flow_params =
  1088. hal_rx_msdu_get_flow_params_6290;
  1089. hal_soc->ops->hal_rx_tlv_get_tcp_chksum =
  1090. hal_rx_tlv_get_tcp_chksum_6290;
  1091. hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6290;
  1092. /* rx - msdu end fast path info fields */
  1093. hal_soc->ops->hal_rx_msdu_packet_metadata_get =
  1094. hal_rx_msdu_packet_metadata_get_generic_li;
  1095. /* rx - TLV struct offsets */
  1096. hal_soc->ops->hal_rx_msdu_end_offset_get =
  1097. hal_rx_msdu_end_offset_get_generic;
  1098. hal_soc->ops->hal_rx_attn_offset_get =
  1099. hal_rx_attn_offset_get_generic;
  1100. hal_soc->ops->hal_rx_msdu_start_offset_get =
  1101. hal_rx_msdu_start_offset_get_generic;
  1102. hal_soc->ops->hal_rx_mpdu_start_offset_get =
  1103. hal_rx_mpdu_start_offset_get_generic;
  1104. hal_soc->ops->hal_rx_mpdu_end_offset_get =
  1105. hal_rx_mpdu_end_offset_get_generic;
  1106. #ifndef NO_RX_PKT_HDR_TLV
  1107. hal_soc->ops->hal_rx_pkt_tlv_offset_get =
  1108. hal_rx_pkt_tlv_offset_get_generic;
  1109. #endif
  1110. hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
  1111. hal_compute_reo_remap_ix2_ix3_6290;
  1112. hal_soc->ops->hal_setup_link_idle_list =
  1113. hal_setup_link_idle_list_generic_li;
  1114. #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET
  1115. hal_soc->ops->hal_get_first_wow_wakeup_packet =
  1116. hal_get_first_wow_wakeup_packet_6290;
  1117. #endif
  1118. hal_soc->ops->hal_compute_reo_remap_ix0 = NULL;
  1119. };
  1120. struct hal_hw_srng_config hw_srng_table_6290[] = {
  1121. /* TODO: max_rings can populated by querying HW capabilities */
  1122. { /* REO_DST */
  1123. .start_ring_id = HAL_SRNG_REO2SW1,
  1124. .max_rings = 4,
  1125. .entry_size = sizeof(struct reo_destination_ring) >> 2,
  1126. .lmac_ring = FALSE,
  1127. .ring_dir = HAL_SRNG_DST_RING,
  1128. .reg_start = {
  1129. HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
  1130. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1131. HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
  1132. SEQ_WCSS_UMAC_REO_REG_OFFSET)
  1133. },
  1134. .reg_size = {
  1135. HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
  1136. HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
  1137. HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
  1138. HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
  1139. },
  1140. .max_size = HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1141. HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
  1142. },
  1143. { /* REO_EXCEPTION */
  1144. /* Designating REO2TCL ring as exception ring. This ring is
  1145. * similar to other REO2SW rings though it is named as REO2TCL.
  1146. * Any of theREO2SW rings can be used as exception ring.
  1147. */
  1148. .start_ring_id = HAL_SRNG_REO2TCL,
  1149. .max_rings = 1,
  1150. .entry_size = sizeof(struct reo_destination_ring) >> 2,
  1151. .lmac_ring = FALSE,
  1152. .ring_dir = HAL_SRNG_DST_RING,
  1153. .reg_start = {
  1154. HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(
  1155. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1156. HWIO_REO_R2_REO2TCL_RING_HP_ADDR(
  1157. SEQ_WCSS_UMAC_REO_REG_OFFSET)
  1158. },
  1159. /* Single ring - provide ring size if multiple rings of this
  1160. * type are supported
  1161. */
  1162. .reg_size = {},
  1163. .max_size = HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >>
  1164. HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT,
  1165. },
  1166. { /* REO_REINJECT */
  1167. .start_ring_id = HAL_SRNG_SW2REO,
  1168. .max_rings = 1,
  1169. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  1170. .lmac_ring = FALSE,
  1171. .ring_dir = HAL_SRNG_SRC_RING,
  1172. .reg_start = {
  1173. HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
  1174. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1175. HWIO_REO_R2_SW2REO_RING_HP_ADDR(
  1176. SEQ_WCSS_UMAC_REO_REG_OFFSET)
  1177. },
  1178. /* Single ring - provide ring size if multiple rings of this
  1179. * type are supported
  1180. */
  1181. .reg_size = {},
  1182. .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
  1183. HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
  1184. },
  1185. { /* REO_CMD */
  1186. .start_ring_id = HAL_SRNG_REO_CMD,
  1187. .max_rings = 1,
  1188. .entry_size = (sizeof(struct tlv_32_hdr) +
  1189. sizeof(struct reo_get_queue_stats)) >> 2,
  1190. .lmac_ring = FALSE,
  1191. .ring_dir = HAL_SRNG_SRC_RING,
  1192. .reg_start = {
  1193. HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
  1194. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1195. HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
  1196. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1197. },
  1198. /* Single ring - provide ring size if multiple rings of this
  1199. * type are supported
  1200. */
  1201. .reg_size = {},
  1202. .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
  1203. HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
  1204. },
  1205. { /* REO_STATUS */
  1206. .start_ring_id = HAL_SRNG_REO_STATUS,
  1207. .max_rings = 1,
  1208. .entry_size = (sizeof(struct tlv_32_hdr) +
  1209. sizeof(struct reo_get_queue_stats_status)) >> 2,
  1210. .lmac_ring = FALSE,
  1211. .ring_dir = HAL_SRNG_DST_RING,
  1212. .reg_start = {
  1213. HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
  1214. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1215. HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
  1216. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1217. },
  1218. /* Single ring - provide ring size if multiple rings of this
  1219. * type are supported
  1220. */
  1221. .reg_size = {},
  1222. .max_size =
  1223. HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
  1224. HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
  1225. },
  1226. { /* TCL_DATA */
  1227. .start_ring_id = HAL_SRNG_SW2TCL1,
  1228. .max_rings = 3,
  1229. .entry_size = (sizeof(struct tlv_32_hdr) +
  1230. sizeof(struct tcl_data_cmd)) >> 2,
  1231. .lmac_ring = FALSE,
  1232. .ring_dir = HAL_SRNG_SRC_RING,
  1233. .reg_start = {
  1234. HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
  1235. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1236. HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
  1237. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1238. },
  1239. .reg_size = {
  1240. HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
  1241. HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
  1242. HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
  1243. HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
  1244. },
  1245. .max_size = HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1246. HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
  1247. },
  1248. { /* TCL_CMD */
  1249. .start_ring_id = HAL_SRNG_SW2TCL_CMD,
  1250. .max_rings = 1,
  1251. .entry_size = (sizeof(struct tlv_32_hdr) +
  1252. sizeof(struct tcl_gse_cmd)) >> 2,
  1253. .lmac_ring = FALSE,
  1254. .ring_dir = HAL_SRNG_SRC_RING,
  1255. .reg_start = {
  1256. HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(
  1257. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1258. HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(
  1259. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1260. },
  1261. /* Single ring - provide ring size if multiple rings of this
  1262. * type are supported
  1263. */
  1264. .reg_size = {},
  1265. .max_size =
  1266. HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
  1267. HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
  1268. },
  1269. { /* TCL_STATUS */
  1270. .start_ring_id = HAL_SRNG_TCL_STATUS,
  1271. .max_rings = 1,
  1272. .entry_size = (sizeof(struct tlv_32_hdr) +
  1273. sizeof(struct tcl_status_ring)) >> 2,
  1274. .lmac_ring = FALSE,
  1275. .ring_dir = HAL_SRNG_DST_RING,
  1276. .reg_start = {
  1277. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
  1278. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1279. HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
  1280. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1281. },
  1282. /* Single ring - provide ring size if multiple rings of this
  1283. * type are supported
  1284. */
  1285. .reg_size = {},
  1286. .max_size =
  1287. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1288. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
  1289. },
  1290. { /* CE_SRC */
  1291. .start_ring_id = HAL_SRNG_CE_0_SRC,
  1292. .max_rings = 12,
  1293. .entry_size = sizeof(struct ce_src_desc) >> 2,
  1294. .lmac_ring = FALSE,
  1295. .ring_dir = HAL_SRNG_SRC_RING,
  1296. .reg_start = {
  1297. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
  1298. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
  1299. HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
  1300. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
  1301. },
  1302. .reg_size = {
  1303. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
  1304. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
  1305. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
  1306. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
  1307. },
  1308. .max_size =
  1309. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
  1310. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
  1311. },
  1312. { /* CE_DST */
  1313. .start_ring_id = HAL_SRNG_CE_0_DST,
  1314. .max_rings = 12,
  1315. .entry_size = 8 >> 2,
  1316. /*TODO: entry_size above should actually be
  1317. * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
  1318. * of struct ce_dst_desc in HW header files
  1319. */
  1320. .lmac_ring = FALSE,
  1321. .ring_dir = HAL_SRNG_SRC_RING,
  1322. .reg_start = {
  1323. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
  1324. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1325. HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
  1326. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1327. },
  1328. .reg_size = {
  1329. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1330. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1331. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1332. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1333. },
  1334. .max_size =
  1335. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
  1336. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
  1337. },
  1338. { /* CE_DST_STATUS */
  1339. .start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
  1340. .max_rings = 12,
  1341. .entry_size = sizeof(struct ce_stat_desc) >> 2,
  1342. .lmac_ring = FALSE,
  1343. .ring_dir = HAL_SRNG_DST_RING,
  1344. .reg_start = {
  1345. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
  1346. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1347. HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
  1348. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1349. },
  1350. /* TODO: check destination status ring registers */
  1351. .reg_size = {
  1352. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1353. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1354. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1355. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1356. },
  1357. .max_size =
  1358. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
  1359. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
  1360. },
  1361. { /* WBM_IDLE_LINK */
  1362. .start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
  1363. .max_rings = 1,
  1364. .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
  1365. .lmac_ring = FALSE,
  1366. .ring_dir = HAL_SRNG_SRC_RING,
  1367. .reg_start = {
  1368. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1369. HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1370. },
  1371. /* Single ring - provide ring size if multiple rings of this
  1372. * type are supported
  1373. */
  1374. .reg_size = {},
  1375. .max_size =
  1376. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
  1377. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
  1378. },
  1379. { /* SW2WBM_RELEASE */
  1380. .start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
  1381. .max_rings = 1,
  1382. .entry_size = sizeof(struct wbm_release_ring) >> 2,
  1383. .lmac_ring = FALSE,
  1384. .ring_dir = HAL_SRNG_SRC_RING,
  1385. .reg_start = {
  1386. HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1387. HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1388. },
  1389. /* Single ring - provide ring size if multiple rings of this
  1390. * type are supported
  1391. */
  1392. .reg_size = {},
  1393. .max_size =
  1394. HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
  1395. HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
  1396. },
  1397. { /* WBM2SW_RELEASE */
  1398. .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
  1399. .max_rings = 4,
  1400. .entry_size = sizeof(struct wbm_release_ring) >> 2,
  1401. .lmac_ring = FALSE,
  1402. .ring_dir = HAL_SRNG_DST_RING,
  1403. .reg_start = {
  1404. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1405. HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1406. },
  1407. .reg_size = {
  1408. HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
  1409. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1410. HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
  1411. HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1412. },
  1413. .max_size =
  1414. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
  1415. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
  1416. },
  1417. { /* RXDMA_BUF */
  1418. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
  1419. #ifdef IPA_OFFLOAD
  1420. .max_rings = 3,
  1421. #else
  1422. .max_rings = 2,
  1423. #endif
  1424. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  1425. .lmac_ring = TRUE,
  1426. .ring_dir = HAL_SRNG_SRC_RING,
  1427. /* reg_start is not set because LMAC rings are not accessed
  1428. * from host
  1429. */
  1430. .reg_start = {},
  1431. .reg_size = {},
  1432. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1433. },
  1434. { /* RXDMA_DST */
  1435. .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
  1436. .max_rings = 1,
  1437. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  1438. .lmac_ring = TRUE,
  1439. .ring_dir = HAL_SRNG_DST_RING,
  1440. /* reg_start is not set because LMAC rings are not accessed
  1441. * from host
  1442. */
  1443. .reg_start = {},
  1444. .reg_size = {},
  1445. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1446. },
  1447. { /* RXDMA_MONITOR_BUF */
  1448. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
  1449. .max_rings = 1,
  1450. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  1451. .lmac_ring = TRUE,
  1452. .ring_dir = HAL_SRNG_SRC_RING,
  1453. /* reg_start is not set because LMAC rings are not accessed
  1454. * from host
  1455. */
  1456. .reg_start = {},
  1457. .reg_size = {},
  1458. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1459. },
  1460. { /* RXDMA_MONITOR_STATUS */
  1461. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
  1462. .max_rings = 1,
  1463. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  1464. .lmac_ring = TRUE,
  1465. .ring_dir = HAL_SRNG_SRC_RING,
  1466. /* reg_start is not set because LMAC rings are not accessed
  1467. * from host
  1468. */
  1469. .reg_start = {},
  1470. .reg_size = {},
  1471. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1472. },
  1473. { /* RXDMA_MONITOR_DST */
  1474. .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1,
  1475. .max_rings = 1,
  1476. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  1477. .lmac_ring = TRUE,
  1478. .ring_dir = HAL_SRNG_DST_RING,
  1479. /* reg_start is not set because LMAC rings are not accessed
  1480. * from host
  1481. */
  1482. .reg_start = {},
  1483. .reg_size = {},
  1484. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1485. },
  1486. { /* RXDMA_MONITOR_DESC */
  1487. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
  1488. .max_rings = 1,
  1489. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  1490. .lmac_ring = TRUE,
  1491. .ring_dir = HAL_SRNG_SRC_RING,
  1492. /* reg_start is not set because LMAC rings are not accessed
  1493. * from host
  1494. */
  1495. .reg_start = {},
  1496. .reg_size = {},
  1497. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1498. },
  1499. { /* DIR_BUF_RX_DMA_SRC */
  1500. .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
  1501. .max_rings = 1,
  1502. .entry_size = 2,
  1503. .lmac_ring = TRUE,
  1504. .ring_dir = HAL_SRNG_SRC_RING,
  1505. /* reg_start is not set because LMAC rings are not accessed
  1506. * from host
  1507. */
  1508. .reg_start = {},
  1509. .reg_size = {},
  1510. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1511. },
  1512. #ifdef WLAN_FEATURE_CIF_CFR
  1513. { /* WIFI_POS_SRC */
  1514. .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
  1515. .max_rings = 1,
  1516. .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2,
  1517. .lmac_ring = TRUE,
  1518. .ring_dir = HAL_SRNG_SRC_RING,
  1519. /* reg_start is not set because LMAC rings are not accessed
  1520. * from host
  1521. */
  1522. .reg_start = {},
  1523. .reg_size = {},
  1524. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1525. },
  1526. #endif
  1527. { /* REO2PPE */ 0},
  1528. { /* PPE2TCL */ 0},
  1529. { /* PPE_RELEASE */ 0},
  1530. { /* TX_MONITOR_BUF */ 0},
  1531. { /* TX_MONITOR_DST */ 0},
  1532. { /* SW2RXDMA_NEW */ 0},
  1533. };
  1534. /**
  1535. * hal_qca6290_attach() - Attach 6290 target specific hal_soc ops,
  1536. * offset and srng table
  1537. */
  1538. void hal_qca6290_attach(struct hal_soc *hal_soc)
  1539. {
  1540. hal_soc->hw_srng_table = hw_srng_table_6290;
  1541. hal_srng_hw_reg_offset_init_generic(hal_soc);
  1542. hal_hw_txrx_default_ops_attach_li(hal_soc);
  1543. hal_hw_txrx_ops_attach_6290(hal_soc);
  1544. }