hal_5332_tx.h 7.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287
  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
  16. */
  17. #ifndef _HAL_5332_TX_H_
  18. #define _HAL_5332_TX_H_
  19. #include "tcl_data_cmd.h"
  20. #include "phyrx_rssi_legacy.h"
  21. #include "hal_internal.h"
  22. #include "qdf_trace.h"
  23. #include "hal_rx.h"
  24. #include "hal_tx.h"
  25. #include "hal_api_mon.h"
  26. #include <hal_be_tx.h>
  27. #define DSCP_TID_TABLE_SIZE 24
  28. #define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4)
  29. #define HAL_TX_NUM_DSCP_REGISTER_SIZE 32
  30. /**
  31. * hal_tx_set_dscp_tid_map_5332() - Configure default DSCP to TID map table
  32. * @soc: HAL SoC context
  33. * @map: DSCP-TID mapping table
  34. * @id: mapping table ID - 0-31
  35. *
  36. * DSCP are mapped to 8 TID values using TID values programmed
  37. * in any of the 32 DSCP_TID_MAPS (id = 0-31).
  38. *
  39. * Return: none
  40. */
  41. static void hal_tx_set_dscp_tid_map_5332(struct hal_soc *hal_soc, uint8_t *map,
  42. uint8_t id)
  43. {
  44. int i;
  45. uint32_t addr, cmn_reg_addr;
  46. uint32_t value = 0, regval;
  47. uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0;
  48. struct hal_soc *soc = (struct hal_soc *)hal_soc;
  49. if (id >= HAL_MAX_HW_DSCP_TID_V2_MAPS_5332)
  50. return;
  51. cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
  52. MAC_TCL_REG_REG_BASE);
  53. addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
  54. MAC_TCL_REG_REG_BASE,
  55. id * NUM_WORDS_PER_DSCP_TID_TABLE);
  56. /* Enable read/write access */
  57. regval = HAL_REG_READ(soc, cmn_reg_addr);
  58. regval |=
  59. (1 <<
  60. HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
  61. HAL_REG_WRITE(soc, cmn_reg_addr, regval);
  62. /* Write 8 (24 bits) DSCP-TID mappings in each interation */
  63. for (i = 0; i < 64; i += 8) {
  64. value = (map[i] |
  65. (map[i + 1] << 0x3) |
  66. (map[i + 2] << 0x6) |
  67. (map[i + 3] << 0x9) |
  68. (map[i + 4] << 0xc) |
  69. (map[i + 5] << 0xf) |
  70. (map[i + 6] << 0x12) |
  71. (map[i + 7] << 0x15));
  72. qdf_mem_copy(&val[cnt], (void *)&value, 3);
  73. cnt += 3;
  74. }
  75. for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) {
  76. regval = *(uint32_t *)(val + i);
  77. HAL_REG_WRITE(soc, addr,
  78. (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
  79. addr += 4;
  80. }
  81. /* Diasble read/write access */
  82. regval = HAL_REG_READ(soc, cmn_reg_addr);
  83. regval &=
  84. ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
  85. HAL_REG_WRITE(soc, cmn_reg_addr, regval);
  86. }
  87. /**
  88. * hal_tx_update_dscp_tid_5332() - Update the dscp tid map table as updated
  89. * by the user
  90. * @soc: HAL SoC context
  91. * @map: DSCP-TID mapping table
  92. * @id : MAP ID
  93. * @dscp: DSCP_TID map index
  94. *
  95. * Return: void
  96. */
  97. static void hal_tx_update_dscp_tid_5332(struct hal_soc *soc, uint8_t tid,
  98. uint8_t id, uint8_t dscp)
  99. {
  100. uint32_t addr, addr1, cmn_reg_addr;
  101. uint32_t start_value = 0, end_value = 0;
  102. uint32_t regval;
  103. uint8_t end_bits = 0;
  104. uint8_t start_bits = 0;
  105. uint32_t start_index, end_index;
  106. cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
  107. MAC_TCL_REG_REG_BASE);
  108. addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
  109. MAC_TCL_REG_REG_BASE,
  110. id * NUM_WORDS_PER_DSCP_TID_TABLE);
  111. start_index = dscp * HAL_TX_BITS_PER_TID;
  112. end_index = (start_index + (HAL_TX_BITS_PER_TID - 1))
  113. % HAL_TX_NUM_DSCP_REGISTER_SIZE;
  114. start_index = start_index % HAL_TX_NUM_DSCP_REGISTER_SIZE;
  115. addr += (4 * ((dscp * HAL_TX_BITS_PER_TID) /
  116. HAL_TX_NUM_DSCP_REGISTER_SIZE));
  117. if (end_index < start_index) {
  118. end_bits = end_index + 1;
  119. start_bits = HAL_TX_BITS_PER_TID - end_bits;
  120. start_value = tid << start_index;
  121. end_value = tid >> start_bits;
  122. addr1 = addr + 4;
  123. } else {
  124. start_bits = HAL_TX_BITS_PER_TID - end_bits;
  125. start_value = tid << start_index;
  126. addr1 = 0;
  127. }
  128. /* Enable read/write access */
  129. regval = HAL_REG_READ(soc, cmn_reg_addr);
  130. regval |=
  131. (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
  132. HAL_REG_WRITE(soc, cmn_reg_addr, regval);
  133. regval = HAL_REG_READ(soc, addr);
  134. if (end_index < start_index)
  135. regval &= (~0) >> start_bits;
  136. else
  137. regval &= ~(7 << start_index);
  138. regval |= start_value;
  139. HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
  140. if (addr1) {
  141. regval = HAL_REG_READ(soc, addr1);
  142. regval &= (~0) << end_bits;
  143. regval |= end_value;
  144. HAL_REG_WRITE(soc, addr1, (regval &
  145. HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
  146. }
  147. /* Diasble read/write access */
  148. regval = HAL_REG_READ(soc, cmn_reg_addr);
  149. regval &=
  150. ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
  151. HAL_REG_WRITE(soc, cmn_reg_addr, regval);
  152. }
  153. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  154. #define RBM_MAPPING_BMSK HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK
  155. #define RBM_MAPPING_SHFT HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT
  156. #define RBM_TCL_CMD_CREDIT_OFFSET \
  157. (HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT >> 2)
  158. /**
  159. * hal_tx_config_rbm_mapping_be() - Update return buffer manager ring id
  160. * @hal_soc: HAL SoC context
  161. * @hal_ring_hdl: Source ring pointer
  162. * @rbm_id: return buffer manager ring id
  163. *
  164. * Return: void
  165. */
  166. static inline void
  167. hal_tx_config_rbm_mapping_be_5332(hal_soc_handle_t hal_soc_hdl,
  168. hal_ring_handle_t hal_ring_hdl,
  169. uint8_t rbm_id)
  170. {
  171. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  172. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  173. uint32_t reg_addr = 0;
  174. uint32_t reg_val = 0;
  175. uint32_t val = 0;
  176. uint8_t ring_num;
  177. enum hal_ring_type ring_type;
  178. ring_type = srng->ring_type;
  179. ring_num = hal_soc->hw_srng_table[ring_type].start_ring_id;
  180. ring_num = srng->ring_id - ring_num;
  181. reg_addr = HWIO_TCL_R0_RBM_MAPPING0_ADDR(MAC_TCL_REG_REG_BASE);
  182. if (ring_type == TCL_CMD_CREDIT)
  183. ring_num = ring_num + RBM_TCL_CMD_CREDIT_OFFSET;
  184. /* get current value stored in register address */
  185. val = HAL_REG_READ(hal_soc, reg_addr);
  186. /* mask out other stored value */
  187. val &= (~(RBM_MAPPING_BMSK << (RBM_MAPPING_SHFT * ring_num)));
  188. reg_val = val | ((RBM_MAPPING_BMSK & rbm_id) <<
  189. (RBM_MAPPING_SHFT * ring_num));
  190. /* write rbm mapped value to register address */
  191. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  192. }
  193. #else
  194. static inline void
  195. hal_tx_config_rbm_mapping_be_5332(hal_soc_handle_t hal_soc_hdl,
  196. hal_ring_handle_t hal_ring_hdl,
  197. uint8_t rbm_id)
  198. {
  199. }
  200. #endif
  201. /**
  202. * hal_tx_init_cmd_credit_ring_5332() - Initialize command/credit SRNG
  203. * @hal_soc_hdl: Handle to HAL SoC structure
  204. * @hal_srng: Handle to HAL SRNG structure
  205. *
  206. * Return: none
  207. */
  208. static inline void
  209. hal_tx_init_cmd_credit_ring_5332(hal_soc_handle_t hal_soc_hdl,
  210. hal_ring_handle_t hal_ring_hdl)
  211. {
  212. }
  213. /* TX MONITOR */
  214. #ifdef QCA_MONITOR_2_0_SUPPORT
  215. #if defined(TX_MONITOR_WORD_MASK)
  216. typedef struct tx_fes_setup_compact_5332 hal_tx_fes_setup_t;
  217. struct tx_fes_setup_compact_5332 {
  218. /* DWORD - 0 */
  219. uint32_t schedule_id;
  220. /* DWORD - 1 */
  221. uint32_t reserved_1a : 7, // [0: 6]
  222. transmit_start_reason : 3, // [7: 9]
  223. reserved_1b : 13, // [10: 22]
  224. number_of_users : 6, // [28: 23]
  225. MU_type : 1, // [29]
  226. reserved_1c : 2; // [30]
  227. /* DWORD - 2 */
  228. uint32_t reserved_2a : 4, // [0: 3]
  229. ndp_frame : 2, // [4: 5]
  230. txbf : 1, // [6]
  231. reserved_2b : 3, // [7: 9]
  232. static_bandwidth : 3, // [12: 10]
  233. reserved_2c : 1, // [13]
  234. transmission_contains_MU_RTS : 1, // [14]
  235. reserved_2d : 17; // [15: 31]
  236. /* DWORD - 3 */
  237. uint32_t reserved_3a : 15, // [0: 14]
  238. mu_ndp : 1, // [15]
  239. reserved_3b : 11, // [16: 26]
  240. ndpa : 1, // [27]
  241. reserved_3c : 4; // [28: 31]
  242. };
  243. #endif
  244. #endif /* QCA_MONITOR_2_0_SUPPORT */
  245. #endif /* _HAL_5332_TX_H_ */