hal_5332.c 85 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427
  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
  16. */
  17. #include "qdf_types.h"
  18. #include "qdf_util.h"
  19. #include "qdf_mem.h"
  20. #include "qdf_nbuf.h"
  21. #include "qdf_module.h"
  22. #include "target_type.h"
  23. #include "wcss_version.h"
  24. #include "hal_be_hw_headers.h"
  25. #include "hal_internal.h"
  26. #include "hal_api.h"
  27. #include "hal_flow.h"
  28. #include "rx_flow_search_entry.h"
  29. #include "hal_rx_flow_info.h"
  30. #include "hal_be_api.h"
  31. #include "tcl_entrance_from_ppe_ring.h"
  32. #include "sw_monitor_ring.h"
  33. #include "wcss_seq_hwioreg_umac.h"
  34. #include "wfss_ce_reg_seq_hwioreg.h"
  35. #include <uniform_reo_status_header.h>
  36. #include <wbm_release_ring_tx.h>
  37. #include <phyrx_location.h>
  38. #ifdef QCA_MONITOR_2_0_SUPPORT
  39. #include <mon_ingress_ring.h>
  40. #include <mon_destination_ring.h>
  41. #endif
  42. #include "rx_reo_queue_1k.h"
  43. #include <hal_be_rx.h>
  44. #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
  45. RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET
  46. #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
  47. RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
  48. #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
  49. RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
  50. #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
  51. RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
  52. #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
  53. REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
  54. #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \
  55. STATUS_HEADER_REO_STATUS_NUMBER
  56. #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
  57. STATUS_HEADER_TIMESTAMP
  58. #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
  59. RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
  60. #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
  61. RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
  62. #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
  63. TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET
  64. #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
  65. TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET
  66. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
  67. TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET
  68. #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
  69. BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB
  70. #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
  71. BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK
  72. #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
  73. BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB
  74. #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
  75. BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK
  76. #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
  77. BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB
  78. #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
  79. BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK
  80. #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
  81. BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB
  82. #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
  83. BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK
  84. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
  85. TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB
  86. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
  87. TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK
  88. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
  89. WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK
  90. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
  91. WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET
  92. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
  93. WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB
  94. #include "hal_be_api_mon.h"
  95. #define CMEM_REG_BASE 0x00100000
  96. /* For Berryllium sw2rxdma ring size increased to 20 bits */
  97. #define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF
  98. #ifdef CONFIG_WORD_BASED_TLV
  99. #ifndef BIG_ENDIAN_HOST
  100. struct rx_msdu_end_compact_qca5332 {
  101. uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0]
  102. sw_frame_group_id : 7, // [8:2]
  103. reserved_0 : 7, // [15:9]
  104. phy_ppdu_id : 16; // [31:16]
  105. uint32_t ip_hdr_chksum : 16, // [15:0]
  106. reported_mpdu_length : 14, // [29:16]
  107. reserved_1a : 2; // [31:30]
  108. uint32_t key_id_octet : 8, // [7:0]
  109. cce_super_rule : 6, // [13:8]
  110. cce_classify_not_done_truncate : 1, // [14:14]
  111. cce_classify_not_done_cce_dis : 1, // [15:15]
  112. cumulative_l3_checksum : 16; // [31:16]
  113. uint32_t rule_indication_31_0 : 32; // [31:0]
  114. uint32_t rule_indication_63_32 : 32; // [31:0]
  115. uint32_t da_offset : 6, // [5:0]
  116. sa_offset : 6, // [11:6]
  117. da_offset_valid : 1, // [12:12]
  118. sa_offset_valid : 1, // [13:13]
  119. reserved_5a : 2, // [15:14]
  120. l3_type : 16; // [31:16]
  121. uint32_t ipv6_options_crc : 32; // [31:0]
  122. uint32_t tcp_seq_number : 32; // [31:0]
  123. uint32_t tcp_ack_number : 32; // [31:0]
  124. uint32_t tcp_flag : 9, // [8:0]
  125. lro_eligible : 1, // [9:9]
  126. reserved_9a : 6, // [15:10]
  127. window_size : 16; // [31:16]
  128. uint32_t tcp_udp_chksum : 16, // [15:0]
  129. sa_idx_timeout : 1, // [16:16]
  130. da_idx_timeout : 1, // [17:17]
  131. msdu_limit_error : 1, // [18:18]
  132. flow_idx_timeout : 1, // [19:19]
  133. flow_idx_invalid : 1, // [20:20]
  134. wifi_parser_error : 1, // [21:21]
  135. amsdu_parser_error : 1, // [22:22]
  136. sa_is_valid : 1, // [23:23]
  137. da_is_valid : 1, // [24:24]
  138. da_is_mcbc : 1, // [25:25]
  139. l3_header_padding : 2, // [27:26]
  140. first_msdu : 1, // [28:28]
  141. last_msdu : 1, // [29:29]
  142. tcp_udp_chksum_fail_copy : 1, // [30:30]
  143. ip_chksum_fail_copy : 1; // [31:31]
  144. uint32_t sa_idx : 16, // [15:0]
  145. da_idx_or_sw_peer_id : 16; // [31:16]
  146. uint32_t msdu_drop : 1, // [0:0]
  147. reo_destination_indication : 5, // [5:1]
  148. flow_idx : 20, // [25:6]
  149. use_ppe : 1, // [26:26]
  150. reserved_12a : 5; // [31:27]
  151. uint32_t fse_metadata : 32; // [31:0]
  152. uint32_t cce_metadata : 16, // [15:0]
  153. sa_sw_peer_id : 16; // [31:16]
  154. uint32_t aggregation_count : 8, // [7:0]
  155. flow_aggregation_continuation : 1, // [8:8]
  156. fisa_timeout : 1, // [9:9]
  157. reserved_15a : 22; // [31:10]
  158. uint32_t cumulative_l4_checksum : 16, // [15:0]
  159. cumulative_ip_length : 16; // [31:16]
  160. uint32_t reserved_17a : 6, // [5:0]
  161. service_code : 9, // [14:6]
  162. priority_valid : 1, // [15:15]
  163. intra_bss : 1, // [16:16]
  164. dest_chip_id : 2, // [18:17]
  165. multicast_echo : 1, // [19:19]
  166. wds_learning_event : 1, // [20:20]
  167. wds_roaming_event : 1, // [21:21]
  168. wds_keep_alive_event : 1, // [22:22]
  169. reserved_17b : 9; // [31:23]
  170. uint32_t msdu_length : 14, // [13:0]
  171. stbc : 1, // [14:14]
  172. ipsec_esp : 1, // [15:15]
  173. l3_offset : 7, // [22:16]
  174. ipsec_ah : 1, // [23:23]
  175. l4_offset : 8; // [31:24]
  176. uint32_t msdu_number : 8, // [7:0]
  177. decap_format : 2, // [9:8]
  178. ipv4_proto : 1, // [10:10]
  179. ipv6_proto : 1, // [11:11]
  180. tcp_proto : 1, // [12:12]
  181. udp_proto : 1, // [13:13]
  182. ip_frag : 1, // [14:14]
  183. tcp_only_ack : 1, // [15:15]
  184. da_is_bcast_mcast : 1, // [16:16]
  185. toeplitz_hash_sel : 2, // [18:17]
  186. ip_fixed_header_valid : 1, // [19:19]
  187. ip_extn_header_valid : 1, // [20:20]
  188. tcp_udp_header_valid : 1, // [21:21]
  189. mesh_control_present : 1, // [22:22]
  190. ldpc : 1, // [23:23]
  191. ip4_protocol_ip6_next_header : 8; // [31:24]
  192. uint32_t toeplitz_hash_2_or_4 : 32; // [31:0]
  193. uint32_t flow_id_toeplitz : 32; // [31:0]
  194. uint32_t user_rssi : 8, // [7:0]
  195. pkt_type : 4, // [11:8]
  196. sgi : 2, // [13:12]
  197. rate_mcs : 4, // [17:14]
  198. receive_bandwidth : 3, // [20:18]
  199. reception_type : 3, // [23:21]
  200. mimo_ss_bitmap : 8; // [31:24]
  201. uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0]
  202. uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0]
  203. uint32_t sw_phy_meta_data : 32; // [31:0]
  204. uint32_t vlan_ctag_ci : 16, // [15:0]
  205. vlan_stag_ci : 16; // [31:16]
  206. uint32_t reserved_27a : 32; // [31:0]
  207. uint32_t reserved_28a : 32; // [31:0]
  208. uint32_t reserved_29a : 32; // [31:0]
  209. uint32_t first_mpdu : 1, // [0:0]
  210. reserved_30a : 1, // [1:1]
  211. mcast_bcast : 1, // [2:2]
  212. ast_index_not_found : 1, // [3:3]
  213. ast_index_timeout : 1, // [4:4]
  214. power_mgmt : 1, // [5:5]
  215. non_qos : 1, // [6:6]
  216. null_data : 1, // [7:7]
  217. mgmt_type : 1, // [8:8]
  218. ctrl_type : 1, // [9:9]
  219. more_data : 1, // [10:10]
  220. eosp : 1, // [11:11]
  221. a_msdu_error : 1, // [12:12]
  222. fragment_flag : 1, // [13:13]
  223. order : 1, // [14:14]
  224. cce_match : 1, // [15:15]
  225. overflow_err : 1, // [16:16]
  226. msdu_length_err : 1, // [17:17]
  227. tcp_udp_chksum_fail : 1, // [18:18]
  228. ip_chksum_fail : 1, // [19:19]
  229. sa_idx_invalid : 1, // [20:20]
  230. da_idx_invalid : 1, // [21:21]
  231. reserved_30b : 1, // [22:22]
  232. rx_in_tx_decrypt_byp : 1, // [23:23]
  233. encrypt_required : 1, // [24:24]
  234. directed : 1, // [25:25]
  235. buffer_fragment : 1, // [26:26]
  236. mpdu_length_err : 1, // [27:27]
  237. tkip_mic_err : 1, // [28:28]
  238. decrypt_err : 1, // [29:29]
  239. unencrypted_frame_err : 1, // [30:30]
  240. fcs_err : 1; // [31:31]
  241. uint32_t reserved_31a : 10, // [9:0]
  242. decrypt_status_code : 3, // [12:10]
  243. rx_bitmap_not_updated : 1, // [13:13]
  244. reserved_31b : 17, // [30:14]
  245. msdu_done : 1; // [31:31]
  246. };
  247. struct rx_mpdu_start_compact_qca5332 {
  248. struct rxpt_classify_info rxpt_classify_info_details;
  249. uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0]
  250. uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0]
  251. receive_queue_number : 16, // [23:8]
  252. pre_delim_err_warning : 1, // [24:24]
  253. first_delim_err : 1, // [25:25]
  254. reserved_2a : 6; // [31:26]
  255. uint32_t pn_31_0 : 32; // [31:0]
  256. uint32_t pn_63_32 : 32; // [31:0]
  257. uint32_t pn_95_64 : 32; // [31:0]
  258. uint32_t pn_127_96 : 32; // [31:0]
  259. uint32_t epd_en : 1, // [0:0]
  260. all_frames_shall_be_encrypted : 1, // [1:1]
  261. encrypt_type : 4, // [5:2]
  262. wep_key_width_for_variable_key : 2, // [7:6]
  263. mesh_sta : 2, // [9:8]
  264. bssid_hit : 1, // [10:10]
  265. bssid_number : 4, // [14:11]
  266. tid : 4, // [18:15]
  267. reserved_7a : 13; // [31:19]
  268. uint32_t peer_meta_data : 32; // [31:0]
  269. uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0]
  270. sw_frame_group_id : 7, // [8:2]
  271. ndp_frame : 1, // [9:9]
  272. phy_err : 1, // [10:10]
  273. phy_err_during_mpdu_header : 1, // [11:11]
  274. protocol_version_err : 1, // [12:12]
  275. ast_based_lookup_valid : 1, // [13:13]
  276. ranging : 1, // [14:14]
  277. reserved_9a : 1, // [15:15]
  278. phy_ppdu_id : 16; // [31:16]
  279. uint32_t ast_index : 16, // [15:0]
  280. sw_peer_id : 16; // [31:16]
  281. uint32_t mpdu_frame_control_valid : 1, // [0:0]
  282. mpdu_duration_valid : 1, // [1:1]
  283. mac_addr_ad1_valid : 1, // [2:2]
  284. mac_addr_ad2_valid : 1, // [3:3]
  285. mac_addr_ad3_valid : 1, // [4:4]
  286. mac_addr_ad4_valid : 1, // [5:5]
  287. mpdu_sequence_control_valid : 1, // [6:6]
  288. mpdu_qos_control_valid : 1, // [7:7]
  289. mpdu_ht_control_valid : 1, // [8:8]
  290. frame_encryption_info_valid : 1, // [9:9]
  291. mpdu_fragment_number : 4, // [13:10]
  292. more_fragment_flag : 1, // [14:14]
  293. reserved_11a : 1, // [15:15]
  294. fr_ds : 1, // [16:16]
  295. to_ds : 1, // [17:17]
  296. encrypted : 1, // [18:18]
  297. mpdu_retry : 1, // [19:19]
  298. mpdu_sequence_number : 12; // [31:20]
  299. uint32_t key_id_octet : 8, // [7:0]
  300. new_peer_entry : 1, // [8:8]
  301. decrypt_needed : 1, // [9:9]
  302. decap_type : 2, // [11:10]
  303. rx_insert_vlan_c_tag_padding : 1, // [12:12]
  304. rx_insert_vlan_s_tag_padding : 1, // [13:13]
  305. strip_vlan_c_tag_decap : 1, // [14:14]
  306. strip_vlan_s_tag_decap : 1, // [15:15]
  307. pre_delim_count : 12, // [27:16]
  308. ampdu_flag : 1, // [28:28]
  309. bar_frame : 1, // [29:29]
  310. raw_mpdu : 1, // [30:30]
  311. reserved_12 : 1; // [31:31]
  312. uint32_t mpdu_length : 14, // [13:0]
  313. first_mpdu : 1, // [14:14]
  314. mcast_bcast : 1, // [15:15]
  315. ast_index_not_found : 1, // [16:16]
  316. ast_index_timeout : 1, // [17:17]
  317. power_mgmt : 1, // [18:18]
  318. non_qos : 1, // [19:19]
  319. null_data : 1, // [20:20]
  320. mgmt_type : 1, // [21:21]
  321. ctrl_type : 1, // [22:22]
  322. more_data : 1, // [23:23]
  323. eosp : 1, // [24:24]
  324. fragment_flag : 1, // [25:25]
  325. order : 1, // [26:26]
  326. u_apsd_trigger : 1, // [27:27]
  327. encrypt_required : 1, // [28:28]
  328. directed : 1, // [29:29]
  329. amsdu_present : 1, // [30:30]
  330. reserved_13 : 1; // [31:31]
  331. uint32_t mpdu_frame_control_field : 16, // [15:0]
  332. mpdu_duration_field : 16; // [31:16]
  333. uint32_t mac_addr_ad1_31_0 : 32; // [31:0]
  334. uint32_t mac_addr_ad1_47_32 : 16, // [15:0]
  335. mac_addr_ad2_15_0 : 16; // [31:16]
  336. uint32_t mac_addr_ad2_47_16 : 32; // [31:0]
  337. uint32_t mac_addr_ad3_31_0 : 32; // [31:0]
  338. uint32_t mac_addr_ad3_47_32 : 16, // [15:0]
  339. mpdu_sequence_control_field : 16; // [31:16]
  340. uint32_t mac_addr_ad4_31_0 : 32; // [31:0]
  341. uint32_t mac_addr_ad4_47_32 : 16, // [15:0]
  342. mpdu_qos_control_field : 16; // [31:16]
  343. uint32_t mpdu_ht_control_field : 32; // [31:0]
  344. uint32_t vdev_id : 8, // [7:0]
  345. service_code : 9, // [16:8]
  346. priority_valid : 1, // [17:17]
  347. src_info : 12, // [29:18]
  348. reserved_23a : 1, // [30:30]
  349. multi_link_addr_ad1_ad2_valid : 1; // [31:31]
  350. uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0]
  351. uint32_t multi_link_addr_ad1_47_32 : 16, // [15:0]
  352. multi_link_addr_ad2_15_0 : 16; // [31:16]
  353. uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0]
  354. uint32_t reserved_27a : 32; // [31:0]
  355. uint32_t reserved_28a : 32; // [31:0]
  356. uint32_t reserved_29a : 32; // [31:0]
  357. };
  358. #else
  359. struct rx_msdu_end_compact_qca5332 {
  360. uint32_t phy_ppdu_id : 16, // [31:16]
  361. reserved_0 : 7, // [15:9]
  362. sw_frame_group_id : 7, // [8:2]
  363. rxpcu_mpdu_filter_in_category : 2; // [1:0]
  364. uint32_t reserved_1a : 2, // [31:30]
  365. reported_mpdu_length : 14, // [29:16]
  366. ip_hdr_chksum : 16; // [15:0]
  367. uint32_t cumulative_l3_checksum : 16, // [31:16]
  368. cce_classify_not_done_cce_dis : 1, // [15:15]
  369. cce_classify_not_done_truncate : 1, // [14:14]
  370. cce_super_rule : 6, // [13:8]
  371. key_id_octet : 8; // [7:0]
  372. uint32_t rule_indication_31_0 : 32; // [31:0]
  373. uint32_t rule_indication_63_32 : 32; // [31:0]
  374. uint32_t l3_type : 16, // [31:16]
  375. reserved_5a : 2, // [15:14]
  376. sa_offset_valid : 1, // [13:13]
  377. da_offset_valid : 1, // [12:12]
  378. sa_offset : 6, // [11:6]
  379. da_offset : 6; // [5:0]
  380. uint32_t ipv6_options_crc : 32; // [31:0]
  381. uint32_t tcp_seq_number : 32; // [31:0]
  382. uint32_t tcp_ack_number : 32; // [31:0]
  383. uint32_t window_size : 16, // [31:16]
  384. reserved_9a : 6, // [15:10]
  385. lro_eligible : 1, // [9:9]
  386. tcp_flag : 9; // [8:0]
  387. uint32_t ip_chksum_fail_copy : 1, // [31:31]
  388. tcp_udp_chksum_fail_copy : 1, // [30:30]
  389. last_msdu : 1, // [29:29]
  390. first_msdu : 1, // [28:28]
  391. l3_header_padding : 2, // [27:26]
  392. da_is_mcbc : 1, // [25:25]
  393. da_is_valid : 1, // [24:24]
  394. sa_is_valid : 1, // [23:23]
  395. amsdu_parser_error : 1, // [22:22]
  396. wifi_parser_error : 1, // [21:21]
  397. flow_idx_invalid : 1, // [20:20]
  398. flow_idx_timeout : 1, // [19:19]
  399. msdu_limit_error : 1, // [18:18]
  400. da_idx_timeout : 1, // [17:17]
  401. sa_idx_timeout : 1, // [16:16]
  402. tcp_udp_chksum : 16; // [15:0]
  403. uint32_t da_idx_or_sw_peer_id : 16, // [31:16]
  404. sa_idx : 16; // [15:0]
  405. uint32_t reserved_12a : 5, // [31:27]
  406. use_ppe : 1, // [26:26]
  407. flow_idx : 20, // [25:6]
  408. reo_destination_indication : 5, // [5:1]
  409. msdu_drop : 1; // [0:0]
  410. uint32_t fse_metadata : 32; // [31:0]
  411. uint32_t sa_sw_peer_id : 16, // [31:16]
  412. cce_metadata : 16; // [15:0]
  413. uint32_t reserved_15a : 22, // [31:10]
  414. fisa_timeout : 1, // [9:9]
  415. flow_aggregation_continuation : 1, // [8:8]
  416. aggregation_count : 8; // [7:0]
  417. uint32_t cumulative_ip_length : 16, // [31:16]
  418. cumulative_l4_checksum : 16; // [15:0]
  419. uint32_t reserved_17b : 9, // [31:23]
  420. wds_keep_alive_event : 1, // [22:22]
  421. wds_roaming_event : 1, // [21:21]
  422. wds_learning_event : 1, // [20:20]
  423. multicast_echo : 1, // [19:19]
  424. dest_chip_id : 2, // [18:17]
  425. intra_bss : 1, // [16:16]
  426. priority_valid : 1, // [15:15]
  427. service_code : 9, // [14:6]
  428. reserved_17a : 6; // [5:0]
  429. uint32_t l4_offset : 8, // [31:24]
  430. ipsec_ah : 1, // [23:23]
  431. l3_offset : 7, // [22:16]
  432. ipsec_esp : 1, // [15:15]
  433. stbc : 1, // [14:14]
  434. msdu_length : 14; // [13:0]
  435. uint32_t ip4_protocol_ip6_next_header : 8, // [31:24]
  436. ldpc : 1, // [23:23]
  437. mesh_control_present : 1, // [22:22]
  438. tcp_udp_header_valid : 1, // [21:21]
  439. ip_extn_header_valid : 1, // [20:20]
  440. ip_fixed_header_valid : 1, // [19:19]
  441. toeplitz_hash_sel : 2, // [18:17]
  442. da_is_bcast_mcast : 1, // [16:16]
  443. tcp_only_ack : 1, // [15:15]
  444. ip_frag : 1, // [14:14]
  445. udp_proto : 1, // [13:13]
  446. tcp_proto : 1, // [12:12]
  447. ipv6_proto : 1, // [11:11]
  448. ipv4_proto : 1, // [10:10]
  449. decap_format : 2, // [9:8]
  450. msdu_number : 8; // [7:0]
  451. uint32_t toeplitz_hash_2_or_4 : 32; // [31:0]
  452. uint32_t flow_id_toeplitz : 32; // [31:0]
  453. uint32_t mimo_ss_bitmap : 8, // [31:24]
  454. reception_type : 3, // [23:21]
  455. receive_bandwidth : 3, // [20:18]
  456. rate_mcs : 4, // [17:14]
  457. sgi : 2, // [13:12]
  458. pkt_type : 4, // [11:8]
  459. user_rssi : 8; // [7:0]
  460. uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0]
  461. uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0]
  462. uint32_t sw_phy_meta_data : 32; // [31:0]
  463. uint32_t vlan_stag_ci : 16, // [31:16]
  464. vlan_ctag_ci : 16; // [15:0]
  465. uint32_t reserved_27a : 32; // [31:0]
  466. uint32_t reserved_28a : 32; // [31:0]
  467. uint32_t reserved_29a : 32; // [31:0]
  468. uint32_t fcs_err : 1, // [31:31]
  469. unencrypted_frame_err : 1, // [30:30]
  470. decrypt_err : 1, // [29:29]
  471. tkip_mic_err : 1, // [28:28]
  472. mpdu_length_err : 1, // [27:27]
  473. buffer_fragment : 1, // [26:26]
  474. directed : 1, // [25:25]
  475. encrypt_required : 1, // [24:24]
  476. rx_in_tx_decrypt_byp : 1, // [23:23]
  477. reserved_30b : 1, // [22:22]
  478. da_idx_invalid : 1, // [21:21]
  479. sa_idx_invalid : 1, // [20:20]
  480. ip_chksum_fail : 1, // [19:19]
  481. tcp_udp_chksum_fail : 1, // [18:18]
  482. msdu_length_err : 1, // [17:17]
  483. overflow_err : 1, // [16:16]
  484. cce_match : 1, // [15:15]
  485. order : 1, // [14:14]
  486. fragment_flag : 1, // [13:13]
  487. a_msdu_error : 1, // [12:12]
  488. eosp : 1, // [11:11]
  489. more_data : 1, // [10:10]
  490. ctrl_type : 1, // [9:9]
  491. mgmt_type : 1, // [8:8]
  492. null_data : 1, // [7:7]
  493. non_qos : 1, // [6:6]
  494. power_mgmt : 1, // [5:5]
  495. ast_index_timeout : 1, // [4:4]
  496. ast_index_not_found : 1, // [3:3]
  497. mcast_bcast : 1, // [2:2]
  498. reserved_30a : 1, // [1:1]
  499. first_mpdu : 1; // [0:0]
  500. uint32_t msdu_done : 1, // [31:31]
  501. reserved_31b : 17, // [30:14]
  502. rx_bitmap_not_updated : 1, // [13:13]
  503. decrypt_status_code : 3, // [12:10]
  504. reserved_31a : 10; // [9:0]
  505. };
  506. struct rx_mpdu_start_compact_qca5332 {
  507. struct rxpt_classify_info rxpt_classify_info_details;
  508. uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0]
  509. uint32_t reserved_2a : 6, // [31:26]
  510. first_delim_err : 1, // [25:25]
  511. pre_delim_err_warning : 1, // [24:24]
  512. receive_queue_number : 16, // [23:8]
  513. rx_reo_queue_desc_addr_39_32 : 8; // [7:0]
  514. uint32_t pn_31_0 : 32; // [31:0]
  515. uint32_t pn_63_32 : 32; // [31:0]
  516. uint32_t pn_95_64 : 32; // [31:0]
  517. uint32_t pn_127_96 : 32; // [31:0]
  518. uint32_t reserved_7a : 13, // [31:19]
  519. tid : 4, // [18:15]
  520. bssid_number : 4, // [14:11]
  521. bssid_hit : 1, // [10:10]
  522. mesh_sta : 2, // [9:8]
  523. wep_key_width_for_variable_key : 2, // [7:6]
  524. encrypt_type : 4, // [5:2]
  525. all_frames_shall_be_encrypted : 1, // [1:1]
  526. epd_en : 1; // [0:0]
  527. uint32_t peer_meta_data : 32; // [31:0]
  528. uint32_t phy_ppdu_id : 16, // [31:16]
  529. reserved_9a : 1, // [15:15]
  530. ranging : 1, // [14:14]
  531. ast_based_lookup_valid : 1, // [13:13]
  532. protocol_version_err : 1, // [12:12]
  533. phy_err_during_mpdu_header : 1, // [11:11]
  534. phy_err : 1, // [10:10]
  535. ndp_frame : 1, // [9:9]
  536. sw_frame_group_id : 7, // [8:2]
  537. rxpcu_mpdu_filter_in_category : 2; // [1:0]
  538. uint32_t sw_peer_id : 16, // [31:16]
  539. ast_index : 16; // [15:0]
  540. uint32_t mpdu_sequence_number : 12, // [31:20]
  541. mpdu_retry : 1, // [19:19]
  542. encrypted : 1, // [18:18]
  543. to_ds : 1, // [17:17]
  544. fr_ds : 1, // [16:16]
  545. reserved_11a : 1, // [15:15]
  546. more_fragment_flag : 1, // [14:14]
  547. mpdu_fragment_number : 4, // [13:10]
  548. frame_encryption_info_valid : 1, // [9:9]
  549. mpdu_ht_control_valid : 1, // [8:8]
  550. mpdu_qos_control_valid : 1, // [7:7]
  551. mpdu_sequence_control_valid : 1, // [6:6]
  552. mac_addr_ad4_valid : 1, // [5:5]
  553. mac_addr_ad3_valid : 1, // [4:4]
  554. mac_addr_ad2_valid : 1, // [3:3]
  555. mac_addr_ad1_valid : 1, // [2:2]
  556. mpdu_duration_valid : 1, // [1:1]
  557. mpdu_frame_control_valid : 1; // [0:0]
  558. uint32_t reserved_12 : 1, // [31:31]
  559. raw_mpdu : 1, // [30:30]
  560. bar_frame : 1, // [29:29]
  561. ampdu_flag : 1, // [28:28]
  562. pre_delim_count : 12, // [27:16]
  563. strip_vlan_s_tag_decap : 1, // [15:15]
  564. strip_vlan_c_tag_decap : 1, // [14:14]
  565. rx_insert_vlan_s_tag_padding : 1, // [13:13]
  566. rx_insert_vlan_c_tag_padding : 1, // [12:12]
  567. decap_type : 2, // [11:10]
  568. decrypt_needed : 1, // [9:9]
  569. new_peer_entry : 1, // [8:8]
  570. key_id_octet : 8; // [7:0]
  571. uint32_t reserved_13 : 1, // [31:31]
  572. amsdu_present : 1, // [30:30]
  573. directed : 1, // [29:29]
  574. encrypt_required : 1, // [28:28]
  575. u_apsd_trigger : 1, // [27:27]
  576. order : 1, // [26:26]
  577. fragment_flag : 1, // [25:25]
  578. eosp : 1, // [24:24]
  579. more_data : 1, // [23:23]
  580. ctrl_type : 1, // [22:22]
  581. mgmt_type : 1, // [21:21]
  582. null_data : 1, // [20:20]
  583. non_qos : 1, // [19:19]
  584. power_mgmt : 1, // [18:18]
  585. ast_index_timeout : 1, // [17:17]
  586. ast_index_not_found : 1, // [16:16]
  587. mcast_bcast : 1, // [15:15]
  588. first_mpdu : 1, // [14:14]
  589. mpdu_length : 14; // [13:0]
  590. uint32_t mpdu_duration_field : 16, // [31:16]
  591. mpdu_frame_control_field : 16; // [15:0]
  592. uint32_t mac_addr_ad1_31_0 : 32; // [31:0]
  593. uint32_t mac_addr_ad2_15_0 : 16, // [31:16]
  594. mac_addr_ad1_47_32 : 16; // [15:0]
  595. uint32_t mac_addr_ad2_47_16 : 32; // [31:0]
  596. uint32_t mac_addr_ad3_31_0 : 32; // [31:0]
  597. uint32_t mpdu_sequence_control_field : 16, // [31:16]
  598. mac_addr_ad3_47_32 : 16; // [15:0]
  599. uint32_t mac_addr_ad4_31_0 : 32; // [31:0]
  600. uint32_t mpdu_qos_control_field : 16, // [31:16]
  601. mac_addr_ad4_47_32 : 16; // [15:0]
  602. uint32_t mpdu_ht_control_field : 32; // [31:0]
  603. uint32_t multi_link_addr_ad1_ad2_valid : 1, // [31:31]
  604. reserved_23a : 1, // [30:30]
  605. src_info : 12, // [29:18]
  606. priority_valid : 1, // [17:17]
  607. service_code : 9, // [16:8]
  608. vdev_id : 8; // [7:0]
  609. uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0]
  610. uint32_t multi_link_addr_ad2_15_0 : 16, // [31:16]
  611. multi_link_addr_ad1_47_32 : 16; // [15:0]
  612. uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0]
  613. uint32_t reserved_27a : 32; // [31:0]
  614. uint32_t reserved_28a : 32; // [31:0]
  615. uint32_t reserved_29a : 32; // [31:0]
  616. };
  617. #endif /* BIG_ENDIAN_HOST */
  618. /* TLV struct for word based Tlv */
  619. typedef struct rx_mpdu_start_compact_qca5332 hal_rx_mpdu_start_t;
  620. typedef struct rx_msdu_end_compact_qca5332 hal_rx_msdu_end_t;
  621. #endif /* CONFIG_WORD_BASED_TLV */
  622. #include "hal_5332_rx.h"
  623. #include "hal_5332_tx.h"
  624. #include "hal_be_rx_tlv.h"
  625. #include <hal_be_generic_api.h>
  626. #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
  627. #define HAL_PPE_VP_ENTRIES_MAX 32
  628. /**
  629. * hal_get_link_desc_size_5332(): API to get the link desc size
  630. *
  631. * Return: uint32_t
  632. */
  633. static uint32_t hal_get_link_desc_size_5332(void)
  634. {
  635. return LINK_DESC_SIZE;
  636. }
  637. /**
  638. * hal_rx_get_tlv_5332(): API to get the tlv
  639. *
  640. * @rx_tlv: TLV data extracted from the rx packet
  641. * Return: uint8_t
  642. */
  643. static uint8_t hal_rx_get_tlv_5332(void *rx_tlv)
  644. {
  645. return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH);
  646. }
  647. /**
  648. * hal_rx_wbm_err_msdu_continuation_get_5332 () - API to check if WBM
  649. * msdu continuation bit is set
  650. *
  651. *@wbm_desc: wbm release ring descriptor
  652. *
  653. * Return: true if msdu continuation bit is set.
  654. */
  655. uint8_t hal_rx_wbm_err_msdu_continuation_get_5332(void *wbm_desc)
  656. {
  657. uint32_t comp_desc = *(uint32_t *)(((uint8_t *)wbm_desc) +
  658. WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET);
  659. return (comp_desc &
  660. WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK) >>
  661. WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB;
  662. }
  663. /**
  664. * hal_rx_proc_phyrx_other_receive_info_tlv_5332(): API to get tlv info
  665. *
  666. * Return: uint32_t
  667. */
  668. static inline
  669. void hal_rx_proc_phyrx_other_receive_info_tlv_5332(void *rx_tlv_hdr,
  670. void *ppdu_info_hdl)
  671. {
  672. uint32_t tlv_tag, tlv_len;
  673. uint32_t temp_len, other_tlv_len, other_tlv_tag;
  674. void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
  675. void *other_tlv_hdr = NULL;
  676. void *other_tlv = NULL;
  677. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
  678. tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
  679. temp_len = 0;
  680. other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE;
  681. other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr);
  682. other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr);
  683. temp_len += other_tlv_len;
  684. other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
  685. switch (other_tlv_tag) {
  686. default:
  687. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  688. "%s unhandled TLV type: %d, TLV len:%d",
  689. __func__, other_tlv_tag, other_tlv_len);
  690. break;
  691. }
  692. }
  693. #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
  694. static inline
  695. void hal_rx_get_bb_info_5332(void *rx_tlv, void *ppdu_info_hdl)
  696. {
  697. struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
  698. ppdu_info->cfr_info.bb_captured_channel =
  699. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL);
  700. ppdu_info->cfr_info.bb_captured_timeout =
  701. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT);
  702. ppdu_info->cfr_info.bb_captured_reason =
  703. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON);
  704. }
  705. static inline
  706. void hal_rx_get_rtt_info_5332(void *rx_tlv, void *ppdu_info_hdl)
  707. {
  708. struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
  709. ppdu_info->cfr_info.rx_location_info_valid =
  710. HAL_RX_GET(rx_tlv, PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  711. RX_LOCATION_INFO_VALID);
  712. ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 =
  713. HAL_RX_GET(rx_tlv,
  714. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  715. RTT_CHE_BUFFER_POINTER_LOW32);
  716. ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 =
  717. HAL_RX_GET(rx_tlv,
  718. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  719. RTT_CHE_BUFFER_POINTER_HIGH8);
  720. ppdu_info->cfr_info.chan_capture_status =
  721. HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv);
  722. ppdu_info->cfr_info.rx_start_ts =
  723. HAL_RX_GET(rx_tlv,
  724. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  725. RX_START_TS);
  726. ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t)
  727. HAL_RX_GET(rx_tlv,
  728. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  729. RTT_CFO_MEASUREMENT);
  730. ppdu_info->cfr_info.agc_gain_info0 =
  731. HAL_RX_GET(rx_tlv,
  732. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  733. GAIN_CHAIN0);
  734. ppdu_info->cfr_info.agc_gain_info0 |=
  735. (((uint32_t)HAL_RX_GET(rx_tlv,
  736. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  737. GAIN_CHAIN1)) << 16);
  738. ppdu_info->cfr_info.agc_gain_info1 =
  739. HAL_RX_GET(rx_tlv,
  740. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  741. GAIN_CHAIN2);
  742. ppdu_info->cfr_info.agc_gain_info1 |=
  743. (((uint32_t)HAL_RX_GET(rx_tlv,
  744. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  745. GAIN_CHAIN3)) << 16);
  746. ppdu_info->cfr_info.agc_gain_info2 = 0;
  747. ppdu_info->cfr_info.agc_gain_info3 = 0;
  748. }
  749. #endif
  750. /**
  751. * hal_rx_dump_mpdu_start_tlv_5332: dump RX mpdu_start TLV in structured
  752. * human readable format.
  753. * @mpdu_start: pointer the rx_attention TLV in pkt.
  754. * @dbg_level: log level.
  755. *
  756. * Return: void
  757. */
  758. static inline void hal_rx_dump_mpdu_start_tlv_5332(void *mpdustart,
  759. uint8_t dbg_level)
  760. {
  761. #ifdef CONFIG_WORD_BASED_TLV
  762. struct rx_mpdu_start_compact_qca5332 *mpdu_info =
  763. (struct rx_mpdu_start_compact_qca5332 *)mpdustart;
  764. #else
  765. struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart;
  766. struct rx_mpdu_info *mpdu_info =
  767. (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details;
  768. #endif
  769. QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
  770. "rx_mpdu_start tlv (1/5) - "
  771. "rx_reo_queue_desc_addr_31_0 :%x"
  772. "rx_reo_queue_desc_addr_39_32 :%x"
  773. "receive_queue_number:%x "
  774. "pre_delim_err_warning:%x "
  775. "first_delim_err:%x "
  776. "reserved_2a:%x "
  777. "pn_31_0:%x "
  778. "pn_63_32:%x "
  779. "pn_95_64:%x "
  780. "pn_127_96:%x "
  781. "epd_en:%x "
  782. "all_frames_shall_be_encrypted :%x"
  783. "encrypt_type:%x "
  784. "wep_key_width_for_variable_key :%x"
  785. "mesh_sta:%x "
  786. "bssid_hit:%x "
  787. "bssid_number:%x "
  788. "tid:%x "
  789. "reserved_7a:%x ",
  790. mpdu_info->rx_reo_queue_desc_addr_31_0,
  791. mpdu_info->rx_reo_queue_desc_addr_39_32,
  792. mpdu_info->receive_queue_number,
  793. mpdu_info->pre_delim_err_warning,
  794. mpdu_info->first_delim_err,
  795. mpdu_info->reserved_2a,
  796. mpdu_info->pn_31_0,
  797. mpdu_info->pn_63_32,
  798. mpdu_info->pn_95_64,
  799. mpdu_info->pn_127_96,
  800. mpdu_info->epd_en,
  801. mpdu_info->all_frames_shall_be_encrypted,
  802. mpdu_info->encrypt_type,
  803. mpdu_info->wep_key_width_for_variable_key,
  804. mpdu_info->mesh_sta,
  805. mpdu_info->bssid_hit,
  806. mpdu_info->bssid_number,
  807. mpdu_info->tid,
  808. mpdu_info->reserved_7a);
  809. QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
  810. "rx_mpdu_start tlv (2/5) - "
  811. "ast_index:%x "
  812. "sw_peer_id:%x "
  813. "mpdu_frame_control_valid:%x "
  814. "mpdu_duration_valid:%x "
  815. "mac_addr_ad1_valid:%x "
  816. "mac_addr_ad2_valid:%x "
  817. "mac_addr_ad3_valid:%x "
  818. "mac_addr_ad4_valid:%x "
  819. "mpdu_sequence_control_valid :%x"
  820. "mpdu_qos_control_valid:%x "
  821. "mpdu_ht_control_valid:%x "
  822. "frame_encryption_info_valid :%x",
  823. mpdu_info->ast_index,
  824. mpdu_info->sw_peer_id,
  825. mpdu_info->mpdu_frame_control_valid,
  826. mpdu_info->mpdu_duration_valid,
  827. mpdu_info->mac_addr_ad1_valid,
  828. mpdu_info->mac_addr_ad2_valid,
  829. mpdu_info->mac_addr_ad3_valid,
  830. mpdu_info->mac_addr_ad4_valid,
  831. mpdu_info->mpdu_sequence_control_valid,
  832. mpdu_info->mpdu_qos_control_valid,
  833. mpdu_info->mpdu_ht_control_valid,
  834. mpdu_info->frame_encryption_info_valid);
  835. QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
  836. "rx_mpdu_start tlv (3/5) - "
  837. "mpdu_fragment_number:%x "
  838. "more_fragment_flag:%x "
  839. "reserved_11a:%x "
  840. "fr_ds:%x "
  841. "to_ds:%x "
  842. "encrypted:%x "
  843. "mpdu_retry:%x "
  844. "mpdu_sequence_number:%x ",
  845. mpdu_info->mpdu_fragment_number,
  846. mpdu_info->more_fragment_flag,
  847. mpdu_info->reserved_11a,
  848. mpdu_info->fr_ds,
  849. mpdu_info->to_ds,
  850. mpdu_info->encrypted,
  851. mpdu_info->mpdu_retry,
  852. mpdu_info->mpdu_sequence_number);
  853. QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
  854. "rx_mpdu_start tlv (4/5) - "
  855. "mpdu_frame_control_field:%x "
  856. "mpdu_duration_field:%x ",
  857. mpdu_info->mpdu_frame_control_field,
  858. mpdu_info->mpdu_duration_field);
  859. QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
  860. "rx_mpdu_start tlv (5/5) - "
  861. "mac_addr_ad1_31_0:%x "
  862. "mac_addr_ad1_47_32:%x "
  863. "mac_addr_ad2_15_0:%x "
  864. "mac_addr_ad2_47_16:%x "
  865. "mac_addr_ad3_31_0:%x "
  866. "mac_addr_ad3_47_32:%x "
  867. "mpdu_sequence_control_field :%x"
  868. "mac_addr_ad4_31_0:%x "
  869. "mac_addr_ad4_47_32:%x "
  870. "mpdu_qos_control_field:%x ",
  871. mpdu_info->mac_addr_ad1_31_0,
  872. mpdu_info->mac_addr_ad1_47_32,
  873. mpdu_info->mac_addr_ad2_15_0,
  874. mpdu_info->mac_addr_ad2_47_16,
  875. mpdu_info->mac_addr_ad3_31_0,
  876. mpdu_info->mac_addr_ad3_47_32,
  877. mpdu_info->mpdu_sequence_control_field,
  878. mpdu_info->mac_addr_ad4_31_0,
  879. mpdu_info->mac_addr_ad4_47_32,
  880. mpdu_info->mpdu_qos_control_field);
  881. }
  882. /**
  883. * hal_rx_dump_msdu_end_tlv_5332: dump RX msdu_end TLV in structured
  884. * human readable format.
  885. * @ msdu_end: pointer the msdu_end TLV in pkt.
  886. * @ dbg_level: log level.
  887. *
  888. * Return: void
  889. */
  890. static void hal_rx_dump_msdu_end_tlv_5332(void *msduend,
  891. uint8_t dbg_level)
  892. {
  893. #ifdef CONFIG_WORD_BASED_TLV
  894. struct rx_msdu_end_compact_qca5332 *msdu_end =
  895. (struct rx_msdu_end_compact_qca5332 *)msduend;
  896. #else
  897. struct rx_msdu_end *msdu_end =
  898. (struct rx_msdu_end *)msduend;
  899. #endif
  900. QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
  901. "rx_msdu_end tlv - "
  902. "key_id_octet: %d "
  903. "cce_super_rule: %d "
  904. "cce_classify_not_done_truncat: %d "
  905. "cce_classify_not_done_cce_dis: %d "
  906. "rule_indication_31_0: %d "
  907. "tcp_udp_chksum: %d "
  908. "sa_idx_timeout: %d "
  909. "da_idx_timeout: %d "
  910. "msdu_limit_error: %d "
  911. "flow_idx_timeout: %d "
  912. "flow_idx_invalid: %d "
  913. "wifi_parser_error: %d "
  914. "sa_is_valid: %d "
  915. "da_is_valid: %d "
  916. "da_is_mcbc: %d "
  917. "tkip_mic_err: %d "
  918. "l3_header_padding: %d "
  919. "first_msdu: %d "
  920. "last_msdu: %d "
  921. "sa_idx: %d "
  922. "msdu_drop: %d "
  923. "reo_destination_indication: %d "
  924. "flow_idx: %d "
  925. "fse_metadata: %d "
  926. "cce_metadata: %d "
  927. "sa_sw_peer_id: %d ",
  928. msdu_end->key_id_octet,
  929. msdu_end->cce_super_rule,
  930. msdu_end->cce_classify_not_done_truncate,
  931. msdu_end->cce_classify_not_done_cce_dis,
  932. msdu_end->rule_indication_31_0,
  933. msdu_end->tcp_udp_chksum,
  934. msdu_end->sa_idx_timeout,
  935. msdu_end->da_idx_timeout,
  936. msdu_end->msdu_limit_error,
  937. msdu_end->flow_idx_timeout,
  938. msdu_end->flow_idx_invalid,
  939. msdu_end->wifi_parser_error,
  940. msdu_end->sa_is_valid,
  941. msdu_end->da_is_valid,
  942. msdu_end->da_is_mcbc,
  943. msdu_end->tkip_mic_err,
  944. msdu_end->l3_header_padding,
  945. msdu_end->first_msdu,
  946. msdu_end->last_msdu,
  947. msdu_end->sa_idx,
  948. msdu_end->msdu_drop,
  949. msdu_end->reo_destination_indication,
  950. msdu_end->flow_idx,
  951. msdu_end->fse_metadata,
  952. msdu_end->cce_metadata,
  953. msdu_end->sa_sw_peer_id);
  954. }
  955. /**
  956. * hal_reo_status_get_header_5332 - Process reo desc info
  957. * @d - Pointer to reo descriptior
  958. * @b - tlv type info
  959. * @h1 - Pointer to hal_reo_status_header where info to be stored
  960. *
  961. * Return - none.
  962. *
  963. */
  964. static void hal_reo_status_get_header_5332(hal_ring_desc_t ring_desc,
  965. int b, void *h1)
  966. {
  967. uint64_t *d = (uint64_t *)ring_desc;
  968. uint64_t val1 = 0;
  969. struct hal_reo_status_header *h =
  970. (struct hal_reo_status_header *)h1;
  971. /* Offsets of descriptor fields defined in HW headers start
  972. * from the field after TLV header
  973. */
  974. d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
  975. switch (b) {
  976. case HAL_REO_QUEUE_STATS_STATUS_TLV:
  977. val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  978. STATUS_HEADER_REO_STATUS_NUMBER)];
  979. break;
  980. case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
  981. val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS,
  982. STATUS_HEADER_REO_STATUS_NUMBER)];
  983. break;
  984. case HAL_REO_FLUSH_CACHE_STATUS_TLV:
  985. val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
  986. STATUS_HEADER_REO_STATUS_NUMBER)];
  987. break;
  988. case HAL_REO_UNBLK_CACHE_STATUS_TLV:
  989. val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
  990. STATUS_HEADER_REO_STATUS_NUMBER)];
  991. break;
  992. case HAL_REO_TIMOUT_LIST_STATUS_TLV:
  993. val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
  994. STATUS_HEADER_REO_STATUS_NUMBER)];
  995. break;
  996. case HAL_REO_DESC_THRES_STATUS_TLV:
  997. val1 =
  998. d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  999. STATUS_HEADER_REO_STATUS_NUMBER)];
  1000. break;
  1001. case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
  1002. val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS,
  1003. STATUS_HEADER_REO_STATUS_NUMBER)];
  1004. break;
  1005. default:
  1006. qdf_nofl_err("ERROR: Unknown tlv\n");
  1007. break;
  1008. }
  1009. h->cmd_num =
  1010. HAL_GET_FIELD(
  1011. UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER,
  1012. val1);
  1013. h->exec_time =
  1014. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER,
  1015. CMD_EXECUTION_TIME, val1);
  1016. h->status =
  1017. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER,
  1018. REO_CMD_EXECUTION_STATUS, val1);
  1019. switch (b) {
  1020. case HAL_REO_QUEUE_STATS_STATUS_TLV:
  1021. val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  1022. STATUS_HEADER_TIMESTAMP)];
  1023. break;
  1024. case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
  1025. val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS,
  1026. STATUS_HEADER_TIMESTAMP)];
  1027. break;
  1028. case HAL_REO_FLUSH_CACHE_STATUS_TLV:
  1029. val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
  1030. STATUS_HEADER_TIMESTAMP)];
  1031. break;
  1032. case HAL_REO_UNBLK_CACHE_STATUS_TLV:
  1033. val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
  1034. STATUS_HEADER_TIMESTAMP)];
  1035. break;
  1036. case HAL_REO_TIMOUT_LIST_STATUS_TLV:
  1037. val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
  1038. STATUS_HEADER_TIMESTAMP)];
  1039. break;
  1040. case HAL_REO_DESC_THRES_STATUS_TLV:
  1041. val1 =
  1042. d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  1043. STATUS_HEADER_TIMESTAMP)];
  1044. break;
  1045. case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
  1046. val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS,
  1047. STATUS_HEADER_TIMESTAMP)];
  1048. break;
  1049. default:
  1050. qdf_nofl_err("ERROR: Unknown tlv\n");
  1051. break;
  1052. }
  1053. h->tstamp =
  1054. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1);
  1055. }
  1056. static
  1057. void *hal_rx_msdu0_buffer_addr_lsb_5332(void *link_desc_va)
  1058. {
  1059. return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
  1060. }
  1061. static
  1062. void *hal_rx_msdu_desc_info_ptr_get_5332(void *msdu0)
  1063. {
  1064. return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
  1065. }
  1066. static
  1067. void *hal_ent_mpdu_desc_info_5332(void *ent_ring_desc)
  1068. {
  1069. return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
  1070. }
  1071. static
  1072. void *hal_dst_mpdu_desc_info_5332(void *dst_ring_desc)
  1073. {
  1074. return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
  1075. }
  1076. /**
  1077. * hal_reo_config_5332(): Set reo config parameters
  1078. * @soc: hal soc handle
  1079. * @reg_val: value to be set
  1080. * @reo_params: reo parameters
  1081. *
  1082. * Return: void
  1083. */
  1084. static void
  1085. hal_reo_config_5332(struct hal_soc *soc,
  1086. uint32_t reg_val,
  1087. struct hal_reo_params *reo_params)
  1088. {
  1089. HAL_REO_R0_CONFIG(soc, reg_val, reo_params);
  1090. }
  1091. /**
  1092. * hal_rx_msdu_desc_info_get_ptr_5332() - Get msdu desc info ptr
  1093. * @msdu_details_ptr - Pointer to msdu_details_ptr
  1094. *
  1095. * Return - Pointer to rx_msdu_desc_info structure.
  1096. *
  1097. */
  1098. static void *hal_rx_msdu_desc_info_get_ptr_5332(void *msdu_details_ptr)
  1099. {
  1100. return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr);
  1101. }
  1102. /**
  1103. * hal_rx_link_desc_msdu0_ptr_5332 - Get pointer to rx_msdu details
  1104. * @link_desc - Pointer to link desc
  1105. *
  1106. * Return - Pointer to rx_msdu_details structure
  1107. *
  1108. */
  1109. static void *hal_rx_link_desc_msdu0_ptr_5332(void *link_desc)
  1110. {
  1111. return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc);
  1112. }
  1113. /**
  1114. * hal_get_window_address_5332(): Function to get hp/tp address
  1115. * @hal_soc: Pointer to hal_soc
  1116. * @addr: address offset of register
  1117. *
  1118. * Return: modified address offset of register
  1119. */
  1120. static inline qdf_iomem_t hal_get_window_address_5332(struct hal_soc *hal_soc,
  1121. qdf_iomem_t addr)
  1122. {
  1123. uint32_t offset = addr - hal_soc->dev_base_addr;
  1124. qdf_iomem_t new_offset;
  1125. /*
  1126. * Check if offset lies within CE register range(0x740000)
  1127. * or UMAC/DP register range (0x00A00000).
  1128. * If offset lies within CE register range, map it
  1129. * into CE region.
  1130. */
  1131. if (offset < 0xA00000) {
  1132. offset = offset - CE_CFG_WFSS_CE_REG_BASE;
  1133. new_offset = (hal_soc->dev_base_addr_ce + offset);
  1134. return new_offset;
  1135. } else {
  1136. /*
  1137. * If offset lies within DP register range,
  1138. * return the address as such
  1139. */
  1140. return addr;
  1141. }
  1142. }
  1143. static
  1144. void hal_compute_reo_remap_ix2_ix3_5332(uint32_t *ring, uint32_t num_rings,
  1145. uint32_t *remap1, uint32_t *remap2)
  1146. {
  1147. switch (num_rings) {
  1148. case 1:
  1149. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  1150. HAL_REO_REMAP_IX2(ring[0], 17) |
  1151. HAL_REO_REMAP_IX2(ring[0], 18) |
  1152. HAL_REO_REMAP_IX2(ring[0], 19) |
  1153. HAL_REO_REMAP_IX2(ring[0], 20) |
  1154. HAL_REO_REMAP_IX2(ring[0], 21) |
  1155. HAL_REO_REMAP_IX2(ring[0], 22) |
  1156. HAL_REO_REMAP_IX2(ring[0], 23);
  1157. *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
  1158. HAL_REO_REMAP_IX3(ring[0], 25) |
  1159. HAL_REO_REMAP_IX3(ring[0], 26) |
  1160. HAL_REO_REMAP_IX3(ring[0], 27) |
  1161. HAL_REO_REMAP_IX3(ring[0], 28) |
  1162. HAL_REO_REMAP_IX3(ring[0], 29) |
  1163. HAL_REO_REMAP_IX3(ring[0], 30) |
  1164. HAL_REO_REMAP_IX3(ring[0], 31);
  1165. break;
  1166. case 2:
  1167. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  1168. HAL_REO_REMAP_IX2(ring[0], 17) |
  1169. HAL_REO_REMAP_IX2(ring[1], 18) |
  1170. HAL_REO_REMAP_IX2(ring[1], 19) |
  1171. HAL_REO_REMAP_IX2(ring[0], 20) |
  1172. HAL_REO_REMAP_IX2(ring[0], 21) |
  1173. HAL_REO_REMAP_IX2(ring[1], 22) |
  1174. HAL_REO_REMAP_IX2(ring[1], 23);
  1175. *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
  1176. HAL_REO_REMAP_IX3(ring[0], 25) |
  1177. HAL_REO_REMAP_IX3(ring[1], 26) |
  1178. HAL_REO_REMAP_IX3(ring[1], 27) |
  1179. HAL_REO_REMAP_IX3(ring[0], 28) |
  1180. HAL_REO_REMAP_IX3(ring[0], 29) |
  1181. HAL_REO_REMAP_IX3(ring[1], 30) |
  1182. HAL_REO_REMAP_IX3(ring[1], 31);
  1183. break;
  1184. case 3:
  1185. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  1186. HAL_REO_REMAP_IX2(ring[1], 17) |
  1187. HAL_REO_REMAP_IX2(ring[2], 18) |
  1188. HAL_REO_REMAP_IX2(ring[0], 19) |
  1189. HAL_REO_REMAP_IX2(ring[1], 20) |
  1190. HAL_REO_REMAP_IX2(ring[2], 21) |
  1191. HAL_REO_REMAP_IX2(ring[0], 22) |
  1192. HAL_REO_REMAP_IX2(ring[1], 23);
  1193. *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) |
  1194. HAL_REO_REMAP_IX3(ring[0], 25) |
  1195. HAL_REO_REMAP_IX3(ring[1], 26) |
  1196. HAL_REO_REMAP_IX3(ring[2], 27) |
  1197. HAL_REO_REMAP_IX3(ring[0], 28) |
  1198. HAL_REO_REMAP_IX3(ring[1], 29) |
  1199. HAL_REO_REMAP_IX3(ring[2], 30) |
  1200. HAL_REO_REMAP_IX3(ring[0], 31);
  1201. break;
  1202. case 4:
  1203. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  1204. HAL_REO_REMAP_IX2(ring[1], 17) |
  1205. HAL_REO_REMAP_IX2(ring[2], 18) |
  1206. HAL_REO_REMAP_IX2(ring[3], 19) |
  1207. HAL_REO_REMAP_IX2(ring[0], 20) |
  1208. HAL_REO_REMAP_IX2(ring[1], 21) |
  1209. HAL_REO_REMAP_IX2(ring[2], 22) |
  1210. HAL_REO_REMAP_IX2(ring[3], 23);
  1211. *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
  1212. HAL_REO_REMAP_IX3(ring[1], 25) |
  1213. HAL_REO_REMAP_IX3(ring[2], 26) |
  1214. HAL_REO_REMAP_IX3(ring[3], 27) |
  1215. HAL_REO_REMAP_IX3(ring[0], 28) |
  1216. HAL_REO_REMAP_IX3(ring[1], 29) |
  1217. HAL_REO_REMAP_IX3(ring[2], 30) |
  1218. HAL_REO_REMAP_IX3(ring[3], 31);
  1219. break;
  1220. }
  1221. }
  1222. /**
  1223. * hal_rx_flow_setup_fse_5332() - Setup a flow search entry in HW FST
  1224. * @fst: Pointer to the Rx Flow Search Table
  1225. * @table_offset: offset into the table where the flow is to be setup
  1226. * @flow: Flow Parameters
  1227. *
  1228. * Return: Success/Failure
  1229. */
  1230. static void *
  1231. hal_rx_flow_setup_fse_5332(uint8_t *rx_fst, uint32_t table_offset,
  1232. uint8_t *rx_flow)
  1233. {
  1234. struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
  1235. struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow;
  1236. uint8_t *fse;
  1237. bool fse_valid;
  1238. if (table_offset >= fst->max_entries) {
  1239. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1240. "HAL FSE table offset %u exceeds max entries %u",
  1241. table_offset, fst->max_entries);
  1242. return NULL;
  1243. }
  1244. fse = (uint8_t *)fst->base_vaddr +
  1245. (table_offset * HAL_RX_FST_ENTRY_SIZE);
  1246. fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
  1247. if (fse_valid) {
  1248. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  1249. "HAL FSE %pK already valid", fse);
  1250. return NULL;
  1251. }
  1252. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) =
  1253. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96,
  1254. qdf_htonl(flow->tuple_info.src_ip_127_96));
  1255. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) =
  1256. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64,
  1257. qdf_htonl(flow->tuple_info.src_ip_95_64));
  1258. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) =
  1259. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32,
  1260. qdf_htonl(flow->tuple_info.src_ip_63_32));
  1261. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) =
  1262. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0,
  1263. qdf_htonl(flow->tuple_info.src_ip_31_0));
  1264. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) =
  1265. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96,
  1266. qdf_htonl(flow->tuple_info.dest_ip_127_96));
  1267. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) =
  1268. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64,
  1269. qdf_htonl(flow->tuple_info.dest_ip_95_64));
  1270. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) =
  1271. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32,
  1272. qdf_htonl(flow->tuple_info.dest_ip_63_32));
  1273. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) =
  1274. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0,
  1275. qdf_htonl(flow->tuple_info.dest_ip_31_0));
  1276. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT);
  1277. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |=
  1278. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT,
  1279. (flow->tuple_info.dest_port));
  1280. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT);
  1281. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |=
  1282. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT,
  1283. (flow->tuple_info.src_port));
  1284. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL);
  1285. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |=
  1286. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL,
  1287. flow->tuple_info.l4_protocol);
  1288. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER);
  1289. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |=
  1290. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER,
  1291. flow->reo_destination_handler);
  1292. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
  1293. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |=
  1294. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1);
  1295. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA);
  1296. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) =
  1297. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA,
  1298. flow->fse_metadata);
  1299. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION);
  1300. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |=
  1301. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY,
  1302. REO_DESTINATION_INDICATION,
  1303. flow->reo_destination_indication);
  1304. /* Reset all the other fields in FSE */
  1305. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9);
  1306. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP);
  1307. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT);
  1308. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT);
  1309. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP);
  1310. return fse;
  1311. }
  1312. #ifndef NO_RX_PKT_HDR_TLV
  1313. /**
  1314. * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format
  1315. * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt.
  1316. * @ dbg_level: log level.
  1317. *
  1318. * Return: void
  1319. */
  1320. static inline void hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs *pkt_tlvs,
  1321. uint8_t dbg_level)
  1322. {
  1323. struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv;
  1324. hal_verbose_debug("\n---------------\n"
  1325. "rx_pkt_hdr_tlv\n"
  1326. "---------------\n"
  1327. "phy_ppdu_id %llu ",
  1328. pkt_hdr_tlv->phy_ppdu_id);
  1329. hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr,
  1330. sizeof(pkt_hdr_tlv->rx_pkt_hdr));
  1331. }
  1332. #else
  1333. /**
  1334. * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format
  1335. * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt.
  1336. * @ dbg_level: log level.
  1337. *
  1338. * Return: void
  1339. */
  1340. static inline void hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs *pkt_tlvs,
  1341. uint8_t dbg_level)
  1342. {
  1343. }
  1344. #endif
  1345. /**
  1346. * hal_rx_dump_pkt_tlvs_5332(): API to print RX Pkt TLVS qca5332
  1347. * @hal_soc_hdl: hal_soc handle
  1348. * @buf: pointer the pkt buffer
  1349. * @dbg_level: log level
  1350. *
  1351. * Return: void
  1352. */
  1353. #ifdef CONFIG_WORD_BASED_TLV
  1354. static void hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl,
  1355. uint8_t *buf, uint8_t dbg_level)
  1356. {
  1357. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1358. struct rx_msdu_end_compact_qca5332 *msdu_end =
  1359. &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1360. struct rx_mpdu_start_compact_qca5332 *mpdu_start =
  1361. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  1362. hal_rx_dump_msdu_end_tlv_5332(msdu_end, dbg_level);
  1363. hal_rx_dump_mpdu_start_tlv_5332(mpdu_start, dbg_level);
  1364. hal_rx_dump_pkt_hdr_tlv_5332(pkt_tlvs, dbg_level);
  1365. }
  1366. #else
  1367. static void hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl,
  1368. uint8_t *buf, uint8_t dbg_level)
  1369. {
  1370. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1371. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1372. struct rx_mpdu_start *mpdu_start =
  1373. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  1374. hal_rx_dump_msdu_end_tlv_5332(msdu_end, dbg_level);
  1375. hal_rx_dump_mpdu_start_tlv_5332(mpdu_start, dbg_level);
  1376. hal_rx_dump_pkt_hdr_tlv_5332(pkt_tlvs, dbg_level);
  1377. }
  1378. #endif
  1379. #define HAL_NUM_TCL_BANKS_5332 24
  1380. /**
  1381. * hal_cmem_write_5332() - function for CMEM buffer writing
  1382. * @hal_soc_hdl: HAL SOC handle
  1383. * @offset: CMEM address
  1384. * @value: value to write
  1385. *
  1386. * Return: None.
  1387. */
  1388. static void hal_cmem_write_5332(hal_soc_handle_t hal_soc_hdl,
  1389. uint32_t offset,
  1390. uint32_t value)
  1391. {
  1392. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  1393. /* cmem region is ioremapped from CMEM_REG_BASE, hence subtracting
  1394. * that from offset.
  1395. */
  1396. offset = offset - CMEM_REG_BASE;
  1397. pld_reg_write(hal->qdf_dev->dev, offset, value,
  1398. hal->dev_base_addr_cmem);
  1399. }
  1400. /**
  1401. * hal_tx_get_num_tcl_banks_5332() - Get number of banks in target
  1402. *
  1403. * Returns: number of bank
  1404. */
  1405. static uint8_t hal_tx_get_num_tcl_banks_5332(void)
  1406. {
  1407. return HAL_NUM_TCL_BANKS_5332;
  1408. }
  1409. static void hal_reo_setup_5332(struct hal_soc *soc, void *reoparams,
  1410. int qref_reset)
  1411. {
  1412. uint32_t reg_val;
  1413. struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams;
  1414. reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR(
  1415. REO_REG_REG_BASE));
  1416. hal_reo_config_5332(soc, reg_val, reo_params);
  1417. /* Other ring enable bits and REO_ENABLE will be set by FW */
  1418. /* TODO: Setup destination ring mapping if enabled */
  1419. /* TODO: Error destination ring setting is left to default.
  1420. * Default setting is to send all errors to release ring.
  1421. */
  1422. /* Set the reo descriptor swap bits in case of BIG endian platform */
  1423. hal_setup_reo_swap(soc);
  1424. HAL_REG_WRITE(soc,
  1425. HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(REO_REG_REG_BASE),
  1426. HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000);
  1427. HAL_REG_WRITE(soc,
  1428. HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(REO_REG_REG_BASE),
  1429. (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
  1430. HAL_REG_WRITE(soc,
  1431. HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(REO_REG_REG_BASE),
  1432. (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
  1433. HAL_REG_WRITE(soc,
  1434. HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(REO_REG_REG_BASE),
  1435. (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000));
  1436. /*
  1437. * When hash based routing is enabled, routing of the rx packet
  1438. * is done based on the following value: 1 _ _ _ _ The last 4
  1439. * bits are based on hash[3:0]. This means the possible values
  1440. * are 0x10 to 0x1f. This value is used to look-up the
  1441. * ring ID configured in Destination_Ring_Ctrl_IX_* register.
  1442. * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3
  1443. * registers need to be configured to set-up the 16 entries to
  1444. * map the hash values to a ring number. There are 3 bits per
  1445. * hash entry – which are mapped as follows:
  1446. * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI),
  1447. * 7: NOT_USED.
  1448. */
  1449. if (reo_params->rx_hash_enabled) {
  1450. HAL_REG_WRITE(soc,
  1451. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR
  1452. (REO_REG_REG_BASE), reo_params->remap0);
  1453. hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x",
  1454. HAL_REG_READ(soc,
  1455. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(
  1456. REO_REG_REG_BASE)));
  1457. HAL_REG_WRITE(soc,
  1458. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR
  1459. (REO_REG_REG_BASE), reo_params->remap1);
  1460. hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x",
  1461. HAL_REG_READ(soc,
  1462. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
  1463. REO_REG_REG_BASE)));
  1464. HAL_REG_WRITE(soc,
  1465. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR
  1466. (REO_REG_REG_BASE), reo_params->remap2);
  1467. hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x",
  1468. HAL_REG_READ(soc,
  1469. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
  1470. REO_REG_REG_BASE)));
  1471. }
  1472. /* TODO: Check if the following registers shoould be setup by host:
  1473. * AGING_CONTROL
  1474. * HIGH_MEMORY_THRESHOLD
  1475. * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2]
  1476. * GLOBAL_LINK_DESC_COUNT_CTRL
  1477. */
  1478. hal_reo_shared_qaddr_init((hal_soc_handle_t)soc, qref_reset);
  1479. }
  1480. static uint16_t hal_get_rx_max_ba_window_qca5332(int tid)
  1481. {
  1482. return HAL_RX_BA_WINDOW_1024;
  1483. }
  1484. /**
  1485. * hal_qca5332_get_reo_qdesc_size()- Get the reo queue descriptor size
  1486. * from the give Block-Ack window size
  1487. * Return: reo queue descriptor size
  1488. */
  1489. static uint32_t hal_qca5332_get_reo_qdesc_size(uint32_t ba_window_size, int tid)
  1490. {
  1491. /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for
  1492. * NON_QOS_TID until HW issues are resolved.
  1493. */
  1494. if (tid != HAL_NON_QOS_TID)
  1495. ba_window_size = hal_get_rx_max_ba_window_qca5332(tid);
  1496. /* Return descriptor size corresponding to window size of 2 since
  1497. * we set ba_window_size to 2 while setting up REO descriptors as
  1498. * a WAR to get 2k jump exception aggregates are received without
  1499. * a BA session.
  1500. */
  1501. if (ba_window_size <= 1) {
  1502. if (tid != HAL_NON_QOS_TID)
  1503. return sizeof(struct rx_reo_queue) +
  1504. sizeof(struct rx_reo_queue_ext);
  1505. else
  1506. return sizeof(struct rx_reo_queue);
  1507. }
  1508. if (ba_window_size <= 105)
  1509. return sizeof(struct rx_reo_queue) +
  1510. sizeof(struct rx_reo_queue_ext);
  1511. if (ba_window_size <= 210)
  1512. return sizeof(struct rx_reo_queue) +
  1513. (2 * sizeof(struct rx_reo_queue_ext));
  1514. if (ba_window_size <= 256)
  1515. return sizeof(struct rx_reo_queue) +
  1516. (3 * sizeof(struct rx_reo_queue_ext));
  1517. return sizeof(struct rx_reo_queue) +
  1518. (10 * sizeof(struct rx_reo_queue_ext)) +
  1519. sizeof(struct rx_reo_queue_1k);
  1520. }
  1521. /**
  1522. * hal_rx_tlv_msdu_done_copy_get_5332() - Get msdu done copy bit from rx_tlv
  1523. *
  1524. * Returns: msdu done copy bit
  1525. */
  1526. static inline uint32_t hal_rx_tlv_msdu_done_copy_get_5332(uint8_t *buf)
  1527. {
  1528. return HAL_RX_TLV_MSDU_DONE_COPY_GET(buf);
  1529. }
  1530. static void hal_hw_txrx_ops_attach_qca5332(struct hal_soc *hal_soc)
  1531. {
  1532. /* init and setup */
  1533. hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
  1534. hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
  1535. hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
  1536. hal_soc->ops->hal_get_window_address = hal_get_window_address_5332;
  1537. hal_soc->ops->hal_cmem_write = hal_cmem_write_5332;
  1538. /* tx */
  1539. hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_5332;
  1540. hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_5332;
  1541. hal_soc->ops->hal_tx_comp_get_status =
  1542. hal_tx_comp_get_status_generic_be;
  1543. hal_soc->ops->hal_tx_init_cmd_credit_ring =
  1544. hal_tx_init_cmd_credit_ring_5332;
  1545. hal_soc->ops->hal_tx_set_ppe_cmn_cfg = NULL;
  1546. hal_soc->ops->hal_tx_set_ppe_vp_entry = NULL;
  1547. hal_soc->ops->hal_tx_set_ppe_pri2tid = NULL;
  1548. hal_soc->ops->hal_tx_update_ppe_pri2tid = NULL;
  1549. hal_soc->ops->hal_tx_dump_ppe_vp_entry = NULL;
  1550. hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries = NULL;
  1551. hal_soc->ops->hal_tx_enable_pri2tid_map = NULL;
  1552. hal_soc->ops->hal_tx_config_rbm_mapping_be =
  1553. hal_tx_config_rbm_mapping_be_5332;
  1554. /* rx */
  1555. hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be;
  1556. hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
  1557. hal_rx_mon_hw_desc_get_mpdu_status_be;
  1558. hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_5332;
  1559. hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
  1560. hal_rx_proc_phyrx_other_receive_info_tlv_5332;
  1561. hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_5332;
  1562. hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
  1563. hal_rx_dump_mpdu_start_tlv_5332;
  1564. hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_5332;
  1565. hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_5332;
  1566. hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be;
  1567. hal_soc->ops->hal_rx_msdu_start_reception_type_get =
  1568. hal_rx_tlv_reception_type_get_be;
  1569. hal_soc->ops->hal_rx_msdu_end_da_idx_get =
  1570. hal_rx_msdu_end_da_idx_get_be;
  1571. hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
  1572. hal_rx_msdu_desc_info_get_ptr_5332;
  1573. hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
  1574. hal_rx_link_desc_msdu0_ptr_5332;
  1575. hal_soc->ops->hal_reo_status_get_header =
  1576. hal_reo_status_get_header_5332;
  1577. hal_soc->ops->hal_rx_status_get_tlv_info =
  1578. hal_rx_status_get_tlv_info_wrapper_be;
  1579. hal_soc->ops->hal_rx_wbm_err_info_get =
  1580. hal_rx_wbm_err_info_get_generic_be;
  1581. hal_soc->ops->hal_tx_set_pcp_tid_map =
  1582. hal_tx_set_pcp_tid_map_generic_be;
  1583. hal_soc->ops->hal_tx_update_pcp_tid_map =
  1584. hal_tx_update_pcp_tid_generic_be;
  1585. hal_soc->ops->hal_tx_set_tidmap_prty =
  1586. hal_tx_update_tidmap_prty_generic_be;
  1587. hal_soc->ops->hal_rx_get_rx_fragment_number =
  1588. hal_rx_get_rx_fragment_number_be,
  1589. hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
  1590. hal_rx_tlv_da_is_mcbc_get_be;
  1591. hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err =
  1592. hal_rx_tlv_is_tkip_mic_err_get_be;
  1593. hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
  1594. hal_rx_tlv_sa_is_valid_get_be;
  1595. hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be;
  1596. hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_be;
  1597. hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
  1598. hal_rx_tlv_l3_hdr_padding_get_be;
  1599. hal_soc->ops->hal_rx_encryption_info_valid =
  1600. hal_rx_encryption_info_valid_be;
  1601. hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be;
  1602. hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
  1603. hal_rx_tlv_first_msdu_get_be;
  1604. hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
  1605. hal_rx_tlv_da_is_valid_get_be;
  1606. hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
  1607. hal_rx_tlv_last_msdu_get_be;
  1608. hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
  1609. hal_rx_get_mpdu_mac_ad4_valid_be;
  1610. hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
  1611. hal_rx_mpdu_start_sw_peer_id_get_be;
  1612. hal_soc->ops->hal_rx_tlv_peer_meta_data_get =
  1613. hal_rx_mpdu_peer_meta_data_get_be;
  1614. hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be;
  1615. hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be;
  1616. hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
  1617. hal_rx_get_mpdu_frame_control_valid_be;
  1618. hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be;
  1619. hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be;
  1620. hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be;
  1621. hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be;
  1622. hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
  1623. hal_rx_get_mpdu_sequence_control_valid_be;
  1624. hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be;
  1625. hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be;
  1626. hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
  1627. hal_rx_hw_desc_get_ppduid_get_be;
  1628. hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
  1629. hal_rx_mpdu_start_mpdu_qos_control_valid_get_be;
  1630. hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
  1631. hal_rx_msdu_end_sa_sw_peer_id_get_be;
  1632. hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
  1633. hal_rx_msdu0_buffer_addr_lsb_5332;
  1634. hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
  1635. hal_rx_msdu_desc_info_ptr_get_5332;
  1636. hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_5332;
  1637. hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_5332;
  1638. hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be;
  1639. hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be;
  1640. hal_soc->ops->hal_rx_get_mac_addr2_valid =
  1641. hal_rx_get_mac_addr2_valid_be;
  1642. hal_soc->ops->hal_rx_get_filter_category =
  1643. hal_rx_get_filter_category_be;
  1644. hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be;
  1645. hal_soc->ops->hal_reo_config = hal_reo_config_5332;
  1646. hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be;
  1647. hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
  1648. hal_rx_msdu_flow_idx_invalid_be;
  1649. hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
  1650. hal_rx_msdu_flow_idx_timeout_be;
  1651. hal_soc->ops->hal_rx_msdu_fse_metadata_get =
  1652. hal_rx_msdu_fse_metadata_get_be;
  1653. hal_soc->ops->hal_rx_msdu_cce_match_get =
  1654. hal_rx_msdu_cce_match_get_be;
  1655. hal_soc->ops->hal_rx_msdu_cce_metadata_get =
  1656. hal_rx_msdu_cce_metadata_get_be;
  1657. hal_soc->ops->hal_rx_msdu_get_flow_params =
  1658. hal_rx_msdu_get_flow_params_be;
  1659. hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_be;
  1660. hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be;
  1661. #if defined(QCA_WIFI_QCA5332) && defined(WLAN_CFR_ENABLE) && \
  1662. defined(WLAN_ENH_CFR_ENABLE)
  1663. hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_5332;
  1664. hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_5332;
  1665. #else
  1666. hal_soc->ops->hal_rx_get_bb_info = NULL;
  1667. hal_soc->ops->hal_rx_get_rtt_info = NULL;
  1668. #endif
  1669. /* rx - msdu fast path info fields */
  1670. hal_soc->ops->hal_rx_msdu_packet_metadata_get =
  1671. hal_rx_msdu_packet_metadata_get_generic_be;
  1672. hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
  1673. hal_rx_mpdu_start_tlv_tag_valid_be;
  1674. hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get =
  1675. hal_rx_wbm_err_msdu_continuation_get_5332;
  1676. /* rx - TLV struct offsets */
  1677. hal_soc->ops->hal_rx_msdu_end_offset_get =
  1678. hal_rx_msdu_end_offset_get_generic;
  1679. hal_soc->ops->hal_rx_mpdu_start_offset_get =
  1680. hal_rx_mpdu_start_offset_get_generic;
  1681. #ifndef NO_RX_PKT_HDR_TLV
  1682. hal_soc->ops->hal_rx_pkt_tlv_offset_get =
  1683. hal_rx_pkt_tlv_offset_get_generic;
  1684. #endif
  1685. hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_5332;
  1686. hal_soc->ops->hal_rx_flow_get_tuple_info =
  1687. hal_rx_flow_get_tuple_info_be;
  1688. hal_soc->ops->hal_rx_flow_delete_entry =
  1689. hal_rx_flow_delete_entry_be;
  1690. hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be;
  1691. hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
  1692. hal_compute_reo_remap_ix2_ix3_5332;
  1693. hal_soc->ops->hal_rx_msdu_get_reo_destination_indication =
  1694. hal_rx_msdu_get_reo_destination_indication_be;
  1695. hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be;
  1696. hal_soc->ops->hal_rx_msdu_is_wlan_mcast =
  1697. hal_rx_msdu_is_wlan_mcast_generic_be;
  1698. hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_5332;
  1699. hal_soc->ops->hal_rx_tlv_decap_format_get =
  1700. hal_rx_tlv_decap_format_get_be;
  1701. #ifdef RECEIVE_OFFLOAD
  1702. hal_soc->ops->hal_rx_tlv_get_offload_info =
  1703. hal_rx_tlv_get_offload_info_be;
  1704. hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be;
  1705. hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be;
  1706. #endif
  1707. hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get =
  1708. hal_rx_attn_phy_ppdu_id_get_be;
  1709. hal_soc->ops->hal_rx_tlv_msdu_done_get =
  1710. hal_rx_tlv_msdu_done_copy_get_5332;
  1711. hal_soc->ops->hal_rx_tlv_msdu_len_get =
  1712. hal_rx_msdu_start_msdu_len_get_be;
  1713. hal_soc->ops->hal_rx_get_frame_ctrl_field =
  1714. hal_rx_get_frame_ctrl_field_be;
  1715. hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be;
  1716. hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get =
  1717. hal_rx_mpdu_info_ampdu_flag_get_be;
  1718. hal_soc->ops->hal_rx_tlv_msdu_len_set =
  1719. hal_rx_msdu_start_msdu_len_set_be;
  1720. hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be;
  1721. hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be;
  1722. hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_be;
  1723. hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be;
  1724. hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be;
  1725. hal_soc->ops->hal_rx_tlv_decrypt_err_get =
  1726. hal_rx_tlv_decrypt_err_get_be;
  1727. hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be;
  1728. hal_soc->ops->hal_rx_tlv_get_is_decrypted =
  1729. hal_rx_tlv_get_is_decrypted_be;
  1730. hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_be;
  1731. hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be;
  1732. hal_soc->ops->hal_rx_priv_info_set_in_tlv =
  1733. hal_rx_priv_info_set_in_tlv_be;
  1734. hal_soc->ops->hal_rx_priv_info_get_from_tlv =
  1735. hal_rx_priv_info_get_from_tlv_be;
  1736. hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be;
  1737. hal_soc->ops->hal_reo_setup = hal_reo_setup_5332;
  1738. #ifdef REO_SHARED_QREF_TABLE_EN
  1739. hal_soc->ops->hal_reo_shared_qaddr_setup = hal_reo_shared_qaddr_setup_be;
  1740. hal_soc->ops->hal_reo_shared_qaddr_init = hal_reo_shared_qaddr_init_be;
  1741. hal_soc->ops->hal_reo_shared_qaddr_detach = hal_reo_shared_qaddr_detach_be;
  1742. hal_soc->ops->hal_reo_shared_qaddr_write = hal_reo_shared_qaddr_write_be;
  1743. hal_soc->ops->hal_reo_shared_qaddr_cache_clear = hal_reo_shared_qaddr_cache_clear_be;
  1744. #endif
  1745. /* Overwrite the default BE ops */
  1746. hal_soc->ops->hal_get_rx_max_ba_window =
  1747. hal_get_rx_max_ba_window_qca5332;
  1748. hal_soc->ops->hal_get_reo_qdesc_size = hal_qca5332_get_reo_qdesc_size;
  1749. /* TX MONITOR */
  1750. #ifdef QCA_MONITOR_2_0_SUPPORT
  1751. hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv =
  1752. hal_txmon_is_mon_buf_addr_tlv_generic_be;
  1753. hal_soc->ops->hal_txmon_populate_packet_info =
  1754. hal_txmon_populate_packet_info_generic_be;
  1755. hal_soc->ops->hal_txmon_status_parse_tlv =
  1756. hal_txmon_status_parse_tlv_generic_be;
  1757. hal_soc->ops->hal_txmon_status_get_num_users =
  1758. hal_txmon_status_get_num_users_generic_be;
  1759. #endif /* QCA_MONITOR_2_0_SUPPORT */
  1760. hal_soc->ops->hal_compute_reo_remap_ix0 = NULL;
  1761. hal_soc->ops->hal_tx_vdev_mismatch_routing_set =
  1762. hal_tx_vdev_mismatch_routing_set_generic_be;
  1763. hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set =
  1764. hal_tx_mcast_mlo_reinject_routing_set_generic_be;
  1765. hal_soc->ops->hal_get_ba_aging_timeout =
  1766. hal_get_ba_aging_timeout_be_generic;
  1767. hal_soc->ops->hal_setup_link_idle_list =
  1768. hal_setup_link_idle_list_generic_be;
  1769. hal_soc->ops->hal_cookie_conversion_reg_cfg_be =
  1770. hal_cookie_conversion_reg_cfg_generic_be;
  1771. hal_soc->ops->hal_set_ba_aging_timeout =
  1772. hal_set_ba_aging_timeout_be_generic;
  1773. hal_soc->ops->hal_tx_populate_bank_register =
  1774. hal_tx_populate_bank_register_be;
  1775. hal_soc->ops->hal_tx_vdev_mcast_ctrl_set =
  1776. hal_tx_vdev_mcast_ctrl_set_be;
  1777. };
  1778. struct hal_hw_srng_config hw_srng_table_5332[] = {
  1779. /* TODO: max_rings can populated by querying HW capabilities */
  1780. { /* REO_DST */
  1781. .start_ring_id = HAL_SRNG_REO2SW1,
  1782. .max_rings = 8,
  1783. .entry_size = sizeof(struct reo_destination_ring) >> 2,
  1784. .lmac_ring = FALSE,
  1785. .ring_dir = HAL_SRNG_DST_RING,
  1786. .reg_start = {
  1787. HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
  1788. REO_REG_REG_BASE),
  1789. HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
  1790. REO_REG_REG_BASE)
  1791. },
  1792. .reg_size = {
  1793. HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
  1794. HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
  1795. HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
  1796. HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
  1797. },
  1798. .max_size =
  1799. HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1800. HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
  1801. },
  1802. { /* REO_EXCEPTION */
  1803. /* Designating REO2SW0 ring as exception ring. This ring is
  1804. * similar to other REO2SW rings though it is named as REO2SW0.
  1805. * Any of theREO2SW rings can be used as exception ring.
  1806. */
  1807. .start_ring_id = HAL_SRNG_REO2SW0,
  1808. .max_rings = 1,
  1809. .entry_size = sizeof(struct reo_destination_ring) >> 2,
  1810. .lmac_ring = FALSE,
  1811. .ring_dir = HAL_SRNG_DST_RING,
  1812. .reg_start = {
  1813. HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(
  1814. REO_REG_REG_BASE),
  1815. HWIO_REO_R2_REO2SW0_RING_HP_ADDR(
  1816. REO_REG_REG_BASE)
  1817. },
  1818. /* Single ring - provide ring size if multiple rings of this
  1819. * type are supported
  1820. */
  1821. .reg_size = {},
  1822. .max_size =
  1823. HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >>
  1824. HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT,
  1825. },
  1826. { /* REO_REINJECT */
  1827. .start_ring_id = HAL_SRNG_SW2REO,
  1828. .max_rings = 4,
  1829. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  1830. .lmac_ring = FALSE,
  1831. .ring_dir = HAL_SRNG_SRC_RING,
  1832. .reg_start = {
  1833. HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
  1834. REO_REG_REG_BASE),
  1835. HWIO_REO_R2_SW2REO_RING_HP_ADDR(
  1836. REO_REG_REG_BASE)
  1837. },
  1838. /* Single ring - provide ring size if multiple rings of this
  1839. * type are supported
  1840. */
  1841. .reg_size = {
  1842. HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(0) -
  1843. HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(0),
  1844. HWIO_REO_R2_SW2REO1_RING_HP_ADDR(0) -
  1845. HWIO_REO_R2_SW2REO_RING_HP_ADDR(0)
  1846. },
  1847. .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
  1848. HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
  1849. },
  1850. { /* REO_CMD */
  1851. .start_ring_id = HAL_SRNG_REO_CMD,
  1852. .max_rings = 1,
  1853. .entry_size = (sizeof(struct tlv_32_hdr) +
  1854. sizeof(struct reo_get_queue_stats)) >> 2,
  1855. .lmac_ring = FALSE,
  1856. .ring_dir = HAL_SRNG_SRC_RING,
  1857. .reg_start = {
  1858. HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
  1859. REO_REG_REG_BASE),
  1860. HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
  1861. REO_REG_REG_BASE),
  1862. },
  1863. /* Single ring - provide ring size if multiple rings of this
  1864. * type are supported
  1865. */
  1866. .reg_size = {},
  1867. .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
  1868. HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
  1869. },
  1870. { /* REO_STATUS */
  1871. .start_ring_id = HAL_SRNG_REO_STATUS,
  1872. .max_rings = 1,
  1873. .entry_size = (sizeof(struct tlv_32_hdr) +
  1874. sizeof(struct reo_get_queue_stats_status)) >> 2,
  1875. .lmac_ring = FALSE,
  1876. .ring_dir = HAL_SRNG_DST_RING,
  1877. .reg_start = {
  1878. HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
  1879. REO_REG_REG_BASE),
  1880. HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
  1881. REO_REG_REG_BASE),
  1882. },
  1883. /* Single ring - provide ring size if multiple rings of this
  1884. * type are supported
  1885. */
  1886. .reg_size = {},
  1887. .max_size =
  1888. HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
  1889. HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
  1890. },
  1891. { /* TCL_DATA */
  1892. .start_ring_id = HAL_SRNG_SW2TCL1,
  1893. .max_rings = 6,
  1894. .entry_size = sizeof(struct tcl_data_cmd) >> 2,
  1895. .lmac_ring = FALSE,
  1896. .ring_dir = HAL_SRNG_SRC_RING,
  1897. .reg_start = {
  1898. HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
  1899. MAC_TCL_REG_REG_BASE),
  1900. HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
  1901. MAC_TCL_REG_REG_BASE),
  1902. },
  1903. .reg_size = {
  1904. HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
  1905. HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
  1906. HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
  1907. HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
  1908. },
  1909. .max_size =
  1910. HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1911. HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
  1912. },
  1913. { /* TCL_CMD/CREDIT */
  1914. /* qca8074v2 and qca5332 uses this ring for data commands */
  1915. .start_ring_id = HAL_SRNG_SW2TCL_CMD,
  1916. .max_rings = 1,
  1917. .entry_size = sizeof(struct tcl_data_cmd) >> 2,
  1918. .lmac_ring = FALSE,
  1919. .ring_dir = HAL_SRNG_SRC_RING,
  1920. .reg_start = {
  1921. HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(
  1922. MAC_TCL_REG_REG_BASE),
  1923. HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(
  1924. MAC_TCL_REG_REG_BASE),
  1925. },
  1926. /* Single ring - provide ring size if multiple rings of this
  1927. * type are supported
  1928. */
  1929. .reg_size = {},
  1930. .max_size =
  1931. HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >>
  1932. HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT,
  1933. },
  1934. { /* TCL_STATUS */
  1935. .start_ring_id = HAL_SRNG_TCL_STATUS,
  1936. .max_rings = 1,
  1937. .entry_size = (sizeof(struct tlv_32_hdr) +
  1938. sizeof(struct tcl_status_ring)) >> 2,
  1939. .lmac_ring = FALSE,
  1940. .ring_dir = HAL_SRNG_DST_RING,
  1941. .reg_start = {
  1942. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
  1943. MAC_TCL_REG_REG_BASE),
  1944. HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
  1945. MAC_TCL_REG_REG_BASE),
  1946. },
  1947. /* Single ring - provide ring size if multiple rings of this
  1948. * type are supported
  1949. */
  1950. .reg_size = {},
  1951. .max_size =
  1952. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1953. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
  1954. },
  1955. { /* CE_SRC */
  1956. .start_ring_id = HAL_SRNG_CE_0_SRC,
  1957. .max_rings = 16,
  1958. .entry_size = sizeof(struct ce_src_desc) >> 2,
  1959. .lmac_ring = FALSE,
  1960. .ring_dir = HAL_SRNG_SRC_RING,
  1961. .reg_start = {
  1962. HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(
  1963. WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE),
  1964. HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(
  1965. WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE),
  1966. },
  1967. .reg_size = {
  1968. WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
  1969. WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
  1970. WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
  1971. WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
  1972. },
  1973. .max_size =
  1974. HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >>
  1975. HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT,
  1976. },
  1977. { /* CE_DST */
  1978. .start_ring_id = HAL_SRNG_CE_0_DST,
  1979. .max_rings = 16,
  1980. .entry_size = 8 >> 2,
  1981. /*TODO: entry_size above should actually be
  1982. * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
  1983. * of struct ce_dst_desc in HW header files
  1984. */
  1985. .lmac_ring = FALSE,
  1986. .ring_dir = HAL_SRNG_SRC_RING,
  1987. .reg_start = {
  1988. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
  1989. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
  1990. HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
  1991. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
  1992. },
  1993. .reg_size = {
  1994. WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
  1995. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
  1996. WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
  1997. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
  1998. },
  1999. .max_size =
  2000. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
  2001. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
  2002. },
  2003. { /* CE_DST_STATUS */
  2004. .start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
  2005. .max_rings = 16,
  2006. .entry_size = sizeof(struct ce_stat_desc) >> 2,
  2007. .lmac_ring = FALSE,
  2008. .ring_dir = HAL_SRNG_DST_RING,
  2009. .reg_start = {
  2010. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
  2011. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
  2012. HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
  2013. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
  2014. },
  2015. /* TODO: check destination status ring registers */
  2016. .reg_size = {
  2017. WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
  2018. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
  2019. WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
  2020. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
  2021. },
  2022. .max_size =
  2023. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
  2024. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
  2025. },
  2026. { /* WBM_IDLE_LINK */
  2027. .start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
  2028. .max_rings = 1,
  2029. .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
  2030. .lmac_ring = FALSE,
  2031. .ring_dir = HAL_SRNG_SRC_RING,
  2032. .reg_start = {
  2033. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
  2034. HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE),
  2035. },
  2036. /* Single ring - provide ring size if multiple rings of this
  2037. * type are supported
  2038. */
  2039. .reg_size = {},
  2040. .max_size =
  2041. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
  2042. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
  2043. },
  2044. { /* SW2WBM_RELEASE */
  2045. .start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
  2046. .max_rings = 1,
  2047. .entry_size = sizeof(struct wbm_release_ring) >> 2,
  2048. .lmac_ring = FALSE,
  2049. .ring_dir = HAL_SRNG_SRC_RING,
  2050. .reg_start = {
  2051. HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
  2052. HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE),
  2053. },
  2054. /* Single ring - provide ring size if multiple rings of this
  2055. * type are supported
  2056. */
  2057. .reg_size = {},
  2058. .max_size =
  2059. HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
  2060. HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
  2061. },
  2062. { /* WBM2SW_RELEASE */
  2063. .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
  2064. .max_rings = 8,
  2065. .entry_size = sizeof(struct wbm_release_ring) >> 2,
  2066. .lmac_ring = FALSE,
  2067. .ring_dir = HAL_SRNG_DST_RING,
  2068. .reg_start = {
  2069. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(
  2070. WBM_REG_REG_BASE),
  2071. HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(
  2072. WBM_REG_REG_BASE),
  2073. },
  2074. .reg_size = {
  2075. HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(
  2076. WBM_REG_REG_BASE) -
  2077. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(
  2078. WBM_REG_REG_BASE),
  2079. HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(
  2080. WBM_REG_REG_BASE) -
  2081. HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(
  2082. WBM_REG_REG_BASE),
  2083. },
  2084. .max_size =
  2085. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
  2086. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
  2087. },
  2088. { /* RXDMA_BUF */
  2089. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
  2090. #ifdef IPA_OFFLOAD
  2091. .max_rings = 3,
  2092. #else
  2093. .max_rings = 3,
  2094. #endif
  2095. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  2096. .lmac_ring = TRUE,
  2097. .ring_dir = HAL_SRNG_SRC_RING,
  2098. /* reg_start is not set because LMAC rings are not accessed
  2099. * from host
  2100. */
  2101. .reg_start = {},
  2102. .reg_size = {},
  2103. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2104. },
  2105. { /* RXDMA_DST */
  2106. .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
  2107. .max_rings = 0,
  2108. .entry_size = 0/*sizeof(struct reo_entrance_ring) >> 2*/,
  2109. .lmac_ring = TRUE,
  2110. .ring_dir = HAL_SRNG_DST_RING,
  2111. /* reg_start is not set because LMAC rings are not accessed
  2112. * from host
  2113. */
  2114. .reg_start = {},
  2115. .reg_size = {},
  2116. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2117. },
  2118. #ifdef QCA_MONITOR_2_0_SUPPORT
  2119. { /* RXDMA_MONITOR_BUF */
  2120. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
  2121. .max_rings = 1,
  2122. .entry_size = sizeof(struct mon_ingress_ring) >> 2,
  2123. .lmac_ring = TRUE,
  2124. .ring_dir = HAL_SRNG_SRC_RING,
  2125. /* reg_start is not set because LMAC rings are not accessed
  2126. * from host
  2127. */
  2128. .reg_start = {},
  2129. .reg_size = {},
  2130. .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
  2131. },
  2132. #else
  2133. {},
  2134. #endif
  2135. { /* RXDMA_MONITOR_STATUS */
  2136. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
  2137. .max_rings = 0,
  2138. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  2139. .lmac_ring = TRUE,
  2140. .ring_dir = HAL_SRNG_SRC_RING,
  2141. /* reg_start is not set because LMAC rings are not accessed
  2142. * from host
  2143. */
  2144. .reg_start = {},
  2145. .reg_size = {},
  2146. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2147. },
  2148. #ifdef QCA_MONITOR_2_0_SUPPORT
  2149. { /* RXDMA_MONITOR_DST */
  2150. .start_ring_id = HAL_SRNG_WMAC1_RXMON2SW0,
  2151. .max_rings = 2,
  2152. .entry_size = sizeof(struct mon_destination_ring) >> 2,
  2153. .lmac_ring = TRUE,
  2154. .ring_dir = HAL_SRNG_DST_RING,
  2155. /* reg_start is not set because LMAC rings are not accessed
  2156. * from host
  2157. */
  2158. .reg_start = {},
  2159. .reg_size = {},
  2160. .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
  2161. },
  2162. #else
  2163. {},
  2164. #endif
  2165. { /* RXDMA_MONITOR_DESC */
  2166. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
  2167. .max_rings = 0,
  2168. .entry_size = 0/*sizeof(struct sw_monitor_ring) >> 2*/,
  2169. .lmac_ring = TRUE,
  2170. .ring_dir = HAL_SRNG_DST_RING,
  2171. /* reg_start is not set because LMAC rings are not accessed
  2172. * from host
  2173. */
  2174. .reg_start = {},
  2175. .reg_size = {},
  2176. .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
  2177. },
  2178. { /* DIR_BUF_RX_DMA_SRC */
  2179. .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
  2180. /* one ring for spectral and one ring for cfr */
  2181. .max_rings = 2,
  2182. .entry_size = 2,
  2183. .lmac_ring = TRUE,
  2184. .ring_dir = HAL_SRNG_SRC_RING,
  2185. /* reg_start is not set because LMAC rings are not accessed
  2186. * from host
  2187. */
  2188. .reg_start = {},
  2189. .reg_size = {},
  2190. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2191. },
  2192. #ifdef WLAN_FEATURE_CIF_CFR
  2193. { /* WIFI_POS_SRC */
  2194. .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
  2195. .max_rings = 1,
  2196. .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2,
  2197. .lmac_ring = TRUE,
  2198. .ring_dir = HAL_SRNG_SRC_RING,
  2199. /* reg_start is not set because LMAC rings are not accessed
  2200. * from host
  2201. */
  2202. .reg_start = {},
  2203. .reg_size = {},
  2204. .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
  2205. },
  2206. #endif
  2207. /* PPE rings are not present in Miami. Added dummy entries to preserve
  2208. * Array Index
  2209. */
  2210. /* REO2PPE */
  2211. {},
  2212. /* PPE2TCL */
  2213. {},
  2214. /* PPE_RELEASE */
  2215. {},
  2216. #ifdef QCA_MONITOR_2_0_SUPPORT
  2217. { /* TX_MONITOR_BUF */
  2218. .start_ring_id = HAL_SRNG_SW2TXMON_BUF0,
  2219. .max_rings = 1,
  2220. .entry_size = sizeof(struct mon_ingress_ring) >> 2,
  2221. .lmac_ring = TRUE,
  2222. .ring_dir = HAL_SRNG_SRC_RING,
  2223. /* reg_start is not set because LMAC rings are not accessed
  2224. * from host
  2225. */
  2226. .reg_start = {},
  2227. .reg_size = {},
  2228. .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
  2229. },
  2230. { /* TX_MONITOR_DST */
  2231. .start_ring_id = HAL_SRNG_WMAC1_TXMON2SW0,
  2232. .max_rings = 2,
  2233. .entry_size = sizeof(struct mon_destination_ring) >> 2,
  2234. .lmac_ring = TRUE,
  2235. .ring_dir = HAL_SRNG_DST_RING,
  2236. /* reg_start is not set because LMAC rings are not accessed
  2237. * from host
  2238. */
  2239. .reg_start = {},
  2240. .reg_size = {},
  2241. .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
  2242. },
  2243. #else
  2244. {},
  2245. {},
  2246. #endif
  2247. { /* SW2RXDMA */
  2248. .start_ring_id = HAL_SRNG_SW2RXDMA_BUF0,
  2249. .max_rings = 3,
  2250. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  2251. .lmac_ring = TRUE,
  2252. .ring_dir = HAL_SRNG_SRC_RING,
  2253. /* reg_start is not set because LMAC rings are not accessed
  2254. * from host
  2255. */
  2256. .reg_start = {},
  2257. .reg_size = {},
  2258. .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
  2259. .dmac_cmn_ring = TRUE,
  2260. },
  2261. };
  2262. /**
  2263. * hal_srng_hw_reg_offset_init_qca5332() - Initialize the HW srng reg offset
  2264. * applicable only for qca5332
  2265. * @hal_soc: HAL Soc handle
  2266. *
  2267. * Return: None
  2268. */
  2269. static inline void hal_srng_hw_reg_offset_init_qca5332(struct hal_soc *hal_soc)
  2270. {
  2271. int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset;
  2272. hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB),
  2273. hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB),
  2274. hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA),
  2275. hw_reg_offset[DST_PRODUCER_INT2_SETUP] =
  2276. REG_OFFSET(DST, PRODUCER_INT2_SETUP);
  2277. }
  2278. /**
  2279. * hal_qca5332_attach()- Attach 5332 target specific hal_soc ops,
  2280. * offset and srng table
  2281. * Return: void
  2282. */
  2283. void hal_qca5332_attach(struct hal_soc *hal_soc)
  2284. {
  2285. hal_soc->hw_srng_table = hw_srng_table_5332;
  2286. hal_srng_hw_reg_offset_init_generic(hal_soc);
  2287. hal_srng_hw_reg_offset_init_qca5332(hal_soc);
  2288. hal_hw_txrx_default_ops_attach_be(hal_soc);
  2289. hal_hw_txrx_ops_attach_qca5332(hal_soc);
  2290. hal_soc->dmac_cmn_src_rxbuf_ring = true;
  2291. }