hal_li_generic_api.h 80 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_LI_GENERIC_API_H_
  20. #define _HAL_LI_GENERIC_API_H_
  21. #include "hal_tx.h"
  22. #include "hal_li_tx.h"
  23. #include "hal_li_rx.h"
  24. #define HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc) \
  25. (_HAL_MS((*_OFFSET_TO_WORD_PTR(wbm_desc, \
  26. WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET)), \
  27. WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK, \
  28. WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB))
  29. #define HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc) \
  30. (_HAL_MS((*_OFFSET_TO_WORD_PTR(wbm_desc, \
  31. WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET)), \
  32. WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK, \
  33. WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB))
  34. #define HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc) \
  35. (((*(((uint32_t *)wbm_desc) + \
  36. (WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET >> 2))) & \
  37. WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK) >> \
  38. WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB)
  39. #define HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc) \
  40. (((*(((uint32_t *)wbm_desc) + \
  41. (WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET >> 2))) & \
  42. WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK) >> \
  43. WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB)
  44. /**
  45. * hal_rx_wbm_err_info_get_generic_li(): Retrieves WBM error code and reason and
  46. * save it to hal_wbm_err_desc_info structure passed by caller
  47. * @wbm_desc: wbm ring descriptor
  48. * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter.
  49. * Return: void
  50. */
  51. static inline
  52. void hal_rx_wbm_err_info_get_generic_li(void *wbm_desc,
  53. void *wbm_er_info1)
  54. {
  55. struct hal_wbm_err_desc_info *wbm_er_info =
  56. (struct hal_wbm_err_desc_info *)wbm_er_info1;
  57. wbm_er_info->wbm_err_src = HAL_WBM2SW_RELEASE_SRC_GET(wbm_desc);
  58. wbm_er_info->reo_psh_rsn = HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc);
  59. wbm_er_info->reo_err_code = HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc);
  60. wbm_er_info->rxdma_psh_rsn = HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc);
  61. wbm_er_info->rxdma_err_code = HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc);
  62. }
  63. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
  64. static inline void
  65. hal_tx_comp_get_buffer_timestamp_li(void *desc,
  66. struct hal_tx_completion_status *ts)
  67. {
  68. ts->buffer_timestamp = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4,
  69. BUFFER_TIMESTAMP);
  70. }
  71. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY || WLAN_CONFIG_TX_DELAY */
  72. static inline void
  73. hal_tx_comp_get_buffer_timestamp_li(void *desc,
  74. struct hal_tx_completion_status *ts)
  75. {
  76. }
  77. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY || WLAN_CONFIG_TX_DELAY */
  78. #ifdef QCA_UNDECODED_METADATA_SUPPORT
  79. static inline void
  80. hal_rx_get_phyrx_abort(struct hal_soc *hal, void *rx_tlv,
  81. struct hal_rx_ppdu_info *ppdu_info){
  82. switch (hal->target_type) {
  83. case TARGET_TYPE_QCN9000:
  84. ppdu_info->rx_status.phyrx_abort =
  85. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2,
  86. PHYRX_ABORT_REQUEST_INFO_VALID);
  87. ppdu_info->rx_status.phyrx_abort_reason =
  88. HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_11,
  89. PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON);
  90. break;
  91. default:
  92. break;
  93. }
  94. }
  95. static inline void
  96. hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info *ppdu_info,
  97. uint8_t *ht_sig_info)
  98. {
  99. ppdu_info->rx_status.ht_length =
  100. HAL_RX_GET(ht_sig_info, HT_SIG_INFO_0, LENGTH);
  101. ppdu_info->rx_status.smoothing =
  102. HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, SMOOTHING);
  103. ppdu_info->rx_status.not_sounding =
  104. HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, NOT_SOUNDING);
  105. ppdu_info->rx_status.aggregation =
  106. HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, AGGREGATION);
  107. ppdu_info->rx_status.ht_stbc =
  108. HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, STBC);
  109. ppdu_info->rx_status.ht_crc =
  110. HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, CRC);
  111. }
  112. static inline void
  113. hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info *ppdu_info,
  114. uint8_t *l_sig_a_info)
  115. {
  116. ppdu_info->rx_status.l_sig_length =
  117. HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, LENGTH);
  118. ppdu_info->rx_status.l_sig_a_parity =
  119. HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, PARITY);
  120. ppdu_info->rx_status.l_sig_a_pkt_type =
  121. HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, PKT_TYPE);
  122. ppdu_info->rx_status.l_sig_a_implicit_sounding =
  123. HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0,
  124. CAPTURED_IMPLICIT_SOUNDING);
  125. }
  126. static inline void
  127. hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info *ppdu_info,
  128. uint8_t *vht_sig_a_info)
  129. {
  130. ppdu_info->rx_status.vht_no_txop_ps =
  131. HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0,
  132. TXOP_PS_NOT_ALLOWED);
  133. ppdu_info->rx_status.vht_crc =
  134. HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, CRC);
  135. }
  136. static inline void
  137. hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info *ppdu_info,
  138. uint8_t *he_sig_a_su_info) {
  139. ppdu_info->rx_status.he_crc =
  140. HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, CRC);
  141. }
  142. static inline void
  143. hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info *ppdu_info,
  144. uint8_t *he_sig_a_mu_dl_info) {
  145. ppdu_info->rx_status.he_crc =
  146. HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, CRC);
  147. }
  148. #else
  149. static inline void
  150. hal_rx_get_phyrx_abort(struct hal_soc *hal, void *rx_tlv,
  151. struct hal_rx_ppdu_info *ppdu_info)
  152. {
  153. }
  154. static inline void
  155. hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info *ppdu_info,
  156. uint8_t *ht_sig_info)
  157. {
  158. }
  159. static inline void
  160. hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info *ppdu_info,
  161. uint8_t *l_sig_a_info)
  162. {
  163. }
  164. static inline void
  165. hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info *ppdu_info,
  166. uint8_t *vht_sig_a_info)
  167. {
  168. }
  169. static inline void
  170. hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info *ppdu_info,
  171. uint8_t *he_sig_a_su_info)
  172. {
  173. }
  174. static inline void
  175. hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info *ppdu_info,
  176. uint8_t *he_sig_a_mu_dl_info)
  177. {
  178. }
  179. #endif /* QCA_UNDECODED_METADATA_SUPPORT */
  180. /**
  181. * hal_tx_comp_get_status() - TQM Release reason
  182. * @hal_desc: completion ring Tx status
  183. *
  184. * This function will parse the WBM completion descriptor and populate in
  185. * HAL structure
  186. *
  187. * Return: none
  188. */
  189. static inline void
  190. hal_tx_comp_get_status_generic_li(void *desc, void *ts1,
  191. struct hal_soc *hal)
  192. {
  193. uint8_t rate_stats_valid = 0;
  194. uint32_t rate_stats = 0;
  195. struct hal_tx_completion_status *ts =
  196. (struct hal_tx_completion_status *)ts1;
  197. ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3,
  198. TQM_STATUS_NUMBER);
  199. ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4,
  200. ACK_FRAME_RSSI);
  201. ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU);
  202. ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU);
  203. ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4,
  204. MSDU_PART_OF_AMSDU);
  205. ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID);
  206. ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID);
  207. ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3,
  208. TRANSMIT_COUNT);
  209. rate_stats = HAL_TX_DESC_GET(desc, HAL_TX_COMP, TX_RATE_STATS);
  210. rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0,
  211. TX_RATE_STATS_INFO_VALID, rate_stats);
  212. ts->valid = rate_stats_valid;
  213. if (rate_stats_valid) {
  214. ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW,
  215. rate_stats);
  216. ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0,
  217. TRANSMIT_PKT_TYPE, rate_stats);
  218. ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0,
  219. TRANSMIT_STBC, rate_stats);
  220. ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC,
  221. rate_stats);
  222. ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI,
  223. rate_stats);
  224. ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS,
  225. rate_stats);
  226. ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION,
  227. rate_stats);
  228. ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU,
  229. rate_stats);
  230. }
  231. ts->release_src = hal_tx_comp_get_buffer_source(
  232. hal_soc_to_hal_soc_handle(hal),
  233. desc);
  234. ts->status = hal_tx_comp_get_release_reason(
  235. desc,
  236. hal_soc_to_hal_soc_handle(hal));
  237. ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6,
  238. TX_RATE_STATS_INFO_TX_RATE_STATS);
  239. hal_tx_comp_get_buffer_timestamp_li(desc, ts);
  240. }
  241. /**
  242. * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor
  243. * @desc: Handle to Tx Descriptor
  244. * @paddr: Physical Address
  245. * @pool_id: Return Buffer Manager ID
  246. * @desc_id: Descriptor ID
  247. * @type: 0 - Address points to a MSDU buffer
  248. * 1 - Address points to MSDU extension descriptor
  249. *
  250. * Return: void
  251. */
  252. static inline void
  253. hal_tx_desc_set_buf_addr_generic_li(void *desc, dma_addr_t paddr,
  254. uint8_t rbm_id, uint32_t desc_id,
  255. uint8_t type)
  256. {
  257. /* Set buffer_addr_info.buffer_addr_31_0 */
  258. HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0,
  259. BUFFER_ADDR_INFO_BUF_ADDR_INFO) =
  260. HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr);
  261. /* Set buffer_addr_info.buffer_addr_39_32 */
  262. HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
  263. BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
  264. HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32,
  265. (((uint64_t)paddr) >> 32));
  266. /* Set buffer_addr_info.return_buffer_manager = rbm id */
  267. HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
  268. BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
  269. HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1,
  270. RETURN_BUFFER_MANAGER, rbm_id);
  271. /* Set buffer_addr_info.sw_buffer_cookie = desc_id */
  272. HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
  273. BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
  274. HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE,
  275. desc_id);
  276. /* Set Buffer or Ext Descriptor Type */
  277. HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2,
  278. BUF_OR_EXT_DESC_TYPE) |=
  279. HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type);
  280. }
  281. #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX)
  282. /**
  283. * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL
  284. * tlv_tag: Taf of the TLVs
  285. * rx_tlv: the pointer to the TLVs
  286. * @ppdu_info: pointer to ppdu_info
  287. *
  288. * Return: true if the tlv is handled, false if not
  289. */
  290. static inline bool
  291. hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv,
  292. struct hal_rx_ppdu_info *ppdu_info)
  293. {
  294. uint32_t value;
  295. switch (tlv_tag) {
  296. case WIFIPHYRX_HE_SIG_A_MU_UL_E:
  297. {
  298. uint8_t *he_sig_a_mu_ul_info =
  299. (uint8_t *)rx_tlv +
  300. HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0,
  301. HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS);
  302. ppdu_info->rx_status.he_flags = 1;
  303. value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0,
  304. FORMAT_INDICATION);
  305. if (value == 0) {
  306. ppdu_info->rx_status.he_data1 =
  307. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  308. } else {
  309. ppdu_info->rx_status.he_data1 =
  310. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  311. }
  312. /* data1 */
  313. ppdu_info->rx_status.he_data1 |=
  314. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  315. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  316. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN;
  317. /* data2 */
  318. ppdu_info->rx_status.he_data2 |=
  319. QDF_MON_STATUS_TXOP_KNOWN;
  320. /*data3*/
  321. value = HAL_RX_GET(he_sig_a_mu_ul_info,
  322. HE_SIG_A_MU_UL_INFO_0, BSS_COLOR_ID);
  323. ppdu_info->rx_status.he_data3 = value;
  324. /* 1 for UL and 0 for DL */
  325. value = 1;
  326. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  327. ppdu_info->rx_status.he_data3 |= value;
  328. /*data4*/
  329. value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0,
  330. SPATIAL_REUSE);
  331. ppdu_info->rx_status.he_data4 = value;
  332. /*data5*/
  333. value = HAL_RX_GET(he_sig_a_mu_ul_info,
  334. HE_SIG_A_MU_UL_INFO_0, TRANSMIT_BW);
  335. ppdu_info->rx_status.he_data5 = value;
  336. ppdu_info->rx_status.bw = value;
  337. /*data6*/
  338. value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_1,
  339. TXOP_DURATION);
  340. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  341. ppdu_info->rx_status.he_data6 |= value;
  342. return true;
  343. }
  344. default:
  345. return false;
  346. }
  347. }
  348. #else
  349. static inline bool
  350. hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv,
  351. struct hal_rx_ppdu_info *ppdu_info)
  352. {
  353. return false;
  354. }
  355. #endif /* QCA_WIFI_QCA6290_11AX_MU_UL && QCA_WIFI_QCA6290_11AX */
  356. #if defined(RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET) && \
  357. defined(RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET)
  358. static inline void
  359. hal_rx_handle_mu_ul_info(void *rx_tlv,
  360. struct mon_rx_user_status *mon_rx_user_status)
  361. {
  362. mon_rx_user_status->mu_ul_user_v0_word0 =
  363. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_11,
  364. SW_RESPONSE_REFERENCE_PTR);
  365. mon_rx_user_status->mu_ul_user_v0_word1 =
  366. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_22,
  367. SW_RESPONSE_REFERENCE_PTR_EXT);
  368. }
  369. static inline void
  370. hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo,
  371. struct mon_rx_user_status *mon_rx_user_status)
  372. {
  373. uint32_t mpdu_ok_byte_count;
  374. uint32_t mpdu_err_byte_count;
  375. mpdu_ok_byte_count = HAL_RX_GET(rx_tlv,
  376. RX_PPDU_END_USER_STATS_17,
  377. MPDU_OK_BYTE_COUNT);
  378. mpdu_err_byte_count = HAL_RX_GET(rx_tlv,
  379. RX_PPDU_END_USER_STATS_19,
  380. MPDU_ERR_BYTE_COUNT);
  381. mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count;
  382. mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count;
  383. }
  384. #else
  385. static inline void
  386. hal_rx_handle_mu_ul_info(void *rx_tlv,
  387. struct mon_rx_user_status *mon_rx_user_status)
  388. {
  389. }
  390. static inline void
  391. hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo,
  392. struct mon_rx_user_status *mon_rx_user_status)
  393. {
  394. struct hal_rx_ppdu_info *ppdu_info =
  395. (struct hal_rx_ppdu_info *)ppduinfo;
  396. /* HKV1: doesn't support mpdu byte count */
  397. mon_rx_user_status->mpdu_ok_byte_count = ppdu_info->rx_status.ppdu_len;
  398. mon_rx_user_status->mpdu_err_byte_count = 0;
  399. }
  400. #endif
  401. static inline void
  402. hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, uint32_t user_id,
  403. struct mon_rx_user_status *mon_rx_user_status)
  404. {
  405. struct mon_rx_info *mon_rx_info;
  406. struct mon_rx_user_info *mon_rx_user_info;
  407. struct hal_rx_ppdu_info *ppdu_info =
  408. (struct hal_rx_ppdu_info *)ppduinfo;
  409. mon_rx_info = &ppdu_info->rx_info;
  410. mon_rx_user_info = &ppdu_info->rx_user_info[user_id];
  411. mon_rx_user_info->qos_control_info_valid =
  412. mon_rx_info->qos_control_info_valid;
  413. mon_rx_user_info->qos_control = mon_rx_info->qos_control;
  414. mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index;
  415. mon_rx_user_status->tid = ppdu_info->rx_status.tid;
  416. mon_rx_user_status->tcp_msdu_count =
  417. ppdu_info->rx_status.tcp_msdu_count;
  418. mon_rx_user_status->udp_msdu_count =
  419. ppdu_info->rx_status.udp_msdu_count;
  420. mon_rx_user_status->other_msdu_count =
  421. ppdu_info->rx_status.other_msdu_count;
  422. mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control;
  423. mon_rx_user_status->frame_control_info_valid =
  424. ppdu_info->rx_status.frame_control_info_valid;
  425. mon_rx_user_status->data_sequence_control_info_valid =
  426. ppdu_info->rx_status.data_sequence_control_info_valid;
  427. mon_rx_user_status->first_data_seq_ctrl =
  428. ppdu_info->rx_status.first_data_seq_ctrl;
  429. mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type;
  430. mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags;
  431. mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags;
  432. mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags;
  433. mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags;
  434. mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags;
  435. mon_rx_user_status->mpdu_cnt_fcs_ok =
  436. ppdu_info->com_info.mpdu_cnt_fcs_ok;
  437. mon_rx_user_status->mpdu_cnt_fcs_err =
  438. ppdu_info->com_info.mpdu_cnt_fcs_err;
  439. qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap,
  440. &ppdu_info->com_info.mpdu_fcs_ok_bitmap,
  441. HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *
  442. sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0]));
  443. hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status);
  444. }
  445. #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, word_1, word_2, \
  446. ppdu_info, rssi_info_tlv) \
  447. { \
  448. ppdu_info->rx_status.rssi_chain[chain][0] = \
  449. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\
  450. RSSI_PRI20_CHAIN##chain); \
  451. ppdu_info->rx_status.rssi_chain[chain][1] = \
  452. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\
  453. RSSI_EXT20_CHAIN##chain); \
  454. ppdu_info->rx_status.rssi_chain[chain][2] = \
  455. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\
  456. RSSI_EXT40_LOW20_CHAIN##chain); \
  457. ppdu_info->rx_status.rssi_chain[chain][3] = \
  458. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\
  459. RSSI_EXT40_HIGH20_CHAIN##chain); \
  460. ppdu_info->rx_status.rssi_chain[chain][4] = \
  461. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\
  462. RSSI_EXT80_LOW20_CHAIN##chain); \
  463. ppdu_info->rx_status.rssi_chain[chain][5] = \
  464. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\
  465. RSSI_EXT80_LOW_HIGH20_CHAIN##chain); \
  466. ppdu_info->rx_status.rssi_chain[chain][6] = \
  467. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\
  468. RSSI_EXT80_HIGH_LOW20_CHAIN##chain); \
  469. ppdu_info->rx_status.rssi_chain[chain][7] = \
  470. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\
  471. RSSI_EXT80_HIGH20_CHAIN##chain); \
  472. } \
  473. #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \
  474. {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, 0, 1, ppdu_info, rssi_info_tlv) \
  475. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, 2, 3, ppdu_info, rssi_info_tlv) \
  476. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, 4, 5, ppdu_info, rssi_info_tlv) \
  477. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, 6, 7, ppdu_info, rssi_info_tlv) \
  478. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(4, 8, 9, ppdu_info, rssi_info_tlv) \
  479. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(5, 10, 11, ppdu_info, rssi_info_tlv) \
  480. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(6, 12, 13, ppdu_info, rssi_info_tlv) \
  481. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(7, 14, 15, ppdu_info, rssi_info_tlv)} \
  482. static inline uint32_t
  483. hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info,
  484. uint8_t *rssi_info_tlv)
  485. {
  486. HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv)
  487. return 0;
  488. }
  489. #ifdef WLAN_TX_PKT_CAPTURE_ENH
  490. static inline void
  491. hal_get_qos_control(void *rx_tlv,
  492. struct hal_rx_ppdu_info *ppdu_info)
  493. {
  494. ppdu_info->rx_info.qos_control_info_valid =
  495. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  496. QOS_CONTROL_INFO_VALID);
  497. if (ppdu_info->rx_info.qos_control_info_valid)
  498. ppdu_info->rx_info.qos_control =
  499. HAL_RX_GET(rx_tlv,
  500. RX_PPDU_END_USER_STATS_5,
  501. QOS_CONTROL_FIELD);
  502. }
  503. static inline void
  504. hal_get_mac_addr1(uint8_t *rx_mpdu_start,
  505. struct hal_rx_ppdu_info *ppdu_info)
  506. {
  507. if ((ppdu_info->sw_frame_group_id
  508. == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) ||
  509. (ppdu_info->sw_frame_group_id ==
  510. HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) {
  511. ppdu_info->rx_info.mac_addr1_valid =
  512. HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start);
  513. *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] =
  514. HAL_RX_GET(rx_mpdu_start,
  515. RX_MPDU_INFO_15,
  516. MAC_ADDR_AD1_31_0);
  517. if (ppdu_info->sw_frame_group_id ==
  518. HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) {
  519. *(uint32_t *)&ppdu_info->rx_info.mac_addr1[4] =
  520. HAL_RX_GET(rx_mpdu_start,
  521. RX_MPDU_INFO_16,
  522. MAC_ADDR_AD1_47_32);
  523. }
  524. }
  525. }
  526. #else
  527. static inline void
  528. hal_get_qos_control(void *rx_tlv,
  529. struct hal_rx_ppdu_info *ppdu_info)
  530. {
  531. }
  532. static inline void
  533. hal_get_mac_addr1(uint8_t *rx_mpdu_start,
  534. struct hal_rx_ppdu_info *ppdu_info)
  535. {
  536. }
  537. #endif
  538. #ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS
  539. static inline void
  540. hal_update_frame_type_cnt(uint8_t *rx_mpdu_start,
  541. struct hal_rx_ppdu_info *ppdu_info)
  542. {
  543. uint16_t frame_ctrl;
  544. uint8_t fc_type;
  545. if (HAL_RX_GET_FC_VALID(rx_mpdu_start)) {
  546. frame_ctrl = HAL_RX_GET(rx_mpdu_start,
  547. RX_MPDU_INFO_14,
  548. MPDU_FRAME_CONTROL_FIELD);
  549. fc_type = HAL_RX_GET_FRAME_CTRL_TYPE(frame_ctrl);
  550. if (fc_type == HAL_RX_FRAME_CTRL_TYPE_MGMT)
  551. ppdu_info->frm_type_info.rx_mgmt_cnt++;
  552. else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_CTRL)
  553. ppdu_info->frm_type_info.rx_ctrl_cnt++;
  554. else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_DATA)
  555. ppdu_info->frm_type_info.rx_data_cnt++;
  556. }
  557. }
  558. #else
  559. static inline void
  560. hal_update_frame_type_cnt(uint8_t *rx_mpdu_start,
  561. struct hal_rx_ppdu_info *ppdu_info)
  562. {
  563. }
  564. #endif
  565. /**
  566. * hal_rx_status_get_tlv_info() - process receive info TLV
  567. * @rx_tlv_hdr: pointer to TLV header
  568. * @ppdu_info: pointer to ppdu_info
  569. *
  570. * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv
  571. */
  572. static inline uint32_t
  573. hal_rx_status_get_tlv_info_generic_li(void *rx_tlv_hdr, void *ppduinfo,
  574. hal_soc_handle_t hal_soc_hdl,
  575. qdf_nbuf_t nbuf)
  576. {
  577. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  578. uint32_t tlv_tag, user_id, tlv_len, value;
  579. uint8_t group_id = 0;
  580. uint8_t he_dcm = 0;
  581. uint8_t he_stbc = 0;
  582. uint16_t he_gi = 0;
  583. uint16_t he_ltf = 0;
  584. void *rx_tlv;
  585. bool unhandled = false;
  586. struct mon_rx_user_status *mon_rx_user_status;
  587. struct hal_rx_ppdu_info *ppdu_info =
  588. (struct hal_rx_ppdu_info *)ppduinfo;
  589. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
  590. user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr);
  591. tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
  592. rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
  593. switch (tlv_tag) {
  594. case WIFIRX_PPDU_START_E:
  595. {
  596. if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id ==
  597. HAL_RX_GET(rx_tlv, RX_PPDU_START_0, PHY_PPDU_ID)))
  598. hal_err("Matching ppdu_id(%u) detected",
  599. ppdu_info->com_info.last_ppdu_id);
  600. /* Reset ppdu_info before processing the ppdu */
  601. qdf_mem_zero(ppdu_info,
  602. sizeof(struct hal_rx_ppdu_info));
  603. ppdu_info->com_info.last_ppdu_id =
  604. ppdu_info->com_info.ppdu_id =
  605. HAL_RX_GET(rx_tlv, RX_PPDU_START_0,
  606. PHY_PPDU_ID);
  607. /* channel number is set in PHY meta data */
  608. ppdu_info->rx_status.chan_num =
  609. (HAL_RX_GET(rx_tlv, RX_PPDU_START_1,
  610. SW_PHY_META_DATA) & 0x0000FFFF);
  611. ppdu_info->rx_status.chan_freq =
  612. (HAL_RX_GET(rx_tlv, RX_PPDU_START_1,
  613. SW_PHY_META_DATA) & 0xFFFF0000) >> 16;
  614. if (ppdu_info->rx_status.chan_num) {
  615. ppdu_info->rx_status.chan_freq =
  616. hal_rx_radiotap_num_to_freq(
  617. ppdu_info->rx_status.chan_num,
  618. ppdu_info->rx_status.chan_freq);
  619. }
  620. ppdu_info->com_info.ppdu_timestamp =
  621. HAL_RX_GET(rx_tlv, RX_PPDU_START_2,
  622. PPDU_START_TIMESTAMP);
  623. ppdu_info->rx_status.ppdu_timestamp =
  624. ppdu_info->com_info.ppdu_timestamp;
  625. ppdu_info->rx_state = HAL_RX_MON_PPDU_START;
  626. break;
  627. }
  628. case WIFIRX_PPDU_START_USER_INFO_E:
  629. break;
  630. case WIFIRX_PPDU_END_E:
  631. dp_nofl_debug("[%s][%d] ppdu_end_e len=%d",
  632. __func__, __LINE__, tlv_len);
  633. /* This is followed by sub-TLVs of PPDU_END */
  634. ppdu_info->rx_state = HAL_RX_MON_PPDU_END;
  635. break;
  636. case WIFIPHYRX_PKT_END_E:
  637. hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info);
  638. break;
  639. case WIFIRXPCU_PPDU_END_INFO_E:
  640. ppdu_info->rx_status.rx_antenna =
  641. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2, RX_ANTENNA);
  642. ppdu_info->rx_status.tsft =
  643. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1,
  644. WB_TIMESTAMP_UPPER_32);
  645. ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) |
  646. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0,
  647. WB_TIMESTAMP_LOWER_32);
  648. ppdu_info->rx_status.duration =
  649. HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8,
  650. RX_PPDU_DURATION);
  651. hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info);
  652. hal_rx_get_phyrx_abort(hal, rx_tlv, ppdu_info);
  653. break;
  654. /*
  655. * WIFIRX_PPDU_END_USER_STATS_E comes for each user received.
  656. * for MU, based on num users we see this tlv that many times.
  657. */
  658. case WIFIRX_PPDU_END_USER_STATS_E:
  659. {
  660. unsigned long tid = 0;
  661. uint16_t seq = 0;
  662. ppdu_info->rx_status.ast_index =
  663. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4,
  664. AST_INDEX);
  665. tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12,
  666. RECEIVED_QOS_DATA_TID_BITMAP);
  667. ppdu_info->rx_status.tid = qdf_find_first_bit(&tid,
  668. sizeof(tid) * 8);
  669. if (ppdu_info->rx_status.tid == (sizeof(tid) * 8))
  670. ppdu_info->rx_status.tid = HAL_TID_INVALID;
  671. ppdu_info->rx_status.tcp_msdu_count =
  672. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9,
  673. TCP_MSDU_COUNT) +
  674. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10,
  675. TCP_ACK_MSDU_COUNT);
  676. ppdu_info->rx_status.udp_msdu_count =
  677. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9,
  678. UDP_MSDU_COUNT);
  679. ppdu_info->rx_status.other_msdu_count =
  680. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10,
  681. OTHER_MSDU_COUNT);
  682. if (ppdu_info->sw_frame_group_id
  683. != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) {
  684. ppdu_info->rx_status.frame_control_info_valid =
  685. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  686. FRAME_CONTROL_INFO_VALID);
  687. if (ppdu_info->rx_status.frame_control_info_valid)
  688. ppdu_info->rx_status.frame_control =
  689. HAL_RX_GET(rx_tlv,
  690. RX_PPDU_END_USER_STATS_4,
  691. FRAME_CONTROL_FIELD);
  692. hal_get_qos_control(rx_tlv, ppdu_info);
  693. }
  694. ppdu_info->rx_status.data_sequence_control_info_valid =
  695. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  696. DATA_SEQUENCE_CONTROL_INFO_VALID);
  697. seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5,
  698. FIRST_DATA_SEQ_CTRL);
  699. if (ppdu_info->rx_status.data_sequence_control_info_valid)
  700. ppdu_info->rx_status.first_data_seq_ctrl = seq;
  701. ppdu_info->rx_status.preamble_type =
  702. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  703. HT_CONTROL_FIELD_PKT_TYPE);
  704. switch (ppdu_info->rx_status.preamble_type) {
  705. case HAL_RX_PKT_TYPE_11N:
  706. ppdu_info->rx_status.ht_flags = 1;
  707. ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT;
  708. break;
  709. case HAL_RX_PKT_TYPE_11AC:
  710. ppdu_info->rx_status.vht_flags = 1;
  711. break;
  712. case HAL_RX_PKT_TYPE_11AX:
  713. ppdu_info->rx_status.he_flags = 1;
  714. break;
  715. default:
  716. break;
  717. }
  718. ppdu_info->com_info.mpdu_cnt_fcs_ok =
  719. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  720. MPDU_CNT_FCS_OK);
  721. ppdu_info->com_info.mpdu_cnt_fcs_err =
  722. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2,
  723. MPDU_CNT_FCS_ERR);
  724. if ((ppdu_info->com_info.mpdu_cnt_fcs_ok |
  725. ppdu_info->com_info.mpdu_cnt_fcs_err) > 1)
  726. ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG;
  727. else
  728. ppdu_info->rx_status.rs_flags &=
  729. (~IEEE80211_AMPDU_FLAG);
  730. ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] =
  731. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_7,
  732. FCS_OK_BITMAP_31_0);
  733. ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] =
  734. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_8,
  735. FCS_OK_BITMAP_63_32);
  736. if (user_id < HAL_MAX_UL_MU_USERS) {
  737. mon_rx_user_status =
  738. &ppdu_info->rx_user_status[user_id];
  739. hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status);
  740. ppdu_info->com_info.num_users++;
  741. hal_rx_populate_mu_user_info(rx_tlv, ppdu_info,
  742. user_id,
  743. mon_rx_user_status);
  744. }
  745. break;
  746. }
  747. case WIFIRX_PPDU_END_USER_STATS_EXT_E:
  748. ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] =
  749. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_1,
  750. FCS_OK_BITMAP_95_64);
  751. ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] =
  752. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_2,
  753. FCS_OK_BITMAP_127_96);
  754. ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] =
  755. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_3,
  756. FCS_OK_BITMAP_159_128);
  757. ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] =
  758. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_4,
  759. FCS_OK_BITMAP_191_160);
  760. ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] =
  761. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_5,
  762. FCS_OK_BITMAP_223_192);
  763. ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] =
  764. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_6,
  765. FCS_OK_BITMAP_255_224);
  766. break;
  767. case WIFIRX_PPDU_END_STATUS_DONE_E:
  768. return HAL_TLV_STATUS_PPDU_DONE;
  769. case WIFIDUMMY_E:
  770. return HAL_TLV_STATUS_BUF_DONE;
  771. case WIFIPHYRX_HT_SIG_E:
  772. {
  773. uint8_t *ht_sig_info = (uint8_t *)rx_tlv +
  774. HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0,
  775. HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS);
  776. value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1,
  777. FEC_CODING);
  778. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  779. 1 : 0;
  780. ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info,
  781. HT_SIG_INFO_0, MCS);
  782. ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs;
  783. ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info,
  784. HT_SIG_INFO_0, CBW);
  785. ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info,
  786. HT_SIG_INFO_1, SHORT_GI);
  787. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  788. ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >>
  789. HT_SIG_SU_NSS_SHIFT) + 1;
  790. ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1);
  791. hal_rx_get_ht_sig_info(ppdu_info, ht_sig_info);
  792. break;
  793. }
  794. case WIFIPHYRX_L_SIG_B_E:
  795. {
  796. uint8_t *l_sig_b_info = (uint8_t *)rx_tlv +
  797. HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0,
  798. L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS);
  799. value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE);
  800. ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info);
  801. switch (value) {
  802. case 1:
  803. ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS;
  804. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3;
  805. break;
  806. case 2:
  807. ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS;
  808. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2;
  809. break;
  810. case 3:
  811. ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS;
  812. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1;
  813. break;
  814. case 4:
  815. ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS;
  816. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0;
  817. break;
  818. case 5:
  819. ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS;
  820. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6;
  821. break;
  822. case 6:
  823. ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS;
  824. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5;
  825. break;
  826. case 7:
  827. ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS;
  828. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4;
  829. break;
  830. default:
  831. break;
  832. }
  833. ppdu_info->rx_status.cck_flag = 1;
  834. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  835. break;
  836. }
  837. case WIFIPHYRX_L_SIG_A_E:
  838. {
  839. uint8_t *l_sig_a_info = (uint8_t *)rx_tlv +
  840. HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0,
  841. L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS);
  842. value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE);
  843. ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info);
  844. switch (value) {
  845. case 8:
  846. ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS;
  847. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0;
  848. break;
  849. case 9:
  850. ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS;
  851. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1;
  852. break;
  853. case 10:
  854. ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS;
  855. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2;
  856. break;
  857. case 11:
  858. ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS;
  859. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3;
  860. break;
  861. case 12:
  862. ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS;
  863. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4;
  864. break;
  865. case 13:
  866. ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS;
  867. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5;
  868. break;
  869. case 14:
  870. ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS;
  871. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6;
  872. break;
  873. case 15:
  874. ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS;
  875. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7;
  876. break;
  877. default:
  878. break;
  879. }
  880. ppdu_info->rx_status.ofdm_flag = 1;
  881. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  882. hal_rx_get_l_sig_a_info(ppdu_info, l_sig_a_info);
  883. break;
  884. }
  885. case WIFIPHYRX_VHT_SIG_A_E:
  886. {
  887. uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv +
  888. HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0,
  889. VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS);
  890. value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1,
  891. SU_MU_CODING);
  892. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  893. 1 : 0;
  894. group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0,
  895. GROUP_ID);
  896. ppdu_info->rx_status.vht_flag_values5 = group_id;
  897. ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info,
  898. VHT_SIG_A_INFO_1, MCS);
  899. ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info,
  900. VHT_SIG_A_INFO_1, GI_SETTING);
  901. switch (hal->target_type) {
  902. case TARGET_TYPE_QCA8074:
  903. case TARGET_TYPE_QCA8074V2:
  904. case TARGET_TYPE_QCA6018:
  905. case TARGET_TYPE_QCA5018:
  906. case TARGET_TYPE_QCN9000:
  907. case TARGET_TYPE_QCN6122:
  908. #ifdef QCA_WIFI_QCA6390
  909. case TARGET_TYPE_QCA6390:
  910. #endif
  911. case TARGET_TYPE_QCA6490:
  912. ppdu_info->rx_status.is_stbc =
  913. HAL_RX_GET(vht_sig_a_info,
  914. VHT_SIG_A_INFO_0, STBC);
  915. value = HAL_RX_GET(vht_sig_a_info,
  916. VHT_SIG_A_INFO_0, N_STS);
  917. value = value & VHT_SIG_SU_NSS_MASK;
  918. if (ppdu_info->rx_status.is_stbc && (value > 0))
  919. value = ((value + 1) >> 1) - 1;
  920. ppdu_info->rx_status.nss =
  921. ((value & VHT_SIG_SU_NSS_MASK) + 1);
  922. break;
  923. case TARGET_TYPE_QCA6290:
  924. #if !defined(QCA_WIFI_QCA6290_11AX)
  925. ppdu_info->rx_status.is_stbc =
  926. HAL_RX_GET(vht_sig_a_info,
  927. VHT_SIG_A_INFO_0, STBC);
  928. value = HAL_RX_GET(vht_sig_a_info,
  929. VHT_SIG_A_INFO_0, N_STS);
  930. value = value & VHT_SIG_SU_NSS_MASK;
  931. if (ppdu_info->rx_status.is_stbc && (value > 0))
  932. value = ((value + 1) >> 1) - 1;
  933. ppdu_info->rx_status.nss =
  934. ((value & VHT_SIG_SU_NSS_MASK) + 1);
  935. #else
  936. ppdu_info->rx_status.nss = 0;
  937. #endif
  938. break;
  939. case TARGET_TYPE_QCA6750:
  940. ppdu_info->rx_status.nss = 0;
  941. break;
  942. default:
  943. break;
  944. }
  945. ppdu_info->rx_status.vht_flag_values3[0] =
  946. (((ppdu_info->rx_status.mcs) << 4)
  947. | ppdu_info->rx_status.nss);
  948. ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info,
  949. VHT_SIG_A_INFO_0, BANDWIDTH);
  950. ppdu_info->rx_status.vht_flag_values2 =
  951. ppdu_info->rx_status.bw;
  952. ppdu_info->rx_status.vht_flag_values4 =
  953. HAL_RX_GET(vht_sig_a_info,
  954. VHT_SIG_A_INFO_1, SU_MU_CODING);
  955. ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info,
  956. VHT_SIG_A_INFO_1, BEAMFORMED);
  957. if (group_id == 0 || group_id == 63)
  958. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  959. else
  960. ppdu_info->rx_status.reception_type =
  961. HAL_RX_TYPE_MU_MIMO;
  962. hal_rx_get_vht_sig_a_info(ppdu_info, vht_sig_a_info);
  963. break;
  964. }
  965. case WIFIPHYRX_HE_SIG_A_SU_E:
  966. {
  967. uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv +
  968. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0,
  969. HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS);
  970. ppdu_info->rx_status.he_flags = 1;
  971. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0,
  972. FORMAT_INDICATION);
  973. if (value == 0) {
  974. ppdu_info->rx_status.he_data1 =
  975. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  976. } else {
  977. ppdu_info->rx_status.he_data1 =
  978. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  979. }
  980. /* data1 */
  981. ppdu_info->rx_status.he_data1 |=
  982. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  983. QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN |
  984. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  985. QDF_MON_STATUS_HE_MCS_KNOWN |
  986. QDF_MON_STATUS_HE_DCM_KNOWN |
  987. QDF_MON_STATUS_HE_CODING_KNOWN |
  988. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  989. QDF_MON_STATUS_HE_STBC_KNOWN |
  990. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  991. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  992. /* data2 */
  993. ppdu_info->rx_status.he_data2 =
  994. QDF_MON_STATUS_HE_GI_KNOWN;
  995. ppdu_info->rx_status.he_data2 |=
  996. QDF_MON_STATUS_TXBF_KNOWN |
  997. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  998. QDF_MON_STATUS_TXOP_KNOWN |
  999. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  1000. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  1001. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  1002. /* data3 */
  1003. value = HAL_RX_GET(he_sig_a_su_info,
  1004. HE_SIG_A_SU_INFO_0, BSS_COLOR_ID);
  1005. ppdu_info->rx_status.he_data3 = value;
  1006. value = HAL_RX_GET(he_sig_a_su_info,
  1007. HE_SIG_A_SU_INFO_0, BEAM_CHANGE);
  1008. value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT;
  1009. ppdu_info->rx_status.he_data3 |= value;
  1010. value = HAL_RX_GET(he_sig_a_su_info,
  1011. HE_SIG_A_SU_INFO_0, DL_UL_FLAG);
  1012. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  1013. ppdu_info->rx_status.he_data3 |= value;
  1014. value = HAL_RX_GET(he_sig_a_su_info,
  1015. HE_SIG_A_SU_INFO_0, TRANSMIT_MCS);
  1016. ppdu_info->rx_status.mcs = value;
  1017. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  1018. ppdu_info->rx_status.he_data3 |= value;
  1019. value = HAL_RX_GET(he_sig_a_su_info,
  1020. HE_SIG_A_SU_INFO_0, DCM);
  1021. he_dcm = value;
  1022. value = value << QDF_MON_STATUS_DCM_SHIFT;
  1023. ppdu_info->rx_status.he_data3 |= value;
  1024. value = HAL_RX_GET(he_sig_a_su_info,
  1025. HE_SIG_A_SU_INFO_1, CODING);
  1026. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  1027. 1 : 0;
  1028. value = value << QDF_MON_STATUS_CODING_SHIFT;
  1029. ppdu_info->rx_status.he_data3 |= value;
  1030. value = HAL_RX_GET(he_sig_a_su_info,
  1031. HE_SIG_A_SU_INFO_1,
  1032. LDPC_EXTRA_SYMBOL);
  1033. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  1034. ppdu_info->rx_status.he_data3 |= value;
  1035. value = HAL_RX_GET(he_sig_a_su_info,
  1036. HE_SIG_A_SU_INFO_1, STBC);
  1037. he_stbc = value;
  1038. value = value << QDF_MON_STATUS_STBC_SHIFT;
  1039. ppdu_info->rx_status.he_data3 |= value;
  1040. /* data4 */
  1041. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0,
  1042. SPATIAL_REUSE);
  1043. ppdu_info->rx_status.he_data4 = value;
  1044. /* data5 */
  1045. value = HAL_RX_GET(he_sig_a_su_info,
  1046. HE_SIG_A_SU_INFO_0, TRANSMIT_BW);
  1047. ppdu_info->rx_status.he_data5 = value;
  1048. ppdu_info->rx_status.bw = value;
  1049. value = HAL_RX_GET(he_sig_a_su_info,
  1050. HE_SIG_A_SU_INFO_0, CP_LTF_SIZE);
  1051. switch (value) {
  1052. case 0:
  1053. he_gi = HE_GI_0_8;
  1054. he_ltf = HE_LTF_1_X;
  1055. break;
  1056. case 1:
  1057. he_gi = HE_GI_0_8;
  1058. he_ltf = HE_LTF_2_X;
  1059. break;
  1060. case 2:
  1061. he_gi = HE_GI_1_6;
  1062. he_ltf = HE_LTF_2_X;
  1063. break;
  1064. case 3:
  1065. if (he_dcm && he_stbc) {
  1066. he_gi = HE_GI_0_8;
  1067. he_ltf = HE_LTF_4_X;
  1068. } else {
  1069. he_gi = HE_GI_3_2;
  1070. he_ltf = HE_LTF_4_X;
  1071. }
  1072. break;
  1073. }
  1074. ppdu_info->rx_status.sgi = he_gi;
  1075. ppdu_info->rx_status.ltf_size = he_ltf;
  1076. hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf);
  1077. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  1078. ppdu_info->rx_status.he_data5 |= value;
  1079. value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
  1080. ppdu_info->rx_status.he_data5 |= value;
  1081. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS);
  1082. value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
  1083. ppdu_info->rx_status.he_data5 |= value;
  1084. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  1085. PACKET_EXTENSION_A_FACTOR);
  1086. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  1087. ppdu_info->rx_status.he_data5 |= value;
  1088. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF);
  1089. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  1090. ppdu_info->rx_status.he_data5 |= value;
  1091. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  1092. PACKET_EXTENSION_PE_DISAMBIGUITY);
  1093. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  1094. ppdu_info->rx_status.he_data5 |= value;
  1095. /* data6 */
  1096. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS);
  1097. value++;
  1098. ppdu_info->rx_status.nss = value;
  1099. ppdu_info->rx_status.he_data6 = value;
  1100. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  1101. DOPPLER_INDICATION);
  1102. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  1103. ppdu_info->rx_status.he_data6 |= value;
  1104. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  1105. TXOP_DURATION);
  1106. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  1107. ppdu_info->rx_status.he_data6 |= value;
  1108. ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info,
  1109. HE_SIG_A_SU_INFO_1, TXBF);
  1110. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  1111. hal_rx_get_crc_he_sig_a_su_info(ppdu_info, he_sig_a_su_info);
  1112. break;
  1113. }
  1114. case WIFIPHYRX_HE_SIG_A_MU_DL_E:
  1115. {
  1116. uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv +
  1117. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0,
  1118. HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS);
  1119. ppdu_info->rx_status.he_mu_flags = 1;
  1120. /* HE Flags */
  1121. /*data1*/
  1122. ppdu_info->rx_status.he_data1 =
  1123. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  1124. ppdu_info->rx_status.he_data1 |=
  1125. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  1126. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  1127. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  1128. QDF_MON_STATUS_HE_STBC_KNOWN |
  1129. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  1130. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  1131. /* data2 */
  1132. ppdu_info->rx_status.he_data2 =
  1133. QDF_MON_STATUS_HE_GI_KNOWN;
  1134. ppdu_info->rx_status.he_data2 |=
  1135. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  1136. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  1137. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  1138. QDF_MON_STATUS_TXOP_KNOWN |
  1139. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  1140. /*data3*/
  1141. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1142. HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID);
  1143. ppdu_info->rx_status.he_data3 = value;
  1144. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1145. HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG);
  1146. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  1147. ppdu_info->rx_status.he_data3 |= value;
  1148. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1149. HE_SIG_A_MU_DL_INFO_1,
  1150. LDPC_EXTRA_SYMBOL);
  1151. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  1152. ppdu_info->rx_status.he_data3 |= value;
  1153. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1154. HE_SIG_A_MU_DL_INFO_1, STBC);
  1155. he_stbc = value;
  1156. value = value << QDF_MON_STATUS_STBC_SHIFT;
  1157. ppdu_info->rx_status.he_data3 |= value;
  1158. /*data4*/
  1159. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0,
  1160. SPATIAL_REUSE);
  1161. ppdu_info->rx_status.he_data4 = value;
  1162. /*data5*/
  1163. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1164. HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW);
  1165. ppdu_info->rx_status.he_data5 = value;
  1166. ppdu_info->rx_status.bw = value;
  1167. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1168. HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE);
  1169. switch (value) {
  1170. case 0:
  1171. he_gi = HE_GI_0_8;
  1172. he_ltf = HE_LTF_4_X;
  1173. break;
  1174. case 1:
  1175. he_gi = HE_GI_0_8;
  1176. he_ltf = HE_LTF_2_X;
  1177. break;
  1178. case 2:
  1179. he_gi = HE_GI_1_6;
  1180. he_ltf = HE_LTF_2_X;
  1181. break;
  1182. case 3:
  1183. he_gi = HE_GI_3_2;
  1184. he_ltf = HE_LTF_4_X;
  1185. break;
  1186. }
  1187. ppdu_info->rx_status.sgi = he_gi;
  1188. ppdu_info->rx_status.ltf_size = he_ltf;
  1189. hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf);
  1190. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  1191. ppdu_info->rx_status.he_data5 |= value;
  1192. value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
  1193. ppdu_info->rx_status.he_data5 |= value;
  1194. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1195. HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS);
  1196. value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
  1197. ppdu_info->rx_status.he_data5 |= value;
  1198. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
  1199. PACKET_EXTENSION_A_FACTOR);
  1200. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  1201. ppdu_info->rx_status.he_data5 |= value;
  1202. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
  1203. PACKET_EXTENSION_PE_DISAMBIGUITY);
  1204. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  1205. ppdu_info->rx_status.he_data5 |= value;
  1206. /*data6*/
  1207. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0,
  1208. DOPPLER_INDICATION);
  1209. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  1210. ppdu_info->rx_status.he_data6 |= value;
  1211. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
  1212. TXOP_DURATION);
  1213. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  1214. ppdu_info->rx_status.he_data6 |= value;
  1215. /* HE-MU Flags */
  1216. /* HE-MU-flags1 */
  1217. ppdu_info->rx_status.he_flags1 =
  1218. QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  1219. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  1220. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN |
  1221. QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN |
  1222. QDF_MON_STATUS_RU_0_KNOWN;
  1223. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1224. HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B);
  1225. ppdu_info->rx_status.he_flags1 |= value;
  1226. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1227. HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B);
  1228. value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT;
  1229. ppdu_info->rx_status.he_flags1 |= value;
  1230. /* HE-MU-flags2 */
  1231. ppdu_info->rx_status.he_flags2 =
  1232. QDF_MON_STATUS_BW_KNOWN;
  1233. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1234. HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW);
  1235. ppdu_info->rx_status.he_flags2 |= value;
  1236. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1237. HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B);
  1238. value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  1239. ppdu_info->rx_status.he_flags2 |= value;
  1240. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1241. HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS);
  1242. value = value - 1;
  1243. value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT;
  1244. ppdu_info->rx_status.he_flags2 |= value;
  1245. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO;
  1246. hal_rx_get_crc_he_sig_a_mu_dl_info(ppdu_info,
  1247. he_sig_a_mu_dl_info);
  1248. break;
  1249. }
  1250. case WIFIPHYRX_HE_SIG_B1_MU_E:
  1251. {
  1252. uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv +
  1253. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0,
  1254. HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS);
  1255. ppdu_info->rx_status.he_sig_b_common_known |=
  1256. QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0;
  1257. /* TODO: Check on the availability of other fields in
  1258. * sig_b_common
  1259. */
  1260. value = HAL_RX_GET(he_sig_b1_mu_info,
  1261. HE_SIG_B1_MU_INFO_0, RU_ALLOCATION);
  1262. ppdu_info->rx_status.he_RU[0] = value;
  1263. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO;
  1264. break;
  1265. }
  1266. case WIFIPHYRX_HE_SIG_B2_MU_E:
  1267. {
  1268. uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv +
  1269. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0,
  1270. HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS);
  1271. /*
  1272. * Not all "HE" fields can be updated from
  1273. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  1274. * to populate rest of the "HE" fields for MU scenarios.
  1275. */
  1276. /* HE-data1 */
  1277. ppdu_info->rx_status.he_data1 |=
  1278. QDF_MON_STATUS_HE_MCS_KNOWN |
  1279. QDF_MON_STATUS_HE_CODING_KNOWN;
  1280. /* HE-data2 */
  1281. /* HE-data3 */
  1282. value = HAL_RX_GET(he_sig_b2_mu_info,
  1283. HE_SIG_B2_MU_INFO_0, STA_MCS);
  1284. ppdu_info->rx_status.mcs = value;
  1285. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  1286. ppdu_info->rx_status.he_data3 |= value;
  1287. value = HAL_RX_GET(he_sig_b2_mu_info,
  1288. HE_SIG_B2_MU_INFO_0, STA_CODING);
  1289. value = value << QDF_MON_STATUS_CODING_SHIFT;
  1290. ppdu_info->rx_status.he_data3 |= value;
  1291. /* HE-data4 */
  1292. value = HAL_RX_GET(he_sig_b2_mu_info,
  1293. HE_SIG_B2_MU_INFO_0, STA_ID);
  1294. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  1295. ppdu_info->rx_status.he_data4 |= value;
  1296. /* HE-data5 */
  1297. /* HE-data6 */
  1298. value = HAL_RX_GET(he_sig_b2_mu_info,
  1299. HE_SIG_B2_MU_INFO_0, NSTS);
  1300. /* value n indicates n+1 spatial streams */
  1301. value++;
  1302. ppdu_info->rx_status.nss = value;
  1303. ppdu_info->rx_status.he_data6 |= value;
  1304. break;
  1305. }
  1306. case WIFIPHYRX_HE_SIG_B2_OFDMA_E:
  1307. {
  1308. uint8_t *he_sig_b2_ofdma_info =
  1309. (uint8_t *)rx_tlv +
  1310. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0,
  1311. HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS);
  1312. /*
  1313. * Not all "HE" fields can be updated from
  1314. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  1315. * to populate rest of "HE" fields for MU OFDMA scenarios.
  1316. */
  1317. /* HE-data1 */
  1318. ppdu_info->rx_status.he_data1 |=
  1319. QDF_MON_STATUS_HE_MCS_KNOWN |
  1320. QDF_MON_STATUS_HE_DCM_KNOWN |
  1321. QDF_MON_STATUS_HE_CODING_KNOWN;
  1322. /* HE-data2 */
  1323. ppdu_info->rx_status.he_data2 |=
  1324. QDF_MON_STATUS_TXBF_KNOWN;
  1325. /* HE-data3 */
  1326. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1327. HE_SIG_B2_OFDMA_INFO_0, STA_MCS);
  1328. ppdu_info->rx_status.mcs = value;
  1329. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  1330. ppdu_info->rx_status.he_data3 |= value;
  1331. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1332. HE_SIG_B2_OFDMA_INFO_0, STA_DCM);
  1333. he_dcm = value;
  1334. value = value << QDF_MON_STATUS_DCM_SHIFT;
  1335. ppdu_info->rx_status.he_data3 |= value;
  1336. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1337. HE_SIG_B2_OFDMA_INFO_0, STA_CODING);
  1338. value = value << QDF_MON_STATUS_CODING_SHIFT;
  1339. ppdu_info->rx_status.he_data3 |= value;
  1340. /* HE-data4 */
  1341. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1342. HE_SIG_B2_OFDMA_INFO_0, STA_ID);
  1343. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  1344. ppdu_info->rx_status.he_data4 |= value;
  1345. /* HE-data5 */
  1346. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1347. HE_SIG_B2_OFDMA_INFO_0, TXBF);
  1348. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  1349. ppdu_info->rx_status.he_data5 |= value;
  1350. /* HE-data6 */
  1351. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1352. HE_SIG_B2_OFDMA_INFO_0, NSTS);
  1353. /* value n indicates n+1 spatial streams */
  1354. value++;
  1355. ppdu_info->rx_status.nss = value;
  1356. ppdu_info->rx_status.he_data6 |= value;
  1357. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA;
  1358. break;
  1359. }
  1360. case WIFIPHYRX_RSSI_LEGACY_E:
  1361. {
  1362. uint8_t reception_type;
  1363. int8_t rssi_value;
  1364. uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv +
  1365. HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19,
  1366. RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS);
  1367. ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv,
  1368. PHYRX_RSSI_LEGACY_35, RSSI_COMB);
  1369. ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv);
  1370. ppdu_info->rx_status.he_re = 0;
  1371. reception_type = HAL_RX_GET(rx_tlv,
  1372. PHYRX_RSSI_LEGACY_0,
  1373. RECEPTION_TYPE);
  1374. switch (reception_type) {
  1375. case QDF_RECEPTION_TYPE_ULOFMDA:
  1376. ppdu_info->rx_status.reception_type =
  1377. HAL_RX_TYPE_MU_OFDMA;
  1378. ppdu_info->rx_status.ulofdma_flag = 1;
  1379. ppdu_info->rx_status.he_data1 =
  1380. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  1381. break;
  1382. case QDF_RECEPTION_TYPE_ULMIMO:
  1383. ppdu_info->rx_status.reception_type =
  1384. HAL_RX_TYPE_MU_MIMO;
  1385. ppdu_info->rx_status.he_data1 =
  1386. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  1387. break;
  1388. default:
  1389. ppdu_info->rx_status.reception_type =
  1390. HAL_RX_TYPE_SU;
  1391. break;
  1392. }
  1393. hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv);
  1394. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1395. RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0);
  1396. ppdu_info->rx_status.rssi[0] = rssi_value;
  1397. dp_nofl_debug("RSSI_PRI20_CHAIN0: %d\n", rssi_value);
  1398. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1399. RECEIVE_RSSI_INFO_2, RSSI_PRI20_CHAIN1);
  1400. ppdu_info->rx_status.rssi[1] = rssi_value;
  1401. dp_nofl_debug("RSSI_PRI20_CHAIN1: %d\n", rssi_value);
  1402. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1403. RECEIVE_RSSI_INFO_4, RSSI_PRI20_CHAIN2);
  1404. ppdu_info->rx_status.rssi[2] = rssi_value;
  1405. dp_nofl_debug("RSSI_PRI20_CHAIN2: %d\n", rssi_value);
  1406. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1407. RECEIVE_RSSI_INFO_6, RSSI_PRI20_CHAIN3);
  1408. ppdu_info->rx_status.rssi[3] = rssi_value;
  1409. dp_nofl_debug("RSSI_PRI20_CHAIN3: %d\n", rssi_value);
  1410. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1411. RECEIVE_RSSI_INFO_8, RSSI_PRI20_CHAIN4);
  1412. ppdu_info->rx_status.rssi[4] = rssi_value;
  1413. dp_nofl_debug("RSSI_PRI20_CHAIN4: %d\n", rssi_value);
  1414. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1415. RECEIVE_RSSI_INFO_10,
  1416. RSSI_PRI20_CHAIN5);
  1417. ppdu_info->rx_status.rssi[5] = rssi_value;
  1418. dp_nofl_debug("RSSI_PRI20_CHAIN5: %d\n", rssi_value);
  1419. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1420. RECEIVE_RSSI_INFO_12,
  1421. RSSI_PRI20_CHAIN6);
  1422. ppdu_info->rx_status.rssi[6] = rssi_value;
  1423. dp_nofl_debug("RSSI_PRI20_CHAIN6: %d\n", rssi_value);
  1424. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1425. RECEIVE_RSSI_INFO_14,
  1426. RSSI_PRI20_CHAIN7);
  1427. ppdu_info->rx_status.rssi[7] = rssi_value;
  1428. dp_nofl_debug("RSSI_PRI20_CHAIN7: %d\n", rssi_value);
  1429. break;
  1430. }
  1431. case WIFIPHYRX_OTHER_RECEIVE_INFO_E:
  1432. hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr,
  1433. ppdu_info);
  1434. break;
  1435. case WIFIRX_HEADER_E:
  1436. {
  1437. struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info;
  1438. if (ppdu_info->fcs_ok_cnt >=
  1439. HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) {
  1440. hal_err("Number of MPDUs(%d) per status buff exceeded",
  1441. ppdu_info->fcs_ok_cnt);
  1442. break;
  1443. }
  1444. /* Update first_msdu_payload for every mpdu and increment
  1445. * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV
  1446. */
  1447. ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload =
  1448. rx_tlv;
  1449. ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len;
  1450. ppdu_info->msdu_info.first_msdu_payload = rx_tlv;
  1451. ppdu_info->msdu_info.payload_len = tlv_len;
  1452. ppdu_info->user_id = user_id;
  1453. ppdu_info->hdr_len = tlv_len;
  1454. ppdu_info->data = rx_tlv;
  1455. ppdu_info->data += 4;
  1456. /* for every RX_HEADER TLV increment mpdu_cnt */
  1457. com_info->mpdu_cnt++;
  1458. return HAL_TLV_STATUS_HEADER;
  1459. }
  1460. case WIFIRX_MPDU_START_E:
  1461. {
  1462. uint8_t *rx_mpdu_start = (uint8_t *)rx_tlv;
  1463. uint32_t ppdu_id = HAL_RX_GET_PPDU_ID(rx_mpdu_start);
  1464. uint8_t filter_category = 0;
  1465. hal_update_frame_type_cnt(rx_mpdu_start, ppdu_info);
  1466. ppdu_info->nac_info.fc_valid =
  1467. HAL_RX_GET_FC_VALID(rx_mpdu_start);
  1468. ppdu_info->nac_info.to_ds_flag =
  1469. HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start);
  1470. ppdu_info->nac_info.frame_control =
  1471. HAL_RX_GET(rx_mpdu_start,
  1472. RX_MPDU_INFO_14,
  1473. MPDU_FRAME_CONTROL_FIELD);
  1474. ppdu_info->sw_frame_group_id =
  1475. HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start);
  1476. ppdu_info->rx_user_status[user_id].sw_peer_id =
  1477. HAL_RX_GET_SW_PEER_ID(rx_mpdu_start);
  1478. if (ppdu_info->sw_frame_group_id ==
  1479. HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) {
  1480. ppdu_info->rx_status.frame_control_info_valid =
  1481. ppdu_info->nac_info.fc_valid;
  1482. ppdu_info->rx_status.frame_control =
  1483. ppdu_info->nac_info.frame_control;
  1484. }
  1485. hal_get_mac_addr1(rx_mpdu_start,
  1486. ppdu_info);
  1487. ppdu_info->nac_info.mac_addr2_valid =
  1488. HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start);
  1489. *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] =
  1490. HAL_RX_GET(rx_mpdu_start,
  1491. RX_MPDU_INFO_16,
  1492. MAC_ADDR_AD2_15_0);
  1493. *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] =
  1494. HAL_RX_GET(rx_mpdu_start,
  1495. RX_MPDU_INFO_17,
  1496. MAC_ADDR_AD2_47_16);
  1497. if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) {
  1498. ppdu_info->rx_status.prev_ppdu_id = ppdu_id;
  1499. ppdu_info->rx_status.ppdu_len =
  1500. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13,
  1501. MPDU_LENGTH);
  1502. } else {
  1503. ppdu_info->rx_status.ppdu_len +=
  1504. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13,
  1505. MPDU_LENGTH);
  1506. }
  1507. filter_category =
  1508. HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start);
  1509. if (filter_category == 0)
  1510. ppdu_info->rx_status.rxpcu_filter_pass = 1;
  1511. else if (filter_category == 1)
  1512. ppdu_info->rx_status.monitor_direct_used = 1;
  1513. ppdu_info->nac_info.mcast_bcast =
  1514. HAL_RX_GET(rx_mpdu_start,
  1515. RX_MPDU_INFO_13,
  1516. MCAST_BCAST);
  1517. break;
  1518. }
  1519. case WIFIRX_MPDU_END_E:
  1520. ppdu_info->user_id = user_id;
  1521. ppdu_info->fcs_err =
  1522. HAL_RX_GET(rx_tlv, RX_MPDU_END_1,
  1523. FCS_ERR);
  1524. return HAL_TLV_STATUS_MPDU_END;
  1525. case WIFIRX_MSDU_END_E:
  1526. if (user_id < HAL_MAX_UL_MU_USERS) {
  1527. ppdu_info->rx_msdu_info[user_id].cce_metadata =
  1528. HAL_RX_MSDU_END_CCE_METADATA_GET(rx_tlv);
  1529. ppdu_info->rx_msdu_info[user_id].fse_metadata =
  1530. HAL_RX_MSDU_END_FSE_METADATA_GET(rx_tlv);
  1531. ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout =
  1532. HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(rx_tlv);
  1533. ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid =
  1534. HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(rx_tlv);
  1535. ppdu_info->rx_msdu_info[user_id].flow_idx =
  1536. HAL_RX_MSDU_END_FLOW_IDX_GET(rx_tlv);
  1537. }
  1538. return HAL_TLV_STATUS_MSDU_END;
  1539. case 0:
  1540. return HAL_TLV_STATUS_PPDU_DONE;
  1541. default:
  1542. if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info))
  1543. unhandled = false;
  1544. else
  1545. unhandled = true;
  1546. break;
  1547. }
  1548. if (!unhandled)
  1549. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1550. "%s TLV type: %d, TLV len:%d %s",
  1551. __func__, tlv_tag, tlv_len,
  1552. unhandled == true ? "unhandled" : "");
  1553. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1554. }
  1555. /**
  1556. * hal_tx_comp_get_release_reason_generic_li() - TQM Release reason
  1557. * @hal_desc: completion ring descriptor pointer
  1558. *
  1559. * This function will return the type of pointer - buffer or descriptor
  1560. *
  1561. * Return: buffer type
  1562. */
  1563. static inline uint8_t hal_tx_comp_get_release_reason_generic_li(void *hal_desc)
  1564. {
  1565. uint32_t comp_desc =
  1566. *(uint32_t *)(((uint8_t *)hal_desc) +
  1567. WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET);
  1568. return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >>
  1569. WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB;
  1570. }
  1571. /**
  1572. * hal_get_wbm_internal_error_generic_li() - is WBM internal error
  1573. * @hal_desc: completion ring descriptor pointer
  1574. *
  1575. * This function will return 0 or 1 - is it WBM internal error or not
  1576. *
  1577. * Return: uint8_t
  1578. */
  1579. static inline uint8_t hal_get_wbm_internal_error_generic_li(void *hal_desc)
  1580. {
  1581. uint32_t comp_desc =
  1582. *(uint32_t *)(((uint8_t *)hal_desc) +
  1583. HAL_WBM_INTERNAL_ERROR_OFFSET);
  1584. return (comp_desc & HAL_WBM_INTERNAL_ERROR_MASK) >>
  1585. HAL_WBM_INTERNAL_ERROR_LSB;
  1586. }
  1587. /**
  1588. * hal_rx_dump_mpdu_start_tlv_generic_li: dump RX mpdu_start TLV in structured
  1589. * human readable format.
  1590. * @mpdu_start: pointer the rx_attention TLV in pkt.
  1591. * @dbg_level: log level.
  1592. *
  1593. * Return: void
  1594. */
  1595. static inline void hal_rx_dump_mpdu_start_tlv_generic_li(void *mpdustart,
  1596. uint8_t dbg_level)
  1597. {
  1598. struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart;
  1599. struct rx_mpdu_info *mpdu_info =
  1600. (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details;
  1601. hal_verbose_debug(
  1602. "rx_mpdu_start tlv (1/5) - "
  1603. "rxpcu_mpdu_filter_in_category: %x "
  1604. "sw_frame_group_id: %x "
  1605. "ndp_frame: %x "
  1606. "phy_err: %x "
  1607. "phy_err_during_mpdu_header: %x "
  1608. "protocol_version_err: %x "
  1609. "ast_based_lookup_valid: %x "
  1610. "phy_ppdu_id: %x "
  1611. "ast_index: %x "
  1612. "sw_peer_id: %x "
  1613. "mpdu_frame_control_valid: %x "
  1614. "mpdu_duration_valid: %x "
  1615. "mac_addr_ad1_valid: %x "
  1616. "mac_addr_ad2_valid: %x "
  1617. "mac_addr_ad3_valid: %x "
  1618. "mac_addr_ad4_valid: %x "
  1619. "mpdu_sequence_control_valid: %x "
  1620. "mpdu_qos_control_valid: %x "
  1621. "mpdu_ht_control_valid: %x "
  1622. "frame_encryption_info_valid: %x ",
  1623. mpdu_info->rxpcu_mpdu_filter_in_category,
  1624. mpdu_info->sw_frame_group_id,
  1625. mpdu_info->ndp_frame,
  1626. mpdu_info->phy_err,
  1627. mpdu_info->phy_err_during_mpdu_header,
  1628. mpdu_info->protocol_version_err,
  1629. mpdu_info->ast_based_lookup_valid,
  1630. mpdu_info->phy_ppdu_id,
  1631. mpdu_info->ast_index,
  1632. mpdu_info->sw_peer_id,
  1633. mpdu_info->mpdu_frame_control_valid,
  1634. mpdu_info->mpdu_duration_valid,
  1635. mpdu_info->mac_addr_ad1_valid,
  1636. mpdu_info->mac_addr_ad2_valid,
  1637. mpdu_info->mac_addr_ad3_valid,
  1638. mpdu_info->mac_addr_ad4_valid,
  1639. mpdu_info->mpdu_sequence_control_valid,
  1640. mpdu_info->mpdu_qos_control_valid,
  1641. mpdu_info->mpdu_ht_control_valid,
  1642. mpdu_info->frame_encryption_info_valid);
  1643. hal_verbose_debug(
  1644. "rx_mpdu_start tlv (2/5) - "
  1645. "fr_ds: %x "
  1646. "to_ds: %x "
  1647. "encrypted: %x "
  1648. "mpdu_retry: %x "
  1649. "mpdu_sequence_number: %x "
  1650. "epd_en: %x "
  1651. "all_frames_shall_be_encrypted: %x "
  1652. "encrypt_type: %x "
  1653. "mesh_sta: %x "
  1654. "bssid_hit: %x "
  1655. "bssid_number: %x "
  1656. "tid: %x "
  1657. "pn_31_0: %x "
  1658. "pn_63_32: %x "
  1659. "pn_95_64: %x "
  1660. "pn_127_96: %x "
  1661. "peer_meta_data: %x "
  1662. "rxpt_classify_info.reo_destination_indication: %x "
  1663. "rxpt_classify_info.use_flow_id_toeplitz_clfy: %x "
  1664. "rx_reo_queue_desc_addr_31_0: %x ",
  1665. mpdu_info->fr_ds,
  1666. mpdu_info->to_ds,
  1667. mpdu_info->encrypted,
  1668. mpdu_info->mpdu_retry,
  1669. mpdu_info->mpdu_sequence_number,
  1670. mpdu_info->epd_en,
  1671. mpdu_info->all_frames_shall_be_encrypted,
  1672. mpdu_info->encrypt_type,
  1673. mpdu_info->mesh_sta,
  1674. mpdu_info->bssid_hit,
  1675. mpdu_info->bssid_number,
  1676. mpdu_info->tid,
  1677. mpdu_info->pn_31_0,
  1678. mpdu_info->pn_63_32,
  1679. mpdu_info->pn_95_64,
  1680. mpdu_info->pn_127_96,
  1681. mpdu_info->peer_meta_data,
  1682. mpdu_info->rxpt_classify_info_details.reo_destination_indication,
  1683. mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy,
  1684. mpdu_info->rx_reo_queue_desc_addr_31_0);
  1685. hal_verbose_debug(
  1686. "rx_mpdu_start tlv (3/5) - "
  1687. "rx_reo_queue_desc_addr_39_32: %x "
  1688. "receive_queue_number: %x "
  1689. "pre_delim_err_warning: %x "
  1690. "first_delim_err: %x "
  1691. "key_id_octet: %x "
  1692. "new_peer_entry: %x "
  1693. "decrypt_needed: %x "
  1694. "decap_type: %x "
  1695. "rx_insert_vlan_c_tag_padding: %x "
  1696. "rx_insert_vlan_s_tag_padding: %x "
  1697. "strip_vlan_c_tag_decap: %x "
  1698. "strip_vlan_s_tag_decap: %x "
  1699. "pre_delim_count: %x "
  1700. "ampdu_flag: %x "
  1701. "bar_frame: %x "
  1702. "mpdu_length: %x "
  1703. "first_mpdu: %x "
  1704. "mcast_bcast: %x "
  1705. "ast_index_not_found: %x "
  1706. "ast_index_timeout: %x ",
  1707. mpdu_info->rx_reo_queue_desc_addr_39_32,
  1708. mpdu_info->receive_queue_number,
  1709. mpdu_info->pre_delim_err_warning,
  1710. mpdu_info->first_delim_err,
  1711. mpdu_info->key_id_octet,
  1712. mpdu_info->new_peer_entry,
  1713. mpdu_info->decrypt_needed,
  1714. mpdu_info->decap_type,
  1715. mpdu_info->rx_insert_vlan_c_tag_padding,
  1716. mpdu_info->rx_insert_vlan_s_tag_padding,
  1717. mpdu_info->strip_vlan_c_tag_decap,
  1718. mpdu_info->strip_vlan_s_tag_decap,
  1719. mpdu_info->pre_delim_count,
  1720. mpdu_info->ampdu_flag,
  1721. mpdu_info->bar_frame,
  1722. mpdu_info->mpdu_length,
  1723. mpdu_info->first_mpdu,
  1724. mpdu_info->mcast_bcast,
  1725. mpdu_info->ast_index_not_found,
  1726. mpdu_info->ast_index_timeout);
  1727. hal_verbose_debug(
  1728. "rx_mpdu_start tlv (4/5) - "
  1729. "power_mgmt: %x "
  1730. "non_qos: %x "
  1731. "null_data: %x "
  1732. "mgmt_type: %x "
  1733. "ctrl_type: %x "
  1734. "more_data: %x "
  1735. "eosp: %x "
  1736. "fragment_flag: %x "
  1737. "order: %x "
  1738. "u_apsd_trigger: %x "
  1739. "encrypt_required: %x "
  1740. "directed: %x "
  1741. "mpdu_frame_control_field: %x "
  1742. "mpdu_duration_field: %x "
  1743. "mac_addr_ad1_31_0: %x "
  1744. "mac_addr_ad1_47_32: %x "
  1745. "mac_addr_ad2_15_0: %x "
  1746. "mac_addr_ad2_47_16: %x "
  1747. "mac_addr_ad3_31_0: %x "
  1748. "mac_addr_ad3_47_32: %x ",
  1749. mpdu_info->power_mgmt,
  1750. mpdu_info->non_qos,
  1751. mpdu_info->null_data,
  1752. mpdu_info->mgmt_type,
  1753. mpdu_info->ctrl_type,
  1754. mpdu_info->more_data,
  1755. mpdu_info->eosp,
  1756. mpdu_info->fragment_flag,
  1757. mpdu_info->order,
  1758. mpdu_info->u_apsd_trigger,
  1759. mpdu_info->encrypt_required,
  1760. mpdu_info->directed,
  1761. mpdu_info->mpdu_frame_control_field,
  1762. mpdu_info->mpdu_duration_field,
  1763. mpdu_info->mac_addr_ad1_31_0,
  1764. mpdu_info->mac_addr_ad1_47_32,
  1765. mpdu_info->mac_addr_ad2_15_0,
  1766. mpdu_info->mac_addr_ad2_47_16,
  1767. mpdu_info->mac_addr_ad3_31_0,
  1768. mpdu_info->mac_addr_ad3_47_32);
  1769. hal_verbose_debug(
  1770. "rx_mpdu_start tlv (5/5) - "
  1771. "mpdu_sequence_control_field: %x "
  1772. "mac_addr_ad4_31_0: %x "
  1773. "mac_addr_ad4_47_32: %x "
  1774. "mpdu_qos_control_field: %x "
  1775. "mpdu_ht_control_field: %x ",
  1776. mpdu_info->mpdu_sequence_control_field,
  1777. mpdu_info->mac_addr_ad4_31_0,
  1778. mpdu_info->mac_addr_ad4_47_32,
  1779. mpdu_info->mpdu_qos_control_field,
  1780. mpdu_info->mpdu_ht_control_field);
  1781. }
  1782. /**
  1783. * hal_tx_set_pcp_tid_map_generic_li() - Configure default PCP to TID map table
  1784. * @soc: HAL SoC context
  1785. * @map: PCP-TID mapping table
  1786. *
  1787. * PCP are mapped to 8 TID values using TID values programmed
  1788. * in one set of mapping registers PCP_TID_MAP_<0 to 6>
  1789. * The mapping register has TID mapping for 8 PCP values
  1790. *
  1791. * Return: none
  1792. */
  1793. static void hal_tx_set_pcp_tid_map_generic_li(struct hal_soc *soc, uint8_t *map)
  1794. {
  1795. uint32_t addr, value;
  1796. addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
  1797. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
  1798. value = (map[0] |
  1799. (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) |
  1800. (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) |
  1801. (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) |
  1802. (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) |
  1803. (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) |
  1804. (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) |
  1805. (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT));
  1806. HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
  1807. }
  1808. /**
  1809. * hal_tx_update_pcp_tid_generic_li() - Update the pcp tid map table with
  1810. * value received from user-space
  1811. * @soc: HAL SoC context
  1812. * @pcp: pcp value
  1813. * @tid : tid value
  1814. *
  1815. * Return: void
  1816. */
  1817. static void
  1818. hal_tx_update_pcp_tid_generic_li(struct hal_soc *soc,
  1819. uint8_t pcp, uint8_t tid)
  1820. {
  1821. uint32_t addr, value, regval;
  1822. addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
  1823. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
  1824. value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp);
  1825. /* Read back previous PCP TID config and update
  1826. * with new config.
  1827. */
  1828. regval = HAL_REG_READ(soc, addr);
  1829. regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp));
  1830. regval |= value;
  1831. HAL_REG_WRITE(soc, addr,
  1832. (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
  1833. }
  1834. /**
  1835. * hal_tx_update_tidmap_prty_generic_li() - Update the tid map priority
  1836. * @soc: HAL SoC context
  1837. * @val: priority value
  1838. *
  1839. * Return: void
  1840. */
  1841. static
  1842. void hal_tx_update_tidmap_prty_generic_li(struct hal_soc *soc, uint8_t value)
  1843. {
  1844. uint32_t addr;
  1845. addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR(
  1846. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
  1847. HAL_REG_WRITE(soc, addr,
  1848. (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK));
  1849. }
  1850. /**
  1851. * hal_rx_msdu_packet_metadata_get(): API to get the
  1852. * msdu information from rx_msdu_end TLV
  1853. *
  1854. * @ buf: pointer to the start of RX PKT TLV headers
  1855. * @ hal_rx_msdu_metadata: pointer to the msdu info structure
  1856. */
  1857. static void
  1858. hal_rx_msdu_packet_metadata_get_generic_li(uint8_t *buf,
  1859. void *pkt_msdu_metadata)
  1860. {
  1861. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1862. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1863. struct hal_rx_msdu_metadata *msdu_metadata =
  1864. (struct hal_rx_msdu_metadata *)pkt_msdu_metadata;
  1865. msdu_metadata->l3_hdr_pad =
  1866. HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
  1867. msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end);
  1868. msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
  1869. msdu_metadata->sa_sw_peer_id =
  1870. HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
  1871. }
  1872. /**
  1873. * hal_rx_msdu_end_offset_get_generic(): API to get the
  1874. * msdu_end structure offset rx_pkt_tlv structure
  1875. *
  1876. * NOTE: API returns offset of msdu_end TLV from structure
  1877. * rx_pkt_tlvs
  1878. */
  1879. static uint32_t hal_rx_msdu_end_offset_get_generic(void)
  1880. {
  1881. return RX_PKT_TLV_OFFSET(msdu_end_tlv);
  1882. }
  1883. /**
  1884. * hal_rx_attn_offset_get_generic(): API to get the
  1885. * msdu_end structure offset rx_pkt_tlv structure
  1886. *
  1887. * NOTE: API returns offset of attn TLV from structure
  1888. * rx_pkt_tlvs
  1889. */
  1890. static uint32_t hal_rx_attn_offset_get_generic(void)
  1891. {
  1892. return RX_PKT_TLV_OFFSET(attn_tlv);
  1893. }
  1894. /**
  1895. * hal_rx_msdu_start_offset_get_generic(): API to get the
  1896. * msdu_start structure offset rx_pkt_tlv structure
  1897. *
  1898. * NOTE: API returns offset of attn TLV from structure
  1899. * rx_pkt_tlvs
  1900. */
  1901. static uint32_t hal_rx_msdu_start_offset_get_generic(void)
  1902. {
  1903. return RX_PKT_TLV_OFFSET(msdu_start_tlv);
  1904. }
  1905. /**
  1906. * hal_rx_mpdu_start_offset_get_generic(): API to get the
  1907. * mpdu_start structure offset rx_pkt_tlv structure
  1908. *
  1909. * NOTE: API returns offset of attn TLV from structure
  1910. * rx_pkt_tlvs
  1911. */
  1912. static uint32_t hal_rx_mpdu_start_offset_get_generic(void)
  1913. {
  1914. return RX_PKT_TLV_OFFSET(mpdu_start_tlv);
  1915. }
  1916. /**
  1917. * hal_rx_mpdu_end_offset_get_generic(): API to get the
  1918. * mpdu_end structure offset rx_pkt_tlv structure
  1919. *
  1920. * NOTE: API returns offset of attn TLV from structure
  1921. * rx_pkt_tlvs
  1922. */
  1923. static uint32_t hal_rx_mpdu_end_offset_get_generic(void)
  1924. {
  1925. return RX_PKT_TLV_OFFSET(mpdu_end_tlv);
  1926. }
  1927. #ifndef NO_RX_PKT_HDR_TLV
  1928. static uint32_t hal_rx_pkt_tlv_offset_get_generic(void)
  1929. {
  1930. return RX_PKT_TLV_OFFSET(pkt_hdr_tlv);
  1931. }
  1932. #endif
  1933. #if defined(QDF_BIG_ENDIAN_MACHINE)
  1934. /**
  1935. * hal_setup_reo_swap() - Set the swap flag for big endian machines
  1936. * @soc: HAL soc handle
  1937. *
  1938. * Return: None
  1939. */
  1940. static inline void hal_setup_reo_swap(struct hal_soc *soc)
  1941. {
  1942. uint32_t reg_val;
  1943. reg_val = HAL_REG_READ(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(
  1944. SEQ_WCSS_UMAC_REO_REG_OFFSET));
  1945. reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, WRITE_STRUCT_SWAP, 1);
  1946. reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, READ_STRUCT_SWAP, 1);
  1947. HAL_REG_WRITE(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(
  1948. SEQ_WCSS_UMAC_REO_REG_OFFSET), reg_val);
  1949. }
  1950. #else
  1951. static inline void hal_setup_reo_swap(struct hal_soc *soc)
  1952. {
  1953. }
  1954. #endif
  1955. /**
  1956. * hal_reo_setup_generic_li - Initialize HW REO block
  1957. *
  1958. * @hal_soc: Opaque HAL SOC handle
  1959. * @reo_params: parameters needed by HAL for REO config
  1960. * @qref_reset: reset qref
  1961. */
  1962. static
  1963. void hal_reo_setup_generic_li(struct hal_soc *soc, void *reoparams,
  1964. int qref_reset)
  1965. {
  1966. uint32_t reg_val;
  1967. struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams;
  1968. reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR(
  1969. SEQ_WCSS_UMAC_REO_REG_OFFSET));
  1970. hal_reo_config(soc, reg_val, reo_params);
  1971. /* Other ring enable bits and REO_ENABLE will be set by FW */
  1972. /* TODO: Setup destination ring mapping if enabled */
  1973. /* TODO: Error destination ring setting is left to default.
  1974. * Default setting is to send all errors to release ring.
  1975. */
  1976. /* Set the reo descriptor swap bits in case of BIG endian platform */
  1977. hal_setup_reo_swap(soc);
  1978. HAL_REG_WRITE(soc,
  1979. HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
  1980. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1981. HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000);
  1982. HAL_REG_WRITE(soc,
  1983. HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
  1984. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1985. (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
  1986. HAL_REG_WRITE(soc,
  1987. HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
  1988. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1989. (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
  1990. HAL_REG_WRITE(soc,
  1991. HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
  1992. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1993. (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000));
  1994. /*
  1995. * When hash based routing is enabled, routing of the rx packet
  1996. * is done based on the following value: 1 _ _ _ _ The last 4
  1997. * bits are based on hash[3:0]. This means the possible values
  1998. * are 0x10 to 0x1f. This value is used to look-up the
  1999. * ring ID configured in Destination_Ring_Ctrl_IX_* register.
  2000. * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3
  2001. * registers need to be configured to set-up the 16 entries to
  2002. * map the hash values to a ring number. There are 3 bits per
  2003. * hash entry – which are mapped as follows:
  2004. * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI),
  2005. * 7: NOT_USED.
  2006. */
  2007. if (reo_params->rx_hash_enabled) {
  2008. if (reo_params->remap0)
  2009. HAL_REG_WRITE(soc,
  2010. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(
  2011. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  2012. reo_params->remap0);
  2013. hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 0x%x",
  2014. HAL_REG_READ(soc,
  2015. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(
  2016. SEQ_WCSS_UMAC_REO_REG_OFFSET)));
  2017. HAL_REG_WRITE(soc,
  2018. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
  2019. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  2020. reo_params->remap1);
  2021. hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x",
  2022. HAL_REG_READ(soc,
  2023. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
  2024. SEQ_WCSS_UMAC_REO_REG_OFFSET)));
  2025. HAL_REG_WRITE(soc,
  2026. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
  2027. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  2028. reo_params->remap2);
  2029. hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x",
  2030. HAL_REG_READ(soc,
  2031. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
  2032. SEQ_WCSS_UMAC_REO_REG_OFFSET)));
  2033. }
  2034. /* TODO: Check if the following registers shoould be setup by host:
  2035. * AGING_CONTROL
  2036. * HIGH_MEMORY_THRESHOLD
  2037. * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2]
  2038. * GLOBAL_LINK_DESC_COUNT_CTRL
  2039. */
  2040. }
  2041. /**
  2042. * hal_setup_link_idle_list_generic_li - Setup scattered idle list using the
  2043. * buffer list provided
  2044. *
  2045. * @hal_soc: Opaque HAL SOC handle
  2046. * @scatter_bufs_base_paddr: Array of physical base addresses
  2047. * @scatter_bufs_base_vaddr: Array of virtual base addresses
  2048. * @num_scatter_bufs: Number of scatter buffers in the above lists
  2049. * @scatter_buf_size: Size of each scatter buffer
  2050. * @last_buf_end_offset: Offset to the last entry
  2051. * @num_entries: Total entries of all scatter bufs
  2052. *
  2053. * Return: None
  2054. */
  2055. static void
  2056. hal_setup_link_idle_list_generic_li(struct hal_soc *soc,
  2057. qdf_dma_addr_t scatter_bufs_base_paddr[],
  2058. void *scatter_bufs_base_vaddr[],
  2059. uint32_t num_scatter_bufs,
  2060. uint32_t scatter_buf_size,
  2061. uint32_t last_buf_end_offset,
  2062. uint32_t num_entries)
  2063. {
  2064. int i;
  2065. uint32_t *prev_buf_link_ptr = NULL;
  2066. uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size;
  2067. uint32_t val;
  2068. /* Link the scatter buffers */
  2069. for (i = 0; i < num_scatter_bufs; i++) {
  2070. if (i > 0) {
  2071. prev_buf_link_ptr[0] =
  2072. scatter_bufs_base_paddr[i] & 0xffffffff;
  2073. prev_buf_link_ptr[1] = HAL_SM(
  2074. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  2075. BASE_ADDRESS_39_32,
  2076. ((uint64_t)(scatter_bufs_base_paddr[i])
  2077. >> 32)) | HAL_SM(
  2078. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  2079. ADDRESS_MATCH_TAG,
  2080. ADDRESS_MATCH_TAG_VAL);
  2081. }
  2082. prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] +
  2083. scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE);
  2084. }
  2085. /* TBD: Register programming partly based on MLD & the rest based on
  2086. * inputs from HW team. Not complete yet.
  2087. */
  2088. reg_scatter_buf_size = (scatter_buf_size -
  2089. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) / 64;
  2090. reg_tot_scatter_buf_size = ((scatter_buf_size -
  2091. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs) / 64;
  2092. HAL_REG_WRITE(soc,
  2093. HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR
  2094. (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  2095. HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL,
  2096. SCATTER_BUFFER_SIZE,
  2097. reg_scatter_buf_size) |
  2098. HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL,
  2099. LINK_DESC_IDLE_LIST_MODE, 0x1));
  2100. HAL_REG_WRITE(soc,
  2101. HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR
  2102. (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  2103. HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE,
  2104. SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST,
  2105. reg_tot_scatter_buf_size));
  2106. HAL_REG_WRITE(soc,
  2107. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR
  2108. (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  2109. scatter_bufs_base_paddr[0] & 0xffffffff);
  2110. HAL_REG_WRITE(soc,
  2111. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR
  2112. (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  2113. ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) &
  2114. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK);
  2115. HAL_REG_WRITE(soc,
  2116. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR
  2117. (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  2118. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  2119. BASE_ADDRESS_39_32,
  2120. ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32)) |
  2121. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  2122. ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL));
  2123. /* ADDRESS_MATCH_TAG field in the above register is expected to match
  2124. * with the upper bits of link pointer. The above write sets this field
  2125. * to zero and we are also setting the upper bits of link pointers to
  2126. * zero while setting up the link list of scatter buffers above
  2127. */
  2128. /* Setup head and tail pointers for the idle list */
  2129. HAL_REG_WRITE(soc,
  2130. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR
  2131. (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  2132. scatter_bufs_base_paddr[num_scatter_bufs - 1] &
  2133. 0xffffffff);
  2134. HAL_REG_WRITE(soc,
  2135. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR
  2136. (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  2137. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
  2138. BUFFER_ADDRESS_39_32,
  2139. ((uint64_t)(scatter_bufs_base_paddr
  2140. [num_scatter_bufs - 1]) >> 32)) |
  2141. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
  2142. HEAD_POINTER_OFFSET, last_buf_end_offset >> 2));
  2143. HAL_REG_WRITE(soc,
  2144. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR
  2145. (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  2146. scatter_bufs_base_paddr[0] & 0xffffffff);
  2147. HAL_REG_WRITE(soc,
  2148. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR
  2149. (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  2150. scatter_bufs_base_paddr[0] & 0xffffffff);
  2151. HAL_REG_WRITE(soc,
  2152. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR
  2153. (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  2154. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
  2155. BUFFER_ADDRESS_39_32,
  2156. ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32)) |
  2157. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
  2158. TAIL_POINTER_OFFSET, 0));
  2159. HAL_REG_WRITE(soc,
  2160. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR
  2161. (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2 * num_entries);
  2162. /* Set RING_ID_DISABLE */
  2163. val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1);
  2164. /*
  2165. * SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence
  2166. * check the presence of the bit before toggling it.
  2167. */
  2168. #ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK
  2169. val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1);
  2170. #endif
  2171. HAL_REG_WRITE(soc,
  2172. HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR
  2173. (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  2174. val);
  2175. }
  2176. #ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET
  2177. /**
  2178. * hal_tx_desc_set_search_type_generic_li - Set the search type value
  2179. * @desc: Handle to Tx Descriptor
  2180. * @search_type: search type
  2181. * 0 – Normal search
  2182. * 1 – Index based address search
  2183. * 2 – Index based flow search
  2184. *
  2185. * Return: void
  2186. */
  2187. static inline
  2188. void hal_tx_desc_set_search_type_generic_li(void *desc, uint8_t search_type)
  2189. {
  2190. HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |=
  2191. HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type);
  2192. }
  2193. #else
  2194. static inline
  2195. void hal_tx_desc_set_search_type_generic_li(void *desc, uint8_t search_type)
  2196. {
  2197. }
  2198. #endif
  2199. #ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET
  2200. /**
  2201. * hal_tx_desc_set_search_index_generic_li - Set the search index value
  2202. * @desc: Handle to Tx Descriptor
  2203. * @search_index: The index that will be used for index based address or
  2204. * flow search. The field is valid when 'search_type' is
  2205. * 1 0r 2
  2206. *
  2207. * Return: void
  2208. */
  2209. static inline
  2210. void hal_tx_desc_set_search_index_generic_li(void *desc, uint32_t search_index)
  2211. {
  2212. HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |=
  2213. HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index);
  2214. }
  2215. #else
  2216. static inline
  2217. void hal_tx_desc_set_search_index_generic_li(void *desc, uint32_t search_index)
  2218. {
  2219. }
  2220. #endif
  2221. #ifdef TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET
  2222. /**
  2223. * hal_tx_desc_set_cache_set_num_generic_li - Set the cache-set-num value
  2224. * @desc: Handle to Tx Descriptor
  2225. * @cache_num: Cache set number that should be used to cache the index
  2226. * based search results, for address and flow search.
  2227. * This value should be equal to LSB four bits of the hash value
  2228. * of match data, in case of search index points to an entry
  2229. * which may be used in content based search also. The value can
  2230. * be anything when the entry pointed by search index will not be
  2231. * used for content based search.
  2232. *
  2233. * Return: void
  2234. */
  2235. static inline
  2236. void hal_tx_desc_set_cache_set_num_generic_li(void *desc, uint8_t cache_num)
  2237. {
  2238. HAL_SET_FLD(desc, TCL_DATA_CMD_5, CACHE_SET_NUM) |=
  2239. HAL_TX_SM(TCL_DATA_CMD_5, CACHE_SET_NUM, cache_num);
  2240. }
  2241. #else
  2242. static inline
  2243. void hal_tx_desc_set_cache_set_num_generic_li(void *desc, uint8_t cache_num)
  2244. {
  2245. }
  2246. #endif
  2247. #ifdef WLAN_SUPPORT_RX_FISA
  2248. /**
  2249. * hal_rx_flow_get_tuple_info_li() - Setup a flow search entry in HW FST
  2250. * @fst: Pointer to the Rx Flow Search Table
  2251. * @hal_hash: HAL 5 tuple hash
  2252. * @tuple_info: 5-tuple info of the flow returned to the caller
  2253. *
  2254. * Return: Success/Failure
  2255. */
  2256. static void *
  2257. hal_rx_flow_get_tuple_info_li(uint8_t *rx_fst, uint32_t hal_hash,
  2258. uint8_t *flow_tuple_info)
  2259. {
  2260. struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
  2261. void *hal_fse = NULL;
  2262. struct hal_flow_tuple_info *tuple_info
  2263. = (struct hal_flow_tuple_info *)flow_tuple_info;
  2264. hal_fse = (uint8_t *)fst->base_vaddr +
  2265. (hal_hash * HAL_RX_FST_ENTRY_SIZE);
  2266. if (!hal_fse || !tuple_info)
  2267. return NULL;
  2268. if (!HAL_GET_FLD(hal_fse, RX_FLOW_SEARCH_ENTRY_9, VALID))
  2269. return NULL;
  2270. tuple_info->src_ip_127_96 =
  2271. qdf_ntohl(HAL_GET_FLD(hal_fse,
  2272. RX_FLOW_SEARCH_ENTRY_0,
  2273. SRC_IP_127_96));
  2274. tuple_info->src_ip_95_64 =
  2275. qdf_ntohl(HAL_GET_FLD(hal_fse,
  2276. RX_FLOW_SEARCH_ENTRY_1,
  2277. SRC_IP_95_64));
  2278. tuple_info->src_ip_63_32 =
  2279. qdf_ntohl(HAL_GET_FLD(hal_fse,
  2280. RX_FLOW_SEARCH_ENTRY_2,
  2281. SRC_IP_63_32));
  2282. tuple_info->src_ip_31_0 =
  2283. qdf_ntohl(HAL_GET_FLD(hal_fse,
  2284. RX_FLOW_SEARCH_ENTRY_3,
  2285. SRC_IP_31_0));
  2286. tuple_info->dest_ip_127_96 =
  2287. qdf_ntohl(HAL_GET_FLD(hal_fse,
  2288. RX_FLOW_SEARCH_ENTRY_4,
  2289. DEST_IP_127_96));
  2290. tuple_info->dest_ip_95_64 =
  2291. qdf_ntohl(HAL_GET_FLD(hal_fse,
  2292. RX_FLOW_SEARCH_ENTRY_5,
  2293. DEST_IP_95_64));
  2294. tuple_info->dest_ip_63_32 =
  2295. qdf_ntohl(HAL_GET_FLD(hal_fse,
  2296. RX_FLOW_SEARCH_ENTRY_6,
  2297. DEST_IP_63_32));
  2298. tuple_info->dest_ip_31_0 =
  2299. qdf_ntohl(HAL_GET_FLD(hal_fse,
  2300. RX_FLOW_SEARCH_ENTRY_7,
  2301. DEST_IP_31_0));
  2302. tuple_info->dest_port = HAL_GET_FLD(hal_fse,
  2303. RX_FLOW_SEARCH_ENTRY_8,
  2304. DEST_PORT);
  2305. tuple_info->src_port = HAL_GET_FLD(hal_fse,
  2306. RX_FLOW_SEARCH_ENTRY_8,
  2307. SRC_PORT);
  2308. tuple_info->l4_protocol = HAL_GET_FLD(hal_fse,
  2309. RX_FLOW_SEARCH_ENTRY_9,
  2310. L4_PROTOCOL);
  2311. return hal_fse;
  2312. }
  2313. /**
  2314. * hal_rx_flow_delete_entry_li() - Setup a flow search entry in HW FST
  2315. * @fst: Pointer to the Rx Flow Search Table
  2316. * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST
  2317. *
  2318. * Return: Success/Failure
  2319. */
  2320. static QDF_STATUS
  2321. hal_rx_flow_delete_entry_li(uint8_t *rx_fst, void *hal_rx_fse)
  2322. {
  2323. uint8_t *fse = (uint8_t *)hal_rx_fse;
  2324. if (!HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID))
  2325. return QDF_STATUS_E_NOENT;
  2326. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID);
  2327. return QDF_STATUS_SUCCESS;
  2328. }
  2329. /**
  2330. * hal_rx_fst_get_fse_size_li() - Retrieve the size of each entry
  2331. *
  2332. * Return: size of each entry/flow in Rx FST
  2333. */
  2334. static inline uint32_t
  2335. hal_rx_fst_get_fse_size_li(void)
  2336. {
  2337. return HAL_RX_FST_ENTRY_SIZE;
  2338. }
  2339. #else
  2340. static inline void *
  2341. hal_rx_flow_get_tuple_info_li(uint8_t *rx_fst, uint32_t hal_hash,
  2342. uint8_t *flow_tuple_info)
  2343. {
  2344. return NULL;
  2345. }
  2346. static inline QDF_STATUS
  2347. hal_rx_flow_delete_entry_li(uint8_t *rx_fst, void *hal_rx_fse)
  2348. {
  2349. return QDF_STATUS_SUCCESS;
  2350. }
  2351. static inline uint32_t
  2352. hal_rx_fst_get_fse_size_li(void)
  2353. {
  2354. return 0;
  2355. }
  2356. #endif /* WLAN_SUPPORT_RX_FISA */
  2357. /**
  2358. * hal_rx_get_frame_ctrl_field(): Function to retrieve frame control field
  2359. *
  2360. * @nbuf: Network buffer
  2361. * Returns: rx more fragment bit
  2362. *
  2363. */
  2364. static uint16_t hal_rx_get_frame_ctrl_field_li(uint8_t *buf)
  2365. {
  2366. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  2367. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  2368. uint16_t frame_ctrl = 0;
  2369. frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info);
  2370. return frame_ctrl;
  2371. }
  2372. #endif /* _HAL_LI_GENERIC_API_H_ */