hal_li_generic_api.c 37 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "hal_li_api.h"
  20. #include "hal_li_hw_headers.h"
  21. #include "hal_li_reo.h"
  22. #include "hal_rx.h"
  23. #include "hal_li_rx.h"
  24. #include "hal_tx.h"
  25. #include <hal_api_mon.h>
  26. static uint16_t hal_get_rx_max_ba_window_li(int tid)
  27. {
  28. return HAL_RX_BA_WINDOW_256;
  29. }
  30. static uint32_t hal_get_reo_qdesc_size_li(uint32_t ba_window_size, int tid)
  31. {
  32. /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for
  33. * NON_QOS_TID until HW issues are resolved.
  34. */
  35. if (tid != HAL_NON_QOS_TID)
  36. ba_window_size = hal_get_rx_max_ba_window_li(tid);
  37. /* Return descriptor size corresponding to window size of 2 since
  38. * we set ba_window_size to 2 while setting up REO descriptors as
  39. * a WAR to get 2k jump exception aggregates are received without
  40. * a BA session.
  41. */
  42. if (ba_window_size <= 1) {
  43. if (tid != HAL_NON_QOS_TID)
  44. return sizeof(struct rx_reo_queue) +
  45. sizeof(struct rx_reo_queue_ext);
  46. else
  47. return sizeof(struct rx_reo_queue);
  48. }
  49. if (ba_window_size <= 105)
  50. return sizeof(struct rx_reo_queue) +
  51. sizeof(struct rx_reo_queue_ext);
  52. if (ba_window_size <= 210)
  53. return sizeof(struct rx_reo_queue) +
  54. (2 * sizeof(struct rx_reo_queue_ext));
  55. return sizeof(struct rx_reo_queue) +
  56. (3 * sizeof(struct rx_reo_queue_ext));
  57. }
  58. void hal_set_link_desc_addr_li(void *desc, uint32_t cookie,
  59. qdf_dma_addr_t link_desc_paddr,
  60. uint8_t bm_id)
  61. {
  62. uint32_t *buf_addr = (uint32_t *)desc;
  63. HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0,
  64. link_desc_paddr & 0xffffffff);
  65. HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32,
  66. (uint64_t)link_desc_paddr >> 32);
  67. HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, RETURN_BUFFER_MANAGER,
  68. bm_id);
  69. HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE,
  70. cookie);
  71. }
  72. void hal_tx_init_data_ring_li(hal_soc_handle_t hal_soc_hdl,
  73. hal_ring_handle_t hal_ring_hdl)
  74. {
  75. uint8_t *desc_addr;
  76. struct hal_srng_params srng_params;
  77. uint32_t desc_size;
  78. uint32_t num_desc;
  79. hal_get_srng_params(hal_soc_hdl, hal_ring_hdl, &srng_params);
  80. desc_addr = (uint8_t *)srng_params.ring_base_vaddr;
  81. desc_size = sizeof(struct tcl_data_cmd);
  82. num_desc = srng_params.num_entries;
  83. while (num_desc) {
  84. HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG,
  85. desc_size);
  86. desc_addr += (desc_size + sizeof(struct tlv_32_hdr));
  87. num_desc--;
  88. }
  89. }
  90. /*
  91. * hal_rx_msdu_is_wlan_mcast_generic_li(): Check if the buffer is for multicast
  92. * address
  93. * @nbuf: Network buffer
  94. *
  95. * Returns: flag to indicate whether the nbuf has MC/BC address
  96. */
  97. static uint32_t hal_rx_msdu_is_wlan_mcast_generic_li(qdf_nbuf_t nbuf)
  98. {
  99. uint8_t *buf = qdf_nbuf_data(nbuf);
  100. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  101. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  102. return rx_attn->mcast_bcast;
  103. }
  104. /**
  105. * hal_rx_tlv_decap_format_get_li() - Get packet decap format from the TLV
  106. * @hw_desc_addr: rx tlv desc
  107. *
  108. * Return: pkt decap format
  109. */
  110. static uint32_t hal_rx_tlv_decap_format_get_li(void *hw_desc_addr)
  111. {
  112. struct rx_msdu_start *rx_msdu_start;
  113. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  114. rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
  115. return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT);
  116. }
  117. /**
  118. * hal_rx_dump_pkt_tlvs_li(): API to print all member elements of
  119. * RX TLVs
  120. * @ buf: pointer the pkt buffer.
  121. * @ dbg_level: log level.
  122. *
  123. * Return: void
  124. */
  125. static void hal_rx_dump_pkt_tlvs_li(hal_soc_handle_t hal_soc_hdl,
  126. uint8_t *buf, uint8_t dbg_level)
  127. {
  128. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  129. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  130. struct rx_mpdu_start *mpdu_start =
  131. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  132. struct rx_msdu_start *msdu_start =
  133. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  134. struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
  135. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  136. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  137. hal_rx_dump_rx_attention_tlv(rx_attn, dbg_level);
  138. hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level, hal_soc);
  139. hal_rx_dump_msdu_start_tlv(hal_soc, msdu_start, dbg_level);
  140. hal_rx_dump_mpdu_end_tlv(mpdu_end, dbg_level);
  141. hal_rx_dump_msdu_end_tlv(hal_soc, msdu_end, dbg_level);
  142. hal_rx_dump_pkt_hdr_tlv(pkt_tlvs, dbg_level);
  143. }
  144. /**
  145. * hal_rx_tlv_get_offload_info_li() - Get the offload info from TLV
  146. * @rx_tlv: RX tlv start address in buffer
  147. * @offload_info: Buffer to store the offload info
  148. *
  149. * Return: 0 on success, -EINVAL on failure.
  150. */
  151. static int
  152. hal_rx_tlv_get_offload_info_li(uint8_t *rx_tlv,
  153. struct hal_offload_info *offload_info)
  154. {
  155. offload_info->flow_id = HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(rx_tlv);
  156. offload_info->ipv6_proto = HAL_RX_TLV_GET_IPV6(rx_tlv);
  157. offload_info->lro_eligible = HAL_RX_TLV_GET_LRO_ELIGIBLE(rx_tlv);
  158. offload_info->tcp_proto = HAL_RX_TLV_GET_TCP_PROTO(rx_tlv);
  159. if (offload_info->tcp_proto) {
  160. offload_info->tcp_pure_ack =
  161. HAL_RX_TLV_GET_TCP_PURE_ACK(rx_tlv);
  162. offload_info->tcp_offset = HAL_RX_TLV_GET_TCP_OFFSET(rx_tlv);
  163. offload_info->tcp_win = HAL_RX_TLV_GET_TCP_WIN(rx_tlv);
  164. offload_info->tcp_seq_num = HAL_RX_TLV_GET_TCP_SEQ(rx_tlv);
  165. offload_info->tcp_ack_num = HAL_RX_TLV_GET_TCP_ACK(rx_tlv);
  166. }
  167. return 0;
  168. }
  169. /*
  170. * hal_rx_attn_phy_ppdu_id_get(): get phy_ppdu_id value
  171. * from rx attention
  172. * @buf: pointer to rx_pkt_tlvs
  173. *
  174. * Return: phy_ppdu_id
  175. */
  176. static uint16_t hal_rx_attn_phy_ppdu_id_get_li(uint8_t *buf)
  177. {
  178. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  179. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  180. uint16_t phy_ppdu_id;
  181. phy_ppdu_id = HAL_RX_ATTN_PHY_PPDU_ID_GET(rx_attn);
  182. return phy_ppdu_id;
  183. }
  184. /**
  185. * hal_rx_msdu_start_msdu_len_get(): API to get the MSDU length
  186. * from rx_msdu_start TLV
  187. *
  188. * @ buf: pointer to the start of RX PKT TLV headers
  189. * Return: msdu length
  190. */
  191. static uint32_t hal_rx_msdu_start_msdu_len_get_li(uint8_t *buf)
  192. {
  193. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  194. struct rx_msdu_start *msdu_start =
  195. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  196. uint32_t msdu_len;
  197. msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start);
  198. return msdu_len;
  199. }
  200. /**
  201. * hal_rx_get_proto_params_li() - Get l4 proto values from TLV
  202. * @buf: rx tlv address
  203. * @proto_params: Buffer to store proto parameters
  204. *
  205. * Return: 0 on success.
  206. */
  207. static int hal_rx_get_proto_params_li(uint8_t *buf, void *proto_params)
  208. {
  209. struct hal_proto_params *param =
  210. (struct hal_proto_params *)proto_params;
  211. param->tcp_proto = HAL_RX_TLV_GET_TCP_PROTO(buf);
  212. param->udp_proto = HAL_RX_TLV_GET_UDP_PROTO(buf);
  213. param->ipv6_proto = HAL_RX_TLV_GET_IPV6(buf);
  214. return 0;
  215. }
  216. /**
  217. * hal_rx_get_l3_l4_offsets_li() - Get l3/l4 header offset from TLV
  218. * @buf: rx tlv start address
  219. * @l3_hdr_offset: buffer to store l3 offset
  220. * @l4_hdr_offset: buffer to store l4 offset
  221. *
  222. * Return: 0 on success.
  223. */
  224. static int hal_rx_get_l3_l4_offsets_li(uint8_t *buf, uint32_t *l3_hdr_offset,
  225. uint32_t *l4_hdr_offset)
  226. {
  227. *l3_hdr_offset = HAL_RX_TLV_GET_IP_OFFSET(buf);
  228. *l4_hdr_offset = HAL_RX_TLV_GET_TCP_OFFSET(buf);
  229. return 0;
  230. }
  231. /**
  232. * hal_rx_tlv_get_pn_num_li() - Get packet number from RX TLV
  233. * @buf: rx tlv address
  234. * @pn_num: buffer to store packet number
  235. *
  236. * Return: None
  237. */
  238. static inline void hal_rx_tlv_get_pn_num_li(uint8_t *buf, uint64_t *pn_num)
  239. {
  240. struct rx_pkt_tlvs *rx_pkt_tlv =
  241. (struct rx_pkt_tlvs *)buf;
  242. struct rx_mpdu_info *rx_mpdu_info_details =
  243. &rx_pkt_tlv->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
  244. pn_num[0] = rx_mpdu_info_details->pn_31_0;
  245. pn_num[0] |=
  246. ((uint64_t)rx_mpdu_info_details->pn_63_32 << 32);
  247. pn_num[1] = rx_mpdu_info_details->pn_95_64;
  248. pn_num[1] |=
  249. ((uint64_t)rx_mpdu_info_details->pn_127_96 << 32);
  250. }
  251. #ifdef NO_RX_PKT_HDR_TLV
  252. /**
  253. * hal_rx_pkt_hdr_get_li() - Get rx packet header start address.
  254. * @buf: packet start address
  255. *
  256. * Return: packet data start address.
  257. */
  258. static inline uint8_t *hal_rx_pkt_hdr_get_li(uint8_t *buf)
  259. {
  260. return buf + RX_PKT_TLVS_LEN;
  261. }
  262. #else
  263. static inline uint8_t *hal_rx_pkt_hdr_get_li(uint8_t *buf)
  264. {
  265. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  266. return pkt_tlvs->pkt_hdr_tlv.rx_pkt_hdr;
  267. }
  268. #endif
  269. /**
  270. * hal_rx_priv_info_set_in_tlv_li(): Save the private info to
  271. * the reserved bytes of rx_tlv_hdr
  272. * @buf: start of rx_tlv_hdr
  273. * @priv_data: hal_wbm_err_desc_info structure
  274. * @len: length of the private data
  275. * Return: void
  276. */
  277. static inline void
  278. hal_rx_priv_info_set_in_tlv_li(uint8_t *buf, uint8_t *priv_data,
  279. uint32_t len)
  280. {
  281. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  282. uint32_t copy_len = (len > RX_PADDING0_BYTES) ?
  283. RX_PADDING0_BYTES : len;
  284. qdf_mem_copy(pkt_tlvs->rx_padding0, priv_data, copy_len);
  285. }
  286. /**
  287. * hal_rx_priv_info_get_from_tlv_li(): retrieve the private data from
  288. * the reserved bytes of rx_tlv_hdr.
  289. * @buf: start of rx_tlv_hdr
  290. * @priv_data: hal_wbm_err_desc_info structure
  291. * @len: length of the private data
  292. * Return: void
  293. */
  294. static inline void
  295. hal_rx_priv_info_get_from_tlv_li(uint8_t *buf, uint8_t *priv_data,
  296. uint32_t len)
  297. {
  298. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  299. uint32_t copy_len = (len > RX_PADDING0_BYTES) ?
  300. RX_PADDING0_BYTES : len;
  301. qdf_mem_copy(priv_data, pkt_tlvs->rx_padding0, copy_len);
  302. }
  303. /**
  304. * hal_rx_get_tlv_size_generic_li() - Get rx packet tlv size
  305. * @rx_pkt_tlv_size: TLV size for regular RX packets
  306. * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets
  307. *
  308. * Return: size of rx pkt tlv before the actual data
  309. */
  310. static void hal_rx_get_tlv_size_generic_li(uint16_t *rx_pkt_tlv_size,
  311. uint16_t *rx_mon_pkt_tlv_size)
  312. {
  313. *rx_pkt_tlv_size = RX_PKT_TLVS_LEN;
  314. *rx_mon_pkt_tlv_size = SIZE_OF_MONITOR_TLV;
  315. }
  316. /**
  317. * hal_rx_wbm_err_src_get_li() - Get WBM error source from descriptor
  318. * @ring_desc: ring descriptor
  319. *
  320. * Return: wbm error source
  321. */
  322. uint32_t hal_rx_wbm_err_src_get_li(hal_ring_desc_t ring_desc)
  323. {
  324. return HAL_WBM2SW_RELEASE_SRC_GET(ring_desc);
  325. }
  326. /**
  327. * hal_rx_ret_buf_manager_get_li() - Get return buffer manager from ring desc
  328. * @ring_desc: ring descriptor
  329. *
  330. * Return: rbm
  331. */
  332. uint8_t hal_rx_ret_buf_manager_get_li(hal_ring_desc_t ring_desc)
  333. {
  334. /*
  335. * The following macro takes buf_addr_info as argument,
  336. * but since buf_addr_info is the first field in ring_desc
  337. * Hence the following call is OK
  338. */
  339. return HAL_RX_BUF_RBM_GET(ring_desc);
  340. }
  341. /**
  342. * hal_rx_reo_buf_paddr_get_li: Gets the physical address and
  343. * cookie from the REO destination ring element
  344. *
  345. * @ rx_desc: Opaque cookie pointer used by HAL to get to
  346. * the current descriptor
  347. * @ buf_info: structure to return the buffer information
  348. * Return: void
  349. */
  350. static void hal_rx_reo_buf_paddr_get_li(hal_ring_desc_t rx_desc,
  351. struct hal_buf_info *buf_info)
  352. {
  353. struct reo_destination_ring *reo_ring =
  354. (struct reo_destination_ring *)rx_desc;
  355. buf_info->paddr =
  356. (HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_ring) |
  357. ((uint64_t)(HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_ring)) << 32));
  358. buf_info->sw_cookie = HAL_RX_REO_BUF_COOKIE_GET(reo_ring);
  359. }
  360. /**
  361. * hal_rx_msdu_link_desc_set_li: Retrieves MSDU Link Descriptor to WBM
  362. *
  363. * @ hal_soc_hdl : HAL version of the SOC pointer
  364. * @ src_srng_desc : void pointer to the WBM Release Ring descriptor
  365. * @ buf_addr_info : void pointer to the buffer_addr_info
  366. * @ bm_action : put in IDLE list or release to MSDU_LIST
  367. *
  368. * Return: void
  369. */
  370. /* look at implementation at dp_hw_link_desc_pool_setup()*/
  371. static void hal_rx_msdu_link_desc_set_li(hal_soc_handle_t hal_soc_hdl,
  372. void *src_srng_desc,
  373. hal_buff_addrinfo_t buf_addr_info,
  374. uint8_t bm_action)
  375. {
  376. /*
  377. * The offsets for fields used in this function are same in
  378. * wbm_release_ring for Lithium and wbm_release_ring_tx
  379. * for Beryllium. hence we can use wbm_release_ring directly.
  380. */
  381. struct wbm_release_ring *wbm_rel_srng =
  382. (struct wbm_release_ring *)src_srng_desc;
  383. uint32_t addr_31_0;
  384. uint8_t addr_39_32;
  385. /* Structure copy !!! */
  386. wbm_rel_srng->released_buff_or_desc_addr_info =
  387. *(struct buffer_addr_info *)buf_addr_info;
  388. addr_31_0 =
  389. wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_31_0;
  390. addr_39_32 =
  391. wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_39_32;
  392. HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING,
  393. RELEASE_SOURCE_MODULE, HAL_RX_WBM_ERR_SRC_SW);
  394. HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING, BM_ACTION,
  395. bm_action);
  396. HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING,
  397. BUFFER_OR_DESC_TYPE,
  398. HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC);
  399. /* WBM error is indicated when any of the link descriptors given to
  400. * WBM has a NULL address, and one those paths is the link descriptors
  401. * released from host after processing RXDMA errors,
  402. * or from Rx defrag path, and we want to add an assert here to ensure
  403. * host is not releasing descriptors with NULL address.
  404. */
  405. if (qdf_unlikely(!addr_31_0 && !addr_39_32)) {
  406. hal_dump_wbm_rel_desc(src_srng_desc);
  407. qdf_assert_always(0);
  408. }
  409. }
  410. static
  411. void hal_rx_buf_cookie_rbm_get_li(uint32_t *buf_addr_info_hdl,
  412. hal_buf_info_t buf_info_hdl)
  413. {
  414. struct hal_buf_info *buf_info =
  415. (struct hal_buf_info *)buf_info_hdl;
  416. struct buffer_addr_info *buf_addr_info =
  417. (struct buffer_addr_info *)buf_addr_info_hdl;
  418. buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
  419. /*
  420. * buffer addr info is the first member of ring desc, so the typecast
  421. * can be done.
  422. */
  423. buf_info->rbm = hal_rx_ret_buf_manager_get_li
  424. ((hal_ring_desc_t)buf_addr_info);
  425. }
  426. /**
  427. * hal_rx_msdu_link_desc_get(): API to get the MSDU information
  428. * from the MSDU link descriptor
  429. *
  430. * @ hal_soc_hdl : HAL version of the SOC pointer
  431. * @msdu_link_desc: Opaque pointer used by HAL to get to the
  432. * MSDU link descriptor (struct rx_msdu_link)
  433. *
  434. * @msdu_list: Return the list of MSDUs contained in this link descriptor
  435. *
  436. * @num_msdus: Number of MSDUs in the MPDU
  437. *
  438. * Return: void
  439. */
  440. static inline void hal_rx_msdu_list_get_li(hal_soc_handle_t hal_soc_hdl,
  441. void *msdu_link_desc,
  442. void *hal_msdu_list,
  443. uint16_t *num_msdus)
  444. {
  445. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  446. struct rx_msdu_details *msdu_details;
  447. struct rx_msdu_desc_info *msdu_desc_info;
  448. struct hal_rx_msdu_list *msdu_list = hal_msdu_list;
  449. struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc;
  450. int i;
  451. struct hal_buf_info buf_info;
  452. msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc);
  453. hal_debug("msdu_link=%pK msdu_details=%pK", msdu_link, msdu_details);
  454. for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
  455. /* num_msdus received in mpdu descriptor may be incorrect
  456. * sometimes due to HW issue. Check msdu buffer address also
  457. */
  458. if (!i && (HAL_RX_BUFFER_ADDR_31_0_GET(
  459. &msdu_details[i].buffer_addr_info_details) == 0))
  460. break;
  461. if (HAL_RX_BUFFER_ADDR_31_0_GET(
  462. &msdu_details[i].buffer_addr_info_details) == 0) {
  463. /* set the last msdu bit in the prev msdu_desc_info */
  464. msdu_desc_info =
  465. hal_rx_msdu_desc_info_get_ptr
  466. (&msdu_details[i - 1], hal_soc);
  467. HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  468. break;
  469. }
  470. msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i],
  471. hal_soc);
  472. /* set first MSDU bit or the last MSDU bit */
  473. if (!i)
  474. HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  475. else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
  476. HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  477. msdu_list->msdu_info[i].msdu_flags =
  478. hal_rx_msdu_flags_get(hal_soc_hdl, msdu_desc_info);
  479. msdu_list->msdu_info[i].msdu_len =
  480. HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info);
  481. /* addr field in buf_info will not be valid */
  482. hal_rx_buf_cookie_rbm_get_li(
  483. (uint32_t *)
  484. &msdu_details[i].buffer_addr_info_details,
  485. &buf_info);
  486. msdu_list->sw_cookie[i] = buf_info.sw_cookie;
  487. msdu_list->rbm[i] = buf_info.rbm;
  488. msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET(
  489. &msdu_details[i].buffer_addr_info_details) |
  490. (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET(
  491. &msdu_details[i].buffer_addr_info_details) << 32;
  492. hal_debug("i=%d sw_cookie=%d", i, msdu_list->sw_cookie[i]);
  493. }
  494. *num_msdus = i;
  495. }
  496. /*
  497. * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the
  498. * rxdma ring entry.
  499. * @rxdma_entry: descriptor entry
  500. * @paddr: physical address of nbuf data pointer.
  501. * @cookie: SW cookie used as a index to SW rx desc.
  502. * @manager: who owns the nbuf (host, NSS, etc...).
  503. *
  504. */
  505. static void hal_rxdma_buff_addr_info_set_li(void *rxdma_entry,
  506. qdf_dma_addr_t paddr, uint32_t cookie, uint8_t manager)
  507. {
  508. uint32_t paddr_lo = ((u64)paddr & 0x00000000ffffffff);
  509. uint32_t paddr_hi = ((u64)paddr & 0xffffffff00000000) >> 32;
  510. HAL_RXDMA_PADDR_LO_SET(rxdma_entry, paddr_lo);
  511. HAL_RXDMA_PADDR_HI_SET(rxdma_entry, paddr_hi);
  512. HAL_RXDMA_COOKIE_SET(rxdma_entry, cookie);
  513. HAL_RXDMA_MANAGER_SET(rxdma_entry, manager);
  514. }
  515. /**
  516. * hal_rx_get_reo_error_code_li() - Get REO error code from ring desc
  517. * @rx_desc: rx descriptor
  518. *
  519. * Return: REO error code
  520. */
  521. static uint32_t hal_rx_get_reo_error_code_li(hal_ring_desc_t rx_desc)
  522. {
  523. struct reo_destination_ring *reo_desc =
  524. (struct reo_destination_ring *)rx_desc;
  525. return HAL_RX_REO_ERROR_GET(reo_desc);
  526. }
  527. /**
  528. * hal_gen_reo_remap_val_generic_li() - Generate the reo map value
  529. * @ix0_map: mapping values for reo
  530. *
  531. * Return: IX0 reo remap register value to be written
  532. */
  533. static uint32_t
  534. hal_gen_reo_remap_val_generic_li(enum hal_reo_remap_reg remap_reg,
  535. uint8_t *ix0_map)
  536. {
  537. uint32_t ix_val = 0;
  538. switch (remap_reg) {
  539. case HAL_REO_REMAP_REG_IX0:
  540. ix_val = HAL_REO_REMAP_IX0(ix0_map[0], 0) |
  541. HAL_REO_REMAP_IX0(ix0_map[1], 1) |
  542. HAL_REO_REMAP_IX0(ix0_map[2], 2) |
  543. HAL_REO_REMAP_IX0(ix0_map[3], 3) |
  544. HAL_REO_REMAP_IX0(ix0_map[4], 4) |
  545. HAL_REO_REMAP_IX0(ix0_map[5], 5) |
  546. HAL_REO_REMAP_IX0(ix0_map[6], 6) |
  547. HAL_REO_REMAP_IX0(ix0_map[7], 7);
  548. break;
  549. case HAL_REO_REMAP_REG_IX2:
  550. ix_val = HAL_REO_REMAP_IX2(ix0_map[0], 16) |
  551. HAL_REO_REMAP_IX2(ix0_map[1], 17) |
  552. HAL_REO_REMAP_IX2(ix0_map[2], 18) |
  553. HAL_REO_REMAP_IX2(ix0_map[3], 19) |
  554. HAL_REO_REMAP_IX2(ix0_map[4], 20) |
  555. HAL_REO_REMAP_IX2(ix0_map[5], 21) |
  556. HAL_REO_REMAP_IX2(ix0_map[6], 22) |
  557. HAL_REO_REMAP_IX2(ix0_map[7], 23);
  558. break;
  559. default:
  560. break;
  561. }
  562. return ix_val;
  563. }
  564. /**
  565. * hal_rx_tlv_csum_err_get_li() - Get IP and tcp-udp checksum fail flag
  566. * @rx_tlv_hdr: start address of rx_tlv_hdr
  567. * @ip_csum_err: buffer to return ip_csum_fail flag
  568. * @tcp_udp_csum_fail: placeholder to return tcp-udp checksum fail flag
  569. *
  570. * Return: None
  571. */
  572. static inline void
  573. hal_rx_tlv_csum_err_get_li(uint8_t *rx_tlv_hdr, uint32_t *ip_csum_err,
  574. uint32_t *tcp_udp_csum_err)
  575. {
  576. *ip_csum_err = hal_rx_attn_ip_cksum_fail_get(rx_tlv_hdr);
  577. *tcp_udp_csum_err = hal_rx_attn_tcp_udp_cksum_fail_get(rx_tlv_hdr);
  578. }
  579. static
  580. void hal_rx_tlv_get_pkt_capture_flags_li(uint8_t *rx_tlv_pkt_hdr,
  581. struct hal_rx_pkt_capture_flags *flags)
  582. {
  583. struct rx_pkt_tlvs *rx_tlv_hdr = (struct rx_pkt_tlvs *)rx_tlv_pkt_hdr;
  584. struct rx_attention *rx_attn = &rx_tlv_hdr->attn_tlv.rx_attn;
  585. struct rx_mpdu_start *mpdu_start =
  586. &rx_tlv_hdr->mpdu_start_tlv.rx_mpdu_start;
  587. struct rx_mpdu_end *mpdu_end = &rx_tlv_hdr->mpdu_end_tlv.rx_mpdu_end;
  588. struct rx_msdu_start *msdu_start =
  589. &rx_tlv_hdr->msdu_start_tlv.rx_msdu_start;
  590. flags->encrypt_type = mpdu_start->rx_mpdu_info_details.encrypt_type;
  591. flags->fcs_err = mpdu_end->fcs_err;
  592. flags->fragment_flag = rx_attn->fragment_flag;
  593. flags->chan_freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start);
  594. flags->rssi_comb = HAL_RX_MSDU_START_RSSI_GET(msdu_start);
  595. flags->tsft = msdu_start->ppdu_start_timestamp;
  596. }
  597. static uint8_t hal_rx_err_status_get_li(hal_ring_desc_t rx_desc)
  598. {
  599. return HAL_RX_ERROR_STATUS_GET(rx_desc);
  600. }
  601. static uint8_t hal_rx_reo_buf_type_get_li(hal_ring_desc_t rx_desc)
  602. {
  603. return HAL_RX_REO_BUF_TYPE_GET(rx_desc);
  604. }
  605. static inline bool
  606. hal_rx_mpdu_info_ampdu_flag_get_li(uint8_t *buf)
  607. {
  608. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  609. struct rx_mpdu_start *mpdu_start =
  610. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  611. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  612. bool ampdu_flag;
  613. ampdu_flag = HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(mpdu_info);
  614. return ampdu_flag;
  615. }
  616. static
  617. uint32_t hal_rx_tlv_mpdu_len_err_get_li(void *hw_desc_addr)
  618. {
  619. struct rx_attention *rx_attn;
  620. struct rx_mon_pkt_tlvs *rx_desc =
  621. (struct rx_mon_pkt_tlvs *)hw_desc_addr;
  622. rx_attn = &rx_desc->attn_tlv.rx_attn;
  623. return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR);
  624. }
  625. static
  626. uint32_t hal_rx_tlv_mpdu_fcs_err_get_li(void *hw_desc_addr)
  627. {
  628. struct rx_attention *rx_attn;
  629. struct rx_mon_pkt_tlvs *rx_desc =
  630. (struct rx_mon_pkt_tlvs *)hw_desc_addr;
  631. rx_attn = &rx_desc->attn_tlv.rx_attn;
  632. return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR);
  633. }
  634. #ifdef NO_RX_PKT_HDR_TLV
  635. static uint8_t *hal_rx_desc_get_80211_hdr_li(void *hw_desc_addr)
  636. {
  637. uint8_t *rx_pkt_hdr;
  638. struct rx_mon_pkt_tlvs *rx_desc =
  639. (struct rx_mon_pkt_tlvs *)hw_desc_addr;
  640. rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0];
  641. return rx_pkt_hdr;
  642. }
  643. #else
  644. static uint8_t *hal_rx_desc_get_80211_hdr_li(void *hw_desc_addr)
  645. {
  646. uint8_t *rx_pkt_hdr;
  647. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  648. rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0];
  649. return rx_pkt_hdr;
  650. }
  651. #endif
  652. static uint32_t hal_rx_hw_desc_mpdu_user_id_li(void *hw_desc_addr)
  653. {
  654. struct rx_mon_pkt_tlvs *rx_desc =
  655. (struct rx_mon_pkt_tlvs *)hw_desc_addr;
  656. uint32_t user_id;
  657. user_id = HAL_RX_GET_USER_TLV32_USERID(
  658. &rx_desc->mpdu_start_tlv);
  659. return user_id;
  660. }
  661. /**
  662. * hal_rx_msdu_start_msdu_len_set_li(): API to set the MSDU length
  663. * from rx_msdu_start TLV
  664. *
  665. * @buf: pointer to the start of RX PKT TLV headers
  666. * @len: msdu length
  667. *
  668. * Return: none
  669. */
  670. static inline void
  671. hal_rx_msdu_start_msdu_len_set_li(uint8_t *buf, uint32_t len)
  672. {
  673. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  674. struct rx_msdu_start *msdu_start =
  675. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  676. void *wrd1;
  677. wrd1 = (uint8_t *)msdu_start + RX_MSDU_START_1_MSDU_LENGTH_OFFSET;
  678. *(uint32_t *)wrd1 &= (~RX_MSDU_START_1_MSDU_LENGTH_MASK);
  679. *(uint32_t *)wrd1 |= len;
  680. }
  681. /*
  682. * hal_rx_tlv_bw_get_li(): API to get the Bandwidth
  683. * Interval from rx_msdu_start
  684. *
  685. * @buf: pointer to the start of RX PKT TLV header
  686. * Return: uint32_t(bw)
  687. */
  688. static inline uint32_t hal_rx_tlv_bw_get_li(uint8_t *buf)
  689. {
  690. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  691. struct rx_msdu_start *msdu_start =
  692. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  693. uint32_t bw;
  694. bw = HAL_RX_MSDU_START_BW_GET(msdu_start);
  695. return bw;
  696. }
  697. /*
  698. * hal_rx_tlv_get_freq_li(): API to get the frequency of operating channel
  699. * from rx_msdu_start
  700. *
  701. * @buf: pointer to the start of RX PKT TLV header
  702. * Return: uint32_t(frequency)
  703. */
  704. static inline uint32_t
  705. hal_rx_tlv_get_freq_li(uint8_t *buf)
  706. {
  707. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  708. struct rx_msdu_start *msdu_start =
  709. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  710. uint32_t freq;
  711. freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start);
  712. return freq;
  713. }
  714. /**
  715. * hal_rx_tlv_sgi_get_li(): API to get the Short Gaurd
  716. * Interval from rx_msdu_start TLV
  717. *
  718. * @buf: pointer to the start of RX PKT TLV headers
  719. * Return: uint32_t(sgi)
  720. */
  721. static inline uint32_t
  722. hal_rx_tlv_sgi_get_li(uint8_t *buf)
  723. {
  724. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  725. struct rx_msdu_start *msdu_start =
  726. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  727. uint32_t sgi;
  728. sgi = HAL_RX_MSDU_START_SGI_GET(msdu_start);
  729. return sgi;
  730. }
  731. /**
  732. * hal_rx_tlv_rate_mcs_get_li(): API to get the MCS rate
  733. * from rx_msdu_start TLV
  734. *
  735. * @buf: pointer to the start of RX PKT TLV headers
  736. * Return: uint32_t(rate_mcs)
  737. */
  738. static inline uint32_t
  739. hal_rx_tlv_rate_mcs_get_li(uint8_t *buf)
  740. {
  741. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  742. struct rx_msdu_start *msdu_start =
  743. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  744. uint32_t rate_mcs;
  745. rate_mcs = HAL_RX_MSDU_START_RATE_MCS_GET(msdu_start);
  746. return rate_mcs;
  747. }
  748. /*
  749. * hal_rx_tlv_get_pkt_type_li(): API to get the pkt type
  750. * from rx_msdu_start
  751. *
  752. * @buf: pointer to the start of RX PKT TLV header
  753. * Return: uint32_t(pkt type)
  754. */
  755. static inline uint32_t hal_rx_tlv_get_pkt_type_li(uint8_t *buf)
  756. {
  757. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  758. struct rx_msdu_start *msdu_start =
  759. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  760. uint32_t pkt_type;
  761. pkt_type = HAL_RX_MSDU_START_PKT_TYPE_GET(msdu_start);
  762. return pkt_type;
  763. }
  764. /**
  765. * hal_rx_tlv_mic_err_get_li(): API to get the MIC ERR
  766. * from rx_mpdu_end TLV
  767. *
  768. * @buf: pointer to the start of RX PKT TLV headers
  769. * Return: uint32_t(mic_err)
  770. */
  771. static inline uint32_t
  772. hal_rx_tlv_mic_err_get_li(uint8_t *buf)
  773. {
  774. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  775. struct rx_mpdu_end *mpdu_end =
  776. &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
  777. uint32_t mic_err;
  778. mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end);
  779. return mic_err;
  780. }
  781. /**
  782. * hal_rx_tlv_decrypt_err_get_li(): API to get the Decrypt ERR
  783. * from rx_mpdu_end TLV
  784. *
  785. * @buf: pointer to the start of RX PKT TLV headers
  786. * Return: uint32_t(decrypt_err)
  787. */
  788. static inline uint32_t
  789. hal_rx_tlv_decrypt_err_get_li(uint8_t *buf)
  790. {
  791. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  792. struct rx_mpdu_end *mpdu_end =
  793. &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
  794. uint32_t decrypt_err;
  795. decrypt_err = HAL_RX_MPDU_END_DECRYPT_ERR_GET(mpdu_end);
  796. return decrypt_err;
  797. }
  798. /*
  799. * hal_rx_tlv_first_mpdu_get_li(): get fist_mpdu bit from rx attention
  800. * @buf: pointer to rx_pkt_tlvs
  801. *
  802. * reutm: uint32_t(first_msdu)
  803. */
  804. static inline uint32_t
  805. hal_rx_tlv_first_mpdu_get_li(uint8_t *buf)
  806. {
  807. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  808. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  809. uint32_t first_mpdu;
  810. first_mpdu = HAL_RX_ATTN_FIRST_MPDU_GET(rx_attn);
  811. return first_mpdu;
  812. }
  813. /*
  814. * hal_rx_msdu_get_keyid_li(): API to get the key id if the decrypted packet
  815. * from rx_msdu_end
  816. *
  817. * @buf: pointer to the start of RX PKT TLV header
  818. * Return: uint32_t(key id)
  819. */
  820. static inline uint8_t
  821. hal_rx_msdu_get_keyid_li(uint8_t *buf)
  822. {
  823. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  824. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  825. uint32_t keyid_octet;
  826. keyid_octet = HAL_RX_MSDU_END_KEYID_OCTET_GET(msdu_end);
  827. return keyid_octet & 0x3;
  828. }
  829. /*
  830. * hal_rx_tlv_get_is_decrypted_li(): API to get the decrypt status of the
  831. * packet from rx_attention
  832. *
  833. * @buf: pointer to the start of RX PKT TLV header
  834. * Return: uint32_t(decryt status)
  835. */
  836. static inline uint32_t
  837. hal_rx_tlv_get_is_decrypted_li(uint8_t *buf)
  838. {
  839. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  840. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  841. uint32_t is_decrypt = 0;
  842. uint32_t decrypt_status;
  843. decrypt_status = HAL_RX_ATTN_DECRYPT_STATUS_GET(rx_attn);
  844. if (!decrypt_status)
  845. is_decrypt = 1;
  846. return is_decrypt;
  847. }
  848. /**
  849. * hal_rx_msdu_reo_dst_ind_get_li: Gets the REO
  850. * destination ring ID from the msdu desc info
  851. *
  852. * @ hal_soc_hdl : HAL version of the SOC pointer
  853. * @msdu_link_desc : Opaque cookie pointer used by HAL to get to
  854. * the current descriptor
  855. *
  856. * Return: dst_ind (REO destination ring ID)
  857. */
  858. static inline uint32_t
  859. hal_rx_msdu_reo_dst_ind_get_li(hal_soc_handle_t hal_soc_hdl,
  860. void *msdu_link_desc)
  861. {
  862. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  863. struct rx_msdu_details *msdu_details;
  864. struct rx_msdu_desc_info *msdu_desc_info;
  865. struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc;
  866. uint32_t dst_ind;
  867. msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc);
  868. /* The first msdu in the link should exsist */
  869. msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[0],
  870. hal_soc);
  871. dst_ind = HAL_RX_MSDU_REO_DST_IND_GET(msdu_desc_info);
  872. return dst_ind;
  873. }
  874. static inline void
  875. hal_mpdu_desc_info_set_li(hal_soc_handle_t hal_soc_hdl,
  876. void *ent_desc,
  877. void *mpdu_desc,
  878. uint32_t seq_no)
  879. {
  880. struct rx_mpdu_desc_info *mpdu_desc_info =
  881. (struct rx_mpdu_desc_info *)mpdu_desc;
  882. HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info,
  883. MSDU_COUNT, 0x1);
  884. HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info,
  885. MPDU_SEQUENCE_NUMBER, seq_no);
  886. /* unset frag bit */
  887. HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info,
  888. FRAGMENT_FLAG, 0x0);
  889. /* set sa/da valid bits */
  890. HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info,
  891. SA_IS_VALID, 0x1);
  892. HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info,
  893. DA_IS_VALID, 0x1);
  894. HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info,
  895. RAW_MPDU, 0x0);
  896. }
  897. static inline void
  898. hal_msdu_desc_info_set_li(hal_soc_handle_t hal_soc_hdl,
  899. void *msdu_desc, uint32_t dst_ind,
  900. uint32_t nbuf_len)
  901. {
  902. struct rx_msdu_desc_info *msdu_desc_info =
  903. (struct rx_msdu_desc_info *)msdu_desc;
  904. HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
  905. FIRST_MSDU_IN_MPDU_FLAG, 1);
  906. HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
  907. LAST_MSDU_IN_MPDU_FLAG, 1);
  908. HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
  909. MSDU_CONTINUATION, 0x0);
  910. HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
  911. REO_DESTINATION_INDICATION,
  912. dst_ind);
  913. HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
  914. MSDU_LENGTH, nbuf_len);
  915. HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
  916. SA_IS_VALID, 1);
  917. HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
  918. DA_IS_VALID, 1);
  919. }
  920. static inline
  921. uint8_t *hal_get_reo_ent_desc_qdesc_addr_li(uint8_t *desc)
  922. {
  923. return desc + REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET;
  924. }
  925. static inline
  926. void hal_set_reo_ent_desc_reo_dest_ind_li(uint8_t *desc, uint32_t dst_ind)
  927. {
  928. HAL_RX_FLD_SET(desc, REO_ENTRANCE_RING_5,
  929. REO_DESTINATION_INDICATION, dst_ind);
  930. }
  931. static inline void
  932. hal_rx_wbm_rel_buf_paddr_get_li(hal_ring_desc_t rx_desc,
  933. struct hal_buf_info *buf_info)
  934. {
  935. struct wbm_release_ring *wbm_rel_ring =
  936. (struct wbm_release_ring *)rx_desc;
  937. buf_info->paddr =
  938. (HAL_RX_WBM_BUF_ADDR_31_0_GET(wbm_rel_ring) |
  939. ((uint64_t)(HAL_RX_WBM_BUF_ADDR_39_32_GET(wbm_rel_ring)) << 32));
  940. buf_info->sw_cookie = HAL_RX_WBM_BUF_COOKIE_GET(wbm_rel_ring);
  941. }
  942. static QDF_STATUS hal_reo_status_update_li(hal_soc_handle_t hal_soc_hdl,
  943. hal_ring_desc_t reo_desc,
  944. void *st_handle,
  945. uint32_t tlv, int *num_ref)
  946. {
  947. union hal_reo_status *reo_status_ref;
  948. reo_status_ref = (union hal_reo_status *)st_handle;
  949. switch (tlv) {
  950. case HAL_REO_QUEUE_STATS_STATUS_TLV:
  951. hal_reo_queue_stats_status_li(reo_desc,
  952. &reo_status_ref->queue_status,
  953. hal_soc_hdl);
  954. *num_ref = reo_status_ref->queue_status.header.cmd_num;
  955. break;
  956. case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
  957. hal_reo_flush_queue_status_li(reo_desc,
  958. &reo_status_ref->fl_queue_status,
  959. hal_soc_hdl);
  960. *num_ref = reo_status_ref->fl_queue_status.header.cmd_num;
  961. break;
  962. case HAL_REO_FLUSH_CACHE_STATUS_TLV:
  963. hal_reo_flush_cache_status_li(reo_desc,
  964. &reo_status_ref->fl_cache_status,
  965. hal_soc_hdl);
  966. *num_ref = reo_status_ref->fl_cache_status.header.cmd_num;
  967. break;
  968. case HAL_REO_UNBLK_CACHE_STATUS_TLV:
  969. hal_reo_unblock_cache_status_li(
  970. reo_desc, hal_soc_hdl,
  971. &reo_status_ref->unblk_cache_status);
  972. *num_ref = reo_status_ref->unblk_cache_status.header.cmd_num;
  973. break;
  974. case HAL_REO_TIMOUT_LIST_STATUS_TLV:
  975. hal_reo_flush_timeout_list_status_li(
  976. reo_desc,
  977. &reo_status_ref->fl_timeout_status,
  978. hal_soc_hdl);
  979. *num_ref = reo_status_ref->fl_timeout_status.header.cmd_num;
  980. break;
  981. case HAL_REO_DESC_THRES_STATUS_TLV:
  982. hal_reo_desc_thres_reached_status_li(
  983. reo_desc,
  984. &reo_status_ref->thres_status,
  985. hal_soc_hdl);
  986. *num_ref = reo_status_ref->thres_status.header.cmd_num;
  987. break;
  988. case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
  989. hal_reo_rx_update_queue_status_li(
  990. reo_desc,
  991. &reo_status_ref->rx_queue_status,
  992. hal_soc_hdl);
  993. *num_ref = reo_status_ref->rx_queue_status.header.cmd_num;
  994. break;
  995. default:
  996. QDF_TRACE(QDF_MODULE_ID_DP_REO, QDF_TRACE_LEVEL_WARN,
  997. "hal_soc %pK: no handler for TLV:%d",
  998. hal_soc_hdl, tlv);
  999. return QDF_STATUS_E_FAILURE;
  1000. } /* switch */
  1001. return QDF_STATUS_SUCCESS;
  1002. }
  1003. /**
  1004. * hal_get_idle_link_bm_id_li() - Get idle link BM id from chid_id
  1005. * @chip_id: mlo chip_id
  1006. *
  1007. * Returns: RBM ID
  1008. */
  1009. static uint8_t hal_get_idle_link_bm_id_li(uint8_t chip_id)
  1010. {
  1011. return WBM_IDLE_DESC_LIST;
  1012. }
  1013. /**
  1014. * hal_hw_txrx_default_ops_attach_li() - Attach the default hal ops for
  1015. * lithium chipsets.
  1016. * @hal_soc_hdl: HAL soc handle
  1017. *
  1018. * Return: None
  1019. */
  1020. void hal_hw_txrx_default_ops_attach_li(struct hal_soc *hal_soc)
  1021. {
  1022. hal_soc->ops->hal_get_reo_qdesc_size = hal_get_reo_qdesc_size_li;
  1023. hal_soc->ops->hal_get_rx_max_ba_window =
  1024. hal_get_rx_max_ba_window_li;
  1025. hal_soc->ops->hal_set_link_desc_addr = hal_set_link_desc_addr_li;
  1026. hal_soc->ops->hal_tx_init_data_ring = hal_tx_init_data_ring_li;
  1027. hal_soc->ops->hal_get_ba_aging_timeout = hal_get_ba_aging_timeout_li;
  1028. hal_soc->ops->hal_set_ba_aging_timeout = hal_set_ba_aging_timeout_li;
  1029. hal_soc->ops->hal_get_reo_reg_base_offset =
  1030. hal_get_reo_reg_base_offset_li;
  1031. hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_li;
  1032. hal_soc->ops->hal_rx_msdu_is_wlan_mcast =
  1033. hal_rx_msdu_is_wlan_mcast_generic_li;
  1034. hal_soc->ops->hal_rx_tlv_decap_format_get =
  1035. hal_rx_tlv_decap_format_get_li;
  1036. hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_li;
  1037. hal_soc->ops->hal_rx_tlv_get_offload_info =
  1038. hal_rx_tlv_get_offload_info_li;
  1039. hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get =
  1040. hal_rx_attn_phy_ppdu_id_get_li;
  1041. hal_soc->ops->hal_rx_tlv_msdu_done_get = hal_rx_attn_msdu_done_get_li;
  1042. hal_soc->ops->hal_rx_tlv_msdu_len_get =
  1043. hal_rx_msdu_start_msdu_len_get_li;
  1044. hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_li;
  1045. hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_li;
  1046. hal_soc->ops->hal_rx_reo_buf_paddr_get = hal_rx_reo_buf_paddr_get_li;
  1047. hal_soc->ops->hal_rx_msdu_link_desc_set = hal_rx_msdu_link_desc_set_li;
  1048. hal_soc->ops->hal_rx_buf_cookie_rbm_get = hal_rx_buf_cookie_rbm_get_li;
  1049. hal_soc->ops->hal_rx_ret_buf_manager_get =
  1050. hal_rx_ret_buf_manager_get_li;
  1051. hal_soc->ops->hal_rxdma_buff_addr_info_set =
  1052. hal_rxdma_buff_addr_info_set_li;
  1053. hal_soc->ops->hal_rx_msdu_flags_get = hal_rx_msdu_flags_get_li;
  1054. hal_soc->ops->hal_rx_get_reo_error_code = hal_rx_get_reo_error_code_li;
  1055. hal_soc->ops->hal_gen_reo_remap_val =
  1056. hal_gen_reo_remap_val_generic_li;
  1057. hal_soc->ops->hal_rx_tlv_csum_err_get =
  1058. hal_rx_tlv_csum_err_get_li;
  1059. hal_soc->ops->hal_rx_mpdu_desc_info_get =
  1060. hal_rx_mpdu_desc_info_get_li;
  1061. hal_soc->ops->hal_rx_err_status_get = hal_rx_err_status_get_li;
  1062. hal_soc->ops->hal_rx_reo_buf_type_get = hal_rx_reo_buf_type_get_li;
  1063. hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_li;
  1064. hal_soc->ops->hal_rx_wbm_err_src_get = hal_rx_wbm_err_src_get_li;
  1065. hal_soc->ops->hal_rx_wbm_rel_buf_paddr_get =
  1066. hal_rx_wbm_rel_buf_paddr_get_li;
  1067. hal_soc->ops->hal_rx_priv_info_set_in_tlv =
  1068. hal_rx_priv_info_set_in_tlv_li;
  1069. hal_soc->ops->hal_rx_priv_info_get_from_tlv =
  1070. hal_rx_priv_info_get_from_tlv_li;
  1071. hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get =
  1072. hal_rx_mpdu_info_ampdu_flag_get_li;
  1073. hal_soc->ops->hal_rx_tlv_mpdu_len_err_get =
  1074. hal_rx_tlv_mpdu_len_err_get_li;
  1075. hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get =
  1076. hal_rx_tlv_mpdu_fcs_err_get_li;
  1077. hal_soc->ops->hal_reo_send_cmd = hal_reo_send_cmd_li;
  1078. hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags =
  1079. hal_rx_tlv_get_pkt_capture_flags_li;
  1080. hal_soc->ops->hal_rx_desc_get_80211_hdr = hal_rx_desc_get_80211_hdr_li;
  1081. hal_soc->ops->hal_rx_hw_desc_mpdu_user_id =
  1082. hal_rx_hw_desc_mpdu_user_id_li;
  1083. hal_soc->ops->hal_reo_qdesc_setup = hal_reo_qdesc_setup_li;
  1084. hal_soc->ops->hal_rx_tlv_msdu_len_set =
  1085. hal_rx_msdu_start_msdu_len_set_li;
  1086. hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_li;
  1087. hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_li;
  1088. hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_li;
  1089. hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_li;
  1090. hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_li;
  1091. hal_soc->ops->hal_rx_tlv_get_pn_num = hal_rx_tlv_get_pn_num_li;
  1092. hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_li;
  1093. hal_soc->ops->hal_rx_tlv_decrypt_err_get =
  1094. hal_rx_tlv_decrypt_err_get_li;
  1095. hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_li;
  1096. hal_soc->ops->hal_rx_tlv_get_is_decrypted =
  1097. hal_rx_tlv_get_is_decrypted_li;
  1098. hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_li;
  1099. hal_soc->ops->hal_rx_msdu_reo_dst_ind_get =
  1100. hal_rx_msdu_reo_dst_ind_get_li;
  1101. hal_soc->ops->hal_msdu_desc_info_set = hal_msdu_desc_info_set_li;
  1102. hal_soc->ops->hal_mpdu_desc_info_set = hal_mpdu_desc_info_set_li;
  1103. hal_soc->ops->hal_reo_status_update = hal_reo_status_update_li;
  1104. hal_soc->ops->hal_get_tlv_hdr_size = hal_get_tlv_hdr_size_li;
  1105. hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr =
  1106. hal_get_reo_ent_desc_qdesc_addr_li;
  1107. hal_soc->ops->hal_rx_get_qdesc_addr = hal_rx_get_qdesc_addr_li;
  1108. hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind =
  1109. hal_set_reo_ent_desc_reo_dest_ind_li;
  1110. hal_soc->ops->hal_get_idle_link_bm_id = hal_get_idle_link_bm_id_li;
  1111. }