hal_be_reo.c 38 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "qdf_module.h"
  20. #include "hal_hw_headers.h"
  21. #include "hal_be_hw_headers.h"
  22. #include "hal_reo.h"
  23. #include "hal_be_reo.h"
  24. #include "hal_be_api.h"
  25. uint32_t hal_get_reo_reg_base_offset_be(void)
  26. {
  27. return REO_REG_REG_BASE;
  28. }
  29. /**
  30. * hal_reo_qdesc_setup - Setup HW REO queue descriptor
  31. *
  32. * @hal_soc: Opaque HAL SOC handle
  33. * @ba_window_size: BlockAck window size
  34. * @start_seq: Starting sequence number
  35. * @hw_qdesc_vaddr: Virtual address of REO queue descriptor memory
  36. * @hw_qdesc_paddr: Physical address of REO queue descriptor memory
  37. * @tid: TID
  38. *
  39. */
  40. void hal_reo_qdesc_setup_be(hal_soc_handle_t hal_soc_hdl, int tid,
  41. uint32_t ba_window_size,
  42. uint32_t start_seq, void *hw_qdesc_vaddr,
  43. qdf_dma_addr_t hw_qdesc_paddr,
  44. int pn_type, uint8_t vdev_stats_id)
  45. {
  46. uint32_t *reo_queue_desc = (uint32_t *)hw_qdesc_vaddr;
  47. uint32_t *reo_queue_ext_desc;
  48. uint32_t reg_val;
  49. uint32_t pn_enable;
  50. uint32_t pn_size = 0;
  51. qdf_mem_zero(hw_qdesc_vaddr, sizeof(struct rx_reo_queue));
  52. hal_uniform_desc_hdr_setup(reo_queue_desc, HAL_DESC_REO_OWNED,
  53. HAL_REO_QUEUE_DESC);
  54. /* Fixed pattern in reserved bits for debugging */
  55. HAL_DESC_SET_FIELD(reo_queue_desc, UNIFORM_DESCRIPTOR_HEADER,
  56. RESERVED_0A, 0xDDBEEF);
  57. /* This a just a SW meta data and will be copied to REO destination
  58. * descriptors indicated by hardware.
  59. * TODO: Setting TID in this field. See if we should set something else.
  60. */
  61. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE,
  62. RECEIVE_QUEUE_NUMBER, tid);
  63. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE,
  64. VLD, 1);
  65. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE,
  66. ASSOCIATED_LINK_DESCRIPTOR_COUNTER,
  67. HAL_RX_LINK_DESC_CNTR);
  68. /*
  69. * Fields DISABLE_DUPLICATE_DETECTION and SOFT_REORDER_ENABLE will be 0
  70. */
  71. reg_val = TID_TO_WME_AC(tid);
  72. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE, AC, reg_val);
  73. if (ba_window_size < 1)
  74. ba_window_size = 1;
  75. /* WAR to get 2k exception in Non BA case.
  76. * Setting window size to 2 to get 2k jump exception
  77. * when we receive aggregates in Non BA case
  78. */
  79. ba_window_size = hal_update_non_ba_win_size(tid, ba_window_size);
  80. /* Set RTY bit for non-BA case. Duplicate detection is currently not
  81. * done by HW in non-BA case if RTY bit is not set.
  82. * TODO: This is a temporary War and should be removed once HW fix is
  83. * made to check and discard duplicates even if RTY bit is not set.
  84. */
  85. if (ba_window_size == 1)
  86. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE, RTY, 1);
  87. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE, BA_WINDOW_SIZE,
  88. ba_window_size - 1);
  89. switch (pn_type) {
  90. case HAL_PN_WPA:
  91. pn_enable = 1;
  92. pn_size = PN_SIZE_48;
  93. break;
  94. case HAL_PN_WAPI_EVEN:
  95. case HAL_PN_WAPI_UNEVEN:
  96. pn_enable = 1;
  97. pn_size = PN_SIZE_128;
  98. break;
  99. default:
  100. pn_enable = 0;
  101. break;
  102. }
  103. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE, PN_CHECK_NEEDED,
  104. pn_enable);
  105. if (pn_type == HAL_PN_WAPI_EVEN)
  106. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE,
  107. PN_SHALL_BE_EVEN, 1);
  108. else if (pn_type == HAL_PN_WAPI_UNEVEN)
  109. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE,
  110. PN_SHALL_BE_UNEVEN, 1);
  111. /*
  112. * TODO: Need to check if PN handling in SW needs to be enabled
  113. * So far this is not a requirement
  114. */
  115. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE, PN_SIZE,
  116. pn_size);
  117. /* TODO: Check if RX_REO_QUEUE_IGNORE_AMPDU_FLAG need to be set
  118. * based on BA window size and/or AMPDU capabilities
  119. */
  120. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE,
  121. IGNORE_AMPDU_FLAG, 1);
  122. if (start_seq <= 0xfff)
  123. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE, SSN,
  124. start_seq);
  125. /* TODO: SVLD should be set to 1 if a valid SSN is received in ADDBA,
  126. * but REO is not delivering packets if we set it to 1. Need to enable
  127. * this once the issue is resolved
  128. */
  129. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE, SVLD, 0);
  130. hal_update_stats_counter_index(reo_queue_desc, vdev_stats_id);
  131. /* TODO: Check if we should set start PN for WAPI */
  132. /* TODO: HW queue descriptors are currently allocated for max BA
  133. * window size for all QOS TIDs so that same descriptor can be used
  134. * later when ADDBA request is received. This should be changed to
  135. * allocate HW queue descriptors based on BA window size being
  136. * negotiated (0 for non BA cases), and reallocate when BA window
  137. * size changes and also send WMI message to FW to change the REO
  138. * queue descriptor in Rx peer entry as part of dp_rx_tid_update.
  139. */
  140. if (tid == HAL_NON_QOS_TID)
  141. return;
  142. reo_queue_ext_desc = (uint32_t *)
  143. (((struct rx_reo_queue *)reo_queue_desc) + 1);
  144. qdf_mem_zero(reo_queue_ext_desc, 3 *
  145. sizeof(struct rx_reo_queue_ext));
  146. /* Initialize first reo queue extension descriptor */
  147. hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
  148. HAL_DESC_REO_OWNED,
  149. HAL_REO_QUEUE_EXT_DESC);
  150. /* Fixed pattern in reserved bits for debugging */
  151. HAL_DESC_SET_FIELD(reo_queue_ext_desc,
  152. UNIFORM_DESCRIPTOR_HEADER, RESERVED_0A,
  153. 0xADBEEF);
  154. /* Initialize second reo queue extension descriptor */
  155. reo_queue_ext_desc = (uint32_t *)
  156. (((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
  157. hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
  158. HAL_DESC_REO_OWNED,
  159. HAL_REO_QUEUE_EXT_DESC);
  160. /* Fixed pattern in reserved bits for debugging */
  161. HAL_DESC_SET_FIELD(reo_queue_ext_desc,
  162. UNIFORM_DESCRIPTOR_HEADER, RESERVED_0A,
  163. 0xBDBEEF);
  164. /* Initialize third reo queue extension descriptor */
  165. reo_queue_ext_desc = (uint32_t *)
  166. (((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
  167. hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
  168. HAL_DESC_REO_OWNED,
  169. HAL_REO_QUEUE_EXT_DESC);
  170. /* Fixed pattern in reserved bits for debugging */
  171. HAL_DESC_SET_FIELD(reo_queue_ext_desc,
  172. UNIFORM_DESCRIPTOR_HEADER, RESERVED_0A,
  173. 0xCDBEEF);
  174. }
  175. qdf_export_symbol(hal_reo_qdesc_setup_be);
  176. static void
  177. hal_reo_cmd_set_descr_addr_be(uint32_t *reo_desc,
  178. enum hal_reo_cmd_type type,
  179. uint32_t paddr_lo,
  180. uint8_t paddr_hi)
  181. {
  182. switch (type) {
  183. case CMD_GET_QUEUE_STATS:
  184. HAL_DESC_64_SET_FIELD(reo_desc, REO_GET_QUEUE_STATS,
  185. RX_REO_QUEUE_DESC_ADDR_31_0, paddr_lo);
  186. HAL_DESC_64_SET_FIELD(reo_desc, REO_GET_QUEUE_STATS,
  187. RX_REO_QUEUE_DESC_ADDR_39_32, paddr_hi);
  188. break;
  189. case CMD_FLUSH_QUEUE:
  190. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_QUEUE,
  191. FLUSH_DESC_ADDR_31_0, paddr_lo);
  192. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_QUEUE,
  193. FLUSH_DESC_ADDR_39_32, paddr_hi);
  194. break;
  195. case CMD_FLUSH_CACHE:
  196. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_CACHE,
  197. FLUSH_ADDR_31_0, paddr_lo);
  198. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_CACHE,
  199. FLUSH_ADDR_39_32, paddr_hi);
  200. break;
  201. case CMD_UPDATE_RX_REO_QUEUE:
  202. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  203. RX_REO_QUEUE_DESC_ADDR_31_0, paddr_lo);
  204. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  205. RX_REO_QUEUE_DESC_ADDR_39_32, paddr_hi);
  206. break;
  207. default:
  208. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  209. "%s: Invalid REO command type", __func__);
  210. break;
  211. }
  212. }
  213. static int
  214. hal_reo_cmd_queue_stats_be(hal_ring_handle_t hal_ring_hdl,
  215. hal_soc_handle_t hal_soc_hdl,
  216. struct hal_reo_cmd_params *cmd)
  217. {
  218. uint32_t *reo_desc, val;
  219. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  220. hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
  221. reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
  222. if (!reo_desc) {
  223. hal_srng_access_end_reap(hal_soc, hal_ring_hdl);
  224. hal_warn_rl("Out of cmd ring entries");
  225. return -EBUSY;
  226. }
  227. HAL_SET_TLV_HDR(reo_desc, WIFIREO_GET_QUEUE_STATS_E,
  228. sizeof(struct reo_get_queue_stats));
  229. /*
  230. * Offsets of descriptor fields defined in HW headers start from
  231. * the field after TLV header
  232. */
  233. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  234. qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
  235. sizeof(struct reo_get_queue_stats) -
  236. (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
  237. HAL_DESC_64_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER,
  238. REO_STATUS_REQUIRED, cmd->std.need_status);
  239. hal_reo_cmd_set_descr_addr_be(reo_desc, CMD_GET_QUEUE_STATS,
  240. cmd->std.addr_lo,
  241. cmd->std.addr_hi);
  242. HAL_DESC_64_SET_FIELD(reo_desc, REO_GET_QUEUE_STATS, CLEAR_STATS,
  243. cmd->u.stats_params.clear);
  244. hal_srng_access_end_v1(hal_soc_hdl, hal_ring_hdl,
  245. HIF_RTPM_ID_HAL_REO_CMD);
  246. val = reo_desc[CMD_HEADER_DW_OFFSET];
  247. return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER, REO_CMD_NUMBER,
  248. val);
  249. }
  250. static int
  251. hal_reo_cmd_flush_queue_be(hal_ring_handle_t hal_ring_hdl,
  252. hal_soc_handle_t hal_soc_hdl,
  253. struct hal_reo_cmd_params *cmd)
  254. {
  255. uint32_t *reo_desc, val;
  256. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  257. hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
  258. reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
  259. if (!reo_desc) {
  260. hal_srng_access_end_reap(hal_soc, hal_ring_hdl);
  261. hal_warn_rl("Out of cmd ring entries");
  262. return -EBUSY;
  263. }
  264. HAL_SET_TLV_HDR(reo_desc, WIFIREO_FLUSH_QUEUE_E,
  265. sizeof(struct reo_flush_queue));
  266. /*
  267. * Offsets of descriptor fields defined in HW headers start from
  268. * the field after TLV header
  269. */
  270. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  271. qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
  272. sizeof(struct reo_flush_queue) -
  273. (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
  274. HAL_DESC_64_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER,
  275. REO_STATUS_REQUIRED, cmd->std.need_status);
  276. hal_reo_cmd_set_descr_addr_be(reo_desc, CMD_FLUSH_QUEUE,
  277. cmd->std.addr_lo, cmd->std.addr_hi);
  278. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_QUEUE,
  279. BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH,
  280. cmd->u.fl_queue_params.block_use_after_flush);
  281. if (cmd->u.fl_queue_params.block_use_after_flush) {
  282. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_QUEUE,
  283. BLOCK_RESOURCE_INDEX,
  284. cmd->u.fl_queue_params.index);
  285. }
  286. hal_srng_access_end_v1(hal_soc_hdl, hal_ring_hdl,
  287. HIF_RTPM_ID_HAL_REO_CMD);
  288. val = reo_desc[CMD_HEADER_DW_OFFSET];
  289. return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER, REO_CMD_NUMBER,
  290. val);
  291. }
  292. static int
  293. hal_reo_cmd_flush_cache_be(hal_ring_handle_t hal_ring_hdl,
  294. hal_soc_handle_t hal_soc_hdl,
  295. struct hal_reo_cmd_params *cmd)
  296. {
  297. uint32_t *reo_desc, val;
  298. struct hal_reo_cmd_flush_cache_params *cp;
  299. uint8_t index = 0;
  300. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  301. cp = &cmd->u.fl_cache_params;
  302. hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
  303. /* We need a cache block resource for this operation, and REO HW has
  304. * only 4 such blocking resources. These resources are managed using
  305. * reo_res_bitmap, and we return failure if none is available.
  306. */
  307. if (cp->block_use_after_flush) {
  308. index = hal_find_zero_bit(hal_soc->reo_res_bitmap);
  309. if (index > 3) {
  310. hal_srng_access_end_reap(hal_soc, hal_ring_hdl);
  311. hal_warn_rl("No blocking resource available!");
  312. return -EBUSY;
  313. }
  314. hal_soc->index = index;
  315. }
  316. reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
  317. if (!reo_desc) {
  318. hal_srng_access_end_reap(hal_soc, hal_ring_hdl);
  319. hal_srng_dump(hal_ring_handle_to_hal_srng(hal_ring_hdl));
  320. return -EBUSY;
  321. }
  322. HAL_SET_TLV_HDR(reo_desc, WIFIREO_FLUSH_CACHE_E,
  323. sizeof(struct reo_flush_cache));
  324. /*
  325. * Offsets of descriptor fields defined in HW headers start from
  326. * the field after TLV header
  327. */
  328. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  329. qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
  330. sizeof(struct reo_flush_cache) -
  331. (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
  332. HAL_DESC_64_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER,
  333. REO_STATUS_REQUIRED, cmd->std.need_status);
  334. hal_reo_cmd_set_descr_addr_be(reo_desc, CMD_FLUSH_CACHE,
  335. cmd->std.addr_lo, cmd->std.addr_hi);
  336. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_CACHE,
  337. FORWARD_ALL_MPDUS_IN_QUEUE,
  338. cp->fwd_mpdus_in_queue);
  339. /* set it to 0 for now */
  340. cp->rel_block_index = 0;
  341. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_CACHE,
  342. RELEASE_CACHE_BLOCK_INDEX, cp->rel_block_index);
  343. if (cp->block_use_after_flush) {
  344. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_CACHE,
  345. CACHE_BLOCK_RESOURCE_INDEX, index);
  346. }
  347. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_CACHE,
  348. FLUSH_WITHOUT_INVALIDATE, cp->flush_no_inval);
  349. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_CACHE,
  350. BLOCK_CACHE_USAGE_AFTER_FLUSH,
  351. cp->block_use_after_flush);
  352. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_CACHE, FLUSH_ENTIRE_CACHE,
  353. cp->flush_entire_cache);
  354. hal_srng_access_end_v1(hal_soc_hdl, hal_ring_hdl,
  355. HIF_RTPM_ID_HAL_REO_CMD);
  356. val = reo_desc[CMD_HEADER_DW_OFFSET];
  357. return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER, REO_CMD_NUMBER,
  358. val);
  359. }
  360. static int
  361. hal_reo_cmd_unblock_cache_be(hal_ring_handle_t hal_ring_hdl,
  362. hal_soc_handle_t hal_soc_hdl,
  363. struct hal_reo_cmd_params *cmd)
  364. {
  365. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  366. uint32_t *reo_desc, val;
  367. uint8_t index = 0;
  368. hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
  369. if (cmd->u.unblk_cache_params.type == UNBLOCK_RES_INDEX) {
  370. index = hal_find_one_bit(hal_soc->reo_res_bitmap);
  371. if (index > 3) {
  372. hal_srng_access_end(hal_soc, hal_ring_hdl);
  373. qdf_print("No blocking resource to unblock!");
  374. return -EBUSY;
  375. }
  376. }
  377. reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
  378. if (!reo_desc) {
  379. hal_srng_access_end_reap(hal_soc, hal_ring_hdl);
  380. hal_warn_rl("Out of cmd ring entries");
  381. return -EBUSY;
  382. }
  383. HAL_SET_TLV_HDR(reo_desc, WIFIREO_UNBLOCK_CACHE_E,
  384. sizeof(struct reo_unblock_cache));
  385. /*
  386. * Offsets of descriptor fields defined in HW headers start from
  387. * the field after TLV header
  388. */
  389. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  390. qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
  391. sizeof(struct reo_unblock_cache) -
  392. (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
  393. HAL_DESC_64_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER,
  394. REO_STATUS_REQUIRED, cmd->std.need_status);
  395. HAL_DESC_64_SET_FIELD(reo_desc, REO_UNBLOCK_CACHE,
  396. UNBLOCK_TYPE, cmd->u.unblk_cache_params.type);
  397. if (cmd->u.unblk_cache_params.type == UNBLOCK_RES_INDEX) {
  398. HAL_DESC_64_SET_FIELD(reo_desc, REO_UNBLOCK_CACHE,
  399. CACHE_BLOCK_RESOURCE_INDEX,
  400. cmd->u.unblk_cache_params.index);
  401. }
  402. hal_srng_access_end(hal_soc, hal_ring_hdl);
  403. val = reo_desc[CMD_HEADER_DW_OFFSET];
  404. return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER, REO_CMD_NUMBER,
  405. val);
  406. }
  407. static int
  408. hal_reo_cmd_flush_timeout_list_be(hal_ring_handle_t hal_ring_hdl,
  409. hal_soc_handle_t hal_soc_hdl,
  410. struct hal_reo_cmd_params *cmd)
  411. {
  412. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  413. uint32_t *reo_desc, val;
  414. hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
  415. reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
  416. if (!reo_desc) {
  417. hal_srng_access_end_reap(hal_soc, hal_ring_hdl);
  418. hal_warn_rl("Out of cmd ring entries");
  419. return -EBUSY;
  420. }
  421. HAL_SET_TLV_HDR(reo_desc, WIFIREO_FLUSH_TIMEOUT_LIST_E,
  422. sizeof(struct reo_flush_timeout_list));
  423. /*
  424. * Offsets of descriptor fields defined in HW headers start from
  425. * the field after TLV header
  426. */
  427. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  428. qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
  429. sizeof(struct reo_flush_timeout_list) -
  430. (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
  431. HAL_DESC_64_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER,
  432. REO_STATUS_REQUIRED, cmd->std.need_status);
  433. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_TIMEOUT_LIST, AC_TIMOUT_LIST,
  434. cmd->u.fl_tim_list_params.ac_list);
  435. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_TIMEOUT_LIST,
  436. MINIMUM_RELEASE_DESC_COUNT,
  437. cmd->u.fl_tim_list_params.min_rel_desc);
  438. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_TIMEOUT_LIST,
  439. MINIMUM_FORWARD_BUF_COUNT,
  440. cmd->u.fl_tim_list_params.min_fwd_buf);
  441. hal_srng_access_end(hal_soc, hal_ring_hdl);
  442. val = reo_desc[CMD_HEADER_DW_OFFSET];
  443. return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER, REO_CMD_NUMBER,
  444. val);
  445. }
  446. static int
  447. hal_reo_cmd_update_rx_queue_be(hal_ring_handle_t hal_ring_hdl,
  448. hal_soc_handle_t hal_soc_hdl,
  449. struct hal_reo_cmd_params *cmd)
  450. {
  451. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  452. uint32_t *reo_desc, val;
  453. struct hal_reo_cmd_update_queue_params *p;
  454. p = &cmd->u.upd_queue_params;
  455. hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
  456. reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
  457. if (!reo_desc) {
  458. hal_srng_access_end_reap(hal_soc, hal_ring_hdl);
  459. hal_warn_rl("Out of cmd ring entries");
  460. return -EBUSY;
  461. }
  462. HAL_SET_TLV_HDR(reo_desc, WIFIREO_UPDATE_RX_REO_QUEUE_E,
  463. sizeof(struct reo_update_rx_reo_queue));
  464. /*
  465. * Offsets of descriptor fields defined in HW headers start from
  466. * the field after TLV header
  467. */
  468. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  469. qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
  470. sizeof(struct reo_update_rx_reo_queue) -
  471. (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
  472. HAL_DESC_64_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER,
  473. REO_STATUS_REQUIRED, cmd->std.need_status);
  474. hal_reo_cmd_set_descr_addr_be(reo_desc, CMD_UPDATE_RX_REO_QUEUE,
  475. cmd->std.addr_lo, cmd->std.addr_hi);
  476. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  477. UPDATE_RECEIVE_QUEUE_NUMBER,
  478. p->update_rx_queue_num);
  479. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE, UPDATE_VLD,
  480. p->update_vld);
  481. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  482. UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER,
  483. p->update_assoc_link_desc);
  484. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  485. UPDATE_DISABLE_DUPLICATE_DETECTION,
  486. p->update_disable_dup_detect);
  487. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  488. UPDATE_DISABLE_DUPLICATE_DETECTION,
  489. p->update_disable_dup_detect);
  490. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  491. UPDATE_SOFT_REORDER_ENABLE,
  492. p->update_soft_reorder_enab);
  493. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  494. UPDATE_AC, p->update_ac);
  495. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  496. UPDATE_BAR, p->update_bar);
  497. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  498. UPDATE_BAR, p->update_bar);
  499. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  500. UPDATE_RTY, p->update_rty);
  501. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  502. UPDATE_CHK_2K_MODE, p->update_chk_2k_mode);
  503. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  504. UPDATE_OOR_MODE, p->update_oor_mode);
  505. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  506. UPDATE_BA_WINDOW_SIZE, p->update_ba_window_size);
  507. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  508. UPDATE_PN_CHECK_NEEDED,
  509. p->update_pn_check_needed);
  510. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  511. UPDATE_PN_SHALL_BE_EVEN, p->update_pn_even);
  512. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  513. UPDATE_PN_SHALL_BE_UNEVEN, p->update_pn_uneven);
  514. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  515. UPDATE_PN_HANDLING_ENABLE,
  516. p->update_pn_hand_enab);
  517. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  518. UPDATE_PN_SIZE, p->update_pn_size);
  519. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  520. UPDATE_IGNORE_AMPDU_FLAG, p->update_ignore_ampdu);
  521. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  522. UPDATE_SVLD, p->update_svld);
  523. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  524. UPDATE_SSN, p->update_ssn);
  525. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  526. UPDATE_SEQ_2K_ERROR_DETECTED_FLAG,
  527. p->update_seq_2k_err_detect);
  528. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  529. UPDATE_PN_VALID, p->update_pn_valid);
  530. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  531. UPDATE_PN, p->update_pn);
  532. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  533. RECEIVE_QUEUE_NUMBER, p->rx_queue_num);
  534. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  535. VLD, p->vld);
  536. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  537. ASSOCIATED_LINK_DESCRIPTOR_COUNTER,
  538. p->assoc_link_desc);
  539. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  540. DISABLE_DUPLICATE_DETECTION,
  541. p->disable_dup_detect);
  542. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  543. SOFT_REORDER_ENABLE, p->soft_reorder_enab);
  544. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE, AC, p->ac);
  545. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  546. BAR, p->bar);
  547. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  548. CHK_2K_MODE, p->chk_2k_mode);
  549. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  550. RTY, p->rty);
  551. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  552. OOR_MODE, p->oor_mode);
  553. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  554. PN_CHECK_NEEDED, p->pn_check_needed);
  555. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  556. PN_SHALL_BE_EVEN, p->pn_even);
  557. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  558. PN_SHALL_BE_UNEVEN, p->pn_uneven);
  559. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  560. PN_HANDLING_ENABLE, p->pn_hand_enab);
  561. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  562. IGNORE_AMPDU_FLAG, p->ignore_ampdu);
  563. if (p->ba_window_size < 1)
  564. p->ba_window_size = 1;
  565. /*
  566. * WAR to get 2k exception in Non BA case.
  567. * Setting window size to 2 to get 2k jump exception
  568. * when we receive aggregates in Non BA case
  569. */
  570. if (p->ba_window_size == 1)
  571. p->ba_window_size++;
  572. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  573. BA_WINDOW_SIZE, p->ba_window_size - 1);
  574. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  575. PN_SIZE, p->pn_size);
  576. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  577. SVLD, p->svld);
  578. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  579. SSN, p->ssn);
  580. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  581. SEQ_2K_ERROR_DETECTED_FLAG, p->seq_2k_err_detect);
  582. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  583. PN_ERROR_DETECTED_FLAG, p->pn_err_detect);
  584. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  585. PN_31_0, p->pn_31_0);
  586. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  587. PN_63_32, p->pn_63_32);
  588. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  589. PN_95_64, p->pn_95_64);
  590. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  591. PN_127_96, p->pn_127_96);
  592. hal_srng_access_end_v1(hal_soc_hdl, hal_ring_hdl,
  593. HIF_RTPM_ID_HAL_REO_CMD);
  594. val = reo_desc[CMD_HEADER_DW_OFFSET];
  595. return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER, REO_CMD_NUMBER,
  596. val);
  597. }
  598. int hal_reo_send_cmd_be(hal_soc_handle_t hal_soc_hdl,
  599. hal_ring_handle_t hal_ring_hdl,
  600. enum hal_reo_cmd_type cmd,
  601. void *params)
  602. {
  603. struct hal_reo_cmd_params *cmd_params =
  604. (struct hal_reo_cmd_params *)params;
  605. int num = 0;
  606. switch (cmd) {
  607. case CMD_GET_QUEUE_STATS:
  608. num = hal_reo_cmd_queue_stats_be(hal_ring_hdl,
  609. hal_soc_hdl, cmd_params);
  610. break;
  611. case CMD_FLUSH_QUEUE:
  612. num = hal_reo_cmd_flush_queue_be(hal_ring_hdl,
  613. hal_soc_hdl, cmd_params);
  614. break;
  615. case CMD_FLUSH_CACHE:
  616. num = hal_reo_cmd_flush_cache_be(hal_ring_hdl,
  617. hal_soc_hdl, cmd_params);
  618. break;
  619. case CMD_UNBLOCK_CACHE:
  620. num = hal_reo_cmd_unblock_cache_be(hal_ring_hdl,
  621. hal_soc_hdl, cmd_params);
  622. break;
  623. case CMD_FLUSH_TIMEOUT_LIST:
  624. num = hal_reo_cmd_flush_timeout_list_be(hal_ring_hdl,
  625. hal_soc_hdl,
  626. cmd_params);
  627. break;
  628. case CMD_UPDATE_RX_REO_QUEUE:
  629. num = hal_reo_cmd_update_rx_queue_be(hal_ring_hdl,
  630. hal_soc_hdl, cmd_params);
  631. break;
  632. default:
  633. hal_err("Invalid REO command type: %d", cmd);
  634. return -EINVAL;
  635. };
  636. return num;
  637. }
  638. void
  639. hal_reo_queue_stats_status_be(hal_ring_desc_t ring_desc,
  640. void *st_handle,
  641. hal_soc_handle_t hal_soc_hdl)
  642. {
  643. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  644. struct hal_reo_queue_status *st =
  645. (struct hal_reo_queue_status *)st_handle;
  646. uint64_t *reo_desc = (uint64_t *)ring_desc;
  647. uint64_t val;
  648. /*
  649. * Offsets of descriptor fields defined in HW headers start
  650. * from the field after TLV header
  651. */
  652. reo_desc += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
  653. /* header */
  654. hal_reo_status_get_header(ring_desc, HAL_REO_QUEUE_STATS_STATUS_TLV,
  655. &(st->header), hal_soc);
  656. /* SSN */
  657. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, SSN)];
  658. st->ssn = HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS, SSN, val);
  659. /* current index */
  660. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  661. CURRENT_INDEX)];
  662. st->curr_idx =
  663. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  664. CURRENT_INDEX, val);
  665. /* PN bits */
  666. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  667. PN_31_0)];
  668. st->pn_31_0 =
  669. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  670. PN_31_0, val);
  671. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  672. PN_63_32)];
  673. st->pn_63_32 =
  674. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  675. PN_63_32, val);
  676. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  677. PN_95_64)];
  678. st->pn_95_64 =
  679. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  680. PN_95_64, val);
  681. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  682. PN_127_96)];
  683. st->pn_127_96 =
  684. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  685. PN_127_96, val);
  686. /* timestamps */
  687. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  688. LAST_RX_ENQUEUE_TIMESTAMP)];
  689. st->last_rx_enq_tstamp =
  690. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  691. LAST_RX_ENQUEUE_TIMESTAMP, val);
  692. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  693. LAST_RX_DEQUEUE_TIMESTAMP)];
  694. st->last_rx_deq_tstamp =
  695. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  696. LAST_RX_DEQUEUE_TIMESTAMP, val);
  697. /* rx bitmap */
  698. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  699. RX_BITMAP_31_0)];
  700. st->rx_bitmap_31_0 =
  701. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  702. RX_BITMAP_31_0, val);
  703. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  704. RX_BITMAP_63_32)];
  705. st->rx_bitmap_63_32 =
  706. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  707. RX_BITMAP_63_32, val);
  708. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  709. RX_BITMAP_95_64)];
  710. st->rx_bitmap_95_64 =
  711. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  712. RX_BITMAP_95_64, val);
  713. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  714. RX_BITMAP_127_96)];
  715. st->rx_bitmap_127_96 =
  716. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  717. RX_BITMAP_127_96, val);
  718. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  719. RX_BITMAP_159_128)];
  720. st->rx_bitmap_159_128 =
  721. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  722. RX_BITMAP_159_128, val);
  723. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  724. RX_BITMAP_191_160)];
  725. st->rx_bitmap_191_160 =
  726. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  727. RX_BITMAP_191_160, val);
  728. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  729. RX_BITMAP_223_192)];
  730. st->rx_bitmap_223_192 =
  731. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  732. RX_BITMAP_223_192, val);
  733. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  734. RX_BITMAP_255_224)];
  735. st->rx_bitmap_255_224 =
  736. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  737. RX_BITMAP_255_224, val);
  738. /* various counts */
  739. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  740. CURRENT_MPDU_COUNT)];
  741. st->curr_mpdu_cnt =
  742. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  743. CURRENT_MPDU_COUNT, val);
  744. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  745. CURRENT_MSDU_COUNT)];
  746. st->curr_msdu_cnt =
  747. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  748. CURRENT_MSDU_COUNT, val);
  749. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  750. TIMEOUT_COUNT)];
  751. st->fwd_timeout_cnt =
  752. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  753. TIMEOUT_COUNT, val);
  754. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  755. FORWARD_DUE_TO_BAR_COUNT)];
  756. st->fwd_bar_cnt =
  757. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  758. FORWARD_DUE_TO_BAR_COUNT, val);
  759. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  760. DUPLICATE_COUNT)];
  761. st->dup_cnt =
  762. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  763. DUPLICATE_COUNT, val);
  764. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  765. FRAMES_IN_ORDER_COUNT)];
  766. st->frms_in_order_cnt =
  767. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  768. FRAMES_IN_ORDER_COUNT, val);
  769. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  770. BAR_RECEIVED_COUNT)];
  771. st->bar_rcvd_cnt =
  772. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  773. BAR_RECEIVED_COUNT, val);
  774. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  775. MPDU_FRAMES_PROCESSED_COUNT)];
  776. st->mpdu_frms_cnt =
  777. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  778. MPDU_FRAMES_PROCESSED_COUNT, val);
  779. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  780. MSDU_FRAMES_PROCESSED_COUNT)];
  781. st->msdu_frms_cnt =
  782. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  783. MSDU_FRAMES_PROCESSED_COUNT, val);
  784. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  785. TOTAL_PROCESSED_BYTE_COUNT)];
  786. st->total_cnt =
  787. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  788. TOTAL_PROCESSED_BYTE_COUNT, val);
  789. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  790. LATE_RECEIVE_MPDU_COUNT)];
  791. st->late_recv_mpdu_cnt =
  792. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  793. LATE_RECEIVE_MPDU_COUNT, val);
  794. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  795. WINDOW_JUMP_2K)];
  796. st->win_jump_2k =
  797. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  798. WINDOW_JUMP_2K, val);
  799. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  800. HOLE_COUNT)];
  801. st->hole_cnt =
  802. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  803. HOLE_COUNT, val);
  804. }
  805. void
  806. hal_reo_flush_queue_status_be(hal_ring_desc_t ring_desc,
  807. void *st_handle,
  808. hal_soc_handle_t hal_soc_hdl)
  809. {
  810. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  811. struct hal_reo_flush_queue_status *st =
  812. (struct hal_reo_flush_queue_status *)st_handle;
  813. uint64_t *reo_desc = (uint64_t *)ring_desc;
  814. uint64_t val;
  815. /*
  816. * Offsets of descriptor fields defined in HW headers start
  817. * from the field after TLV header
  818. */
  819. reo_desc += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
  820. /* header */
  821. hal_reo_status_get_header(ring_desc, HAL_REO_FLUSH_QUEUE_STATUS_TLV,
  822. &(st->header), hal_soc);
  823. /* error bit */
  824. val = reo_desc[HAL_OFFSET(REO_FLUSH_QUEUE_STATUS,
  825. ERROR_DETECTED)];
  826. st->error = HAL_GET_FIELD(REO_FLUSH_QUEUE_STATUS, ERROR_DETECTED,
  827. val);
  828. }
  829. void
  830. hal_reo_flush_cache_status_be(hal_ring_desc_t ring_desc,
  831. void *st_handle,
  832. hal_soc_handle_t hal_soc_hdl)
  833. {
  834. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  835. struct hal_reo_flush_cache_status *st =
  836. (struct hal_reo_flush_cache_status *)st_handle;
  837. uint64_t *reo_desc = (uint64_t *)ring_desc;
  838. uint64_t val;
  839. /*
  840. * Offsets of descriptor fields defined in HW headers start
  841. * from the field after TLV header
  842. */
  843. reo_desc += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
  844. /* header */
  845. hal_reo_status_get_header(ring_desc, HAL_REO_FLUSH_CACHE_STATUS_TLV,
  846. &(st->header), hal_soc);
  847. /* error bit */
  848. val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
  849. ERROR_DETECTED)];
  850. st->error = HAL_GET_FIELD(REO_FLUSH_QUEUE_STATUS, ERROR_DETECTED,
  851. val);
  852. /* block error */
  853. val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
  854. BLOCK_ERROR_DETAILS)];
  855. st->block_error = HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS,
  856. BLOCK_ERROR_DETAILS,
  857. val);
  858. if (!st->block_error)
  859. qdf_set_bit(hal_soc->index,
  860. (unsigned long *)&hal_soc->reo_res_bitmap);
  861. /* cache flush status */
  862. val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
  863. CACHE_CONTROLLER_FLUSH_STATUS_HIT)];
  864. st->cache_flush_status = HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS,
  865. CACHE_CONTROLLER_FLUSH_STATUS_HIT,
  866. val);
  867. /* cache flush descriptor type */
  868. val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
  869. CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE)];
  870. st->cache_flush_status_desc_type =
  871. HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS,
  872. CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE,
  873. val);
  874. /* cache flush count */
  875. val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
  876. CACHE_CONTROLLER_FLUSH_COUNT)];
  877. st->cache_flush_cnt =
  878. HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS,
  879. CACHE_CONTROLLER_FLUSH_COUNT,
  880. val);
  881. }
  882. void
  883. hal_reo_unblock_cache_status_be(hal_ring_desc_t ring_desc,
  884. hal_soc_handle_t hal_soc_hdl,
  885. void *st_handle)
  886. {
  887. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  888. struct hal_reo_unblk_cache_status *st =
  889. (struct hal_reo_unblk_cache_status *)st_handle;
  890. uint64_t *reo_desc = (uint64_t *)ring_desc;
  891. uint64_t val;
  892. /*
  893. * Offsets of descriptor fields defined in HW headers start
  894. * from the field after TLV header
  895. */
  896. reo_desc += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
  897. /* header */
  898. hal_reo_status_get_header(ring_desc, HAL_REO_UNBLK_CACHE_STATUS_TLV,
  899. &st->header, hal_soc);
  900. /* error bit */
  901. val = reo_desc[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
  902. ERROR_DETECTED)];
  903. st->error = HAL_GET_FIELD(REO_UNBLOCK_CACHE_STATUS,
  904. ERROR_DETECTED,
  905. val);
  906. /* unblock type */
  907. val = reo_desc[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
  908. UNBLOCK_TYPE)];
  909. st->unblock_type = HAL_GET_FIELD(REO_UNBLOCK_CACHE_STATUS,
  910. UNBLOCK_TYPE,
  911. val);
  912. if (!st->error && (st->unblock_type == UNBLOCK_RES_INDEX))
  913. qdf_clear_bit(hal_soc->index,
  914. (unsigned long *)&hal_soc->reo_res_bitmap);
  915. }
  916. void hal_reo_flush_timeout_list_status_be(hal_ring_desc_t ring_desc,
  917. void *st_handle,
  918. hal_soc_handle_t hal_soc_hdl)
  919. {
  920. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  921. struct hal_reo_flush_timeout_list_status *st =
  922. (struct hal_reo_flush_timeout_list_status *)st_handle;
  923. uint64_t *reo_desc = (uint64_t *)ring_desc;
  924. uint64_t val;
  925. /*
  926. * Offsets of descriptor fields defined in HW headers start
  927. * from the field after TLV header
  928. */
  929. reo_desc += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
  930. /* header */
  931. hal_reo_status_get_header(ring_desc, HAL_REO_TIMOUT_LIST_STATUS_TLV,
  932. &(st->header), hal_soc);
  933. /* error bit */
  934. val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
  935. ERROR_DETECTED)];
  936. st->error = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS,
  937. ERROR_DETECTED,
  938. val);
  939. /* list empty */
  940. val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
  941. TIMOUT_LIST_EMPTY)];
  942. st->list_empty = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS,
  943. TIMOUT_LIST_EMPTY,
  944. val);
  945. /* release descriptor count */
  946. val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
  947. RELEASE_DESC_COUNT)];
  948. st->rel_desc_cnt = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS,
  949. RELEASE_DESC_COUNT,
  950. val);
  951. /* forward buf count */
  952. val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
  953. FORWARD_BUF_COUNT)];
  954. st->fwd_buf_cnt = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS,
  955. FORWARD_BUF_COUNT,
  956. val);
  957. }
  958. void hal_reo_desc_thres_reached_status_be(hal_ring_desc_t ring_desc,
  959. void *st_handle,
  960. hal_soc_handle_t hal_soc_hdl)
  961. {
  962. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  963. struct hal_reo_desc_thres_reached_status *st =
  964. (struct hal_reo_desc_thres_reached_status *)st_handle;
  965. uint64_t *reo_desc = (uint64_t *)ring_desc;
  966. uint64_t val;
  967. /*
  968. * Offsets of descriptor fields defined in HW headers start
  969. * from the field after TLV header
  970. */
  971. reo_desc += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
  972. /* header */
  973. hal_reo_status_get_header(ring_desc,
  974. HAL_REO_DESC_THRES_STATUS_TLV,
  975. &(st->header), hal_soc);
  976. /* threshold index */
  977. val = reo_desc[HAL_OFFSET_QW(
  978. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  979. THRESHOLD_INDEX)];
  980. st->thres_index = HAL_GET_FIELD(
  981. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  982. THRESHOLD_INDEX,
  983. val);
  984. /* link desc counters */
  985. val = reo_desc[HAL_OFFSET_QW(
  986. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  987. LINK_DESCRIPTOR_COUNTER0)];
  988. st->link_desc_counter0 = HAL_GET_FIELD(
  989. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  990. LINK_DESCRIPTOR_COUNTER0,
  991. val);
  992. val = reo_desc[HAL_OFFSET_QW(
  993. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  994. LINK_DESCRIPTOR_COUNTER1)];
  995. st->link_desc_counter1 = HAL_GET_FIELD(
  996. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  997. LINK_DESCRIPTOR_COUNTER1,
  998. val);
  999. val = reo_desc[HAL_OFFSET_QW(
  1000. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  1001. LINK_DESCRIPTOR_COUNTER2)];
  1002. st->link_desc_counter2 = HAL_GET_FIELD(
  1003. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  1004. LINK_DESCRIPTOR_COUNTER2,
  1005. val);
  1006. val = reo_desc[HAL_OFFSET_QW(
  1007. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  1008. LINK_DESCRIPTOR_COUNTER_SUM)];
  1009. st->link_desc_counter_sum = HAL_GET_FIELD(
  1010. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  1011. LINK_DESCRIPTOR_COUNTER_SUM,
  1012. val);
  1013. }
  1014. void
  1015. hal_reo_rx_update_queue_status_be(hal_ring_desc_t ring_desc,
  1016. void *st_handle,
  1017. hal_soc_handle_t hal_soc_hdl)
  1018. {
  1019. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1020. struct hal_reo_update_rx_queue_status *st =
  1021. (struct hal_reo_update_rx_queue_status *)st_handle;
  1022. uint64_t *reo_desc = (uint64_t *)ring_desc;
  1023. /*
  1024. * Offsets of descriptor fields defined in HW headers start
  1025. * from the field after TLV header
  1026. */
  1027. reo_desc += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
  1028. /* header */
  1029. hal_reo_status_get_header(ring_desc,
  1030. HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV,
  1031. &(st->header), hal_soc);
  1032. }
  1033. uint8_t hal_get_tlv_hdr_size_be(void)
  1034. {
  1035. return sizeof(struct tlv_32_hdr);
  1036. }