dp_be.h 22 KB

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  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef __DP_BE_H
  20. #define __DP_BE_H
  21. #include <dp_types.h>
  22. #include <hal_be_tx.h>
  23. #ifdef WLAN_MLO_MULTI_CHIP
  24. #include "mlo/dp_mlo.h"
  25. #else
  26. #include <dp_peer.h>
  27. #endif
  28. #ifdef WIFI_MONITOR_SUPPORT
  29. #include <dp_mon.h>
  30. #endif
  31. enum CMEM_MEM_CLIENTS {
  32. COOKIE_CONVERSION,
  33. FISA_FST,
  34. };
  35. /* maximum number of entries in one page of secondary page table */
  36. #define DP_CC_SPT_PAGE_MAX_ENTRIES 512
  37. /* maximum number of entries in one page of secondary page table */
  38. #define DP_CC_SPT_PAGE_MAX_ENTRIES_MASK (DP_CC_SPT_PAGE_MAX_ENTRIES - 1)
  39. /* maximum number of entries in primary page table */
  40. #define DP_CC_PPT_MAX_ENTRIES 1024
  41. /* cookie conversion required CMEM offset from CMEM pool */
  42. #define DP_CC_MEM_OFFSET_IN_CMEM 0
  43. /* cookie conversion primary page table size 4K */
  44. #define DP_CC_PPT_MEM_SIZE 4096
  45. /* FST required CMEM offset from CMEM pool */
  46. #define DP_FST_MEM_OFFSET_IN_CMEM \
  47. (DP_CC_MEM_OFFSET_IN_CMEM + DP_CC_PPT_MEM_SIZE)
  48. /* CMEM size for FISA FST 16K */
  49. #define DP_CMEM_FST_SIZE 16384
  50. /* lower 9 bits in Desc ID for offset in page of SPT */
  51. #define DP_CC_DESC_ID_SPT_VA_OS_SHIFT 0
  52. #define DP_CC_DESC_ID_SPT_VA_OS_MASK 0x1FF
  53. #define DP_CC_DESC_ID_SPT_VA_OS_LSB 0
  54. #define DP_CC_DESC_ID_SPT_VA_OS_MSB 8
  55. /* higher 11 bits in Desc ID for offset in CMEM of PPT */
  56. #define DP_CC_DESC_ID_PPT_PAGE_OS_LSB 9
  57. #define DP_CC_DESC_ID_PPT_PAGE_OS_MSB 19
  58. #define DP_CC_DESC_ID_PPT_PAGE_OS_SHIFT 9
  59. #define DP_CC_DESC_ID_PPT_PAGE_OS_MASK 0xFFE00
  60. /*
  61. * page 4K unaligned case, single SPT page physical address
  62. * need 8 bytes in PPT
  63. */
  64. #define DP_CC_PPT_ENTRY_SIZE_4K_UNALIGNED 8
  65. /*
  66. * page 4K aligned case, single SPT page physical address
  67. * need 4 bytes in PPT
  68. */
  69. #define DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED 4
  70. /* 4K aligned case, number of bits HW append for one PPT entry value */
  71. #define DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED 12
  72. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  73. /* WBM2SW ring id for rx release */
  74. #define WBM2SW_REL_ERR_RING_NUM 3
  75. #else
  76. /* WBM2SW ring id for rx release */
  77. #define WBM2SW_REL_ERR_RING_NUM 5
  78. #endif
  79. /* tx descriptor are programmed at start of CMEM region*/
  80. #define DP_TX_DESC_CMEM_OFFSET 0
  81. /* size of CMEM needed for a tx desc pool*/
  82. #define DP_TX_DESC_POOL_CMEM_SIZE \
  83. ((WLAN_CFG_NUM_TX_DESC_MAX / DP_CC_SPT_PAGE_MAX_ENTRIES) * \
  84. DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)
  85. /* Offset of rx descripotor pool */
  86. #define DP_RX_DESC_CMEM_OFFSET \
  87. DP_TX_DESC_CMEM_OFFSET + (MAX_TXDESC_POOLS * DP_TX_DESC_POOL_CMEM_SIZE)
  88. /* size of CMEM needed for a rx desc pool */
  89. #define DP_RX_DESC_POOL_CMEM_SIZE \
  90. ((WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX / DP_CC_SPT_PAGE_MAX_ENTRIES) * \
  91. DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)
  92. /* get ppt_id from CMEM_OFFSET */
  93. #define DP_CMEM_OFFSET_TO_PPT_ID(offset) \
  94. ((offset) / DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)
  95. /* The MAX PPE PRI2TID */
  96. #ifdef WLAN_SUPPORT_PPEDS
  97. #define DP_TX_INT_PRI2TID_MAX 15
  98. #endif
  99. /**
  100. * struct dp_spt_page_desc - secondary page table page descriptors
  101. * @next: pointer to next linked SPT page Desc
  102. * @page_v_addr: page virtual address
  103. * @page_p_addr: page physical address
  104. * @ppt_index: entry index in primary page table where this page physical
  105. address stored
  106. * @avail_entry_index: index for available entry that store TX/RX Desc VA
  107. */
  108. struct dp_spt_page_desc {
  109. uint8_t *page_v_addr;
  110. qdf_dma_addr_t page_p_addr;
  111. uint32_t ppt_index;
  112. };
  113. /**
  114. * struct dp_hw_cookie_conversion_t - main context for HW cookie conversion
  115. * @cmem_offset: CMEM offset from base address for primary page table setup
  116. * @total_page_num: total DDR page allocated
  117. * @page_desc_freelist: available page Desc list
  118. * @page_desc_base: page Desc buffer base address.
  119. * @page_pool: DDR pages pool
  120. * @cc_lock: locks for page acquiring/free
  121. */
  122. struct dp_hw_cookie_conversion_t {
  123. uint32_t cmem_offset;
  124. uint32_t total_page_num;
  125. struct dp_spt_page_desc *page_desc_base;
  126. struct qdf_mem_multi_page_t page_pool;
  127. qdf_spinlock_t cc_lock;
  128. };
  129. /**
  130. * struct dp_spt_page_desc_list - containor of SPT page desc list info
  131. * @spt_page_list_head: head of SPT page descriptor list
  132. * @spt_page_list_tail: tail of SPT page descriptor list
  133. * @num_spt_pages: number of SPT page descriptor allocated
  134. */
  135. struct dp_spt_page_desc_list {
  136. struct dp_spt_page_desc *spt_page_list_head;
  137. struct dp_spt_page_desc *spt_page_list_tail;
  138. uint16_t num_spt_pages;
  139. };
  140. /* HW reading 8 bytes for VA */
  141. #define DP_CC_HW_READ_BYTES 8
  142. #define DP_CC_SPT_PAGE_UPDATE_VA(_page_base_va, _index, _desc_va) \
  143. { *((uintptr_t *)((_page_base_va) + (_index) * DP_CC_HW_READ_BYTES)) \
  144. = (uintptr_t)(_desc_va); }
  145. /**
  146. * struct dp_tx_bank_profile - DP wrapper for TCL banks
  147. * @is_configured: flag indicating if this bank is configured
  148. * @ref_count: ref count indicating number of users of the bank
  149. * @bank_config: HAL TX bank configuration
  150. */
  151. struct dp_tx_bank_profile {
  152. uint8_t is_configured;
  153. qdf_atomic_t ref_count;
  154. union hal_tx_bank_config bank_config;
  155. };
  156. #ifdef WLAN_SUPPORT_PPEDS
  157. /**
  158. * struct dp_ppe_vp_tbl_entry - PPE Virtual table entry
  159. * @is_configured: Boolean that the entry is configured.
  160. */
  161. struct dp_ppe_vp_tbl_entry {
  162. bool is_configured;
  163. };
  164. /**
  165. * struct dp_ppe_vp_profile - PPE direct switch profiler per vdev
  166. * @vp_num: Virtual port number
  167. * @ppe_vp_num_idx: Index to the PPE VP table entry
  168. * @search_idx_reg_num: Address search Index register number
  169. * @drop_prec_enable: Drop precedance enable
  170. * @to_fw: To FW exception enable/disable.
  171. * @use_ppe_int_pri: Use PPE INT_PRI to TID mapping table
  172. */
  173. struct dp_ppe_vp_profile {
  174. uint8_t vp_num;
  175. uint8_t ppe_vp_num_idx;
  176. uint8_t search_idx_reg_num;
  177. uint8_t drop_prec_enable;
  178. uint8_t to_fw;
  179. uint8_t use_ppe_int_pri;
  180. };
  181. #endif
  182. /**
  183. * struct dp_soc_be - Extended DP soc for BE targets
  184. * @soc: dp soc structure
  185. * @num_bank_profiles: num TX bank profiles
  186. * @bank_profiles: bank profiles for various TX banks
  187. * @cc_cmem_base: cmem offset reserved for CC
  188. * @tx_cc_ctx: Cookie conversion context for tx desc pools
  189. * @rx_cc_ctx: Cookie conversion context for rx desc pools
  190. * @monitor_soc_be: BE specific monitor object
  191. * @mlo_enabled: Flag to indicate MLO is enabled or not
  192. * @mlo_chip_id: MLO chip_id
  193. * @ml_ctxt: pointer to global ml_context
  194. * @delta_tqm: delta_tqm
  195. * @mlo_tstamp_offset: mlo timestamp offset
  196. * @mld_peer_hash: peer hash table for ML peers
  197. * Associated peer with this MAC address)
  198. * @mld_peer_hash_lock: lock to protect mld_peer_hash
  199. * @reo2ppe_ring: REO2PPE ring
  200. * @ppe2tcl_ring: PPE2TCL ring
  201. * @ppe_release_ring: PPE release ring
  202. * @ppe_vp_tbl: PPE VP table
  203. * @ppe_vp_tbl_lock: PPE VP table lock
  204. * @num_ppe_vp_entries : Number of PPE VP entries
  205. * @ipa_bank_id: TCL bank id used by IPA
  206. */
  207. struct dp_soc_be {
  208. struct dp_soc soc;
  209. uint8_t num_bank_profiles;
  210. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  211. qdf_mutex_t tx_bank_lock;
  212. #else
  213. qdf_spinlock_t tx_bank_lock;
  214. #endif
  215. struct dp_tx_bank_profile *bank_profiles;
  216. struct dp_spt_page_desc *page_desc_base;
  217. uint32_t cc_cmem_base;
  218. struct dp_hw_cookie_conversion_t tx_cc_ctx[MAX_TXDESC_POOLS];
  219. struct dp_hw_cookie_conversion_t rx_cc_ctx[MAX_RXDESC_POOLS];
  220. #ifdef WLAN_SUPPORT_PPEDS
  221. struct dp_srng reo2ppe_ring;
  222. struct dp_srng ppe2tcl_ring;
  223. struct dp_srng ppe_release_ring;
  224. struct dp_ppe_vp_tbl_entry *ppe_vp_tbl;
  225. qdf_mutex_t ppe_vp_tbl_lock;
  226. uint8_t num_ppe_vp_entries;
  227. #endif
  228. #ifdef WLAN_FEATURE_11BE_MLO
  229. #ifdef WLAN_MLO_MULTI_CHIP
  230. uint8_t mlo_enabled;
  231. uint8_t mlo_chip_id;
  232. struct dp_mlo_ctxt *ml_ctxt;
  233. uint64_t delta_tqm;
  234. uint64_t mlo_tstamp_offset;
  235. #else
  236. /* Protect mld peer hash table */
  237. DP_MUTEX_TYPE mld_peer_hash_lock;
  238. struct {
  239. uint32_t mask;
  240. uint32_t idx_bits;
  241. TAILQ_HEAD(, dp_peer) * bins;
  242. } mld_peer_hash;
  243. #endif
  244. #endif
  245. #ifdef IPA_OFFLOAD
  246. int8_t ipa_bank_id;
  247. #endif
  248. };
  249. /* convert struct dp_soc_be pointer to struct dp_soc pointer */
  250. #define DP_SOC_BE_GET_SOC(be_soc) ((struct dp_soc *)be_soc)
  251. /**
  252. * struct dp_pdev_be - Extended DP pdev for BE targets
  253. * @pdev: dp pdev structure
  254. * @monitor_pdev_be: BE specific monitor object
  255. * @mlo_link_id: MLO link id for PDEV
  256. * @delta_tsf2: delta_tsf2
  257. */
  258. struct dp_pdev_be {
  259. struct dp_pdev pdev;
  260. #ifdef WLAN_MLO_MULTI_CHIP
  261. uint8_t mlo_link_id;
  262. uint64_t delta_tsf2;
  263. #endif
  264. };
  265. /**
  266. * struct dp_vdev_be - Extended DP vdev for BE targets
  267. * @vdev: dp vdev structure
  268. * @bank_id: bank_id to be used for TX
  269. * @vdev_id_check_en: flag if HW vdev_id check is enabled for vdev
  270. * @ppe_vp_enabled: flag to check if PPE VP is enabled for vdev
  271. * @ppe_vp_profile: PPE VP profile
  272. */
  273. struct dp_vdev_be {
  274. struct dp_vdev vdev;
  275. int8_t bank_id;
  276. uint8_t vdev_id_check_en;
  277. #ifdef WLAN_MLO_MULTI_CHIP
  278. /* partner list used for Intra-BSS */
  279. uint8_t partner_vdev_list[WLAN_MAX_MLO_CHIPS][WLAN_MAX_MLO_LINKS_PER_SOC];
  280. #ifdef WLAN_FEATURE_11BE_MLO
  281. #ifdef WLAN_MCAST_MLO
  282. /* DP MLO seq number */
  283. uint16_t seq_num;
  284. /* MLO Mcast primary vdev */
  285. bool mcast_primary;
  286. #endif
  287. #endif
  288. #endif
  289. unsigned long ppe_vp_enabled;
  290. #ifdef WLAN_SUPPORT_PPEDS
  291. struct dp_ppe_vp_profile ppe_vp_profile;
  292. #endif
  293. };
  294. /**
  295. * struct dp_peer_be - Extended DP peer for BE targets
  296. * @dp_peer: dp peer structure
  297. */
  298. struct dp_peer_be {
  299. struct dp_peer peer;
  300. };
  301. /**
  302. * dp_get_soc_context_size_be() - get context size for target specific DP soc
  303. *
  304. * Return: value in bytes for BE specific soc structure
  305. */
  306. qdf_size_t dp_get_soc_context_size_be(void);
  307. /**
  308. * dp_initialize_arch_ops_be() - initialize BE specific arch ops
  309. * @arch_ops: arch ops pointer
  310. *
  311. * Return: none
  312. */
  313. void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops);
  314. /**
  315. * dp_get_context_size_be() - get BE specific size for peer/vdev/pdev/soc
  316. * @arch_ops: arch ops pointer
  317. *
  318. * Return: size in bytes for the context_type
  319. */
  320. qdf_size_t dp_get_context_size_be(enum dp_context_type context_type);
  321. /**
  322. * dp_get_be_soc_from_dp_soc() - get dp_soc_be from dp_soc
  323. * @soc: dp_soc pointer
  324. *
  325. * Return: dp_soc_be pointer
  326. */
  327. static inline struct dp_soc_be *dp_get_be_soc_from_dp_soc(struct dp_soc *soc)
  328. {
  329. return (struct dp_soc_be *)soc;
  330. }
  331. #ifdef WLAN_MLO_MULTI_CHIP
  332. typedef struct dp_mlo_ctxt *dp_mld_peer_hash_obj_t;
  333. /*
  334. * dp_mlo_get_peer_hash_obj() - return the container struct of MLO hash table
  335. *
  336. * @soc: soc handle
  337. *
  338. * return: MLD peer hash object
  339. */
  340. static inline dp_mld_peer_hash_obj_t
  341. dp_mlo_get_peer_hash_obj(struct dp_soc *soc)
  342. {
  343. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  344. return be_soc->ml_ctxt;
  345. }
  346. void dp_clr_mlo_ptnr_list(struct dp_soc *soc, struct dp_vdev *vdev);
  347. #if defined(WLAN_FEATURE_11BE_MLO)
  348. /**
  349. * dp_mlo_partner_chips_map() - Map MLO peers to partner SOCs
  350. * @soc: Soc handle
  351. * @peer: DP peer handle for ML peer
  352. * @peer_id: peer_id
  353. * Return: None
  354. */
  355. void dp_mlo_partner_chips_map(struct dp_soc *soc,
  356. struct dp_peer *peer,
  357. uint16_t peer_id);
  358. /**
  359. * dp_mlo_partner_chips_unmap() - Unmap MLO peers to partner SOCs
  360. * @soc: Soc handle
  361. * @peer_id: peer_id
  362. * Return: None
  363. */
  364. void dp_mlo_partner_chips_unmap(struct dp_soc *soc,
  365. uint16_t peer_id);
  366. #ifdef WLAN_MCAST_MLO
  367. typedef void dp_ptnr_vdev_iter_func(struct dp_vdev_be *be_vdev,
  368. struct dp_vdev *ptnr_vdev,
  369. void *arg);
  370. typedef void dp_ptnr_soc_iter_func(struct dp_soc *ptnr_soc,
  371. void *arg);
  372. /*
  373. * dp_mcast_mlo_iter_ptnr_vdev - API to iterate through ptnr vdev list
  374. * @be_soc: dp_soc_be pointer
  375. * @be_vdev: dp_vdev_be pointer
  376. * @func : function to be called for each peer
  377. * @arg : argument need to be passed to func
  378. * @mod_id: module id
  379. *
  380. * Return: None
  381. */
  382. void dp_mcast_mlo_iter_ptnr_vdev(struct dp_soc_be *be_soc,
  383. struct dp_vdev_be *be_vdev,
  384. dp_ptnr_vdev_iter_func func,
  385. void *arg,
  386. enum dp_mod_id mod_id);
  387. /*
  388. * dp_mcast_mlo_iter_ptnr_soc - API to iterate through ptnr soc list
  389. * @be_soc: dp_soc_be pointer
  390. * @func : function to be called for each peer
  391. * @arg : argument need to be passed to func
  392. *
  393. * Return: None
  394. */
  395. void dp_mcast_mlo_iter_ptnr_soc(struct dp_soc_be *be_soc,
  396. dp_ptnr_soc_iter_func func,
  397. void *arg);
  398. /*
  399. * dp_mlo_get_mcast_primary_vdev- get ref to mcast primary vdev
  400. * @be_soc: dp_soc_be pointer
  401. * @be_vdev: dp_vdev_be pointer
  402. * @mod_id: module id
  403. *
  404. * Return: mcast primary DP VDEV handle on success, NULL on failure
  405. */
  406. struct dp_vdev *dp_mlo_get_mcast_primary_vdev(struct dp_soc_be *be_soc,
  407. struct dp_vdev_be *be_vdev,
  408. enum dp_mod_id mod_id);
  409. #endif
  410. #endif
  411. #else
  412. typedef struct dp_soc_be *dp_mld_peer_hash_obj_t;
  413. static inline dp_mld_peer_hash_obj_t
  414. dp_mlo_get_peer_hash_obj(struct dp_soc *soc)
  415. {
  416. return dp_get_be_soc_from_dp_soc(soc);
  417. }
  418. static inline void dp_clr_mlo_ptnr_list(struct dp_soc *soc,
  419. struct dp_vdev *vdev)
  420. {
  421. }
  422. #endif
  423. /*
  424. * dp_mlo_peer_find_hash_attach_be() - API to initialize ML peer hash table
  425. *
  426. * @mld_hash_obj: Peer has object
  427. * @hash_elems: number of entries in hash table
  428. *
  429. * return: QDF_STATUS_SUCCESS when attach is success else QDF_STATUS_FAILURE
  430. */
  431. QDF_STATUS
  432. dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj,
  433. int hash_elems);
  434. /*
  435. * dp_mlo_peer_find_hash_detach_be() - API to de-initialize ML peer hash table
  436. *
  437. * @mld_hash_obj: Peer has object
  438. *
  439. * return: void
  440. */
  441. void dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj);
  442. /**
  443. * dp_get_be_pdev_from_dp_pdev() - get dp_pdev_be from dp_pdev
  444. * @pdev: dp_pdev pointer
  445. *
  446. * Return: dp_pdev_be pointer
  447. */
  448. static inline
  449. struct dp_pdev_be *dp_get_be_pdev_from_dp_pdev(struct dp_pdev *pdev)
  450. {
  451. return (struct dp_pdev_be *)pdev;
  452. }
  453. /**
  454. * dp_get_be_vdev_from_dp_vdev() - get dp_vdev_be from dp_vdev
  455. * @vdev: dp_vdev pointer
  456. *
  457. * Return: dp_vdev_be pointer
  458. */
  459. static inline
  460. struct dp_vdev_be *dp_get_be_vdev_from_dp_vdev(struct dp_vdev *vdev)
  461. {
  462. return (struct dp_vdev_be *)vdev;
  463. }
  464. /**
  465. * dp_get_be_peer_from_dp_peer() - get dp_peer_be from dp_peer
  466. * @peer: dp_peer pointer
  467. *
  468. * Return: dp_peer_be pointer
  469. */
  470. static inline
  471. struct dp_peer_be *dp_get_be_peer_from_dp_peer(struct dp_peer *peer)
  472. {
  473. return (struct dp_peer_be *)peer;
  474. }
  475. QDF_STATUS
  476. dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc,
  477. struct dp_hw_cookie_conversion_t *cc_ctx,
  478. uint32_t num_descs,
  479. enum dp_desc_type desc_type,
  480. uint8_t desc_pool_id);
  481. QDF_STATUS
  482. dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc,
  483. struct dp_hw_cookie_conversion_t *cc_ctx);
  484. QDF_STATUS
  485. dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc,
  486. struct dp_hw_cookie_conversion_t *cc_ctx);
  487. QDF_STATUS
  488. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  489. struct dp_hw_cookie_conversion_t *cc_ctx);
  490. /**
  491. * dp_cc_spt_page_desc_alloc() - allocate SPT DDR page descriptor from pool
  492. * @be_soc: beryllium soc handler
  493. * @list_head: pointer to page desc head
  494. * @list_tail: pointer to page desc tail
  495. * @num_desc: number of TX/RX Descs required for SPT pages
  496. *
  497. * Return: number of SPT page Desc allocated
  498. */
  499. uint16_t dp_cc_spt_page_desc_alloc(struct dp_soc_be *be_soc,
  500. struct dp_spt_page_desc **list_head,
  501. struct dp_spt_page_desc **list_tail,
  502. uint16_t num_desc);
  503. /**
  504. * dp_cc_spt_page_desc_free() - free SPT DDR page descriptor to pool
  505. * @be_soc: beryllium soc handler
  506. * @list_head: pointer to page desc head
  507. * @list_tail: pointer to page desc tail
  508. * @page_nums: number of page desc freed back to pool
  509. */
  510. void dp_cc_spt_page_desc_free(struct dp_soc_be *be_soc,
  511. struct dp_spt_page_desc **list_head,
  512. struct dp_spt_page_desc **list_tail,
  513. uint16_t page_nums);
  514. /**
  515. * dp_cc_desc_id_generate() - generate SW cookie ID according to
  516. DDR page 4K aligned or not
  517. * @ppt_index: offset index in primary page table
  518. * @spt_index: offset index in sceondary DDR page
  519. *
  520. * Generate SW cookie ID to match as HW expected
  521. *
  522. * Return: cookie ID
  523. */
  524. static inline uint32_t dp_cc_desc_id_generate(uint32_t ppt_index,
  525. uint16_t spt_index)
  526. {
  527. /*
  528. * for 4k aligned case, cmem entry size is 4 bytes,
  529. * HW index from bit19~bit10 value = ppt_index / 2, high 32bits flag
  530. * from bit9 value = ppt_index % 2, then bit 19 ~ bit9 value is
  531. * exactly same with original ppt_index value.
  532. * for 4k un-aligned case, cmem entry size is 8 bytes.
  533. * bit19 ~ bit9 will be HW index value, same as ppt_index value.
  534. */
  535. return ((((uint32_t)ppt_index) << DP_CC_DESC_ID_PPT_PAGE_OS_SHIFT) |
  536. spt_index);
  537. }
  538. /**
  539. * dp_cc_desc_va_find() - find TX/RX Descs virtual address by ID
  540. * @be_soc: be soc handle
  541. * @desc_id: TX/RX Dess ID
  542. *
  543. * Return: TX/RX Desc virtual address
  544. */
  545. static inline uintptr_t dp_cc_desc_find(struct dp_soc *soc,
  546. uint32_t desc_id)
  547. {
  548. struct dp_soc_be *be_soc;
  549. uint16_t ppt_page_id, spt_va_id;
  550. uint8_t *spt_page_va;
  551. be_soc = dp_get_be_soc_from_dp_soc(soc);
  552. ppt_page_id = (desc_id & DP_CC_DESC_ID_PPT_PAGE_OS_MASK) >>
  553. DP_CC_DESC_ID_PPT_PAGE_OS_SHIFT;
  554. spt_va_id = (desc_id & DP_CC_DESC_ID_SPT_VA_OS_MASK) >>
  555. DP_CC_DESC_ID_SPT_VA_OS_SHIFT;
  556. /*
  557. * ppt index in cmem is same order where the page in the
  558. * page desc array during initialization.
  559. * entry size in DDR page is 64 bits, for 32 bits system,
  560. * only lower 32 bits VA value is needed.
  561. */
  562. spt_page_va = be_soc->page_desc_base[ppt_page_id].page_v_addr;
  563. return (*((uintptr_t *)(spt_page_va +
  564. spt_va_id * DP_CC_HW_READ_BYTES)));
  565. }
  566. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  567. /**
  568. * enum dp_srng_near_full_levels - SRNG Near FULL levels
  569. * @DP_SRNG_THRESH_SAFE: SRNG level safe for yielding the near full mode
  570. * of processing the entries in SRNG
  571. * @DP_SRNG_THRESH_NEAR_FULL: SRNG level enters the near full mode
  572. * of processing the entries in SRNG
  573. * @DP_SRNG_THRESH_CRITICAL: SRNG level enters the critical level of full
  574. * condition and drastic steps need to be taken for processing
  575. * the entries in SRNG
  576. */
  577. enum dp_srng_near_full_levels {
  578. DP_SRNG_THRESH_SAFE,
  579. DP_SRNG_THRESH_NEAR_FULL,
  580. DP_SRNG_THRESH_CRITICAL,
  581. };
  582. /**
  583. * dp_srng_check_ring_near_full() - Check if SRNG is marked as near-full from
  584. * its corresponding near-full irq handler
  585. * @soc: Datapath SoC handle
  586. * @dp_srng: datapath handle for this SRNG
  587. *
  588. * Return: 1, if the srng was marked as near-full
  589. * 0, if the srng was not marked as near-full
  590. */
  591. static inline int dp_srng_check_ring_near_full(struct dp_soc *soc,
  592. struct dp_srng *dp_srng)
  593. {
  594. return qdf_atomic_read(&dp_srng->near_full);
  595. }
  596. /**
  597. * dp_srng_get_near_full_level() - Check the num available entries in the
  598. * consumer srng and return the level of the srng
  599. * near full state.
  600. * @soc: Datapath SoC Handle [To be validated by the caller]
  601. * @hal_ring_hdl: SRNG handle
  602. *
  603. * Return: near-full level
  604. */
  605. static inline int
  606. dp_srng_get_near_full_level(struct dp_soc *soc, struct dp_srng *dp_srng)
  607. {
  608. uint32_t num_valid;
  609. num_valid = hal_srng_dst_num_valid_nolock(soc->hal_soc,
  610. dp_srng->hal_srng,
  611. true);
  612. if (num_valid > dp_srng->crit_thresh)
  613. return DP_SRNG_THRESH_CRITICAL;
  614. else if (num_valid < dp_srng->safe_thresh)
  615. return DP_SRNG_THRESH_SAFE;
  616. else
  617. return DP_SRNG_THRESH_NEAR_FULL;
  618. }
  619. #define DP_SRNG_PER_LOOP_NF_REAP_MULTIPLIER 2
  620. /**
  621. * dp_srng_test_and_update_nf_params() - Test the near full level and update
  622. * the reap_limit and flags to reflect the state.
  623. * @soc: Datapath soc handle
  624. * @srng: Datapath handle for the srng
  625. * @max_reap_limit: [Output Param] Buffer to set the map_reap_limit as
  626. * per the near-full state
  627. *
  628. * Return: 1, if the srng is near full
  629. * 0, if the srng is not near full
  630. */
  631. static inline int
  632. _dp_srng_test_and_update_nf_params(struct dp_soc *soc,
  633. struct dp_srng *srng,
  634. int *max_reap_limit)
  635. {
  636. int ring_near_full = 0, near_full_level;
  637. if (dp_srng_check_ring_near_full(soc, srng)) {
  638. near_full_level = dp_srng_get_near_full_level(soc, srng);
  639. switch (near_full_level) {
  640. case DP_SRNG_THRESH_CRITICAL:
  641. /* Currently not doing anything special here */
  642. fallthrough;
  643. case DP_SRNG_THRESH_NEAR_FULL:
  644. ring_near_full = 1;
  645. *max_reap_limit *= DP_SRNG_PER_LOOP_NF_REAP_MULTIPLIER;
  646. break;
  647. case DP_SRNG_THRESH_SAFE:
  648. qdf_atomic_set(&srng->near_full, 0);
  649. ring_near_full = 0;
  650. break;
  651. default:
  652. qdf_assert(0);
  653. break;
  654. }
  655. }
  656. return ring_near_full;
  657. }
  658. #else
  659. static inline int
  660. _dp_srng_test_and_update_nf_params(struct dp_soc *soc,
  661. struct dp_srng *srng,
  662. int *max_reap_limit)
  663. {
  664. return 0;
  665. }
  666. #endif
  667. static inline
  668. uint32_t dp_desc_pool_get_cmem_base(uint8_t chip_id, uint8_t desc_pool_id,
  669. enum dp_desc_type desc_type)
  670. {
  671. switch (desc_type) {
  672. case DP_TX_DESC_TYPE:
  673. return (DP_TX_DESC_CMEM_OFFSET +
  674. (desc_pool_id * DP_TX_DESC_POOL_CMEM_SIZE));
  675. case DP_RX_DESC_BUF_TYPE:
  676. return (DP_RX_DESC_CMEM_OFFSET +
  677. ((chip_id * MAX_RXDESC_POOLS) + desc_pool_id) *
  678. DP_RX_DESC_POOL_CMEM_SIZE);
  679. default:
  680. QDF_BUG(0);
  681. }
  682. return 0;
  683. }
  684. #ifndef WLAN_MLO_MULTI_CHIP
  685. static inline
  686. void dp_soc_mlo_fill_params(struct dp_soc *soc,
  687. struct cdp_soc_attach_params *params)
  688. {
  689. }
  690. static inline
  691. void dp_pdev_mlo_fill_params(struct dp_pdev *pdev,
  692. struct cdp_pdev_attach_params *params)
  693. {
  694. }
  695. static inline
  696. void dp_mlo_update_link_to_pdev_map(struct dp_soc *soc, struct dp_pdev *pdev)
  697. {
  698. }
  699. static inline
  700. void dp_mlo_update_link_to_pdev_unmap(struct dp_soc *soc, struct dp_pdev *pdev)
  701. {
  702. }
  703. #endif
  704. /*
  705. * dp_txrx_set_vdev_param_be: target specific ops while setting vdev params
  706. * @soc : DP soc handle
  707. * @vdev: pointer to vdev structure
  708. * @param: parameter type to get value
  709. * @val: value
  710. *
  711. * return: QDF_STATUS
  712. */
  713. QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc,
  714. struct dp_vdev *vdev,
  715. enum cdp_vdev_param_type param,
  716. cdp_config_param_type val);
  717. #endif