sde_encoder_phys_wb.c 52 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  6. #include <linux/debugfs.h>
  7. #include <drm/sde_drm.h>
  8. #include "sde_encoder_phys.h"
  9. #include "sde_formats.h"
  10. #include "sde_hw_top.h"
  11. #include "sde_hw_interrupts.h"
  12. #include "sde_core_irq.h"
  13. #include "sde_wb.h"
  14. #include "sde_vbif.h"
  15. #include "sde_crtc.h"
  16. #define to_sde_encoder_phys_wb(x) \
  17. container_of(x, struct sde_encoder_phys_wb, base)
  18. #define WBID(wb_enc) \
  19. ((wb_enc && wb_enc->wb_dev) ? wb_enc->wb_dev->wb_idx - WB_0 : -1)
  20. #define TO_S15D16(_x_) ((_x_) << 7)
  21. static const u32 cwb_irq_tbl[PINGPONG_MAX] = {SDE_NONE, INTR_IDX_PP1_OVFL,
  22. INTR_IDX_PP2_OVFL, INTR_IDX_PP3_OVFL, INTR_IDX_PP4_OVFL,
  23. INTR_IDX_PP5_OVFL, SDE_NONE, SDE_NONE};
  24. /**
  25. * sde_rgb2yuv_601l - rgb to yuv color space conversion matrix
  26. *
  27. */
  28. static struct sde_csc_cfg sde_encoder_phys_wb_rgb2yuv_601l = {
  29. {
  30. TO_S15D16(0x0083), TO_S15D16(0x0102), TO_S15D16(0x0032),
  31. TO_S15D16(0x1fb5), TO_S15D16(0x1f6c), TO_S15D16(0x00e1),
  32. TO_S15D16(0x00e1), TO_S15D16(0x1f45), TO_S15D16(0x1fdc)
  33. },
  34. { 0x00, 0x00, 0x00 },
  35. { 0x0040, 0x0200, 0x0200 },
  36. { 0x000, 0x3ff, 0x000, 0x3ff, 0x000, 0x3ff },
  37. { 0x040, 0x3ac, 0x040, 0x3c0, 0x040, 0x3c0 },
  38. };
  39. /**
  40. * sde_encoder_phys_wb_is_master - report wb always as master encoder
  41. */
  42. static bool sde_encoder_phys_wb_is_master(struct sde_encoder_phys *phys_enc)
  43. {
  44. return true;
  45. }
  46. /**
  47. * sde_encoder_phys_wb_get_intr_type - get interrupt type based on block mode
  48. * @hw_wb: Pointer to h/w writeback driver
  49. */
  50. static enum sde_intr_type sde_encoder_phys_wb_get_intr_type(
  51. struct sde_hw_wb *hw_wb)
  52. {
  53. return (hw_wb->caps->features & BIT(SDE_WB_BLOCK_MODE)) ?
  54. SDE_IRQ_TYPE_WB_ROT_COMP : SDE_IRQ_TYPE_WB_WFD_COMP;
  55. }
  56. /**
  57. * sde_encoder_phys_wb_set_ot_limit - set OT limit for writeback interface
  58. * @phys_enc: Pointer to physical encoder
  59. */
  60. static void sde_encoder_phys_wb_set_ot_limit(
  61. struct sde_encoder_phys *phys_enc)
  62. {
  63. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  64. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  65. struct sde_vbif_set_ot_params ot_params;
  66. memset(&ot_params, 0, sizeof(ot_params));
  67. ot_params.xin_id = hw_wb->caps->xin_id;
  68. ot_params.num = hw_wb->idx - WB_0;
  69. ot_params.width = wb_enc->wb_roi.w;
  70. ot_params.height = wb_enc->wb_roi.h;
  71. ot_params.is_wfd = true;
  72. ot_params.frame_rate = phys_enc->cached_mode.vrefresh;
  73. ot_params.vbif_idx = hw_wb->caps->vbif_idx;
  74. ot_params.clk_ctrl = hw_wb->caps->clk_ctrl;
  75. ot_params.rd = false;
  76. sde_vbif_set_ot_limit(phys_enc->sde_kms, &ot_params);
  77. }
  78. /**
  79. * sde_encoder_phys_wb_set_qos_remap - set QoS remapper for writeback
  80. * @phys_enc: Pointer to physical encoder
  81. */
  82. static void sde_encoder_phys_wb_set_qos_remap(
  83. struct sde_encoder_phys *phys_enc)
  84. {
  85. struct sde_encoder_phys_wb *wb_enc;
  86. struct sde_hw_wb *hw_wb;
  87. struct drm_crtc *crtc;
  88. struct sde_vbif_set_qos_params qos_params;
  89. if (!phys_enc || !phys_enc->parent || !phys_enc->parent->crtc) {
  90. SDE_ERROR("invalid arguments\n");
  91. return;
  92. }
  93. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  94. if (!wb_enc->crtc) {
  95. SDE_ERROR("invalid crtc");
  96. return;
  97. }
  98. crtc = wb_enc->crtc;
  99. if (!wb_enc->hw_wb || !wb_enc->hw_wb->caps) {
  100. SDE_ERROR("invalid writeback hardware\n");
  101. return;
  102. }
  103. hw_wb = wb_enc->hw_wb;
  104. memset(&qos_params, 0, sizeof(qos_params));
  105. qos_params.vbif_idx = hw_wb->caps->vbif_idx;
  106. qos_params.xin_id = hw_wb->caps->xin_id;
  107. qos_params.clk_ctrl = hw_wb->caps->clk_ctrl;
  108. qos_params.num = hw_wb->idx - WB_0;
  109. qos_params.client_type = phys_enc->in_clone_mode ?
  110. VBIF_CWB_CLIENT : VBIF_NRT_CLIENT;
  111. SDE_DEBUG("[qos_remap] wb:%d vbif:%d xin:%d clone:%d\n",
  112. qos_params.num,
  113. qos_params.vbif_idx,
  114. qos_params.xin_id, qos_params.client_type);
  115. sde_vbif_set_qos_remap(phys_enc->sde_kms, &qos_params);
  116. }
  117. /**
  118. * sde_encoder_phys_wb_set_qos - set QoS/danger/safe LUTs for writeback
  119. * @phys_enc: Pointer to physical encoder
  120. */
  121. static void sde_encoder_phys_wb_set_qos(struct sde_encoder_phys *phys_enc)
  122. {
  123. struct sde_encoder_phys_wb *wb_enc;
  124. struct sde_hw_wb *hw_wb;
  125. struct sde_hw_wb_qos_cfg qos_cfg = {0};
  126. struct sde_perf_cfg *perf;
  127. u32 fps_index = 0, lut_index, index, frame_rate, qos_count;
  128. if (!phys_enc || !phys_enc->sde_kms || !phys_enc->sde_kms->catalog) {
  129. SDE_ERROR("invalid parameter(s)\n");
  130. return;
  131. }
  132. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  133. if (!wb_enc->hw_wb) {
  134. SDE_ERROR("invalid writeback hardware\n");
  135. return;
  136. }
  137. perf = &phys_enc->sde_kms->catalog->perf;
  138. frame_rate = phys_enc->cached_mode.vrefresh;
  139. hw_wb = wb_enc->hw_wb;
  140. qos_count = perf->qos_refresh_count;
  141. while (qos_count && perf->qos_refresh_rate) {
  142. if (frame_rate >= perf->qos_refresh_rate[qos_count - 1]) {
  143. fps_index = qos_count - 1;
  144. break;
  145. }
  146. qos_count--;
  147. }
  148. qos_cfg.danger_safe_en = true;
  149. if (phys_enc->in_clone_mode)
  150. lut_index = SDE_QOS_LUT_USAGE_CWB;
  151. else
  152. lut_index = SDE_QOS_LUT_USAGE_NRT;
  153. index = (fps_index * SDE_QOS_LUT_USAGE_MAX) + lut_index;
  154. qos_cfg.danger_lut = perf->danger_lut[index];
  155. qos_cfg.safe_lut = (u32) perf->safe_lut[index];
  156. qos_cfg.creq_lut = perf->creq_lut[index];
  157. SDE_DEBUG("wb_enc:%d hw idx:%d fps:%d mode:%d luts[0x%x,0x%x 0x%llx]\n",
  158. DRMID(phys_enc->parent), hw_wb->idx - WB_0,
  159. frame_rate, phys_enc->in_clone_mode,
  160. qos_cfg.danger_lut, qos_cfg.safe_lut, qos_cfg.creq_lut);
  161. if (hw_wb->ops.setup_qos_lut)
  162. hw_wb->ops.setup_qos_lut(hw_wb, &qos_cfg);
  163. }
  164. /**
  165. * sde_encoder_phys_setup_cdm - setup chroma down block
  166. * @phys_enc: Pointer to physical encoder
  167. * @fb: Pointer to output framebuffer
  168. * @format: Output format
  169. */
  170. void sde_encoder_phys_setup_cdm(struct sde_encoder_phys *phys_enc,
  171. struct drm_framebuffer *fb, const struct sde_format *format,
  172. struct sde_rect *wb_roi)
  173. {
  174. struct sde_hw_cdm *hw_cdm;
  175. struct sde_hw_cdm_cfg *cdm_cfg;
  176. struct sde_hw_pingpong *hw_pp;
  177. int ret;
  178. if (!phys_enc || !format)
  179. return;
  180. cdm_cfg = &phys_enc->cdm_cfg;
  181. hw_pp = phys_enc->hw_pp;
  182. hw_cdm = phys_enc->hw_cdm;
  183. if (!hw_cdm)
  184. return;
  185. if (!SDE_FORMAT_IS_YUV(format)) {
  186. SDE_DEBUG("[cdm_disable fmt:%x]\n",
  187. format->base.pixel_format);
  188. if (hw_cdm && hw_cdm->ops.disable)
  189. hw_cdm->ops.disable(hw_cdm);
  190. return;
  191. }
  192. memset(cdm_cfg, 0, sizeof(struct sde_hw_cdm_cfg));
  193. if (!wb_roi)
  194. return;
  195. cdm_cfg->output_width = wb_roi->w;
  196. cdm_cfg->output_height = wb_roi->h;
  197. cdm_cfg->output_fmt = format;
  198. cdm_cfg->output_type = CDM_CDWN_OUTPUT_WB;
  199. cdm_cfg->output_bit_depth = SDE_FORMAT_IS_DX(format) ?
  200. CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT;
  201. /* enable 10 bit logic */
  202. switch (cdm_cfg->output_fmt->chroma_sample) {
  203. case SDE_CHROMA_RGB:
  204. cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
  205. cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
  206. break;
  207. case SDE_CHROMA_H2V1:
  208. cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
  209. cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
  210. break;
  211. case SDE_CHROMA_420:
  212. cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
  213. cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE;
  214. break;
  215. case SDE_CHROMA_H1V2:
  216. default:
  217. SDE_ERROR("unsupported chroma sampling type\n");
  218. cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
  219. cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
  220. break;
  221. }
  222. SDE_DEBUG("[cdm_enable:%d,%d,%X,%d,%d,%d,%d]\n",
  223. cdm_cfg->output_width,
  224. cdm_cfg->output_height,
  225. cdm_cfg->output_fmt->base.pixel_format,
  226. cdm_cfg->output_type,
  227. cdm_cfg->output_bit_depth,
  228. cdm_cfg->h_cdwn_type,
  229. cdm_cfg->v_cdwn_type);
  230. if (hw_cdm && hw_cdm->ops.setup_csc_data) {
  231. ret = hw_cdm->ops.setup_csc_data(hw_cdm,
  232. &sde_encoder_phys_wb_rgb2yuv_601l);
  233. if (ret < 0) {
  234. SDE_ERROR("failed to setup CSC %d\n", ret);
  235. return;
  236. }
  237. }
  238. if (hw_cdm && hw_cdm->ops.setup_cdwn) {
  239. ret = hw_cdm->ops.setup_cdwn(hw_cdm, cdm_cfg);
  240. if (ret < 0) {
  241. SDE_ERROR("failed to setup CDM %d\n", ret);
  242. return;
  243. }
  244. }
  245. if (hw_cdm && hw_pp && hw_cdm->ops.enable) {
  246. cdm_cfg->pp_id = hw_pp->idx;
  247. ret = hw_cdm->ops.enable(hw_cdm, cdm_cfg);
  248. if (ret < 0) {
  249. SDE_ERROR("failed to enable CDM %d\n", ret);
  250. return;
  251. }
  252. }
  253. }
  254. /**
  255. * sde_encoder_phys_wb_setup_fb - setup output framebuffer
  256. * @phys_enc: Pointer to physical encoder
  257. * @fb: Pointer to output framebuffer
  258. * @wb_roi: Pointer to output region of interest
  259. */
  260. static void sde_encoder_phys_wb_setup_fb(struct sde_encoder_phys *phys_enc,
  261. struct drm_framebuffer *fb, struct sde_rect *wb_roi)
  262. {
  263. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  264. struct sde_hw_wb *hw_wb;
  265. struct sde_hw_wb_cfg *wb_cfg;
  266. struct sde_hw_wb_cdp_cfg *cdp_cfg;
  267. const struct msm_format *format;
  268. int ret;
  269. struct msm_gem_address_space *aspace;
  270. u32 fb_mode;
  271. if (!phys_enc || !phys_enc->sde_kms || !phys_enc->sde_kms->catalog ||
  272. !phys_enc->connector) {
  273. SDE_ERROR("invalid encoder\n");
  274. return;
  275. }
  276. hw_wb = wb_enc->hw_wb;
  277. wb_cfg = &wb_enc->wb_cfg;
  278. cdp_cfg = &wb_enc->cdp_cfg;
  279. memset(wb_cfg, 0, sizeof(struct sde_hw_wb_cfg));
  280. wb_cfg->intf_mode = phys_enc->intf_mode;
  281. fb_mode = sde_connector_get_property(phys_enc->connector->state,
  282. CONNECTOR_PROP_FB_TRANSLATION_MODE);
  283. if (phys_enc->enable_state == SDE_ENC_DISABLING)
  284. wb_cfg->is_secure = false;
  285. else if (fb_mode == SDE_DRM_FB_SEC)
  286. wb_cfg->is_secure = true;
  287. else
  288. wb_cfg->is_secure = false;
  289. aspace = (wb_cfg->is_secure) ?
  290. wb_enc->aspace[SDE_IOMMU_DOMAIN_SECURE] :
  291. wb_enc->aspace[SDE_IOMMU_DOMAIN_UNSECURE];
  292. SDE_DEBUG("[fb_secure:%d]\n", wb_cfg->is_secure);
  293. ret = msm_framebuffer_prepare(fb, aspace);
  294. if (ret) {
  295. SDE_ERROR("prep fb failed, %d\n", ret);
  296. return;
  297. }
  298. /* cache framebuffer for cleanup in writeback done */
  299. wb_enc->wb_fb = fb;
  300. wb_enc->wb_aspace = aspace;
  301. drm_framebuffer_get(fb);
  302. format = msm_framebuffer_format(fb);
  303. if (!format) {
  304. SDE_DEBUG("invalid format for fb\n");
  305. return;
  306. }
  307. wb_cfg->dest.format = sde_get_sde_format_ext(
  308. format->pixel_format,
  309. fb->modifier);
  310. if (!wb_cfg->dest.format) {
  311. /* this error should be detected during atomic_check */
  312. SDE_ERROR("failed to get format %x\n", format->pixel_format);
  313. return;
  314. }
  315. wb_cfg->roi = *wb_roi;
  316. if (hw_wb->caps->features & BIT(SDE_WB_XY_ROI_OFFSET)) {
  317. ret = sde_format_populate_layout(aspace, fb, &wb_cfg->dest);
  318. if (ret) {
  319. SDE_DEBUG("failed to populate layout %d\n", ret);
  320. return;
  321. }
  322. wb_cfg->dest.width = fb->width;
  323. wb_cfg->dest.height = fb->height;
  324. wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes;
  325. } else {
  326. ret = sde_format_populate_layout_with_roi(aspace, fb, wb_roi,
  327. &wb_cfg->dest);
  328. if (ret) {
  329. /* this error should be detected during atomic_check */
  330. SDE_DEBUG("failed to populate layout %d\n", ret);
  331. return;
  332. }
  333. }
  334. if ((wb_cfg->dest.format->fetch_planes == SDE_PLANE_PLANAR) &&
  335. (wb_cfg->dest.format->element[0] == C1_B_Cb))
  336. swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);
  337. SDE_DEBUG("[fb_offset:%8.8x,%8.8x,%8.8x,%8.8x]\n",
  338. wb_cfg->dest.plane_addr[0],
  339. wb_cfg->dest.plane_addr[1],
  340. wb_cfg->dest.plane_addr[2],
  341. wb_cfg->dest.plane_addr[3]);
  342. SDE_DEBUG("[fb_stride:%8.8x,%8.8x,%8.8x,%8.8x]\n",
  343. wb_cfg->dest.plane_pitch[0],
  344. wb_cfg->dest.plane_pitch[1],
  345. wb_cfg->dest.plane_pitch[2],
  346. wb_cfg->dest.plane_pitch[3]);
  347. if (hw_wb->ops.setup_roi)
  348. hw_wb->ops.setup_roi(hw_wb, wb_cfg);
  349. if (hw_wb->ops.setup_outformat)
  350. hw_wb->ops.setup_outformat(hw_wb, wb_cfg);
  351. if (hw_wb->ops.setup_cdp) {
  352. memset(cdp_cfg, 0, sizeof(struct sde_hw_wb_cdp_cfg));
  353. cdp_cfg->enable = phys_enc->sde_kms->catalog->perf.cdp_cfg
  354. [SDE_PERF_CDP_USAGE_NRT].wr_enable;
  355. cdp_cfg->ubwc_meta_enable =
  356. SDE_FORMAT_IS_UBWC(wb_cfg->dest.format);
  357. cdp_cfg->tile_amortize_enable =
  358. SDE_FORMAT_IS_UBWC(wb_cfg->dest.format) ||
  359. SDE_FORMAT_IS_TILE(wb_cfg->dest.format);
  360. cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;
  361. hw_wb->ops.setup_cdp(hw_wb, cdp_cfg);
  362. }
  363. if (hw_wb->ops.setup_outaddress) {
  364. SDE_EVT32(hw_wb->idx,
  365. wb_cfg->dest.width,
  366. wb_cfg->dest.height,
  367. wb_cfg->dest.plane_addr[0],
  368. wb_cfg->dest.plane_size[0],
  369. wb_cfg->dest.plane_addr[1],
  370. wb_cfg->dest.plane_size[1],
  371. wb_cfg->dest.plane_addr[2],
  372. wb_cfg->dest.plane_size[2],
  373. wb_cfg->dest.plane_addr[3],
  374. wb_cfg->dest.plane_size[3]);
  375. hw_wb->ops.setup_outaddress(hw_wb, wb_cfg);
  376. }
  377. }
  378. static void _sde_encoder_phys_wb_setup_cwb(struct sde_encoder_phys *phys_enc,
  379. bool enable)
  380. {
  381. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  382. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  383. struct sde_hw_ctl *hw_ctl = phys_enc->hw_ctl;
  384. struct sde_crtc *crtc = to_sde_crtc(wb_enc->crtc);
  385. struct sde_hw_pingpong *hw_pp = phys_enc->hw_pp;
  386. bool need_merge = (crtc->num_mixers > 1);
  387. int i = 0;
  388. if (!phys_enc->in_clone_mode) {
  389. SDE_DEBUG("not in CWB mode. early return\n");
  390. return;
  391. }
  392. if (!hw_pp || !hw_ctl || !hw_wb || hw_pp->idx >= PINGPONG_MAX) {
  393. SDE_ERROR("invalid hw resources - return\n");
  394. return;
  395. }
  396. hw_ctl = crtc->mixers[0].hw_ctl;
  397. if (hw_ctl && hw_ctl->ops.setup_intf_cfg_v1 &&
  398. test_bit(SDE_WB_CWB_CTRL, &hw_wb->caps->features)) {
  399. struct sde_hw_intf_cfg_v1 intf_cfg = { 0, };
  400. for (i = 0; i < crtc->num_mixers; i++)
  401. intf_cfg.cwb[intf_cfg.cwb_count++] =
  402. (enum sde_cwb)(hw_pp->idx + i);
  403. if (hw_pp->merge_3d && (intf_cfg.merge_3d_count <
  404. MAX_MERGE_3D_PER_CTL_V1) && need_merge)
  405. intf_cfg.merge_3d[intf_cfg.merge_3d_count++] =
  406. hw_pp->merge_3d->idx;
  407. if (hw_pp->ops.setup_3d_mode)
  408. hw_pp->ops.setup_3d_mode(hw_pp, (enable && need_merge) ?
  409. BLEND_3D_H_ROW_INT : 0);
  410. if (hw_wb->ops.bind_pingpong_blk)
  411. hw_wb->ops.bind_pingpong_blk(hw_wb, enable, hw_pp->idx);
  412. if (hw_ctl->ops.update_intf_cfg) {
  413. hw_ctl->ops.update_intf_cfg(hw_ctl, &intf_cfg, enable);
  414. SDE_DEBUG("in CWB mode on CTL_%d PP-%d merge3d:%d\n",
  415. hw_ctl->idx - CTL_0,
  416. hw_pp->idx - PINGPONG_0,
  417. hw_pp->merge_3d ?
  418. hw_pp->merge_3d->idx - MERGE_3D_0 : -1);
  419. }
  420. } else {
  421. struct sde_hw_intf_cfg *intf_cfg = &phys_enc->intf_cfg;
  422. memset(intf_cfg, 0, sizeof(struct sde_hw_intf_cfg));
  423. intf_cfg->intf = SDE_NONE;
  424. intf_cfg->wb = hw_wb->idx;
  425. if (hw_ctl && hw_ctl->ops.update_wb_cfg) {
  426. hw_ctl->ops.update_wb_cfg(hw_ctl, intf_cfg, enable);
  427. SDE_DEBUG("in CWB mode adding WB for CTL_%d\n",
  428. hw_ctl->idx - CTL_0);
  429. }
  430. }
  431. }
  432. /**
  433. * sde_encoder_phys_wb_setup_cdp - setup chroma down prefetch block
  434. * @phys_enc: Pointer to physical encoder
  435. */
  436. static void sde_encoder_phys_wb_setup_cdp(struct sde_encoder_phys *phys_enc,
  437. const struct sde_format *format)
  438. {
  439. struct sde_encoder_phys_wb *wb_enc;
  440. struct sde_hw_wb *hw_wb;
  441. struct sde_hw_cdm *hw_cdm;
  442. struct sde_hw_ctl *ctl;
  443. const int num_wb = 1;
  444. if (!phys_enc) {
  445. SDE_ERROR("invalid encoder\n");
  446. return;
  447. }
  448. if (phys_enc->in_clone_mode) {
  449. SDE_DEBUG("in CWB mode. early return\n");
  450. return;
  451. }
  452. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  453. hw_wb = wb_enc->hw_wb;
  454. hw_cdm = phys_enc->hw_cdm;
  455. ctl = phys_enc->hw_ctl;
  456. if (test_bit(SDE_CTL_ACTIVE_CFG, &ctl->caps->features) &&
  457. (phys_enc->hw_ctl &&
  458. phys_enc->hw_ctl->ops.setup_intf_cfg_v1)) {
  459. struct sde_hw_intf_cfg_v1 *intf_cfg_v1 = &phys_enc->intf_cfg_v1;
  460. struct sde_hw_pingpong *hw_pp = phys_enc->hw_pp;
  461. enum sde_3d_blend_mode mode_3d;
  462. memset(intf_cfg_v1, 0, sizeof(struct sde_hw_intf_cfg_v1));
  463. mode_3d = sde_encoder_helper_get_3d_blend_mode(phys_enc);
  464. intf_cfg_v1->intf_count = SDE_NONE;
  465. intf_cfg_v1->wb_count = num_wb;
  466. intf_cfg_v1->wb[0] = hw_wb->idx;
  467. if (SDE_FORMAT_IS_YUV(format)) {
  468. intf_cfg_v1->cdm_count = num_wb;
  469. intf_cfg_v1->cdm[0] = hw_cdm->idx;
  470. }
  471. if (mode_3d && hw_pp && hw_pp->merge_3d &&
  472. intf_cfg_v1->merge_3d_count < MAX_MERGE_3D_PER_CTL_V1)
  473. intf_cfg_v1->merge_3d[intf_cfg_v1->merge_3d_count++] =
  474. hw_pp->merge_3d->idx;
  475. if (hw_pp && hw_pp->ops.setup_3d_mode)
  476. hw_pp->ops.setup_3d_mode(hw_pp, mode_3d);
  477. /* setup which pp blk will connect to this wb */
  478. if (hw_pp && hw_wb->ops.bind_pingpong_blk)
  479. hw_wb->ops.bind_pingpong_blk(hw_wb, true,
  480. hw_pp->idx);
  481. phys_enc->hw_ctl->ops.setup_intf_cfg_v1(phys_enc->hw_ctl,
  482. intf_cfg_v1);
  483. } else if (phys_enc->hw_ctl && phys_enc->hw_ctl->ops.setup_intf_cfg) {
  484. struct sde_hw_intf_cfg *intf_cfg = &phys_enc->intf_cfg;
  485. memset(intf_cfg, 0, sizeof(struct sde_hw_intf_cfg));
  486. intf_cfg->intf = SDE_NONE;
  487. intf_cfg->wb = hw_wb->idx;
  488. intf_cfg->mode_3d =
  489. sde_encoder_helper_get_3d_blend_mode(phys_enc);
  490. phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl,
  491. intf_cfg);
  492. }
  493. }
  494. static void _sde_enc_phys_wb_detect_cwb(struct sde_encoder_phys *phys_enc,
  495. struct drm_crtc_state *crtc_state)
  496. {
  497. struct drm_encoder *encoder;
  498. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  499. const struct sde_wb_cfg *wb_cfg = wb_enc->hw_wb->caps;
  500. phys_enc->in_clone_mode = false;
  501. /* Check if WB has CWB support */
  502. if (!(wb_cfg->features & BIT(SDE_WB_HAS_CWB)))
  503. return;
  504. /* if any other encoder is connected to same crtc enable clone mode*/
  505. drm_for_each_encoder(encoder, crtc_state->crtc->dev) {
  506. if (encoder->crtc != crtc_state->crtc)
  507. continue;
  508. if (phys_enc->parent != encoder) {
  509. phys_enc->in_clone_mode = true;
  510. break;
  511. }
  512. }
  513. SDE_DEBUG("detect CWB - status:%d\n", phys_enc->in_clone_mode);
  514. }
  515. static int _sde_enc_phys_wb_validate_cwb(struct sde_encoder_phys *phys_enc,
  516. struct drm_crtc_state *crtc_state,
  517. struct drm_connector_state *conn_state)
  518. {
  519. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc_state);
  520. struct sde_rect wb_roi = {0,};
  521. struct sde_rect pu_roi = {0,};
  522. int data_pt;
  523. int ds_outw = 0;
  524. int ds_outh = 0;
  525. int ds_in_use = false;
  526. int i = 0;
  527. int ret = 0;
  528. if (!phys_enc->in_clone_mode) {
  529. SDE_DEBUG("not in CWB mode. early return\n");
  530. goto exit;
  531. }
  532. ret = sde_wb_connector_state_get_output_roi(conn_state, &wb_roi);
  533. if (ret) {
  534. SDE_ERROR("failed to get roi %d\n", ret);
  535. goto exit;
  536. }
  537. data_pt = sde_crtc_get_property(cstate, CRTC_PROP_CAPTURE_OUTPUT);
  538. /* compute cumulative ds output dimensions if in use */
  539. for (i = 0; i < cstate->num_ds; i++)
  540. if (cstate->ds_cfg[i].scl3_cfg.enable) {
  541. ds_in_use = true;
  542. ds_outw += cstate->ds_cfg[i].scl3_cfg.dst_width;
  543. ds_outh = cstate->ds_cfg[i].scl3_cfg.dst_height;
  544. }
  545. /* if ds in use check wb roi against ds output dimensions */
  546. if ((data_pt == CAPTURE_DSPP_OUT) && ds_in_use &&
  547. ((wb_roi.w != ds_outw) || (wb_roi.h != ds_outh))) {
  548. SDE_ERROR("invalid wb roi with dest scalar [%dx%d vs %dx%d]\n",
  549. wb_roi.w, wb_roi.h, ds_outw, ds_outh);
  550. ret = -EINVAL;
  551. goto exit;
  552. }
  553. /* validate conn roi against pu rect */
  554. if (cstate->user_roi_list.num_rects) {
  555. sde_kms_rect_merge_rectangles(&cstate->user_roi_list, &pu_roi);
  556. if (wb_roi.w != pu_roi.w || wb_roi.h != pu_roi.h) {
  557. SDE_ERROR("invalid wb roi with pu [%dx%d vs %dx%d]\n",
  558. wb_roi.w, wb_roi.h, pu_roi.w, pu_roi.h);
  559. ret = -EINVAL;
  560. goto exit;
  561. }
  562. }
  563. exit:
  564. return ret;
  565. }
  566. /**
  567. * sde_encoder_phys_wb_atomic_check - verify and fixup given atomic states
  568. * @phys_enc: Pointer to physical encoder
  569. * @crtc_state: Pointer to CRTC atomic state
  570. * @conn_state: Pointer to connector atomic state
  571. */
  572. static int sde_encoder_phys_wb_atomic_check(
  573. struct sde_encoder_phys *phys_enc,
  574. struct drm_crtc_state *crtc_state,
  575. struct drm_connector_state *conn_state)
  576. {
  577. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  578. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  579. const struct sde_wb_cfg *wb_cfg = hw_wb->caps;
  580. struct drm_framebuffer *fb;
  581. const struct sde_format *fmt;
  582. struct sde_rect wb_roi;
  583. const struct drm_display_mode *mode = &crtc_state->mode;
  584. int rc;
  585. SDE_DEBUG("[atomic_check:%d,\"%s\",%d,%d]\n",
  586. hw_wb->idx - WB_0, mode->name,
  587. mode->hdisplay, mode->vdisplay);
  588. if (!conn_state || !conn_state->connector) {
  589. SDE_ERROR("invalid connector state\n");
  590. return -EINVAL;
  591. } else if (conn_state->connector->status !=
  592. connector_status_connected) {
  593. SDE_ERROR("connector not connected %d\n",
  594. conn_state->connector->status);
  595. return -EINVAL;
  596. }
  597. _sde_enc_phys_wb_detect_cwb(phys_enc, crtc_state);
  598. memset(&wb_roi, 0, sizeof(struct sde_rect));
  599. rc = sde_wb_connector_state_get_output_roi(conn_state, &wb_roi);
  600. if (rc) {
  601. SDE_ERROR("failed to get roi %d\n", rc);
  602. return rc;
  603. }
  604. SDE_DEBUG("[roi:%u,%u,%u,%u]\n", wb_roi.x, wb_roi.y,
  605. wb_roi.w, wb_roi.h);
  606. /* bypass check if commit with no framebuffer */
  607. fb = sde_wb_connector_state_get_output_fb(conn_state);
  608. if (!fb) {
  609. SDE_DEBUG("no output framebuffer\n");
  610. return 0;
  611. }
  612. SDE_DEBUG("[fb_id:%u][fb:%u,%u]\n", fb->base.id,
  613. fb->width, fb->height);
  614. fmt = sde_get_sde_format_ext(fb->format->format, fb->modifier);
  615. if (!fmt) {
  616. SDE_ERROR("unsupported output pixel format:%x\n",
  617. fb->format->format);
  618. return -EINVAL;
  619. }
  620. SDE_DEBUG("[fb_fmt:%x,%llx]\n", fb->format->format,
  621. fb->modifier);
  622. if (SDE_FORMAT_IS_YUV(fmt) &&
  623. !(wb_cfg->features & BIT(SDE_WB_YUV_CONFIG))) {
  624. SDE_ERROR("invalid output format %x\n", fmt->base.pixel_format);
  625. return -EINVAL;
  626. }
  627. if (SDE_FORMAT_IS_UBWC(fmt) &&
  628. !(wb_cfg->features & BIT(SDE_WB_UBWC))) {
  629. SDE_ERROR("invalid output format %x\n", fmt->base.pixel_format);
  630. return -EINVAL;
  631. }
  632. if (SDE_FORMAT_IS_YUV(fmt) != !!phys_enc->hw_cdm)
  633. crtc_state->mode_changed = true;
  634. if (wb_roi.w && wb_roi.h) {
  635. if (wb_roi.w != mode->hdisplay) {
  636. SDE_ERROR("invalid roi w=%d, mode w=%d\n", wb_roi.w,
  637. mode->hdisplay);
  638. return -EINVAL;
  639. } else if (wb_roi.h != mode->vdisplay) {
  640. SDE_ERROR("invalid roi h=%d, mode h=%d\n", wb_roi.h,
  641. mode->vdisplay);
  642. return -EINVAL;
  643. } else if (wb_roi.x + wb_roi.w > fb->width) {
  644. SDE_ERROR("invalid roi x=%d, w=%d, fb w=%d\n",
  645. wb_roi.x, wb_roi.w, fb->width);
  646. return -EINVAL;
  647. } else if (wb_roi.y + wb_roi.h > fb->height) {
  648. SDE_ERROR("invalid roi y=%d, h=%d, fb h=%d\n",
  649. wb_roi.y, wb_roi.h, fb->height);
  650. return -EINVAL;
  651. } else if (wb_roi.w > wb_cfg->sblk->maxlinewidth) {
  652. SDE_ERROR("invalid roi w=%d, maxlinewidth=%u\n",
  653. wb_roi.w, wb_cfg->sblk->maxlinewidth);
  654. return -EINVAL;
  655. }
  656. } else {
  657. if (wb_roi.x || wb_roi.y) {
  658. SDE_ERROR("invalid roi x=%d, y=%d\n",
  659. wb_roi.x, wb_roi.y);
  660. return -EINVAL;
  661. } else if (fb->width != mode->hdisplay) {
  662. SDE_ERROR("invalid fb w=%d, mode w=%d\n", fb->width,
  663. mode->hdisplay);
  664. return -EINVAL;
  665. } else if (fb->height != mode->vdisplay) {
  666. SDE_ERROR("invalid fb h=%d, mode h=%d\n", fb->height,
  667. mode->vdisplay);
  668. return -EINVAL;
  669. } else if (fb->width > wb_cfg->sblk->maxlinewidth) {
  670. SDE_ERROR("invalid fb w=%d, maxlinewidth=%u\n",
  671. fb->width, wb_cfg->sblk->maxlinewidth);
  672. return -EINVAL;
  673. }
  674. }
  675. rc = _sde_enc_phys_wb_validate_cwb(phys_enc, crtc_state, conn_state);
  676. if (rc) {
  677. SDE_ERROR("failed in cwb validation %d\n", rc);
  678. return rc;
  679. }
  680. return rc;
  681. }
  682. static void _sde_encoder_phys_wb_update_cwb_flush(
  683. struct sde_encoder_phys *phys_enc, bool enable)
  684. {
  685. struct sde_encoder_phys_wb *wb_enc;
  686. struct sde_hw_wb *hw_wb;
  687. struct sde_hw_ctl *hw_ctl;
  688. struct sde_hw_cdm *hw_cdm;
  689. struct sde_hw_pingpong *hw_pp;
  690. struct sde_crtc *crtc;
  691. struct sde_crtc_state *crtc_state;
  692. int i = 0;
  693. int cwb_capture_mode = 0;
  694. enum sde_cwb cwb_idx = 0;
  695. enum sde_cwb src_pp_idx = 0;
  696. bool dspp_out = false;
  697. bool need_merge = false;
  698. if (!phys_enc->in_clone_mode) {
  699. SDE_DEBUG("not in CWB mode. early return\n");
  700. return;
  701. }
  702. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  703. crtc = to_sde_crtc(wb_enc->crtc);
  704. crtc_state = to_sde_crtc_state(wb_enc->crtc->state);
  705. cwb_capture_mode = sde_crtc_get_property(crtc_state,
  706. CRTC_PROP_CAPTURE_OUTPUT);
  707. hw_pp = phys_enc->hw_pp;
  708. hw_wb = wb_enc->hw_wb;
  709. hw_cdm = phys_enc->hw_cdm;
  710. /* In CWB mode, program actual source master sde_hw_ctl from crtc */
  711. hw_ctl = crtc->mixers[0].hw_ctl;
  712. if (!hw_ctl || !hw_wb || !hw_pp) {
  713. SDE_ERROR("[wb] HW resource not available for CWB\n");
  714. return;
  715. }
  716. /* treating LM idx of primary display ctl path as source ping-pong idx*/
  717. src_pp_idx = (enum sde_cwb)crtc->mixers[0].hw_lm->idx;
  718. cwb_idx = (enum sde_cwb)hw_pp->idx;
  719. dspp_out = (cwb_capture_mode == CAPTURE_DSPP_OUT);
  720. need_merge = (crtc->num_mixers > 1) ? true : false;
  721. if (src_pp_idx > CWB_0 || ((cwb_idx + crtc->num_mixers) > CWB_MAX)) {
  722. SDE_ERROR("invalid hw config for CWB\n");
  723. return;
  724. }
  725. if (hw_ctl->ops.update_bitmask)
  726. hw_ctl->ops.update_bitmask(hw_ctl, SDE_HW_FLUSH_WB,
  727. hw_wb->idx, 1);
  728. if (hw_ctl->ops.update_bitmask && hw_cdm)
  729. hw_ctl->ops.update_bitmask(hw_ctl, SDE_HW_FLUSH_CDM,
  730. hw_cdm->idx, 1);
  731. if (test_bit(SDE_WB_CWB_CTRL, &hw_wb->caps->features)) {
  732. for (i = 0; i < crtc->num_mixers; i++) {
  733. cwb_idx = (enum sde_cwb) (hw_pp->idx + i);
  734. src_pp_idx = (enum sde_cwb) (src_pp_idx + i);
  735. if (hw_wb->ops.program_cwb_ctrl)
  736. hw_wb->ops.program_cwb_ctrl(hw_wb, cwb_idx,
  737. src_pp_idx, dspp_out, enable);
  738. if (hw_ctl->ops.update_bitmask)
  739. hw_ctl->ops.update_bitmask(hw_ctl,
  740. SDE_HW_FLUSH_CWB, cwb_idx, 1);
  741. }
  742. if (need_merge && hw_ctl->ops.update_bitmask
  743. && hw_pp && hw_pp->merge_3d)
  744. hw_ctl->ops.update_bitmask(hw_ctl,
  745. SDE_HW_FLUSH_MERGE_3D,
  746. hw_pp->merge_3d->idx, 1);
  747. } else {
  748. phys_enc->hw_mdptop->ops.set_cwb_ppb_cntl(phys_enc->hw_mdptop,
  749. need_merge, dspp_out);
  750. }
  751. }
  752. /**
  753. * _sde_encoder_phys_wb_update_flush - flush hardware update
  754. * @phys_enc: Pointer to physical encoder
  755. */
  756. static void _sde_encoder_phys_wb_update_flush(struct sde_encoder_phys *phys_enc)
  757. {
  758. struct sde_encoder_phys_wb *wb_enc;
  759. struct sde_hw_wb *hw_wb;
  760. struct sde_hw_ctl *hw_ctl;
  761. struct sde_hw_cdm *hw_cdm;
  762. struct sde_hw_pingpong *hw_pp;
  763. struct sde_ctl_flush_cfg pending_flush = {0,};
  764. if (!phys_enc)
  765. return;
  766. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  767. hw_wb = wb_enc->hw_wb;
  768. hw_cdm = phys_enc->hw_cdm;
  769. hw_pp = phys_enc->hw_pp;
  770. hw_ctl = phys_enc->hw_ctl;
  771. SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
  772. if (phys_enc->in_clone_mode) {
  773. SDE_DEBUG("in CWB mode. early return\n");
  774. return;
  775. }
  776. if (!hw_ctl) {
  777. SDE_DEBUG("[wb:%d] no ctl assigned\n", hw_wb->idx - WB_0);
  778. return;
  779. }
  780. if (hw_ctl->ops.update_bitmask)
  781. hw_ctl->ops.update_bitmask(hw_ctl, SDE_HW_FLUSH_WB,
  782. hw_wb->idx, 1);
  783. if (hw_ctl->ops.update_bitmask && hw_cdm)
  784. hw_ctl->ops.update_bitmask(hw_ctl, SDE_HW_FLUSH_CDM,
  785. hw_cdm->idx, 1);
  786. if (hw_ctl->ops.update_bitmask && hw_pp && hw_pp->merge_3d)
  787. hw_ctl->ops.update_bitmask(hw_ctl, SDE_HW_FLUSH_MERGE_3D,
  788. hw_pp->merge_3d->idx, 1);
  789. if (hw_ctl->ops.get_pending_flush)
  790. hw_ctl->ops.get_pending_flush(hw_ctl,
  791. &pending_flush);
  792. SDE_DEBUG("Pending flush mask for CTL_%d is 0x%x, WB %d\n",
  793. hw_ctl->idx - CTL_0, pending_flush.pending_flush_mask,
  794. hw_wb->idx - WB_0);
  795. }
  796. /**
  797. * sde_encoder_phys_wb_setup - setup writeback encoder
  798. * @phys_enc: Pointer to physical encoder
  799. */
  800. static void sde_encoder_phys_wb_setup(
  801. struct sde_encoder_phys *phys_enc)
  802. {
  803. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  804. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  805. struct drm_display_mode mode = phys_enc->cached_mode;
  806. struct drm_framebuffer *fb;
  807. struct sde_rect *wb_roi = &wb_enc->wb_roi;
  808. SDE_DEBUG("[mode_set:%d,\"%s\",%d,%d]\n",
  809. hw_wb->idx - WB_0, mode.name,
  810. mode.hdisplay, mode.vdisplay);
  811. memset(wb_roi, 0, sizeof(struct sde_rect));
  812. /* clear writeback framebuffer - will be updated in setup_fb */
  813. wb_enc->wb_fb = NULL;
  814. wb_enc->wb_aspace = NULL;
  815. if (phys_enc->enable_state == SDE_ENC_DISABLING) {
  816. fb = wb_enc->fb_disable;
  817. wb_roi->w = 0;
  818. wb_roi->h = 0;
  819. } else {
  820. fb = sde_wb_get_output_fb(wb_enc->wb_dev);
  821. sde_wb_get_output_roi(wb_enc->wb_dev, wb_roi);
  822. }
  823. if (!fb) {
  824. SDE_DEBUG("no output framebuffer\n");
  825. return;
  826. }
  827. SDE_DEBUG("[fb_id:%u][fb:%u,%u]\n", fb->base.id,
  828. fb->width, fb->height);
  829. if (wb_roi->w == 0 || wb_roi->h == 0) {
  830. wb_roi->x = 0;
  831. wb_roi->y = 0;
  832. wb_roi->w = fb->width;
  833. wb_roi->h = fb->height;
  834. }
  835. SDE_DEBUG("[roi:%u,%u,%u,%u]\n", wb_roi->x, wb_roi->y,
  836. wb_roi->w, wb_roi->h);
  837. wb_enc->wb_fmt = sde_get_sde_format_ext(fb->format->format,
  838. fb->modifier);
  839. if (!wb_enc->wb_fmt) {
  840. SDE_ERROR("unsupported output pixel format: %d\n",
  841. fb->format->format);
  842. return;
  843. }
  844. SDE_DEBUG("[fb_fmt:%x,%llx]\n", fb->format->format,
  845. fb->modifier);
  846. sde_encoder_phys_wb_set_ot_limit(phys_enc);
  847. sde_encoder_phys_wb_set_qos_remap(phys_enc);
  848. sde_encoder_phys_wb_set_qos(phys_enc);
  849. sde_encoder_phys_setup_cdm(phys_enc, fb, wb_enc->wb_fmt, wb_roi);
  850. sde_encoder_phys_wb_setup_fb(phys_enc, fb, wb_roi);
  851. sde_encoder_phys_wb_setup_cdp(phys_enc, wb_enc->wb_fmt);
  852. _sde_encoder_phys_wb_setup_cwb(phys_enc, true);
  853. }
  854. static void _sde_encoder_phys_wb_frame_done_helper(void *arg, bool frame_error)
  855. {
  856. struct sde_encoder_phys_wb *wb_enc = arg;
  857. struct sde_encoder_phys *phys_enc = &wb_enc->base;
  858. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  859. u32 event = frame_error ? SDE_ENCODER_FRAME_EVENT_ERROR : 0;
  860. SDE_DEBUG("[wb:%d,%u]\n", hw_wb->idx - WB_0, wb_enc->frame_count);
  861. /* don't notify upper layer for internal commit */
  862. if (phys_enc->enable_state == SDE_ENC_DISABLING)
  863. goto complete;
  864. if (phys_enc->parent_ops.handle_frame_done &&
  865. atomic_add_unless(&phys_enc->pending_retire_fence_cnt, -1, 0)) {
  866. event |= SDE_ENCODER_FRAME_EVENT_DONE |
  867. SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE;
  868. if (!phys_enc->in_clone_mode)
  869. event |= SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE;
  870. phys_enc->parent_ops.handle_frame_done(phys_enc->parent,
  871. phys_enc, event);
  872. }
  873. if (!phys_enc->in_clone_mode && phys_enc->parent_ops.handle_vblank_virt)
  874. phys_enc->parent_ops.handle_vblank_virt(phys_enc->parent,
  875. phys_enc);
  876. SDE_EVT32_IRQ(DRMID(phys_enc->parent), hw_wb->idx - WB_0, event,
  877. frame_error);
  878. complete:
  879. wake_up_all(&phys_enc->pending_kickoff_wq);
  880. }
  881. /**
  882. * sde_encoder_phys_wb_done_irq - Pingpong overflow interrupt handler for CWB
  883. * @arg: Pointer to writeback encoder
  884. * @irq_idx: interrupt index
  885. */
  886. static void sde_encoder_phys_cwb_ovflow(void *arg, int irq_idx)
  887. {
  888. _sde_encoder_phys_wb_frame_done_helper(arg, true);
  889. }
  890. /**
  891. * sde_encoder_phys_wb_done_irq - writeback interrupt handler
  892. * @arg: Pointer to writeback encoder
  893. * @irq_idx: interrupt index
  894. */
  895. static void sde_encoder_phys_wb_done_irq(void *arg, int irq_idx)
  896. {
  897. _sde_encoder_phys_wb_frame_done_helper(arg, false);
  898. }
  899. /**
  900. * sde_encoder_phys_wb_irq_ctrl - irq control of WB
  901. * @phys: Pointer to physical encoder
  902. * @enable: indicates enable or disable interrupts
  903. */
  904. static void sde_encoder_phys_wb_irq_ctrl(
  905. struct sde_encoder_phys *phys, bool enable)
  906. {
  907. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys);
  908. int index = 0, refcount;
  909. int ret = 0, pp = 0;
  910. if (!wb_enc)
  911. return;
  912. if (wb_enc->bypass_irqreg)
  913. return;
  914. pp = phys->hw_pp->idx - PINGPONG_0;
  915. if ((pp + CRTC_DUAL_MIXERS) >= PINGPONG_MAX) {
  916. SDE_ERROR("invalid pingpong index for WB or CWB\n");
  917. return;
  918. }
  919. refcount = atomic_read(&phys->wbirq_refcount);
  920. if (enable && atomic_inc_return(&phys->wbirq_refcount) == 1) {
  921. sde_encoder_helper_register_irq(phys, INTR_IDX_WB_DONE);
  922. if (ret)
  923. atomic_dec_return(&phys->wbirq_refcount);
  924. for (index = 0; index < CRTC_DUAL_MIXERS; index++)
  925. if (cwb_irq_tbl[index + pp] != SDE_NONE)
  926. sde_encoder_helper_register_irq(phys,
  927. cwb_irq_tbl[index + pp]);
  928. } else if (!enable &&
  929. atomic_dec_return(&phys->wbirq_refcount) == 0) {
  930. sde_encoder_helper_unregister_irq(phys, INTR_IDX_WB_DONE);
  931. if (ret)
  932. atomic_inc_return(&phys->wbirq_refcount);
  933. for (index = 0; index < CRTC_DUAL_MIXERS; index++)
  934. if (cwb_irq_tbl[index + pp] != SDE_NONE)
  935. sde_encoder_helper_unregister_irq(phys,
  936. cwb_irq_tbl[index + pp]);
  937. }
  938. }
  939. /**
  940. * sde_encoder_phys_wb_mode_set - set display mode
  941. * @phys_enc: Pointer to physical encoder
  942. * @mode: Pointer to requested display mode
  943. * @adj_mode: Pointer to adjusted display mode
  944. */
  945. static void sde_encoder_phys_wb_mode_set(
  946. struct sde_encoder_phys *phys_enc,
  947. struct drm_display_mode *mode,
  948. struct drm_display_mode *adj_mode)
  949. {
  950. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  951. struct sde_rm *rm = &phys_enc->sde_kms->rm;
  952. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  953. struct sde_rm_hw_iter iter;
  954. int i, instance;
  955. phys_enc->cached_mode = *adj_mode;
  956. instance = phys_enc->split_role == ENC_ROLE_SLAVE ? 1 : 0;
  957. SDE_DEBUG("[mode_set_cache:%d,\"%s\",%d,%d]\n",
  958. hw_wb->idx - WB_0, mode->name,
  959. mode->hdisplay, mode->vdisplay);
  960. phys_enc->hw_ctl = NULL;
  961. phys_enc->hw_cdm = NULL;
  962. /* Retrieve previously allocated HW Resources. CTL shouldn't fail */
  963. sde_rm_init_hw_iter(&iter, phys_enc->parent->base.id, SDE_HW_BLK_CTL);
  964. for (i = 0; i <= instance; i++) {
  965. sde_rm_get_hw(rm, &iter);
  966. if (i == instance)
  967. phys_enc->hw_ctl = (struct sde_hw_ctl *) iter.hw;
  968. }
  969. if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) {
  970. SDE_ERROR("failed init ctl: %ld\n",
  971. (!phys_enc->hw_ctl) ?
  972. -EINVAL : PTR_ERR(phys_enc->hw_ctl));
  973. phys_enc->hw_ctl = NULL;
  974. return;
  975. }
  976. /* CDM is optional */
  977. sde_rm_init_hw_iter(&iter, phys_enc->parent->base.id, SDE_HW_BLK_CDM);
  978. for (i = 0; i <= instance; i++) {
  979. sde_rm_get_hw(rm, &iter);
  980. if (i == instance)
  981. phys_enc->hw_cdm = (struct sde_hw_cdm *) iter.hw;
  982. }
  983. if (IS_ERR(phys_enc->hw_cdm)) {
  984. SDE_ERROR("CDM required but not allocated: %ld\n",
  985. PTR_ERR(phys_enc->hw_cdm));
  986. phys_enc->hw_cdm = NULL;
  987. }
  988. }
  989. static int sde_encoder_phys_wb_frame_timeout(struct sde_encoder_phys *phys_enc)
  990. {
  991. u32 event = 0;
  992. while (atomic_add_unless(&phys_enc->pending_retire_fence_cnt, -1, 0) &&
  993. phys_enc->parent_ops.handle_frame_done) {
  994. event = SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE
  995. | SDE_ENCODER_FRAME_EVENT_ERROR;
  996. if (!phys_enc->in_clone_mode)
  997. event |= SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE;
  998. phys_enc->parent_ops.handle_frame_done(
  999. phys_enc->parent, phys_enc, event);
  1000. SDE_EVT32(DRMID(phys_enc->parent), event,
  1001. atomic_read(&phys_enc->pending_retire_fence_cnt));
  1002. }
  1003. return event;
  1004. }
  1005. static int _sde_encoder_phys_wb_wait_for_commit_done(
  1006. struct sde_encoder_phys *phys_enc, bool is_disable)
  1007. {
  1008. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1009. u32 event = 0;
  1010. u64 wb_time = 0;
  1011. int rc = 0;
  1012. struct sde_encoder_wait_info wait_info = {0};
  1013. /* Return EWOULDBLOCK since we know the wait isn't necessary */
  1014. if (phys_enc->enable_state == SDE_ENC_DISABLED) {
  1015. SDE_ERROR("encoder already disabled\n");
  1016. return -EWOULDBLOCK;
  1017. }
  1018. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc), wb_enc->frame_count,
  1019. wb_enc->kickoff_count, !!wb_enc->wb_fb, is_disable,
  1020. phys_enc->in_clone_mode);
  1021. if (!is_disable && phys_enc->in_clone_mode &&
  1022. (atomic_read(&phys_enc->pending_retire_fence_cnt) <= 1))
  1023. goto skip_wait;
  1024. /* signal completion if commit with no framebuffer */
  1025. if (!wb_enc->wb_fb) {
  1026. SDE_DEBUG("no output framebuffer\n");
  1027. _sde_encoder_phys_wb_frame_done_helper(wb_enc, false);
  1028. }
  1029. wait_info.wq = &phys_enc->pending_kickoff_wq;
  1030. wait_info.atomic_cnt = &phys_enc->pending_retire_fence_cnt;
  1031. wait_info.timeout_ms = max_t(u32, wb_enc->wbdone_timeout,
  1032. KICKOFF_TIMEOUT_MS);
  1033. rc = sde_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_WB_DONE,
  1034. &wait_info);
  1035. if (rc == -ETIMEDOUT) {
  1036. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc),
  1037. wb_enc->frame_count, SDE_EVTLOG_ERROR);
  1038. SDE_ERROR("wb:%d kickoff timed out\n", WBID(wb_enc));
  1039. event = sde_encoder_phys_wb_frame_timeout(phys_enc);
  1040. }
  1041. /* cleanup writeback framebuffer */
  1042. if (wb_enc->wb_fb && wb_enc->wb_aspace) {
  1043. msm_framebuffer_cleanup(wb_enc->wb_fb, wb_enc->wb_aspace);
  1044. drm_framebuffer_put(wb_enc->wb_fb);
  1045. wb_enc->wb_fb = NULL;
  1046. wb_enc->wb_aspace = NULL;
  1047. }
  1048. skip_wait:
  1049. /* remove vote for iommu/clk/bus */
  1050. wb_enc->frame_count++;
  1051. if (!rc) {
  1052. wb_enc->end_time = ktime_get();
  1053. wb_time = (u64)ktime_to_us(wb_enc->end_time) -
  1054. (u64)ktime_to_us(wb_enc->start_time);
  1055. SDE_DEBUG("wb:%d took %llu us\n", WBID(wb_enc), wb_time);
  1056. }
  1057. /* cleanup previous buffer if pending */
  1058. if (wb_enc->cwb_old_fb && wb_enc->cwb_old_aspace) {
  1059. msm_framebuffer_cleanup(wb_enc->cwb_old_fb, wb_enc->cwb_old_aspace);
  1060. drm_framebuffer_put(wb_enc->cwb_old_fb);
  1061. wb_enc->cwb_old_fb = NULL;
  1062. wb_enc->cwb_old_aspace = NULL;
  1063. }
  1064. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc), wb_enc->frame_count,
  1065. wb_time, event, rc);
  1066. return rc;
  1067. }
  1068. /**
  1069. * sde_encoder_phys_wb_wait_for_commit_done - wait until request is committed
  1070. * @phys_enc: Pointer to physical encoder
  1071. */
  1072. static int sde_encoder_phys_wb_wait_for_commit_done(
  1073. struct sde_encoder_phys *phys_enc)
  1074. {
  1075. return _sde_encoder_phys_wb_wait_for_commit_done(phys_enc, false);
  1076. }
  1077. /**
  1078. * sde_encoder_phys_wb_prepare_for_kickoff - pre-kickoff processing
  1079. * @phys_enc: Pointer to physical encoder
  1080. * @params: kickoff parameters
  1081. * Returns: Zero on success
  1082. */
  1083. static int sde_encoder_phys_wb_prepare_for_kickoff(
  1084. struct sde_encoder_phys *phys_enc,
  1085. struct sde_encoder_kickoff_params *params)
  1086. {
  1087. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1088. SDE_DEBUG("[wb:%d,%u]\n", wb_enc->hw_wb->idx - WB_0,
  1089. wb_enc->kickoff_count);
  1090. if (phys_enc->in_clone_mode) {
  1091. wb_enc->cwb_old_fb = wb_enc->wb_fb;
  1092. wb_enc->cwb_old_aspace = wb_enc->wb_aspace;
  1093. }
  1094. wb_enc->kickoff_count++;
  1095. /* set OT limit & enable traffic shaper */
  1096. sde_encoder_phys_wb_setup(phys_enc);
  1097. _sde_encoder_phys_wb_update_flush(phys_enc);
  1098. _sde_encoder_phys_wb_update_cwb_flush(phys_enc, true);
  1099. /* vote for iommu/clk/bus */
  1100. wb_enc->start_time = ktime_get();
  1101. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc),
  1102. wb_enc->kickoff_count, wb_enc->frame_count,
  1103. phys_enc->in_clone_mode);
  1104. return 0;
  1105. }
  1106. /**
  1107. * sde_encoder_phys_wb_trigger_flush - trigger flush processing
  1108. * @phys_enc: Pointer to physical encoder
  1109. */
  1110. static void sde_encoder_phys_wb_trigger_flush(struct sde_encoder_phys *phys_enc)
  1111. {
  1112. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1113. if (!phys_enc || !wb_enc->hw_wb) {
  1114. SDE_ERROR("invalid encoder\n");
  1115. return;
  1116. }
  1117. /*
  1118. * Bail out iff in CWB mode. In case of CWB, primary control-path
  1119. * which is actually driving would trigger the flush
  1120. */
  1121. if (phys_enc->in_clone_mode) {
  1122. SDE_DEBUG("in CWB mode. early return\n");
  1123. return;
  1124. }
  1125. SDE_DEBUG("[wb:%d]\n", wb_enc->hw_wb->idx - WB_0);
  1126. /* clear pending flush if commit with no framebuffer */
  1127. if (!wb_enc->wb_fb) {
  1128. SDE_DEBUG("no output framebuffer\n");
  1129. return;
  1130. }
  1131. sde_encoder_helper_trigger_flush(phys_enc);
  1132. }
  1133. /**
  1134. * sde_encoder_phys_wb_handle_post_kickoff - post-kickoff processing
  1135. * @phys_enc: Pointer to physical encoder
  1136. */
  1137. static void sde_encoder_phys_wb_handle_post_kickoff(
  1138. struct sde_encoder_phys *phys_enc)
  1139. {
  1140. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1141. SDE_DEBUG("[wb:%d]\n", wb_enc->hw_wb->idx - WB_0);
  1142. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc));
  1143. }
  1144. /**
  1145. * _sde_encoder_phys_wb_init_internal_fb - create fb for internal commit
  1146. * @wb_enc: Pointer to writeback encoder
  1147. * @pixel_format: DRM pixel format
  1148. * @width: Desired fb width
  1149. * @height: Desired fb height
  1150. * @pitch: Desired fb pitch
  1151. */
  1152. static int _sde_encoder_phys_wb_init_internal_fb(
  1153. struct sde_encoder_phys_wb *wb_enc,
  1154. uint32_t pixel_format, uint32_t width,
  1155. uint32_t height, uint32_t pitch)
  1156. {
  1157. struct drm_device *dev;
  1158. struct drm_framebuffer *fb;
  1159. struct drm_mode_fb_cmd2 mode_cmd;
  1160. uint32_t size;
  1161. int nplanes, i, ret;
  1162. struct msm_gem_address_space *aspace;
  1163. const struct drm_format_info *info;
  1164. if (!wb_enc || !wb_enc->base.parent || !wb_enc->base.sde_kms) {
  1165. SDE_ERROR("invalid params\n");
  1166. return -EINVAL;
  1167. }
  1168. aspace = wb_enc->base.sde_kms->aspace[SDE_IOMMU_DOMAIN_UNSECURE];
  1169. if (!aspace) {
  1170. SDE_ERROR("invalid address space\n");
  1171. return -EINVAL;
  1172. }
  1173. dev = wb_enc->base.sde_kms->dev;
  1174. if (!dev) {
  1175. SDE_ERROR("invalid dev\n");
  1176. return -EINVAL;
  1177. }
  1178. memset(&mode_cmd, 0, sizeof(mode_cmd));
  1179. mode_cmd.pixel_format = pixel_format;
  1180. mode_cmd.width = width;
  1181. mode_cmd.height = height;
  1182. mode_cmd.pitches[0] = pitch;
  1183. size = sde_format_get_framebuffer_size(pixel_format,
  1184. mode_cmd.width, mode_cmd.height,
  1185. mode_cmd.pitches, 0);
  1186. if (!size) {
  1187. SDE_DEBUG("not creating zero size buffer\n");
  1188. return -EINVAL;
  1189. }
  1190. /* allocate gem tracking object */
  1191. info = drm_get_format_info(dev, &mode_cmd);
  1192. nplanes = info->num_planes;
  1193. if (nplanes >= SDE_MAX_PLANES) {
  1194. SDE_ERROR("requested format has too many planes\n");
  1195. return -EINVAL;
  1196. }
  1197. wb_enc->bo_disable[0] = msm_gem_new(dev, size,
  1198. MSM_BO_SCANOUT | MSM_BO_WC);
  1199. if (IS_ERR_OR_NULL(wb_enc->bo_disable[0])) {
  1200. ret = PTR_ERR(wb_enc->bo_disable[0]);
  1201. wb_enc->bo_disable[0] = NULL;
  1202. SDE_ERROR("failed to create bo, %d\n", ret);
  1203. return ret;
  1204. }
  1205. for (i = 0; i < nplanes; ++i) {
  1206. wb_enc->bo_disable[i] = wb_enc->bo_disable[0];
  1207. mode_cmd.pitches[i] = width * info->cpp[i];
  1208. }
  1209. fb = msm_framebuffer_init(dev, &mode_cmd, wb_enc->bo_disable);
  1210. if (IS_ERR_OR_NULL(fb)) {
  1211. ret = PTR_ERR(fb);
  1212. drm_gem_object_put(wb_enc->bo_disable[0]);
  1213. wb_enc->bo_disable[0] = NULL;
  1214. SDE_ERROR("failed to init fb, %d\n", ret);
  1215. return ret;
  1216. }
  1217. /* prepare the backing buffer now so that it's available later */
  1218. ret = msm_framebuffer_prepare(fb, aspace);
  1219. if (!ret)
  1220. wb_enc->fb_disable = fb;
  1221. return ret;
  1222. }
  1223. /**
  1224. * _sde_encoder_phys_wb_destroy_internal_fb - deconstruct internal fb
  1225. * @wb_enc: Pointer to writeback encoder
  1226. */
  1227. static void _sde_encoder_phys_wb_destroy_internal_fb(
  1228. struct sde_encoder_phys_wb *wb_enc)
  1229. {
  1230. if (!wb_enc)
  1231. return;
  1232. if (wb_enc->fb_disable) {
  1233. drm_framebuffer_unregister_private(wb_enc->fb_disable);
  1234. drm_framebuffer_remove(wb_enc->fb_disable);
  1235. wb_enc->fb_disable = NULL;
  1236. }
  1237. if (wb_enc->bo_disable[0]) {
  1238. drm_gem_object_put(wb_enc->bo_disable[0]);
  1239. wb_enc->bo_disable[0] = NULL;
  1240. }
  1241. }
  1242. /**
  1243. * sde_encoder_phys_wb_enable - enable writeback encoder
  1244. * @phys_enc: Pointer to physical encoder
  1245. */
  1246. static void sde_encoder_phys_wb_enable(struct sde_encoder_phys *phys_enc)
  1247. {
  1248. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1249. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  1250. struct drm_device *dev;
  1251. struct drm_connector *connector;
  1252. SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
  1253. if (!wb_enc->base.parent || !wb_enc->base.parent->dev) {
  1254. SDE_ERROR("invalid drm device\n");
  1255. return;
  1256. }
  1257. dev = wb_enc->base.parent->dev;
  1258. /* find associated writeback connector */
  1259. connector = phys_enc->connector;
  1260. if (!connector || connector->encoder != phys_enc->parent) {
  1261. SDE_ERROR("failed to find writeback connector\n");
  1262. return;
  1263. }
  1264. wb_enc->wb_dev = sde_wb_connector_get_wb(connector);
  1265. phys_enc->enable_state = SDE_ENC_ENABLED;
  1266. /*
  1267. * cache the crtc in wb_enc on enable for duration of use case
  1268. * for correctly servicing asynchronous irq events and timers
  1269. */
  1270. wb_enc->crtc = phys_enc->parent->crtc;
  1271. }
  1272. /**
  1273. * sde_encoder_phys_wb_disable - disable writeback encoder
  1274. * @phys_enc: Pointer to physical encoder
  1275. */
  1276. static void sde_encoder_phys_wb_disable(struct sde_encoder_phys *phys_enc)
  1277. {
  1278. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1279. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  1280. SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
  1281. if (phys_enc->enable_state == SDE_ENC_DISABLED) {
  1282. SDE_ERROR("encoder is already disabled\n");
  1283. return;
  1284. }
  1285. SDE_DEBUG("[wait_for_done: wb:%d, frame:%u, kickoff:%u]\n",
  1286. hw_wb->idx - WB_0, wb_enc->frame_count,
  1287. wb_enc->kickoff_count);
  1288. _sde_encoder_phys_wb_wait_for_commit_done(phys_enc, true);
  1289. if (!phys_enc->hw_ctl || !phys_enc->parent ||
  1290. !phys_enc->sde_kms || !wb_enc->fb_disable) {
  1291. SDE_DEBUG("invalid enc, skipping extra commit\n");
  1292. goto exit;
  1293. }
  1294. /* avoid reset frame for CWB */
  1295. if (phys_enc->in_clone_mode) {
  1296. _sde_encoder_phys_wb_setup_cwb(phys_enc, false);
  1297. _sde_encoder_phys_wb_update_cwb_flush(phys_enc, false);
  1298. phys_enc->in_clone_mode = false;
  1299. goto exit;
  1300. }
  1301. /* reset h/w before final flush */
  1302. if (phys_enc->hw_ctl->ops.clear_pending_flush)
  1303. phys_enc->hw_ctl->ops.clear_pending_flush(phys_enc->hw_ctl);
  1304. /*
  1305. * New CTL reset sequence from 5.0 MDP onwards.
  1306. * If has_3d_merge_reset is not set, legacy reset
  1307. * sequence is executed.
  1308. */
  1309. if (hw_wb->catalog->has_3d_merge_reset) {
  1310. sde_encoder_helper_phys_disable(phys_enc, wb_enc);
  1311. goto exit;
  1312. }
  1313. if (sde_encoder_helper_reset_mixers(phys_enc, NULL))
  1314. goto exit;
  1315. phys_enc->enable_state = SDE_ENC_DISABLING;
  1316. sde_encoder_phys_wb_prepare_for_kickoff(phys_enc, NULL);
  1317. sde_encoder_phys_wb_irq_ctrl(phys_enc, true);
  1318. if (phys_enc->hw_ctl->ops.trigger_flush)
  1319. phys_enc->hw_ctl->ops.trigger_flush(phys_enc->hw_ctl);
  1320. sde_encoder_helper_trigger_start(phys_enc);
  1321. _sde_encoder_phys_wb_wait_for_commit_done(phys_enc, true);
  1322. sde_encoder_phys_wb_irq_ctrl(phys_enc, false);
  1323. exit:
  1324. /*
  1325. * frame count and kickoff count are only used for debug purpose. Frame
  1326. * count can be more than kickoff count at the end of disable call due
  1327. * to extra frame_done wait. It does not cause any issue because
  1328. * frame_done wait is based on retire_fence count. Leaving these
  1329. * counters for debugging purpose.
  1330. */
  1331. if (wb_enc->frame_count != wb_enc->kickoff_count) {
  1332. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc),
  1333. wb_enc->kickoff_count, wb_enc->frame_count,
  1334. phys_enc->in_clone_mode);
  1335. wb_enc->frame_count = wb_enc->kickoff_count;
  1336. }
  1337. phys_enc->enable_state = SDE_ENC_DISABLED;
  1338. wb_enc->crtc = NULL;
  1339. }
  1340. /**
  1341. * sde_encoder_phys_wb_get_hw_resources - get hardware resources
  1342. * @phys_enc: Pointer to physical encoder
  1343. * @hw_res: Pointer to encoder resources
  1344. */
  1345. static void sde_encoder_phys_wb_get_hw_resources(
  1346. struct sde_encoder_phys *phys_enc,
  1347. struct sde_encoder_hw_resources *hw_res,
  1348. struct drm_connector_state *conn_state)
  1349. {
  1350. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1351. struct sde_hw_wb *hw_wb;
  1352. struct drm_framebuffer *fb;
  1353. const struct sde_format *fmt = NULL;
  1354. if (!phys_enc) {
  1355. SDE_ERROR("invalid encoder\n");
  1356. return;
  1357. }
  1358. fb = sde_wb_connector_state_get_output_fb(conn_state);
  1359. if (fb) {
  1360. fmt = sde_get_sde_format_ext(fb->format->format, fb->modifier);
  1361. if (!fmt) {
  1362. SDE_ERROR("unsupported output pixel format:%d\n",
  1363. fb->format->format);
  1364. return;
  1365. }
  1366. }
  1367. hw_wb = wb_enc->hw_wb;
  1368. hw_res->wbs[hw_wb->idx - WB_0] = phys_enc->intf_mode;
  1369. hw_res->needs_cdm = fmt ? SDE_FORMAT_IS_YUV(fmt) : false;
  1370. SDE_DEBUG("[wb:%d] intf_mode=%d needs_cdm=%d\n", hw_wb->idx - WB_0,
  1371. hw_res->wbs[hw_wb->idx - WB_0],
  1372. hw_res->needs_cdm);
  1373. }
  1374. #ifdef CONFIG_DEBUG_FS
  1375. /**
  1376. * sde_encoder_phys_wb_init_debugfs - initialize writeback encoder debugfs
  1377. * @phys_enc: Pointer to physical encoder
  1378. * @debugfs_root: Pointer to virtual encoder's debugfs_root dir
  1379. */
  1380. static int sde_encoder_phys_wb_init_debugfs(
  1381. struct sde_encoder_phys *phys_enc, struct dentry *debugfs_root)
  1382. {
  1383. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1384. if (!phys_enc || !wb_enc->hw_wb || !debugfs_root)
  1385. return -EINVAL;
  1386. if (!debugfs_create_u32("wbdone_timeout", 0600,
  1387. debugfs_root, &wb_enc->wbdone_timeout)) {
  1388. SDE_ERROR("failed to create debugfs/wbdone_timeout\n");
  1389. return -ENOMEM;
  1390. }
  1391. return 0;
  1392. }
  1393. #else
  1394. static int sde_encoder_phys_wb_init_debugfs(
  1395. struct sde_encoder_phys *phys_enc, struct dentry *debugfs_root)
  1396. {
  1397. return 0;
  1398. }
  1399. #endif
  1400. static int sde_encoder_phys_wb_late_register(struct sde_encoder_phys *phys_enc,
  1401. struct dentry *debugfs_root)
  1402. {
  1403. return sde_encoder_phys_wb_init_debugfs(phys_enc, debugfs_root);
  1404. }
  1405. /**
  1406. * sde_encoder_phys_wb_destroy - destroy writeback encoder
  1407. * @phys_enc: Pointer to physical encoder
  1408. */
  1409. static void sde_encoder_phys_wb_destroy(struct sde_encoder_phys *phys_enc)
  1410. {
  1411. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1412. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  1413. SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
  1414. if (!phys_enc)
  1415. return;
  1416. _sde_encoder_phys_wb_destroy_internal_fb(wb_enc);
  1417. kfree(wb_enc);
  1418. }
  1419. /**
  1420. * sde_encoder_phys_wb_init_ops - initialize writeback operations
  1421. * @ops: Pointer to encoder operation table
  1422. */
  1423. static void sde_encoder_phys_wb_init_ops(struct sde_encoder_phys_ops *ops)
  1424. {
  1425. ops->late_register = sde_encoder_phys_wb_late_register;
  1426. ops->is_master = sde_encoder_phys_wb_is_master;
  1427. ops->mode_set = sde_encoder_phys_wb_mode_set;
  1428. ops->enable = sde_encoder_phys_wb_enable;
  1429. ops->disable = sde_encoder_phys_wb_disable;
  1430. ops->destroy = sde_encoder_phys_wb_destroy;
  1431. ops->atomic_check = sde_encoder_phys_wb_atomic_check;
  1432. ops->get_hw_resources = sde_encoder_phys_wb_get_hw_resources;
  1433. ops->wait_for_commit_done = sde_encoder_phys_wb_wait_for_commit_done;
  1434. ops->prepare_for_kickoff = sde_encoder_phys_wb_prepare_for_kickoff;
  1435. ops->handle_post_kickoff = sde_encoder_phys_wb_handle_post_kickoff;
  1436. ops->trigger_flush = sde_encoder_phys_wb_trigger_flush;
  1437. ops->trigger_start = sde_encoder_helper_trigger_start;
  1438. ops->hw_reset = sde_encoder_helper_hw_reset;
  1439. ops->irq_control = sde_encoder_phys_wb_irq_ctrl;
  1440. }
  1441. /**
  1442. * sde_encoder_phys_wb_init - initialize writeback encoder
  1443. * @init: Pointer to init info structure with initialization params
  1444. */
  1445. struct sde_encoder_phys *sde_encoder_phys_wb_init(
  1446. struct sde_enc_phys_init_params *p)
  1447. {
  1448. struct sde_encoder_phys *phys_enc;
  1449. struct sde_encoder_phys_wb *wb_enc;
  1450. struct sde_hw_mdp *hw_mdp;
  1451. struct sde_encoder_irq *irq;
  1452. int ret = 0;
  1453. SDE_DEBUG("\n");
  1454. if (!p || !p->parent) {
  1455. SDE_ERROR("invalid params\n");
  1456. ret = -EINVAL;
  1457. goto fail_alloc;
  1458. }
  1459. wb_enc = kzalloc(sizeof(*wb_enc), GFP_KERNEL);
  1460. if (!wb_enc) {
  1461. SDE_ERROR("failed to allocate wb enc\n");
  1462. ret = -ENOMEM;
  1463. goto fail_alloc;
  1464. }
  1465. wb_enc->wbdone_timeout = KICKOFF_TIMEOUT_MS;
  1466. phys_enc = &wb_enc->base;
  1467. if (p->sde_kms->vbif[VBIF_NRT]) {
  1468. wb_enc->aspace[SDE_IOMMU_DOMAIN_UNSECURE] =
  1469. p->sde_kms->aspace[MSM_SMMU_DOMAIN_NRT_UNSECURE];
  1470. wb_enc->aspace[SDE_IOMMU_DOMAIN_SECURE] =
  1471. p->sde_kms->aspace[MSM_SMMU_DOMAIN_NRT_SECURE];
  1472. } else {
  1473. wb_enc->aspace[SDE_IOMMU_DOMAIN_UNSECURE] =
  1474. p->sde_kms->aspace[MSM_SMMU_DOMAIN_UNSECURE];
  1475. wb_enc->aspace[SDE_IOMMU_DOMAIN_SECURE] =
  1476. p->sde_kms->aspace[MSM_SMMU_DOMAIN_SECURE];
  1477. }
  1478. hw_mdp = sde_rm_get_mdp(&p->sde_kms->rm);
  1479. if (IS_ERR_OR_NULL(hw_mdp)) {
  1480. ret = PTR_ERR(hw_mdp);
  1481. SDE_ERROR("failed to init hw_top: %d\n", ret);
  1482. goto fail_mdp_init;
  1483. }
  1484. phys_enc->hw_mdptop = hw_mdp;
  1485. /**
  1486. * hw_wb resource permanently assigned to this encoder
  1487. * Other resources allocated at atomic commit time by use case
  1488. */
  1489. if (p->wb_idx != SDE_NONE) {
  1490. struct sde_rm_hw_iter iter;
  1491. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_WB);
  1492. while (sde_rm_get_hw(&p->sde_kms->rm, &iter)) {
  1493. struct sde_hw_wb *hw_wb = (struct sde_hw_wb *)iter.hw;
  1494. if (hw_wb->idx == p->wb_idx) {
  1495. wb_enc->hw_wb = hw_wb;
  1496. break;
  1497. }
  1498. }
  1499. if (!wb_enc->hw_wb) {
  1500. ret = -EINVAL;
  1501. SDE_ERROR("failed to init hw_wb%d\n", p->wb_idx - WB_0);
  1502. goto fail_wb_init;
  1503. }
  1504. } else {
  1505. ret = -EINVAL;
  1506. SDE_ERROR("invalid wb_idx\n");
  1507. goto fail_wb_check;
  1508. }
  1509. sde_encoder_phys_wb_init_ops(&phys_enc->ops);
  1510. phys_enc->parent = p->parent;
  1511. phys_enc->parent_ops = p->parent_ops;
  1512. phys_enc->sde_kms = p->sde_kms;
  1513. phys_enc->split_role = p->split_role;
  1514. phys_enc->intf_mode = INTF_MODE_WB_LINE;
  1515. phys_enc->intf_idx = p->intf_idx;
  1516. phys_enc->enc_spinlock = p->enc_spinlock;
  1517. phys_enc->vblank_ctl_lock = p->vblank_ctl_lock;
  1518. atomic_set(&phys_enc->pending_retire_fence_cnt, 0);
  1519. atomic_set(&phys_enc->wbirq_refcount, 0);
  1520. init_waitqueue_head(&phys_enc->pending_kickoff_wq);
  1521. irq = &phys_enc->irq[INTR_IDX_WB_DONE];
  1522. INIT_LIST_HEAD(&irq->cb.list);
  1523. irq->name = "wb_done";
  1524. irq->hw_idx = wb_enc->hw_wb->idx;
  1525. irq->irq_idx = -1;
  1526. irq->intr_type = sde_encoder_phys_wb_get_intr_type(wb_enc->hw_wb);
  1527. irq->intr_idx = INTR_IDX_WB_DONE;
  1528. irq->cb.arg = wb_enc;
  1529. irq->cb.func = sde_encoder_phys_wb_done_irq;
  1530. irq = &phys_enc->irq[INTR_IDX_PP1_OVFL];
  1531. INIT_LIST_HEAD(&irq->cb.list);
  1532. irq->name = "pp1_overflow";
  1533. irq->hw_idx = CWB_1;
  1534. irq->irq_idx = -1;
  1535. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1536. irq->intr_idx = INTR_IDX_PP1_OVFL;
  1537. irq->cb.arg = wb_enc;
  1538. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1539. irq = &phys_enc->irq[INTR_IDX_PP2_OVFL];
  1540. INIT_LIST_HEAD(&irq->cb.list);
  1541. irq->name = "pp2_overflow";
  1542. irq->hw_idx = CWB_2;
  1543. irq->irq_idx = -1;
  1544. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1545. irq->intr_idx = INTR_IDX_PP2_OVFL;
  1546. irq->cb.arg = wb_enc;
  1547. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1548. irq = &phys_enc->irq[INTR_IDX_PP3_OVFL];
  1549. INIT_LIST_HEAD(&irq->cb.list);
  1550. irq->name = "pp3_overflow";
  1551. irq->hw_idx = CWB_3;
  1552. irq->irq_idx = -1;
  1553. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1554. irq->intr_idx = INTR_IDX_PP3_OVFL;
  1555. irq->cb.arg = wb_enc;
  1556. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1557. irq = &phys_enc->irq[INTR_IDX_PP4_OVFL];
  1558. INIT_LIST_HEAD(&irq->cb.list);
  1559. irq->name = "pp4_overflow";
  1560. irq->hw_idx = CWB_4;
  1561. irq->irq_idx = -1;
  1562. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1563. irq->intr_idx = INTR_IDX_PP4_OVFL;
  1564. irq->cb.arg = wb_enc;
  1565. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1566. irq = &phys_enc->irq[INTR_IDX_PP5_OVFL];
  1567. INIT_LIST_HEAD(&irq->cb.list);
  1568. irq->name = "pp5_overflow";
  1569. irq->hw_idx = CWB_5;
  1570. irq->irq_idx = -1;
  1571. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1572. irq->intr_idx = INTR_IDX_PP5_OVFL;
  1573. irq->cb.arg = wb_enc;
  1574. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1575. /* create internal buffer for disable logic */
  1576. if (_sde_encoder_phys_wb_init_internal_fb(wb_enc,
  1577. DRM_FORMAT_RGB888, 2, 1, 6)) {
  1578. SDE_ERROR("failed to init internal fb\n");
  1579. goto fail_wb_init;
  1580. }
  1581. SDE_DEBUG("Created sde_encoder_phys_wb for wb %d\n",
  1582. wb_enc->hw_wb->idx - WB_0);
  1583. return phys_enc;
  1584. fail_wb_init:
  1585. fail_wb_check:
  1586. fail_mdp_init:
  1587. kfree(wb_enc);
  1588. fail_alloc:
  1589. return ERR_PTR(ret);
  1590. }