wcd938x.c 135 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "wcd938x-registers.h"
  23. #include "wcd938x.h"
  24. #include "internal.h"
  25. #include "asoc/bolero-slave-internal.h"
  26. #define NUM_SWRS_DT_PARAMS 5
  27. #define WCD938X_VARIANT_ENTRY_SIZE 32
  28. #define WCD938X_VERSION_1_0 1
  29. #define WCD938X_VERSION_ENTRY_SIZE 32
  30. #define EAR_RX_PATH_AUX 1
  31. #define ADC_MODE_VAL_HIFI 0x01
  32. #define ADC_MODE_VAL_LO_HIF 0x02
  33. #define ADC_MODE_VAL_NORMAL 0x03
  34. #define ADC_MODE_VAL_LP 0x05
  35. #define ADC_MODE_VAL_ULP1 0x09
  36. #define ADC_MODE_VAL_ULP2 0x0B
  37. #define NUM_ATTEMPTS 5
  38. #define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
  39. #define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone"
  40. #define DAPM_MICBIAS3_STANDALONE "MIC BIAS3 Standalone"
  41. #define DAPM_MICBIAS4_STANDALONE "MIC BIAS4 Standalone"
  42. #define WCD938X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  43. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  44. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  45. SNDRV_PCM_RATE_384000)
  46. /* Fractional Rates */
  47. #define WCD938X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  48. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  49. #define WCD938X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  50. SNDRV_PCM_FMTBIT_S24_LE |\
  51. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  52. enum {
  53. CODEC_TX = 0,
  54. CODEC_RX,
  55. };
  56. enum {
  57. WCD_ADC1 = 0,
  58. WCD_ADC2,
  59. WCD_ADC3,
  60. WCD_ADC4,
  61. ALLOW_BUCK_DISABLE,
  62. HPH_COMP_DELAY,
  63. HPH_PA_DELAY,
  64. AMIC2_BCS_ENABLE,
  65. WCD_SUPPLIES_LPM_MODE,
  66. WCD_ADC1_MODE,
  67. WCD_ADC2_MODE,
  68. WCD_ADC3_MODE,
  69. WCD_ADC4_MODE,
  70. };
  71. enum {
  72. ADC_MODE_INVALID = 0,
  73. ADC_MODE_HIFI,
  74. ADC_MODE_LO_HIF,
  75. ADC_MODE_NORMAL,
  76. ADC_MODE_LP,
  77. ADC_MODE_ULP1,
  78. ADC_MODE_ULP2,
  79. };
  80. static u8 tx_mode_bit[] = {
  81. [ADC_MODE_INVALID] = 0x00,
  82. [ADC_MODE_HIFI] = 0x01,
  83. [ADC_MODE_LO_HIF] = 0x02,
  84. [ADC_MODE_NORMAL] = 0x04,
  85. [ADC_MODE_LP] = 0x08,
  86. [ADC_MODE_ULP1] = 0x10,
  87. [ADC_MODE_ULP2] = 0x20,
  88. };
  89. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  90. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  91. static int wcd938x_handle_post_irq(void *data);
  92. static int wcd938x_reset(struct device *dev);
  93. static int wcd938x_reset_low(struct device *dev);
  94. static int wcd938x_get_adc_mode(int val);
  95. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  96. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  97. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  98. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  99. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  100. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  101. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  102. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  103. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  104. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  105. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  106. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  107. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  108. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  109. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  110. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  111. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  112. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  113. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  114. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  115. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  116. };
  117. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  118. .name = "wcd938x",
  119. .irqs = wcd938x_irqs,
  120. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  121. .num_regs = 3,
  122. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  123. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  124. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  125. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  126. .use_ack = 1,
  127. .runtime_pm = false,
  128. .handle_post_irq = wcd938x_handle_post_irq,
  129. .irq_drv_data = NULL,
  130. };
  131. static int wcd938x_handle_post_irq(void *data)
  132. {
  133. struct wcd938x_priv *wcd938x = data;
  134. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  135. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  136. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  137. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  138. wcd938x->tx_swr_dev->slave_irq_pending =
  139. ((sts1 || sts2 || sts3) ? true : false);
  140. return IRQ_HANDLED;
  141. }
  142. static int wcd938x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  143. {
  144. int ret = 0;
  145. int bank = 0;
  146. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  147. if (ret)
  148. return -EINVAL;
  149. return ((bank & 0x40) ? 1: 0);
  150. }
  151. static int wcd938x_get_clk_rate(int mode)
  152. {
  153. int rate;
  154. switch (mode) {
  155. case ADC_MODE_ULP2:
  156. rate = SWR_CLK_RATE_0P6MHZ;
  157. break;
  158. case ADC_MODE_ULP1:
  159. rate = SWR_CLK_RATE_1P2MHZ;
  160. break;
  161. case ADC_MODE_LP:
  162. rate = SWR_CLK_RATE_4P8MHZ;
  163. break;
  164. case ADC_MODE_NORMAL:
  165. case ADC_MODE_LO_HIF:
  166. case ADC_MODE_HIFI:
  167. case ADC_MODE_INVALID:
  168. default:
  169. rate = SWR_CLK_RATE_9P6MHZ;
  170. break;
  171. }
  172. return rate;
  173. }
  174. static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component,
  175. int rate, int bank)
  176. {
  177. u8 mask = (bank ? 0xF0 : 0x0F);
  178. u8 val = 0;
  179. switch (rate) {
  180. case SWR_CLK_RATE_0P6MHZ:
  181. val = (bank ? 0x60 : 0x06);
  182. break;
  183. case SWR_CLK_RATE_1P2MHZ:
  184. val = (bank ? 0x50 : 0x05);
  185. break;
  186. case SWR_CLK_RATE_2P4MHZ:
  187. val = (bank ? 0x30 : 0x03);
  188. break;
  189. case SWR_CLK_RATE_4P8MHZ:
  190. val = (bank ? 0x10 : 0x01);
  191. break;
  192. case SWR_CLK_RATE_9P6MHZ:
  193. default:
  194. val = 0x00;
  195. break;
  196. }
  197. snd_soc_component_update_bits(component,
  198. WCD938X_DIGITAL_SWR_TX_CLK_RATE,
  199. mask, val);
  200. return 0;
  201. }
  202. static int wcd938x_init_reg(struct snd_soc_component *component)
  203. {
  204. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  205. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  206. /* 1 msec delay as per HW requirement */
  207. usleep_range(1000, 1010);
  208. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  209. /* 1 msec delay as per HW requirement */
  210. usleep_range(1000, 1010);
  211. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  212. 0x10, 0x00);
  213. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  214. 0xF0, 0x80);
  215. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  216. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  217. /* 10 msec delay as per HW requirement */
  218. usleep_range(10000, 10010);
  219. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  220. snd_soc_component_update_bits(component,
  221. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  222. 0xF0, 0x00);
  223. snd_soc_component_update_bits(component,
  224. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  225. 0x1F, 0x15);
  226. snd_soc_component_update_bits(component,
  227. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  228. 0x1F, 0x15);
  229. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  230. 0xC0, 0x80);
  231. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  232. 0x02, 0x02);
  233. snd_soc_component_update_bits(component,
  234. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  235. 0xFF, 0x14);
  236. snd_soc_component_update_bits(component,
  237. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  238. 0x1F, 0x08);
  239. snd_soc_component_update_bits(component,
  240. WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
  241. snd_soc_component_update_bits(component,
  242. WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
  243. snd_soc_component_update_bits(component,
  244. WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
  245. snd_soc_component_update_bits(component,
  246. WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
  247. snd_soc_component_update_bits(component,
  248. WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
  249. snd_soc_component_update_bits(component,
  250. WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
  251. snd_soc_component_update_bits(component,
  252. WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
  253. snd_soc_component_update_bits(component,
  254. WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
  255. snd_soc_component_update_bits(component,
  256. WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
  257. snd_soc_component_update_bits(component,
  258. WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
  259. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E,
  260. ((snd_soc_component_read(component,
  261. WCD938X_DIGITAL_EFUSE_REG_30) & 0x07) << 1));
  262. snd_soc_component_update_bits(component,
  263. WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
  264. return 0;
  265. }
  266. static int wcd938x_set_port_params(struct snd_soc_component *component,
  267. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  268. u8 *ch_mask, u32 *ch_rate,
  269. u8 *port_type, u8 path)
  270. {
  271. int i, j;
  272. u8 num_ports = 0;
  273. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  274. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  275. switch (path) {
  276. case CODEC_RX:
  277. map = &wcd938x->rx_port_mapping;
  278. num_ports = wcd938x->num_rx_ports;
  279. break;
  280. case CODEC_TX:
  281. map = &wcd938x->tx_port_mapping;
  282. num_ports = wcd938x->num_tx_ports;
  283. break;
  284. default:
  285. dev_err(component->dev, "%s Invalid path selected %u\n",
  286. __func__, path);
  287. return -EINVAL;
  288. }
  289. for (i = 0; i <= num_ports; i++) {
  290. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  291. if ((*map)[i][j].slave_port_type == slv_prt_type)
  292. goto found;
  293. }
  294. }
  295. found:
  296. if (i > num_ports || j == MAX_CH_PER_PORT) {
  297. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  298. __func__, slv_prt_type);
  299. return -EINVAL;
  300. }
  301. *port_id = i;
  302. *num_ch = (*map)[i][j].num_ch;
  303. *ch_mask = (*map)[i][j].ch_mask;
  304. *ch_rate = (*map)[i][j].ch_rate;
  305. *port_type = (*map)[i][j].master_port_type;
  306. return 0;
  307. }
  308. /* qcom,swr-tx-port-params = <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,*UC0*
  309. <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, *UC1*
  310. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC2*
  311. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC3 */
  312. static int wcd938x_parse_port_params(struct device *dev,
  313. char *prop, u8 path)
  314. {
  315. u32 *dt_array, map_size, max_uc;
  316. int ret = 0;
  317. u32 cnt = 0;
  318. u32 i, j;
  319. struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  320. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  321. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  322. switch (path) {
  323. case CODEC_TX:
  324. map = &wcd938x->tx_port_params;
  325. map_uc = &wcd938x->swr_tx_port_params;
  326. break;
  327. default:
  328. ret = -EINVAL;
  329. goto err_port_map;
  330. }
  331. if (!of_find_property(dev->of_node, prop,
  332. &map_size)) {
  333. dev_err(dev, "missing port mapping prop %s\n", prop);
  334. ret = -EINVAL;
  335. goto err_port_map;
  336. }
  337. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  338. if (max_uc != SWR_UC_MAX) {
  339. dev_err(dev, "%s: port params not provided for all usecases\n",
  340. __func__);
  341. ret = -EINVAL;
  342. goto err_port_map;
  343. }
  344. dt_array = kzalloc(map_size, GFP_KERNEL);
  345. if (!dt_array) {
  346. ret = -ENOMEM;
  347. goto err_alloc;
  348. }
  349. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  350. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  351. if (ret) {
  352. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  353. __func__, prop);
  354. goto err_pdata_fail;
  355. }
  356. for (i = 0; i < max_uc; i++) {
  357. for (j = 0; j < SWR_NUM_PORTS; j++) {
  358. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  359. (*map)[i][j].offset1 = dt_array[cnt];
  360. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  361. }
  362. (*map_uc)[i].pp = &(*map)[i][0];
  363. }
  364. kfree(dt_array);
  365. return 0;
  366. err_pdata_fail:
  367. kfree(dt_array);
  368. err_alloc:
  369. err_port_map:
  370. return ret;
  371. }
  372. static int wcd938x_parse_port_mapping(struct device *dev,
  373. char *prop, u8 path)
  374. {
  375. u32 *dt_array, map_size, map_length;
  376. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  377. u32 slave_port_type, master_port_type;
  378. u32 i, ch_iter = 0;
  379. int ret = 0;
  380. u8 *num_ports = NULL;
  381. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  382. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  383. switch (path) {
  384. case CODEC_RX:
  385. map = &wcd938x->rx_port_mapping;
  386. num_ports = &wcd938x->num_rx_ports;
  387. break;
  388. case CODEC_TX:
  389. map = &wcd938x->tx_port_mapping;
  390. num_ports = &wcd938x->num_tx_ports;
  391. break;
  392. default:
  393. dev_err(dev, "%s Invalid path selected %u\n",
  394. __func__, path);
  395. return -EINVAL;
  396. }
  397. if (!of_find_property(dev->of_node, prop,
  398. &map_size)) {
  399. dev_err(dev, "missing port mapping prop %s\n", prop);
  400. ret = -EINVAL;
  401. goto err_port_map;
  402. }
  403. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  404. dt_array = kzalloc(map_size, GFP_KERNEL);
  405. if (!dt_array) {
  406. ret = -ENOMEM;
  407. goto err_alloc;
  408. }
  409. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  410. NUM_SWRS_DT_PARAMS * map_length);
  411. if (ret) {
  412. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  413. __func__, prop);
  414. goto err_pdata_fail;
  415. }
  416. for (i = 0; i < map_length; i++) {
  417. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  418. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  419. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  420. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  421. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  422. if (port_num != old_port_num)
  423. ch_iter = 0;
  424. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  425. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  426. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  427. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  428. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  429. old_port_num = port_num;
  430. }
  431. *num_ports = port_num;
  432. kfree(dt_array);
  433. return 0;
  434. err_pdata_fail:
  435. kfree(dt_array);
  436. err_alloc:
  437. err_port_map:
  438. return ret;
  439. }
  440. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  441. u8 slv_port_type, int clk_rate,
  442. u8 enable)
  443. {
  444. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  445. u8 port_id, num_ch, ch_mask;
  446. u8 ch_type = 0;
  447. u32 ch_rate;
  448. int slave_ch_idx;
  449. u8 num_port = 1;
  450. int ret = 0;
  451. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  452. &num_ch, &ch_mask, &ch_rate,
  453. &ch_type, CODEC_TX);
  454. if (ret)
  455. return ret;
  456. if (clk_rate)
  457. ch_rate = clk_rate;
  458. slave_ch_idx = wcd938x_slave_get_slave_ch_val(slv_port_type);
  459. if (slave_ch_idx != -EINVAL)
  460. ch_type = wcd938x->tx_master_ch_map[slave_ch_idx];
  461. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  462. __func__, slave_ch_idx, ch_type);
  463. if (enable)
  464. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  465. num_port, &ch_mask, &ch_rate,
  466. &num_ch, &ch_type);
  467. else
  468. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  469. num_port, &ch_mask, &ch_type);
  470. return ret;
  471. }
  472. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  473. u8 slv_port_type, u8 enable)
  474. {
  475. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  476. u8 port_id, num_ch, ch_mask, port_type;
  477. u32 ch_rate;
  478. u8 num_port = 1;
  479. int ret = 0;
  480. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  481. &num_ch, &ch_mask, &ch_rate,
  482. &port_type, CODEC_RX);
  483. if (ret)
  484. return ret;
  485. if (enable)
  486. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  487. num_port, &ch_mask, &ch_rate,
  488. &num_ch, &port_type);
  489. else
  490. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  491. num_port, &ch_mask, &port_type);
  492. return ret;
  493. }
  494. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  495. {
  496. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  497. if (wcd938x->rx_clk_cnt == 0) {
  498. snd_soc_component_update_bits(component,
  499. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  500. snd_soc_component_update_bits(component,
  501. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  502. snd_soc_component_update_bits(component,
  503. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  504. snd_soc_component_update_bits(component,
  505. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  506. snd_soc_component_update_bits(component,
  507. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  508. snd_soc_component_update_bits(component,
  509. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  510. snd_soc_component_update_bits(component,
  511. WCD938X_AUX_AUXPA, 0x10, 0x10);
  512. }
  513. wcd938x->rx_clk_cnt++;
  514. return 0;
  515. }
  516. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  517. {
  518. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  519. wcd938x->rx_clk_cnt--;
  520. if (wcd938x->rx_clk_cnt == 0) {
  521. snd_soc_component_update_bits(component,
  522. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  523. snd_soc_component_update_bits(component,
  524. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  525. snd_soc_component_update_bits(component,
  526. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  527. snd_soc_component_update_bits(component,
  528. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  529. snd_soc_component_update_bits(component,
  530. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  531. }
  532. return 0;
  533. }
  534. /*
  535. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  536. * @component: handle to snd_soc_component *
  537. *
  538. * return wcd938x_mbhc handle or error code in case of failure
  539. */
  540. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  541. {
  542. struct wcd938x_priv *wcd938x;
  543. if (!component) {
  544. pr_err("%s: Invalid params, NULL component\n", __func__);
  545. return NULL;
  546. }
  547. wcd938x = snd_soc_component_get_drvdata(component);
  548. if (!wcd938x) {
  549. pr_err("%s: wcd938x is NULL\n", __func__);
  550. return NULL;
  551. }
  552. return wcd938x->mbhc;
  553. }
  554. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  555. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  556. struct snd_kcontrol *kcontrol,
  557. int event)
  558. {
  559. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  560. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  561. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  562. w->name, event);
  563. switch (event) {
  564. case SND_SOC_DAPM_PRE_PMU:
  565. wcd938x_rx_clk_enable(component);
  566. snd_soc_component_update_bits(component,
  567. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  568. snd_soc_component_update_bits(component,
  569. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  570. snd_soc_component_update_bits(component,
  571. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  572. break;
  573. case SND_SOC_DAPM_POST_PMU:
  574. snd_soc_component_update_bits(component,
  575. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  576. if (wcd938x->comp1_enable) {
  577. snd_soc_component_update_bits(component,
  578. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  579. /* 5msec compander delay as per HW requirement */
  580. if (!wcd938x->comp2_enable ||
  581. (snd_soc_component_read(component,
  582. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  583. usleep_range(5000, 5010);
  584. snd_soc_component_update_bits(component,
  585. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  586. } else {
  587. snd_soc_component_update_bits(component,
  588. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  589. 0x02, 0x00);
  590. snd_soc_component_update_bits(component,
  591. WCD938X_HPH_L_EN, 0x20, 0x20);
  592. }
  593. break;
  594. case SND_SOC_DAPM_POST_PMD:
  595. snd_soc_component_update_bits(component,
  596. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  597. 0x0F, 0x01);
  598. break;
  599. }
  600. return 0;
  601. }
  602. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  603. struct snd_kcontrol *kcontrol,
  604. int event)
  605. {
  606. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  607. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  608. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  609. w->name, event);
  610. switch (event) {
  611. case SND_SOC_DAPM_PRE_PMU:
  612. wcd938x_rx_clk_enable(component);
  613. snd_soc_component_update_bits(component,
  614. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  615. snd_soc_component_update_bits(component,
  616. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  617. snd_soc_component_update_bits(component,
  618. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  619. break;
  620. case SND_SOC_DAPM_POST_PMU:
  621. snd_soc_component_update_bits(component,
  622. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  623. if (wcd938x->comp2_enable) {
  624. snd_soc_component_update_bits(component,
  625. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  626. /* 5msec compander delay as per HW requirement */
  627. if (!wcd938x->comp1_enable ||
  628. (snd_soc_component_read(component,
  629. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  630. usleep_range(5000, 5010);
  631. snd_soc_component_update_bits(component,
  632. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  633. } else {
  634. snd_soc_component_update_bits(component,
  635. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  636. 0x01, 0x00);
  637. snd_soc_component_update_bits(component,
  638. WCD938X_HPH_R_EN, 0x20, 0x20);
  639. }
  640. break;
  641. case SND_SOC_DAPM_POST_PMD:
  642. snd_soc_component_update_bits(component,
  643. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  644. 0x0F, 0x01);
  645. break;
  646. }
  647. return 0;
  648. }
  649. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  650. struct snd_kcontrol *kcontrol,
  651. int event)
  652. {
  653. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  654. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  655. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  656. w->name, event);
  657. switch (event) {
  658. case SND_SOC_DAPM_PRE_PMU:
  659. wcd938x_rx_clk_enable(component);
  660. wcd938x->ear_rx_path =
  661. snd_soc_component_read(
  662. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  663. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  664. snd_soc_component_update_bits(component,
  665. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x00);
  666. snd_soc_component_update_bits(component,
  667. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  668. snd_soc_component_update_bits(component,
  669. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  670. snd_soc_component_update_bits(component,
  671. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  672. } else {
  673. snd_soc_component_update_bits(component,
  674. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  675. snd_soc_component_update_bits(component,
  676. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  677. if (wcd938x->comp1_enable)
  678. snd_soc_component_update_bits(component,
  679. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  680. 0x02, 0x02);
  681. }
  682. /* 5 msec delay as per HW requirement */
  683. usleep_range(5000, 5010);
  684. if (wcd938x->flyback_cur_det_disable == 0)
  685. snd_soc_component_update_bits(component,
  686. WCD938X_FLYBACK_EN,
  687. 0x04, 0x00);
  688. wcd938x->flyback_cur_det_disable++;
  689. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  690. WCD_CLSH_EVENT_PRE_DAC,
  691. WCD_CLSH_STATE_EAR,
  692. wcd938x->hph_mode);
  693. break;
  694. case SND_SOC_DAPM_POST_PMD:
  695. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  696. snd_soc_component_update_bits(component,
  697. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x00);
  698. snd_soc_component_update_bits(component,
  699. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  700. } else {
  701. snd_soc_component_update_bits(component,
  702. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x00);
  703. snd_soc_component_update_bits(component,
  704. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x00);
  705. if (wcd938x->comp1_enable)
  706. snd_soc_component_update_bits(component,
  707. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  708. 0x02, 0x00);
  709. }
  710. snd_soc_component_update_bits(component,
  711. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  712. snd_soc_component_update_bits(component,
  713. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x80);
  714. break;
  715. };
  716. return 0;
  717. }
  718. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  719. struct snd_kcontrol *kcontrol,
  720. int event)
  721. {
  722. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  723. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  724. int ret = 0;
  725. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  726. w->name, event);
  727. switch (event) {
  728. case SND_SOC_DAPM_PRE_PMU:
  729. wcd938x_rx_clk_enable(component);
  730. snd_soc_component_update_bits(component,
  731. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  732. snd_soc_component_update_bits(component,
  733. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  734. snd_soc_component_update_bits(component,
  735. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  736. if (wcd938x->flyback_cur_det_disable == 0)
  737. snd_soc_component_update_bits(component,
  738. WCD938X_FLYBACK_EN,
  739. 0x04, 0x00);
  740. wcd938x->flyback_cur_det_disable++;
  741. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  742. WCD_CLSH_EVENT_PRE_DAC,
  743. WCD_CLSH_STATE_AUX,
  744. wcd938x->hph_mode);
  745. break;
  746. case SND_SOC_DAPM_POST_PMD:
  747. snd_soc_component_update_bits(component,
  748. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  749. break;
  750. };
  751. return ret;
  752. }
  753. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  754. struct snd_kcontrol *kcontrol,
  755. int event)
  756. {
  757. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  758. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  759. int ret = 0;
  760. int hph_mode = wcd938x->hph_mode;
  761. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  762. w->name, event);
  763. switch (event) {
  764. case SND_SOC_DAPM_PRE_PMU:
  765. if (wcd938x->ldoh)
  766. snd_soc_component_update_bits(component,
  767. WCD938X_LDOH_MODE,
  768. 0x80, 0x80);
  769. if (wcd938x->update_wcd_event)
  770. wcd938x->update_wcd_event(wcd938x->handle,
  771. SLV_BOLERO_EVT_RX_MUTE,
  772. (WCD_RX2 << 0x10 | 0x1));
  773. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  774. wcd938x->rx_swr_dev->dev_num,
  775. true);
  776. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  777. WCD_CLSH_EVENT_PRE_DAC,
  778. WCD_CLSH_STATE_HPHR,
  779. hph_mode);
  780. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  781. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  782. hph_mode == CLS_H_ULP) {
  783. snd_soc_component_update_bits(component,
  784. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  785. }
  786. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  787. 0x10, 0x10);
  788. wcd_clsh_set_hph_mode(component, hph_mode);
  789. /* 100 usec delay as per HW requirement */
  790. usleep_range(100, 110);
  791. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  792. snd_soc_component_update_bits(component,
  793. WCD938X_DIGITAL_PDM_WD_CTL1, 0x07, 0x03);
  794. break;
  795. case SND_SOC_DAPM_POST_PMU:
  796. /*
  797. * 7ms sleep is required if compander is enabled as per
  798. * HW requirement. If compander is disabled, then
  799. * 20ms delay is required.
  800. */
  801. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  802. if (!wcd938x->comp2_enable)
  803. usleep_range(20000, 20100);
  804. else
  805. usleep_range(7000, 7100);
  806. if (hph_mode == CLS_H_LP ||
  807. hph_mode == CLS_H_LOHIFI ||
  808. hph_mode == CLS_H_ULP)
  809. snd_soc_component_update_bits(component,
  810. WCD938X_HPH_REFBUFF_LP_CTL, 0x01,
  811. 0x00);
  812. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  813. }
  814. snd_soc_component_update_bits(component,
  815. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  816. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  817. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  818. snd_soc_component_update_bits(component,
  819. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  820. if (wcd938x->update_wcd_event)
  821. wcd938x->update_wcd_event(wcd938x->handle,
  822. SLV_BOLERO_EVT_RX_MUTE,
  823. (WCD_RX2 << 0x10));
  824. wcd_enable_irq(&wcd938x->irq_info,
  825. WCD938X_IRQ_HPHR_PDM_WD_INT);
  826. break;
  827. case SND_SOC_DAPM_PRE_PMD:
  828. if (wcd938x->update_wcd_event)
  829. wcd938x->update_wcd_event(wcd938x->handle,
  830. SLV_BOLERO_EVT_RX_MUTE,
  831. (WCD_RX2 << 0x10 | 0x1));
  832. wcd_disable_irq(&wcd938x->irq_info,
  833. WCD938X_IRQ_HPHR_PDM_WD_INT);
  834. if (wcd938x->update_wcd_event && wcd938x->comp2_enable)
  835. wcd938x->update_wcd_event(wcd938x->handle,
  836. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  837. (WCD_RX2 << 0x10));
  838. /*
  839. * 7ms sleep is required if compander is enabled as per
  840. * HW requirement. If compander is disabled, then
  841. * 20ms delay is required.
  842. */
  843. if (!wcd938x->comp2_enable)
  844. usleep_range(20000, 20100);
  845. else
  846. usleep_range(7000, 7100);
  847. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  848. 0x40, 0x00);
  849. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  850. WCD_EVENT_PRE_HPHR_PA_OFF,
  851. &wcd938x->mbhc->wcd_mbhc);
  852. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  853. break;
  854. case SND_SOC_DAPM_POST_PMD:
  855. /*
  856. * 7ms sleep is required if compander is enabled as per
  857. * HW requirement. If compander is disabled, then
  858. * 20ms delay is required.
  859. */
  860. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  861. if (!wcd938x->comp2_enable)
  862. usleep_range(20000, 20100);
  863. else
  864. usleep_range(7000, 7100);
  865. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  866. }
  867. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  868. WCD_EVENT_POST_HPHR_PA_OFF,
  869. &wcd938x->mbhc->wcd_mbhc);
  870. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  871. 0x10, 0x00);
  872. snd_soc_component_update_bits(component,
  873. WCD938X_DIGITAL_PDM_WD_CTL1, 0x07, 0x00);
  874. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  875. WCD_CLSH_EVENT_POST_PA,
  876. WCD_CLSH_STATE_HPHR,
  877. hph_mode);
  878. if (wcd938x->ldoh)
  879. snd_soc_component_update_bits(component,
  880. WCD938X_LDOH_MODE,
  881. 0x80, 0x00);
  882. break;
  883. };
  884. return ret;
  885. }
  886. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  887. struct snd_kcontrol *kcontrol,
  888. int event)
  889. {
  890. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  891. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  892. int ret = 0;
  893. int hph_mode = wcd938x->hph_mode;
  894. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  895. w->name, event);
  896. switch (event) {
  897. case SND_SOC_DAPM_PRE_PMU:
  898. if (wcd938x->ldoh)
  899. snd_soc_component_update_bits(component,
  900. WCD938X_LDOH_MODE,
  901. 0x80, 0x80);
  902. if (wcd938x->update_wcd_event)
  903. wcd938x->update_wcd_event(wcd938x->handle,
  904. SLV_BOLERO_EVT_RX_MUTE,
  905. (WCD_RX1 << 0x10 | 0x01));
  906. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  907. wcd938x->rx_swr_dev->dev_num,
  908. true);
  909. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  910. WCD_CLSH_EVENT_PRE_DAC,
  911. WCD_CLSH_STATE_HPHL,
  912. hph_mode);
  913. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  914. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  915. hph_mode == CLS_H_ULP) {
  916. snd_soc_component_update_bits(component,
  917. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  918. }
  919. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  920. 0x20, 0x20);
  921. wcd_clsh_set_hph_mode(component, hph_mode);
  922. /* 100 usec delay as per HW requirement */
  923. usleep_range(100, 110);
  924. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  925. snd_soc_component_update_bits(component,
  926. WCD938X_DIGITAL_PDM_WD_CTL0, 0x07, 0x03);
  927. break;
  928. case SND_SOC_DAPM_POST_PMU:
  929. /*
  930. * 7ms sleep is required if compander is enabled as per
  931. * HW requirement. If compander is disabled, then
  932. * 20ms delay is required.
  933. */
  934. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  935. if (!wcd938x->comp1_enable)
  936. usleep_range(20000, 20100);
  937. else
  938. usleep_range(7000, 7100);
  939. if (hph_mode == CLS_H_LP ||
  940. hph_mode == CLS_H_LOHIFI ||
  941. hph_mode == CLS_H_ULP)
  942. snd_soc_component_update_bits(component,
  943. WCD938X_HPH_REFBUFF_LP_CTL,
  944. 0x01, 0x00);
  945. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  946. }
  947. snd_soc_component_update_bits(component,
  948. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  949. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  950. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  951. snd_soc_component_update_bits(component,
  952. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  953. if (wcd938x->update_wcd_event)
  954. wcd938x->update_wcd_event(wcd938x->handle,
  955. SLV_BOLERO_EVT_RX_MUTE,
  956. (WCD_RX1 << 0x10));
  957. wcd_enable_irq(&wcd938x->irq_info,
  958. WCD938X_IRQ_HPHL_PDM_WD_INT);
  959. break;
  960. case SND_SOC_DAPM_PRE_PMD:
  961. if (wcd938x->update_wcd_event)
  962. wcd938x->update_wcd_event(wcd938x->handle,
  963. SLV_BOLERO_EVT_RX_MUTE,
  964. (WCD_RX1 << 0x10 | 0x1));
  965. wcd_disable_irq(&wcd938x->irq_info,
  966. WCD938X_IRQ_HPHL_PDM_WD_INT);
  967. if (wcd938x->update_wcd_event && wcd938x->comp1_enable)
  968. wcd938x->update_wcd_event(wcd938x->handle,
  969. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  970. (WCD_RX1 << 0x10));
  971. /*
  972. * 7ms sleep is required if compander is enabled as per
  973. * HW requirement. If compander is disabled, then
  974. * 20ms delay is required.
  975. */
  976. if (!wcd938x->comp1_enable)
  977. usleep_range(20000, 20100);
  978. else
  979. usleep_range(7000, 7100);
  980. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  981. 0x80, 0x00);
  982. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  983. WCD_EVENT_PRE_HPHL_PA_OFF,
  984. &wcd938x->mbhc->wcd_mbhc);
  985. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  986. break;
  987. case SND_SOC_DAPM_POST_PMD:
  988. /*
  989. * 7ms sleep is required if compander is enabled as per
  990. * HW requirement. If compander is disabled, then
  991. * 20ms delay is required.
  992. */
  993. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  994. if (!wcd938x->comp1_enable)
  995. usleep_range(21000, 21100);
  996. else
  997. usleep_range(7000, 7100);
  998. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  999. }
  1000. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1001. WCD_EVENT_POST_HPHL_PA_OFF,
  1002. &wcd938x->mbhc->wcd_mbhc);
  1003. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1004. 0x20, 0x00);
  1005. snd_soc_component_update_bits(component,
  1006. WCD938X_DIGITAL_PDM_WD_CTL0, 0x07, 0x00);
  1007. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1008. WCD_CLSH_EVENT_POST_PA,
  1009. WCD_CLSH_STATE_HPHL,
  1010. hph_mode);
  1011. if (wcd938x->ldoh)
  1012. snd_soc_component_update_bits(component,
  1013. WCD938X_LDOH_MODE,
  1014. 0x80, 0x00);
  1015. break;
  1016. };
  1017. return ret;
  1018. }
  1019. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  1020. struct snd_kcontrol *kcontrol,
  1021. int event)
  1022. {
  1023. struct snd_soc_component *component =
  1024. snd_soc_dapm_to_component(w->dapm);
  1025. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1026. int hph_mode = wcd938x->hph_mode;
  1027. int ret = 0;
  1028. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1029. w->name, event);
  1030. switch (event) {
  1031. case SND_SOC_DAPM_PRE_PMU:
  1032. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  1033. wcd938x->rx_swr_dev->dev_num,
  1034. true);
  1035. snd_soc_component_update_bits(component,
  1036. WCD938X_DIGITAL_PDM_WD_CTL2, 0x01, 0x01);
  1037. break;
  1038. case SND_SOC_DAPM_POST_PMU:
  1039. /* 1 msec delay as per HW requirement */
  1040. usleep_range(1000, 1010);
  1041. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1042. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1043. snd_soc_component_update_bits(component,
  1044. WCD938X_ANA_RX_SUPPLIES,
  1045. 0x02, 0x02);
  1046. if (wcd938x->update_wcd_event)
  1047. wcd938x->update_wcd_event(wcd938x->handle,
  1048. SLV_BOLERO_EVT_RX_MUTE,
  1049. (WCD_RX3 << 0x10));
  1050. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  1051. break;
  1052. case SND_SOC_DAPM_PRE_PMD:
  1053. wcd_disable_irq(&wcd938x->irq_info,
  1054. WCD938X_IRQ_AUX_PDM_WD_INT);
  1055. if (wcd938x->update_wcd_event)
  1056. wcd938x->update_wcd_event(wcd938x->handle,
  1057. SLV_BOLERO_EVT_RX_MUTE,
  1058. (WCD_RX3 << 0x10 | 0x1));
  1059. break;
  1060. case SND_SOC_DAPM_POST_PMD:
  1061. /* 1 msec delay as per HW requirement */
  1062. usleep_range(1000, 1010);
  1063. snd_soc_component_update_bits(component,
  1064. WCD938X_DIGITAL_PDM_WD_CTL2, 0x01, 0x00);
  1065. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1066. WCD_CLSH_EVENT_POST_PA,
  1067. WCD_CLSH_STATE_AUX,
  1068. hph_mode);
  1069. wcd938x->flyback_cur_det_disable--;
  1070. if (wcd938x->flyback_cur_det_disable == 0)
  1071. snd_soc_component_update_bits(component,
  1072. WCD938X_FLYBACK_EN,
  1073. 0x04, 0x04);
  1074. break;
  1075. };
  1076. return ret;
  1077. }
  1078. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1079. struct snd_kcontrol *kcontrol,
  1080. int event)
  1081. {
  1082. struct snd_soc_component *component =
  1083. snd_soc_dapm_to_component(w->dapm);
  1084. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1085. int hph_mode = wcd938x->hph_mode;
  1086. int ret = 0;
  1087. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1088. w->name, event);
  1089. switch (event) {
  1090. case SND_SOC_DAPM_PRE_PMU:
  1091. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  1092. wcd938x->rx_swr_dev->dev_num,
  1093. true);
  1094. /*
  1095. * Enable watchdog interrupt for HPHL or AUX
  1096. * depending on mux value
  1097. */
  1098. wcd938x->ear_rx_path =
  1099. snd_soc_component_read(
  1100. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  1101. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1102. snd_soc_component_update_bits(component,
  1103. WCD938X_DIGITAL_PDM_WD_CTL2,
  1104. 0x01, 0x01);
  1105. else
  1106. snd_soc_component_update_bits(component,
  1107. WCD938X_DIGITAL_PDM_WD_CTL0,
  1108. 0x07, 0x03);
  1109. if (!wcd938x->comp1_enable)
  1110. snd_soc_component_update_bits(component,
  1111. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  1112. break;
  1113. case SND_SOC_DAPM_POST_PMU:
  1114. /* 6 msec delay as per HW requirement */
  1115. usleep_range(6000, 6010);
  1116. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1117. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1118. snd_soc_component_update_bits(component,
  1119. WCD938X_ANA_RX_SUPPLIES,
  1120. 0x02, 0x02);
  1121. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1122. if (wcd938x->update_wcd_event)
  1123. wcd938x->update_wcd_event(wcd938x->handle,
  1124. SLV_BOLERO_EVT_RX_MUTE,
  1125. (WCD_RX3 << 0x10));
  1126. wcd_enable_irq(&wcd938x->irq_info,
  1127. WCD938X_IRQ_AUX_PDM_WD_INT);
  1128. } else {
  1129. if (wcd938x->update_wcd_event)
  1130. wcd938x->update_wcd_event(wcd938x->handle,
  1131. SLV_BOLERO_EVT_RX_MUTE,
  1132. (WCD_RX1 << 0x10));
  1133. wcd_enable_irq(&wcd938x->irq_info,
  1134. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1135. }
  1136. break;
  1137. case SND_SOC_DAPM_PRE_PMD:
  1138. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1139. wcd_disable_irq(&wcd938x->irq_info,
  1140. WCD938X_IRQ_AUX_PDM_WD_INT);
  1141. if (wcd938x->update_wcd_event)
  1142. wcd938x->update_wcd_event(wcd938x->handle,
  1143. SLV_BOLERO_EVT_RX_MUTE,
  1144. (WCD_RX3 << 0x10 | 0x1));
  1145. } else {
  1146. wcd_disable_irq(&wcd938x->irq_info,
  1147. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1148. if (wcd938x->update_wcd_event)
  1149. wcd938x->update_wcd_event(wcd938x->handle,
  1150. SLV_BOLERO_EVT_RX_MUTE,
  1151. (WCD_RX1 << 0x10 | 0x1));
  1152. }
  1153. break;
  1154. case SND_SOC_DAPM_POST_PMD:
  1155. if (!wcd938x->comp1_enable)
  1156. snd_soc_component_update_bits(component,
  1157. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  1158. /* 7 msec delay as per HW requirement */
  1159. usleep_range(7000, 7010);
  1160. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1161. snd_soc_component_update_bits(component,
  1162. WCD938X_DIGITAL_PDM_WD_CTL2,
  1163. 0x01, 0x00);
  1164. else
  1165. snd_soc_component_update_bits(component,
  1166. WCD938X_DIGITAL_PDM_WD_CTL0,
  1167. 0x07, 0x00);
  1168. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1169. WCD_CLSH_EVENT_POST_PA,
  1170. WCD_CLSH_STATE_EAR,
  1171. hph_mode);
  1172. wcd938x->flyback_cur_det_disable--;
  1173. if (wcd938x->flyback_cur_det_disable == 0)
  1174. snd_soc_component_update_bits(component,
  1175. WCD938X_FLYBACK_EN,
  1176. 0x04, 0x04);
  1177. break;
  1178. };
  1179. return ret;
  1180. }
  1181. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  1182. struct snd_kcontrol *kcontrol,
  1183. int event)
  1184. {
  1185. struct snd_soc_component *component =
  1186. snd_soc_dapm_to_component(w->dapm);
  1187. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1188. int mode = wcd938x->hph_mode;
  1189. int ret = 0;
  1190. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1191. w->name, event);
  1192. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1193. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1194. wcd938x_rx_connect_port(component, CLSH,
  1195. SND_SOC_DAPM_EVENT_ON(event));
  1196. }
  1197. if (SND_SOC_DAPM_EVENT_OFF(event))
  1198. ret = swr_slvdev_datapath_control(
  1199. wcd938x->rx_swr_dev,
  1200. wcd938x->rx_swr_dev->dev_num,
  1201. false);
  1202. return ret;
  1203. }
  1204. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  1205. struct snd_kcontrol *kcontrol,
  1206. int event)
  1207. {
  1208. struct snd_soc_component *component =
  1209. snd_soc_dapm_to_component(w->dapm);
  1210. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1211. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1212. w->name, event);
  1213. switch (event) {
  1214. case SND_SOC_DAPM_PRE_PMU:
  1215. wcd938x_rx_connect_port(component, HPH_L, true);
  1216. if (wcd938x->comp1_enable)
  1217. wcd938x_rx_connect_port(component, COMP_L, true);
  1218. break;
  1219. case SND_SOC_DAPM_POST_PMD:
  1220. wcd938x_rx_connect_port(component, HPH_L, false);
  1221. if (wcd938x->comp1_enable)
  1222. wcd938x_rx_connect_port(component, COMP_L, false);
  1223. wcd938x_rx_clk_disable(component);
  1224. snd_soc_component_update_bits(component,
  1225. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1226. 0x01, 0x00);
  1227. break;
  1228. };
  1229. return 0;
  1230. }
  1231. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  1232. struct snd_kcontrol *kcontrol, int event)
  1233. {
  1234. struct snd_soc_component *component =
  1235. snd_soc_dapm_to_component(w->dapm);
  1236. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1237. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1238. w->name, event);
  1239. switch (event) {
  1240. case SND_SOC_DAPM_PRE_PMU:
  1241. wcd938x_rx_connect_port(component, HPH_R, true);
  1242. if (wcd938x->comp2_enable)
  1243. wcd938x_rx_connect_port(component, COMP_R, true);
  1244. break;
  1245. case SND_SOC_DAPM_POST_PMD:
  1246. wcd938x_rx_connect_port(component, HPH_R, false);
  1247. if (wcd938x->comp2_enable)
  1248. wcd938x_rx_connect_port(component, COMP_R, false);
  1249. wcd938x_rx_clk_disable(component);
  1250. snd_soc_component_update_bits(component,
  1251. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1252. 0x02, 0x00);
  1253. break;
  1254. };
  1255. return 0;
  1256. }
  1257. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  1258. struct snd_kcontrol *kcontrol,
  1259. int event)
  1260. {
  1261. struct snd_soc_component *component =
  1262. snd_soc_dapm_to_component(w->dapm);
  1263. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1264. w->name, event);
  1265. switch (event) {
  1266. case SND_SOC_DAPM_PRE_PMU:
  1267. wcd938x_rx_connect_port(component, LO, true);
  1268. break;
  1269. case SND_SOC_DAPM_POST_PMD:
  1270. wcd938x_rx_connect_port(component, LO, false);
  1271. /* 6 msec delay as per HW requirement */
  1272. usleep_range(6000, 6010);
  1273. wcd938x_rx_clk_disable(component);
  1274. snd_soc_component_update_bits(component,
  1275. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1276. break;
  1277. }
  1278. return 0;
  1279. }
  1280. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1281. struct snd_kcontrol *kcontrol,
  1282. int event)
  1283. {
  1284. struct snd_soc_component *component =
  1285. snd_soc_dapm_to_component(w->dapm);
  1286. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1287. u16 dmic_clk_reg, dmic_clk_en_reg;
  1288. s32 *dmic_clk_cnt;
  1289. u8 dmic_ctl_shift = 0;
  1290. u8 dmic_clk_shift = 0;
  1291. u8 dmic_clk_mask = 0;
  1292. u16 dmic2_left_en = 0;
  1293. int ret = 0;
  1294. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1295. w->name, event);
  1296. switch (w->shift) {
  1297. case 0:
  1298. case 1:
  1299. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  1300. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1301. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  1302. dmic_clk_mask = 0x0F;
  1303. dmic_clk_shift = 0x00;
  1304. dmic_ctl_shift = 0x00;
  1305. break;
  1306. case 2:
  1307. dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1308. case 3:
  1309. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  1310. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1311. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1312. dmic_clk_mask = 0xF0;
  1313. dmic_clk_shift = 0x04;
  1314. dmic_ctl_shift = 0x01;
  1315. break;
  1316. case 4:
  1317. case 5:
  1318. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  1319. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1320. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  1321. dmic_clk_mask = 0x0F;
  1322. dmic_clk_shift = 0x00;
  1323. dmic_ctl_shift = 0x02;
  1324. break;
  1325. case 6:
  1326. case 7:
  1327. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  1328. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1329. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  1330. dmic_clk_mask = 0xF0;
  1331. dmic_clk_shift = 0x04;
  1332. dmic_ctl_shift = 0x03;
  1333. break;
  1334. default:
  1335. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1336. __func__);
  1337. return -EINVAL;
  1338. };
  1339. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1340. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1341. switch (event) {
  1342. case SND_SOC_DAPM_PRE_PMU:
  1343. snd_soc_component_update_bits(component,
  1344. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1345. (0x01 << dmic_ctl_shift), 0x00);
  1346. /* 250us sleep as per HW requirement */
  1347. usleep_range(250, 260);
  1348. if (dmic2_left_en)
  1349. snd_soc_component_update_bits(component,
  1350. dmic2_left_en, 0x80, 0x80);
  1351. /* Setting DMIC clock rate to 2.4MHz */
  1352. snd_soc_component_update_bits(component,
  1353. dmic_clk_reg, dmic_clk_mask,
  1354. (0x03 << dmic_clk_shift));
  1355. snd_soc_component_update_bits(component,
  1356. dmic_clk_en_reg, 0x08, 0x08);
  1357. /* enable clock scaling */
  1358. snd_soc_component_update_bits(component,
  1359. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  1360. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1361. wcd938x->tx_swr_dev->dev_num,
  1362. true);
  1363. break;
  1364. case SND_SOC_DAPM_POST_PMD:
  1365. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), 0,
  1366. false);
  1367. snd_soc_component_update_bits(component,
  1368. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1369. (0x01 << dmic_ctl_shift),
  1370. (0x01 << dmic_ctl_shift));
  1371. if (dmic2_left_en)
  1372. snd_soc_component_update_bits(component,
  1373. dmic2_left_en, 0x80, 0x00);
  1374. snd_soc_component_update_bits(component,
  1375. dmic_clk_en_reg, 0x08, 0x00);
  1376. break;
  1377. };
  1378. return ret;
  1379. }
  1380. /*
  1381. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1382. * @micb_mv: micbias in mv
  1383. *
  1384. * return register value converted
  1385. */
  1386. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1387. {
  1388. /* min micbias voltage is 1V and maximum is 2.85V */
  1389. if (micb_mv < 1000 || micb_mv > 2850) {
  1390. pr_err("%s: unsupported micbias voltage\n", __func__);
  1391. return -EINVAL;
  1392. }
  1393. return (micb_mv - 1000) / 50;
  1394. }
  1395. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1396. /*
  1397. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1398. * @component: handle to snd_soc_component *
  1399. * @req_volt: micbias voltage to be set
  1400. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1401. *
  1402. * return 0 if adjustment is success or error code in case of failure
  1403. */
  1404. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1405. int req_volt, int micb_num)
  1406. {
  1407. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1408. int cur_vout_ctl, req_vout_ctl;
  1409. int micb_reg, micb_val, micb_en;
  1410. int ret = 0;
  1411. switch (micb_num) {
  1412. case MIC_BIAS_1:
  1413. micb_reg = WCD938X_ANA_MICB1;
  1414. break;
  1415. case MIC_BIAS_2:
  1416. micb_reg = WCD938X_ANA_MICB2;
  1417. break;
  1418. case MIC_BIAS_3:
  1419. micb_reg = WCD938X_ANA_MICB3;
  1420. break;
  1421. case MIC_BIAS_4:
  1422. micb_reg = WCD938X_ANA_MICB4;
  1423. break;
  1424. default:
  1425. return -EINVAL;
  1426. }
  1427. mutex_lock(&wcd938x->micb_lock);
  1428. /*
  1429. * If requested micbias voltage is same as current micbias
  1430. * voltage, then just return. Otherwise, adjust voltage as
  1431. * per requested value. If micbias is already enabled, then
  1432. * to avoid slow micbias ramp-up or down enable pull-up
  1433. * momentarily, change the micbias value and then re-enable
  1434. * micbias.
  1435. */
  1436. micb_val = snd_soc_component_read(component, micb_reg);
  1437. micb_en = (micb_val & 0xC0) >> 6;
  1438. cur_vout_ctl = micb_val & 0x3F;
  1439. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1440. if (req_vout_ctl < 0) {
  1441. ret = -EINVAL;
  1442. goto exit;
  1443. }
  1444. if (cur_vout_ctl == req_vout_ctl) {
  1445. ret = 0;
  1446. goto exit;
  1447. }
  1448. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1449. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1450. req_volt, micb_en);
  1451. if (micb_en == 0x1)
  1452. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1453. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1454. if (micb_en == 0x1) {
  1455. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1456. /*
  1457. * Add 2ms delay as per HW requirement after enabling
  1458. * micbias
  1459. */
  1460. usleep_range(2000, 2100);
  1461. }
  1462. exit:
  1463. mutex_unlock(&wcd938x->micb_lock);
  1464. return ret;
  1465. }
  1466. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1467. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1468. struct snd_kcontrol *kcontrol,
  1469. int event)
  1470. {
  1471. struct snd_soc_component *component =
  1472. snd_soc_dapm_to_component(w->dapm);
  1473. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1474. int ret = 0;
  1475. int bank = 0;
  1476. u8 mode = 0;
  1477. int i = 0;
  1478. int rate = 0;
  1479. bank = (wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1480. wcd938x->tx_swr_dev->dev_num) ? 0 : 1);
  1481. /* power mode is applicable only to analog mics */
  1482. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1483. /* Get channel rate */
  1484. rate = wcd938x_get_clk_rate(wcd938x->tx_mode[w->shift - ADC1]);
  1485. }
  1486. switch (event) {
  1487. case SND_SOC_DAPM_PRE_PMU:
  1488. /* Check AMIC2 is connected to ADC2 to take an action on BCS */
  1489. if (w->shift == ADC2 && !(snd_soc_component_read(component,
  1490. WCD938X_TX_NEW_AMIC_MUX_CFG) & 0x80)) {
  1491. if (!wcd938x->bcs_dis)
  1492. wcd938x_tx_connect_port(component, MBHC,
  1493. SWR_CLK_RATE_4P8MHZ, true);
  1494. set_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1495. }
  1496. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1497. set_bit(w->shift - ADC1, &wcd938x->status_mask);
  1498. wcd938x_tx_connect_port(component, w->shift, rate,
  1499. true);
  1500. } else {
  1501. wcd938x_tx_connect_port(component, w->shift,
  1502. SWR_CLK_RATE_2P4MHZ, true);
  1503. }
  1504. break;
  1505. case SND_SOC_DAPM_POST_PMD:
  1506. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1507. if (strnstr(w->name, "ADC1", sizeof("ADC1"))) {
  1508. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1509. clear_bit(WCD_ADC1_MODE, &wcd938x->status_mask);
  1510. } else if (strnstr(w->name, "ADC2", sizeof("ADC2"))) {
  1511. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1512. clear_bit(WCD_ADC2_MODE, &wcd938x->status_mask);
  1513. } else if (strnstr(w->name, "ADC3", sizeof("ADC3"))) {
  1514. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1515. clear_bit(WCD_ADC3_MODE, &wcd938x->status_mask);
  1516. } else if (strnstr(w->name, "ADC4", sizeof("ADC4"))) {
  1517. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1518. clear_bit(WCD_ADC4_MODE, &wcd938x->status_mask);
  1519. }
  1520. }
  1521. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1522. if (test_bit(WCD_ADC1, &wcd938x->status_mask) ||
  1523. test_bit(WCD_ADC1_MODE, &wcd938x->status_mask))
  1524. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
  1525. if (test_bit(WCD_ADC2, &wcd938x->status_mask) ||
  1526. test_bit(WCD_ADC2_MODE, &wcd938x->status_mask))
  1527. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
  1528. if (test_bit(WCD_ADC3, &wcd938x->status_mask) ||
  1529. test_bit(WCD_ADC3_MODE, &wcd938x->status_mask))
  1530. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
  1531. if (test_bit(WCD_ADC4, &wcd938x->status_mask) ||
  1532. test_bit(WCD_ADC4_MODE, &wcd938x->status_mask))
  1533. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
  1534. if (mode != 0) {
  1535. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1536. if (mode & (1 << i)) {
  1537. i++;
  1538. break;
  1539. }
  1540. }
  1541. }
  1542. rate = wcd938x_get_clk_rate(i);
  1543. if (wcd938x->adc_count) {
  1544. rate = (wcd938x->adc_count * rate);
  1545. if (rate > SWR_CLK_RATE_9P6MHZ)
  1546. rate = SWR_CLK_RATE_9P6MHZ;
  1547. }
  1548. wcd938x_set_swr_clk_rate(component, rate, bank);
  1549. }
  1550. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1551. wcd938x->tx_swr_dev->dev_num,
  1552. false);
  1553. if (strnstr(w->name, "ADC", sizeof("ADC")))
  1554. wcd938x_set_swr_clk_rate(component, rate, !bank);
  1555. break;
  1556. };
  1557. return ret;
  1558. }
  1559. static int wcd938x_get_adc_mode(int val)
  1560. {
  1561. int ret = 0;
  1562. switch (val) {
  1563. case ADC_MODE_INVALID:
  1564. ret = ADC_MODE_VAL_NORMAL;
  1565. break;
  1566. case ADC_MODE_HIFI:
  1567. ret = ADC_MODE_VAL_HIFI;
  1568. break;
  1569. case ADC_MODE_LO_HIF:
  1570. ret = ADC_MODE_VAL_LO_HIF;
  1571. break;
  1572. case ADC_MODE_NORMAL:
  1573. ret = ADC_MODE_VAL_NORMAL;
  1574. break;
  1575. case ADC_MODE_LP:
  1576. ret = ADC_MODE_VAL_LP;
  1577. break;
  1578. case ADC_MODE_ULP1:
  1579. ret = ADC_MODE_VAL_ULP1;
  1580. break;
  1581. case ADC_MODE_ULP2:
  1582. ret = ADC_MODE_VAL_ULP2;
  1583. break;
  1584. default:
  1585. ret = -EINVAL;
  1586. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1587. break;
  1588. }
  1589. return ret;
  1590. }
  1591. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1592. int channel, int mode)
  1593. {
  1594. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1595. int ret = 0;
  1596. switch (channel) {
  1597. case 0:
  1598. reg = WCD938X_ANA_TX_CH2;
  1599. mask = 0x40;
  1600. break;
  1601. case 1:
  1602. reg = WCD938X_ANA_TX_CH2;
  1603. mask = 0x20;
  1604. break;
  1605. case 2:
  1606. reg = WCD938X_ANA_TX_CH4;
  1607. mask = 0x40;
  1608. break;
  1609. case 3:
  1610. reg = WCD938X_ANA_TX_CH4;
  1611. mask = 0x20;
  1612. break;
  1613. default:
  1614. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1615. ret = -EINVAL;
  1616. break;
  1617. }
  1618. if (!mode)
  1619. val = 0x00;
  1620. else
  1621. val = mask;
  1622. if (!ret)
  1623. snd_soc_component_update_bits(component, reg, mask, val);
  1624. return ret;
  1625. }
  1626. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1627. struct snd_kcontrol *kcontrol,
  1628. int event){
  1629. struct snd_soc_component *component =
  1630. snd_soc_dapm_to_component(w->dapm);
  1631. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1632. int clk_rate = 0, ret = 0;
  1633. int mode = 0, i = 0, bank = 0;
  1634. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1635. w->name, event);
  1636. bank = (wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1637. wcd938x->tx_swr_dev->dev_num) ? 0 : 1);
  1638. switch (event) {
  1639. case SND_SOC_DAPM_PRE_PMU:
  1640. wcd938x->adc_count++;
  1641. if (test_bit(WCD_ADC1, &wcd938x->status_mask) ||
  1642. test_bit(WCD_ADC1_MODE, &wcd938x->status_mask))
  1643. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
  1644. if (test_bit(WCD_ADC2, &wcd938x->status_mask) ||
  1645. test_bit(WCD_ADC2_MODE, &wcd938x->status_mask))
  1646. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
  1647. if (test_bit(WCD_ADC3, &wcd938x->status_mask) ||
  1648. test_bit(WCD_ADC3_MODE, &wcd938x->status_mask))
  1649. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
  1650. if (test_bit(WCD_ADC4, &wcd938x->status_mask) ||
  1651. test_bit(WCD_ADC4_MODE, &wcd938x->status_mask))
  1652. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
  1653. if (mode != 0) {
  1654. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1655. if (mode & (1 << i)) {
  1656. i++;
  1657. break;
  1658. }
  1659. }
  1660. }
  1661. clk_rate = wcd938x_get_clk_rate(i);
  1662. /* clk_rate depends on number of paths getting enabled */
  1663. clk_rate = (wcd938x->adc_count * clk_rate);
  1664. if (clk_rate > SWR_CLK_RATE_9P6MHZ)
  1665. clk_rate = SWR_CLK_RATE_9P6MHZ;
  1666. wcd938x_set_swr_clk_rate(component, clk_rate, bank);
  1667. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1668. wcd938x->tx_swr_dev->dev_num,
  1669. true);
  1670. wcd938x_set_swr_clk_rate(component, clk_rate, !bank);
  1671. break;
  1672. case SND_SOC_DAPM_POST_PMD:
  1673. wcd938x->adc_count--;
  1674. if (wcd938x->adc_count < 0)
  1675. wcd938x->adc_count = 0;
  1676. wcd938x_tx_connect_port(component, ADC1 + w->shift, 0, false);
  1677. if (w->shift + ADC1 == ADC2 &&
  1678. test_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask)) {
  1679. if (!wcd938x->bcs_dis)
  1680. wcd938x_tx_connect_port(component, MBHC, 0,
  1681. false);
  1682. clear_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1683. }
  1684. break;
  1685. };
  1686. return ret;
  1687. }
  1688. void wcd938x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1689. bool bcs_disable)
  1690. {
  1691. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1692. if (wcd938x->update_wcd_event) {
  1693. if (bcs_disable)
  1694. wcd938x->update_wcd_event(wcd938x->handle,
  1695. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  1696. else
  1697. wcd938x->update_wcd_event(wcd938x->handle,
  1698. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  1699. }
  1700. }
  1701. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1702. struct snd_kcontrol *kcontrol, int event)
  1703. {
  1704. struct snd_soc_component *component =
  1705. snd_soc_dapm_to_component(w->dapm);
  1706. struct wcd938x_priv *wcd938x =
  1707. snd_soc_component_get_drvdata(component);
  1708. int ret = 0;
  1709. u8 mode = 0;
  1710. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1711. w->name, event);
  1712. switch (event) {
  1713. case SND_SOC_DAPM_PRE_PMU:
  1714. snd_soc_component_update_bits(component,
  1715. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1716. snd_soc_component_update_bits(component,
  1717. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1718. snd_soc_component_update_bits(component,
  1719. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1720. snd_soc_component_update_bits(component,
  1721. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1722. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1723. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1724. if (mode < 0) {
  1725. dev_info(component->dev,
  1726. "%s: invalid mode, setting to normal mode\n",
  1727. __func__);
  1728. mode = ADC_MODE_VAL_NORMAL;
  1729. }
  1730. switch (w->shift) {
  1731. case 0:
  1732. snd_soc_component_update_bits(component,
  1733. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1734. mode);
  1735. snd_soc_component_update_bits(component,
  1736. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x10);
  1737. break;
  1738. case 1:
  1739. snd_soc_component_update_bits(component,
  1740. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1741. mode << 4);
  1742. snd_soc_component_update_bits(component,
  1743. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x20);
  1744. break;
  1745. case 2:
  1746. snd_soc_component_update_bits(component,
  1747. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1748. mode);
  1749. snd_soc_component_update_bits(component,
  1750. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
  1751. break;
  1752. case 3:
  1753. snd_soc_component_update_bits(component,
  1754. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1755. mode << 4);
  1756. snd_soc_component_update_bits(component,
  1757. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1758. break;
  1759. default:
  1760. break;
  1761. }
  1762. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1763. break;
  1764. case SND_SOC_DAPM_POST_PMD:
  1765. switch (w->shift) {
  1766. case 0:
  1767. snd_soc_component_update_bits(component,
  1768. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1769. 0x00);
  1770. snd_soc_component_update_bits(component,
  1771. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1772. break;
  1773. case 1:
  1774. snd_soc_component_update_bits(component,
  1775. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1776. 0x00);
  1777. snd_soc_component_update_bits(component,
  1778. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x00);
  1779. break;
  1780. case 2:
  1781. snd_soc_component_update_bits(component,
  1782. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1783. 0x00);
  1784. snd_soc_component_update_bits(component,
  1785. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x00);
  1786. break;
  1787. case 3:
  1788. snd_soc_component_update_bits(component,
  1789. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1790. 0x00);
  1791. snd_soc_component_update_bits(component,
  1792. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1793. break;
  1794. default:
  1795. break;
  1796. }
  1797. if (wcd938x->adc_count == 0) {
  1798. snd_soc_component_update_bits(component,
  1799. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1800. snd_soc_component_update_bits(component,
  1801. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1802. }
  1803. break;
  1804. };
  1805. return ret;
  1806. }
  1807. int wcd938x_micbias_control(struct snd_soc_component *component,
  1808. int micb_num, int req, bool is_dapm)
  1809. {
  1810. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1811. int micb_index = micb_num - 1;
  1812. u16 micb_reg;
  1813. int pre_off_event = 0, post_off_event = 0;
  1814. int post_on_event = 0, post_dapm_off = 0;
  1815. int post_dapm_on = 0;
  1816. int ret = 0;
  1817. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1818. dev_err(component->dev,
  1819. "%s: Invalid micbias index, micb_ind:%d\n",
  1820. __func__, micb_index);
  1821. return -EINVAL;
  1822. }
  1823. if (NULL == wcd938x) {
  1824. dev_err(component->dev,
  1825. "%s: wcd938x private data is NULL\n", __func__);
  1826. return -EINVAL;
  1827. }
  1828. switch (micb_num) {
  1829. case MIC_BIAS_1:
  1830. micb_reg = WCD938X_ANA_MICB1;
  1831. break;
  1832. case MIC_BIAS_2:
  1833. micb_reg = WCD938X_ANA_MICB2;
  1834. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1835. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1836. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1837. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1838. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1839. break;
  1840. case MIC_BIAS_3:
  1841. micb_reg = WCD938X_ANA_MICB3;
  1842. break;
  1843. case MIC_BIAS_4:
  1844. micb_reg = WCD938X_ANA_MICB4;
  1845. break;
  1846. default:
  1847. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1848. __func__, micb_num);
  1849. return -EINVAL;
  1850. };
  1851. mutex_lock(&wcd938x->micb_lock);
  1852. switch (req) {
  1853. case MICB_PULLUP_ENABLE:
  1854. if (!wcd938x->dev_up) {
  1855. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1856. __func__, req);
  1857. ret = -ENODEV;
  1858. goto done;
  1859. }
  1860. wcd938x->pullup_ref[micb_index]++;
  1861. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1862. (wcd938x->micb_ref[micb_index] == 0))
  1863. snd_soc_component_update_bits(component, micb_reg,
  1864. 0xC0, 0x80);
  1865. break;
  1866. case MICB_PULLUP_DISABLE:
  1867. if (wcd938x->pullup_ref[micb_index] > 0)
  1868. wcd938x->pullup_ref[micb_index]--;
  1869. if (!wcd938x->dev_up) {
  1870. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1871. __func__, req);
  1872. ret = -ENODEV;
  1873. goto done;
  1874. }
  1875. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1876. (wcd938x->micb_ref[micb_index] == 0))
  1877. snd_soc_component_update_bits(component, micb_reg,
  1878. 0xC0, 0x00);
  1879. break;
  1880. case MICB_ENABLE:
  1881. if (!wcd938x->dev_up) {
  1882. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1883. __func__, req);
  1884. ret = -ENODEV;
  1885. goto done;
  1886. }
  1887. wcd938x->micb_ref[micb_index]++;
  1888. if (wcd938x->micb_ref[micb_index] == 1) {
  1889. snd_soc_component_update_bits(component,
  1890. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0, 0xF0);
  1891. snd_soc_component_update_bits(component,
  1892. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1893. snd_soc_component_update_bits(component,
  1894. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1895. snd_soc_component_update_bits(component,
  1896. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1897. snd_soc_component_update_bits(component,
  1898. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1899. snd_soc_component_update_bits(component,
  1900. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1901. snd_soc_component_update_bits(component,
  1902. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1903. snd_soc_component_update_bits(component,
  1904. micb_reg, 0xC0, 0x40);
  1905. if (post_on_event)
  1906. blocking_notifier_call_chain(
  1907. &wcd938x->mbhc->notifier,
  1908. post_on_event,
  1909. &wcd938x->mbhc->wcd_mbhc);
  1910. }
  1911. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1912. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1913. post_dapm_on,
  1914. &wcd938x->mbhc->wcd_mbhc);
  1915. break;
  1916. case MICB_DISABLE:
  1917. if (wcd938x->micb_ref[micb_index] > 0)
  1918. wcd938x->micb_ref[micb_index]--;
  1919. if (!wcd938x->dev_up) {
  1920. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1921. __func__, req);
  1922. ret = -ENODEV;
  1923. goto done;
  1924. }
  1925. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1926. (wcd938x->pullup_ref[micb_index] > 0))
  1927. snd_soc_component_update_bits(component, micb_reg,
  1928. 0xC0, 0x80);
  1929. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1930. (wcd938x->pullup_ref[micb_index] == 0)) {
  1931. if (pre_off_event && wcd938x->mbhc)
  1932. blocking_notifier_call_chain(
  1933. &wcd938x->mbhc->notifier,
  1934. pre_off_event,
  1935. &wcd938x->mbhc->wcd_mbhc);
  1936. snd_soc_component_update_bits(component, micb_reg,
  1937. 0xC0, 0x00);
  1938. if (post_off_event && wcd938x->mbhc)
  1939. blocking_notifier_call_chain(
  1940. &wcd938x->mbhc->notifier,
  1941. post_off_event,
  1942. &wcd938x->mbhc->wcd_mbhc);
  1943. }
  1944. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1945. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1946. post_dapm_off,
  1947. &wcd938x->mbhc->wcd_mbhc);
  1948. break;
  1949. };
  1950. dev_dbg(component->dev,
  1951. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1952. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1953. wcd938x->pullup_ref[micb_index]);
  1954. done:
  1955. mutex_unlock(&wcd938x->micb_lock);
  1956. return ret;
  1957. }
  1958. EXPORT_SYMBOL(wcd938x_micbias_control);
  1959. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1960. {
  1961. int ret = 0;
  1962. uint8_t devnum = 0;
  1963. int num_retry = NUM_ATTEMPTS;
  1964. do {
  1965. /* retry after 1ms */
  1966. usleep_range(1000, 1010);
  1967. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1968. } while (ret && --num_retry);
  1969. if (ret)
  1970. dev_err(&swr_dev->dev,
  1971. "%s get devnum %d for dev addr %llx failed\n",
  1972. __func__, devnum, swr_dev->addr);
  1973. swr_dev->dev_num = devnum;
  1974. return 0;
  1975. }
  1976. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1977. struct wcd_mbhc_config *mbhc_cfg)
  1978. {
  1979. if (mbhc_cfg->enable_usbc_analog) {
  1980. if (!(snd_soc_component_read(component, WCD938X_ANA_MBHC_MECH)
  1981. & 0x20))
  1982. return true;
  1983. }
  1984. return false;
  1985. }
  1986. int wcd938x_swr_dmic_register_notifier(struct snd_soc_component *component,
  1987. struct notifier_block *nblock,
  1988. bool enable)
  1989. {
  1990. struct wcd938x_priv *wcd938x_priv;
  1991. if(NULL == component) {
  1992. pr_err("%s: wcd938x component is NULL\n", __func__);
  1993. return -EINVAL;
  1994. }
  1995. wcd938x_priv = snd_soc_component_get_drvdata(component);
  1996. wcd938x_priv->notify_swr_dmic = enable;
  1997. if (enable)
  1998. return blocking_notifier_chain_register(&wcd938x_priv->notifier,
  1999. nblock);
  2000. else
  2001. return blocking_notifier_chain_unregister(
  2002. &wcd938x_priv->notifier, nblock);
  2003. }
  2004. EXPORT_SYMBOL(wcd938x_swr_dmic_register_notifier);
  2005. static int wcd938x_event_notify(struct notifier_block *block,
  2006. unsigned long val,
  2007. void *data)
  2008. {
  2009. u16 event = (val & 0xffff);
  2010. int ret = 0;
  2011. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  2012. struct snd_soc_component *component = wcd938x->component;
  2013. struct wcd_mbhc *mbhc;
  2014. switch (event) {
  2015. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  2016. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  2017. snd_soc_component_update_bits(component,
  2018. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  2019. set_bit(WCD_ADC1_MODE, &wcd938x->status_mask);
  2020. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  2021. }
  2022. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  2023. snd_soc_component_update_bits(component,
  2024. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  2025. set_bit(WCD_ADC2_MODE, &wcd938x->status_mask);
  2026. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  2027. }
  2028. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  2029. snd_soc_component_update_bits(component,
  2030. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  2031. set_bit(WCD_ADC3_MODE, &wcd938x->status_mask);
  2032. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  2033. }
  2034. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  2035. snd_soc_component_update_bits(component,
  2036. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  2037. set_bit(WCD_ADC4_MODE, &wcd938x->status_mask);
  2038. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  2039. }
  2040. break;
  2041. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  2042. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  2043. 0xC0, 0x00);
  2044. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  2045. 0x80, 0x00);
  2046. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  2047. 0x80, 0x00);
  2048. break;
  2049. case BOLERO_SLV_EVT_SSR_DOWN:
  2050. wcd938x->dev_up = false;
  2051. if(wcd938x->notify_swr_dmic)
  2052. blocking_notifier_call_chain(&wcd938x->notifier,
  2053. WCD938X_EVT_SSR_DOWN,
  2054. NULL);
  2055. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = true;
  2056. mbhc = &wcd938x->mbhc->wcd_mbhc;
  2057. wcd938x->usbc_hs_status = get_usbc_hs_status(component,
  2058. mbhc->mbhc_cfg);
  2059. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  2060. wcd938x_reset_low(wcd938x->dev);
  2061. break;
  2062. case BOLERO_SLV_EVT_SSR_UP:
  2063. wcd938x_reset(wcd938x->dev);
  2064. /* allow reset to take effect */
  2065. usleep_range(10000, 10010);
  2066. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  2067. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  2068. wcd938x_init_reg(component);
  2069. regcache_mark_dirty(wcd938x->regmap);
  2070. regcache_sync(wcd938x->regmap);
  2071. /* Initialize MBHC module */
  2072. mbhc = &wcd938x->mbhc->wcd_mbhc;
  2073. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  2074. if (ret) {
  2075. dev_err(component->dev, "%s: mbhc initialization failed\n",
  2076. __func__);
  2077. } else {
  2078. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  2079. }
  2080. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = false;
  2081. wcd938x->dev_up = true;
  2082. if(wcd938x->notify_swr_dmic)
  2083. blocking_notifier_call_chain(&wcd938x->notifier,
  2084. WCD938X_EVT_SSR_UP,
  2085. NULL);
  2086. if (wcd938x->usbc_hs_status)
  2087. mdelay(500);
  2088. break;
  2089. case BOLERO_SLV_EVT_CLK_NOTIFY:
  2090. snd_soc_component_update_bits(component,
  2091. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  2092. ((val >> 0x10) << 0x01));
  2093. break;
  2094. default:
  2095. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  2096. break;
  2097. }
  2098. return 0;
  2099. }
  2100. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2101. int event)
  2102. {
  2103. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2104. int micb_num;
  2105. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  2106. __func__, w->name, event);
  2107. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  2108. micb_num = MIC_BIAS_1;
  2109. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  2110. micb_num = MIC_BIAS_2;
  2111. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  2112. micb_num = MIC_BIAS_3;
  2113. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  2114. micb_num = MIC_BIAS_4;
  2115. else
  2116. return -EINVAL;
  2117. switch (event) {
  2118. case SND_SOC_DAPM_PRE_PMU:
  2119. wcd938x_micbias_control(component, micb_num,
  2120. MICB_ENABLE, true);
  2121. break;
  2122. case SND_SOC_DAPM_POST_PMU:
  2123. /* 1 msec delay as per HW requirement */
  2124. usleep_range(1000, 1100);
  2125. break;
  2126. case SND_SOC_DAPM_POST_PMD:
  2127. wcd938x_micbias_control(component, micb_num,
  2128. MICB_DISABLE, true);
  2129. break;
  2130. };
  2131. return 0;
  2132. }
  2133. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2134. struct snd_kcontrol *kcontrol,
  2135. int event)
  2136. {
  2137. return __wcd938x_codec_enable_micbias(w, event);
  2138. }
  2139. static int __wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2140. int event)
  2141. {
  2142. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2143. int micb_num;
  2144. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  2145. __func__, w->name, event);
  2146. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  2147. micb_num = MIC_BIAS_1;
  2148. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  2149. micb_num = MIC_BIAS_2;
  2150. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  2151. micb_num = MIC_BIAS_3;
  2152. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  2153. micb_num = MIC_BIAS_4;
  2154. else
  2155. return -EINVAL;
  2156. switch (event) {
  2157. case SND_SOC_DAPM_PRE_PMU:
  2158. wcd938x_micbias_control(component, micb_num,
  2159. MICB_PULLUP_ENABLE, true);
  2160. break;
  2161. case SND_SOC_DAPM_POST_PMU:
  2162. /* 1 msec delay as per HW requirement */
  2163. usleep_range(1000, 1100);
  2164. break;
  2165. case SND_SOC_DAPM_POST_PMD:
  2166. wcd938x_micbias_control(component, micb_num,
  2167. MICB_PULLUP_DISABLE, true);
  2168. break;
  2169. };
  2170. return 0;
  2171. }
  2172. static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2173. struct snd_kcontrol *kcontrol,
  2174. int event)
  2175. {
  2176. return __wcd938x_codec_enable_micbias_pullup(w, event);
  2177. }
  2178. static int wcd938x_wakeup(void *handle, bool enable)
  2179. {
  2180. struct wcd938x_priv *priv;
  2181. int ret = 0;
  2182. if (!handle) {
  2183. pr_err("%s: NULL handle\n", __func__);
  2184. return -EINVAL;
  2185. }
  2186. priv = (struct wcd938x_priv *)handle;
  2187. if (!priv->tx_swr_dev) {
  2188. pr_err("%s: tx swr dev is NULL\n", __func__);
  2189. return -EINVAL;
  2190. }
  2191. mutex_lock(&priv->wakeup_lock);
  2192. if (enable)
  2193. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2194. else
  2195. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2196. mutex_unlock(&priv->wakeup_lock);
  2197. return ret;
  2198. }
  2199. static int wcd938x_codec_force_enable_micbias(struct snd_soc_dapm_widget *w,
  2200. struct snd_kcontrol *kcontrol,
  2201. int event)
  2202. {
  2203. int ret = 0;
  2204. struct snd_soc_component *component =
  2205. snd_soc_dapm_to_component(w->dapm);
  2206. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2207. switch (event) {
  2208. case SND_SOC_DAPM_PRE_PMU:
  2209. wcd938x_wakeup(wcd938x, true);
  2210. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_PRE_PMU);
  2211. wcd938x_wakeup(wcd938x, false);
  2212. break;
  2213. case SND_SOC_DAPM_POST_PMD:
  2214. wcd938x_wakeup(wcd938x, true);
  2215. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_POST_PMD);
  2216. wcd938x_wakeup(wcd938x, false);
  2217. break;
  2218. }
  2219. return ret;
  2220. }
  2221. static int wcd938x_enable_micbias(struct wcd938x_priv *wcd938x,
  2222. int micb_num, int req)
  2223. {
  2224. int micb_index = micb_num - 1;
  2225. u16 micb_reg;
  2226. if (NULL == wcd938x) {
  2227. pr_err("%s: wcd938x private data is NULL\n", __func__);
  2228. return -EINVAL;
  2229. }
  2230. switch (micb_num) {
  2231. case MIC_BIAS_1:
  2232. micb_reg = WCD938X_ANA_MICB1;
  2233. break;
  2234. case MIC_BIAS_2:
  2235. micb_reg = WCD938X_ANA_MICB2;
  2236. break;
  2237. case MIC_BIAS_3:
  2238. micb_reg = WCD938X_ANA_MICB3;
  2239. break;
  2240. case MIC_BIAS_4:
  2241. micb_reg = WCD938X_ANA_MICB4;
  2242. break;
  2243. default:
  2244. pr_err("%s: Invalid micbias number: %d\n", __func__, micb_num);
  2245. return -EINVAL;
  2246. };
  2247. pr_debug("%s: req: %d micb_num: %d micb_ref: %d pullup_ref: %d\n",
  2248. __func__, req, micb_num, wcd938x->micb_ref[micb_index],
  2249. wcd938x->pullup_ref[micb_index]);
  2250. mutex_lock(&wcd938x->micb_lock);
  2251. switch (req) {
  2252. case MICB_ENABLE:
  2253. wcd938x->micb_ref[micb_index]++;
  2254. if (wcd938x->micb_ref[micb_index] == 1) {
  2255. regmap_update_bits(wcd938x->regmap,
  2256. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  2257. regmap_update_bits(wcd938x->regmap,
  2258. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  2259. regmap_update_bits(wcd938x->regmap,
  2260. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  2261. regmap_update_bits(wcd938x->regmap,
  2262. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  2263. regmap_update_bits(wcd938x->regmap,
  2264. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  2265. regmap_update_bits(wcd938x->regmap,
  2266. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  2267. regmap_update_bits(wcd938x->regmap,
  2268. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  2269. regmap_update_bits(wcd938x->regmap,
  2270. micb_reg, 0xC0, 0x40);
  2271. regmap_update_bits(wcd938x->regmap, micb_reg, 0x3F, 0x10);
  2272. }
  2273. break;
  2274. case MICB_PULLUP_ENABLE:
  2275. wcd938x->pullup_ref[micb_index]++;
  2276. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  2277. (wcd938x->micb_ref[micb_index] == 0))
  2278. regmap_update_bits(wcd938x->regmap, micb_reg,
  2279. 0xC0, 0x80);
  2280. break;
  2281. case MICB_PULLUP_DISABLE:
  2282. if (wcd938x->pullup_ref[micb_index] > 0)
  2283. wcd938x->pullup_ref[micb_index]--;
  2284. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  2285. (wcd938x->micb_ref[micb_index] == 0))
  2286. regmap_update_bits(wcd938x->regmap, micb_reg,
  2287. 0xC0, 0x00);
  2288. break;
  2289. case MICB_DISABLE:
  2290. if (wcd938x->micb_ref[micb_index] > 0)
  2291. wcd938x->micb_ref[micb_index]--;
  2292. if ((wcd938x->micb_ref[micb_index] == 0) &&
  2293. (wcd938x->pullup_ref[micb_index] > 0))
  2294. regmap_update_bits(wcd938x->regmap, micb_reg,
  2295. 0xC0, 0x80);
  2296. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  2297. (wcd938x->pullup_ref[micb_index] == 0))
  2298. regmap_update_bits(wcd938x->regmap, micb_reg,
  2299. 0xC0, 0x00);
  2300. break;
  2301. };
  2302. mutex_unlock(&wcd938x->micb_lock);
  2303. return 0;
  2304. }
  2305. int wcd938x_codec_force_enable_micbias_v2(struct snd_soc_component *component,
  2306. int event, int micb_num)
  2307. {
  2308. struct wcd938x_priv *wcd938x_priv = NULL;
  2309. int ret = 0;
  2310. int micb_index = micb_num - 1;
  2311. if(NULL == component) {
  2312. pr_err("%s: wcd938x component is NULL\n", __func__);
  2313. return -EINVAL;
  2314. }
  2315. if(event != SND_SOC_DAPM_PRE_PMU && event != SND_SOC_DAPM_POST_PMD) {
  2316. pr_err("%s: invalid event: %d\n", __func__, event);
  2317. return -EINVAL;
  2318. }
  2319. if(micb_num < MIC_BIAS_1 || micb_num > MIC_BIAS_4) {
  2320. pr_err("%s: invalid mic bias num: %d\n", __func__, micb_num);
  2321. return -EINVAL;
  2322. }
  2323. wcd938x_priv = snd_soc_component_get_drvdata(component);
  2324. if (!wcd938x_priv->dev_up) {
  2325. if ((wcd938x_priv->pullup_ref[micb_index] > 0) &&
  2326. (event == SND_SOC_DAPM_POST_PMD)) {
  2327. wcd938x_priv->pullup_ref[micb_index]--;
  2328. ret = -ENODEV;
  2329. goto done;
  2330. }
  2331. }
  2332. switch (event) {
  2333. case SND_SOC_DAPM_PRE_PMU:
  2334. wcd938x_wakeup(wcd938x_priv, true);
  2335. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_ENABLE);
  2336. wcd938x_wakeup(wcd938x_priv, false);
  2337. break;
  2338. case SND_SOC_DAPM_POST_PMD:
  2339. wcd938x_wakeup(wcd938x_priv, true);
  2340. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_DISABLE);
  2341. wcd938x_wakeup(wcd938x_priv, false);
  2342. break;
  2343. }
  2344. done:
  2345. return ret;
  2346. }
  2347. EXPORT_SYMBOL(wcd938x_codec_force_enable_micbias_v2);
  2348. static inline int wcd938x_tx_path_get(const char *wname,
  2349. unsigned int *path_num)
  2350. {
  2351. int ret = 0;
  2352. char *widget_name = NULL;
  2353. char *w_name = NULL;
  2354. char *path_num_char = NULL;
  2355. char *path_name = NULL;
  2356. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2357. if (!widget_name)
  2358. return -EINVAL;
  2359. w_name = widget_name;
  2360. path_name = strsep(&widget_name, " ");
  2361. if (!path_name) {
  2362. pr_err("%s: Invalid widget name = %s\n",
  2363. __func__, widget_name);
  2364. ret = -EINVAL;
  2365. goto err;
  2366. }
  2367. path_num_char = strpbrk(path_name, "0123");
  2368. if (!path_num_char) {
  2369. pr_err("%s: tx path index not found\n",
  2370. __func__);
  2371. ret = -EINVAL;
  2372. goto err;
  2373. }
  2374. ret = kstrtouint(path_num_char, 10, path_num);
  2375. if (ret < 0)
  2376. pr_err("%s: Invalid tx path = %s\n",
  2377. __func__, w_name);
  2378. err:
  2379. kfree(w_name);
  2380. return ret;
  2381. }
  2382. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  2383. struct snd_ctl_elem_value *ucontrol)
  2384. {
  2385. struct snd_soc_component *component =
  2386. snd_soc_kcontrol_component(kcontrol);
  2387. struct wcd938x_priv *wcd938x = NULL;
  2388. int ret = 0;
  2389. unsigned int path = 0;
  2390. if (!component)
  2391. return -EINVAL;
  2392. wcd938x = snd_soc_component_get_drvdata(component);
  2393. if (!wcd938x)
  2394. return -EINVAL;
  2395. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2396. if (ret < 0)
  2397. return ret;
  2398. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  2399. return 0;
  2400. }
  2401. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  2402. struct snd_ctl_elem_value *ucontrol)
  2403. {
  2404. struct snd_soc_component *component =
  2405. snd_soc_kcontrol_component(kcontrol);
  2406. struct wcd938x_priv *wcd938x = NULL;
  2407. u32 mode_val;
  2408. unsigned int path = 0;
  2409. int ret = 0;
  2410. if (!component)
  2411. return -EINVAL;
  2412. wcd938x = snd_soc_component_get_drvdata(component);
  2413. if (!wcd938x)
  2414. return -EINVAL;
  2415. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2416. if (ret)
  2417. return ret;
  2418. mode_val = ucontrol->value.enumerated.item[0];
  2419. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2420. wcd938x->tx_mode[path] = mode_val;
  2421. return 0;
  2422. }
  2423. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2424. struct snd_ctl_elem_value *ucontrol)
  2425. {
  2426. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2427. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2428. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  2429. return 0;
  2430. }
  2431. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2432. struct snd_ctl_elem_value *ucontrol)
  2433. {
  2434. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2435. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2436. u32 mode_val;
  2437. mode_val = ucontrol->value.enumerated.item[0];
  2438. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2439. if (wcd938x->variant == WCD9380) {
  2440. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  2441. dev_info(component->dev,
  2442. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  2443. __func__);
  2444. mode_val = CLS_H_ULP;
  2445. }
  2446. }
  2447. if (mode_val == CLS_H_NORMAL) {
  2448. dev_info(component->dev,
  2449. "%s:Invalid HPH Mode, default to class_AB\n",
  2450. __func__);
  2451. mode_val = CLS_H_ULP;
  2452. }
  2453. wcd938x->hph_mode = mode_val;
  2454. return 0;
  2455. }
  2456. static int wcd938x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  2457. struct snd_ctl_elem_value *ucontrol)
  2458. {
  2459. u8 ear_pa_gain = 0;
  2460. struct snd_soc_component *component =
  2461. snd_soc_kcontrol_component(kcontrol);
  2462. ear_pa_gain = snd_soc_component_read(component,
  2463. WCD938X_ANA_EAR_COMPANDER_CTL);
  2464. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  2465. ucontrol->value.integer.value[0] = ear_pa_gain;
  2466. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  2467. ear_pa_gain);
  2468. return 0;
  2469. }
  2470. static int wcd938x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  2471. struct snd_ctl_elem_value *ucontrol)
  2472. {
  2473. u8 ear_pa_gain = 0;
  2474. struct snd_soc_component *component =
  2475. snd_soc_kcontrol_component(kcontrol);
  2476. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2477. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2478. __func__, ucontrol->value.integer.value[0]);
  2479. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  2480. if (!wcd938x->comp1_enable) {
  2481. snd_soc_component_update_bits(component,
  2482. WCD938X_ANA_EAR_COMPANDER_CTL,
  2483. 0x7C, ear_pa_gain);
  2484. }
  2485. return 0;
  2486. }
  2487. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  2488. struct snd_ctl_elem_value *ucontrol)
  2489. {
  2490. struct snd_soc_component *component =
  2491. snd_soc_kcontrol_component(kcontrol);
  2492. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2493. bool hphr;
  2494. struct soc_multi_mixer_control *mc;
  2495. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2496. hphr = mc->shift;
  2497. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  2498. wcd938x->comp1_enable;
  2499. return 0;
  2500. }
  2501. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  2502. struct snd_ctl_elem_value *ucontrol)
  2503. {
  2504. struct snd_soc_component *component =
  2505. snd_soc_kcontrol_component(kcontrol);
  2506. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2507. int value = ucontrol->value.integer.value[0];
  2508. bool hphr;
  2509. struct soc_multi_mixer_control *mc;
  2510. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2511. hphr = mc->shift;
  2512. if (hphr)
  2513. wcd938x->comp2_enable = value;
  2514. else
  2515. wcd938x->comp1_enable = value;
  2516. return 0;
  2517. }
  2518. static int wcd938x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  2519. struct snd_kcontrol *kcontrol,
  2520. int event)
  2521. {
  2522. struct snd_soc_component *component =
  2523. snd_soc_dapm_to_component(w->dapm);
  2524. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2525. struct wcd938x_pdata *pdata = NULL;
  2526. int ret = 0;
  2527. pdata = dev_get_platdata(wcd938x->dev);
  2528. if (!pdata) {
  2529. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  2530. return -EINVAL;
  2531. }
  2532. if (!msm_cdc_is_ondemand_supply(wcd938x->dev,
  2533. wcd938x->supplies,
  2534. pdata->regulator,
  2535. pdata->num_supplies,
  2536. "cdc-vdd-buck"))
  2537. return 0;
  2538. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2539. w->name, event);
  2540. switch (event) {
  2541. case SND_SOC_DAPM_PRE_PMU:
  2542. if (test_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask)) {
  2543. dev_dbg(component->dev,
  2544. "%s: buck already in enabled state\n",
  2545. __func__);
  2546. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2547. return 0;
  2548. }
  2549. ret = msm_cdc_enable_ondemand_supply(wcd938x->dev,
  2550. wcd938x->supplies,
  2551. pdata->regulator,
  2552. pdata->num_supplies,
  2553. "cdc-vdd-buck");
  2554. if (ret == -EINVAL) {
  2555. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  2556. __func__);
  2557. return ret;
  2558. }
  2559. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2560. /*
  2561. * 200us sleep is required after LDO is enabled as per
  2562. * HW requirement
  2563. */
  2564. usleep_range(200, 250);
  2565. break;
  2566. case SND_SOC_DAPM_POST_PMD:
  2567. set_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2568. break;
  2569. }
  2570. return 0;
  2571. }
  2572. static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
  2573. struct snd_ctl_elem_value *ucontrol)
  2574. {
  2575. struct snd_soc_component *component =
  2576. snd_soc_kcontrol_component(kcontrol);
  2577. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2578. ucontrol->value.integer.value[0] = wcd938x->ldoh;
  2579. return 0;
  2580. }
  2581. static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
  2582. struct snd_ctl_elem_value *ucontrol)
  2583. {
  2584. struct snd_soc_component *component =
  2585. snd_soc_kcontrol_component(kcontrol);
  2586. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2587. wcd938x->ldoh = ucontrol->value.integer.value[0];
  2588. return 0;
  2589. }
  2590. const char * const tx_master_ch_text[] = {
  2591. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  2592. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  2593. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  2594. "SWRM_PCM_IN",
  2595. };
  2596. const struct soc_enum tx_master_ch_enum =
  2597. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2598. tx_master_ch_text);
  2599. static void wcd938x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2600. {
  2601. u8 ch_type = 0;
  2602. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2603. ch_type = ADC1;
  2604. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2605. ch_type = ADC2;
  2606. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2607. ch_type = ADC3;
  2608. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2609. ch_type = ADC4;
  2610. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2611. ch_type = DMIC0;
  2612. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2613. ch_type = DMIC1;
  2614. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2615. ch_type = MBHC;
  2616. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2617. ch_type = DMIC2;
  2618. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2619. ch_type = DMIC3;
  2620. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2621. ch_type = DMIC4;
  2622. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2623. ch_type = DMIC5;
  2624. else if (strnstr(wname, "DMIC6", sizeof("DMIC6")))
  2625. ch_type = DMIC6;
  2626. else if (strnstr(wname, "DMIC7", sizeof("DMIC7")))
  2627. ch_type = DMIC7;
  2628. else
  2629. pr_err("%s: port name: %s is not listed\n", __func__, wname);
  2630. if (ch_type)
  2631. *ch_idx = wcd938x_slave_get_slave_ch_val(ch_type);
  2632. else
  2633. *ch_idx = -EINVAL;
  2634. }
  2635. static int wcd938x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2636. struct snd_ctl_elem_value *ucontrol)
  2637. {
  2638. struct snd_soc_component *component =
  2639. snd_soc_kcontrol_component(kcontrol);
  2640. struct wcd938x_priv *wcd938x = NULL;
  2641. int slave_ch_idx = -EINVAL;
  2642. if (component == NULL)
  2643. return -EINVAL;
  2644. wcd938x = snd_soc_component_get_drvdata(component);
  2645. if (wcd938x == NULL)
  2646. return -EINVAL;
  2647. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2648. if (slave_ch_idx < 0 || slave_ch_idx >= WCD938X_MAX_SLAVE_CH_TYPES)
  2649. return -EINVAL;
  2650. ucontrol->value.integer.value[0] = wcd938x_slave_get_master_ch_val(
  2651. wcd938x->tx_master_ch_map[slave_ch_idx]);
  2652. return 0;
  2653. }
  2654. static int wcd938x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2655. struct snd_ctl_elem_value *ucontrol)
  2656. {
  2657. struct snd_soc_component *component =
  2658. snd_soc_kcontrol_component(kcontrol);
  2659. struct wcd938x_priv *wcd938x = NULL;
  2660. int slave_ch_idx = -EINVAL;
  2661. if (component == NULL)
  2662. return -EINVAL;
  2663. wcd938x = snd_soc_component_get_drvdata(component);
  2664. if (wcd938x == NULL)
  2665. return -EINVAL;
  2666. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2667. if (slave_ch_idx < 0 || slave_ch_idx >= WCD938X_MAX_SLAVE_CH_TYPES)
  2668. return -EINVAL;
  2669. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2670. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2671. __func__, ucontrol->value.enumerated.item[0]);
  2672. wcd938x->tx_master_ch_map[slave_ch_idx] = wcd938x_slave_get_master_ch(
  2673. ucontrol->value.enumerated.item[0]);
  2674. return 0;
  2675. }
  2676. static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol,
  2677. struct snd_ctl_elem_value *ucontrol)
  2678. {
  2679. struct snd_soc_component *component =
  2680. snd_soc_kcontrol_component(kcontrol);
  2681. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2682. ucontrol->value.integer.value[0] = wcd938x->bcs_dis;
  2683. return 0;
  2684. }
  2685. static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol,
  2686. struct snd_ctl_elem_value *ucontrol)
  2687. {
  2688. struct snd_soc_component *component =
  2689. snd_soc_kcontrol_component(kcontrol);
  2690. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2691. wcd938x->bcs_dis = ucontrol->value.integer.value[0];
  2692. return 0;
  2693. }
  2694. static const char * const tx_mode_mux_text_wcd9380[] = {
  2695. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2696. };
  2697. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  2698. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  2699. tx_mode_mux_text_wcd9380);
  2700. static const char * const tx_mode_mux_text[] = {
  2701. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2702. "ADC_ULP1", "ADC_ULP2",
  2703. };
  2704. static const struct soc_enum tx_mode_mux_enum =
  2705. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2706. tx_mode_mux_text);
  2707. static const char * const rx_hph_mode_mux_text_wcd9380[] = {
  2708. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  2709. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  2710. "CLS_AB_LOHIFI",
  2711. };
  2712. static const char * const wcd938x_ear_pa_gain_text[] = {
  2713. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  2714. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  2715. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  2716. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  2717. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  2718. };
  2719. static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
  2720. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
  2721. rx_hph_mode_mux_text_wcd9380);
  2722. static SOC_ENUM_SINGLE_EXT_DECL(wcd938x_ear_pa_gain_enum,
  2723. wcd938x_ear_pa_gain_text);
  2724. static const char * const rx_hph_mode_mux_text[] = {
  2725. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2726. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2727. };
  2728. static const struct soc_enum rx_hph_mode_mux_enum =
  2729. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2730. rx_hph_mode_mux_text);
  2731. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  2732. SOC_ENUM_EXT("EAR PA GAIN", wcd938x_ear_pa_gain_enum,
  2733. wcd938x_ear_pa_gain_get, wcd938x_ear_pa_gain_put),
  2734. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
  2735. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2736. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  2737. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2738. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  2739. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2740. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  2741. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2742. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  2743. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2744. };
  2745. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  2746. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2747. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2748. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2749. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2750. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2751. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2752. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2753. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2754. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  2755. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2756. };
  2757. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  2758. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2759. wcd938x_get_compander, wcd938x_set_compander),
  2760. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2761. wcd938x_get_compander, wcd938x_set_compander),
  2762. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  2763. wcd938x_ldoh_get, wcd938x_ldoh_put),
  2764. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2765. wcd938x_bcs_get, wcd938x_bcs_put),
  2766. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  2767. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  2768. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  2769. analog_gain),
  2770. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  2771. analog_gain),
  2772. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  2773. analog_gain),
  2774. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  2775. analog_gain),
  2776. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2777. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2778. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2779. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2780. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2781. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2782. SOC_ENUM_EXT("ADC4 ChMap", tx_master_ch_enum,
  2783. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2784. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2785. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2786. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2787. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2788. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2789. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2790. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2791. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2792. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2793. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2794. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2795. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2796. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2797. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2798. SOC_ENUM_EXT("DMIC6 ChMap", tx_master_ch_enum,
  2799. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2800. SOC_ENUM_EXT("DMIC7 ChMap", tx_master_ch_enum,
  2801. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2802. };
  2803. static const struct snd_kcontrol_new adc1_switch[] = {
  2804. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2805. };
  2806. static const struct snd_kcontrol_new adc2_switch[] = {
  2807. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2808. };
  2809. static const struct snd_kcontrol_new adc3_switch[] = {
  2810. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2811. };
  2812. static const struct snd_kcontrol_new adc4_switch[] = {
  2813. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2814. };
  2815. static const struct snd_kcontrol_new amic1_switch[] = {
  2816. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2817. };
  2818. static const struct snd_kcontrol_new amic2_switch[] = {
  2819. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2820. };
  2821. static const struct snd_kcontrol_new amic3_switch[] = {
  2822. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2823. };
  2824. static const struct snd_kcontrol_new amic4_switch[] = {
  2825. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2826. };
  2827. static const struct snd_kcontrol_new amic5_switch[] = {
  2828. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2829. };
  2830. static const struct snd_kcontrol_new amic6_switch[] = {
  2831. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2832. };
  2833. static const struct snd_kcontrol_new amic7_switch[] = {
  2834. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2835. };
  2836. static const struct snd_kcontrol_new va_amic1_switch[] = {
  2837. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2838. };
  2839. static const struct snd_kcontrol_new va_amic2_switch[] = {
  2840. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2841. };
  2842. static const struct snd_kcontrol_new va_amic3_switch[] = {
  2843. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2844. };
  2845. static const struct snd_kcontrol_new va_amic4_switch[] = {
  2846. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2847. };
  2848. static const struct snd_kcontrol_new va_amic5_switch[] = {
  2849. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2850. };
  2851. static const struct snd_kcontrol_new va_amic6_switch[] = {
  2852. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2853. };
  2854. static const struct snd_kcontrol_new va_amic7_switch[] = {
  2855. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2856. };
  2857. static const struct snd_kcontrol_new dmic1_switch[] = {
  2858. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2859. };
  2860. static const struct snd_kcontrol_new dmic2_switch[] = {
  2861. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2862. };
  2863. static const struct snd_kcontrol_new dmic3_switch[] = {
  2864. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2865. };
  2866. static const struct snd_kcontrol_new dmic4_switch[] = {
  2867. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2868. };
  2869. static const struct snd_kcontrol_new dmic5_switch[] = {
  2870. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2871. };
  2872. static const struct snd_kcontrol_new dmic6_switch[] = {
  2873. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2874. };
  2875. static const struct snd_kcontrol_new dmic7_switch[] = {
  2876. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2877. };
  2878. static const struct snd_kcontrol_new dmic8_switch[] = {
  2879. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2880. };
  2881. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2882. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2883. };
  2884. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2885. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2886. };
  2887. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2888. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2889. };
  2890. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2891. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2892. };
  2893. static const char * const adc2_mux_text[] = {
  2894. "INP2", "INP3"
  2895. };
  2896. static const struct soc_enum adc2_enum =
  2897. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  2898. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2899. static const struct snd_kcontrol_new tx_adc2_mux =
  2900. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2901. static const char * const adc3_mux_text[] = {
  2902. "INP4", "INP6"
  2903. };
  2904. static const struct soc_enum adc3_enum =
  2905. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  2906. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2907. static const struct snd_kcontrol_new tx_adc3_mux =
  2908. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2909. static const char * const adc4_mux_text[] = {
  2910. "INP5", "INP7"
  2911. };
  2912. static const struct soc_enum adc4_enum =
  2913. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  2914. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  2915. static const struct snd_kcontrol_new tx_adc4_mux =
  2916. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  2917. static const char * const rdac3_mux_text[] = {
  2918. "RX1", "RX3"
  2919. };
  2920. static const char * const hdr12_mux_text[] = {
  2921. "NO_HDR12", "HDR12"
  2922. };
  2923. static const struct soc_enum hdr12_enum =
  2924. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  2925. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  2926. static const struct snd_kcontrol_new tx_hdr12_mux =
  2927. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  2928. static const char * const hdr34_mux_text[] = {
  2929. "NO_HDR34", "HDR34"
  2930. };
  2931. static const struct soc_enum hdr34_enum =
  2932. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  2933. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  2934. static const struct snd_kcontrol_new tx_hdr34_mux =
  2935. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  2936. static const struct soc_enum rdac3_enum =
  2937. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2938. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2939. static const struct snd_kcontrol_new rx_rdac3_mux =
  2940. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2941. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  2942. /*input widgets*/
  2943. SND_SOC_DAPM_INPUT("AMIC1"),
  2944. SND_SOC_DAPM_INPUT("AMIC2"),
  2945. SND_SOC_DAPM_INPUT("AMIC3"),
  2946. SND_SOC_DAPM_INPUT("AMIC4"),
  2947. SND_SOC_DAPM_INPUT("AMIC5"),
  2948. SND_SOC_DAPM_INPUT("AMIC6"),
  2949. SND_SOC_DAPM_INPUT("AMIC7"),
  2950. SND_SOC_DAPM_INPUT("VA AMIC1"),
  2951. SND_SOC_DAPM_INPUT("VA AMIC2"),
  2952. SND_SOC_DAPM_INPUT("VA AMIC3"),
  2953. SND_SOC_DAPM_INPUT("VA AMIC4"),
  2954. SND_SOC_DAPM_INPUT("VA AMIC5"),
  2955. SND_SOC_DAPM_INPUT("VA AMIC6"),
  2956. SND_SOC_DAPM_INPUT("VA AMIC7"),
  2957. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2958. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2959. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2960. /*
  2961. * These dummy widgets are null connected to WCD938x dapm input and
  2962. * output widgets which are not actual path endpoints. This ensures
  2963. * dapm doesnt set these dapm input and output widgets as endpoints.
  2964. */
  2965. SND_SOC_DAPM_INPUT("WCD_TX_DUMMY"),
  2966. SND_SOC_DAPM_OUTPUT("WCD_RX_DUMMY"),
  2967. /*tx widgets*/
  2968. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2969. wcd938x_codec_enable_adc,
  2970. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2971. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2972. wcd938x_codec_enable_adc,
  2973. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2974. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2975. wcd938x_codec_enable_adc,
  2976. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2977. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  2978. wcd938x_codec_enable_adc,
  2979. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2980. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2981. wcd938x_codec_enable_dmic,
  2982. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2983. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2984. wcd938x_codec_enable_dmic,
  2985. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2986. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2987. wcd938x_codec_enable_dmic,
  2988. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2989. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2990. wcd938x_codec_enable_dmic,
  2991. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2992. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2993. wcd938x_codec_enable_dmic,
  2994. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2995. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2996. wcd938x_codec_enable_dmic,
  2997. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2998. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  2999. wcd938x_codec_enable_dmic,
  3000. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3001. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  3002. wcd938x_codec_enable_dmic,
  3003. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3004. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  3005. NULL, 0, wcd938x_enable_req,
  3006. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3007. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  3008. NULL, 0, wcd938x_enable_req,
  3009. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3010. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  3011. NULL, 0, wcd938x_enable_req,
  3012. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3013. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  3014. NULL, 0, wcd938x_enable_req,
  3015. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3016. SND_SOC_DAPM_MIXER_E("AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3017. amic1_switch, ARRAY_SIZE(amic1_switch), NULL,
  3018. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3019. SND_SOC_DAPM_MIXER_E("AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3020. amic2_switch, ARRAY_SIZE(amic2_switch), NULL,
  3021. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3022. SND_SOC_DAPM_MIXER_E("AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3023. amic3_switch, ARRAY_SIZE(amic3_switch), NULL,
  3024. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3025. SND_SOC_DAPM_MIXER_E("AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3026. amic4_switch, ARRAY_SIZE(amic4_switch), NULL,
  3027. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3028. SND_SOC_DAPM_MIXER_E("AMIC5_MIXER", SND_SOC_NOPM, 0, 0,
  3029. amic5_switch, ARRAY_SIZE(amic5_switch), NULL,
  3030. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3031. SND_SOC_DAPM_MIXER_E("AMIC6_MIXER", SND_SOC_NOPM, 0, 0,
  3032. amic6_switch, ARRAY_SIZE(amic6_switch), NULL,
  3033. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3034. SND_SOC_DAPM_MIXER_E("AMIC7_MIXER", SND_SOC_NOPM, 0, 0,
  3035. amic7_switch, ARRAY_SIZE(amic7_switch), NULL,
  3036. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3037. SND_SOC_DAPM_MIXER_E("VA_AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3038. va_amic1_switch, ARRAY_SIZE(va_amic1_switch), NULL,
  3039. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3040. SND_SOC_DAPM_MIXER_E("VA_AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3041. va_amic2_switch, ARRAY_SIZE(va_amic2_switch), NULL,
  3042. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3043. SND_SOC_DAPM_MIXER_E("VA_AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3044. va_amic3_switch, ARRAY_SIZE(va_amic3_switch), NULL,
  3045. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3046. SND_SOC_DAPM_MIXER_E("VA_AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3047. va_amic4_switch, ARRAY_SIZE(va_amic4_switch), NULL,
  3048. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3049. SND_SOC_DAPM_MIXER_E("VA_AMIC5_MIXER", SND_SOC_NOPM, 0, 0,
  3050. va_amic5_switch, ARRAY_SIZE(va_amic5_switch), NULL,
  3051. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3052. SND_SOC_DAPM_MIXER_E("VA_AMIC6_MIXER", SND_SOC_NOPM, 0, 0,
  3053. va_amic6_switch, ARRAY_SIZE(va_amic6_switch), NULL,
  3054. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3055. SND_SOC_DAPM_MIXER_E("VA_AMIC7_MIXER", SND_SOC_NOPM, 0, 0,
  3056. va_amic7_switch, ARRAY_SIZE(va_amic7_switch), NULL,
  3057. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3058. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  3059. &tx_adc2_mux),
  3060. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  3061. &tx_adc3_mux),
  3062. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  3063. &tx_adc4_mux),
  3064. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  3065. &tx_hdr12_mux),
  3066. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  3067. &tx_hdr34_mux),
  3068. /*tx mixers*/
  3069. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, ADC1, 0,
  3070. adc1_switch, ARRAY_SIZE(adc1_switch),
  3071. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3072. SND_SOC_DAPM_POST_PMD),
  3073. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, ADC2, 0,
  3074. adc2_switch, ARRAY_SIZE(adc2_switch),
  3075. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3076. SND_SOC_DAPM_POST_PMD),
  3077. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, ADC3, 0, adc3_switch,
  3078. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  3079. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3080. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, ADC4, 0, adc4_switch,
  3081. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  3082. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3083. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
  3084. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  3085. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3086. SND_SOC_DAPM_POST_PMD),
  3087. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
  3088. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  3089. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3090. SND_SOC_DAPM_POST_PMD),
  3091. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
  3092. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  3093. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3094. SND_SOC_DAPM_POST_PMD),
  3095. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
  3096. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  3097. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3098. SND_SOC_DAPM_POST_PMD),
  3099. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
  3100. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  3101. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3102. SND_SOC_DAPM_POST_PMD),
  3103. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
  3104. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  3105. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3106. SND_SOC_DAPM_POST_PMD),
  3107. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, DMIC7,
  3108. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  3109. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3110. SND_SOC_DAPM_POST_PMD),
  3111. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, DMIC8,
  3112. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  3113. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3114. SND_SOC_DAPM_POST_PMD),
  3115. /* micbias widgets*/
  3116. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3117. wcd938x_codec_enable_micbias,
  3118. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3119. SND_SOC_DAPM_POST_PMD),
  3120. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3121. wcd938x_codec_enable_micbias,
  3122. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3123. SND_SOC_DAPM_POST_PMD),
  3124. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3125. wcd938x_codec_enable_micbias,
  3126. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3127. SND_SOC_DAPM_POST_PMD),
  3128. SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  3129. wcd938x_codec_enable_micbias,
  3130. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3131. SND_SOC_DAPM_POST_PMD),
  3132. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0,
  3133. wcd938x_codec_force_enable_micbias,
  3134. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3135. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS2_STANDALONE, SND_SOC_NOPM, 0, 0,
  3136. wcd938x_codec_force_enable_micbias,
  3137. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3138. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS3_STANDALONE, SND_SOC_NOPM, 0, 0,
  3139. wcd938x_codec_force_enable_micbias,
  3140. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3141. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS4_STANDALONE, SND_SOC_NOPM, 0, 0,
  3142. wcd938x_codec_force_enable_micbias,
  3143. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3144. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  3145. wcd938x_codec_enable_vdd_buck,
  3146. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3147. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  3148. wcd938x_enable_clsh,
  3149. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3150. /*rx widgets*/
  3151. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  3152. wcd938x_codec_enable_ear_pa,
  3153. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3154. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3155. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  3156. wcd938x_codec_enable_aux_pa,
  3157. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3158. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3159. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  3160. wcd938x_codec_enable_hphl_pa,
  3161. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3162. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3163. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  3164. wcd938x_codec_enable_hphr_pa,
  3165. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3166. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3167. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  3168. wcd938x_codec_hphl_dac_event,
  3169. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3170. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3171. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  3172. wcd938x_codec_hphr_dac_event,
  3173. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3174. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3175. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  3176. wcd938x_codec_ear_dac_event,
  3177. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3178. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3179. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  3180. wcd938x_codec_aux_dac_event,
  3181. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3182. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3183. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  3184. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  3185. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  3186. SND_SOC_DAPM_POST_PMD),
  3187. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  3188. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  3189. SND_SOC_DAPM_POST_PMD),
  3190. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  3191. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  3192. SND_SOC_DAPM_POST_PMD),
  3193. /* rx mixer widgets*/
  3194. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  3195. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  3196. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  3197. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  3198. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  3199. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  3200. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  3201. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  3202. /*output widgets tx*/
  3203. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  3204. /*output widgets rx*/
  3205. SND_SOC_DAPM_OUTPUT("EAR"),
  3206. SND_SOC_DAPM_OUTPUT("AUX"),
  3207. SND_SOC_DAPM_OUTPUT("HPHL"),
  3208. SND_SOC_DAPM_OUTPUT("HPHR"),
  3209. /* micbias pull up widgets*/
  3210. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3211. wcd938x_codec_enable_micbias_pullup,
  3212. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3213. SND_SOC_DAPM_POST_PMD),
  3214. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3215. wcd938x_codec_enable_micbias_pullup,
  3216. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3217. SND_SOC_DAPM_POST_PMD),
  3218. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3219. wcd938x_codec_enable_micbias_pullup,
  3220. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3221. SND_SOC_DAPM_POST_PMD),
  3222. SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  3223. wcd938x_codec_enable_micbias_pullup,
  3224. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3225. SND_SOC_DAPM_POST_PMD),
  3226. };
  3227. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  3228. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  3229. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  3230. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  3231. {"ADC1 REQ", NULL, "ADC1"},
  3232. {"ADC1", NULL, "AMIC1_MIXER"},
  3233. {"AMIC1_MIXER", "Switch", "AMIC1"},
  3234. {"AMIC1_MIXER", NULL, "VA_AMIC1_MIXER"},
  3235. {"VA_AMIC1_MIXER", "Switch", "VA AMIC1"},
  3236. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  3237. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  3238. {"ADC2 REQ", NULL, "ADC2"},
  3239. {"ADC2", NULL, "HDR12 MUX"},
  3240. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  3241. {"HDR12 MUX", "HDR12", "AMIC1_MIXER"},
  3242. {"ADC2 MUX", "INP3", "AMIC3_MIXER"},
  3243. {"AMIC3_MIXER", "Switch", "AMIC3"},
  3244. {"AMIC3_MIXER", NULL, "VA_AMIC3_MIXER"},
  3245. {"VA_AMIC3_MIXER", "Switch", "VA AMIC3"},
  3246. {"ADC2 MUX", "INP2", "AMIC2_MIXER"},
  3247. {"AMIC2_MIXER", "Switch", "AMIC2"},
  3248. {"AMIC2_MIXER", NULL, "VA_AMIC2_MIXER"},
  3249. {"VA_AMIC2_MIXER", "Switch", "VA AMIC2"},
  3250. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  3251. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  3252. {"ADC3 REQ", NULL, "ADC3"},
  3253. {"ADC3", NULL, "HDR34 MUX"},
  3254. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  3255. {"HDR34 MUX", "HDR34", "AMIC5_MIXER"},
  3256. {"ADC3 MUX", "INP4", "AMIC4_MIXER"},
  3257. {"AMIC4_MIXER", "Switch", "AMIC4"},
  3258. {"AMIC4_MIXER", NULL, "VA_AMIC4_MIXER"},
  3259. {"VA_AMIC4_MIXER", "Switch", "VA AMIC4"},
  3260. {"ADC3 MUX", "INP6", "AMIC6_MIXER"},
  3261. {"AMIC6_MIXER", "Switch", "AMIC6"},
  3262. {"AMIC6_MIXER", NULL, "VA_AMIC6_MIXER"},
  3263. {"VA_AMIC6_MIXER", "Switch", "VA AMIC6"},
  3264. {"WCD_TX_OUTPUT", NULL, "ADC4_MIXER"},
  3265. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  3266. {"ADC4 REQ", NULL, "ADC4"},
  3267. {"ADC4", NULL, "ADC4 MUX"},
  3268. {"ADC4 MUX", "INP5", "AMIC5_MIXER"},
  3269. {"AMIC5_MIXER", "Switch", "AMIC5"},
  3270. {"AMIC5_MIXER", NULL, "VA_AMIC5_MIXER"},
  3271. {"VA_AMIC5_MIXER", "Switch", "VA AMIC5"},
  3272. {"ADC4 MUX", "INP7", "AMIC7_MIXER"},
  3273. {"AMIC7_MIXER", "Switch", "AMIC7"},
  3274. {"AMIC7_MIXER", NULL, "VA_AMIC7_MIXER"},
  3275. {"VA_AMIC7_MIXER", "Switch", "VA AMIC7"},
  3276. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  3277. {"DMIC1_MIXER", "Switch", "DMIC1"},
  3278. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  3279. {"DMIC2_MIXER", "Switch", "DMIC2"},
  3280. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  3281. {"DMIC3_MIXER", "Switch", "DMIC3"},
  3282. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  3283. {"DMIC4_MIXER", "Switch", "DMIC4"},
  3284. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  3285. {"DMIC5_MIXER", "Switch", "DMIC5"},
  3286. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  3287. {"DMIC6_MIXER", "Switch", "DMIC6"},
  3288. {"WCD_TX_OUTPUT", NULL, "DMIC7_MIXER"},
  3289. {"DMIC7_MIXER", "Switch", "DMIC7"},
  3290. {"WCD_TX_OUTPUT", NULL, "DMIC8_MIXER"},
  3291. {"DMIC8_MIXER", "Switch", "DMIC8"},
  3292. {"IN1_HPHL", NULL, "WCD_RX_DUMMY"},
  3293. {"IN1_HPHL", NULL, "VDD_BUCK"},
  3294. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  3295. {"RX1", NULL, "IN1_HPHL"},
  3296. {"RDAC1", NULL, "RX1"},
  3297. {"HPHL_RDAC", "Switch", "RDAC1"},
  3298. {"HPHL PGA", NULL, "HPHL_RDAC"},
  3299. {"HPHL", NULL, "HPHL PGA"},
  3300. {"IN2_HPHR", NULL, "WCD_RX_DUMMY"},
  3301. {"IN2_HPHR", NULL, "VDD_BUCK"},
  3302. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  3303. {"RX2", NULL, "IN2_HPHR"},
  3304. {"RDAC2", NULL, "RX2"},
  3305. {"HPHR_RDAC", "Switch", "RDAC2"},
  3306. {"HPHR PGA", NULL, "HPHR_RDAC"},
  3307. {"HPHR", NULL, "HPHR PGA"},
  3308. {"IN3_AUX", NULL, "WCD_RX_DUMMY"},
  3309. {"IN3_AUX", NULL, "VDD_BUCK"},
  3310. {"IN3_AUX", NULL, "CLS_H_PORT"},
  3311. {"RX3", NULL, "IN3_AUX"},
  3312. {"RDAC4", NULL, "RX3"},
  3313. {"AUX_RDAC", "Switch", "RDAC4"},
  3314. {"AUX PGA", NULL, "AUX_RDAC"},
  3315. {"AUX", NULL, "AUX PGA"},
  3316. {"RDAC3_MUX", "RX3", "RX3"},
  3317. {"RDAC3_MUX", "RX1", "RX1"},
  3318. {"RDAC3", NULL, "RDAC3_MUX"},
  3319. {"EAR_RDAC", "Switch", "RDAC3"},
  3320. {"EAR PGA", NULL, "EAR_RDAC"},
  3321. {"EAR", NULL, "EAR PGA"},
  3322. };
  3323. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  3324. void *file_private_data,
  3325. struct file *file,
  3326. char __user *buf, size_t count,
  3327. loff_t pos)
  3328. {
  3329. struct wcd938x_priv *priv;
  3330. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  3331. int len = 0;
  3332. priv = (struct wcd938x_priv *) entry->private_data;
  3333. if (!priv) {
  3334. pr_err("%s: wcd938x priv is null\n", __func__);
  3335. return -EINVAL;
  3336. }
  3337. switch (priv->version) {
  3338. case WCD938X_VERSION_1_0:
  3339. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  3340. break;
  3341. default:
  3342. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3343. }
  3344. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3345. }
  3346. static struct snd_info_entry_ops wcd938x_info_ops = {
  3347. .read = wcd938x_version_read,
  3348. };
  3349. static ssize_t wcd938x_variant_read(struct snd_info_entry *entry,
  3350. void *file_private_data,
  3351. struct file *file,
  3352. char __user *buf, size_t count,
  3353. loff_t pos)
  3354. {
  3355. struct wcd938x_priv *priv;
  3356. char buffer[WCD938X_VARIANT_ENTRY_SIZE];
  3357. int len = 0;
  3358. priv = (struct wcd938x_priv *) entry->private_data;
  3359. if (!priv) {
  3360. pr_err("%s: wcd938x priv is null\n", __func__);
  3361. return -EINVAL;
  3362. }
  3363. switch (priv->variant) {
  3364. case WCD9380:
  3365. len = snprintf(buffer, sizeof(buffer), "WCD9380\n");
  3366. break;
  3367. case WCD9385:
  3368. len = snprintf(buffer, sizeof(buffer), "WCD9385\n");
  3369. break;
  3370. default:
  3371. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3372. }
  3373. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3374. }
  3375. static struct snd_info_entry_ops wcd938x_variant_ops = {
  3376. .read = wcd938x_variant_read,
  3377. };
  3378. /*
  3379. * wcd938x_get_codec_variant
  3380. * @component: component instance
  3381. *
  3382. * Return: codec variant or -EINVAL in error.
  3383. */
  3384. int wcd938x_get_codec_variant(struct snd_soc_component *component)
  3385. {
  3386. struct wcd938x_priv *priv = NULL;
  3387. if (!component)
  3388. return -EINVAL;
  3389. priv = snd_soc_component_get_drvdata(component);
  3390. if (!priv) {
  3391. dev_err(component->dev,
  3392. "%s:wcd938x not probed\n", __func__);
  3393. return 0;
  3394. }
  3395. return priv->variant;
  3396. }
  3397. EXPORT_SYMBOL(wcd938x_get_codec_variant);
  3398. /*
  3399. * wcd938x_info_create_codec_entry - creates wcd938x module
  3400. * @codec_root: The parent directory
  3401. * @component: component instance
  3402. *
  3403. * Creates wcd938x module, variant and version entry under the given
  3404. * parent directory.
  3405. *
  3406. * Return: 0 on success or negative error code on failure.
  3407. */
  3408. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  3409. struct snd_soc_component *component)
  3410. {
  3411. struct snd_info_entry *version_entry;
  3412. struct snd_info_entry *variant_entry;
  3413. struct wcd938x_priv *priv;
  3414. struct snd_soc_card *card;
  3415. if (!codec_root || !component)
  3416. return -EINVAL;
  3417. priv = snd_soc_component_get_drvdata(component);
  3418. if (priv->entry) {
  3419. dev_dbg(priv->dev,
  3420. "%s:wcd938x module already created\n", __func__);
  3421. return 0;
  3422. }
  3423. card = component->card;
  3424. priv->entry = snd_info_create_module_entry(codec_root->module,
  3425. "wcd938x", codec_root);
  3426. if (!priv->entry) {
  3427. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  3428. __func__);
  3429. return -ENOMEM;
  3430. }
  3431. priv->entry->mode = S_IFDIR | 0555;
  3432. if (snd_info_register(priv->entry) < 0) {
  3433. snd_info_free_entry(priv->entry);
  3434. return -ENOMEM;
  3435. }
  3436. version_entry = snd_info_create_card_entry(card->snd_card,
  3437. "version",
  3438. priv->entry);
  3439. if (!version_entry) {
  3440. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  3441. __func__);
  3442. snd_info_free_entry(priv->entry);
  3443. return -ENOMEM;
  3444. }
  3445. version_entry->private_data = priv;
  3446. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  3447. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3448. version_entry->c.ops = &wcd938x_info_ops;
  3449. if (snd_info_register(version_entry) < 0) {
  3450. snd_info_free_entry(version_entry);
  3451. snd_info_free_entry(priv->entry);
  3452. return -ENOMEM;
  3453. }
  3454. priv->version_entry = version_entry;
  3455. variant_entry = snd_info_create_card_entry(card->snd_card,
  3456. "variant",
  3457. priv->entry);
  3458. if (!variant_entry) {
  3459. dev_dbg(component->dev, "%s: failed to create wcd938x variant entry\n",
  3460. __func__);
  3461. snd_info_free_entry(version_entry);
  3462. snd_info_free_entry(priv->entry);
  3463. return -ENOMEM;
  3464. }
  3465. variant_entry->private_data = priv;
  3466. variant_entry->size = WCD938X_VARIANT_ENTRY_SIZE;
  3467. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  3468. variant_entry->c.ops = &wcd938x_variant_ops;
  3469. if (snd_info_register(variant_entry) < 0) {
  3470. snd_info_free_entry(variant_entry);
  3471. snd_info_free_entry(version_entry);
  3472. snd_info_free_entry(priv->entry);
  3473. return -ENOMEM;
  3474. }
  3475. priv->variant_entry = variant_entry;
  3476. return 0;
  3477. }
  3478. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  3479. static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x,
  3480. struct wcd938x_pdata *pdata)
  3481. {
  3482. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  3483. int rc = 0;
  3484. if (!pdata) {
  3485. dev_err(wcd938x->dev, "%s: NULL pdata\n", __func__);
  3486. return -ENODEV;
  3487. }
  3488. /* set micbias voltage */
  3489. vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  3490. vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  3491. vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  3492. vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  3493. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  3494. vout_ctl_4 < 0) {
  3495. rc = -EINVAL;
  3496. goto done;
  3497. }
  3498. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 0x3F,
  3499. vout_ctl_1);
  3500. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 0x3F,
  3501. vout_ctl_2);
  3502. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 0x3F,
  3503. vout_ctl_3);
  3504. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 0x3F,
  3505. vout_ctl_4);
  3506. done:
  3507. return rc;
  3508. }
  3509. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  3510. {
  3511. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3512. struct snd_soc_dapm_context *dapm =
  3513. snd_soc_component_get_dapm(component);
  3514. int variant;
  3515. int ret = -EINVAL;
  3516. dev_info(component->dev, "%s()\n", __func__);
  3517. wcd938x = snd_soc_component_get_drvdata(component);
  3518. if (!wcd938x)
  3519. return -EINVAL;
  3520. wcd938x->component = component;
  3521. snd_soc_component_init_regmap(component, wcd938x->regmap);
  3522. variant = (snd_soc_component_read(component,
  3523. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  3524. wcd938x->variant = variant;
  3525. wcd938x->fw_data = devm_kzalloc(component->dev,
  3526. sizeof(*(wcd938x->fw_data)),
  3527. GFP_KERNEL);
  3528. if (!wcd938x->fw_data) {
  3529. dev_err(component->dev, "Failed to allocate fw_data\n");
  3530. ret = -ENOMEM;
  3531. goto err;
  3532. }
  3533. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  3534. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  3535. WCD9XXX_CODEC_HWDEP_NODE, component);
  3536. if (ret < 0) {
  3537. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  3538. goto err_hwdep;
  3539. }
  3540. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  3541. if (ret) {
  3542. pr_err("%s: mbhc initialization failed\n", __func__);
  3543. goto err_hwdep;
  3544. }
  3545. snd_soc_dapm_ignore_suspend(dapm, "WCD938X_AIF Playback");
  3546. snd_soc_dapm_ignore_suspend(dapm, "WCD938X_AIF Capture");
  3547. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3548. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3549. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3550. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3551. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  3552. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  3553. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  3554. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC1");
  3555. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC2");
  3556. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC3");
  3557. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC4");
  3558. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC5");
  3559. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC6");
  3560. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC7");
  3561. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  3562. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3563. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3564. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3565. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3566. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3567. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3568. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3569. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_DUMMY");
  3570. snd_soc_dapm_ignore_suspend(dapm, "WCD_RX_DUMMY");
  3571. snd_soc_dapm_sync(dapm);
  3572. wcd_cls_h_init(&wcd938x->clsh_info);
  3573. wcd938x_init_reg(component);
  3574. if (wcd938x->variant == WCD9380) {
  3575. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  3576. ARRAY_SIZE(wcd9380_snd_controls));
  3577. if (ret < 0) {
  3578. dev_err(component->dev,
  3579. "%s: Failed to add snd ctrls for variant: %d\n",
  3580. __func__, wcd938x->variant);
  3581. goto err_hwdep;
  3582. }
  3583. }
  3584. if (wcd938x->variant == WCD9385) {
  3585. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  3586. ARRAY_SIZE(wcd9385_snd_controls));
  3587. if (ret < 0) {
  3588. dev_err(component->dev,
  3589. "%s: Failed to add snd ctrls for variant: %d\n",
  3590. __func__, wcd938x->variant);
  3591. goto err_hwdep;
  3592. }
  3593. }
  3594. wcd938x->version = WCD938X_VERSION_1_0;
  3595. /* Register event notifier */
  3596. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  3597. if (wcd938x->register_notifier) {
  3598. ret = wcd938x->register_notifier(wcd938x->handle,
  3599. &wcd938x->nblock,
  3600. true);
  3601. if (ret) {
  3602. dev_err(component->dev,
  3603. "%s: Failed to register notifier %d\n",
  3604. __func__, ret);
  3605. return ret;
  3606. }
  3607. }
  3608. return ret;
  3609. err_hwdep:
  3610. wcd938x->fw_data = NULL;
  3611. err:
  3612. return ret;
  3613. }
  3614. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  3615. {
  3616. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3617. if (!wcd938x) {
  3618. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  3619. __func__);
  3620. return;
  3621. }
  3622. if (wcd938x->register_notifier)
  3623. wcd938x->register_notifier(wcd938x->handle,
  3624. &wcd938x->nblock,
  3625. false);
  3626. }
  3627. static int wcd938x_soc_codec_suspend(struct snd_soc_component *component)
  3628. {
  3629. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3630. if (!wcd938x)
  3631. return 0;
  3632. wcd938x->dapm_bias_off = true;
  3633. return 0;
  3634. }
  3635. static int wcd938x_soc_codec_resume(struct snd_soc_component *component)
  3636. {
  3637. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3638. if (!wcd938x)
  3639. return 0;
  3640. wcd938x->dapm_bias_off = false;
  3641. return 0;
  3642. }
  3643. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  3644. .name = WCD938X_DRV_NAME,
  3645. .probe = wcd938x_soc_codec_probe,
  3646. .remove = wcd938x_soc_codec_remove,
  3647. .controls = wcd938x_snd_controls,
  3648. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  3649. .dapm_widgets = wcd938x_dapm_widgets,
  3650. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  3651. .dapm_routes = wcd938x_audio_map,
  3652. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  3653. .suspend = wcd938x_soc_codec_suspend,
  3654. .resume = wcd938x_soc_codec_resume,
  3655. };
  3656. static int wcd938x_reset(struct device *dev)
  3657. {
  3658. struct wcd938x_priv *wcd938x = NULL;
  3659. int rc = 0;
  3660. int value = 0;
  3661. if (!dev)
  3662. return -ENODEV;
  3663. wcd938x = dev_get_drvdata(dev);
  3664. if (!wcd938x)
  3665. return -EINVAL;
  3666. if (!wcd938x->rst_np) {
  3667. dev_err(dev, "%s: reset gpio device node not specified\n",
  3668. __func__);
  3669. return -EINVAL;
  3670. }
  3671. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  3672. if (value > 0)
  3673. return 0;
  3674. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3675. if (rc) {
  3676. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3677. __func__);
  3678. return rc;
  3679. }
  3680. /* 20us sleep required after pulling the reset gpio to LOW */
  3681. usleep_range(20, 30);
  3682. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  3683. if (rc) {
  3684. dev_err(dev, "%s: wcd active state request fail!\n",
  3685. __func__);
  3686. return rc;
  3687. }
  3688. /* 20us sleep required after pulling the reset gpio to HIGH */
  3689. usleep_range(20, 30);
  3690. return rc;
  3691. }
  3692. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  3693. u32 *val)
  3694. {
  3695. int rc = 0;
  3696. rc = of_property_read_u32(dev->of_node, name, val);
  3697. if (rc)
  3698. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3699. __func__, name, dev->of_node->full_name);
  3700. return rc;
  3701. }
  3702. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  3703. struct wcd938x_micbias_setting *mb)
  3704. {
  3705. u32 prop_val = 0;
  3706. int rc = 0;
  3707. /* MB1 */
  3708. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3709. NULL)) {
  3710. rc = wcd938x_read_of_property_u32(dev,
  3711. "qcom,cdc-micbias1-mv",
  3712. &prop_val);
  3713. if (!rc)
  3714. mb->micb1_mv = prop_val;
  3715. } else {
  3716. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3717. __func__);
  3718. }
  3719. /* MB2 */
  3720. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3721. NULL)) {
  3722. rc = wcd938x_read_of_property_u32(dev,
  3723. "qcom,cdc-micbias2-mv",
  3724. &prop_val);
  3725. if (!rc)
  3726. mb->micb2_mv = prop_val;
  3727. } else {
  3728. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3729. __func__);
  3730. }
  3731. /* MB3 */
  3732. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3733. NULL)) {
  3734. rc = wcd938x_read_of_property_u32(dev,
  3735. "qcom,cdc-micbias3-mv",
  3736. &prop_val);
  3737. if (!rc)
  3738. mb->micb3_mv = prop_val;
  3739. } else {
  3740. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3741. __func__);
  3742. }
  3743. /* MB4 */
  3744. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  3745. NULL)) {
  3746. rc = wcd938x_read_of_property_u32(dev,
  3747. "qcom,cdc-micbias4-mv",
  3748. &prop_val);
  3749. if (!rc)
  3750. mb->micb4_mv = prop_val;
  3751. } else {
  3752. dev_info(dev, "%s: Micbias4 DT property not found\n",
  3753. __func__);
  3754. }
  3755. }
  3756. static int wcd938x_reset_low(struct device *dev)
  3757. {
  3758. struct wcd938x_priv *wcd938x = NULL;
  3759. int rc = 0;
  3760. if (!dev)
  3761. return -ENODEV;
  3762. wcd938x = dev_get_drvdata(dev);
  3763. if (!wcd938x)
  3764. return -EINVAL;
  3765. if (!wcd938x->rst_np) {
  3766. dev_err(dev, "%s: reset gpio device node not specified\n",
  3767. __func__);
  3768. return -EINVAL;
  3769. }
  3770. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3771. if (rc) {
  3772. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3773. __func__);
  3774. return rc;
  3775. }
  3776. /* 20us sleep required after pulling the reset gpio to LOW */
  3777. usleep_range(20, 30);
  3778. return rc;
  3779. }
  3780. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  3781. {
  3782. struct wcd938x_pdata *pdata = NULL;
  3783. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  3784. GFP_KERNEL);
  3785. if (!pdata)
  3786. return NULL;
  3787. pdata->rst_np = of_parse_phandle(dev->of_node,
  3788. "qcom,wcd-rst-gpio-node", 0);
  3789. if (!pdata->rst_np) {
  3790. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3791. __func__, "qcom,wcd-rst-gpio-node",
  3792. dev->of_node->full_name);
  3793. return NULL;
  3794. }
  3795. /* Parse power supplies */
  3796. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3797. &pdata->num_supplies);
  3798. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3799. dev_err(dev, "%s: no power supplies defined for codec\n",
  3800. __func__);
  3801. return NULL;
  3802. }
  3803. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3804. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3805. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  3806. return pdata;
  3807. }
  3808. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  3809. {
  3810. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  3811. __func__, irq);
  3812. return IRQ_HANDLED;
  3813. }
  3814. static struct snd_soc_dai_driver wcd938x_dai[] = {
  3815. {
  3816. .name = "wcd938x_cdc",
  3817. .playback = {
  3818. .stream_name = "WCD938X_AIF Playback",
  3819. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3820. .formats = WCD938X_FORMATS,
  3821. .rate_max = 384000,
  3822. .rate_min = 8000,
  3823. .channels_min = 1,
  3824. .channels_max = 4,
  3825. },
  3826. .capture = {
  3827. .stream_name = "WCD938X_AIF Capture",
  3828. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3829. .formats = WCD938X_FORMATS,
  3830. .rate_max = 384000,
  3831. .rate_min = 8000,
  3832. .channels_min = 1,
  3833. .channels_max = 4,
  3834. },
  3835. },
  3836. };
  3837. static int wcd938x_bind(struct device *dev)
  3838. {
  3839. int ret = 0, i = 0;
  3840. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  3841. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3842. /*
  3843. * Add 5msec delay to provide sufficient time for
  3844. * soundwire auto enumeration of slave devices as
  3845. * as per HW requirement.
  3846. */
  3847. usleep_range(5000, 5010);
  3848. ret = component_bind_all(dev, wcd938x);
  3849. if (ret) {
  3850. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3851. __func__, ret);
  3852. return ret;
  3853. }
  3854. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3855. if (!wcd938x->rx_swr_dev) {
  3856. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3857. __func__);
  3858. ret = -ENODEV;
  3859. goto err;
  3860. }
  3861. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3862. if (!wcd938x->tx_swr_dev) {
  3863. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3864. __func__);
  3865. ret = -ENODEV;
  3866. goto err;
  3867. }
  3868. swr_init_port_params(wcd938x->tx_swr_dev, SWR_NUM_PORTS,
  3869. wcd938x->swr_tx_port_params);
  3870. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  3871. &wcd938x_regmap_config);
  3872. if (!wcd938x->regmap) {
  3873. dev_err(dev, "%s: Regmap init failed\n",
  3874. __func__);
  3875. goto err;
  3876. }
  3877. /* Set all interupts as edge triggered */
  3878. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  3879. regmap_write(wcd938x->regmap,
  3880. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  3881. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  3882. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  3883. wcd938x->irq_info.codec_name = "WCD938X";
  3884. wcd938x->irq_info.regmap = wcd938x->regmap;
  3885. wcd938x->irq_info.dev = dev;
  3886. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  3887. if (ret) {
  3888. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  3889. __func__, ret);
  3890. goto err;
  3891. }
  3892. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  3893. ret = wcd938x_set_micbias_data(wcd938x, pdata);
  3894. if (ret < 0) {
  3895. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  3896. goto err_irq;
  3897. }
  3898. /* Request for watchdog interrupt */
  3899. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  3900. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3901. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  3902. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3903. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  3904. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3905. /* Disable watchdog interrupt for HPH and AUX */
  3906. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  3907. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  3908. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  3909. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  3910. wcd938x_dai, ARRAY_SIZE(wcd938x_dai));
  3911. if (ret) {
  3912. dev_err(dev, "%s: Codec registration failed\n",
  3913. __func__);
  3914. goto err_irq;
  3915. }
  3916. wcd938x->dev_up = true;
  3917. return ret;
  3918. err_irq:
  3919. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3920. err:
  3921. component_unbind_all(dev, wcd938x);
  3922. return ret;
  3923. }
  3924. static void wcd938x_unbind(struct device *dev)
  3925. {
  3926. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3927. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT, NULL);
  3928. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT, NULL);
  3929. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT, NULL);
  3930. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3931. snd_soc_unregister_component(dev);
  3932. component_unbind_all(dev, wcd938x);
  3933. }
  3934. static const struct of_device_id wcd938x_dt_match[] = {
  3935. { .compatible = "qcom,wcd938x-codec", .data = "wcd938x"},
  3936. {}
  3937. };
  3938. static const struct component_master_ops wcd938x_comp_ops = {
  3939. .bind = wcd938x_bind,
  3940. .unbind = wcd938x_unbind,
  3941. };
  3942. static int wcd938x_compare_of(struct device *dev, void *data)
  3943. {
  3944. return dev->of_node == data;
  3945. }
  3946. static void wcd938x_release_of(struct device *dev, void *data)
  3947. {
  3948. of_node_put(data);
  3949. }
  3950. static int wcd938x_add_slave_components(struct device *dev,
  3951. struct component_match **matchptr)
  3952. {
  3953. struct device_node *np, *rx_node, *tx_node;
  3954. np = dev->of_node;
  3955. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3956. if (!rx_node) {
  3957. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3958. return -ENODEV;
  3959. }
  3960. of_node_get(rx_node);
  3961. component_match_add_release(dev, matchptr,
  3962. wcd938x_release_of,
  3963. wcd938x_compare_of,
  3964. rx_node);
  3965. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3966. if (!tx_node) {
  3967. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3968. return -ENODEV;
  3969. }
  3970. of_node_get(tx_node);
  3971. component_match_add_release(dev, matchptr,
  3972. wcd938x_release_of,
  3973. wcd938x_compare_of,
  3974. tx_node);
  3975. return 0;
  3976. }
  3977. static int wcd938x_probe(struct platform_device *pdev)
  3978. {
  3979. struct component_match *match = NULL;
  3980. struct wcd938x_priv *wcd938x = NULL;
  3981. struct wcd938x_pdata *pdata = NULL;
  3982. struct wcd_ctrl_platform_data *plat_data = NULL;
  3983. struct device *dev = &pdev->dev;
  3984. int ret;
  3985. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  3986. GFP_KERNEL);
  3987. if (!wcd938x)
  3988. return -ENOMEM;
  3989. dev_set_drvdata(dev, wcd938x);
  3990. wcd938x->dev = dev;
  3991. pdata = wcd938x_populate_dt_data(dev);
  3992. if (!pdata) {
  3993. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3994. return -EINVAL;
  3995. }
  3996. dev->platform_data = pdata;
  3997. wcd938x->rst_np = pdata->rst_np;
  3998. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  3999. pdata->regulator, pdata->num_supplies);
  4000. if (!wcd938x->supplies) {
  4001. dev_err(dev, "%s: Cannot init wcd supplies\n",
  4002. __func__);
  4003. return ret;
  4004. }
  4005. plat_data = dev_get_platdata(dev->parent);
  4006. if (!plat_data) {
  4007. dev_err(dev, "%s: platform data from parent is NULL\n",
  4008. __func__);
  4009. return -EINVAL;
  4010. }
  4011. wcd938x->handle = (void *)plat_data->handle;
  4012. if (!wcd938x->handle) {
  4013. dev_err(dev, "%s: handle is NULL\n", __func__);
  4014. return -EINVAL;
  4015. }
  4016. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  4017. if (!wcd938x->update_wcd_event) {
  4018. dev_err(dev, "%s: update_wcd_event api is null!\n",
  4019. __func__);
  4020. return -EINVAL;
  4021. }
  4022. wcd938x->register_notifier = plat_data->register_notifier;
  4023. if (!wcd938x->register_notifier) {
  4024. dev_err(dev, "%s: register_notifier api is null!\n",
  4025. __func__);
  4026. return -EINVAL;
  4027. }
  4028. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  4029. pdata->regulator,
  4030. pdata->num_supplies);
  4031. if (ret) {
  4032. dev_err(dev, "%s: wcd static supply enable failed!\n",
  4033. __func__);
  4034. return ret;
  4035. }
  4036. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  4037. CODEC_RX);
  4038. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  4039. CODEC_TX);
  4040. if (ret) {
  4041. dev_err(dev, "Failed to read port mapping\n");
  4042. goto err;
  4043. }
  4044. ret = wcd938x_parse_port_params(dev, "qcom,swr-tx-port-params",
  4045. CODEC_TX);
  4046. if (ret) {
  4047. dev_err(dev, "Failed to read port params\n");
  4048. goto err;
  4049. }
  4050. mutex_init(&wcd938x->wakeup_lock);
  4051. mutex_init(&wcd938x->micb_lock);
  4052. ret = wcd938x_add_slave_components(dev, &match);
  4053. if (ret)
  4054. goto err_lock_init;
  4055. wcd938x_reset(dev);
  4056. wcd938x->wakeup = wcd938x_wakeup;
  4057. return component_master_add_with_match(dev,
  4058. &wcd938x_comp_ops, match);
  4059. err_lock_init:
  4060. mutex_destroy(&wcd938x->micb_lock);
  4061. mutex_destroy(&wcd938x->wakeup_lock);
  4062. err:
  4063. return ret;
  4064. }
  4065. static int wcd938x_remove(struct platform_device *pdev)
  4066. {
  4067. struct wcd938x_priv *wcd938x = NULL;
  4068. wcd938x = platform_get_drvdata(pdev);
  4069. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  4070. mutex_destroy(&wcd938x->micb_lock);
  4071. mutex_destroy(&wcd938x->wakeup_lock);
  4072. dev_set_drvdata(&pdev->dev, NULL);
  4073. return 0;
  4074. }
  4075. #ifdef CONFIG_PM_SLEEP
  4076. static int wcd938x_suspend(struct device *dev)
  4077. {
  4078. struct wcd938x_priv *wcd938x = NULL;
  4079. int ret = 0;
  4080. struct wcd938x_pdata *pdata = NULL;
  4081. if (!dev)
  4082. return -ENODEV;
  4083. wcd938x = dev_get_drvdata(dev);
  4084. if (!wcd938x)
  4085. return -EINVAL;
  4086. pdata = dev_get_platdata(wcd938x->dev);
  4087. if (!pdata) {
  4088. dev_err(dev, "%s: pdata is NULL\n", __func__);
  4089. return -EINVAL;
  4090. }
  4091. if (test_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask)) {
  4092. ret = msm_cdc_disable_ondemand_supply(wcd938x->dev,
  4093. wcd938x->supplies,
  4094. pdata->regulator,
  4095. pdata->num_supplies,
  4096. "cdc-vdd-buck");
  4097. if (ret == -EINVAL) {
  4098. dev_err(dev, "%s: vdd buck is not disabled\n",
  4099. __func__);
  4100. return 0;
  4101. }
  4102. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  4103. }
  4104. if (wcd938x->dapm_bias_off) {
  4105. msm_cdc_set_supplies_lpm_mode(wcd938x->dev,
  4106. wcd938x->supplies,
  4107. pdata->regulator,
  4108. pdata->num_supplies,
  4109. true);
  4110. set_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask);
  4111. }
  4112. return 0;
  4113. }
  4114. static int wcd938x_resume(struct device *dev)
  4115. {
  4116. struct wcd938x_priv *wcd938x = NULL;
  4117. struct wcd938x_pdata *pdata = NULL;
  4118. if (!dev)
  4119. return -ENODEV;
  4120. wcd938x = dev_get_drvdata(dev);
  4121. if (!wcd938x)
  4122. return -EINVAL;
  4123. pdata = dev_get_platdata(wcd938x->dev);
  4124. if (!pdata) {
  4125. dev_err(dev, "%s: pdata is NULL\n", __func__);
  4126. return -EINVAL;
  4127. }
  4128. if (test_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask)) {
  4129. msm_cdc_set_supplies_lpm_mode(wcd938x->dev,
  4130. wcd938x->supplies,
  4131. pdata->regulator,
  4132. pdata->num_supplies,
  4133. false);
  4134. clear_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask);
  4135. }
  4136. return 0;
  4137. }
  4138. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  4139. .suspend_late = wcd938x_suspend,
  4140. .resume_early = wcd938x_resume,
  4141. };
  4142. #endif
  4143. static struct platform_driver wcd938x_codec_driver = {
  4144. .probe = wcd938x_probe,
  4145. .remove = wcd938x_remove,
  4146. .driver = {
  4147. .name = "wcd938x_codec",
  4148. .owner = THIS_MODULE,
  4149. .of_match_table = of_match_ptr(wcd938x_dt_match),
  4150. #ifdef CONFIG_PM_SLEEP
  4151. .pm = &wcd938x_dev_pm_ops,
  4152. #endif
  4153. .suppress_bind_attrs = true,
  4154. },
  4155. };
  4156. module_platform_driver(wcd938x_codec_driver);
  4157. MODULE_DESCRIPTION("WCD938X Codec driver");
  4158. MODULE_LICENSE("GPL v2");