dp_be_rx.c 45 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "cdp_txrx_cmn_struct.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_types.h"
  22. #include "dp_rx.h"
  23. #include "dp_tx.h"
  24. #include "dp_be_rx.h"
  25. #include "dp_peer.h"
  26. #include "hal_rx.h"
  27. #include "hal_be_rx.h"
  28. #include "hal_api.h"
  29. #include "hal_be_api.h"
  30. #include "qdf_nbuf.h"
  31. #include "hal_be_rx_tlv.h"
  32. #ifdef MESH_MODE_SUPPORT
  33. #include "if_meta_hdr.h"
  34. #endif
  35. #include "dp_internal.h"
  36. #include "dp_ipa.h"
  37. #ifdef FEATURE_WDS
  38. #include "dp_txrx_wds.h"
  39. #endif
  40. #include "dp_hist.h"
  41. #include "dp_rx_buffer_pool.h"
  42. #ifndef AST_OFFLOAD_ENABLE
  43. static void
  44. dp_rx_wds_learn(struct dp_soc *soc,
  45. struct dp_vdev *vdev,
  46. uint8_t *rx_tlv_hdr,
  47. struct dp_txrx_peer *txrx_peer,
  48. qdf_nbuf_t nbuf,
  49. struct hal_rx_msdu_metadata msdu_metadata)
  50. {
  51. /* WDS Source Port Learning */
  52. if (qdf_likely(vdev->wds_enabled))
  53. dp_rx_wds_srcport_learn(soc,
  54. rx_tlv_hdr,
  55. txrx_peer,
  56. nbuf,
  57. msdu_metadata);
  58. }
  59. #else
  60. #ifdef QCA_SUPPORT_WDS_EXTENDED
  61. /**
  62. * dp_wds_ext_peer_learn_be() - function to send event to control
  63. * path on receiving 1st 4-address frame from backhaul.
  64. * @soc: DP soc
  65. * @ta_txrx_peer: WDS repeater txrx peer
  66. * @rx_tlv_hdr : start address of rx tlvs
  67. * @nbuf: RX packet buffer
  68. *
  69. * Return: void
  70. */
  71. static inline void dp_wds_ext_peer_learn_be(struct dp_soc *soc,
  72. struct dp_txrx_peer *ta_txrx_peer,
  73. uint8_t *rx_tlv_hdr,
  74. qdf_nbuf_t nbuf)
  75. {
  76. uint8_t wds_ext_src_mac[QDF_MAC_ADDR_SIZE];
  77. struct dp_peer *ta_base_peer;
  78. /* instead of checking addr4 is valid or not in per packet path
  79. * check for init bit, which will be set on reception of
  80. * first addr4 valid packet.
  81. */
  82. if (!ta_txrx_peer->vdev->wds_ext_enabled ||
  83. qdf_atomic_test_bit(WDS_EXT_PEER_INIT_BIT,
  84. &ta_txrx_peer->wds_ext.init))
  85. return;
  86. if (qdf_nbuf_is_rx_chfrag_start(nbuf) &&
  87. hal_rx_get_mpdu_mac_ad4_valid_be(rx_tlv_hdr)) {
  88. qdf_atomic_test_and_set_bit(WDS_EXT_PEER_INIT_BIT,
  89. &ta_txrx_peer->wds_ext.init);
  90. ta_base_peer = dp_peer_get_ref_by_id(soc, ta_txrx_peer->peer_id,
  91. DP_MOD_ID_RX);
  92. if (!ta_base_peer)
  93. return;
  94. qdf_mem_copy(wds_ext_src_mac, &ta_base_peer->mac_addr.raw[0],
  95. QDF_MAC_ADDR_SIZE);
  96. dp_peer_unref_delete(ta_base_peer, DP_MOD_ID_RX);
  97. soc->cdp_soc.ol_ops->rx_wds_ext_peer_learn(
  98. soc->ctrl_psoc,
  99. ta_txrx_peer->peer_id,
  100. ta_txrx_peer->vdev->vdev_id,
  101. wds_ext_src_mac);
  102. }
  103. }
  104. #else
  105. static inline void dp_wds_ext_peer_learn_be(struct dp_soc *soc,
  106. struct dp_txrx_peer *ta_txrx_peer,
  107. uint8_t *rx_tlv_hdr,
  108. qdf_nbuf_t nbuf)
  109. {
  110. }
  111. #endif
  112. static void
  113. dp_rx_wds_learn(struct dp_soc *soc,
  114. struct dp_vdev *vdev,
  115. uint8_t *rx_tlv_hdr,
  116. struct dp_txrx_peer *ta_txrx_peer,
  117. qdf_nbuf_t nbuf,
  118. struct hal_rx_msdu_metadata msdu_metadata)
  119. {
  120. dp_wds_ext_peer_learn_be(soc, ta_txrx_peer, rx_tlv_hdr, nbuf);
  121. }
  122. #endif
  123. #if defined(DP_PKT_STATS_PER_LMAC) && defined(WLAN_FEATURE_11BE_MLO)
  124. static inline void
  125. dp_rx_set_msdu_lmac_id(qdf_nbuf_t nbuf, uint32_t peer_mdata)
  126. {
  127. uint8_t lmac_id;
  128. lmac_id = dp_rx_peer_metadata_lmac_id_get_be(peer_mdata);
  129. qdf_nbuf_set_lmac_id(nbuf, lmac_id);
  130. }
  131. #else
  132. static inline void
  133. dp_rx_set_msdu_lmac_id(qdf_nbuf_t nbuf, uint32_t peer_mdata)
  134. {
  135. }
  136. #endif
  137. /**
  138. * dp_rx_process_be() - Brain of the Rx processing functionality
  139. * Called from the bottom half (tasklet/NET_RX_SOFTIRQ)
  140. * @int_ctx: per interrupt context
  141. * @hal_ring: opaque pointer to the HAL Rx Ring, which will be serviced
  142. * @reo_ring_num: ring number (0, 1, 2 or 3) of the reo ring.
  143. * @quota: No. of units (packets) that can be serviced in one shot.
  144. *
  145. * This function implements the core of Rx functionality. This is
  146. * expected to handle only non-error frames.
  147. *
  148. * Return: uint32_t: No. of elements processed
  149. */
  150. uint32_t dp_rx_process_be(struct dp_intr *int_ctx,
  151. hal_ring_handle_t hal_ring_hdl, uint8_t reo_ring_num,
  152. uint32_t quota)
  153. {
  154. hal_ring_desc_t ring_desc;
  155. hal_ring_desc_t last_prefetched_hw_desc;
  156. hal_soc_handle_t hal_soc;
  157. struct dp_rx_desc *rx_desc = NULL;
  158. struct dp_rx_desc *last_prefetched_sw_desc = NULL;
  159. qdf_nbuf_t nbuf, next;
  160. bool near_full;
  161. union dp_rx_desc_list_elem_t *head[WLAN_MAX_MLO_CHIPS][MAX_PDEV_CNT];
  162. union dp_rx_desc_list_elem_t *tail[WLAN_MAX_MLO_CHIPS][MAX_PDEV_CNT];
  163. uint32_t num_pending = 0;
  164. uint32_t rx_bufs_used = 0, rx_buf_cookie;
  165. uint16_t msdu_len = 0;
  166. uint16_t peer_id;
  167. uint8_t vdev_id;
  168. struct dp_txrx_peer *txrx_peer;
  169. dp_txrx_ref_handle txrx_ref_handle = NULL;
  170. struct dp_vdev *vdev;
  171. uint32_t pkt_len = 0;
  172. struct hal_rx_mpdu_desc_info mpdu_desc_info;
  173. struct hal_rx_msdu_desc_info msdu_desc_info;
  174. enum hal_reo_error_status error;
  175. uint32_t peer_mdata;
  176. uint8_t *rx_tlv_hdr;
  177. uint32_t rx_bufs_reaped[WLAN_MAX_MLO_CHIPS][MAX_PDEV_CNT];
  178. uint8_t mac_id = 0;
  179. struct dp_pdev *rx_pdev;
  180. bool enh_flag;
  181. struct dp_srng *dp_rxdma_srng;
  182. struct rx_desc_pool *rx_desc_pool;
  183. struct dp_soc *soc = int_ctx->soc;
  184. struct cdp_tid_rx_stats *tid_stats;
  185. qdf_nbuf_t nbuf_head;
  186. qdf_nbuf_t nbuf_tail;
  187. qdf_nbuf_t deliver_list_head;
  188. qdf_nbuf_t deliver_list_tail;
  189. uint32_t num_rx_bufs_reaped = 0;
  190. uint32_t intr_id;
  191. struct hif_opaque_softc *scn;
  192. int32_t tid = 0;
  193. bool is_prev_msdu_last = true;
  194. uint32_t num_entries_avail = 0;
  195. uint32_t rx_ol_pkt_cnt = 0;
  196. uint32_t num_entries = 0;
  197. struct hal_rx_msdu_metadata msdu_metadata;
  198. QDF_STATUS status;
  199. qdf_nbuf_t ebuf_head;
  200. qdf_nbuf_t ebuf_tail;
  201. uint8_t pkt_capture_offload = 0;
  202. struct dp_srng *rx_ring = &soc->reo_dest_ring[reo_ring_num];
  203. int max_reap_limit, ring_near_full;
  204. struct dp_soc *replenish_soc;
  205. uint8_t chip_id;
  206. uint64_t current_time = 0;
  207. uint32_t old_tid;
  208. uint32_t peer_ext_stats;
  209. uint32_t dsf;
  210. DP_HIST_INIT();
  211. qdf_assert_always(soc && hal_ring_hdl);
  212. hal_soc = soc->hal_soc;
  213. qdf_assert_always(hal_soc);
  214. scn = soc->hif_handle;
  215. intr_id = int_ctx->dp_intr_id;
  216. num_entries = hal_srng_get_num_entries(hal_soc, hal_ring_hdl);
  217. dp_runtime_pm_mark_last_busy(soc);
  218. more_data:
  219. /* reset local variables here to be re-used in the function */
  220. nbuf_head = NULL;
  221. nbuf_tail = NULL;
  222. deliver_list_head = NULL;
  223. deliver_list_tail = NULL;
  224. txrx_peer = NULL;
  225. vdev = NULL;
  226. num_rx_bufs_reaped = 0;
  227. ebuf_head = NULL;
  228. ebuf_tail = NULL;
  229. ring_near_full = 0;
  230. max_reap_limit = dp_rx_get_loop_pkt_limit(soc);
  231. qdf_mem_zero(rx_bufs_reaped, sizeof(rx_bufs_reaped));
  232. qdf_mem_zero(&mpdu_desc_info, sizeof(mpdu_desc_info));
  233. qdf_mem_zero(&msdu_desc_info, sizeof(msdu_desc_info));
  234. qdf_mem_zero(head, sizeof(head));
  235. qdf_mem_zero(tail, sizeof(tail));
  236. old_tid = 0xff;
  237. dsf = 0;
  238. peer_ext_stats = 0;
  239. rx_pdev = NULL;
  240. tid_stats = NULL;
  241. dp_pkt_get_timestamp(&current_time);
  242. ring_near_full = _dp_srng_test_and_update_nf_params(soc, rx_ring,
  243. &max_reap_limit);
  244. peer_ext_stats = wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx);
  245. if (qdf_unlikely(dp_rx_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  246. /*
  247. * Need API to convert from hal_ring pointer to
  248. * Ring Type / Ring Id combo
  249. */
  250. DP_STATS_INC(soc, rx.err.hal_ring_access_fail, 1);
  251. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  252. FL("HAL RING Access Failed -- %pK"), hal_ring_hdl);
  253. goto done;
  254. }
  255. hal_srng_update_ring_usage_wm_no_lock(soc->hal_soc, hal_ring_hdl);
  256. if (!num_pending)
  257. num_pending = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, 0);
  258. if (num_pending > quota)
  259. num_pending = quota;
  260. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_pending);
  261. last_prefetched_hw_desc = dp_srng_dst_prefetch_32_byte_desc(hal_soc,
  262. hal_ring_hdl,
  263. num_pending);
  264. /*
  265. * start reaping the buffers from reo ring and queue
  266. * them in per vdev queue.
  267. * Process the received pkts in a different per vdev loop.
  268. */
  269. while (qdf_likely(num_pending)) {
  270. ring_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  271. if (qdf_unlikely(!ring_desc))
  272. break;
  273. error = HAL_RX_ERROR_STATUS_GET(ring_desc);
  274. if (qdf_unlikely(error == HAL_REO_ERROR_DETECTED)) {
  275. dp_rx_err("%pK: HAL RING 0x%pK:error %d",
  276. soc, hal_ring_hdl, error);
  277. DP_STATS_INC(soc, rx.err.hal_reo_error[reo_ring_num],
  278. 1);
  279. /* Don't know how to deal with this -- assert */
  280. qdf_assert(0);
  281. }
  282. dp_rx_ring_record_entry(soc, reo_ring_num, ring_desc);
  283. rx_buf_cookie = HAL_RX_REO_BUF_COOKIE_GET(ring_desc);
  284. status = dp_rx_cookie_check_and_invalidate(ring_desc);
  285. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  286. DP_STATS_INC(soc, rx.err.stale_cookie, 1);
  287. break;
  288. }
  289. rx_desc = (struct dp_rx_desc *)
  290. hal_rx_get_reo_desc_va(ring_desc);
  291. dp_rx_desc_sw_cc_check(soc, rx_buf_cookie, &rx_desc);
  292. status = dp_rx_desc_sanity(soc, hal_soc, hal_ring_hdl,
  293. ring_desc, rx_desc);
  294. if (QDF_IS_STATUS_ERROR(status)) {
  295. if (qdf_unlikely(rx_desc && rx_desc->nbuf)) {
  296. qdf_assert_always(!rx_desc->unmapped);
  297. dp_rx_nbuf_unmap(soc, rx_desc, reo_ring_num);
  298. rx_desc->unmapped = 1;
  299. dp_rx_buffer_pool_nbuf_free(soc, rx_desc->nbuf,
  300. rx_desc->pool_id);
  301. dp_rx_add_to_free_desc_list(
  302. &head[rx_desc->chip_id][rx_desc->pool_id],
  303. &tail[rx_desc->chip_id][rx_desc->pool_id],
  304. rx_desc);
  305. }
  306. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  307. continue;
  308. }
  309. /*
  310. * this is a unlikely scenario where the host is reaping
  311. * a descriptor which it already reaped just a while ago
  312. * but is yet to replenish it back to HW.
  313. * In this case host will dump the last 128 descriptors
  314. * including the software descriptor rx_desc and assert.
  315. */
  316. if (qdf_unlikely(!rx_desc->in_use)) {
  317. DP_STATS_INC(soc, rx.err.hal_reo_dest_dup, 1);
  318. dp_info_rl("Reaping rx_desc not in use!");
  319. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  320. ring_desc, rx_desc);
  321. /* ignore duplicate RX desc and continue to process */
  322. /* Pop out the descriptor */
  323. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  324. continue;
  325. }
  326. status = dp_rx_desc_nbuf_sanity_check(soc, ring_desc, rx_desc);
  327. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  328. DP_STATS_INC(soc, rx.err.nbuf_sanity_fail, 1);
  329. dp_info_rl("Nbuf sanity check failure!");
  330. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  331. ring_desc, rx_desc);
  332. rx_desc->in_err_state = 1;
  333. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  334. continue;
  335. }
  336. if (qdf_unlikely(!dp_rx_desc_check_magic(rx_desc))) {
  337. dp_err("Invalid rx_desc cookie=%d", rx_buf_cookie);
  338. DP_STATS_INC(soc, rx.err.rx_desc_invalid_magic, 1);
  339. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  340. ring_desc, rx_desc);
  341. }
  342. /* Get MPDU DESC info */
  343. hal_rx_mpdu_desc_info_get_be(ring_desc, &mpdu_desc_info);
  344. /* Get MSDU DESC info */
  345. hal_rx_msdu_desc_info_get_be(ring_desc, &msdu_desc_info);
  346. if (qdf_unlikely(msdu_desc_info.msdu_flags &
  347. HAL_MSDU_F_MSDU_CONTINUATION)) {
  348. /* previous msdu has end bit set, so current one is
  349. * the new MPDU
  350. */
  351. if (is_prev_msdu_last) {
  352. /* Get number of entries available in HW ring */
  353. num_entries_avail =
  354. hal_srng_dst_num_valid(hal_soc,
  355. hal_ring_hdl, 1);
  356. /* For new MPDU check if we can read complete
  357. * MPDU by comparing the number of buffers
  358. * available and number of buffers needed to
  359. * reap this MPDU
  360. */
  361. if ((msdu_desc_info.msdu_len /
  362. (RX_DATA_BUFFER_SIZE -
  363. soc->rx_pkt_tlv_size) + 1) >
  364. num_pending) {
  365. DP_STATS_INC(soc,
  366. rx.msdu_scatter_wait_break,
  367. 1);
  368. dp_rx_cookie_reset_invalid_bit(
  369. ring_desc);
  370. /* As we are going to break out of the
  371. * loop because of unavailability of
  372. * descs to form complete SG, we need to
  373. * reset the TP in the REO destination
  374. * ring.
  375. */
  376. hal_srng_dst_dec_tp(hal_soc,
  377. hal_ring_hdl);
  378. break;
  379. }
  380. is_prev_msdu_last = false;
  381. }
  382. }
  383. if (mpdu_desc_info.mpdu_flags & HAL_MPDU_F_RETRY_BIT)
  384. qdf_nbuf_set_rx_retry_flag(rx_desc->nbuf, 1);
  385. if (qdf_unlikely(mpdu_desc_info.mpdu_flags &
  386. HAL_MPDU_F_RAW_AMPDU))
  387. qdf_nbuf_set_raw_frame(rx_desc->nbuf, 1);
  388. if (!is_prev_msdu_last &&
  389. msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  390. is_prev_msdu_last = true;
  391. rx_bufs_reaped[rx_desc->chip_id][rx_desc->pool_id]++;
  392. peer_mdata = mpdu_desc_info.peer_meta_data;
  393. QDF_NBUF_CB_RX_PEER_ID(rx_desc->nbuf) =
  394. dp_rx_peer_metadata_peer_id_get_be(soc, peer_mdata);
  395. QDF_NBUF_CB_RX_VDEV_ID(rx_desc->nbuf) =
  396. dp_rx_peer_metadata_vdev_id_get_be(soc, peer_mdata);
  397. dp_rx_set_msdu_lmac_id(rx_desc->nbuf, peer_mdata);
  398. /* to indicate whether this msdu is rx offload */
  399. pkt_capture_offload =
  400. DP_PEER_METADATA_OFFLOAD_GET_BE(peer_mdata);
  401. /*
  402. * save msdu flags first, last and continuation msdu in
  403. * nbuf->cb, also save mcbc, is_da_valid, is_sa_valid and
  404. * length to nbuf->cb. This ensures the info required for
  405. * per pkt processing is always in the same cache line.
  406. * This helps in improving throughput for smaller pkt
  407. * sizes.
  408. */
  409. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_FIRST_MSDU_IN_MPDU)
  410. qdf_nbuf_set_rx_chfrag_start(rx_desc->nbuf, 1);
  411. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_MSDU_CONTINUATION)
  412. qdf_nbuf_set_rx_chfrag_cont(rx_desc->nbuf, 1);
  413. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  414. qdf_nbuf_set_rx_chfrag_end(rx_desc->nbuf, 1);
  415. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_MCBC)
  416. qdf_nbuf_set_da_mcbc(rx_desc->nbuf, 1);
  417. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_VALID)
  418. qdf_nbuf_set_da_valid(rx_desc->nbuf, 1);
  419. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_SA_IS_VALID)
  420. qdf_nbuf_set_sa_valid(rx_desc->nbuf, 1);
  421. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_INTRA_BSS)
  422. qdf_nbuf_set_intra_bss(rx_desc->nbuf, 1);
  423. if (qdf_likely(mpdu_desc_info.mpdu_flags &
  424. HAL_MPDU_F_QOS_CONTROL_VALID))
  425. qdf_nbuf_set_tid_val(rx_desc->nbuf, mpdu_desc_info.tid);
  426. /* set sw exception */
  427. qdf_nbuf_set_rx_reo_dest_ind_or_sw_excpt(
  428. rx_desc->nbuf,
  429. hal_rx_sw_exception_get_be(ring_desc));
  430. QDF_NBUF_CB_RX_PKT_LEN(rx_desc->nbuf) = msdu_desc_info.msdu_len;
  431. QDF_NBUF_CB_RX_CTX_ID(rx_desc->nbuf) = reo_ring_num;
  432. /*
  433. * move unmap after scattered msdu waiting break logic
  434. * in case double skb unmap happened.
  435. */
  436. dp_rx_nbuf_unmap(soc, rx_desc, reo_ring_num);
  437. rx_desc->unmapped = 1;
  438. DP_RX_PROCESS_NBUF(soc, nbuf_head, nbuf_tail, ebuf_head,
  439. ebuf_tail, rx_desc);
  440. quota -= 1;
  441. num_pending -= 1;
  442. dp_rx_add_to_free_desc_list
  443. (&head[rx_desc->chip_id][rx_desc->pool_id],
  444. &tail[rx_desc->chip_id][rx_desc->pool_id], rx_desc);
  445. num_rx_bufs_reaped++;
  446. dp_rx_prefetch_hw_sw_nbuf_32_byte_desc(soc, hal_soc,
  447. num_pending,
  448. hal_ring_hdl,
  449. &last_prefetched_hw_desc,
  450. &last_prefetched_sw_desc);
  451. /*
  452. * only if complete msdu is received for scatter case,
  453. * then allow break.
  454. */
  455. if (is_prev_msdu_last &&
  456. dp_rx_reap_loop_pkt_limit_hit(soc, num_rx_bufs_reaped,
  457. max_reap_limit))
  458. break;
  459. }
  460. done:
  461. dp_rx_srng_access_end(int_ctx, soc, hal_ring_hdl);
  462. qdf_dsb();
  463. dp_rx_per_core_stats_update(soc, reo_ring_num, num_rx_bufs_reaped);
  464. for (chip_id = 0; chip_id < WLAN_MAX_MLO_CHIPS; chip_id++) {
  465. for (mac_id = 0; mac_id < MAX_PDEV_CNT; mac_id++) {
  466. /*
  467. * continue with next mac_id if no pkts were reaped
  468. * from that pool
  469. */
  470. if (!rx_bufs_reaped[chip_id][mac_id])
  471. continue;
  472. replenish_soc = dp_rx_replensih_soc_get(soc, chip_id);
  473. dp_rxdma_srng =
  474. &replenish_soc->rx_refill_buf_ring[mac_id];
  475. rx_desc_pool = &replenish_soc->rx_desc_buf[mac_id];
  476. dp_rx_buffers_replenish_simple(replenish_soc, mac_id,
  477. dp_rxdma_srng,
  478. rx_desc_pool,
  479. rx_bufs_reaped[chip_id][mac_id],
  480. &head[chip_id][mac_id],
  481. &tail[chip_id][mac_id]);
  482. }
  483. }
  484. /* Peer can be NULL is case of LFR */
  485. if (qdf_likely(txrx_peer))
  486. vdev = NULL;
  487. /*
  488. * BIG loop where each nbuf is dequeued from global queue,
  489. * processed and queued back on a per vdev basis. These nbufs
  490. * are sent to stack as and when we run out of nbufs
  491. * or a new nbuf dequeued from global queue has a different
  492. * vdev when compared to previous nbuf.
  493. */
  494. nbuf = nbuf_head;
  495. while (nbuf) {
  496. next = nbuf->next;
  497. dp_rx_prefetch_nbuf_data_be(nbuf, next);
  498. if (qdf_unlikely(dp_rx_is_raw_frame_dropped(nbuf))) {
  499. nbuf = next;
  500. DP_STATS_INC(soc, rx.err.raw_frm_drop, 1);
  501. continue;
  502. }
  503. rx_tlv_hdr = qdf_nbuf_data(nbuf);
  504. vdev_id = QDF_NBUF_CB_RX_VDEV_ID(nbuf);
  505. peer_id = QDF_NBUF_CB_RX_PEER_ID(nbuf);
  506. if (dp_rx_is_list_ready(deliver_list_head, vdev, txrx_peer,
  507. peer_id, vdev_id)) {
  508. dp_rx_deliver_to_stack(soc, vdev, txrx_peer,
  509. deliver_list_head,
  510. deliver_list_tail);
  511. deliver_list_head = NULL;
  512. deliver_list_tail = NULL;
  513. }
  514. /* Get TID from struct cb->tid_val, save to tid */
  515. tid = qdf_nbuf_get_tid_val(nbuf);
  516. if (qdf_unlikely(!txrx_peer)) {
  517. txrx_peer = dp_rx_get_txrx_peer_and_vdev(soc, nbuf,
  518. peer_id,
  519. &txrx_ref_handle,
  520. pkt_capture_offload,
  521. &vdev,
  522. &rx_pdev, &dsf,
  523. &old_tid);
  524. if (qdf_unlikely(!txrx_peer) || qdf_unlikely(!vdev)) {
  525. nbuf = next;
  526. continue;
  527. }
  528. enh_flag = rx_pdev->enhanced_stats_en;
  529. } else if (txrx_peer && txrx_peer->peer_id != peer_id) {
  530. dp_txrx_peer_unref_delete(txrx_ref_handle,
  531. DP_MOD_ID_RX);
  532. txrx_peer = dp_rx_get_txrx_peer_and_vdev(soc, nbuf,
  533. peer_id,
  534. &txrx_ref_handle,
  535. pkt_capture_offload,
  536. &vdev,
  537. &rx_pdev, &dsf,
  538. &old_tid);
  539. if (qdf_unlikely(!txrx_peer) || qdf_unlikely(!vdev)) {
  540. nbuf = next;
  541. continue;
  542. }
  543. enh_flag = rx_pdev->enhanced_stats_en;
  544. }
  545. if (txrx_peer) {
  546. QDF_NBUF_CB_DP_TRACE_PRINT(nbuf) = false;
  547. qdf_dp_trace_set_track(nbuf, QDF_RX);
  548. QDF_NBUF_CB_RX_DP_TRACE(nbuf) = 1;
  549. QDF_NBUF_CB_RX_PACKET_TRACK(nbuf) =
  550. QDF_NBUF_RX_PKT_DATA_TRACK;
  551. }
  552. rx_bufs_used++;
  553. /* when hlos tid override is enabled, save tid in
  554. * skb->priority
  555. */
  556. if (qdf_unlikely(vdev->skip_sw_tid_classification &
  557. DP_TXRX_HLOS_TID_OVERRIDE_ENABLED))
  558. qdf_nbuf_set_priority(nbuf, tid);
  559. DP_RX_TID_SAVE(nbuf, tid);
  560. if (qdf_unlikely(dsf) || qdf_unlikely(peer_ext_stats) ||
  561. dp_rx_pkt_tracepoints_enabled())
  562. qdf_nbuf_set_timestamp(nbuf);
  563. if (qdf_likely(old_tid != tid)) {
  564. tid_stats =
  565. &rx_pdev->stats.tid_stats.tid_rx_stats[reo_ring_num][tid];
  566. old_tid = tid;
  567. }
  568. /*
  569. * Check if DMA completed -- msdu_done is the last bit
  570. * to be written
  571. */
  572. if (qdf_unlikely(!qdf_nbuf_is_rx_chfrag_cont(nbuf) &&
  573. !hal_rx_tlv_msdu_done_get_be(rx_tlv_hdr))) {
  574. dp_err("MSDU DONE failure");
  575. DP_STATS_INC(soc, rx.err.msdu_done_fail, 1);
  576. hal_rx_dump_pkt_tlvs(hal_soc, rx_tlv_hdr,
  577. QDF_TRACE_LEVEL_INFO);
  578. tid_stats->fail_cnt[MSDU_DONE_FAILURE]++;
  579. dp_rx_nbuf_free(nbuf);
  580. qdf_assert(0);
  581. nbuf = next;
  582. continue;
  583. }
  584. DP_HIST_PACKET_COUNT_INC(vdev->pdev->pdev_id);
  585. /*
  586. * First IF condition:
  587. * 802.11 Fragmented pkts are reinjected to REO
  588. * HW block as SG pkts and for these pkts we only
  589. * need to pull the RX TLVS header length.
  590. * Second IF condition:
  591. * The below condition happens when an MSDU is spread
  592. * across multiple buffers. This can happen in two cases
  593. * 1. The nbuf size is smaller then the received msdu.
  594. * ex: we have set the nbuf size to 2048 during
  595. * nbuf_alloc. but we received an msdu which is
  596. * 2304 bytes in size then this msdu is spread
  597. * across 2 nbufs.
  598. *
  599. * 2. AMSDUs when RAW mode is enabled.
  600. * ex: 1st MSDU is in 1st nbuf and 2nd MSDU is spread
  601. * across 1st nbuf and 2nd nbuf and last MSDU is
  602. * spread across 2nd nbuf and 3rd nbuf.
  603. *
  604. * for these scenarios let us create a skb frag_list and
  605. * append these buffers till the last MSDU of the AMSDU
  606. * Third condition:
  607. * This is the most likely case, we receive 802.3 pkts
  608. * decapsulated by HW, here we need to set the pkt length.
  609. */
  610. hal_rx_msdu_packet_metadata_get_generic_be(rx_tlv_hdr,
  611. &msdu_metadata);
  612. if (qdf_unlikely(qdf_nbuf_is_frag(nbuf))) {
  613. bool is_mcbc, is_sa_vld, is_da_vld;
  614. is_mcbc = hal_rx_msdu_end_da_is_mcbc_get(soc->hal_soc,
  615. rx_tlv_hdr);
  616. is_sa_vld =
  617. hal_rx_msdu_end_sa_is_valid_get(soc->hal_soc,
  618. rx_tlv_hdr);
  619. is_da_vld =
  620. hal_rx_msdu_end_da_is_valid_get(soc->hal_soc,
  621. rx_tlv_hdr);
  622. qdf_nbuf_set_da_mcbc(nbuf, is_mcbc);
  623. qdf_nbuf_set_da_valid(nbuf, is_da_vld);
  624. qdf_nbuf_set_sa_valid(nbuf, is_sa_vld);
  625. qdf_nbuf_pull_head(nbuf, soc->rx_pkt_tlv_size);
  626. } else if (qdf_nbuf_is_rx_chfrag_cont(nbuf)) {
  627. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  628. nbuf = dp_rx_sg_create(soc, nbuf);
  629. next = nbuf->next;
  630. if (qdf_nbuf_is_raw_frame(nbuf)) {
  631. DP_STATS_INC(vdev->pdev, rx_raw_pkts, 1);
  632. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  633. rx.raw, 1,
  634. msdu_len);
  635. } else {
  636. dp_rx_nbuf_free(nbuf);
  637. DP_STATS_INC(soc, rx.err.scatter_msdu, 1);
  638. dp_info_rl("scatter msdu len %d, dropped",
  639. msdu_len);
  640. nbuf = next;
  641. continue;
  642. }
  643. } else {
  644. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  645. pkt_len = msdu_len +
  646. msdu_metadata.l3_hdr_pad +
  647. soc->rx_pkt_tlv_size;
  648. qdf_nbuf_set_pktlen(nbuf, pkt_len);
  649. dp_rx_skip_tlvs(soc, nbuf, msdu_metadata.l3_hdr_pad);
  650. }
  651. dp_rx_send_pktlog(soc, rx_pdev, nbuf, QDF_TX_RX_STATUS_OK);
  652. /*
  653. * process frame for mulitpass phrase processing
  654. */
  655. if (qdf_unlikely(vdev->multipass_en)) {
  656. if (dp_rx_multipass_process(txrx_peer, nbuf,
  657. tid) == false) {
  658. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  659. rx.multipass_rx_pkt_drop,
  660. 1);
  661. dp_rx_nbuf_free(nbuf);
  662. nbuf = next;
  663. continue;
  664. }
  665. }
  666. if (!dp_wds_rx_policy_check(rx_tlv_hdr, vdev, txrx_peer)) {
  667. dp_rx_err("%pK: Policy Check Drop pkt", soc);
  668. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  669. rx.policy_check_drop, 1);
  670. tid_stats->fail_cnt[POLICY_CHECK_DROP]++;
  671. /* Drop & free packet */
  672. dp_rx_nbuf_free(nbuf);
  673. /* Statistics */
  674. nbuf = next;
  675. continue;
  676. }
  677. if (qdf_unlikely(txrx_peer && (txrx_peer->nawds_enabled) &&
  678. (qdf_nbuf_is_da_mcbc(nbuf)) &&
  679. (hal_rx_get_mpdu_mac_ad4_valid_be(rx_tlv_hdr)
  680. == false))) {
  681. tid_stats->fail_cnt[NAWDS_MCAST_DROP]++;
  682. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  683. rx.nawds_mcast_drop, 1);
  684. dp_rx_nbuf_free(nbuf);
  685. nbuf = next;
  686. continue;
  687. }
  688. /*
  689. * Drop non-EAPOL frames from unauthorized peer.
  690. */
  691. if (qdf_likely(txrx_peer) &&
  692. qdf_unlikely(!txrx_peer->authorize) &&
  693. !qdf_nbuf_is_raw_frame(nbuf)) {
  694. bool is_eapol = qdf_nbuf_is_ipv4_eapol_pkt(nbuf) ||
  695. qdf_nbuf_is_ipv4_wapi_pkt(nbuf);
  696. if (!is_eapol) {
  697. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  698. rx.peer_unauth_rx_pkt_drop,
  699. 1);
  700. dp_rx_nbuf_free(nbuf);
  701. nbuf = next;
  702. continue;
  703. }
  704. }
  705. if (soc->process_rx_status)
  706. dp_rx_cksum_offload(vdev->pdev, nbuf, rx_tlv_hdr);
  707. /* Update the protocol tag in SKB based on CCE metadata */
  708. dp_rx_update_protocol_tag(soc, vdev, nbuf, rx_tlv_hdr,
  709. reo_ring_num, false, true);
  710. /* Update the flow tag in SKB based on FSE metadata */
  711. dp_rx_update_flow_tag(soc, vdev, nbuf, rx_tlv_hdr, true);
  712. dp_rx_msdu_stats_update(soc, nbuf, rx_tlv_hdr, txrx_peer,
  713. reo_ring_num, tid_stats);
  714. if (qdf_unlikely(vdev->mesh_vdev)) {
  715. if (dp_rx_filter_mesh_packets(vdev, nbuf, rx_tlv_hdr)
  716. == QDF_STATUS_SUCCESS) {
  717. dp_rx_info("%pK: mesh pkt filtered", soc);
  718. tid_stats->fail_cnt[MESH_FILTER_DROP]++;
  719. DP_STATS_INC(vdev->pdev, dropped.mesh_filter,
  720. 1);
  721. dp_rx_nbuf_free(nbuf);
  722. nbuf = next;
  723. continue;
  724. }
  725. dp_rx_fill_mesh_stats(vdev, nbuf, rx_tlv_hdr,
  726. txrx_peer);
  727. }
  728. if (qdf_likely(vdev->rx_decap_type ==
  729. htt_cmn_pkt_type_ethernet) &&
  730. qdf_likely(!vdev->mesh_vdev)) {
  731. dp_rx_wds_learn(soc, vdev,
  732. rx_tlv_hdr,
  733. txrx_peer,
  734. nbuf,
  735. msdu_metadata);
  736. /* Intrabss-fwd */
  737. if (dp_rx_check_ap_bridge(vdev))
  738. if (dp_rx_intrabss_fwd_be(soc, txrx_peer,
  739. rx_tlv_hdr,
  740. nbuf,
  741. msdu_metadata)) {
  742. nbuf = next;
  743. tid_stats->intrabss_cnt++;
  744. continue; /* Get next desc */
  745. }
  746. }
  747. dp_rx_fill_gro_info(soc, rx_tlv_hdr, nbuf, &rx_ol_pkt_cnt);
  748. dp_rx_mark_first_packet_after_wow_wakeup(vdev->pdev, rx_tlv_hdr,
  749. nbuf);
  750. dp_rx_update_stats(soc, nbuf);
  751. dp_pkt_add_timestamp(txrx_peer->vdev, QDF_PKT_RX_DRIVER_ENTRY,
  752. current_time, nbuf);
  753. DP_RX_LIST_APPEND(deliver_list_head,
  754. deliver_list_tail,
  755. nbuf);
  756. DP_PEER_TO_STACK_INCC_PKT(txrx_peer, 1,
  757. QDF_NBUF_CB_RX_PKT_LEN(nbuf),
  758. enh_flag);
  759. if (qdf_unlikely(txrx_peer->in_twt))
  760. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  761. rx.to_stack_twt, 1,
  762. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  763. tid_stats->delivered_to_stack++;
  764. nbuf = next;
  765. }
  766. DP_RX_DELIVER_TO_STACK(soc, vdev, txrx_peer, peer_id,
  767. pkt_capture_offload,
  768. deliver_list_head,
  769. deliver_list_tail);
  770. if (qdf_likely(txrx_peer))
  771. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_RX);
  772. /*
  773. * If we are processing in near-full condition, there are 3 scenario
  774. * 1) Ring entries has reached critical state
  775. * 2) Ring entries are still near high threshold
  776. * 3) Ring entries are below the safe level
  777. *
  778. * One more loop will move the state to normal processing and yield
  779. */
  780. if (ring_near_full && quota)
  781. goto more_data;
  782. if (dp_rx_enable_eol_data_check(soc) && rx_bufs_used) {
  783. if (quota) {
  784. num_pending =
  785. dp_rx_srng_get_num_pending(hal_soc,
  786. hal_ring_hdl,
  787. num_entries,
  788. &near_full);
  789. if (num_pending) {
  790. DP_STATS_INC(soc, rx.hp_oos2, 1);
  791. if (!hif_exec_should_yield(scn, intr_id))
  792. goto more_data;
  793. if (qdf_unlikely(near_full)) {
  794. DP_STATS_INC(soc, rx.near_full, 1);
  795. goto more_data;
  796. }
  797. }
  798. }
  799. if (vdev && vdev->osif_fisa_flush)
  800. vdev->osif_fisa_flush(soc, reo_ring_num);
  801. if (vdev && vdev->osif_gro_flush && rx_ol_pkt_cnt) {
  802. vdev->osif_gro_flush(vdev->osif_vdev,
  803. reo_ring_num);
  804. }
  805. }
  806. /* Update histogram statistics by looping through pdev's */
  807. DP_RX_HIST_STATS_PER_PDEV();
  808. return rx_bufs_used; /* Assume no scale factor for now */
  809. }
  810. #ifdef RX_DESC_MULTI_PAGE_ALLOC
  811. /**
  812. * dp_rx_desc_pool_init_be_cc() - initial RX desc pool for cookie conversion
  813. * @soc: Handle to DP Soc structure
  814. * @rx_desc_pool: Rx descriptor pool handler
  815. * @pool_id: Rx descriptor pool ID
  816. *
  817. * Return: QDF_STATUS_SUCCESS - succeeded, others - failed
  818. */
  819. static QDF_STATUS
  820. dp_rx_desc_pool_init_be_cc(struct dp_soc *soc,
  821. struct rx_desc_pool *rx_desc_pool,
  822. uint32_t pool_id)
  823. {
  824. struct dp_hw_cookie_conversion_t *cc_ctx;
  825. struct dp_soc_be *be_soc;
  826. union dp_rx_desc_list_elem_t *rx_desc_elem;
  827. struct dp_spt_page_desc *page_desc;
  828. uint32_t ppt_idx = 0;
  829. uint32_t avail_entry_index = 0;
  830. if (!rx_desc_pool->pool_size) {
  831. dp_err("desc_num 0 !!");
  832. return QDF_STATUS_E_FAILURE;
  833. }
  834. be_soc = dp_get_be_soc_from_dp_soc(soc);
  835. cc_ctx = &be_soc->rx_cc_ctx[pool_id];
  836. page_desc = &cc_ctx->page_desc_base[0];
  837. rx_desc_elem = rx_desc_pool->freelist;
  838. while (rx_desc_elem) {
  839. if (avail_entry_index == 0) {
  840. if (ppt_idx >= cc_ctx->total_page_num) {
  841. dp_alert("insufficient secondary page tables");
  842. qdf_assert_always(0);
  843. }
  844. page_desc = &cc_ctx->page_desc_base[ppt_idx++];
  845. }
  846. /* put each RX Desc VA to SPT pages and
  847. * get corresponding ID
  848. */
  849. DP_CC_SPT_PAGE_UPDATE_VA(page_desc->page_v_addr,
  850. avail_entry_index,
  851. &rx_desc_elem->rx_desc);
  852. rx_desc_elem->rx_desc.cookie =
  853. dp_cc_desc_id_generate(page_desc->ppt_index,
  854. avail_entry_index);
  855. rx_desc_elem->rx_desc.chip_id = dp_mlo_get_chip_id(soc);
  856. rx_desc_elem->rx_desc.pool_id = pool_id;
  857. rx_desc_elem->rx_desc.in_use = 0;
  858. rx_desc_elem = rx_desc_elem->next;
  859. avail_entry_index = (avail_entry_index + 1) &
  860. DP_CC_SPT_PAGE_MAX_ENTRIES_MASK;
  861. }
  862. return QDF_STATUS_SUCCESS;
  863. }
  864. #else
  865. static QDF_STATUS
  866. dp_rx_desc_pool_init_be_cc(struct dp_soc *soc,
  867. struct rx_desc_pool *rx_desc_pool,
  868. uint32_t pool_id)
  869. {
  870. struct dp_hw_cookie_conversion_t *cc_ctx;
  871. struct dp_soc_be *be_soc;
  872. struct dp_spt_page_desc *page_desc;
  873. uint32_t ppt_idx = 0;
  874. uint32_t avail_entry_index = 0;
  875. int i = 0;
  876. if (!rx_desc_pool->pool_size) {
  877. dp_err("desc_num 0 !!");
  878. return QDF_STATUS_E_FAILURE;
  879. }
  880. be_soc = dp_get_be_soc_from_dp_soc(soc);
  881. cc_ctx = &be_soc->rx_cc_ctx[pool_id];
  882. page_desc = &cc_ctx->page_desc_base[0];
  883. for (i = 0; i <= rx_desc_pool->pool_size - 1; i++) {
  884. if (i == rx_desc_pool->pool_size - 1)
  885. rx_desc_pool->array[i].next = NULL;
  886. else
  887. rx_desc_pool->array[i].next =
  888. &rx_desc_pool->array[i + 1];
  889. if (avail_entry_index == 0) {
  890. if (ppt_idx >= cc_ctx->total_page_num) {
  891. dp_alert("insufficient secondary page tables");
  892. qdf_assert_always(0);
  893. }
  894. page_desc = &cc_ctx->page_desc_base[ppt_idx++];
  895. }
  896. /* put each RX Desc VA to SPT pages and
  897. * get corresponding ID
  898. */
  899. DP_CC_SPT_PAGE_UPDATE_VA(page_desc->page_v_addr,
  900. avail_entry_index,
  901. &rx_desc_pool->array[i].rx_desc);
  902. rx_desc_pool->array[i].rx_desc.cookie =
  903. dp_cc_desc_id_generate(page_desc->ppt_index,
  904. avail_entry_index);
  905. rx_desc_pool->array[i].rx_desc.pool_id = pool_id;
  906. rx_desc_pool->array[i].rx_desc.in_use = 0;
  907. rx_desc_pool->array[i].rx_desc.chip_id =
  908. dp_mlo_get_chip_id(soc);
  909. avail_entry_index = (avail_entry_index + 1) &
  910. DP_CC_SPT_PAGE_MAX_ENTRIES_MASK;
  911. }
  912. return QDF_STATUS_SUCCESS;
  913. }
  914. #endif
  915. static void
  916. dp_rx_desc_pool_deinit_be_cc(struct dp_soc *soc,
  917. struct rx_desc_pool *rx_desc_pool,
  918. uint32_t pool_id)
  919. {
  920. struct dp_spt_page_desc *page_desc;
  921. struct dp_soc_be *be_soc;
  922. int i = 0;
  923. struct dp_hw_cookie_conversion_t *cc_ctx;
  924. be_soc = dp_get_be_soc_from_dp_soc(soc);
  925. cc_ctx = &be_soc->rx_cc_ctx[pool_id];
  926. for (i = 0; i < cc_ctx->total_page_num; i++) {
  927. page_desc = &cc_ctx->page_desc_base[i];
  928. qdf_mem_zero(page_desc->page_v_addr, qdf_page_size);
  929. }
  930. }
  931. QDF_STATUS dp_rx_desc_pool_init_be(struct dp_soc *soc,
  932. struct rx_desc_pool *rx_desc_pool,
  933. uint32_t pool_id)
  934. {
  935. QDF_STATUS status = QDF_STATUS_SUCCESS;
  936. /* Only regular RX buffer desc pool use HW cookie conversion */
  937. if (rx_desc_pool->desc_type == DP_RX_DESC_BUF_TYPE) {
  938. dp_info("rx_desc_buf pool init");
  939. status = dp_rx_desc_pool_init_be_cc(soc,
  940. rx_desc_pool,
  941. pool_id);
  942. } else {
  943. dp_info("non_rx_desc_buf_pool init");
  944. status = dp_rx_desc_pool_init_generic(soc, rx_desc_pool,
  945. pool_id);
  946. }
  947. return status;
  948. }
  949. void dp_rx_desc_pool_deinit_be(struct dp_soc *soc,
  950. struct rx_desc_pool *rx_desc_pool,
  951. uint32_t pool_id)
  952. {
  953. if (rx_desc_pool->desc_type == DP_RX_DESC_BUF_TYPE)
  954. dp_rx_desc_pool_deinit_be_cc(soc, rx_desc_pool, pool_id);
  955. }
  956. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  957. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  958. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  959. void *ring_desc,
  960. struct dp_rx_desc **r_rx_desc)
  961. {
  962. if (hal_rx_wbm_get_cookie_convert_done(ring_desc)) {
  963. /* HW cookie conversion done */
  964. *r_rx_desc = (struct dp_rx_desc *)
  965. hal_rx_wbm_get_desc_va(ring_desc);
  966. } else {
  967. /* SW do cookie conversion */
  968. uint32_t cookie = HAL_RX_BUF_COOKIE_GET(ring_desc);
  969. *r_rx_desc = (struct dp_rx_desc *)
  970. dp_cc_desc_find(soc, cookie);
  971. }
  972. return QDF_STATUS_SUCCESS;
  973. }
  974. #else
  975. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  976. void *ring_desc,
  977. struct dp_rx_desc **r_rx_desc)
  978. {
  979. *r_rx_desc = (struct dp_rx_desc *)
  980. hal_rx_wbm_get_desc_va(ring_desc);
  981. return QDF_STATUS_SUCCESS;
  982. }
  983. #endif /* DP_HW_COOKIE_CONVERT_EXCEPTION */
  984. #else
  985. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  986. void *ring_desc,
  987. struct dp_rx_desc **r_rx_desc)
  988. {
  989. /* SW do cookie conversion */
  990. uint32_t cookie = HAL_RX_BUF_COOKIE_GET(ring_desc);
  991. *r_rx_desc = (struct dp_rx_desc *)
  992. dp_cc_desc_find(soc, cookie);
  993. return QDF_STATUS_SUCCESS;
  994. }
  995. #endif /* DP_FEATURE_HW_COOKIE_CONVERSION */
  996. struct dp_rx_desc *dp_rx_desc_cookie_2_va_be(struct dp_soc *soc,
  997. uint32_t cookie)
  998. {
  999. return (struct dp_rx_desc *)dp_cc_desc_find(soc, cookie);
  1000. }
  1001. #if defined(WLAN_FEATURE_11BE_MLO)
  1002. #if defined(WLAN_MLO_MULTI_CHIP) && defined(WLAN_MCAST_MLO)
  1003. #define DP_RANDOM_MAC_ID_BIT_MASK 0xC0
  1004. #define DP_RANDOM_MAC_OFFSET 1
  1005. #define DP_MAC_LOCAL_ADMBIT_MASK 0x2
  1006. #define DP_MAC_LOCAL_ADMBIT_OFFSET 0
  1007. static inline void dp_rx_dummy_src_mac(struct dp_vdev *vdev,
  1008. qdf_nbuf_t nbuf)
  1009. {
  1010. uint8_t random_mac[QDF_MAC_ADDR_SIZE] = {0};
  1011. qdf_ether_header_t *eh =
  1012. (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1013. qdf_mem_copy(random_mac, &vdev->mld_mac_addr.raw[0], QDF_MAC_ADDR_SIZE);
  1014. random_mac[DP_MAC_LOCAL_ADMBIT_OFFSET] =
  1015. random_mac[DP_MAC_LOCAL_ADMBIT_OFFSET] |
  1016. DP_MAC_LOCAL_ADMBIT_MASK;
  1017. random_mac[DP_RANDOM_MAC_OFFSET] =
  1018. random_mac[DP_RANDOM_MAC_OFFSET] ^ DP_RANDOM_MAC_ID_BIT_MASK;
  1019. qdf_mem_copy(&eh->ether_shost[0], random_mac, QDF_MAC_ADDR_SIZE);
  1020. }
  1021. #ifdef QCA_SUPPORT_WDS_EXTENDED
  1022. static inline bool dp_rx_mlo_igmp_wds_ext_handler(struct dp_txrx_peer *peer)
  1023. {
  1024. return qdf_atomic_test_bit(WDS_EXT_PEER_INIT_BIT, &peer->wds_ext.init);
  1025. }
  1026. #else
  1027. static inline bool dp_rx_mlo_igmp_wds_ext_handler(struct dp_txrx_peer *peer)
  1028. {
  1029. return false;
  1030. }
  1031. #endif
  1032. bool dp_rx_mlo_igmp_handler(struct dp_soc *soc,
  1033. struct dp_vdev *vdev,
  1034. struct dp_txrx_peer *peer,
  1035. qdf_nbuf_t nbuf)
  1036. {
  1037. struct dp_vdev *mcast_primary_vdev = NULL;
  1038. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1039. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1040. uint8_t tid = qdf_nbuf_get_tid_val(nbuf);
  1041. struct cdp_tid_rx_stats *tid_stats = &peer->vdev->pdev->stats.
  1042. tid_stats.tid_rx_wbm_stats[0][tid];
  1043. if (!(qdf_nbuf_is_ipv4_igmp_pkt(nbuf) ||
  1044. qdf_nbuf_is_ipv6_igmp_pkt(nbuf)))
  1045. return false;
  1046. if (!peer->bss_peer) {
  1047. if (dp_rx_intrabss_mcbc_fwd(soc, peer, NULL, nbuf, tid_stats))
  1048. dp_rx_err("forwarding failed");
  1049. }
  1050. /*
  1051. * In the case of ME6, Backhaul WDS, NAWDS
  1052. * send the igmp pkt on the same link where it received,
  1053. * as these features will use peer based tcl metadata
  1054. */
  1055. qdf_nbuf_set_next(nbuf, NULL);
  1056. if (vdev->mcast_enhancement_en || be_vdev->mcast_primary ||
  1057. peer->nawds_enabled)
  1058. goto send_pkt;
  1059. if (qdf_unlikely(dp_rx_mlo_igmp_wds_ext_handler(peer)))
  1060. goto send_pkt;
  1061. mcast_primary_vdev = dp_mlo_get_mcast_primary_vdev(be_soc, be_vdev,
  1062. DP_MOD_ID_RX);
  1063. if (!mcast_primary_vdev) {
  1064. dp_rx_debug("Non mlo vdev");
  1065. goto send_pkt;
  1066. }
  1067. if (qdf_unlikely(vdev->wrap_vdev)) {
  1068. /* In the case of qwrap repeater send the original
  1069. * packet on the interface where it received,
  1070. * packet with dummy src on the mcast primary interface.
  1071. */
  1072. qdf_nbuf_t nbuf_copy;
  1073. nbuf_copy = qdf_nbuf_copy(nbuf);
  1074. if (qdf_likely(nbuf_copy))
  1075. dp_rx_deliver_to_stack(soc, vdev, peer, nbuf_copy,
  1076. NULL);
  1077. }
  1078. dp_rx_dummy_src_mac(vdev, nbuf);
  1079. dp_rx_deliver_to_stack(mcast_primary_vdev->pdev->soc,
  1080. mcast_primary_vdev,
  1081. peer,
  1082. nbuf,
  1083. NULL);
  1084. dp_vdev_unref_delete(mcast_primary_vdev->pdev->soc,
  1085. mcast_primary_vdev,
  1086. DP_MOD_ID_RX);
  1087. return true;
  1088. send_pkt:
  1089. dp_rx_deliver_to_stack(be_vdev->vdev.pdev->soc,
  1090. &be_vdev->vdev,
  1091. peer,
  1092. nbuf,
  1093. NULL);
  1094. return true;
  1095. }
  1096. #else
  1097. bool dp_rx_mlo_igmp_handler(struct dp_soc *soc,
  1098. struct dp_vdev *vdev,
  1099. struct dp_txrx_peer *peer,
  1100. qdf_nbuf_t nbuf)
  1101. {
  1102. return false;
  1103. }
  1104. #endif
  1105. #endif
  1106. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1107. uint32_t dp_rx_nf_process(struct dp_intr *int_ctx,
  1108. hal_ring_handle_t hal_ring_hdl,
  1109. uint8_t reo_ring_num,
  1110. uint32_t quota)
  1111. {
  1112. struct dp_soc *soc = int_ctx->soc;
  1113. struct dp_srng *rx_ring = &soc->reo_dest_ring[reo_ring_num];
  1114. uint32_t work_done = 0;
  1115. if (dp_srng_get_near_full_level(soc, rx_ring) <
  1116. DP_SRNG_THRESH_NEAR_FULL)
  1117. return 0;
  1118. qdf_atomic_set(&rx_ring->near_full, 1);
  1119. work_done++;
  1120. return work_done;
  1121. }
  1122. #endif
  1123. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  1124. #ifdef WLAN_FEATURE_11BE_MLO
  1125. /**
  1126. * dp_rx_intrabss_fwd_mlo_allow() - check if MLO forwarding is allowed
  1127. * @ta_peer: transmitter peer handle
  1128. * @da_peer: destination peer handle
  1129. *
  1130. * Return: true - MLO forwarding case, false: not
  1131. */
  1132. static inline bool
  1133. dp_rx_intrabss_fwd_mlo_allow(struct dp_txrx_peer *ta_peer,
  1134. struct dp_txrx_peer *da_peer)
  1135. {
  1136. /* one of TA/DA peer should belong to MLO connection peer,
  1137. * only MLD peer type is as expected
  1138. */
  1139. if (!IS_MLO_DP_MLD_TXRX_PEER(ta_peer) &&
  1140. !IS_MLO_DP_MLD_TXRX_PEER(da_peer))
  1141. return false;
  1142. /* TA peer and DA peer's vdev should be partner MLO vdevs */
  1143. if (dp_peer_find_mac_addr_cmp(&ta_peer->vdev->mld_mac_addr,
  1144. &da_peer->vdev->mld_mac_addr))
  1145. return false;
  1146. return true;
  1147. }
  1148. #else
  1149. static inline bool
  1150. dp_rx_intrabss_fwd_mlo_allow(struct dp_txrx_peer *ta_peer,
  1151. struct dp_txrx_peer *da_peer)
  1152. {
  1153. return false;
  1154. }
  1155. #endif
  1156. #ifdef INTRA_BSS_FWD_OFFLOAD
  1157. /**
  1158. * dp_rx_intrabss_ucast_check_be() - Check if intrabss is allowed
  1159. for unicast frame
  1160. * @soc: SOC hanlde
  1161. * @nbuf: RX packet buffer
  1162. * @ta_peer: transmitter DP peer handle
  1163. * @msdu_metadata: MSDU meta data info
  1164. * @p_tx_vdev_id: get vdev id for Intra-BSS TX
  1165. *
  1166. * Return: true - intrabss allowed
  1167. false - not allow
  1168. */
  1169. static bool
  1170. dp_rx_intrabss_ucast_check_be(qdf_nbuf_t nbuf,
  1171. struct dp_txrx_peer *ta_peer,
  1172. struct hal_rx_msdu_metadata *msdu_metadata,
  1173. struct dp_be_intrabss_params *params)
  1174. {
  1175. uint16_t da_peer_id;
  1176. struct dp_txrx_peer *da_peer;
  1177. dp_txrx_ref_handle txrx_ref_handle = NULL;
  1178. if (!qdf_nbuf_is_intra_bss(nbuf))
  1179. return false;
  1180. da_peer_id = dp_rx_peer_metadata_peer_id_get_be(
  1181. params->dest_soc,
  1182. msdu_metadata->da_idx);
  1183. da_peer = dp_txrx_peer_get_ref_by_id(params->dest_soc, da_peer_id,
  1184. &txrx_ref_handle, DP_MOD_ID_RX);
  1185. if (!da_peer)
  1186. return false;
  1187. params->tx_vdev_id = da_peer->vdev->vdev_id;
  1188. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_RX);
  1189. return true;
  1190. }
  1191. #else
  1192. #ifdef WLAN_MLO_MULTI_CHIP
  1193. static bool
  1194. dp_rx_intrabss_ucast_check_be(qdf_nbuf_t nbuf,
  1195. struct dp_txrx_peer *ta_peer,
  1196. struct hal_rx_msdu_metadata *msdu_metadata,
  1197. struct dp_be_intrabss_params *params)
  1198. {
  1199. uint16_t da_peer_id;
  1200. struct dp_txrx_peer *da_peer;
  1201. bool ret = false;
  1202. uint8_t dest_chip_id;
  1203. dp_txrx_ref_handle txrx_ref_handle = NULL;
  1204. struct dp_vdev_be *be_vdev =
  1205. dp_get_be_vdev_from_dp_vdev(ta_peer->vdev);
  1206. struct dp_soc_be *be_soc =
  1207. dp_get_be_soc_from_dp_soc(params->dest_soc);
  1208. if (!(qdf_nbuf_is_da_valid(nbuf) || qdf_nbuf_is_da_mcbc(nbuf)))
  1209. return false;
  1210. dest_chip_id = HAL_RX_DEST_CHIP_ID_GET(msdu_metadata);
  1211. qdf_assert_always(dest_chip_id <= (DP_MLO_MAX_DEST_CHIP_ID - 1));
  1212. da_peer_id = HAL_RX_PEER_ID_GET(msdu_metadata);
  1213. /* use dest chip id when TA is MLD peer and DA is legacy */
  1214. if (be_soc->mlo_enabled &&
  1215. ta_peer->mld_peer &&
  1216. !(da_peer_id & HAL_RX_DA_IDX_ML_PEER_MASK)) {
  1217. /* validate chip_id, get a ref, and re-assign soc */
  1218. params->dest_soc =
  1219. dp_mlo_get_soc_ref_by_chip_id(be_soc->ml_ctxt,
  1220. dest_chip_id);
  1221. if (!params->dest_soc)
  1222. return false;
  1223. da_peer = dp_txrx_peer_get_ref_by_id(params->dest_soc,
  1224. da_peer_id,
  1225. &txrx_ref_handle,
  1226. DP_MOD_ID_RX);
  1227. if (!da_peer)
  1228. return false;
  1229. } else {
  1230. da_peer = dp_txrx_peer_get_ref_by_id(params->dest_soc,
  1231. da_peer_id,
  1232. &txrx_ref_handle,
  1233. DP_MOD_ID_RX);
  1234. if (!da_peer)
  1235. return false;
  1236. params->dest_soc = da_peer->vdev->pdev->soc;
  1237. if (!params->dest_soc)
  1238. goto rel_da_peer;
  1239. }
  1240. params->tx_vdev_id = da_peer->vdev->vdev_id;
  1241. /* If the source or destination peer in the isolation
  1242. * list then dont forward instead push to bridge stack.
  1243. */
  1244. if (dp_get_peer_isolation(ta_peer) ||
  1245. dp_get_peer_isolation(da_peer)) {
  1246. ret = false;
  1247. goto rel_da_peer;
  1248. }
  1249. if (da_peer->bss_peer || (da_peer == ta_peer)) {
  1250. ret = false;
  1251. goto rel_da_peer;
  1252. }
  1253. /* Same vdev, support Inra-BSS */
  1254. if (da_peer->vdev == ta_peer->vdev) {
  1255. ret = true;
  1256. goto rel_da_peer;
  1257. }
  1258. /* MLO specific Intra-BSS check */
  1259. if (dp_rx_intrabss_fwd_mlo_allow(ta_peer, da_peer)) {
  1260. /* use dest chip id for legacy dest peer */
  1261. if (!(da_peer_id & HAL_RX_DA_IDX_ML_PEER_MASK)) {
  1262. if (!(be_vdev->partner_vdev_list[dest_chip_id][0] ==
  1263. params->tx_vdev_id) &&
  1264. !(be_vdev->partner_vdev_list[dest_chip_id][1] ==
  1265. params->tx_vdev_id)) {
  1266. /*dp_soc_unref_delete(soc);*/
  1267. goto rel_da_peer;
  1268. }
  1269. }
  1270. ret = true;
  1271. }
  1272. rel_da_peer:
  1273. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_RX);
  1274. return ret;
  1275. }
  1276. #else
  1277. static bool
  1278. dp_rx_intrabss_ucast_check_be(qdf_nbuf_t nbuf,
  1279. struct dp_txrx_peer *ta_peer,
  1280. struct hal_rx_msdu_metadata *msdu_metadata,
  1281. struct dp_be_intrabss_params *params)
  1282. {
  1283. uint16_t da_peer_id;
  1284. struct dp_txrx_peer *da_peer;
  1285. bool ret = false;
  1286. dp_txrx_ref_handle txrx_ref_handle = NULL;
  1287. if (!qdf_nbuf_is_da_valid(nbuf) || qdf_nbuf_is_da_mcbc(nbuf))
  1288. return false;
  1289. da_peer_id = dp_rx_peer_metadata_peer_id_get_be(
  1290. params->dest_soc,
  1291. msdu_metadata->da_idx);
  1292. da_peer = dp_txrx_peer_get_ref_by_id(params->dest_soc, da_peer_id,
  1293. &txrx_ref_handle, DP_MOD_ID_RX);
  1294. if (!da_peer)
  1295. return false;
  1296. params->tx_vdev_id = da_peer->vdev->vdev_id;
  1297. /* If the source or destination peer in the isolation
  1298. * list then dont forward instead push to bridge stack.
  1299. */
  1300. if (dp_get_peer_isolation(ta_peer) ||
  1301. dp_get_peer_isolation(da_peer))
  1302. goto rel_da_peer;
  1303. if (da_peer->bss_peer || da_peer == ta_peer)
  1304. goto rel_da_peer;
  1305. /* Same vdev, support Inra-BSS */
  1306. if (da_peer->vdev == ta_peer->vdev) {
  1307. ret = true;
  1308. goto rel_da_peer;
  1309. }
  1310. /* MLO specific Intra-BSS check */
  1311. if (dp_rx_intrabss_fwd_mlo_allow(ta_peer, da_peer)) {
  1312. ret = true;
  1313. goto rel_da_peer;
  1314. }
  1315. rel_da_peer:
  1316. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_RX);
  1317. return ret;
  1318. }
  1319. #endif /* WLAN_MLO_MULTI_CHIP */
  1320. #endif /* INTRA_BSS_FWD_OFFLOAD */
  1321. /*
  1322. * dp_rx_intrabss_handle_nawds_be() - Forward mcbc intrabss pkts in nawds case
  1323. * @soc: core txrx main context
  1324. * @ta_txrx_peer: source txrx_peer entry
  1325. * @nbuf_copy: nbuf that has to be intrabss forwarded
  1326. * @tid_stats: tid_stats structure
  1327. *
  1328. * Return: true if it is forwarded else false
  1329. */
  1330. bool
  1331. dp_rx_intrabss_handle_nawds_be(struct dp_soc *soc,
  1332. struct dp_txrx_peer *ta_txrx_peer,
  1333. qdf_nbuf_t nbuf_copy,
  1334. struct cdp_tid_rx_stats *tid_stats)
  1335. {
  1336. if (qdf_unlikely(ta_txrx_peer->vdev->nawds_enabled)) {
  1337. struct cdp_tx_exception_metadata tx_exc_metadata = {0};
  1338. uint16_t len = QDF_NBUF_CB_RX_PKT_LEN(nbuf_copy);
  1339. tx_exc_metadata.peer_id = ta_txrx_peer->peer_id;
  1340. tx_exc_metadata.is_intrabss_fwd = 1;
  1341. tx_exc_metadata.tid = HTT_TX_EXT_TID_INVALID;
  1342. if (dp_tx_send_exception((struct cdp_soc_t *)soc,
  1343. ta_txrx_peer->vdev->vdev_id,
  1344. nbuf_copy,
  1345. &tx_exc_metadata)) {
  1346. DP_PEER_PER_PKT_STATS_INC_PKT(ta_txrx_peer,
  1347. rx.intra_bss.fail, 1,
  1348. len);
  1349. tid_stats->fail_cnt[INTRABSS_DROP]++;
  1350. qdf_nbuf_free(nbuf_copy);
  1351. } else {
  1352. DP_PEER_PER_PKT_STATS_INC_PKT(ta_txrx_peer,
  1353. rx.intra_bss.pkts, 1,
  1354. len);
  1355. tid_stats->intrabss_cnt++;
  1356. }
  1357. return true;
  1358. }
  1359. return false;
  1360. }
  1361. /*
  1362. * dp_rx_intrabss_fwd_be() - API for intrabss fwd. For EAPOL
  1363. * pkt with DA not equal to vdev mac addr, fwd is not allowed.
  1364. * @soc: core txrx main context
  1365. * @ta_peer: source peer entry
  1366. * @rx_tlv_hdr: start address of rx tlvs
  1367. * @nbuf: nbuf that has to be intrabss forwarded
  1368. * @msdu_metadata: msdu metadata
  1369. *
  1370. * Return: true if it is forwarded else false
  1371. */
  1372. bool dp_rx_intrabss_fwd_be(struct dp_soc *soc, struct dp_txrx_peer *ta_peer,
  1373. uint8_t *rx_tlv_hdr, qdf_nbuf_t nbuf,
  1374. struct hal_rx_msdu_metadata msdu_metadata)
  1375. {
  1376. uint8_t tid = qdf_nbuf_get_tid_val(nbuf);
  1377. uint8_t ring_id = QDF_NBUF_CB_RX_CTX_ID(nbuf);
  1378. struct cdp_tid_rx_stats *tid_stats = &ta_peer->vdev->pdev->stats.
  1379. tid_stats.tid_rx_stats[ring_id][tid];
  1380. bool ret = false;
  1381. struct dp_be_intrabss_params params;
  1382. /* if it is a broadcast pkt (eg: ARP) and it is not its own
  1383. * source, then clone the pkt and send the cloned pkt for
  1384. * intra BSS forwarding and original pkt up the network stack
  1385. * Note: how do we handle multicast pkts. do we forward
  1386. * all multicast pkts as is or let a higher layer module
  1387. * like igmpsnoop decide whether to forward or not with
  1388. * Mcast enhancement.
  1389. */
  1390. if (qdf_nbuf_is_da_mcbc(nbuf) && !ta_peer->bss_peer) {
  1391. return dp_rx_intrabss_mcbc_fwd(soc, ta_peer, rx_tlv_hdr,
  1392. nbuf, tid_stats);
  1393. }
  1394. if (dp_rx_intrabss_eapol_drop_check(soc, ta_peer, rx_tlv_hdr,
  1395. nbuf))
  1396. return true;
  1397. params.dest_soc = soc;
  1398. if (dp_rx_intrabss_ucast_check_be(nbuf, ta_peer,
  1399. &msdu_metadata, &params)) {
  1400. ret = dp_rx_intrabss_ucast_fwd(params.dest_soc, ta_peer,
  1401. params.tx_vdev_id,
  1402. rx_tlv_hdr, nbuf, tid_stats);
  1403. }
  1404. return ret;
  1405. }
  1406. #endif