dp_be.c 53 KB

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  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include <wlan_utility.h>
  20. #include <dp_internal.h>
  21. #include <dp_htt.h>
  22. #include "dp_be.h"
  23. #include "dp_be_tx.h"
  24. #include "dp_be_rx.h"
  25. #ifdef WIFI_MONITOR_SUPPORT
  26. #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT)
  27. #include "dp_mon_2.0.h"
  28. #endif
  29. #include "dp_mon.h"
  30. #endif
  31. #include <hal_be_api.h>
  32. /* Generic AST entry aging timer value */
  33. #define DP_AST_AGING_TIMER_DEFAULT_MS 5000
  34. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  35. #define DP_TX_VDEV_ID_CHECK_ENABLE 0
  36. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  37. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  38. {1, 4, HAL_BE_WBM_SW4_BM_ID, 0},
  39. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  40. #ifdef QCA_WIFI_KIWI_V2
  41. {3, 5, HAL_BE_WBM_SW5_BM_ID, 0},
  42. {4, 6, HAL_BE_WBM_SW6_BM_ID, 0}
  43. #else
  44. {3, 6, HAL_BE_WBM_SW5_BM_ID, 0},
  45. {4, 7, HAL_BE_WBM_SW6_BM_ID, 0}
  46. #endif
  47. };
  48. #else
  49. #define DP_TX_VDEV_ID_CHECK_ENABLE 1
  50. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  51. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  52. {1, 1, HAL_BE_WBM_SW1_BM_ID, 0},
  53. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  54. {3, 3, HAL_BE_WBM_SW3_BM_ID, 0},
  55. {4, 4, HAL_BE_WBM_SW4_BM_ID, 0}
  56. };
  57. #endif
  58. static void dp_soc_cfg_attach_be(struct dp_soc *soc)
  59. {
  60. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  61. wlan_cfg_set_rx_rel_ring_id(soc_cfg_ctx, WBM2SW_REL_ERR_RING_NUM);
  62. soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array;
  63. /* this is used only when dmac mode is enabled */
  64. soc->num_rx_refill_buf_rings = 1;
  65. soc->wlan_cfg_ctx->notify_frame_support =
  66. DP_MARK_NOTIFY_FRAME_SUPPORT;
  67. }
  68. qdf_size_t dp_get_context_size_be(enum dp_context_type context_type)
  69. {
  70. switch (context_type) {
  71. case DP_CONTEXT_TYPE_SOC:
  72. return sizeof(struct dp_soc_be);
  73. case DP_CONTEXT_TYPE_PDEV:
  74. return sizeof(struct dp_pdev_be);
  75. case DP_CONTEXT_TYPE_VDEV:
  76. return sizeof(struct dp_vdev_be);
  77. case DP_CONTEXT_TYPE_PEER:
  78. return sizeof(struct dp_peer_be);
  79. default:
  80. return 0;
  81. }
  82. }
  83. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  84. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  85. /**
  86. * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement
  87. per wbm2sw ring
  88. * @cc_cfg: HAL HW cookie conversion configuration structure pointer
  89. *
  90. * Return: None
  91. */
  92. static inline
  93. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  94. {
  95. cc_cfg->wbm2sw6_cc_en = 1;
  96. cc_cfg->wbm2sw5_cc_en = 1;
  97. cc_cfg->wbm2sw4_cc_en = 1;
  98. cc_cfg->wbm2sw3_cc_en = 1;
  99. cc_cfg->wbm2sw2_cc_en = 1;
  100. /* disable wbm2sw1 hw cc as it's for FW */
  101. cc_cfg->wbm2sw1_cc_en = 0;
  102. cc_cfg->wbm2sw0_cc_en = 1;
  103. cc_cfg->wbm2fw_cc_en = 0;
  104. }
  105. #else
  106. static inline
  107. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  108. {
  109. cc_cfg->wbm2sw6_cc_en = 1;
  110. cc_cfg->wbm2sw5_cc_en = 1;
  111. cc_cfg->wbm2sw4_cc_en = 1;
  112. cc_cfg->wbm2sw3_cc_en = 1;
  113. cc_cfg->wbm2sw2_cc_en = 1;
  114. cc_cfg->wbm2sw1_cc_en = 1;
  115. cc_cfg->wbm2sw0_cc_en = 1;
  116. cc_cfg->wbm2fw_cc_en = 0;
  117. }
  118. #endif
  119. #if defined(WLAN_SUPPORT_RX_FISA)
  120. static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
  121. {
  122. dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
  123. soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
  124. /* get CMEM for cookie conversion */
  125. if (soc->cmem_avail_size < DP_CMEM_FST_SIZE) {
  126. dp_err("cmem_size 0x%llx bytes < 16K", soc->cmem_avail_size);
  127. return QDF_STATUS_E_NOMEM;
  128. }
  129. soc->fst_cmem_size = DP_CMEM_FST_SIZE;
  130. soc->fst_cmem_base = soc->cmem_base +
  131. (soc->cmem_total_size - soc->cmem_avail_size);
  132. soc->cmem_avail_size -= soc->fst_cmem_size;
  133. dp_info("fst_cmem_base 0x%llx, fst_cmem_size 0x%llx",
  134. soc->fst_cmem_base, soc->fst_cmem_size);
  135. return QDF_STATUS_SUCCESS;
  136. }
  137. #else /* !WLAN_SUPPORT_RX_FISA */
  138. static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
  139. {
  140. return QDF_STATUS_SUCCESS;
  141. }
  142. #endif
  143. /**
  144. * dp_cc_reg_cfg_init() - initialize and configure HW cookie
  145. conversion register
  146. * @soc: SOC handle
  147. * @is_4k_align: page address 4k alignd
  148. *
  149. * Return: None
  150. */
  151. static void dp_cc_reg_cfg_init(struct dp_soc *soc,
  152. bool is_4k_align)
  153. {
  154. struct hal_hw_cc_config cc_cfg = { 0 };
  155. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  156. if (soc->cdp_soc.ol_ops->get_con_mode &&
  157. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  158. return;
  159. if (!soc->wlan_cfg_ctx->hw_cc_enabled) {
  160. dp_info("INI skip HW CC register setting");
  161. return;
  162. }
  163. cc_cfg.lut_base_addr_31_0 = be_soc->cc_cmem_base;
  164. cc_cfg.cc_global_en = true;
  165. cc_cfg.page_4k_align = is_4k_align;
  166. cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB;
  167. cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB;
  168. /* 36th bit should be 1 then HW know this is CMEM address */
  169. cc_cfg.lut_base_addr_39_32 = 0x10;
  170. cc_cfg.error_path_cookie_conv_en = true;
  171. cc_cfg.release_path_cookie_conv_en = true;
  172. dp_cc_wbm_sw_en_cfg(&cc_cfg);
  173. hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg);
  174. }
  175. /**
  176. * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing
  177. * @hal_soc_hdl: HAL SOC handle
  178. * @offset: CMEM address
  179. * @value: value to write
  180. *
  181. * Return: None.
  182. */
  183. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  184. uint32_t offset,
  185. uint32_t value)
  186. {
  187. hal_cmem_write(hal_soc_hdl, offset, value);
  188. }
  189. /**
  190. * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for
  191. HW cookie conversion
  192. * @soc: SOC handle
  193. * @cc_ctx: cookie conversion context pointer
  194. *
  195. * Return: 0 in case of success, else error value
  196. */
  197. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  198. {
  199. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  200. dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
  201. soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
  202. /* get CMEM for cookie conversion */
  203. if (soc->cmem_avail_size < DP_CC_PPT_MEM_SIZE) {
  204. dp_err("cmem_size 0x%llx bytes < 4K", soc->cmem_avail_size);
  205. return QDF_STATUS_E_RESOURCES;
  206. }
  207. be_soc->cc_cmem_base = (uint32_t)(soc->cmem_base +
  208. DP_CC_MEM_OFFSET_IN_CMEM);
  209. soc->cmem_avail_size -= DP_CC_PPT_MEM_SIZE;
  210. dp_info("cc_cmem_base 0x%x, cmem_avail_size 0x%llx",
  211. be_soc->cc_cmem_base, soc->cmem_avail_size);
  212. return QDF_STATUS_SUCCESS;
  213. }
  214. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  215. uint8_t for_feature)
  216. {
  217. QDF_STATUS status = QDF_STATUS_E_NOMEM;
  218. switch (for_feature) {
  219. case COOKIE_CONVERSION:
  220. status = dp_hw_cc_cmem_addr_init(soc);
  221. break;
  222. case FISA_FST:
  223. status = dp_fisa_fst_cmem_addr_init(soc);
  224. break;
  225. default:
  226. dp_err("Invalid CMEM request");
  227. }
  228. return status;
  229. }
  230. #else
  231. static inline void dp_cc_reg_cfg_init(struct dp_soc *soc,
  232. bool is_4k_align) {}
  233. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  234. uint32_t offset,
  235. uint32_t value)
  236. { }
  237. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  238. {
  239. return QDF_STATUS_SUCCESS;
  240. }
  241. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  242. uint8_t for_feature)
  243. {
  244. return QDF_STATUS_SUCCESS;
  245. }
  246. #endif
  247. QDF_STATUS
  248. dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc,
  249. struct dp_hw_cookie_conversion_t *cc_ctx,
  250. uint32_t num_descs,
  251. enum dp_desc_type desc_type,
  252. uint8_t desc_pool_id)
  253. {
  254. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  255. uint32_t num_spt_pages, i = 0;
  256. struct dp_spt_page_desc *spt_desc;
  257. struct qdf_mem_dma_page_t *dma_page;
  258. uint8_t chip_id;
  259. /* estimate how many SPT DDR pages needed */
  260. num_spt_pages = num_descs / DP_CC_SPT_PAGE_MAX_ENTRIES;
  261. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  262. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  263. dp_info("num_spt_pages needed %d", num_spt_pages);
  264. dp_desc_multi_pages_mem_alloc(soc, DP_HW_CC_SPT_PAGE_TYPE,
  265. &cc_ctx->page_pool, qdf_page_size,
  266. num_spt_pages, 0, false);
  267. if (!cc_ctx->page_pool.dma_pages) {
  268. dp_err("spt ddr pages allocation failed");
  269. return QDF_STATUS_E_RESOURCES;
  270. }
  271. cc_ctx->page_desc_base = qdf_mem_malloc(
  272. num_spt_pages * sizeof(struct dp_spt_page_desc));
  273. if (!cc_ctx->page_desc_base) {
  274. dp_err("spt page descs allocation failed");
  275. goto fail_0;
  276. }
  277. chip_id = dp_mlo_get_chip_id(soc);
  278. cc_ctx->cmem_offset = dp_desc_pool_get_cmem_base(chip_id, desc_pool_id,
  279. desc_type);
  280. /* initial page desc */
  281. spt_desc = cc_ctx->page_desc_base;
  282. dma_page = cc_ctx->page_pool.dma_pages;
  283. while (i < num_spt_pages) {
  284. /* check if page address 4K aligned */
  285. if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) {
  286. dp_err("non-4k aligned pages addr %pK",
  287. (void *)dma_page[i].page_p_addr);
  288. goto fail_1;
  289. }
  290. spt_desc[i].page_v_addr =
  291. dma_page[i].page_v_addr_start;
  292. spt_desc[i].page_p_addr =
  293. dma_page[i].page_p_addr;
  294. i++;
  295. }
  296. cc_ctx->total_page_num = num_spt_pages;
  297. qdf_spinlock_create(&cc_ctx->cc_lock);
  298. return QDF_STATUS_SUCCESS;
  299. fail_1:
  300. qdf_mem_free(cc_ctx->page_desc_base);
  301. fail_0:
  302. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  303. &cc_ctx->page_pool, 0, false);
  304. return QDF_STATUS_E_FAILURE;
  305. }
  306. QDF_STATUS
  307. dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc,
  308. struct dp_hw_cookie_conversion_t *cc_ctx)
  309. {
  310. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  311. qdf_mem_free(cc_ctx->page_desc_base);
  312. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  313. &cc_ctx->page_pool, 0, false);
  314. qdf_spinlock_destroy(&cc_ctx->cc_lock);
  315. return QDF_STATUS_SUCCESS;
  316. }
  317. QDF_STATUS
  318. dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc,
  319. struct dp_hw_cookie_conversion_t *cc_ctx)
  320. {
  321. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  322. uint32_t i = 0;
  323. struct dp_spt_page_desc *spt_desc;
  324. uint32_t ppt_index;
  325. uint32_t ppt_id_start;
  326. if (!cc_ctx->total_page_num) {
  327. dp_err("total page num is 0");
  328. return QDF_STATUS_E_INVAL;
  329. }
  330. ppt_id_start = DP_CMEM_OFFSET_TO_PPT_ID(cc_ctx->cmem_offset);
  331. spt_desc = cc_ctx->page_desc_base;
  332. while (i < cc_ctx->total_page_num) {
  333. /* write page PA to CMEM */
  334. dp_hw_cc_cmem_write(soc->hal_soc,
  335. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  336. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  337. (spt_desc[i].page_p_addr >>
  338. DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED));
  339. ppt_index = ppt_id_start + i;
  340. if (ppt_index >= DP_CC_PPT_MAX_ENTRIES)
  341. qdf_assert_always(0);
  342. spt_desc[i].ppt_index = ppt_index;
  343. be_soc->page_desc_base[ppt_index].page_v_addr =
  344. spt_desc[i].page_v_addr;
  345. i++;
  346. }
  347. return QDF_STATUS_SUCCESS;
  348. }
  349. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  350. QDF_STATUS
  351. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  352. struct dp_hw_cookie_conversion_t *cc_ctx)
  353. {
  354. uint32_t ppt_index;
  355. struct dp_spt_page_desc *spt_desc;
  356. int i = 0;
  357. spt_desc = cc_ctx->page_desc_base;
  358. while (i < cc_ctx->total_page_num) {
  359. ppt_index = spt_desc[i].ppt_index;
  360. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  361. i++;
  362. }
  363. return QDF_STATUS_SUCCESS;
  364. }
  365. #else
  366. QDF_STATUS
  367. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  368. struct dp_hw_cookie_conversion_t *cc_ctx)
  369. {
  370. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  371. uint32_t ppt_index;
  372. struct dp_spt_page_desc *spt_desc;
  373. int i = 0;
  374. spt_desc = cc_ctx->page_desc_base;
  375. while (i < cc_ctx->total_page_num) {
  376. /* reset PA in CMEM to NULL */
  377. dp_hw_cc_cmem_write(soc->hal_soc,
  378. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  379. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  380. 0);
  381. ppt_index = spt_desc[i].ppt_index;
  382. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  383. i++;
  384. }
  385. return QDF_STATUS_SUCCESS;
  386. }
  387. #endif
  388. static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc)
  389. {
  390. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  391. int i = 0;
  392. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  393. dp_hw_cookie_conversion_detach(be_soc,
  394. &be_soc->tx_cc_ctx[i]);
  395. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  396. dp_hw_cookie_conversion_detach(be_soc,
  397. &be_soc->rx_cc_ctx[i]);
  398. qdf_mem_free(be_soc->page_desc_base);
  399. be_soc->page_desc_base = NULL;
  400. return QDF_STATUS_SUCCESS;
  401. }
  402. #ifdef WLAN_MLO_MULTI_CHIP
  403. #ifdef WLAN_MCAST_MLO
  404. static inline void
  405. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  406. {
  407. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  408. be_vdev->mcast_primary = false;
  409. be_vdev->seq_num = 0;
  410. dp_tx_mcast_mlo_reinject_routing_set(soc,
  411. (void *)&be_vdev->mcast_primary);
  412. if (vdev->opmode == wlan_op_mode_ap) {
  413. if (vdev->mlo_vdev)
  414. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  415. vdev->vdev_id,
  416. HAL_TX_MCAST_CTRL_DROP);
  417. else
  418. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  419. vdev->vdev_id,
  420. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  421. }
  422. }
  423. static inline void
  424. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  425. {
  426. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  427. be_vdev->seq_num = 0;
  428. be_vdev->mcast_primary = false;
  429. vdev->mlo_vdev = false;
  430. }
  431. #else
  432. static inline void
  433. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  434. {
  435. }
  436. static inline void
  437. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  438. {
  439. }
  440. #endif
  441. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  442. {
  443. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  444. qdf_mem_set(be_vdev->partner_vdev_list,
  445. WLAN_MAX_MLO_CHIPS * WLAN_MAX_MLO_LINKS_PER_SOC,
  446. CDP_INVALID_VDEV_ID);
  447. }
  448. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  449. struct cdp_lro_hash_config *lro_hash)
  450. {
  451. dp_mlo_get_rx_hash_key(soc, lro_hash);
  452. }
  453. #else
  454. static inline void
  455. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  456. {
  457. }
  458. static inline void
  459. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  460. {
  461. }
  462. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  463. {
  464. }
  465. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  466. struct cdp_lro_hash_config *lro_hash)
  467. {
  468. dp_get_rx_hash_key_bytes(lro_hash);
  469. }
  470. #endif
  471. static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc,
  472. struct cdp_soc_attach_params *params)
  473. {
  474. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  475. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  476. uint32_t max_tx_rx_desc_num, num_spt_pages;
  477. uint32_t num_entries;
  478. int i = 0;
  479. max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS +
  480. WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS;
  481. /* estimate how many SPT DDR pages needed */
  482. num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES;
  483. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  484. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  485. be_soc->page_desc_base = qdf_mem_malloc(
  486. DP_CC_PPT_MAX_ENTRIES * sizeof(struct dp_spt_page_desc));
  487. if (!be_soc->page_desc_base) {
  488. dp_err("spt page descs allocation failed");
  489. return QDF_STATUS_E_NOMEM;
  490. }
  491. soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id();
  492. qdf_status = dp_get_cmem_allocation(soc, COOKIE_CONVERSION);
  493. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  494. goto fail;
  495. dp_soc_mlo_fill_params(soc, params);
  496. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  497. num_entries = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  498. qdf_status =
  499. dp_hw_cookie_conversion_attach(be_soc,
  500. &be_soc->tx_cc_ctx[i],
  501. num_entries,
  502. DP_TX_DESC_TYPE, i);
  503. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  504. goto fail;
  505. }
  506. qdf_status = dp_get_cmem_allocation(soc, FISA_FST);
  507. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  508. goto fail;
  509. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  510. num_entries =
  511. wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx);
  512. qdf_status =
  513. dp_hw_cookie_conversion_attach(be_soc,
  514. &be_soc->rx_cc_ctx[i],
  515. num_entries,
  516. DP_RX_DESC_BUF_TYPE, i);
  517. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  518. goto fail;
  519. }
  520. return qdf_status;
  521. fail:
  522. dp_soc_detach_be(soc);
  523. return qdf_status;
  524. }
  525. static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc)
  526. {
  527. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  528. int i = 0;
  529. dp_tx_deinit_bank_profiles(be_soc);
  530. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  531. dp_hw_cookie_conversion_deinit(be_soc,
  532. &be_soc->tx_cc_ctx[i]);
  533. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  534. dp_hw_cookie_conversion_deinit(be_soc,
  535. &be_soc->rx_cc_ctx[i]);
  536. return QDF_STATUS_SUCCESS;
  537. }
  538. static QDF_STATUS dp_soc_init_be(struct dp_soc *soc)
  539. {
  540. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  541. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  542. int i = 0;
  543. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  544. qdf_status =
  545. dp_hw_cookie_conversion_init(be_soc,
  546. &be_soc->tx_cc_ctx[i]);
  547. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  548. goto fail;
  549. }
  550. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  551. qdf_status =
  552. dp_hw_cookie_conversion_init(be_soc,
  553. &be_soc->rx_cc_ctx[i]);
  554. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  555. goto fail;
  556. }
  557. /* route vdev_id mismatch notification via FW completion */
  558. hal_tx_vdev_mismatch_routing_set(soc->hal_soc,
  559. HAL_TX_VDEV_MISMATCH_FW_NOTIFY);
  560. qdf_status = dp_tx_init_bank_profiles(be_soc);
  561. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  562. goto fail;
  563. /* write WBM/REO cookie conversion CFG register */
  564. dp_cc_reg_cfg_init(soc, true);
  565. return qdf_status;
  566. fail:
  567. dp_soc_deinit_be(soc);
  568. return qdf_status;
  569. }
  570. static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev,
  571. struct cdp_pdev_attach_params *params)
  572. {
  573. dp_pdev_mlo_fill_params(pdev, params);
  574. dp_mlo_update_link_to_pdev_map(pdev->soc, pdev);
  575. return QDF_STATUS_SUCCESS;
  576. }
  577. static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev)
  578. {
  579. dp_mlo_update_link_to_pdev_unmap(pdev->soc, pdev);
  580. return QDF_STATUS_SUCCESS;
  581. }
  582. static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  583. {
  584. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  585. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  586. struct dp_pdev *pdev = vdev->pdev;
  587. if (vdev->opmode == wlan_op_mode_monitor)
  588. return QDF_STATUS_SUCCESS;
  589. be_vdev->vdev_id_check_en = DP_TX_VDEV_ID_CHECK_ENABLE;
  590. be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
  591. vdev->bank_id = be_vdev->bank_id;
  592. if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) {
  593. QDF_BUG(0);
  594. return QDF_STATUS_E_FAULT;
  595. }
  596. if (vdev->opmode == wlan_op_mode_sta) {
  597. if (soc->cdp_soc.ol_ops->set_mec_timer)
  598. soc->cdp_soc.ol_ops->set_mec_timer(
  599. soc->ctrl_psoc,
  600. vdev->vdev_id,
  601. DP_AST_AGING_TIMER_DEFAULT_MS);
  602. if (pdev->isolation)
  603. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  604. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  605. else
  606. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  607. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  608. }
  609. dp_mlo_mcast_init(soc, vdev);
  610. dp_mlo_init_ptnr_list(vdev);
  611. return QDF_STATUS_SUCCESS;
  612. }
  613. static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  614. {
  615. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  616. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  617. if (vdev->opmode == wlan_op_mode_monitor)
  618. return QDF_STATUS_SUCCESS;
  619. if (vdev->opmode == wlan_op_mode_ap)
  620. dp_mlo_mcast_deinit(soc, vdev);
  621. dp_tx_put_bank_profile(be_soc, be_vdev);
  622. dp_clr_mlo_ptnr_list(soc, vdev);
  623. return QDF_STATUS_SUCCESS;
  624. }
  625. qdf_size_t dp_get_soc_context_size_be(void)
  626. {
  627. return sizeof(struct dp_soc_be);
  628. }
  629. #ifdef NO_RX_PKT_HDR_TLV
  630. /**
  631. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  632. * @soc: Common DP soc handle
  633. *
  634. * Return: QDF_STATUS
  635. */
  636. static QDF_STATUS
  637. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  638. {
  639. int i;
  640. int mac_id;
  641. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  642. struct dp_srng *rx_mac_srng;
  643. QDF_STATUS status = QDF_STATUS_SUCCESS;
  644. /*
  645. * In Beryllium chipset msdu_start, mpdu_end
  646. * and rx_attn are part of msdu_end/mpdu_start
  647. */
  648. htt_tlv_filter.msdu_start = 0;
  649. htt_tlv_filter.mpdu_end = 0;
  650. htt_tlv_filter.attention = 0;
  651. htt_tlv_filter.mpdu_start = 1;
  652. htt_tlv_filter.msdu_end = 1;
  653. htt_tlv_filter.packet = 1;
  654. htt_tlv_filter.packet_header = 0;
  655. htt_tlv_filter.ppdu_start = 0;
  656. htt_tlv_filter.ppdu_end = 0;
  657. htt_tlv_filter.ppdu_end_user_stats = 0;
  658. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  659. htt_tlv_filter.ppdu_end_status_done = 0;
  660. htt_tlv_filter.enable_fp = 1;
  661. htt_tlv_filter.enable_md = 0;
  662. htt_tlv_filter.enable_md = 0;
  663. htt_tlv_filter.enable_mo = 0;
  664. htt_tlv_filter.fp_mgmt_filter = 0;
  665. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  666. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  667. FILTER_DATA_MCAST |
  668. FILTER_DATA_DATA);
  669. htt_tlv_filter.mo_mgmt_filter = 0;
  670. htt_tlv_filter.mo_ctrl_filter = 0;
  671. htt_tlv_filter.mo_data_filter = 0;
  672. htt_tlv_filter.md_data_filter = 0;
  673. htt_tlv_filter.offset_valid = true;
  674. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  675. htt_tlv_filter.rx_mpdu_end_offset = 0;
  676. htt_tlv_filter.rx_msdu_start_offset = 0;
  677. htt_tlv_filter.rx_attn_offset = 0;
  678. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  679. /*Not subscribing rx_pkt_header*/
  680. htt_tlv_filter.rx_header_offset = 0;
  681. htt_tlv_filter.rx_mpdu_start_offset =
  682. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  683. htt_tlv_filter.rx_msdu_end_offset =
  684. hal_rx_msdu_end_offset_get(soc->hal_soc);
  685. for (i = 0; i < MAX_PDEV_CNT; i++) {
  686. struct dp_pdev *pdev = soc->pdev_list[i];
  687. if (!pdev)
  688. continue;
  689. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  690. int mac_for_pdev =
  691. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  692. /*
  693. * Obtain lmac id from pdev to access the LMAC ring
  694. * in soc context
  695. */
  696. int lmac_id =
  697. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  698. pdev->pdev_id);
  699. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  700. if (!rx_mac_srng->hal_srng)
  701. continue;
  702. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  703. rx_mac_srng->hal_srng,
  704. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  705. &htt_tlv_filter);
  706. }
  707. }
  708. return status;
  709. }
  710. #else
  711. /**
  712. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  713. * @soc: Common DP soc handle
  714. *
  715. * Return: QDF_STATUS
  716. */
  717. static QDF_STATUS
  718. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  719. {
  720. int i;
  721. int mac_id;
  722. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  723. struct dp_srng *rx_mac_srng;
  724. QDF_STATUS status = QDF_STATUS_SUCCESS;
  725. /*
  726. * In Beryllium chipset msdu_start, mpdu_end
  727. * and rx_attn are part of msdu_end/mpdu_start
  728. */
  729. htt_tlv_filter.msdu_start = 0;
  730. htt_tlv_filter.mpdu_end = 0;
  731. htt_tlv_filter.attention = 0;
  732. htt_tlv_filter.mpdu_start = 1;
  733. htt_tlv_filter.msdu_end = 1;
  734. htt_tlv_filter.packet = 1;
  735. htt_tlv_filter.packet_header = 1;
  736. htt_tlv_filter.ppdu_start = 0;
  737. htt_tlv_filter.ppdu_end = 0;
  738. htt_tlv_filter.ppdu_end_user_stats = 0;
  739. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  740. htt_tlv_filter.ppdu_end_status_done = 0;
  741. htt_tlv_filter.enable_fp = 1;
  742. htt_tlv_filter.enable_md = 0;
  743. htt_tlv_filter.enable_md = 0;
  744. htt_tlv_filter.enable_mo = 0;
  745. htt_tlv_filter.fp_mgmt_filter = 0;
  746. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  747. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  748. FILTER_DATA_MCAST |
  749. FILTER_DATA_DATA);
  750. htt_tlv_filter.mo_mgmt_filter = 0;
  751. htt_tlv_filter.mo_ctrl_filter = 0;
  752. htt_tlv_filter.mo_data_filter = 0;
  753. htt_tlv_filter.md_data_filter = 0;
  754. htt_tlv_filter.offset_valid = true;
  755. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  756. htt_tlv_filter.rx_mpdu_end_offset = 0;
  757. htt_tlv_filter.rx_msdu_start_offset = 0;
  758. htt_tlv_filter.rx_attn_offset = 0;
  759. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  760. htt_tlv_filter.rx_header_offset =
  761. hal_rx_pkt_tlv_offset_get(soc->hal_soc);
  762. htt_tlv_filter.rx_mpdu_start_offset =
  763. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  764. htt_tlv_filter.rx_msdu_end_offset =
  765. hal_rx_msdu_end_offset_get(soc->hal_soc);
  766. dp_info("TLV subscription\n"
  767. "msdu_start %d, mpdu_end %d, attention %d"
  768. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n"
  769. "TLV offsets\n"
  770. "msdu_start %d, mpdu_end %d, attention %d"
  771. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n",
  772. htt_tlv_filter.msdu_start,
  773. htt_tlv_filter.mpdu_end,
  774. htt_tlv_filter.attention,
  775. htt_tlv_filter.mpdu_start,
  776. htt_tlv_filter.msdu_end,
  777. htt_tlv_filter.packet_header,
  778. htt_tlv_filter.packet,
  779. htt_tlv_filter.rx_msdu_start_offset,
  780. htt_tlv_filter.rx_mpdu_end_offset,
  781. htt_tlv_filter.rx_attn_offset,
  782. htt_tlv_filter.rx_mpdu_start_offset,
  783. htt_tlv_filter.rx_msdu_end_offset,
  784. htt_tlv_filter.rx_header_offset,
  785. htt_tlv_filter.rx_packet_offset);
  786. for (i = 0; i < MAX_PDEV_CNT; i++) {
  787. struct dp_pdev *pdev = soc->pdev_list[i];
  788. if (!pdev)
  789. continue;
  790. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  791. int mac_for_pdev =
  792. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  793. /*
  794. * Obtain lmac id from pdev to access the LMAC ring
  795. * in soc context
  796. */
  797. int lmac_id =
  798. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  799. pdev->pdev_id);
  800. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  801. if (!rx_mac_srng->hal_srng)
  802. continue;
  803. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  804. rx_mac_srng->hal_srng,
  805. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  806. &htt_tlv_filter);
  807. }
  808. }
  809. return status;
  810. }
  811. #endif
  812. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  813. /**
  814. * dp_service_near_full_srngs_be() - Main bottom half callback for the
  815. * near-full IRQs.
  816. * @soc: Datapath SoC handle
  817. * @int_ctx: Interrupt context
  818. * @dp_budget: Budget of the work that can be done in the bottom half
  819. *
  820. * Return: work done in the handler
  821. */
  822. static uint32_t
  823. dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx,
  824. uint32_t dp_budget)
  825. {
  826. int ring = 0;
  827. int budget = dp_budget;
  828. uint32_t work_done = 0;
  829. uint32_t remaining_quota = dp_budget;
  830. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  831. int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask;
  832. int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask;
  833. int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask;
  834. int rx_near_full_mask = rx_near_full_grp_1_mask |
  835. rx_near_full_grp_2_mask;
  836. dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x",
  837. rx_near_full_mask,
  838. tx_ring_near_full_mask);
  839. if (rx_near_full_mask) {
  840. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  841. if (!(rx_near_full_mask & (1 << ring)))
  842. continue;
  843. work_done = dp_rx_nf_process(int_ctx,
  844. soc->reo_dest_ring[ring].hal_srng,
  845. ring, remaining_quota);
  846. if (work_done) {
  847. intr_stats->num_rx_ring_near_full_masks[ring]++;
  848. dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d",
  849. rx_near_full_mask, ring,
  850. work_done,
  851. budget);
  852. budget -= work_done;
  853. if (budget <= 0)
  854. goto budget_done;
  855. remaining_quota = budget;
  856. }
  857. }
  858. }
  859. if (tx_ring_near_full_mask) {
  860. for (ring = 0; ring < soc->num_tcl_data_rings; ring++) {
  861. if (!(tx_ring_near_full_mask & (1 << ring)))
  862. continue;
  863. work_done = dp_tx_comp_nf_handler(int_ctx, soc,
  864. soc->tx_comp_ring[ring].hal_srng,
  865. ring, remaining_quota);
  866. if (work_done) {
  867. intr_stats->num_tx_comp_ring_near_full_masks[ring]++;
  868. dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d",
  869. tx_ring_near_full_mask, ring,
  870. work_done, budget);
  871. budget -= work_done;
  872. if (budget <= 0)
  873. break;
  874. remaining_quota = budget;
  875. }
  876. }
  877. }
  878. intr_stats->num_near_full_masks++;
  879. budget_done:
  880. return dp_budget - budget;
  881. }
  882. /**
  883. * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full
  884. * state and set the reap_limit appropriately
  885. * as per the near full state
  886. * @soc: Datapath soc handle
  887. * @dp_srng: Datapath handle for SRNG
  888. * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per
  889. * the srng near-full state
  890. *
  891. * Return: 1, if the srng is in near-full state
  892. * 0, if the srng is not in near-full state
  893. */
  894. static int
  895. dp_srng_test_and_update_nf_params_be(struct dp_soc *soc,
  896. struct dp_srng *dp_srng,
  897. int *max_reap_limit)
  898. {
  899. return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit);
  900. }
  901. /**
  902. * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the
  903. * near full IRQ handling operations.
  904. * @arch_ops: arch ops handle
  905. *
  906. * Return: none
  907. */
  908. static inline void
  909. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  910. {
  911. arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be;
  912. arch_ops->dp_srng_test_and_update_nf_params =
  913. dp_srng_test_and_update_nf_params_be;
  914. }
  915. #else
  916. static inline void
  917. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  918. {
  919. }
  920. #endif
  921. #ifdef WLAN_SUPPORT_PPEDS
  922. static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
  923. {
  924. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  925. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  926. soc_cfg_ctx = soc->wlan_cfg_ctx;
  927. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  928. return;
  929. dp_srng_deinit(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0);
  930. wlan_minidump_remove(be_soc->ppe_release_ring.base_vaddr_unaligned,
  931. be_soc->ppe_release_ring.alloc_size,
  932. soc->ctrl_psoc,
  933. WLAN_MD_DP_SRNG_PPE_RELEASE,
  934. "ppe_release_ring");
  935. dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0);
  936. wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  937. be_soc->ppe2tcl_ring.alloc_size,
  938. soc->ctrl_psoc,
  939. WLAN_MD_DP_SRNG_PPE2TCL,
  940. "ppe2tcl_ring");
  941. dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0);
  942. wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  943. be_soc->reo2ppe_ring.alloc_size,
  944. soc->ctrl_psoc,
  945. WLAN_MD_DP_SRNG_REO2PPE,
  946. "reo2ppe_ring");
  947. }
  948. static void dp_soc_ppe_srng_free(struct dp_soc *soc)
  949. {
  950. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  951. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  952. soc_cfg_ctx = soc->wlan_cfg_ctx;
  953. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  954. return;
  955. dp_srng_free(soc, &be_soc->ppe_release_ring);
  956. dp_srng_free(soc, &be_soc->ppe2tcl_ring);
  957. dp_srng_free(soc, &be_soc->reo2ppe_ring);
  958. }
  959. static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
  960. {
  961. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  962. uint32_t entries;
  963. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  964. soc_cfg_ctx = soc->wlan_cfg_ctx;
  965. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  966. return QDF_STATUS_SUCCESS;
  967. entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx);
  968. if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE,
  969. entries, 0)) {
  970. dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc);
  971. goto fail;
  972. }
  973. entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx);
  974. if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL,
  975. entries, 0)) {
  976. dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc);
  977. goto fail;
  978. }
  979. entries = wlan_cfg_get_dp_soc_ppe_release_ring_size(soc_cfg_ctx);
  980. if (dp_srng_alloc(soc, &be_soc->ppe_release_ring, PPE_RELEASE,
  981. entries, 0)) {
  982. dp_err("%pK: dp_srng_alloc failed for ppe_release_ring", soc);
  983. goto fail;
  984. }
  985. return QDF_STATUS_SUCCESS;
  986. fail:
  987. dp_soc_ppe_srng_free(soc);
  988. return QDF_STATUS_E_NOMEM;
  989. }
  990. static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
  991. {
  992. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  993. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  994. hal_soc_handle_t hal_soc = soc->hal_soc;
  995. soc_cfg_ctx = soc->wlan_cfg_ctx;
  996. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  997. return QDF_STATUS_SUCCESS;
  998. if (dp_srng_init(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0)) {
  999. dp_err("%pK: dp_srng_init failed for reo2ppe", soc);
  1000. goto fail;
  1001. }
  1002. wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  1003. be_soc->reo2ppe_ring.alloc_size,
  1004. soc->ctrl_psoc,
  1005. WLAN_MD_DP_SRNG_REO2PPE,
  1006. "reo2ppe_ring");
  1007. hal_reo_config_reo2ppe_dest_info(hal_soc);
  1008. if (dp_srng_init(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0)) {
  1009. dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc);
  1010. goto fail;
  1011. }
  1012. wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  1013. be_soc->ppe2tcl_ring.alloc_size,
  1014. soc->ctrl_psoc,
  1015. WLAN_MD_DP_SRNG_PPE2TCL,
  1016. "ppe2tcl_ring");
  1017. if (dp_srng_init(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0, 0)) {
  1018. dp_err("%pK: dp_srng_init failed for ppe_release_ring", soc);
  1019. goto fail;
  1020. }
  1021. wlan_minidump_log(be_soc->ppe_release_ring.base_vaddr_unaligned,
  1022. be_soc->ppe_release_ring.alloc_size,
  1023. soc->ctrl_psoc,
  1024. WLAN_MD_DP_SRNG_PPE_RELEASE,
  1025. "ppe_release_ring");
  1026. return QDF_STATUS_SUCCESS;
  1027. fail:
  1028. dp_soc_ppe_srng_deinit(soc);
  1029. return QDF_STATUS_E_NOMEM;
  1030. }
  1031. #else
  1032. static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
  1033. {
  1034. }
  1035. static void dp_soc_ppe_srng_free(struct dp_soc *soc)
  1036. {
  1037. }
  1038. static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
  1039. {
  1040. return QDF_STATUS_SUCCESS;
  1041. }
  1042. static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
  1043. {
  1044. return QDF_STATUS_SUCCESS;
  1045. }
  1046. #endif
  1047. static void dp_soc_srng_deinit_be(struct dp_soc *soc)
  1048. {
  1049. uint32_t i;
  1050. dp_soc_ppe_srng_deinit(soc);
  1051. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1052. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1053. dp_srng_deinit(soc, &soc->rx_refill_buf_ring[i],
  1054. RXDMA_BUF, 0);
  1055. }
  1056. }
  1057. }
  1058. static void dp_soc_srng_free_be(struct dp_soc *soc)
  1059. {
  1060. uint32_t i;
  1061. dp_soc_ppe_srng_free(soc);
  1062. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1063. for (i = 0; i < soc->num_rx_refill_buf_rings; i++)
  1064. dp_srng_free(soc, &soc->rx_refill_buf_ring[i]);
  1065. }
  1066. }
  1067. static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc)
  1068. {
  1069. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1070. uint32_t ring_size;
  1071. uint32_t i;
  1072. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1073. ring_size = wlan_cfg_get_dp_soc_rxdma_refill_ring_size(soc_cfg_ctx);
  1074. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1075. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1076. if (dp_srng_alloc(soc, &soc->rx_refill_buf_ring[i],
  1077. RXDMA_BUF, ring_size, 0)) {
  1078. dp_err("%pK: dp_srng_alloc failed refill ring",
  1079. soc);
  1080. goto fail;
  1081. }
  1082. }
  1083. }
  1084. if (dp_soc_ppe_srng_alloc(soc)) {
  1085. dp_err("%pK: ppe rings alloc failed",
  1086. soc);
  1087. goto fail;
  1088. }
  1089. return QDF_STATUS_SUCCESS;
  1090. fail:
  1091. dp_soc_srng_free_be(soc);
  1092. return QDF_STATUS_E_NOMEM;
  1093. }
  1094. static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc)
  1095. {
  1096. int i = 0;
  1097. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1098. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1099. if (dp_srng_init(soc, &soc->rx_refill_buf_ring[i],
  1100. RXDMA_BUF, 0, 0)) {
  1101. dp_err("%pK: dp_srng_init failed refill ring",
  1102. soc);
  1103. goto fail;
  1104. }
  1105. }
  1106. }
  1107. if (dp_soc_ppe_srng_init(soc)) {
  1108. dp_err("%pK: ppe rings init failed",
  1109. soc);
  1110. goto fail;
  1111. }
  1112. return QDF_STATUS_SUCCESS;
  1113. fail:
  1114. dp_soc_srng_deinit_be(soc);
  1115. return QDF_STATUS_E_NOMEM;
  1116. }
  1117. #ifdef WLAN_FEATURE_11BE_MLO
  1118. static inline unsigned
  1119. dp_mlo_peer_find_hash_index(dp_mld_peer_hash_obj_t mld_hash_obj,
  1120. union dp_align_mac_addr *mac_addr)
  1121. {
  1122. uint32_t index;
  1123. index =
  1124. mac_addr->align2.bytes_ab ^
  1125. mac_addr->align2.bytes_cd ^
  1126. mac_addr->align2.bytes_ef;
  1127. index ^= index >> mld_hash_obj->mld_peer_hash.idx_bits;
  1128. index &= mld_hash_obj->mld_peer_hash.mask;
  1129. return index;
  1130. }
  1131. QDF_STATUS
  1132. dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj,
  1133. int hash_elems)
  1134. {
  1135. int i, log2;
  1136. if (!mld_hash_obj)
  1137. return QDF_STATUS_E_FAILURE;
  1138. hash_elems *= DP_PEER_HASH_LOAD_MULT;
  1139. hash_elems >>= DP_PEER_HASH_LOAD_SHIFT;
  1140. log2 = dp_log2_ceil(hash_elems);
  1141. hash_elems = 1 << log2;
  1142. mld_hash_obj->mld_peer_hash.mask = hash_elems - 1;
  1143. mld_hash_obj->mld_peer_hash.idx_bits = log2;
  1144. /* allocate an array of TAILQ peer object lists */
  1145. mld_hash_obj->mld_peer_hash.bins = qdf_mem_malloc(
  1146. hash_elems * sizeof(TAILQ_HEAD(anonymous_tail_q, dp_peer)));
  1147. if (!mld_hash_obj->mld_peer_hash.bins)
  1148. return QDF_STATUS_E_NOMEM;
  1149. for (i = 0; i < hash_elems; i++)
  1150. TAILQ_INIT(&mld_hash_obj->mld_peer_hash.bins[i]);
  1151. qdf_spinlock_create(&mld_hash_obj->mld_peer_hash_lock);
  1152. return QDF_STATUS_SUCCESS;
  1153. }
  1154. void
  1155. dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj)
  1156. {
  1157. if (!mld_hash_obj)
  1158. return;
  1159. if (mld_hash_obj->mld_peer_hash.bins) {
  1160. qdf_mem_free(mld_hash_obj->mld_peer_hash.bins);
  1161. mld_hash_obj->mld_peer_hash.bins = NULL;
  1162. qdf_spinlock_destroy(&mld_hash_obj->mld_peer_hash_lock);
  1163. }
  1164. }
  1165. #ifdef WLAN_MLO_MULTI_CHIP
  1166. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1167. {
  1168. /* In case of MULTI chip MLO peer hash table when MLO global object
  1169. * is created, avoid from SOC attach path
  1170. */
  1171. return QDF_STATUS_SUCCESS;
  1172. }
  1173. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1174. {
  1175. }
  1176. #else
  1177. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1178. {
  1179. dp_mld_peer_hash_obj_t mld_hash_obj;
  1180. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1181. if (!mld_hash_obj)
  1182. return QDF_STATUS_E_FAILURE;
  1183. return dp_mlo_peer_find_hash_attach_be(mld_hash_obj, soc->max_peers);
  1184. }
  1185. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1186. {
  1187. dp_mld_peer_hash_obj_t mld_hash_obj;
  1188. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1189. if (!mld_hash_obj)
  1190. return;
  1191. return dp_mlo_peer_find_hash_detach_be(mld_hash_obj);
  1192. }
  1193. #endif
  1194. static struct dp_peer *
  1195. dp_mlo_peer_find_hash_find_be(struct dp_soc *soc,
  1196. uint8_t *peer_mac_addr,
  1197. int mac_addr_is_aligned,
  1198. enum dp_mod_id mod_id,
  1199. uint8_t vdev_id)
  1200. {
  1201. union dp_align_mac_addr local_mac_addr_aligned, *mac_addr;
  1202. uint32_t index;
  1203. struct dp_peer *peer;
  1204. struct dp_vdev *vdev;
  1205. dp_mld_peer_hash_obj_t mld_hash_obj;
  1206. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1207. if (!mld_hash_obj)
  1208. return NULL;
  1209. if (!mld_hash_obj->mld_peer_hash.bins)
  1210. return NULL;
  1211. if (mac_addr_is_aligned) {
  1212. mac_addr = (union dp_align_mac_addr *)peer_mac_addr;
  1213. } else {
  1214. qdf_mem_copy(
  1215. &local_mac_addr_aligned.raw[0],
  1216. peer_mac_addr, QDF_MAC_ADDR_SIZE);
  1217. mac_addr = &local_mac_addr_aligned;
  1218. }
  1219. if (vdev_id != DP_VDEV_ALL) {
  1220. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, mod_id);
  1221. if (!vdev) {
  1222. dp_err("vdev is null\n");
  1223. return NULL;
  1224. }
  1225. } else {
  1226. vdev = NULL;
  1227. }
  1228. /* search mld peer table if no link peer for given mac address */
  1229. index = dp_mlo_peer_find_hash_index(mld_hash_obj, mac_addr);
  1230. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1231. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1232. hash_list_elem) {
  1233. if (dp_peer_find_mac_addr_cmp(mac_addr, &peer->mac_addr) == 0) {
  1234. if ((vdev_id == DP_VDEV_ALL) || (
  1235. dp_peer_find_mac_addr_cmp(
  1236. &peer->vdev->mld_mac_addr,
  1237. &vdev->mld_mac_addr) == 0)) {
  1238. /* take peer reference before returning */
  1239. if (dp_peer_get_ref(NULL, peer, mod_id) !=
  1240. QDF_STATUS_SUCCESS)
  1241. peer = NULL;
  1242. if (vdev)
  1243. dp_vdev_unref_delete(soc, vdev, mod_id);
  1244. qdf_spin_unlock_bh(
  1245. &mld_hash_obj->mld_peer_hash_lock);
  1246. return peer;
  1247. }
  1248. }
  1249. }
  1250. if (vdev)
  1251. dp_vdev_unref_delete(soc, vdev, mod_id);
  1252. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1253. return NULL; /* failure */
  1254. }
  1255. static void
  1256. dp_mlo_peer_find_hash_remove_be(struct dp_soc *soc, struct dp_peer *peer)
  1257. {
  1258. uint32_t index;
  1259. struct dp_peer *tmppeer = NULL;
  1260. int found = 0;
  1261. dp_mld_peer_hash_obj_t mld_hash_obj;
  1262. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1263. if (!mld_hash_obj)
  1264. return;
  1265. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1266. QDF_ASSERT(!TAILQ_EMPTY(&mld_hash_obj->mld_peer_hash.bins[index]));
  1267. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1268. TAILQ_FOREACH(tmppeer, &mld_hash_obj->mld_peer_hash.bins[index],
  1269. hash_list_elem) {
  1270. if (tmppeer == peer) {
  1271. found = 1;
  1272. break;
  1273. }
  1274. }
  1275. QDF_ASSERT(found);
  1276. TAILQ_REMOVE(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1277. hash_list_elem);
  1278. dp_peer_unref_delete(peer, DP_MOD_ID_CONFIG);
  1279. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1280. }
  1281. static void
  1282. dp_mlo_peer_find_hash_add_be(struct dp_soc *soc, struct dp_peer *peer)
  1283. {
  1284. uint32_t index;
  1285. dp_mld_peer_hash_obj_t mld_hash_obj;
  1286. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1287. if (!mld_hash_obj)
  1288. return;
  1289. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1290. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1291. if (QDF_IS_STATUS_ERROR(dp_peer_get_ref(NULL, peer,
  1292. DP_MOD_ID_CONFIG))) {
  1293. dp_err("fail to get peer ref:" QDF_MAC_ADDR_FMT,
  1294. QDF_MAC_ADDR_REF(peer->mac_addr.raw));
  1295. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1296. return;
  1297. }
  1298. TAILQ_INSERT_TAIL(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1299. hash_list_elem);
  1300. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1301. }
  1302. void dp_print_mlo_ast_stats_be(struct dp_soc *soc)
  1303. {
  1304. uint32_t index;
  1305. struct dp_peer *peer;
  1306. dp_mld_peer_hash_obj_t mld_hash_obj;
  1307. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1308. if (!mld_hash_obj)
  1309. return;
  1310. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1311. for (index = 0; index < mld_hash_obj->mld_peer_hash.mask; index++) {
  1312. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1313. hash_list_elem) {
  1314. dp_print_peer_ast_entries(soc, peer, NULL);
  1315. }
  1316. }
  1317. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1318. }
  1319. #endif
  1320. #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
  1321. static void dp_reconfig_tx_vdev_mcast_ctrl_be(struct dp_soc *soc,
  1322. struct dp_vdev *vdev)
  1323. {
  1324. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1325. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1326. hal_soc_handle_t hal_soc = soc->hal_soc;
  1327. uint8_t vdev_id = vdev->vdev_id;
  1328. if (vdev->opmode == wlan_op_mode_sta) {
  1329. if (vdev->pdev->isolation)
  1330. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1331. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1332. else
  1333. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1334. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  1335. } else if (vdev->opmode == wlan_op_mode_ap) {
  1336. if (vdev->mlo_vdev) {
  1337. if (be_vdev->mcast_primary) {
  1338. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1339. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  1340. hal_tx_vdev_mcast_ctrl_set(hal_soc,
  1341. vdev_id + 128,
  1342. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1343. dp_mcast_mlo_iter_ptnr_soc(be_soc,
  1344. dp_tx_mcast_mlo_reinject_routing_set,
  1345. (void *)&be_vdev->mcast_primary);
  1346. } else {
  1347. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1348. HAL_TX_MCAST_CTRL_DROP);
  1349. }
  1350. } else {
  1351. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  1352. vdev_id,
  1353. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1354. }
  1355. }
  1356. }
  1357. static void dp_bank_reconfig_be(struct dp_soc *soc, struct dp_vdev *vdev)
  1358. {
  1359. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1360. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1361. union hal_tx_bank_config *bank_config;
  1362. if (!be_vdev || be_vdev->bank_id == DP_BE_INVALID_BANK_ID)
  1363. return;
  1364. bank_config = &be_soc->bank_profiles[be_vdev->bank_id].bank_config;
  1365. hal_tx_populate_bank_register(be_soc->soc.hal_soc, bank_config,
  1366. be_vdev->bank_id);
  1367. }
  1368. #endif
  1369. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1370. defined(WLAN_MCAST_MLO)
  1371. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1372. struct dp_vdev_be *be_vdev,
  1373. cdp_config_param_type val)
  1374. {
  1375. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(
  1376. be_vdev->vdev.pdev->soc);
  1377. hal_soc_handle_t hal_soc = be_vdev->vdev.pdev->soc->hal_soc;
  1378. uint8_t vdev_id = be_vdev->vdev.vdev_id;
  1379. be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev;
  1380. if (be_vdev->mcast_primary) {
  1381. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1382. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  1383. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id + 128,
  1384. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1385. dp_mcast_mlo_iter_ptnr_soc(be_soc,
  1386. dp_tx_mcast_mlo_reinject_routing_set,
  1387. (void *)&be_vdev->mcast_primary);
  1388. } else {
  1389. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1390. HAL_TX_MCAST_CTRL_DROP);
  1391. }
  1392. }
  1393. #else
  1394. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1395. struct dp_vdev_be *be_vdev,
  1396. cdp_config_param_type val)
  1397. {
  1398. }
  1399. #endif
  1400. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  1401. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1402. uint8_t tx_ring_id,
  1403. uint8_t bm_id)
  1404. {
  1405. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  1406. soc->tcl_data_ring[tx_ring_id].hal_srng,
  1407. bm_id);
  1408. }
  1409. #else
  1410. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1411. uint8_t tx_ring_id,
  1412. uint8_t bm_id)
  1413. {
  1414. }
  1415. #endif
  1416. QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc,
  1417. struct dp_vdev *vdev,
  1418. enum cdp_vdev_param_type param,
  1419. cdp_config_param_type val)
  1420. {
  1421. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1422. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1423. switch (param) {
  1424. case CDP_TX_ENCAP_TYPE:
  1425. case CDP_UPDATE_DSCP_TO_TID_MAP:
  1426. case CDP_UPDATE_TDLS_FLAGS:
  1427. dp_tx_update_bank_profile(be_soc, be_vdev);
  1428. break;
  1429. case CDP_ENABLE_CIPHER:
  1430. if (vdev->tx_encap_type == htt_cmn_pkt_type_raw)
  1431. dp_tx_update_bank_profile(be_soc, be_vdev);
  1432. break;
  1433. case CDP_SET_MCAST_VDEV:
  1434. dp_txrx_set_mlo_mcast_primary_vdev_param_be(be_vdev, val);
  1435. break;
  1436. default:
  1437. dp_warn("invalid param %d", param);
  1438. break;
  1439. }
  1440. return QDF_STATUS_SUCCESS;
  1441. }
  1442. #ifdef WLAN_FEATURE_11BE_MLO
  1443. #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH
  1444. static inline void
  1445. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1446. {
  1447. soc->peer_id_shift = dp_log2_ceil(soc->max_peers);
  1448. soc->peer_id_mask = (1 << soc->peer_id_shift) - 1;
  1449. /*
  1450. * Double the peers since we use ML indication bit
  1451. * alongwith peer_id to find peers.
  1452. */
  1453. soc->max_peer_id = 1 << (soc->peer_id_shift + 1);
  1454. }
  1455. #else
  1456. static inline void
  1457. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1458. {
  1459. soc->max_peer_id =
  1460. (1 << (HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S + 1)) - 1;
  1461. }
  1462. #endif /* DP_USE_REDUCED_PEER_ID_FIELD_WIDTH */
  1463. #else
  1464. static inline void
  1465. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1466. {
  1467. soc->max_peer_id = soc->max_peers;
  1468. }
  1469. #endif /* WLAN_FEATURE_11BE_MLO */
  1470. static void dp_peer_map_detach_be(struct dp_soc *soc)
  1471. {
  1472. if (soc->host_ast_db_enable)
  1473. dp_peer_ast_hash_detach(soc);
  1474. }
  1475. static QDF_STATUS dp_peer_map_attach_be(struct dp_soc *soc)
  1476. {
  1477. QDF_STATUS status;
  1478. if (soc->host_ast_db_enable) {
  1479. status = dp_peer_ast_hash_attach(soc);
  1480. if (QDF_IS_STATUS_ERROR(status))
  1481. return status;
  1482. }
  1483. dp_soc_max_peer_id_set(soc);
  1484. return QDF_STATUS_SUCCESS;
  1485. }
  1486. static struct dp_peer *dp_find_peer_by_destmac_be(struct dp_soc *soc,
  1487. uint8_t *dest_mac,
  1488. uint8_t vdev_id)
  1489. {
  1490. struct dp_peer *peer = NULL;
  1491. struct dp_peer *tgt_peer = NULL;
  1492. struct dp_ast_entry *ast_entry = NULL;
  1493. uint16_t peer_id;
  1494. qdf_spin_lock_bh(&soc->ast_lock);
  1495. ast_entry = dp_peer_ast_hash_find_soc(soc, dest_mac);
  1496. if (!ast_entry) {
  1497. qdf_spin_unlock_bh(&soc->ast_lock);
  1498. dp_err("NULL ast entry");
  1499. return NULL;
  1500. }
  1501. peer_id = ast_entry->peer_id;
  1502. qdf_spin_unlock_bh(&soc->ast_lock);
  1503. if (peer_id == HTT_INVALID_PEER)
  1504. return NULL;
  1505. peer = dp_peer_get_ref_by_id(soc, peer_id, DP_MOD_ID_SAWF);
  1506. if (!peer) {
  1507. dp_err("NULL peer for peer_id:%d", peer_id);
  1508. return NULL;
  1509. }
  1510. tgt_peer = dp_get_tgt_peer_from_peer(peer);
  1511. /*
  1512. * Once tgt_peer is obtained,
  1513. * release the ref taken for original peer.
  1514. */
  1515. dp_peer_get_ref(NULL, tgt_peer, DP_MOD_ID_SAWF);
  1516. dp_peer_unref_delete(peer, DP_MOD_ID_SAWF);
  1517. return tgt_peer;
  1518. }
  1519. #ifdef WLAN_FEATURE_11BE_MLO
  1520. #ifdef WLAN_MCAST_MLO
  1521. static inline void
  1522. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  1523. {
  1524. arch_ops->dp_tx_mcast_handler = dp_tx_mlo_mcast_handler_be;
  1525. arch_ops->dp_rx_mcast_handler = dp_rx_mlo_igmp_handler;
  1526. }
  1527. #else /* WLAN_MCAST_MLO */
  1528. static inline void
  1529. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  1530. {
  1531. }
  1532. #endif /* WLAN_MCAST_MLO */
  1533. #ifdef WLAN_MLO_MULTI_CHIP
  1534. static inline void
  1535. dp_initialize_arch_ops_be_mlo_ptnr_chip(struct dp_arch_ops *arch_ops)
  1536. {
  1537. arch_ops->dp_partner_chips_map = dp_mlo_partner_chips_map;
  1538. arch_ops->dp_partner_chips_unmap = dp_mlo_partner_chips_unmap;
  1539. }
  1540. #else
  1541. static inline void
  1542. dp_initialize_arch_ops_be_mlo_ptnr_chip(struct dp_arch_ops *arch_ops)
  1543. {
  1544. }
  1545. #endif
  1546. static inline void
  1547. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  1548. {
  1549. dp_initialize_arch_ops_be_mcast_mlo(arch_ops);
  1550. dp_initialize_arch_ops_be_mlo_ptnr_chip(arch_ops);
  1551. arch_ops->mlo_peer_find_hash_detach =
  1552. dp_mlo_peer_find_hash_detach_wrapper;
  1553. arch_ops->mlo_peer_find_hash_attach =
  1554. dp_mlo_peer_find_hash_attach_wrapper;
  1555. arch_ops->mlo_peer_find_hash_add = dp_mlo_peer_find_hash_add_be;
  1556. arch_ops->mlo_peer_find_hash_remove = dp_mlo_peer_find_hash_remove_be;
  1557. arch_ops->mlo_peer_find_hash_find = dp_mlo_peer_find_hash_find_be;
  1558. }
  1559. #else /* WLAN_FEATURE_11BE_MLO */
  1560. static inline void
  1561. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  1562. {
  1563. }
  1564. #endif /* WLAN_FEATURE_11BE_MLO */
  1565. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  1566. #define DP_LMAC_PEER_ID_MSB_LEGACY 2
  1567. #define DP_LMAC_PEER_ID_MSB_MLO 3
  1568. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  1569. struct cdp_peer_setup_info *setup_info,
  1570. enum cdp_host_reo_dest_ring *reo_dest,
  1571. bool *hash_based,
  1572. uint8_t *lmac_peer_id_msb)
  1573. {
  1574. struct dp_soc *soc = vdev->pdev->soc;
  1575. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1576. if (!be_soc->mlo_enabled)
  1577. return dp_vdev_get_default_reo_hash(vdev, reo_dest,
  1578. hash_based);
  1579. *hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  1580. *reo_dest = vdev->pdev->reo_dest;
  1581. /* Not a ML link peer use non-mlo */
  1582. if (!setup_info) {
  1583. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
  1584. return;
  1585. }
  1586. /* For STA ML VAP we do not have num links info at this point
  1587. * use MLO case always
  1588. */
  1589. if (vdev->opmode == wlan_op_mode_sta) {
  1590. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
  1591. return;
  1592. }
  1593. /* For AP ML VAP consider the peer as ML only it associates with
  1594. * multiple links
  1595. */
  1596. if (setup_info->num_links == 1) {
  1597. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
  1598. return;
  1599. }
  1600. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
  1601. }
  1602. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  1603. uint32_t *remap0,
  1604. uint32_t *remap1,
  1605. uint32_t *remap2)
  1606. {
  1607. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1608. uint32_t reo_config = wlan_cfg_get_reo_rings_mapping(soc->wlan_cfg_ctx);
  1609. uint32_t reo_mlo_config =
  1610. wlan_cfg_mlo_rx_ring_map_get(soc->wlan_cfg_ctx);
  1611. if (!be_soc->mlo_enabled)
  1612. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  1613. *remap0 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
  1614. *remap1 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_config);
  1615. *remap2 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
  1616. return true;
  1617. }
  1618. #else
  1619. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  1620. struct cdp_peer_setup_info *setup_info,
  1621. enum cdp_host_reo_dest_ring *reo_dest,
  1622. bool *hash_based,
  1623. uint8_t *lmac_peer_id_msb)
  1624. {
  1625. dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based);
  1626. }
  1627. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  1628. uint32_t *remap0,
  1629. uint32_t *remap1,
  1630. uint32_t *remap2)
  1631. {
  1632. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  1633. }
  1634. #endif
  1635. void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
  1636. {
  1637. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  1638. arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be;
  1639. arch_ops->dp_rx_process = dp_rx_process_be;
  1640. arch_ops->dp_tx_send_fast = dp_tx_fast_send_be;
  1641. arch_ops->tx_comp_get_params_from_hal_desc =
  1642. dp_tx_comp_get_params_from_hal_desc_be;
  1643. arch_ops->dp_tx_process_htt_completion =
  1644. dp_tx_process_htt_completion_be;
  1645. arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be;
  1646. arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be;
  1647. arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be;
  1648. arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be;
  1649. arch_ops->dp_wbm_get_rx_desc_from_hal_desc =
  1650. dp_wbm_get_rx_desc_from_hal_desc_be;
  1651. arch_ops->dp_tx_compute_hw_delay = dp_tx_compute_tx_delay_be;
  1652. #endif
  1653. arch_ops->txrx_get_context_size = dp_get_context_size_be;
  1654. #ifdef WIFI_MONITOR_SUPPORT
  1655. arch_ops->txrx_get_mon_context_size = dp_mon_get_context_size_be;
  1656. #endif
  1657. arch_ops->dp_rx_desc_cookie_2_va =
  1658. dp_rx_desc_cookie_2_va_be;
  1659. arch_ops->dp_rx_intrabss_handle_nawds = dp_rx_intrabss_handle_nawds_be;
  1660. arch_ops->txrx_soc_attach = dp_soc_attach_be;
  1661. arch_ops->txrx_soc_detach = dp_soc_detach_be;
  1662. arch_ops->txrx_soc_init = dp_soc_init_be;
  1663. arch_ops->txrx_soc_deinit = dp_soc_deinit_be;
  1664. arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be;
  1665. arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be;
  1666. arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be;
  1667. arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be;
  1668. arch_ops->txrx_pdev_attach = dp_pdev_attach_be;
  1669. arch_ops->txrx_pdev_detach = dp_pdev_detach_be;
  1670. arch_ops->txrx_vdev_attach = dp_vdev_attach_be;
  1671. arch_ops->txrx_vdev_detach = dp_vdev_detach_be;
  1672. arch_ops->txrx_peer_map_attach = dp_peer_map_attach_be;
  1673. arch_ops->txrx_peer_map_detach = dp_peer_map_detach_be;
  1674. arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be;
  1675. arch_ops->dp_rx_peer_metadata_peer_id_get =
  1676. dp_rx_peer_metadata_peer_id_get_be;
  1677. arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be;
  1678. arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be;
  1679. arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be;
  1680. dp_initialize_arch_ops_be_mlo(arch_ops);
  1681. arch_ops->dp_peer_rx_reorder_queue_setup =
  1682. dp_peer_rx_reorder_queue_setup_be;
  1683. arch_ops->txrx_print_peer_stats = dp_print_peer_txrx_stats_be;
  1684. arch_ops->dp_find_peer_by_destmac = dp_find_peer_by_destmac_be;
  1685. #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
  1686. arch_ops->dp_bank_reconfig = dp_bank_reconfig_be;
  1687. arch_ops->dp_reconfig_tx_vdev_mcast_ctrl =
  1688. dp_reconfig_tx_vdev_mcast_ctrl_be;
  1689. arch_ops->dp_cc_reg_cfg_init = dp_cc_reg_cfg_init;
  1690. #endif
  1691. dp_init_near_full_arch_ops_be(arch_ops);
  1692. arch_ops->get_rx_hash_key = dp_get_rx_hash_key_be;
  1693. arch_ops->print_mlo_ast_stats = dp_print_mlo_ast_stats_be;
  1694. arch_ops->peer_get_reo_hash = dp_peer_get_reo_hash_be;
  1695. arch_ops->reo_remap_config = dp_reo_remap_config_be;
  1696. }