dsi_drm.c 37 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <drm/drm_atomic_helper.h>
  6. #include <drm/drm_atomic.h>
  7. #include "msm_kms.h"
  8. #include "sde_connector.h"
  9. #include "dsi_drm.h"
  10. #include "sde_trace.h"
  11. #include "sde_dbg.h"
  12. #include "msm_drv.h"
  13. #include "sde_encoder.h"
  14. #define to_dsi_bridge(x) container_of((x), struct dsi_bridge, base)
  15. #define to_dsi_state(x) container_of((x), struct dsi_connector_state, base)
  16. #define DEFAULT_PANEL_JITTER_NUMERATOR 2
  17. #define DEFAULT_PANEL_JITTER_DENOMINATOR 1
  18. #define DEFAULT_PANEL_JITTER_ARRAY_SIZE 2
  19. #define DEFAULT_PANEL_PREFILL_LINES 25
  20. static struct dsi_display_mode_priv_info default_priv_info = {
  21. .panel_jitter_numer = DEFAULT_PANEL_JITTER_NUMERATOR,
  22. .panel_jitter_denom = DEFAULT_PANEL_JITTER_DENOMINATOR,
  23. .panel_prefill_lines = DEFAULT_PANEL_PREFILL_LINES,
  24. .dsc_enabled = false,
  25. };
  26. static void convert_to_dsi_mode(const struct drm_display_mode *drm_mode,
  27. struct dsi_display_mode *dsi_mode)
  28. {
  29. memset(dsi_mode, 0, sizeof(*dsi_mode));
  30. dsi_mode->timing.h_active = drm_mode->hdisplay;
  31. dsi_mode->timing.h_back_porch = drm_mode->htotal - drm_mode->hsync_end;
  32. dsi_mode->timing.h_sync_width = drm_mode->htotal -
  33. (drm_mode->hsync_start + dsi_mode->timing.h_back_porch);
  34. dsi_mode->timing.h_front_porch = drm_mode->hsync_start -
  35. drm_mode->hdisplay;
  36. dsi_mode->timing.h_skew = drm_mode->hskew;
  37. dsi_mode->timing.v_active = drm_mode->vdisplay;
  38. dsi_mode->timing.v_back_porch = drm_mode->vtotal - drm_mode->vsync_end;
  39. dsi_mode->timing.v_sync_width = drm_mode->vtotal -
  40. (drm_mode->vsync_start + dsi_mode->timing.v_back_porch);
  41. dsi_mode->timing.v_front_porch = drm_mode->vsync_start -
  42. drm_mode->vdisplay;
  43. dsi_mode->timing.refresh_rate = drm_mode_vrefresh(drm_mode);
  44. dsi_mode->timing.h_sync_polarity =
  45. !!(drm_mode->flags & DRM_MODE_FLAG_PHSYNC);
  46. dsi_mode->timing.v_sync_polarity =
  47. !!(drm_mode->flags & DRM_MODE_FLAG_PVSYNC);
  48. }
  49. static void msm_parse_mode_priv_info(const struct msm_display_mode *msm_mode,
  50. struct dsi_display_mode *dsi_mode)
  51. {
  52. dsi_mode->priv_info =
  53. (struct dsi_display_mode_priv_info *)msm_mode->private;
  54. if (dsi_mode->priv_info) {
  55. dsi_mode->timing.dsc_enabled = dsi_mode->priv_info->dsc_enabled;
  56. dsi_mode->timing.dsc = &dsi_mode->priv_info->dsc;
  57. dsi_mode->timing.vdc_enabled = dsi_mode->priv_info->vdc_enabled;
  58. dsi_mode->timing.vdc = &dsi_mode->priv_info->vdc;
  59. dsi_mode->timing.pclk_scale = dsi_mode->priv_info->pclk_scale;
  60. }
  61. if (msm_is_mode_seamless(msm_mode))
  62. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_SEAMLESS;
  63. if (msm_is_mode_dynamic_fps(msm_mode))
  64. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DFPS;
  65. if (msm_needs_vblank_pre_modeset(msm_mode))
  66. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_VBLANK_PRE_MODESET;
  67. if (msm_is_mode_seamless_dms(msm_mode))
  68. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  69. if (msm_is_mode_seamless_vrr(msm_mode))
  70. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  71. if (msm_is_mode_seamless_poms_to_vid(msm_mode))
  72. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS_TO_VID;
  73. if (msm_is_mode_seamless_poms_to_cmd(msm_mode))
  74. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS_TO_CMD;
  75. if (msm_is_mode_seamless_dyn_clk(msm_mode))
  76. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DYN_CLK;
  77. }
  78. void dsi_convert_to_drm_mode(const struct dsi_display_mode *dsi_mode,
  79. struct drm_display_mode *drm_mode)
  80. {
  81. char *panel_caps = "vid";
  82. if ((dsi_mode->panel_mode_caps & DSI_OP_VIDEO_MODE) &&
  83. (dsi_mode->panel_mode_caps & DSI_OP_CMD_MODE))
  84. panel_caps = "vid_cmd";
  85. else if (dsi_mode->panel_mode_caps & DSI_OP_VIDEO_MODE)
  86. panel_caps = "vid";
  87. else if (dsi_mode->panel_mode_caps & DSI_OP_CMD_MODE)
  88. panel_caps = "cmd";
  89. memset(drm_mode, 0, sizeof(*drm_mode));
  90. drm_mode->hdisplay = dsi_mode->timing.h_active;
  91. drm_mode->hsync_start = drm_mode->hdisplay +
  92. dsi_mode->timing.h_front_porch;
  93. drm_mode->hsync_end = drm_mode->hsync_start +
  94. dsi_mode->timing.h_sync_width;
  95. drm_mode->htotal = drm_mode->hsync_end + dsi_mode->timing.h_back_porch;
  96. drm_mode->hskew = dsi_mode->timing.h_skew;
  97. drm_mode->vdisplay = dsi_mode->timing.v_active;
  98. drm_mode->vsync_start = drm_mode->vdisplay +
  99. dsi_mode->timing.v_front_porch;
  100. drm_mode->vsync_end = drm_mode->vsync_start +
  101. dsi_mode->timing.v_sync_width;
  102. drm_mode->vtotal = drm_mode->vsync_end + dsi_mode->timing.v_back_porch;
  103. drm_mode->clock = drm_mode->htotal * drm_mode->vtotal * dsi_mode->timing.refresh_rate;
  104. drm_mode->clock /= 1000;
  105. if (dsi_mode->timing.h_sync_polarity)
  106. drm_mode->flags |= DRM_MODE_FLAG_PHSYNC;
  107. if (dsi_mode->timing.v_sync_polarity)
  108. drm_mode->flags |= DRM_MODE_FLAG_PVSYNC;
  109. /* set mode name */
  110. snprintf(drm_mode->name, DRM_DISPLAY_MODE_LEN, "%dx%dx%dx%u%s",
  111. drm_mode->hdisplay, drm_mode->vdisplay,
  112. drm_mode_vrefresh(drm_mode), dsi_mode->pixel_clk_khz,
  113. panel_caps);
  114. }
  115. static void dsi_convert_to_msm_mode(const struct dsi_display_mode *dsi_mode,
  116. struct msm_display_mode *msm_mode)
  117. {
  118. msm_mode->private_flags = 0;
  119. msm_mode->private = (int *)dsi_mode->priv_info;
  120. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_SEAMLESS)
  121. msm_mode->private_flags |= DRM_MODE_FLAG_SEAMLESS;
  122. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DFPS)
  123. msm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYNAMIC_FPS;
  124. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_VBLANK_PRE_MODESET)
  125. msm_mode->private_flags |= MSM_MODE_FLAG_VBLANK_PRE_MODESET;
  126. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DMS)
  127. msm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DMS;
  128. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_VRR)
  129. msm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_VRR;
  130. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_VID)
  131. msm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_POMS_VID;
  132. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_CMD)
  133. msm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_POMS_CMD;
  134. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)
  135. msm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYN_CLK;
  136. }
  137. static int dsi_bridge_attach(struct drm_bridge *bridge,
  138. enum drm_bridge_attach_flags flags)
  139. {
  140. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  141. if (!bridge) {
  142. DSI_ERR("Invalid params\n");
  143. return -EINVAL;
  144. }
  145. DSI_DEBUG("[%d] attached\n", c_bridge->id);
  146. return 0;
  147. }
  148. static void dsi_bridge_pre_enable(struct drm_bridge *bridge)
  149. {
  150. int rc = 0;
  151. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  152. if (!bridge) {
  153. DSI_ERR("Invalid params\n");
  154. return;
  155. }
  156. if (!c_bridge || !c_bridge->display || !c_bridge->display->panel) {
  157. DSI_ERR("Incorrect bridge details\n");
  158. return;
  159. }
  160. atomic_set(&c_bridge->display->panel->esd_recovery_pending, 0);
  161. /* By this point mode should have been validated through mode_fixup */
  162. rc = dsi_display_set_mode(c_bridge->display,
  163. &(c_bridge->dsi_mode), 0x0);
  164. if (rc) {
  165. DSI_ERR("[%d] failed to perform a mode set, rc=%d\n",
  166. c_bridge->id, rc);
  167. return;
  168. }
  169. if (c_bridge->dsi_mode.dsi_mode_flags &
  170. (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  171. DSI_MODE_FLAG_DYN_CLK)) {
  172. DSI_DEBUG("[%d] seamless pre-enable\n", c_bridge->id);
  173. return;
  174. }
  175. SDE_ATRACE_BEGIN("dsi_display_prepare");
  176. rc = dsi_display_prepare(c_bridge->display);
  177. if (rc) {
  178. DSI_ERR("[%d] DSI display prepare failed, rc=%d\n",
  179. c_bridge->id, rc);
  180. SDE_ATRACE_END("dsi_display_prepare");
  181. return;
  182. }
  183. SDE_ATRACE_END("dsi_display_prepare");
  184. SDE_ATRACE_BEGIN("dsi_display_enable");
  185. rc = dsi_display_enable(c_bridge->display);
  186. if (rc) {
  187. DSI_ERR("[%d] DSI display enable failed, rc=%d\n",
  188. c_bridge->id, rc);
  189. (void)dsi_display_unprepare(c_bridge->display);
  190. }
  191. SDE_ATRACE_END("dsi_display_enable");
  192. rc = dsi_display_splash_res_cleanup(c_bridge->display);
  193. if (rc)
  194. DSI_ERR("Continuous splash pipeline cleanup failed, rc=%d\n",
  195. rc);
  196. }
  197. static void dsi_bridge_enable(struct drm_bridge *bridge)
  198. {
  199. int rc = 0;
  200. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  201. struct dsi_display *display;
  202. if (!bridge) {
  203. DSI_ERR("Invalid params\n");
  204. return;
  205. }
  206. if (c_bridge->dsi_mode.dsi_mode_flags &
  207. (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  208. DSI_MODE_FLAG_DYN_CLK)) {
  209. DSI_DEBUG("[%d] seamless enable\n", c_bridge->id);
  210. return;
  211. }
  212. display = c_bridge->display;
  213. rc = dsi_display_post_enable(display);
  214. if (rc)
  215. DSI_ERR("[%d] DSI display post enabled failed, rc=%d\n",
  216. c_bridge->id, rc);
  217. if (display)
  218. display->enabled = true;
  219. if (display && display->drm_conn) {
  220. sde_connector_helper_bridge_enable(display->drm_conn);
  221. if (display->poms_pending) {
  222. display->poms_pending = false;
  223. sde_connector_schedule_status_work(display->drm_conn,
  224. true);
  225. }
  226. }
  227. }
  228. static void dsi_bridge_disable(struct drm_bridge *bridge)
  229. {
  230. int rc = 0;
  231. struct dsi_display *display;
  232. struct sde_connector_state *conn_state;
  233. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  234. if (!bridge) {
  235. DSI_ERR("Invalid params\n");
  236. return;
  237. }
  238. display = c_bridge->display;
  239. if (display)
  240. display->enabled = false;
  241. if (display && display->drm_conn) {
  242. conn_state = to_sde_connector_state(display->drm_conn->state);
  243. if (!conn_state) {
  244. DSI_ERR("invalid params\n");
  245. return;
  246. }
  247. display->poms_pending = msm_is_mode_seamless_poms(
  248. &conn_state->msm_mode);
  249. sde_connector_helper_bridge_disable(display->drm_conn);
  250. }
  251. rc = dsi_display_pre_disable(c_bridge->display);
  252. if (rc) {
  253. DSI_ERR("[%d] DSI display pre disable failed, rc=%d\n",
  254. c_bridge->id, rc);
  255. }
  256. }
  257. static void dsi_bridge_post_disable(struct drm_bridge *bridge)
  258. {
  259. int rc = 0;
  260. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  261. if (!bridge) {
  262. DSI_ERR("Invalid params\n");
  263. return;
  264. }
  265. SDE_ATRACE_BEGIN("dsi_bridge_post_disable");
  266. SDE_ATRACE_BEGIN("dsi_display_disable");
  267. rc = dsi_display_disable(c_bridge->display);
  268. if (rc) {
  269. DSI_ERR("[%d] DSI display disable failed, rc=%d\n",
  270. c_bridge->id, rc);
  271. SDE_ATRACE_END("dsi_display_disable");
  272. return;
  273. }
  274. SDE_ATRACE_END("dsi_display_disable");
  275. rc = dsi_display_unprepare(c_bridge->display);
  276. if (rc) {
  277. DSI_ERR("[%d] DSI display unprepare failed, rc=%d\n",
  278. c_bridge->id, rc);
  279. SDE_ATRACE_END("dsi_bridge_post_disable");
  280. return;
  281. }
  282. SDE_ATRACE_END("dsi_bridge_post_disable");
  283. }
  284. static void dsi_bridge_mode_set(struct drm_bridge *bridge,
  285. const struct drm_display_mode *mode,
  286. const struct drm_display_mode *adjusted_mode)
  287. {
  288. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  289. struct drm_connector *conn;
  290. struct sde_connector_state *conn_state;
  291. if (!bridge || !mode || !adjusted_mode) {
  292. DSI_ERR("Invalid params\n");
  293. return;
  294. }
  295. memset(&(c_bridge->dsi_mode), 0x0, sizeof(struct dsi_display_mode));
  296. convert_to_dsi_mode(adjusted_mode, &(c_bridge->dsi_mode));
  297. conn = sde_encoder_get_connector(bridge->dev, bridge->encoder);
  298. if (!conn)
  299. return;
  300. conn_state = to_sde_connector_state(conn->state);
  301. if (!conn_state) {
  302. DSI_ERR("invalid connector state\n");
  303. return;
  304. }
  305. msm_parse_mode_priv_info(&conn_state->msm_mode,
  306. &(c_bridge->dsi_mode));
  307. /* restore bit_clk_rate also for dynamic clk use cases */
  308. c_bridge->dsi_mode.timing.clk_rate_hz =
  309. dsi_drm_find_bit_clk_rate(c_bridge->display, adjusted_mode);
  310. DSI_DEBUG("clk_rate: %llu\n", c_bridge->dsi_mode.timing.clk_rate_hz);
  311. }
  312. static bool dsi_bridge_mode_fixup(struct drm_bridge *bridge,
  313. const struct drm_display_mode *mode,
  314. struct drm_display_mode *adjusted_mode)
  315. {
  316. int rc = 0;
  317. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  318. struct dsi_display *display;
  319. struct dsi_display_mode dsi_mode, cur_dsi_mode, *panel_dsi_mode;
  320. struct drm_crtc_state *crtc_state;
  321. struct drm_connector_state *drm_conn_state;
  322. struct sde_connector_state *conn_state;
  323. crtc_state = container_of(mode, struct drm_crtc_state, mode);
  324. if (!bridge || !mode || !adjusted_mode) {
  325. DSI_ERR("invalid params\n");
  326. return false;
  327. }
  328. display = c_bridge->display;
  329. if (!display || !display->drm_conn || !display->drm_conn->state) {
  330. DSI_ERR("invalid params\n");
  331. return false;
  332. }
  333. drm_conn_state = drm_atomic_get_new_connector_state(crtc_state->state,
  334. display->drm_conn);
  335. conn_state = to_sde_connector_state(drm_conn_state);
  336. if (!conn_state) {
  337. DSI_ERR("invalid params\n");
  338. return false;
  339. }
  340. /*
  341. * if no timing defined in panel, it must be external mode
  342. * and we'll use empty priv info to populate the mode
  343. */
  344. if (display->panel && !display->panel->num_timing_nodes) {
  345. *adjusted_mode = *mode;
  346. conn_state->msm_mode.base = adjusted_mode;
  347. conn_state->msm_mode.private = (int *)&default_priv_info;
  348. conn_state->msm_mode.private_flags = 0;
  349. return true;
  350. }
  351. convert_to_dsi_mode(mode, &dsi_mode);
  352. msm_parse_mode_priv_info(&conn_state->msm_mode, &dsi_mode);
  353. /*
  354. * retrieve dsi mode from dsi driver's cache since not safe to take
  355. * the drm mode config mutex in all paths
  356. */
  357. rc = dsi_display_find_mode(display, &dsi_mode, &panel_dsi_mode);
  358. if (rc)
  359. return rc;
  360. /* propagate the private info to the adjusted_mode derived dsi mode */
  361. dsi_mode.priv_info = panel_dsi_mode->priv_info;
  362. dsi_mode.dsi_mode_flags = panel_dsi_mode->dsi_mode_flags;
  363. dsi_mode.panel_mode_caps = panel_dsi_mode->panel_mode_caps;
  364. dsi_mode.timing.dsc_enabled = dsi_mode.priv_info->dsc_enabled;
  365. dsi_mode.timing.dsc = &dsi_mode.priv_info->dsc;
  366. rc = dsi_display_validate_mode(c_bridge->display, &dsi_mode,
  367. DSI_VALIDATE_FLAG_ALLOW_ADJUST);
  368. if (rc) {
  369. DSI_ERR("[%d] mode is not valid, rc=%d\n", c_bridge->id, rc);
  370. return false;
  371. }
  372. if (bridge->encoder && bridge->encoder->crtc &&
  373. crtc_state->crtc) {
  374. const struct drm_display_mode *cur_mode =
  375. &crtc_state->crtc->state->mode;
  376. convert_to_dsi_mode(cur_mode, &cur_dsi_mode);
  377. cur_dsi_mode.timing.dsc_enabled =
  378. dsi_mode.priv_info->dsc_enabled;
  379. cur_dsi_mode.timing.dsc = &dsi_mode.priv_info->dsc;
  380. rc = dsi_display_validate_mode_change(c_bridge->display,
  381. &cur_dsi_mode, &dsi_mode);
  382. if (rc) {
  383. DSI_ERR("[%s] seamless mode mismatch failure rc=%d\n",
  384. c_bridge->display->name, rc);
  385. return false;
  386. }
  387. /* No DMS/VRR when drm pipeline is changing */
  388. if (!drm_mode_equal(cur_mode, adjusted_mode) &&
  389. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR)) &&
  390. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)) &&
  391. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_VID)) &&
  392. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_CMD)) &&
  393. (!crtc_state->active_changed ||
  394. display->is_cont_splash_enabled)) {
  395. dsi_mode.dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  396. SDE_EVT32(SDE_EVTLOG_FUNC_CASE2,
  397. dsi_mode.timing.h_active,
  398. dsi_mode.timing.v_active,
  399. dsi_mode.timing.refresh_rate,
  400. dsi_mode.pixel_clk_khz,
  401. dsi_mode.panel_mode_caps);
  402. }
  403. }
  404. /* Reject seamless transition when active changed */
  405. if (crtc_state->active_changed &&
  406. ((dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR) ||
  407. (dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK) ||
  408. (dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_VID) ||
  409. (dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_CMD))) {
  410. DSI_INFO("seamless upon active changed 0x%x %d\n",
  411. dsi_mode.dsi_mode_flags, crtc_state->active_changed);
  412. return false;
  413. }
  414. /* convert back to drm mode, propagating the private info & flags */
  415. dsi_convert_to_drm_mode(&dsi_mode, adjusted_mode);
  416. dsi_convert_to_msm_mode(&dsi_mode, &conn_state->msm_mode);
  417. return true;
  418. }
  419. u32 dsi_drm_get_dfps_maxfps(void *display)
  420. {
  421. u32 dfps_maxfps = 0;
  422. struct dsi_display *dsi_display = display;
  423. /*
  424. * The time of SDE transmitting one frame active data
  425. * will not be changed, if frame rate is adjusted with
  426. * VFP method.
  427. * So only return max fps of DFPS for UIDLE update, if DFPS
  428. * is enabled with VFP.
  429. */
  430. if (dsi_display && dsi_display->panel &&
  431. dsi_display->panel->panel_mode == DSI_OP_VIDEO_MODE &&
  432. dsi_display->panel->dfps_caps.type ==
  433. DSI_DFPS_IMMEDIATE_VFP)
  434. dfps_maxfps =
  435. dsi_display->panel->dfps_caps.max_refresh_rate;
  436. return dfps_maxfps;
  437. }
  438. u64 dsi_drm_find_bit_clk_rate(void *display,
  439. const struct drm_display_mode *drm_mode)
  440. {
  441. int i = 0, count = 0;
  442. struct dsi_display *dsi_display = display;
  443. struct dsi_display_mode *dsi_mode;
  444. u64 bit_clk_rate = 0;
  445. if (!dsi_display || !drm_mode)
  446. return 0;
  447. dsi_display_get_mode_count(dsi_display, &count);
  448. for (i = 0; i < count; i++) {
  449. dsi_mode = &dsi_display->modes[i];
  450. if ((dsi_mode->timing.v_active == drm_mode->vdisplay) &&
  451. (dsi_mode->timing.h_active == drm_mode->hdisplay) &&
  452. (dsi_mode->pixel_clk_khz == drm_mode->clock) &&
  453. (dsi_mode->timing.refresh_rate == drm_mode_vrefresh(drm_mode))) {
  454. bit_clk_rate = dsi_mode->timing.clk_rate_hz;
  455. break;
  456. }
  457. }
  458. return bit_clk_rate;
  459. }
  460. int dsi_conn_get_mode_info(struct drm_connector *connector,
  461. const struct drm_display_mode *drm_mode,
  462. struct msm_mode_info *mode_info,
  463. void *display, const struct msm_resource_caps_info *avail_res)
  464. {
  465. struct dsi_display_mode partial_dsi_mode, *dsi_mode = NULL;
  466. struct dsi_mode_info *timing;
  467. int src_bpp, tar_bpp, rc = 0;
  468. if (!drm_mode || !mode_info)
  469. return -EINVAL;
  470. convert_to_dsi_mode(drm_mode, &partial_dsi_mode);
  471. rc = dsi_display_find_mode(display, &partial_dsi_mode, &dsi_mode);
  472. if (rc || !dsi_mode->priv_info)
  473. return -EINVAL;
  474. memset(mode_info, 0, sizeof(*mode_info));
  475. timing = &dsi_mode->timing;
  476. mode_info->frame_rate = dsi_mode->timing.refresh_rate;
  477. mode_info->vtotal = DSI_V_TOTAL(timing);
  478. mode_info->prefill_lines = dsi_mode->priv_info->panel_prefill_lines;
  479. mode_info->jitter_numer = dsi_mode->priv_info->panel_jitter_numer;
  480. mode_info->jitter_denom = dsi_mode->priv_info->panel_jitter_denom;
  481. mode_info->dfps_maxfps = dsi_drm_get_dfps_maxfps(display);
  482. mode_info->clk_rate = dsi_mode->timing.clk_rate_hz;
  483. mode_info->panel_mode_caps = dsi_mode->panel_mode_caps;
  484. mode_info->mdp_transfer_time_us =
  485. dsi_mode->priv_info->mdp_transfer_time_us;
  486. memcpy(&mode_info->topology, &dsi_mode->priv_info->topology,
  487. sizeof(struct msm_display_topology));
  488. if (dsi_mode->priv_info->dsc_enabled) {
  489. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_DSC;
  490. mode_info->topology.comp_type = MSM_DISPLAY_COMPRESSION_DSC;
  491. memcpy(&mode_info->comp_info.dsc_info, &dsi_mode->priv_info->dsc,
  492. sizeof(dsi_mode->priv_info->dsc));
  493. } else if (dsi_mode->priv_info->vdc_enabled) {
  494. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_VDC;
  495. mode_info->topology.comp_type = MSM_DISPLAY_COMPRESSION_VDC;
  496. memcpy(&mode_info->comp_info.vdc_info, &dsi_mode->priv_info->vdc,
  497. sizeof(dsi_mode->priv_info->vdc));
  498. }
  499. if (mode_info->comp_info.comp_type) {
  500. tar_bpp = dsi_mode->priv_info->pclk_scale.numer;
  501. src_bpp = dsi_mode->priv_info->pclk_scale.denom;
  502. mode_info->comp_info.comp_ratio = mult_frac(1, src_bpp,
  503. tar_bpp);
  504. mode_info->wide_bus_en = dsi_mode->priv_info->widebus_support;
  505. }
  506. if (dsi_mode->priv_info->roi_caps.enabled) {
  507. memcpy(&mode_info->roi_caps, &dsi_mode->priv_info->roi_caps,
  508. sizeof(dsi_mode->priv_info->roi_caps));
  509. }
  510. mode_info->allowed_mode_switches =
  511. dsi_mode->priv_info->allowed_mode_switch;
  512. return 0;
  513. }
  514. static const struct drm_bridge_funcs dsi_bridge_ops = {
  515. .attach = dsi_bridge_attach,
  516. .mode_fixup = dsi_bridge_mode_fixup,
  517. .pre_enable = dsi_bridge_pre_enable,
  518. .enable = dsi_bridge_enable,
  519. .disable = dsi_bridge_disable,
  520. .post_disable = dsi_bridge_post_disable,
  521. .mode_set = dsi_bridge_mode_set,
  522. };
  523. int dsi_conn_set_info_blob(struct drm_connector *connector,
  524. void *info, void *display, struct msm_mode_info *mode_info)
  525. {
  526. struct dsi_display *dsi_display = display;
  527. struct dsi_panel *panel;
  528. enum dsi_pixel_format fmt;
  529. u32 bpp;
  530. if (!info || !dsi_display)
  531. return -EINVAL;
  532. dsi_display->drm_conn = connector;
  533. sde_kms_info_add_keystr(info,
  534. "display type", dsi_display->display_type);
  535. switch (dsi_display->type) {
  536. case DSI_DISPLAY_SINGLE:
  537. sde_kms_info_add_keystr(info, "display config",
  538. "single display");
  539. break;
  540. case DSI_DISPLAY_EXT_BRIDGE:
  541. sde_kms_info_add_keystr(info, "display config", "ext bridge");
  542. break;
  543. case DSI_DISPLAY_SPLIT:
  544. sde_kms_info_add_keystr(info, "display config",
  545. "split display");
  546. break;
  547. case DSI_DISPLAY_SPLIT_EXT_BRIDGE:
  548. sde_kms_info_add_keystr(info, "display config",
  549. "split ext bridge");
  550. break;
  551. default:
  552. DSI_DEBUG("invalid display type:%d\n", dsi_display->type);
  553. break;
  554. }
  555. if (!dsi_display->panel) {
  556. DSI_DEBUG("invalid panel data\n");
  557. goto end;
  558. }
  559. panel = dsi_display->panel;
  560. sde_kms_info_add_keystr(info, "panel name", panel->name);
  561. switch (panel->panel_mode) {
  562. case DSI_OP_VIDEO_MODE:
  563. sde_kms_info_add_keystr(info, "panel mode", "video");
  564. sde_kms_info_add_keystr(info, "qsync support",
  565. panel->qsync_caps.qsync_min_fps ?
  566. "true" : "false");
  567. break;
  568. case DSI_OP_CMD_MODE:
  569. sde_kms_info_add_keystr(info, "panel mode", "command");
  570. sde_kms_info_add_keyint(info, "mdp_transfer_time_us",
  571. mode_info->mdp_transfer_time_us);
  572. sde_kms_info_add_keystr(info, "qsync support",
  573. panel->qsync_caps.qsync_min_fps ?
  574. "true" : "false");
  575. break;
  576. default:
  577. DSI_DEBUG("invalid panel type:%d\n", panel->panel_mode);
  578. break;
  579. }
  580. sde_kms_info_add_keystr(info, "dfps support",
  581. panel->dfps_caps.dfps_support ? "true" : "false");
  582. if (panel->dfps_caps.dfps_support) {
  583. sde_kms_info_add_keyint(info, "min_fps",
  584. panel->dfps_caps.min_refresh_rate);
  585. sde_kms_info_add_keyint(info, "max_fps",
  586. panel->dfps_caps.max_refresh_rate);
  587. }
  588. sde_kms_info_add_keystr(info, "dyn bitclk support",
  589. panel->dyn_clk_caps.dyn_clk_support ? "true" : "false");
  590. switch (panel->phy_props.rotation) {
  591. case DSI_PANEL_ROTATE_NONE:
  592. sde_kms_info_add_keystr(info, "panel orientation", "none");
  593. break;
  594. case DSI_PANEL_ROTATE_H_FLIP:
  595. sde_kms_info_add_keystr(info, "panel orientation", "horz flip");
  596. break;
  597. case DSI_PANEL_ROTATE_V_FLIP:
  598. sde_kms_info_add_keystr(info, "panel orientation", "vert flip");
  599. break;
  600. case DSI_PANEL_ROTATE_HV_FLIP:
  601. sde_kms_info_add_keystr(info, "panel orientation",
  602. "horz & vert flip");
  603. break;
  604. default:
  605. DSI_DEBUG("invalid panel rotation:%d\n",
  606. panel->phy_props.rotation);
  607. break;
  608. }
  609. switch (panel->bl_config.type) {
  610. case DSI_BACKLIGHT_PWM:
  611. sde_kms_info_add_keystr(info, "backlight type", "pwm");
  612. break;
  613. case DSI_BACKLIGHT_WLED:
  614. sde_kms_info_add_keystr(info, "backlight type", "wled");
  615. break;
  616. case DSI_BACKLIGHT_DCS:
  617. sde_kms_info_add_keystr(info, "backlight type", "dcs");
  618. break;
  619. default:
  620. DSI_DEBUG("invalid panel backlight type:%d\n",
  621. panel->bl_config.type);
  622. break;
  623. }
  624. if (panel->spr_info.enable)
  625. sde_kms_info_add_keystr(info, "spr_pack_type",
  626. msm_spr_pack_type_str[panel->spr_info.pack_type]);
  627. if (mode_info && mode_info->roi_caps.enabled) {
  628. sde_kms_info_add_keyint(info, "partial_update_num_roi",
  629. mode_info->roi_caps.num_roi);
  630. sde_kms_info_add_keyint(info, "partial_update_xstart",
  631. mode_info->roi_caps.align.xstart_pix_align);
  632. sde_kms_info_add_keyint(info, "partial_update_walign",
  633. mode_info->roi_caps.align.width_pix_align);
  634. sde_kms_info_add_keyint(info, "partial_update_wmin",
  635. mode_info->roi_caps.align.min_width);
  636. sde_kms_info_add_keyint(info, "partial_update_ystart",
  637. mode_info->roi_caps.align.ystart_pix_align);
  638. sde_kms_info_add_keyint(info, "partial_update_halign",
  639. mode_info->roi_caps.align.height_pix_align);
  640. sde_kms_info_add_keyint(info, "partial_update_hmin",
  641. mode_info->roi_caps.align.min_height);
  642. sde_kms_info_add_keyint(info, "partial_update_roimerge",
  643. mode_info->roi_caps.merge_rois);
  644. }
  645. fmt = dsi_display->config.common_config.dst_format;
  646. bpp = dsi_ctrl_pixel_format_to_bpp(fmt);
  647. sde_kms_info_add_keyint(info, "bit_depth", bpp);
  648. end:
  649. return 0;
  650. }
  651. enum drm_connector_status dsi_conn_detect(struct drm_connector *conn,
  652. bool force,
  653. void *display)
  654. {
  655. enum drm_connector_status status = connector_status_unknown;
  656. struct msm_display_info info;
  657. int rc;
  658. if (!conn || !display)
  659. return status;
  660. /* get display dsi_info */
  661. memset(&info, 0x0, sizeof(info));
  662. rc = dsi_display_get_info(conn, &info, display);
  663. if (rc) {
  664. DSI_ERR("failed to get display info, rc=%d\n", rc);
  665. return connector_status_disconnected;
  666. }
  667. if (info.capabilities & MSM_DISPLAY_CAP_HOT_PLUG)
  668. status = (info.is_connected ? connector_status_connected :
  669. connector_status_disconnected);
  670. else
  671. status = connector_status_connected;
  672. conn->display_info.width_mm = info.width_mm;
  673. conn->display_info.height_mm = info.height_mm;
  674. return status;
  675. }
  676. void dsi_connector_put_modes(struct drm_connector *connector,
  677. void *display)
  678. {
  679. struct drm_display_mode *drm_mode;
  680. struct dsi_display_mode dsi_mode, *full_dsi_mode = NULL;
  681. struct dsi_display *dsi_display;
  682. int rc = 0;
  683. if (!connector || !display)
  684. return;
  685. list_for_each_entry(drm_mode, &connector->modes, head) {
  686. convert_to_dsi_mode(drm_mode, &dsi_mode);
  687. rc = dsi_display_find_mode(display, &dsi_mode, &full_dsi_mode);
  688. if (rc)
  689. continue;
  690. dsi_display_put_mode(display, full_dsi_mode);
  691. }
  692. /* free the display structure modes also */
  693. dsi_display = display;
  694. kfree(dsi_display->modes);
  695. dsi_display->modes = NULL;
  696. }
  697. static int dsi_drm_update_edid_name(struct edid *edid, const char *name)
  698. {
  699. u8 *dtd = (u8 *)&edid->detailed_timings[3];
  700. u8 standard_header[] = {0x00, 0x00, 0x00, 0xFE, 0x00};
  701. u32 dtd_size = 18;
  702. u32 header_size = sizeof(standard_header);
  703. if (!name)
  704. return -EINVAL;
  705. /* Fill standard header */
  706. memcpy(dtd, standard_header, header_size);
  707. dtd_size -= header_size;
  708. dtd_size = min_t(u32, dtd_size, strlen(name));
  709. memcpy(dtd + header_size, name, dtd_size);
  710. return 0;
  711. }
  712. static void dsi_drm_update_dtd(struct edid *edid,
  713. struct dsi_display_mode *modes, u32 modes_count)
  714. {
  715. u32 i;
  716. u32 count = min_t(u32, modes_count, 3);
  717. for (i = 0; i < count; i++) {
  718. struct detailed_timing *dtd = &edid->detailed_timings[i];
  719. struct dsi_display_mode *mode = &modes[i];
  720. struct dsi_mode_info *timing = &mode->timing;
  721. struct detailed_pixel_timing *pd = &dtd->data.pixel_data;
  722. u32 h_blank = timing->h_front_porch + timing->h_sync_width +
  723. timing->h_back_porch;
  724. u32 v_blank = timing->v_front_porch + timing->v_sync_width +
  725. timing->v_back_porch;
  726. u32 h_img = 0, v_img = 0;
  727. dtd->pixel_clock = mode->pixel_clk_khz / 10;
  728. pd->hactive_lo = timing->h_active & 0xFF;
  729. pd->hblank_lo = h_blank & 0xFF;
  730. pd->hactive_hblank_hi = ((h_blank >> 8) & 0xF) |
  731. ((timing->h_active >> 8) & 0xF) << 4;
  732. pd->vactive_lo = timing->v_active & 0xFF;
  733. pd->vblank_lo = v_blank & 0xFF;
  734. pd->vactive_vblank_hi = ((v_blank >> 8) & 0xF) |
  735. ((timing->v_active >> 8) & 0xF) << 4;
  736. pd->hsync_offset_lo = timing->h_front_porch & 0xFF;
  737. pd->hsync_pulse_width_lo = timing->h_sync_width & 0xFF;
  738. pd->vsync_offset_pulse_width_lo =
  739. ((timing->v_front_porch & 0xF) << 4) |
  740. (timing->v_sync_width & 0xF);
  741. pd->hsync_vsync_offset_pulse_width_hi =
  742. (((timing->h_front_porch >> 8) & 0x3) << 6) |
  743. (((timing->h_sync_width >> 8) & 0x3) << 4) |
  744. (((timing->v_front_porch >> 4) & 0x3) << 2) |
  745. (((timing->v_sync_width >> 4) & 0x3) << 0);
  746. pd->width_mm_lo = h_img & 0xFF;
  747. pd->height_mm_lo = v_img & 0xFF;
  748. pd->width_height_mm_hi = (((h_img >> 8) & 0xF) << 4) |
  749. ((v_img >> 8) & 0xF);
  750. pd->hborder = 0;
  751. pd->vborder = 0;
  752. pd->misc = 0;
  753. }
  754. }
  755. static void dsi_drm_update_checksum(struct edid *edid)
  756. {
  757. u8 *data = (u8 *)edid;
  758. u32 i, sum = 0;
  759. for (i = 0; i < EDID_LENGTH - 1; i++)
  760. sum += data[i];
  761. edid->checksum = 0x100 - (sum & 0xFF);
  762. }
  763. int dsi_connector_get_modes(struct drm_connector *connector, void *data,
  764. const struct msm_resource_caps_info *avail_res)
  765. {
  766. int rc, i;
  767. u32 count = 0, edid_size;
  768. struct dsi_display_mode *modes = NULL;
  769. struct drm_display_mode drm_mode;
  770. struct dsi_display *display = data;
  771. struct edid edid;
  772. unsigned int width_mm = connector->display_info.width_mm;
  773. unsigned int height_mm = connector->display_info.height_mm;
  774. const u8 edid_buf[EDID_LENGTH] = {
  775. 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x44, 0x6D,
  776. 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1B, 0x10, 0x01, 0x03,
  777. 0x80, 0x00, 0x00, 0x78, 0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47,
  778. 0x98, 0x27, 0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
  779. 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
  780. 0x01, 0x01, 0x01, 0x01,
  781. };
  782. edid_size = min_t(u32, sizeof(edid), EDID_LENGTH);
  783. memcpy(&edid, edid_buf, edid_size);
  784. rc = dsi_display_get_mode_count(display, &count);
  785. if (rc) {
  786. DSI_ERR("failed to get num of modes, rc=%d\n", rc);
  787. goto end;
  788. }
  789. rc = dsi_display_get_modes(display, &modes);
  790. if (rc) {
  791. DSI_ERR("failed to get modes, rc=%d\n", rc);
  792. count = 0;
  793. goto end;
  794. }
  795. for (i = 0; i < count; i++) {
  796. struct drm_display_mode *m;
  797. memset(&drm_mode, 0x0, sizeof(drm_mode));
  798. dsi_convert_to_drm_mode(&modes[i], &drm_mode);
  799. m = drm_mode_duplicate(connector->dev, &drm_mode);
  800. if (!m) {
  801. DSI_ERR("failed to add mode %ux%u\n",
  802. drm_mode.hdisplay,
  803. drm_mode.vdisplay);
  804. count = -ENOMEM;
  805. goto end;
  806. }
  807. m->width_mm = connector->display_info.width_mm;
  808. m->height_mm = connector->display_info.height_mm;
  809. if (display->cmdline_timing != NO_OVERRIDE) {
  810. /* get the preferred mode from dsi display mode */
  811. if (modes[i].is_preferred)
  812. m->type |= DRM_MODE_TYPE_PREFERRED;
  813. } else if (i == 0) {
  814. /* set the first mode in list as preferred */
  815. m->type |= DRM_MODE_TYPE_PREFERRED;
  816. }
  817. drm_mode_probed_add(connector, m);
  818. }
  819. rc = dsi_drm_update_edid_name(&edid, display->panel->name);
  820. if (rc) {
  821. count = 0;
  822. goto end;
  823. }
  824. edid.width_cm = (connector->display_info.width_mm) / 10;
  825. edid.height_cm = (connector->display_info.height_mm) / 10;
  826. dsi_drm_update_dtd(&edid, modes, count);
  827. dsi_drm_update_checksum(&edid);
  828. rc = drm_connector_update_edid_property(connector, &edid);
  829. if (rc)
  830. count = 0;
  831. /*
  832. * DRM EDID structure maintains panel physical dimensions in
  833. * centimeters, we will be losing the precision anything below cm.
  834. * Changing DRM framework will effect other clients at this
  835. * moment, overriding the values back to millimeter.
  836. */
  837. connector->display_info.width_mm = width_mm;
  838. connector->display_info.height_mm = height_mm;
  839. end:
  840. DSI_DEBUG("MODE COUNT =%d\n\n", count);
  841. return count;
  842. }
  843. enum drm_mode_status dsi_conn_mode_valid(struct drm_connector *connector,
  844. struct drm_display_mode *mode,
  845. void *display, const struct msm_resource_caps_info *avail_res)
  846. {
  847. struct dsi_display_mode dsi_mode;
  848. struct dsi_display_mode *full_dsi_mode = NULL;
  849. struct sde_connector_state *conn_state;
  850. int rc;
  851. if (!connector || !mode) {
  852. DSI_ERR("Invalid params\n");
  853. return MODE_ERROR;
  854. }
  855. convert_to_dsi_mode(mode, &dsi_mode);
  856. conn_state = to_sde_connector_state(connector->state);
  857. if (conn_state)
  858. msm_parse_mode_priv_info(&conn_state->msm_mode, &dsi_mode);
  859. rc = dsi_display_find_mode(display, &dsi_mode, &full_dsi_mode);
  860. if (rc) {
  861. DSI_ERR("could not find mode %s\n", mode->name);
  862. return MODE_ERROR;
  863. }
  864. rc = dsi_display_validate_mode(display, full_dsi_mode,
  865. DSI_VALIDATE_FLAG_ALLOW_ADJUST);
  866. if (rc) {
  867. DSI_ERR("mode not supported, rc=%d\n", rc);
  868. return MODE_BAD;
  869. }
  870. return MODE_OK;
  871. }
  872. int dsi_conn_pre_kickoff(struct drm_connector *connector,
  873. void *display,
  874. struct msm_display_kickoff_params *params)
  875. {
  876. if (!connector || !display || !params) {
  877. DSI_ERR("Invalid params\n");
  878. return -EINVAL;
  879. }
  880. return dsi_display_pre_kickoff(connector, display, params);
  881. }
  882. int dsi_conn_prepare_commit(void *display,
  883. struct msm_display_conn_params *params)
  884. {
  885. if (!display || !params) {
  886. pr_err("Invalid params\n");
  887. return -EINVAL;
  888. }
  889. return dsi_display_pre_commit(display, params);
  890. }
  891. void dsi_conn_enable_event(struct drm_connector *connector,
  892. uint32_t event_idx, bool enable, void *display)
  893. {
  894. struct dsi_event_cb_info event_info;
  895. memset(&event_info, 0, sizeof(event_info));
  896. event_info.event_cb = sde_connector_trigger_event;
  897. event_info.event_usr_ptr = connector;
  898. dsi_display_enable_event(connector, display,
  899. event_idx, &event_info, enable);
  900. }
  901. int dsi_conn_post_kickoff(struct drm_connector *connector,
  902. struct msm_display_conn_params *params)
  903. {
  904. struct drm_encoder *encoder;
  905. struct drm_bridge *bridge;
  906. struct dsi_bridge *c_bridge;
  907. struct dsi_display_mode adj_mode;
  908. struct dsi_display *display;
  909. struct dsi_display_ctrl *m_ctrl, *ctrl;
  910. int i, rc = 0, ctrl_version;
  911. bool enable;
  912. struct dsi_dyn_clk_caps *dyn_clk_caps;
  913. if (!connector || !connector->state) {
  914. DSI_ERR("invalid connector or connector state\n");
  915. return -EINVAL;
  916. }
  917. encoder = connector->state->best_encoder;
  918. if (!encoder) {
  919. DSI_DEBUG("best encoder is not available\n");
  920. return 0;
  921. }
  922. bridge = drm_bridge_chain_get_first_bridge(encoder);
  923. if (!bridge) {
  924. DSI_DEBUG("bridge is not available\n");
  925. return 0;
  926. }
  927. c_bridge = to_dsi_bridge(bridge);
  928. adj_mode = c_bridge->dsi_mode;
  929. display = c_bridge->display;
  930. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  931. if (adj_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR) {
  932. m_ctrl = &display->ctrl[display->clk_master_idx];
  933. ctrl_version = m_ctrl->ctrl->version;
  934. rc = dsi_ctrl_timing_db_update(m_ctrl->ctrl, false);
  935. if (rc) {
  936. DSI_ERR("[%s] failed to dfps update rc=%d\n",
  937. display->name, rc);
  938. return -EINVAL;
  939. }
  940. /*
  941. * When both DFPS and dynamic clock switch with constant
  942. * fps features are enabled, wait for dynamic refresh done
  943. * only in case of clock switch.
  944. * In case where only fps changes, clock remains same.
  945. * So, wait for dynamic refresh done is not required.
  946. */
  947. if ((ctrl_version >= DSI_CTRL_VERSION_2_5) &&
  948. (dyn_clk_caps->maintain_const_fps) &&
  949. (adj_mode.dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)) {
  950. display_for_each_ctrl(i, display) {
  951. ctrl = &display->ctrl[i];
  952. rc = dsi_ctrl_wait4dynamic_refresh_done(
  953. ctrl->ctrl);
  954. if (rc)
  955. DSI_ERR("wait4dfps refresh failed\n");
  956. }
  957. }
  958. /* Update the rest of the controllers */
  959. display_for_each_ctrl(i, display) {
  960. ctrl = &display->ctrl[i];
  961. if (!ctrl->ctrl || (ctrl == m_ctrl))
  962. continue;
  963. rc = dsi_ctrl_timing_db_update(ctrl->ctrl, false);
  964. if (rc) {
  965. DSI_ERR("[%s] failed to dfps update rc=%d\n",
  966. display->name, rc);
  967. return -EINVAL;
  968. }
  969. }
  970. c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_VRR;
  971. }
  972. /* ensure dynamic clk switch flag is reset */
  973. c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_DYN_CLK;
  974. if (params->qsync_update) {
  975. enable = (params->qsync_mode > 0) ? true : false;
  976. display_for_each_ctrl(i, display)
  977. dsi_ctrl_setup_avr(display->ctrl[i].ctrl, enable);
  978. }
  979. return 0;
  980. }
  981. struct dsi_bridge *dsi_drm_bridge_init(struct dsi_display *display,
  982. struct drm_device *dev,
  983. struct drm_encoder *encoder)
  984. {
  985. int rc = 0;
  986. struct dsi_bridge *bridge;
  987. bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
  988. if (!bridge) {
  989. rc = -ENOMEM;
  990. goto error;
  991. }
  992. bridge->display = display;
  993. bridge->base.funcs = &dsi_bridge_ops;
  994. bridge->base.encoder = encoder;
  995. rc = drm_bridge_attach(encoder, &bridge->base, NULL, 0);
  996. if (rc) {
  997. DSI_ERR("failed to attach bridge, rc=%d\n", rc);
  998. goto error_free_bridge;
  999. }
  1000. return bridge;
  1001. error_free_bridge:
  1002. kfree(bridge);
  1003. error:
  1004. return ERR_PTR(rc);
  1005. }
  1006. void dsi_drm_bridge_cleanup(struct dsi_bridge *bridge)
  1007. {
  1008. kfree(bridge);
  1009. }
  1010. static bool is_valid_poms_switch(struct dsi_display_mode *mode_a,
  1011. struct dsi_display_mode *mode_b)
  1012. {
  1013. /*
  1014. * POMS cannot happen in conjunction with any other type of mode set.
  1015. * Check to ensure FPS remains same between the modes and also
  1016. * resolution.
  1017. */
  1018. return((mode_a->timing.refresh_rate == mode_b->timing.refresh_rate) &&
  1019. (mode_a->timing.v_active == mode_b->timing.v_active) &&
  1020. (mode_a->timing.h_active == mode_b->timing.h_active));
  1021. }
  1022. void dsi_conn_set_allowed_mode_switch(struct drm_connector *connector,
  1023. void *display)
  1024. {
  1025. u32 mode_idx = 0, cmp_mode_idx = 0;
  1026. u32 common_mode_caps = 0;
  1027. struct drm_display_mode *drm_mode, *cmp_drm_mode;
  1028. struct dsi_display_mode dsi_mode, *panel_dsi_mode, *cmp_panel_dsi_mode;
  1029. struct list_head *mode_list = &connector->modes;
  1030. struct dsi_display *disp = display;
  1031. struct dsi_panel *panel;
  1032. int mode_count = 0, rc = 0;
  1033. struct dsi_display_mode_priv_info *dsi_mode_info, *cmp_dsi_mode_info;
  1034. bool allow_switch = false;
  1035. if (!disp || !disp->panel) {
  1036. DSI_ERR("invalid parameters");
  1037. return;
  1038. }
  1039. panel = disp->panel;
  1040. list_for_each_entry(drm_mode, &connector->modes, head)
  1041. mode_count++;
  1042. list_for_each_entry(drm_mode, &connector->modes, head) {
  1043. convert_to_dsi_mode(drm_mode, &dsi_mode);
  1044. rc = dsi_display_find_mode(display, &dsi_mode, &panel_dsi_mode);
  1045. if (rc)
  1046. return;
  1047. dsi_mode_info = panel_dsi_mode->priv_info;
  1048. dsi_mode_info->allowed_mode_switch |= BIT(mode_idx);
  1049. if (mode_idx == mode_count - 1)
  1050. break;
  1051. mode_list = mode_list->next;
  1052. cmp_mode_idx = 1;
  1053. list_for_each_entry(cmp_drm_mode, mode_list, head) {
  1054. if (&cmp_drm_mode->head == &connector->modes)
  1055. continue;
  1056. convert_to_dsi_mode(cmp_drm_mode, &dsi_mode);
  1057. rc = dsi_display_find_mode(display, &dsi_mode,
  1058. &cmp_panel_dsi_mode);
  1059. if (rc)
  1060. return;
  1061. cmp_dsi_mode_info = cmp_panel_dsi_mode->priv_info;
  1062. allow_switch = false;
  1063. common_mode_caps = (panel_dsi_mode->panel_mode_caps &
  1064. cmp_panel_dsi_mode->panel_mode_caps);
  1065. /*
  1066. * FPS switch among video modes, is only supported
  1067. * if DFPS or dynamic clocks are specified.
  1068. * Reject any mode switches between video mode timing
  1069. * nodes if support for those features is not present.
  1070. */
  1071. if (common_mode_caps & DSI_OP_CMD_MODE) {
  1072. allow_switch = true;
  1073. } else if ((common_mode_caps & DSI_OP_VIDEO_MODE) &&
  1074. (panel->dfps_caps.dfps_support ||
  1075. panel->dyn_clk_caps.dyn_clk_support)) {
  1076. allow_switch = true;
  1077. } else {
  1078. if (is_valid_poms_switch(panel_dsi_mode,
  1079. cmp_panel_dsi_mode))
  1080. allow_switch = true;
  1081. }
  1082. if (allow_switch) {
  1083. dsi_mode_info->allowed_mode_switch |=
  1084. BIT(mode_idx + cmp_mode_idx);
  1085. cmp_dsi_mode_info->allowed_mode_switch |=
  1086. BIT(mode_idx);
  1087. }
  1088. if ((mode_idx + cmp_mode_idx) >= mode_count - 1)
  1089. break;
  1090. cmp_mode_idx++;
  1091. }
  1092. mode_idx++;
  1093. }
  1094. }