sde_encoder.c 161 KB

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  1. /*
  2. * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/kthread.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/seq_file.h>
  22. #include <linux/sde_rsc.h>
  23. #include "msm_drv.h"
  24. #include "sde_kms.h"
  25. #include <drm/drm_crtc.h>
  26. #include <drm/drm_crtc_helper.h>
  27. #include "sde_hwio.h"
  28. #include "sde_hw_catalog.h"
  29. #include "sde_hw_intf.h"
  30. #include "sde_hw_ctl.h"
  31. #include "sde_formats.h"
  32. #include "sde_encoder_phys.h"
  33. #include "sde_power_handle.h"
  34. #include "sde_hw_dsc.h"
  35. #include "sde_crtc.h"
  36. #include "sde_trace.h"
  37. #include "sde_core_irq.h"
  38. #define SDE_DEBUG_ENC(e, fmt, ...) SDE_DEBUG("enc%d " fmt,\
  39. (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  40. #define SDE_ERROR_ENC(e, fmt, ...) SDE_ERROR("enc%d " fmt,\
  41. (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  42. #define SDE_DEBUG_PHYS(p, fmt, ...) SDE_DEBUG("enc%d intf%d pp%d " fmt,\
  43. (p) ? (p)->parent->base.id : -1, \
  44. (p) ? (p)->intf_idx - INTF_0 : -1, \
  45. (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  46. ##__VA_ARGS__)
  47. #define SDE_ERROR_PHYS(p, fmt, ...) SDE_ERROR("enc%d intf%d pp%d " fmt,\
  48. (p) ? (p)->parent->base.id : -1, \
  49. (p) ? (p)->intf_idx - INTF_0 : -1, \
  50. (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  51. ##__VA_ARGS__)
  52. /*
  53. * Two to anticipate panels that can do cmd/vid dynamic switching
  54. * plan is to create all possible physical encoder types, and switch between
  55. * them at runtime
  56. */
  57. #define NUM_PHYS_ENCODER_TYPES 2
  58. #define MAX_PHYS_ENCODERS_PER_VIRTUAL \
  59. (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
  60. #define MISR_BUFF_SIZE 256
  61. #define IDLE_SHORT_TIMEOUT 1
  62. #define EVT_TIME_OUT_SPLIT 2
  63. /* Maximum number of VSYNC wait attempts for RSC state transition */
  64. #define MAX_RSC_WAIT 5
  65. #define TOPOLOGY_DUALPIPE_MERGE_MODE(x) \
  66. (((x) == SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE) || \
  67. ((x) == SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE) || \
  68. ((x) == SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC))
  69. /**
  70. * enum sde_enc_rc_events - events for resource control state machine
  71. * @SDE_ENC_RC_EVENT_KICKOFF:
  72. * This event happens at NORMAL priority.
  73. * Event that signals the start of the transfer. When this event is
  74. * received, enable MDP/DSI core clocks and request RSC with CMD state.
  75. * Regardless of the previous state, the resource should be in ON state
  76. * at the end of this event.
  77. * @SDE_ENC_RC_EVENT_FRAME_DONE:
  78. * This event happens at INTERRUPT level.
  79. * Event signals the end of the data transfer after the PP FRAME_DONE
  80. * event. At the end of this event, a delayed work is scheduled to go to
  81. * IDLE_PC state after IDLE_POWERCOLLAPSE_DURATION time.
  82. * @SDE_ENC_RC_EVENT_PRE_STOP:
  83. * This event happens at NORMAL priority.
  84. * This event, when received during the ON state, set RSC to IDLE, and
  85. * and leave the RC STATE in the PRE_OFF state.
  86. * It should be followed by the STOP event as part of encoder disable.
  87. * If received during IDLE or OFF states, it will do nothing.
  88. * @SDE_ENC_RC_EVENT_STOP:
  89. * This event happens at NORMAL priority.
  90. * When this event is received, disable all the MDP/DSI core clocks, and
  91. * disable IRQs. It should be called from the PRE_OFF or IDLE states.
  92. * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
  93. * PRE_OFF is expected when PRE_STOP was executed during the ON state.
  94. * Resource state should be in OFF at the end of the event.
  95. * @SDE_ENC_RC_EVENT_PRE_MODESET:
  96. * This event happens at NORMAL priority from a work item.
  97. * Event signals that there is a seamless mode switch is in prgoress. A
  98. * client needs to turn of only irq - leave clocks ON to reduce the mode
  99. * switch latency.
  100. * @SDE_ENC_RC_EVENT_POST_MODESET:
  101. * This event happens at NORMAL priority from a work item.
  102. * Event signals that seamless mode switch is complete and resources are
  103. * acquired. Clients wants to turn on the irq again and update the rsc
  104. * with new vtotal.
  105. * @SDE_ENC_RC_EVENT_ENTER_IDLE:
  106. * This event happens at NORMAL priority from a work item.
  107. * Event signals that there were no frame updates for
  108. * IDLE_POWERCOLLAPSE_DURATION time. This would disable MDP/DSI core clocks
  109. * and request RSC with IDLE state and change the resource state to IDLE.
  110. * @SDE_ENC_RC_EVENT_EARLY_WAKEUP:
  111. * This event is triggered from the input event thread when touch event is
  112. * received from the input device. On receiving this event,
  113. * - If the device is in SDE_ENC_RC_STATE_IDLE state, it turns ON the
  114. clocks and enable RSC.
  115. * - If the device is in SDE_ENC_RC_STATE_ON state, it resets the delayed
  116. * off work since a new commit is imminent.
  117. */
  118. enum sde_enc_rc_events {
  119. SDE_ENC_RC_EVENT_KICKOFF = 1,
  120. SDE_ENC_RC_EVENT_FRAME_DONE,
  121. SDE_ENC_RC_EVENT_PRE_STOP,
  122. SDE_ENC_RC_EVENT_STOP,
  123. SDE_ENC_RC_EVENT_PRE_MODESET,
  124. SDE_ENC_RC_EVENT_POST_MODESET,
  125. SDE_ENC_RC_EVENT_ENTER_IDLE,
  126. SDE_ENC_RC_EVENT_EARLY_WAKEUP,
  127. };
  128. /*
  129. * enum sde_enc_rc_states - states that the resource control maintains
  130. * @SDE_ENC_RC_STATE_OFF: Resource is in OFF state
  131. * @SDE_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state
  132. * @SDE_ENC_RC_STATE_ON: Resource is in ON state
  133. * @SDE_ENC_RC_STATE_MODESET: Resource is in modeset state
  134. * @SDE_ENC_RC_STATE_IDLE: Resource is in IDLE state
  135. */
  136. enum sde_enc_rc_states {
  137. SDE_ENC_RC_STATE_OFF,
  138. SDE_ENC_RC_STATE_PRE_OFF,
  139. SDE_ENC_RC_STATE_ON,
  140. SDE_ENC_RC_STATE_MODESET,
  141. SDE_ENC_RC_STATE_IDLE
  142. };
  143. /**
  144. * struct sde_encoder_virt - virtual encoder. Container of one or more physical
  145. * encoders. Virtual encoder manages one "logical" display. Physical
  146. * encoders manage one intf block, tied to a specific panel/sub-panel.
  147. * Virtual encoder defers as much as possible to the physical encoders.
  148. * Virtual encoder registers itself with the DRM Framework as the encoder.
  149. * @base: drm_encoder base class for registration with DRM
  150. * @enc_spin_lock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
  151. * @bus_scaling_client: Client handle to the bus scaling interface
  152. * @te_source: vsync source pin information
  153. * @ops: Encoder ops from init function
  154. * @num_phys_encs: Actual number of physical encoders contained.
  155. * @phys_encs: Container of physical encoders managed.
  156. * @phys_vid_encs: Video physical encoders for panel mode switch.
  157. * @phys_cmd_encs: Command physical encoders for panel mode switch.
  158. * @cur_master: Pointer to the current master in this mode. Optimization
  159. * Only valid after enable. Cleared as disable.
  160. * @hw_pp Handle to the pingpong blocks used for the display. No.
  161. * pingpong blocks can be different than num_phys_encs.
  162. * @hw_dsc: Array of DSC block handles used for the display.
  163. * @dirty_dsc_ids: Cached dsc indexes for dirty DSC blocks needing flush
  164. * @intfs_swapped Whether or not the phys_enc interfaces have been swapped
  165. * for partial update right-only cases, such as pingpong
  166. * split where virtual pingpong does not generate IRQs
  167. * @crtc_vblank_cb: Callback into the upper layer / CRTC for
  168. * notification of the VBLANK
  169. * @crtc_vblank_cb_data: Data from upper layer for VBLANK notification
  170. * @crtc_kickoff_cb: Callback into CRTC that will flush & start
  171. * all CTL paths
  172. * @crtc_kickoff_cb_data: Opaque user data given to crtc_kickoff_cb
  173. * @debugfs_root: Debug file system root file node
  174. * @enc_lock: Lock around physical encoder create/destroy and
  175. access.
  176. * @frame_done_cnt: Atomic counter for tracking which phys_enc is
  177. * done with frame processing.
  178. * @crtc_frame_event_cb: callback handler for frame event
  179. * @crtc_frame_event_cb_data: callback handler private data
  180. * @vsync_event_timer: vsync timer
  181. * @rsc_client: rsc client pointer
  182. * @rsc_state_init: boolean to indicate rsc config init
  183. * @disp_info: local copy of msm_display_info struct
  184. * @misr_enable: misr enable/disable status
  185. * @misr_frame_count: misr frame count before start capturing the data
  186. * @idle_pc_enabled: indicate if idle power collapse is enabled
  187. * currently. This can be controlled by user-mode
  188. * @rc_lock: resource control mutex lock to protect
  189. * virt encoder over various state changes
  190. * @rc_state: resource controller state
  191. * @delayed_off_work: delayed worker to schedule disabling of
  192. * clks and resources after IDLE_TIMEOUT time.
  193. * @vsync_event_work: worker to handle vsync event for autorefresh
  194. * @input_event_work: worker to handle input device touch events
  195. * @esd_trigger_work: worker to handle esd trigger events
  196. * @input_handler: handler for input device events
  197. * @topology: topology of the display
  198. * @vblank_enabled: boolean to track userspace vblank vote
  199. * @idle_pc_restore: flag to indicate idle_pc_restore happened
  200. * @frame_trigger_mode: frame trigger mode indication for command
  201. * mode display
  202. * @dynamic_hdr_updated: flag to indicate if mempool was programmed
  203. * @rsc_config: rsc configuration for display vtotal, fps, etc.
  204. * @cur_conn_roi: current connector roi
  205. * @prv_conn_roi: previous connector roi to optimize if unchanged
  206. * @crtc pointer to drm_crtc
  207. * @recovery_events_enabled: status of hw recovery feature enable by client
  208. * @elevated_ahb_vote: increase AHB bus speed for the first frame
  209. * after power collapse
  210. * @pm_qos_cpu_req: pm_qos request for cpu frequency
  211. * @mode_info: stores the current mode information
  212. */
  213. struct sde_encoder_virt {
  214. struct drm_encoder base;
  215. spinlock_t enc_spinlock;
  216. struct mutex vblank_ctl_lock;
  217. uint32_t bus_scaling_client;
  218. uint32_t display_num_of_h_tiles;
  219. uint32_t te_source;
  220. struct sde_encoder_ops ops;
  221. unsigned int num_phys_encs;
  222. struct sde_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
  223. struct sde_encoder_phys *phys_vid_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
  224. struct sde_encoder_phys *phys_cmd_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
  225. struct sde_encoder_phys *cur_master;
  226. struct sde_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
  227. struct sde_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
  228. struct sde_hw_pingpong *hw_dsc_pp[MAX_CHANNELS_PER_ENC];
  229. enum sde_dsc dirty_dsc_ids[MAX_CHANNELS_PER_ENC];
  230. bool intfs_swapped;
  231. void (*crtc_vblank_cb)(void *data);
  232. void *crtc_vblank_cb_data;
  233. struct dentry *debugfs_root;
  234. struct mutex enc_lock;
  235. atomic_t frame_done_cnt[MAX_PHYS_ENCODERS_PER_VIRTUAL];
  236. void (*crtc_frame_event_cb)(void *data, u32 event);
  237. struct sde_crtc_frame_event_cb_data crtc_frame_event_cb_data;
  238. struct timer_list vsync_event_timer;
  239. struct sde_rsc_client *rsc_client;
  240. bool rsc_state_init;
  241. struct msm_display_info disp_info;
  242. bool misr_enable;
  243. u32 misr_frame_count;
  244. bool idle_pc_enabled;
  245. struct mutex rc_lock;
  246. enum sde_enc_rc_states rc_state;
  247. struct kthread_delayed_work delayed_off_work;
  248. struct kthread_work vsync_event_work;
  249. struct kthread_work input_event_work;
  250. struct kthread_work esd_trigger_work;
  251. struct input_handler *input_handler;
  252. struct msm_display_topology topology;
  253. bool vblank_enabled;
  254. bool idle_pc_restore;
  255. enum frame_trigger_mode_type frame_trigger_mode;
  256. bool dynamic_hdr_updated;
  257. struct sde_rsc_cmd_config rsc_config;
  258. struct sde_rect cur_conn_roi;
  259. struct sde_rect prv_conn_roi;
  260. struct drm_crtc *crtc;
  261. bool recovery_events_enabled;
  262. bool elevated_ahb_vote;
  263. struct pm_qos_request pm_qos_cpu_req;
  264. struct msm_mode_info mode_info;
  265. };
  266. #define to_sde_encoder_virt(x) container_of(x, struct sde_encoder_virt, base)
  267. void sde_encoder_uidle_enable(struct drm_encoder *drm_enc, bool enable)
  268. {
  269. struct sde_encoder_virt *sde_enc;
  270. int i;
  271. sde_enc = to_sde_encoder_virt(drm_enc);
  272. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  273. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  274. if (phys && phys->hw_ctl && phys->hw_ctl->ops.uidle_enable) {
  275. SDE_EVT32(DRMID(drm_enc), enable);
  276. phys->hw_ctl->ops.uidle_enable(phys->hw_ctl, enable);
  277. }
  278. }
  279. }
  280. static void _sde_encoder_pm_qos_add_request(struct drm_encoder *drm_enc,
  281. struct sde_kms *sde_kms)
  282. {
  283. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  284. struct pm_qos_request *req;
  285. u32 cpu_mask;
  286. u32 cpu_dma_latency;
  287. int cpu;
  288. if (!sde_kms->catalog || !sde_kms->catalog->perf.cpu_mask)
  289. return;
  290. cpu_mask = sde_kms->catalog->perf.cpu_mask;
  291. cpu_dma_latency = sde_kms->catalog->perf.cpu_dma_latency;
  292. req = &sde_enc->pm_qos_cpu_req;
  293. req->type = PM_QOS_REQ_AFFINE_CORES;
  294. cpumask_empty(&req->cpus_affine);
  295. for_each_possible_cpu(cpu) {
  296. if ((1 << cpu) & cpu_mask)
  297. cpumask_set_cpu(cpu, &req->cpus_affine);
  298. }
  299. pm_qos_add_request(req, PM_QOS_CPU_DMA_LATENCY, cpu_dma_latency);
  300. SDE_EVT32_VERBOSE(DRMID(drm_enc), cpu_mask, cpu_dma_latency);
  301. }
  302. static void _sde_encoder_pm_qos_remove_request(struct drm_encoder *drm_enc,
  303. struct sde_kms *sde_kms)
  304. {
  305. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  306. if (!sde_kms->catalog || !sde_kms->catalog->perf.cpu_mask)
  307. return;
  308. pm_qos_remove_request(&sde_enc->pm_qos_cpu_req);
  309. }
  310. static bool _sde_encoder_is_dsc_enabled(struct drm_encoder *drm_enc)
  311. {
  312. struct sde_encoder_virt *sde_enc;
  313. struct msm_compression_info *comp_info;
  314. if (!drm_enc)
  315. return false;
  316. sde_enc = to_sde_encoder_virt(drm_enc);
  317. comp_info = &sde_enc->mode_info.comp_info;
  318. return (comp_info->comp_type == MSM_DISPLAY_COMPRESSION_DSC);
  319. }
  320. static int _sde_encoder_wait_timeout(int32_t drm_id, int32_t hw_id,
  321. s64 timeout_ms, struct sde_encoder_wait_info *info)
  322. {
  323. int rc = 0;
  324. s64 wait_time_jiffies = msecs_to_jiffies(timeout_ms);
  325. ktime_t cur_ktime;
  326. ktime_t exp_ktime = ktime_add_ms(ktime_get(), timeout_ms);
  327. do {
  328. rc = wait_event_timeout(*(info->wq),
  329. atomic_read(info->atomic_cnt) == 0, wait_time_jiffies);
  330. cur_ktime = ktime_get();
  331. SDE_EVT32(drm_id, hw_id, rc, ktime_to_ms(cur_ktime),
  332. timeout_ms, atomic_read(info->atomic_cnt));
  333. /* If we timed out, counter is valid and time is less, wait again */
  334. } while (atomic_read(info->atomic_cnt) && (rc == 0) &&
  335. (ktime_compare_safe(exp_ktime, cur_ktime) > 0));
  336. return rc;
  337. }
  338. bool sde_encoder_is_dsc_merge(struct drm_encoder *drm_enc)
  339. {
  340. enum sde_rm_topology_name topology;
  341. struct sde_encoder_virt *sde_enc;
  342. struct drm_connector *drm_conn;
  343. if (!drm_enc)
  344. return false;
  345. sde_enc = to_sde_encoder_virt(drm_enc);
  346. if (!sde_enc->cur_master)
  347. return false;
  348. drm_conn = sde_enc->cur_master->connector;
  349. if (!drm_conn)
  350. return false;
  351. topology = sde_connector_get_topology_name(drm_conn);
  352. if (topology == SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE)
  353. return true;
  354. return false;
  355. }
  356. bool sde_encoder_is_primary_display(struct drm_encoder *drm_enc)
  357. {
  358. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  359. return sde_enc &&
  360. (sde_enc->disp_info.display_type ==
  361. SDE_CONNECTOR_PRIMARY);
  362. }
  363. int sde_encoder_in_cont_splash(struct drm_encoder *drm_enc)
  364. {
  365. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  366. return sde_enc && sde_enc->cur_master &&
  367. sde_enc->cur_master->cont_splash_enabled;
  368. }
  369. void sde_encoder_helper_report_irq_timeout(struct sde_encoder_phys *phys_enc,
  370. enum sde_intr_idx intr_idx)
  371. {
  372. SDE_EVT32(DRMID(phys_enc->parent),
  373. phys_enc->intf_idx - INTF_0,
  374. phys_enc->hw_pp->idx - PINGPONG_0,
  375. intr_idx);
  376. SDE_ERROR_PHYS(phys_enc, "irq %d timeout\n", intr_idx);
  377. if (phys_enc->parent_ops.handle_frame_done)
  378. phys_enc->parent_ops.handle_frame_done(
  379. phys_enc->parent, phys_enc,
  380. SDE_ENCODER_FRAME_EVENT_ERROR);
  381. }
  382. int sde_encoder_helper_wait_for_irq(struct sde_encoder_phys *phys_enc,
  383. enum sde_intr_idx intr_idx,
  384. struct sde_encoder_wait_info *wait_info)
  385. {
  386. struct sde_encoder_irq *irq;
  387. u32 irq_status;
  388. int ret, i;
  389. if (!phys_enc || !wait_info || intr_idx >= INTR_IDX_MAX) {
  390. SDE_ERROR("invalid params\n");
  391. return -EINVAL;
  392. }
  393. irq = &phys_enc->irq[intr_idx];
  394. /* note: do master / slave checking outside */
  395. /* return EWOULDBLOCK since we know the wait isn't necessary */
  396. if (phys_enc->enable_state == SDE_ENC_DISABLED) {
  397. SDE_ERROR_PHYS(phys_enc, "encoder is disabled\n");
  398. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  399. irq->irq_idx, intr_idx, SDE_EVTLOG_ERROR);
  400. return -EWOULDBLOCK;
  401. }
  402. if (irq->irq_idx < 0) {
  403. SDE_DEBUG_PHYS(phys_enc, "irq %s hw %d disabled, skip wait\n",
  404. irq->name, irq->hw_idx);
  405. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  406. irq->irq_idx);
  407. return 0;
  408. }
  409. SDE_DEBUG_PHYS(phys_enc, "pending_cnt %d\n",
  410. atomic_read(wait_info->atomic_cnt));
  411. SDE_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  412. irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
  413. atomic_read(wait_info->atomic_cnt), SDE_EVTLOG_FUNC_ENTRY);
  414. /*
  415. * Some module X may disable interrupt for longer duration
  416. * and it may trigger all interrupts including timer interrupt
  417. * when module X again enable the interrupt.
  418. * That may cause interrupt wait timeout API in this API.
  419. * It is handled by split the wait timer in two halves.
  420. */
  421. for (i = 0; i < EVT_TIME_OUT_SPLIT; i++) {
  422. ret = _sde_encoder_wait_timeout(DRMID(phys_enc->parent),
  423. irq->hw_idx,
  424. (wait_info->timeout_ms/EVT_TIME_OUT_SPLIT),
  425. wait_info);
  426. if (ret)
  427. break;
  428. }
  429. if (ret <= 0) {
  430. irq_status = sde_core_irq_read(phys_enc->sde_kms,
  431. irq->irq_idx, true);
  432. if (irq_status) {
  433. unsigned long flags;
  434. SDE_EVT32(DRMID(phys_enc->parent), intr_idx,
  435. irq->hw_idx, irq->irq_idx,
  436. phys_enc->hw_pp->idx - PINGPONG_0,
  437. atomic_read(wait_info->atomic_cnt));
  438. SDE_DEBUG_PHYS(phys_enc,
  439. "done but irq %d not triggered\n",
  440. irq->irq_idx);
  441. local_irq_save(flags);
  442. irq->cb.func(phys_enc, irq->irq_idx);
  443. local_irq_restore(flags);
  444. ret = 0;
  445. } else {
  446. ret = -ETIMEDOUT;
  447. SDE_EVT32(DRMID(phys_enc->parent), intr_idx,
  448. irq->hw_idx, irq->irq_idx,
  449. phys_enc->hw_pp->idx - PINGPONG_0,
  450. atomic_read(wait_info->atomic_cnt), irq_status,
  451. SDE_EVTLOG_ERROR);
  452. }
  453. } else {
  454. ret = 0;
  455. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  456. irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
  457. atomic_read(wait_info->atomic_cnt));
  458. }
  459. SDE_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  460. irq->irq_idx, ret, phys_enc->hw_pp->idx - PINGPONG_0,
  461. atomic_read(wait_info->atomic_cnt), SDE_EVTLOG_FUNC_EXIT);
  462. return ret;
  463. }
  464. int sde_encoder_helper_register_irq(struct sde_encoder_phys *phys_enc,
  465. enum sde_intr_idx intr_idx)
  466. {
  467. struct sde_encoder_irq *irq;
  468. int ret = 0;
  469. if (!phys_enc || intr_idx >= INTR_IDX_MAX) {
  470. SDE_ERROR("invalid params\n");
  471. return -EINVAL;
  472. }
  473. irq = &phys_enc->irq[intr_idx];
  474. if (irq->irq_idx >= 0) {
  475. SDE_DEBUG_PHYS(phys_enc,
  476. "skipping already registered irq %s type %d\n",
  477. irq->name, irq->intr_type);
  478. return 0;
  479. }
  480. irq->irq_idx = sde_core_irq_idx_lookup(phys_enc->sde_kms,
  481. irq->intr_type, irq->hw_idx);
  482. if (irq->irq_idx < 0) {
  483. SDE_ERROR_PHYS(phys_enc,
  484. "failed to lookup IRQ index for %s type:%d\n",
  485. irq->name, irq->intr_type);
  486. return -EINVAL;
  487. }
  488. ret = sde_core_irq_register_callback(phys_enc->sde_kms, irq->irq_idx,
  489. &irq->cb);
  490. if (ret) {
  491. SDE_ERROR_PHYS(phys_enc,
  492. "failed to register IRQ callback for %s\n",
  493. irq->name);
  494. irq->irq_idx = -EINVAL;
  495. return ret;
  496. }
  497. ret = sde_core_irq_enable(phys_enc->sde_kms, &irq->irq_idx, 1);
  498. if (ret) {
  499. SDE_ERROR_PHYS(phys_enc,
  500. "enable IRQ for intr:%s failed, irq_idx %d\n",
  501. irq->name, irq->irq_idx);
  502. sde_core_irq_unregister_callback(phys_enc->sde_kms,
  503. irq->irq_idx, &irq->cb);
  504. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  505. irq->irq_idx, SDE_EVTLOG_ERROR);
  506. irq->irq_idx = -EINVAL;
  507. return ret;
  508. }
  509. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx, irq->irq_idx);
  510. SDE_DEBUG_PHYS(phys_enc, "registered irq %s idx: %d\n",
  511. irq->name, irq->irq_idx);
  512. return ret;
  513. }
  514. int sde_encoder_helper_unregister_irq(struct sde_encoder_phys *phys_enc,
  515. enum sde_intr_idx intr_idx)
  516. {
  517. struct sde_encoder_irq *irq;
  518. int ret;
  519. if (!phys_enc) {
  520. SDE_ERROR("invalid encoder\n");
  521. return -EINVAL;
  522. }
  523. irq = &phys_enc->irq[intr_idx];
  524. /* silently skip irqs that weren't registered */
  525. if (irq->irq_idx < 0) {
  526. SDE_ERROR(
  527. "extra unregister irq, enc%d intr_idx:0x%x hw_idx:0x%x irq_idx:0x%x\n",
  528. DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  529. irq->irq_idx);
  530. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  531. irq->irq_idx, SDE_EVTLOG_ERROR);
  532. return 0;
  533. }
  534. ret = sde_core_irq_disable(phys_enc->sde_kms, &irq->irq_idx, 1);
  535. if (ret)
  536. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  537. irq->irq_idx, ret, SDE_EVTLOG_ERROR);
  538. ret = sde_core_irq_unregister_callback(phys_enc->sde_kms, irq->irq_idx,
  539. &irq->cb);
  540. if (ret)
  541. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  542. irq->irq_idx, ret, SDE_EVTLOG_ERROR);
  543. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx, irq->irq_idx);
  544. SDE_DEBUG_PHYS(phys_enc, "unregistered %d\n", irq->irq_idx);
  545. irq->irq_idx = -EINVAL;
  546. return 0;
  547. }
  548. void sde_encoder_get_hw_resources(struct drm_encoder *drm_enc,
  549. struct sde_encoder_hw_resources *hw_res,
  550. struct drm_connector_state *conn_state)
  551. {
  552. struct sde_encoder_virt *sde_enc = NULL;
  553. int i = 0;
  554. if (!hw_res || !drm_enc || !conn_state) {
  555. SDE_ERROR("invalid argument(s), drm_enc %d, res %d, state %d\n",
  556. !drm_enc, !hw_res, !conn_state);
  557. return;
  558. }
  559. sde_enc = to_sde_encoder_virt(drm_enc);
  560. SDE_DEBUG_ENC(sde_enc, "\n");
  561. /* Query resources used by phys encs, expected to be without overlap */
  562. memset(hw_res, 0, sizeof(*hw_res));
  563. hw_res->display_num_of_h_tiles = sde_enc->display_num_of_h_tiles;
  564. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  565. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  566. if (phys && phys->ops.get_hw_resources)
  567. phys->ops.get_hw_resources(phys, hw_res, conn_state);
  568. }
  569. sde_connector_get_mode_info(conn_state, &sde_enc->mode_info);
  570. hw_res->topology = sde_enc->mode_info.topology;
  571. hw_res->display_type = sde_enc->disp_info.display_type;
  572. }
  573. void sde_encoder_destroy(struct drm_encoder *drm_enc)
  574. {
  575. struct sde_encoder_virt *sde_enc = NULL;
  576. int i = 0;
  577. if (!drm_enc) {
  578. SDE_ERROR("invalid encoder\n");
  579. return;
  580. }
  581. sde_enc = to_sde_encoder_virt(drm_enc);
  582. SDE_DEBUG_ENC(sde_enc, "\n");
  583. mutex_lock(&sde_enc->enc_lock);
  584. sde_rsc_client_destroy(sde_enc->rsc_client);
  585. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  586. struct sde_encoder_phys *phys;
  587. phys = sde_enc->phys_vid_encs[i];
  588. if (phys && phys->ops.destroy) {
  589. phys->ops.destroy(phys);
  590. --sde_enc->num_phys_encs;
  591. sde_enc->phys_encs[i] = NULL;
  592. }
  593. phys = sde_enc->phys_cmd_encs[i];
  594. if (phys && phys->ops.destroy) {
  595. phys->ops.destroy(phys);
  596. --sde_enc->num_phys_encs;
  597. sde_enc->phys_encs[i] = NULL;
  598. }
  599. }
  600. if (sde_enc->num_phys_encs)
  601. SDE_ERROR_ENC(sde_enc, "expected 0 num_phys_encs not %d\n",
  602. sde_enc->num_phys_encs);
  603. sde_enc->num_phys_encs = 0;
  604. mutex_unlock(&sde_enc->enc_lock);
  605. drm_encoder_cleanup(drm_enc);
  606. mutex_destroy(&sde_enc->enc_lock);
  607. kfree(sde_enc->input_handler);
  608. sde_enc->input_handler = NULL;
  609. kfree(sde_enc);
  610. }
  611. void sde_encoder_helper_update_intf_cfg(
  612. struct sde_encoder_phys *phys_enc)
  613. {
  614. struct sde_encoder_virt *sde_enc;
  615. struct sde_hw_intf_cfg_v1 *intf_cfg;
  616. enum sde_3d_blend_mode mode_3d;
  617. if (!phys_enc) {
  618. SDE_ERROR("invalid arg, encoder %d\n", !phys_enc);
  619. return;
  620. }
  621. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  622. intf_cfg = &sde_enc->cur_master->intf_cfg_v1;
  623. SDE_DEBUG_ENC(sde_enc,
  624. "intf_cfg updated for %d at idx %d\n",
  625. phys_enc->intf_idx,
  626. intf_cfg->intf_count);
  627. /* setup interface configuration */
  628. if (intf_cfg->intf_count >= MAX_INTF_PER_CTL_V1) {
  629. pr_err("invalid inf_count %d\n", intf_cfg->intf_count);
  630. return;
  631. }
  632. intf_cfg->intf[intf_cfg->intf_count++] = phys_enc->intf_idx;
  633. if (phys_enc == sde_enc->cur_master) {
  634. if (sde_enc->cur_master->intf_mode == INTF_MODE_CMD)
  635. intf_cfg->intf_mode_sel = SDE_CTL_MODE_SEL_CMD;
  636. else
  637. intf_cfg->intf_mode_sel = SDE_CTL_MODE_SEL_VID;
  638. }
  639. /* configure this interface as master for split display */
  640. if (phys_enc->split_role == ENC_ROLE_MASTER)
  641. intf_cfg->intf_master = phys_enc->hw_intf->idx;
  642. /* setup which pp blk will connect to this intf */
  643. if (phys_enc->hw_intf->ops.bind_pingpong_blk)
  644. phys_enc->hw_intf->ops.bind_pingpong_blk(
  645. phys_enc->hw_intf,
  646. true,
  647. phys_enc->hw_pp->idx);
  648. /*setup merge_3d configuration */
  649. mode_3d = sde_encoder_helper_get_3d_blend_mode(phys_enc);
  650. if (mode_3d && phys_enc->hw_pp->merge_3d &&
  651. intf_cfg->merge_3d_count < MAX_MERGE_3D_PER_CTL_V1)
  652. intf_cfg->merge_3d[intf_cfg->merge_3d_count++] =
  653. phys_enc->hw_pp->merge_3d->idx;
  654. if (phys_enc->hw_pp->ops.setup_3d_mode)
  655. phys_enc->hw_pp->ops.setup_3d_mode(phys_enc->hw_pp,
  656. mode_3d);
  657. }
  658. void sde_encoder_helper_split_config(
  659. struct sde_encoder_phys *phys_enc,
  660. enum sde_intf interface)
  661. {
  662. struct sde_encoder_virt *sde_enc;
  663. struct split_pipe_cfg cfg = { 0 };
  664. struct sde_hw_mdp *hw_mdptop;
  665. enum sde_rm_topology_name topology;
  666. struct msm_display_info *disp_info;
  667. if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
  668. SDE_ERROR("invalid arg(s), encoder %d\n", !phys_enc);
  669. return;
  670. }
  671. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  672. hw_mdptop = phys_enc->hw_mdptop;
  673. disp_info = &sde_enc->disp_info;
  674. if (disp_info->intf_type != DRM_MODE_CONNECTOR_DSI)
  675. return;
  676. /**
  677. * disable split modes since encoder will be operating in as the only
  678. * encoder, either for the entire use case in the case of, for example,
  679. * single DSI, or for this frame in the case of left/right only partial
  680. * update.
  681. */
  682. if (phys_enc->split_role == ENC_ROLE_SOLO) {
  683. if (hw_mdptop->ops.setup_split_pipe)
  684. hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
  685. if (hw_mdptop->ops.setup_pp_split)
  686. hw_mdptop->ops.setup_pp_split(hw_mdptop, &cfg);
  687. return;
  688. }
  689. cfg.en = true;
  690. cfg.mode = phys_enc->intf_mode;
  691. cfg.intf = interface;
  692. if (cfg.en && phys_enc->ops.needs_single_flush &&
  693. phys_enc->ops.needs_single_flush(phys_enc))
  694. cfg.split_flush_en = true;
  695. topology = sde_connector_get_topology_name(phys_enc->connector);
  696. if (topology == SDE_RM_TOPOLOGY_PPSPLIT)
  697. cfg.pp_split_slave = cfg.intf;
  698. else
  699. cfg.pp_split_slave = INTF_MAX;
  700. if (phys_enc->split_role == ENC_ROLE_MASTER) {
  701. SDE_DEBUG_ENC(sde_enc, "enable %d\n", cfg.en);
  702. if (hw_mdptop->ops.setup_split_pipe)
  703. hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
  704. } else if (sde_enc->hw_pp[0]) {
  705. /*
  706. * slave encoder
  707. * - determine split index from master index,
  708. * assume master is first pp
  709. */
  710. cfg.pp_split_index = sde_enc->hw_pp[0]->idx - PINGPONG_0;
  711. SDE_DEBUG_ENC(sde_enc, "master using pp%d\n",
  712. cfg.pp_split_index);
  713. if (hw_mdptop->ops.setup_pp_split)
  714. hw_mdptop->ops.setup_pp_split(hw_mdptop, &cfg);
  715. }
  716. }
  717. bool sde_encoder_in_clone_mode(struct drm_encoder *drm_enc)
  718. {
  719. struct sde_encoder_virt *sde_enc;
  720. int i = 0;
  721. if (!drm_enc)
  722. return false;
  723. sde_enc = to_sde_encoder_virt(drm_enc);
  724. if (!sde_enc)
  725. return false;
  726. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  727. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  728. if (phys && phys->in_clone_mode)
  729. return true;
  730. }
  731. return false;
  732. }
  733. static int _sde_encoder_atomic_check_phys_enc(struct sde_encoder_virt *sde_enc,
  734. struct drm_crtc_state *crtc_state,
  735. struct drm_connector_state *conn_state)
  736. {
  737. const struct drm_display_mode *mode;
  738. struct drm_display_mode *adj_mode;
  739. int i = 0;
  740. int ret = 0;
  741. mode = &crtc_state->mode;
  742. adj_mode = &crtc_state->adjusted_mode;
  743. /* perform atomic check on the first physical encoder (master) */
  744. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  745. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  746. if (phys && phys->ops.atomic_check)
  747. ret = phys->ops.atomic_check(phys, crtc_state,
  748. conn_state);
  749. else if (phys && phys->ops.mode_fixup)
  750. if (!phys->ops.mode_fixup(phys, mode, adj_mode))
  751. ret = -EINVAL;
  752. if (ret) {
  753. SDE_ERROR_ENC(sde_enc,
  754. "mode unsupported, phys idx %d\n", i);
  755. break;
  756. }
  757. }
  758. return ret;
  759. }
  760. static int _sde_encoder_atomic_check_pu_roi(struct sde_encoder_virt *sde_enc,
  761. struct drm_crtc_state *crtc_state,
  762. struct drm_connector_state *conn_state,
  763. struct sde_connector_state *sde_conn_state,
  764. struct sde_crtc_state *sde_crtc_state)
  765. {
  766. int ret = 0;
  767. if (crtc_state->mode_changed || crtc_state->active_changed) {
  768. struct sde_rect mode_roi, roi;
  769. mode_roi.x = 0;
  770. mode_roi.y = 0;
  771. mode_roi.w = crtc_state->adjusted_mode.hdisplay;
  772. mode_roi.h = crtc_state->adjusted_mode.vdisplay;
  773. if (sde_conn_state->rois.num_rects) {
  774. sde_kms_rect_merge_rectangles(
  775. &sde_conn_state->rois, &roi);
  776. if (!sde_kms_rect_is_equal(&mode_roi, &roi)) {
  777. SDE_ERROR_ENC(sde_enc,
  778. "roi (%d,%d,%d,%d) on connector invalid during modeset\n",
  779. roi.x, roi.y, roi.w, roi.h);
  780. ret = -EINVAL;
  781. }
  782. }
  783. if (sde_crtc_state->user_roi_list.num_rects) {
  784. sde_kms_rect_merge_rectangles(
  785. &sde_crtc_state->user_roi_list, &roi);
  786. if (!sde_kms_rect_is_equal(&mode_roi, &roi)) {
  787. SDE_ERROR_ENC(sde_enc,
  788. "roi (%d,%d,%d,%d) on crtc invalid during modeset\n",
  789. roi.x, roi.y, roi.w, roi.h);
  790. ret = -EINVAL;
  791. }
  792. }
  793. }
  794. return ret;
  795. }
  796. static int _sde_encoder_atomic_check_reserve(struct drm_encoder *drm_enc,
  797. struct drm_crtc_state *crtc_state,
  798. struct drm_connector_state *conn_state,
  799. struct sde_encoder_virt *sde_enc, struct sde_kms *sde_kms,
  800. struct sde_connector *sde_conn,
  801. struct sde_connector_state *sde_conn_state)
  802. {
  803. int ret = 0;
  804. struct drm_display_mode *adj_mode = &crtc_state->adjusted_mode;
  805. if (sde_conn && drm_atomic_crtc_needs_modeset(crtc_state)) {
  806. struct msm_display_topology *topology = NULL;
  807. ret = sde_conn->ops.get_mode_info(&sde_conn->base, adj_mode,
  808. &sde_conn_state->mode_info,
  809. sde_kms->catalog->max_mixer_width,
  810. sde_conn->display);
  811. if (ret) {
  812. SDE_ERROR_ENC(sde_enc,
  813. "failed to get mode info, rc = %d\n", ret);
  814. return ret;
  815. }
  816. if (sde_conn_state->mode_info.comp_info.comp_type &&
  817. sde_conn_state->mode_info.comp_info.comp_ratio >=
  818. MSM_DISPLAY_COMPRESSION_RATIO_MAX) {
  819. SDE_ERROR_ENC(sde_enc,
  820. "invalid compression ratio: %d\n",
  821. sde_conn_state->mode_info.comp_info.comp_ratio);
  822. ret = -EINVAL;
  823. return ret;
  824. }
  825. /* Reserve dynamic resources, indicating atomic_check phase */
  826. ret = sde_rm_reserve(&sde_kms->rm, drm_enc, crtc_state,
  827. conn_state, true);
  828. if (ret) {
  829. SDE_ERROR_ENC(sde_enc,
  830. "RM failed to reserve resources, rc = %d\n",
  831. ret);
  832. return ret;
  833. }
  834. /**
  835. * Update connector state with the topology selected for the
  836. * resource set validated. Reset the topology if we are
  837. * de-activating crtc.
  838. */
  839. if (crtc_state->active)
  840. topology = &sde_conn_state->mode_info.topology;
  841. ret = sde_rm_update_topology(conn_state, topology);
  842. if (ret) {
  843. SDE_ERROR_ENC(sde_enc,
  844. "RM failed to update topology, rc: %d\n", ret);
  845. return ret;
  846. }
  847. ret = sde_connector_set_blob_data(conn_state->connector,
  848. conn_state,
  849. CONNECTOR_PROP_SDE_INFO);
  850. if (ret) {
  851. SDE_ERROR_ENC(sde_enc,
  852. "connector failed to update info, rc: %d\n",
  853. ret);
  854. return ret;
  855. }
  856. }
  857. return ret;
  858. }
  859. static int sde_encoder_virt_atomic_check(
  860. struct drm_encoder *drm_enc, struct drm_crtc_state *crtc_state,
  861. struct drm_connector_state *conn_state)
  862. {
  863. struct sde_encoder_virt *sde_enc;
  864. struct msm_drm_private *priv;
  865. struct sde_kms *sde_kms;
  866. const struct drm_display_mode *mode;
  867. struct drm_display_mode *adj_mode;
  868. struct sde_connector *sde_conn = NULL;
  869. struct sde_connector_state *sde_conn_state = NULL;
  870. struct sde_crtc_state *sde_crtc_state = NULL;
  871. enum sde_rm_topology_name old_top;
  872. int ret = 0;
  873. if (!drm_enc || !crtc_state || !conn_state) {
  874. SDE_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
  875. !drm_enc, !crtc_state, !conn_state);
  876. return -EINVAL;
  877. }
  878. sde_enc = to_sde_encoder_virt(drm_enc);
  879. SDE_DEBUG_ENC(sde_enc, "\n");
  880. priv = drm_enc->dev->dev_private;
  881. sde_kms = to_sde_kms(priv->kms);
  882. mode = &crtc_state->mode;
  883. adj_mode = &crtc_state->adjusted_mode;
  884. sde_conn = to_sde_connector(conn_state->connector);
  885. sde_conn_state = to_sde_connector_state(conn_state);
  886. sde_crtc_state = to_sde_crtc_state(crtc_state);
  887. SDE_EVT32(DRMID(drm_enc), drm_atomic_crtc_needs_modeset(crtc_state));
  888. ret = _sde_encoder_atomic_check_phys_enc(sde_enc, crtc_state,
  889. conn_state);
  890. if (ret)
  891. return ret;
  892. ret = _sde_encoder_atomic_check_pu_roi(sde_enc, crtc_state,
  893. conn_state, sde_conn_state, sde_crtc_state);
  894. if (ret)
  895. return ret;
  896. /**
  897. * record topology in previous atomic state to be able to handle
  898. * topology transitions correctly.
  899. */
  900. old_top = sde_connector_get_property(conn_state,
  901. CONNECTOR_PROP_TOPOLOGY_NAME);
  902. ret = sde_connector_set_old_topology_name(conn_state, old_top);
  903. if (ret)
  904. return ret;
  905. ret = _sde_encoder_atomic_check_reserve(drm_enc, crtc_state,
  906. conn_state, sde_enc, sde_kms, sde_conn, sde_conn_state);
  907. if (ret)
  908. return ret;
  909. ret = sde_connector_roi_v1_check_roi(conn_state);
  910. if (ret) {
  911. SDE_ERROR_ENC(sde_enc, "connector roi check failed, rc: %d",
  912. ret);
  913. return ret;
  914. }
  915. drm_mode_set_crtcinfo(adj_mode, 0);
  916. SDE_EVT32(DRMID(drm_enc), adj_mode->flags, adj_mode->private_flags);
  917. return ret;
  918. }
  919. static int _sde_encoder_dsc_update_pic_dim(struct msm_display_dsc_info *dsc,
  920. int pic_width, int pic_height)
  921. {
  922. if (!dsc || !pic_width || !pic_height) {
  923. SDE_ERROR("invalid input: pic_width=%d pic_height=%d\n",
  924. pic_width, pic_height);
  925. return -EINVAL;
  926. }
  927. if ((pic_width % dsc->slice_width) ||
  928. (pic_height % dsc->slice_height)) {
  929. SDE_ERROR("pic_dim=%dx%d has to be multiple of slice=%dx%d\n",
  930. pic_width, pic_height,
  931. dsc->slice_width, dsc->slice_height);
  932. return -EINVAL;
  933. }
  934. dsc->pic_width = pic_width;
  935. dsc->pic_height = pic_height;
  936. return 0;
  937. }
  938. static void _sde_encoder_dsc_pclk_param_calc(struct msm_display_dsc_info *dsc,
  939. int intf_width)
  940. {
  941. int slice_per_pkt, slice_per_intf;
  942. int bytes_in_slice, total_bytes_per_intf;
  943. if (!dsc || !dsc->slice_width || !dsc->slice_per_pkt ||
  944. (intf_width < dsc->slice_width)) {
  945. SDE_ERROR("invalid input: intf_width=%d slice_width=%d\n",
  946. intf_width, dsc ? dsc->slice_width : -1);
  947. return;
  948. }
  949. slice_per_pkt = dsc->slice_per_pkt;
  950. slice_per_intf = DIV_ROUND_UP(intf_width, dsc->slice_width);
  951. /*
  952. * If slice_per_pkt is greater than slice_per_intf then default to 1.
  953. * This can happen during partial update.
  954. */
  955. if (slice_per_pkt > slice_per_intf)
  956. slice_per_pkt = 1;
  957. bytes_in_slice = DIV_ROUND_UP(dsc->slice_width * dsc->bpp, 8);
  958. total_bytes_per_intf = bytes_in_slice * slice_per_intf;
  959. dsc->eol_byte_num = total_bytes_per_intf % 3;
  960. dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
  961. dsc->bytes_in_slice = bytes_in_slice;
  962. dsc->bytes_per_pkt = bytes_in_slice * slice_per_pkt;
  963. dsc->pkt_per_line = slice_per_intf / slice_per_pkt;
  964. }
  965. static int _sde_encoder_dsc_initial_line_calc(struct msm_display_dsc_info *dsc,
  966. int enc_ip_width)
  967. {
  968. int max_ssm_delay, max_se_size, obuf_latency;
  969. int input_ssm_out_latency, base_hs_latency;
  970. int multi_hs_extra_latency, mux_word_size;
  971. /* Hardent core config */
  972. int max_muxword_size = 48;
  973. int output_rate = 64;
  974. int rtl_max_bpc = 10;
  975. int pipeline_latency = 28;
  976. max_se_size = 4 * (rtl_max_bpc + 1);
  977. max_ssm_delay = max_se_size + max_muxword_size - 1;
  978. mux_word_size = (dsc->bpc >= 12 ? 64 : 48);
  979. input_ssm_out_latency = pipeline_latency + (3 * (max_ssm_delay + 2));
  980. obuf_latency = DIV_ROUND_UP((9 * output_rate +
  981. mux_word_size), dsc->bpp) + 1;
  982. base_hs_latency = dsc->initial_xmit_delay + input_ssm_out_latency
  983. + obuf_latency;
  984. multi_hs_extra_latency = DIV_ROUND_UP((8 * dsc->chunk_size), dsc->bpp);
  985. dsc->initial_lines = DIV_ROUND_UP((base_hs_latency +
  986. multi_hs_extra_latency), dsc->slice_width);
  987. return 0;
  988. }
  989. static bool _sde_encoder_dsc_ich_reset_override_needed(bool pu_en,
  990. struct msm_display_dsc_info *dsc)
  991. {
  992. /*
  993. * As per the DSC spec, ICH_RESET can be either end of the slice line
  994. * or at the end of the slice. HW internally generates ich_reset at
  995. * end of the slice line if DSC_MERGE is used or encoder has two
  996. * soft slices. However, if encoder has only 1 soft slice and DSC_MERGE
  997. * is not used then it will generate ich_reset at the end of slice.
  998. *
  999. * Now as per the spec, during one PPS session, position where
  1000. * ich_reset is generated should not change. Now if full-screen frame
  1001. * has more than 1 soft slice then HW will automatically generate
  1002. * ich_reset at the end of slice_line. But for the same panel, if
  1003. * partial frame is enabled and only 1 encoder is used with 1 slice,
  1004. * then HW will generate ich_reset at end of the slice. This is a
  1005. * mismatch. Prevent this by overriding HW's decision.
  1006. */
  1007. return pu_en && dsc && (dsc->full_frame_slices > 1) &&
  1008. (dsc->slice_width == dsc->pic_width);
  1009. }
  1010. static void _sde_encoder_dsc_pipe_cfg(struct sde_hw_dsc *hw_dsc,
  1011. struct sde_hw_pingpong *hw_pp, struct msm_display_dsc_info *dsc,
  1012. u32 common_mode, bool ich_reset, bool enable,
  1013. struct sde_hw_pingpong *hw_dsc_pp)
  1014. {
  1015. if (!enable) {
  1016. if (hw_dsc_pp && hw_dsc_pp->ops.disable_dsc)
  1017. hw_dsc_pp->ops.disable_dsc(hw_dsc_pp);
  1018. if (hw_dsc && hw_dsc->ops.dsc_disable)
  1019. hw_dsc->ops.dsc_disable(hw_dsc);
  1020. if (hw_dsc && hw_dsc->ops.bind_pingpong_blk)
  1021. hw_dsc->ops.bind_pingpong_blk(hw_dsc, false,
  1022. PINGPONG_MAX);
  1023. return;
  1024. }
  1025. if (!dsc || !hw_dsc || !hw_pp || !hw_dsc_pp) {
  1026. SDE_ERROR("invalid params %d %d %d %d\n", !dsc, !hw_dsc,
  1027. !hw_pp, !hw_dsc_pp);
  1028. return;
  1029. }
  1030. if (hw_dsc->ops.dsc_config)
  1031. hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode, ich_reset);
  1032. if (hw_dsc->ops.dsc_config_thresh)
  1033. hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc);
  1034. if (hw_dsc_pp->ops.setup_dsc)
  1035. hw_dsc_pp->ops.setup_dsc(hw_dsc_pp);
  1036. if (hw_dsc->ops.bind_pingpong_blk)
  1037. hw_dsc->ops.bind_pingpong_blk(hw_dsc, true, hw_pp->idx);
  1038. if (hw_dsc_pp->ops.enable_dsc)
  1039. hw_dsc_pp->ops.enable_dsc(hw_dsc_pp);
  1040. }
  1041. static void _sde_encoder_get_connector_roi(
  1042. struct sde_encoder_virt *sde_enc,
  1043. struct sde_rect *merged_conn_roi)
  1044. {
  1045. struct drm_connector *drm_conn;
  1046. struct sde_connector_state *c_state;
  1047. if (!sde_enc || !merged_conn_roi)
  1048. return;
  1049. drm_conn = sde_enc->phys_encs[0]->connector;
  1050. if (!drm_conn || !drm_conn->state)
  1051. return;
  1052. c_state = to_sde_connector_state(drm_conn->state);
  1053. sde_kms_rect_merge_rectangles(&c_state->rois, merged_conn_roi);
  1054. }
  1055. static int _sde_encoder_dsc_n_lm_1_enc_1_intf(struct sde_encoder_virt *sde_enc)
  1056. {
  1057. int this_frame_slices;
  1058. int intf_ip_w, enc_ip_w;
  1059. int ich_res, dsc_common_mode = 0;
  1060. struct sde_hw_pingpong *hw_pp = sde_enc->hw_pp[0];
  1061. struct sde_hw_pingpong *hw_dsc_pp = sde_enc->hw_dsc_pp[0];
  1062. struct sde_hw_dsc *hw_dsc = sde_enc->hw_dsc[0];
  1063. struct sde_encoder_phys *enc_master = sde_enc->cur_master;
  1064. const struct sde_rect *roi = &sde_enc->cur_conn_roi;
  1065. struct msm_display_dsc_info *dsc = NULL;
  1066. struct sde_hw_ctl *hw_ctl;
  1067. struct sde_ctl_dsc_cfg cfg;
  1068. if (hw_dsc == NULL || hw_pp == NULL || !enc_master) {
  1069. SDE_ERROR_ENC(sde_enc, "invalid params for DSC\n");
  1070. return -EINVAL;
  1071. }
  1072. hw_ctl = enc_master->hw_ctl;
  1073. memset(&cfg, 0, sizeof(cfg));
  1074. dsc = &sde_enc->mode_info.comp_info.dsc_info;
  1075. _sde_encoder_dsc_update_pic_dim(dsc, roi->w, roi->h);
  1076. this_frame_slices = roi->w / dsc->slice_width;
  1077. intf_ip_w = this_frame_slices * dsc->slice_width;
  1078. _sde_encoder_dsc_pclk_param_calc(dsc, intf_ip_w);
  1079. enc_ip_w = intf_ip_w;
  1080. _sde_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
  1081. ich_res = _sde_encoder_dsc_ich_reset_override_needed(false, dsc);
  1082. if (enc_master->intf_mode == INTF_MODE_VIDEO)
  1083. dsc_common_mode = DSC_MODE_VIDEO;
  1084. SDE_DEBUG_ENC(sde_enc, "pic_w: %d pic_h: %d mode:%d\n",
  1085. roi->w, roi->h, dsc_common_mode);
  1086. SDE_EVT32(DRMID(&sde_enc->base), roi->w, roi->h, dsc_common_mode);
  1087. _sde_encoder_dsc_pipe_cfg(hw_dsc, hw_pp, dsc, dsc_common_mode,
  1088. ich_res, true, hw_dsc_pp);
  1089. cfg.dsc[cfg.dsc_count++] = hw_dsc->idx;
  1090. /* setup dsc active configuration in the control path */
  1091. if (hw_ctl->ops.setup_dsc_cfg) {
  1092. hw_ctl->ops.setup_dsc_cfg(hw_ctl, &cfg);
  1093. SDE_DEBUG_ENC(sde_enc,
  1094. "setup dsc_cfg hw_ctl[%d], count:%d,dsc[0]:%d, dsc[1]:%d\n",
  1095. hw_ctl->idx,
  1096. cfg.dsc_count,
  1097. cfg.dsc[0],
  1098. cfg.dsc[1]);
  1099. }
  1100. if (hw_ctl->ops.update_bitmask_dsc)
  1101. hw_ctl->ops.update_bitmask_dsc(hw_ctl, hw_dsc->idx, 1);
  1102. return 0;
  1103. }
  1104. static int _sde_encoder_dsc_2_lm_2_enc_2_intf(struct sde_encoder_virt *sde_enc,
  1105. struct sde_encoder_kickoff_params *params)
  1106. {
  1107. int this_frame_slices;
  1108. int intf_ip_w, enc_ip_w;
  1109. int ich_res, dsc_common_mode;
  1110. struct sde_encoder_phys *enc_master = sde_enc->cur_master;
  1111. const struct sde_rect *roi = &sde_enc->cur_conn_roi;
  1112. struct sde_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
  1113. struct sde_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
  1114. struct sde_hw_pingpong *hw_dsc_pp[MAX_CHANNELS_PER_ENC];
  1115. struct msm_display_dsc_info dsc[MAX_CHANNELS_PER_ENC];
  1116. bool half_panel_partial_update;
  1117. struct sde_hw_ctl *hw_ctl = NULL;
  1118. struct sde_ctl_dsc_cfg cfg;
  1119. int i;
  1120. if (!enc_master) {
  1121. SDE_ERROR_ENC(sde_enc, "invalid encoder master for DSC\n");
  1122. return -EINVAL;
  1123. }
  1124. memset(&cfg, 0, sizeof(cfg));
  1125. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1126. hw_pp[i] = sde_enc->hw_pp[i];
  1127. hw_dsc[i] = sde_enc->hw_dsc[i];
  1128. hw_dsc_pp[i] = sde_enc->hw_dsc_pp[i];
  1129. if (!hw_pp[i] || !hw_dsc[i] || !hw_dsc_pp[i]) {
  1130. SDE_ERROR_ENC(sde_enc, "invalid params for DSC\n");
  1131. return -EINVAL;
  1132. }
  1133. }
  1134. hw_ctl = enc_master->hw_ctl;
  1135. half_panel_partial_update =
  1136. hweight_long(params->affected_displays) == 1;
  1137. dsc_common_mode = 0;
  1138. if (!half_panel_partial_update)
  1139. dsc_common_mode |= DSC_MODE_SPLIT_PANEL;
  1140. if (enc_master->intf_mode == INTF_MODE_VIDEO)
  1141. dsc_common_mode |= DSC_MODE_VIDEO;
  1142. memcpy(&dsc[0], &sde_enc->mode_info.comp_info.dsc_info, sizeof(dsc[0]));
  1143. memcpy(&dsc[1], &sde_enc->mode_info.comp_info.dsc_info, sizeof(dsc[1]));
  1144. /*
  1145. * Since both DSC use same pic dimension, set same pic dimension
  1146. * to both DSC structures.
  1147. */
  1148. _sde_encoder_dsc_update_pic_dim(&dsc[0], roi->w, roi->h);
  1149. _sde_encoder_dsc_update_pic_dim(&dsc[1], roi->w, roi->h);
  1150. this_frame_slices = roi->w / dsc[0].slice_width;
  1151. intf_ip_w = this_frame_slices * dsc[0].slice_width;
  1152. if (!half_panel_partial_update)
  1153. intf_ip_w /= 2;
  1154. /*
  1155. * In this topology when both interfaces are active, they have same
  1156. * load so intf_ip_w will be same.
  1157. */
  1158. _sde_encoder_dsc_pclk_param_calc(&dsc[0], intf_ip_w);
  1159. _sde_encoder_dsc_pclk_param_calc(&dsc[1], intf_ip_w);
  1160. /*
  1161. * In this topology, since there is no dsc_merge, uncompressed input
  1162. * to encoder and interface is same.
  1163. */
  1164. enc_ip_w = intf_ip_w;
  1165. _sde_encoder_dsc_initial_line_calc(&dsc[0], enc_ip_w);
  1166. _sde_encoder_dsc_initial_line_calc(&dsc[1], enc_ip_w);
  1167. /*
  1168. * __is_ich_reset_override_needed should be called only after
  1169. * updating pic dimension, mdss_panel_dsc_update_pic_dim.
  1170. */
  1171. ich_res = _sde_encoder_dsc_ich_reset_override_needed(
  1172. half_panel_partial_update, &dsc[0]);
  1173. SDE_DEBUG_ENC(sde_enc, "pic_w: %d pic_h: %d mode:%d\n",
  1174. roi->w, roi->h, dsc_common_mode);
  1175. for (i = 0; i < sde_enc->num_phys_encs &&
  1176. i < MAX_CHANNELS_PER_ENC; i++) {
  1177. bool active = !!((1 << i) & params->affected_displays);
  1178. SDE_EVT32(DRMID(&sde_enc->base), roi->w, roi->h,
  1179. dsc_common_mode, i, active);
  1180. _sde_encoder_dsc_pipe_cfg(hw_dsc[i], hw_pp[i], &dsc[i],
  1181. dsc_common_mode, ich_res, active, hw_dsc_pp[i]);
  1182. if (active) {
  1183. if (cfg.dsc_count >= MAX_DSC_PER_CTL_V1) {
  1184. pr_err("Invalid dsc count:%d\n",
  1185. cfg.dsc_count);
  1186. return -EINVAL;
  1187. }
  1188. cfg.dsc[cfg.dsc_count++] = hw_dsc[i]->idx;
  1189. if (hw_ctl->ops.update_bitmask_dsc)
  1190. hw_ctl->ops.update_bitmask_dsc(hw_ctl,
  1191. hw_dsc[i]->idx, 1);
  1192. }
  1193. }
  1194. /* setup dsc active configuration in the control path */
  1195. if (hw_ctl->ops.setup_dsc_cfg) {
  1196. hw_ctl->ops.setup_dsc_cfg(hw_ctl, &cfg);
  1197. SDE_DEBUG_ENC(sde_enc,
  1198. "setup dsc_cfg hw_ctl[%d], count:%d,dsc[0]:%d, dsc[1]:%d\n",
  1199. hw_ctl->idx,
  1200. cfg.dsc_count,
  1201. cfg.dsc[0],
  1202. cfg.dsc[1]);
  1203. }
  1204. return 0;
  1205. }
  1206. static int _sde_encoder_dsc_2_lm_2_enc_1_intf(struct sde_encoder_virt *sde_enc,
  1207. struct sde_encoder_kickoff_params *params)
  1208. {
  1209. int this_frame_slices;
  1210. int intf_ip_w, enc_ip_w;
  1211. int ich_res, dsc_common_mode;
  1212. struct sde_encoder_phys *enc_master = sde_enc->cur_master;
  1213. const struct sde_rect *roi = &sde_enc->cur_conn_roi;
  1214. struct sde_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
  1215. struct sde_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
  1216. struct sde_hw_pingpong *hw_dsc_pp[MAX_CHANNELS_PER_ENC];
  1217. struct msm_display_dsc_info *dsc = NULL;
  1218. bool half_panel_partial_update;
  1219. struct sde_hw_ctl *hw_ctl = NULL;
  1220. struct sde_ctl_dsc_cfg cfg;
  1221. int i;
  1222. if (!enc_master) {
  1223. SDE_ERROR_ENC(sde_enc, "invalid encoder master for DSC\n");
  1224. return -EINVAL;
  1225. }
  1226. memset(&cfg, 0, sizeof(cfg));
  1227. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1228. hw_pp[i] = sde_enc->hw_pp[i];
  1229. hw_dsc[i] = sde_enc->hw_dsc[i];
  1230. hw_dsc_pp[i] = sde_enc->hw_dsc_pp[i];
  1231. if (!hw_pp[i] || !hw_dsc[i] || !hw_dsc_pp[i]) {
  1232. SDE_ERROR_ENC(sde_enc, "invalid params for DSC\n");
  1233. return -EINVAL;
  1234. }
  1235. }
  1236. hw_ctl = enc_master->hw_ctl;
  1237. dsc = &sde_enc->mode_info.comp_info.dsc_info;
  1238. half_panel_partial_update =
  1239. hweight_long(params->affected_displays) == 1;
  1240. dsc_common_mode = 0;
  1241. if (!half_panel_partial_update)
  1242. dsc_common_mode |= DSC_MODE_SPLIT_PANEL | DSC_MODE_MULTIPLEX;
  1243. if (enc_master->intf_mode == INTF_MODE_VIDEO)
  1244. dsc_common_mode |= DSC_MODE_VIDEO;
  1245. _sde_encoder_dsc_update_pic_dim(dsc, roi->w, roi->h);
  1246. this_frame_slices = roi->w / dsc->slice_width;
  1247. intf_ip_w = this_frame_slices * dsc->slice_width;
  1248. _sde_encoder_dsc_pclk_param_calc(dsc, intf_ip_w);
  1249. /*
  1250. * dsc merge case: when using 2 encoders for the same stream,
  1251. * no. of slices need to be same on both the encoders.
  1252. */
  1253. enc_ip_w = intf_ip_w / 2;
  1254. _sde_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
  1255. ich_res = _sde_encoder_dsc_ich_reset_override_needed(
  1256. half_panel_partial_update, dsc);
  1257. SDE_DEBUG_ENC(sde_enc, "pic_w: %d pic_h: %d mode:%d\n",
  1258. roi->w, roi->h, dsc_common_mode);
  1259. SDE_EVT32(DRMID(&sde_enc->base), roi->w, roi->h,
  1260. dsc_common_mode, i, params->affected_displays);
  1261. _sde_encoder_dsc_pipe_cfg(hw_dsc[0], hw_pp[0], dsc, dsc_common_mode,
  1262. ich_res, true, hw_dsc_pp[0]);
  1263. cfg.dsc[0] = hw_dsc[0]->idx;
  1264. cfg.dsc_count++;
  1265. if (hw_ctl->ops.update_bitmask_dsc)
  1266. hw_ctl->ops.update_bitmask_dsc(hw_ctl, hw_dsc[0]->idx, 1);
  1267. _sde_encoder_dsc_pipe_cfg(hw_dsc[1], hw_pp[1], dsc, dsc_common_mode,
  1268. ich_res, !half_panel_partial_update, hw_dsc_pp[1]);
  1269. if (!half_panel_partial_update) {
  1270. cfg.dsc[1] = hw_dsc[1]->idx;
  1271. cfg.dsc_count++;
  1272. if (hw_ctl->ops.update_bitmask_dsc)
  1273. hw_ctl->ops.update_bitmask_dsc(hw_ctl, hw_dsc[1]->idx,
  1274. 1);
  1275. }
  1276. /* setup dsc active configuration in the control path */
  1277. if (hw_ctl->ops.setup_dsc_cfg) {
  1278. hw_ctl->ops.setup_dsc_cfg(hw_ctl, &cfg);
  1279. SDE_DEBUG_ENC(sde_enc,
  1280. "setup_dsc_cfg hw_ctl[%d], count:%d,dsc[0]:%d, dsc[1]:%d\n",
  1281. hw_ctl->idx,
  1282. cfg.dsc_count,
  1283. cfg.dsc[0],
  1284. cfg.dsc[1]);
  1285. }
  1286. return 0;
  1287. }
  1288. static int _sde_encoder_update_roi(struct drm_encoder *drm_enc)
  1289. {
  1290. struct sde_encoder_virt *sde_enc;
  1291. struct drm_connector *drm_conn;
  1292. struct drm_display_mode *adj_mode;
  1293. struct sde_rect roi;
  1294. if (!drm_enc) {
  1295. SDE_ERROR("invalid encoder parameter\n");
  1296. return -EINVAL;
  1297. }
  1298. sde_enc = to_sde_encoder_virt(drm_enc);
  1299. if (!sde_enc->crtc || !sde_enc->crtc->state) {
  1300. SDE_ERROR("invalid crtc parameter\n");
  1301. return -EINVAL;
  1302. }
  1303. if (!sde_enc->cur_master) {
  1304. SDE_ERROR("invalid cur_master parameter\n");
  1305. return -EINVAL;
  1306. }
  1307. adj_mode = &sde_enc->cur_master->cached_mode;
  1308. drm_conn = sde_enc->cur_master->connector;
  1309. _sde_encoder_get_connector_roi(sde_enc, &roi);
  1310. if (sde_kms_rect_is_null(&roi)) {
  1311. roi.w = adj_mode->hdisplay;
  1312. roi.h = adj_mode->vdisplay;
  1313. }
  1314. memcpy(&sde_enc->prv_conn_roi, &sde_enc->cur_conn_roi,
  1315. sizeof(sde_enc->prv_conn_roi));
  1316. memcpy(&sde_enc->cur_conn_roi, &roi, sizeof(sde_enc->cur_conn_roi));
  1317. return 0;
  1318. }
  1319. static int _sde_encoder_dsc_setup(struct sde_encoder_virt *sde_enc,
  1320. struct sde_encoder_kickoff_params *params)
  1321. {
  1322. enum sde_rm_topology_name topology;
  1323. struct drm_connector *drm_conn;
  1324. int ret = 0;
  1325. if (!sde_enc || !params || !sde_enc->phys_encs[0] ||
  1326. !sde_enc->phys_encs[0]->connector)
  1327. return -EINVAL;
  1328. drm_conn = sde_enc->phys_encs[0]->connector;
  1329. topology = sde_connector_get_topology_name(drm_conn);
  1330. if (topology == SDE_RM_TOPOLOGY_NONE) {
  1331. SDE_ERROR_ENC(sde_enc, "topology not set yet\n");
  1332. return -EINVAL;
  1333. }
  1334. SDE_DEBUG_ENC(sde_enc, "topology:%d\n", topology);
  1335. SDE_EVT32(DRMID(&sde_enc->base), topology,
  1336. sde_enc->cur_conn_roi.x,
  1337. sde_enc->cur_conn_roi.y,
  1338. sde_enc->cur_conn_roi.w,
  1339. sde_enc->cur_conn_roi.h,
  1340. sde_enc->prv_conn_roi.x,
  1341. sde_enc->prv_conn_roi.y,
  1342. sde_enc->prv_conn_roi.w,
  1343. sde_enc->prv_conn_roi.h,
  1344. sde_enc->cur_master->cached_mode.hdisplay,
  1345. sde_enc->cur_master->cached_mode.vdisplay);
  1346. if (sde_kms_rect_is_equal(&sde_enc->cur_conn_roi,
  1347. &sde_enc->prv_conn_roi))
  1348. return ret;
  1349. switch (topology) {
  1350. case SDE_RM_TOPOLOGY_SINGLEPIPE_DSC:
  1351. case SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC:
  1352. ret = _sde_encoder_dsc_n_lm_1_enc_1_intf(sde_enc);
  1353. break;
  1354. case SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE:
  1355. ret = _sde_encoder_dsc_2_lm_2_enc_1_intf(sde_enc, params);
  1356. break;
  1357. case SDE_RM_TOPOLOGY_DUALPIPE_DSC:
  1358. ret = _sde_encoder_dsc_2_lm_2_enc_2_intf(sde_enc, params);
  1359. break;
  1360. default:
  1361. SDE_ERROR_ENC(sde_enc, "No DSC support for topology %d",
  1362. topology);
  1363. return -EINVAL;
  1364. }
  1365. return ret;
  1366. }
  1367. void sde_encoder_helper_vsync_config(struct sde_encoder_phys *phys_enc,
  1368. u32 vsync_source, bool is_dummy)
  1369. {
  1370. struct sde_vsync_source_cfg vsync_cfg = { 0 };
  1371. struct msm_drm_private *priv;
  1372. struct sde_kms *sde_kms;
  1373. struct sde_hw_mdp *hw_mdptop;
  1374. struct drm_encoder *drm_enc;
  1375. struct sde_encoder_virt *sde_enc;
  1376. int i;
  1377. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  1378. if (!sde_enc) {
  1379. SDE_ERROR("invalid param sde_enc:%d\n", sde_enc != NULL);
  1380. return;
  1381. } else if (sde_enc->num_phys_encs > ARRAY_SIZE(sde_enc->hw_pp)) {
  1382. SDE_ERROR("invalid num phys enc %d/%d\n",
  1383. sde_enc->num_phys_encs,
  1384. (int) ARRAY_SIZE(sde_enc->hw_pp));
  1385. return;
  1386. }
  1387. drm_enc = &sde_enc->base;
  1388. /* this pointers are checked in virt_enable_helper */
  1389. priv = drm_enc->dev->dev_private;
  1390. sde_kms = to_sde_kms(priv->kms);
  1391. if (!sde_kms) {
  1392. SDE_ERROR("invalid sde_kms\n");
  1393. return;
  1394. }
  1395. hw_mdptop = sde_kms->hw_mdp;
  1396. if (!hw_mdptop) {
  1397. SDE_ERROR("invalid mdptop\n");
  1398. return;
  1399. }
  1400. if (hw_mdptop->ops.setup_vsync_source) {
  1401. for (i = 0; i < sde_enc->num_phys_encs; i++)
  1402. vsync_cfg.ppnumber[i] = sde_enc->hw_pp[i]->idx;
  1403. vsync_cfg.pp_count = sde_enc->num_phys_encs;
  1404. vsync_cfg.frame_rate = sde_enc->mode_info.frame_rate;
  1405. vsync_cfg.vsync_source = vsync_source;
  1406. vsync_cfg.is_dummy = is_dummy;
  1407. hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
  1408. }
  1409. }
  1410. static void _sde_encoder_update_vsync_source(struct sde_encoder_virt *sde_enc,
  1411. struct msm_display_info *disp_info, bool is_dummy)
  1412. {
  1413. struct sde_encoder_phys *phys;
  1414. int i;
  1415. u32 vsync_source;
  1416. if (!sde_enc || !disp_info) {
  1417. SDE_ERROR("invalid param sde_enc:%d or disp_info:%d\n",
  1418. sde_enc != NULL, disp_info != NULL);
  1419. return;
  1420. } else if (sde_enc->num_phys_encs > ARRAY_SIZE(sde_enc->hw_pp)) {
  1421. SDE_ERROR("invalid num phys enc %d/%d\n",
  1422. sde_enc->num_phys_encs,
  1423. (int) ARRAY_SIZE(sde_enc->hw_pp));
  1424. return;
  1425. }
  1426. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_CMD_MODE)) {
  1427. if (is_dummy)
  1428. vsync_source = SDE_VSYNC_SOURCE_WD_TIMER_0 -
  1429. sde_enc->te_source;
  1430. else if (disp_info->is_te_using_watchdog_timer)
  1431. vsync_source = SDE_VSYNC_SOURCE_WD_TIMER_4;
  1432. else
  1433. vsync_source = sde_enc->te_source;
  1434. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1435. phys = sde_enc->phys_encs[i];
  1436. if (phys && phys->ops.setup_vsync_source)
  1437. phys->ops.setup_vsync_source(phys,
  1438. vsync_source, is_dummy);
  1439. }
  1440. }
  1441. }
  1442. static void _sde_encoder_dsc_disable(struct sde_encoder_virt *sde_enc)
  1443. {
  1444. int i;
  1445. struct sde_hw_pingpong *hw_pp = NULL;
  1446. struct sde_hw_pingpong *hw_dsc_pp = NULL;
  1447. struct sde_hw_dsc *hw_dsc = NULL;
  1448. struct sde_hw_ctl *hw_ctl = NULL;
  1449. struct sde_ctl_dsc_cfg cfg;
  1450. if (!sde_enc || !sde_enc->phys_encs[0] ||
  1451. !sde_enc->phys_encs[0]->connector) {
  1452. SDE_ERROR("invalid params %d %d\n",
  1453. !sde_enc, sde_enc ? !sde_enc->phys_encs[0] : -1);
  1454. return;
  1455. }
  1456. if (sde_enc->cur_master)
  1457. hw_ctl = sde_enc->cur_master->hw_ctl;
  1458. /* Disable DSC for all the pp's present in this topology */
  1459. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1460. hw_pp = sde_enc->hw_pp[i];
  1461. hw_dsc = sde_enc->hw_dsc[i];
  1462. hw_dsc_pp = sde_enc->hw_dsc_pp[i];
  1463. _sde_encoder_dsc_pipe_cfg(hw_dsc, hw_pp, NULL,
  1464. 0, 0, 0, hw_dsc_pp);
  1465. if (hw_dsc)
  1466. sde_enc->dirty_dsc_ids[i] = hw_dsc->idx;
  1467. }
  1468. /* Clear the DSC ACTIVE config for this CTL */
  1469. if (hw_ctl && hw_ctl->ops.setup_dsc_cfg) {
  1470. memset(&cfg, 0, sizeof(cfg));
  1471. hw_ctl->ops.setup_dsc_cfg(hw_ctl, &cfg);
  1472. }
  1473. /**
  1474. * Since pending flushes from previous commit get cleared
  1475. * sometime after this point, setting DSC flush bits now
  1476. * will have no effect. Therefore dirty_dsc_ids track which
  1477. * DSC blocks must be flushed for the next trigger.
  1478. */
  1479. }
  1480. static int _sde_encoder_switch_to_watchdog_vsync(struct drm_encoder *drm_enc)
  1481. {
  1482. struct sde_encoder_virt *sde_enc;
  1483. struct msm_display_info disp_info;
  1484. if (!drm_enc) {
  1485. pr_err("invalid drm encoder\n");
  1486. return -EINVAL;
  1487. }
  1488. sde_enc = to_sde_encoder_virt(drm_enc);
  1489. sde_encoder_control_te(drm_enc, false);
  1490. memcpy(&disp_info, &sde_enc->disp_info, sizeof(disp_info));
  1491. disp_info.is_te_using_watchdog_timer = true;
  1492. _sde_encoder_update_vsync_source(sde_enc, &disp_info, false);
  1493. sde_encoder_control_te(drm_enc, true);
  1494. return 0;
  1495. }
  1496. static int _sde_encoder_rsc_client_update_vsync_wait(
  1497. struct drm_encoder *drm_enc, struct sde_encoder_virt *sde_enc,
  1498. int wait_vblank_crtc_id)
  1499. {
  1500. int wait_refcount = 0, ret = 0;
  1501. int pipe = -1;
  1502. int wait_count = 0;
  1503. struct drm_crtc *primary_crtc;
  1504. struct drm_crtc *crtc;
  1505. crtc = sde_enc->crtc;
  1506. if (wait_vblank_crtc_id)
  1507. wait_refcount =
  1508. sde_rsc_client_get_vsync_refcount(sde_enc->rsc_client);
  1509. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id, wait_refcount,
  1510. SDE_EVTLOG_FUNC_ENTRY);
  1511. if (crtc->base.id != wait_vblank_crtc_id) {
  1512. primary_crtc = drm_crtc_find(drm_enc->dev,
  1513. NULL, wait_vblank_crtc_id);
  1514. if (!primary_crtc) {
  1515. SDE_ERROR_ENC(sde_enc,
  1516. "failed to find primary crtc id %d\n",
  1517. wait_vblank_crtc_id);
  1518. return -EINVAL;
  1519. }
  1520. pipe = drm_crtc_index(primary_crtc);
  1521. }
  1522. /**
  1523. * note: VBLANK is expected to be enabled at this point in
  1524. * resource control state machine if on primary CRTC
  1525. */
  1526. for (wait_count = 0; wait_count < MAX_RSC_WAIT; wait_count++) {
  1527. if (sde_rsc_client_is_state_update_complete(
  1528. sde_enc->rsc_client))
  1529. break;
  1530. if (crtc->base.id == wait_vblank_crtc_id)
  1531. ret = sde_encoder_wait_for_event(drm_enc,
  1532. MSM_ENC_VBLANK);
  1533. else
  1534. drm_wait_one_vblank(drm_enc->dev, pipe);
  1535. if (ret) {
  1536. SDE_ERROR_ENC(sde_enc,
  1537. "wait for vblank failed ret:%d\n", ret);
  1538. /**
  1539. * rsc hardware may hang without vsync. avoid rsc hang
  1540. * by generating the vsync from watchdog timer.
  1541. */
  1542. if (crtc->base.id == wait_vblank_crtc_id)
  1543. _sde_encoder_switch_to_watchdog_vsync(drm_enc);
  1544. }
  1545. }
  1546. if (wait_count >= MAX_RSC_WAIT)
  1547. SDE_EVT32(DRMID(drm_enc), wait_vblank_crtc_id, wait_count,
  1548. SDE_EVTLOG_ERROR);
  1549. if (wait_refcount)
  1550. sde_rsc_client_reset_vsync_refcount(sde_enc->rsc_client);
  1551. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id, wait_refcount,
  1552. SDE_EVTLOG_FUNC_EXIT);
  1553. return ret;
  1554. }
  1555. static int _sde_encoder_update_rsc_client(
  1556. struct drm_encoder *drm_enc, bool enable)
  1557. {
  1558. struct sde_encoder_virt *sde_enc;
  1559. struct drm_crtc *crtc;
  1560. enum sde_rsc_state rsc_state = SDE_RSC_IDLE_STATE;
  1561. struct sde_rsc_cmd_config *rsc_config;
  1562. int ret, prefill_lines;
  1563. struct msm_display_info *disp_info;
  1564. struct msm_mode_info *mode_info;
  1565. int wait_vblank_crtc_id = SDE_RSC_INVALID_CRTC_ID;
  1566. u32 qsync_mode = 0;
  1567. if (!drm_enc || !drm_enc->dev) {
  1568. SDE_ERROR("invalid encoder arguments\n");
  1569. return -EINVAL;
  1570. }
  1571. sde_enc = to_sde_encoder_virt(drm_enc);
  1572. mode_info = &sde_enc->mode_info;
  1573. crtc = sde_enc->crtc;
  1574. if (!sde_enc->crtc) {
  1575. SDE_ERROR("invalid crtc parameter\n");
  1576. return -EINVAL;
  1577. }
  1578. disp_info = &sde_enc->disp_info;
  1579. rsc_config = &sde_enc->rsc_config;
  1580. if (!sde_enc->rsc_client) {
  1581. SDE_DEBUG_ENC(sde_enc, "rsc client not created\n");
  1582. return 0;
  1583. }
  1584. /**
  1585. * only primary command mode panel without Qsync can request CMD state.
  1586. * all other panels/displays can request for VID state including
  1587. * secondary command mode panel.
  1588. * Clone mode encoder can request CLK STATE only.
  1589. */
  1590. if (sde_enc->cur_master)
  1591. qsync_mode = sde_connector_get_qsync_mode(
  1592. sde_enc->cur_master->connector);
  1593. if (sde_encoder_in_clone_mode(drm_enc) ||
  1594. (disp_info->display_type != SDE_CONNECTOR_PRIMARY) ||
  1595. (disp_info->display_type && qsync_mode))
  1596. rsc_state = enable ? SDE_RSC_CLK_STATE : SDE_RSC_IDLE_STATE;
  1597. else if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1598. rsc_state = enable ? SDE_RSC_CMD_STATE : SDE_RSC_IDLE_STATE;
  1599. else if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE))
  1600. rsc_state = enable ? SDE_RSC_VID_STATE : SDE_RSC_IDLE_STATE;
  1601. SDE_EVT32(rsc_state, qsync_mode);
  1602. prefill_lines = mode_info->prefill_lines;
  1603. /* compare specific items and reconfigure the rsc */
  1604. if ((rsc_config->fps != mode_info->frame_rate) ||
  1605. (rsc_config->vtotal != mode_info->vtotal) ||
  1606. (rsc_config->prefill_lines != prefill_lines) ||
  1607. (rsc_config->jitter_numer != mode_info->jitter_numer) ||
  1608. (rsc_config->jitter_denom != mode_info->jitter_denom)) {
  1609. rsc_config->fps = mode_info->frame_rate;
  1610. rsc_config->vtotal = mode_info->vtotal;
  1611. rsc_config->prefill_lines = prefill_lines;
  1612. rsc_config->jitter_numer = mode_info->jitter_numer;
  1613. rsc_config->jitter_denom = mode_info->jitter_denom;
  1614. sde_enc->rsc_state_init = false;
  1615. }
  1616. if (rsc_state != SDE_RSC_IDLE_STATE && !sde_enc->rsc_state_init
  1617. && (disp_info->display_type == SDE_CONNECTOR_PRIMARY)) {
  1618. /* update it only once */
  1619. sde_enc->rsc_state_init = true;
  1620. ret = sde_rsc_client_state_update(sde_enc->rsc_client,
  1621. rsc_state, rsc_config, crtc->base.id,
  1622. &wait_vblank_crtc_id);
  1623. } else {
  1624. ret = sde_rsc_client_state_update(sde_enc->rsc_client,
  1625. rsc_state, NULL, crtc->base.id,
  1626. &wait_vblank_crtc_id);
  1627. }
  1628. /**
  1629. * if RSC performed a state change that requires a VBLANK wait, it will
  1630. * set wait_vblank_crtc_id to the CRTC whose VBLANK we must wait on.
  1631. *
  1632. * if we are the primary display, we will need to enable and wait
  1633. * locally since we hold the commit thread
  1634. *
  1635. * if we are an external display, we must send a signal to the primary
  1636. * to enable its VBLANK and wait one, since the RSC hardware is driven
  1637. * by the primary panel's VBLANK signals
  1638. */
  1639. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id);
  1640. if (ret) {
  1641. SDE_ERROR_ENC(sde_enc,
  1642. "sde rsc client update failed ret:%d\n", ret);
  1643. return ret;
  1644. } else if (wait_vblank_crtc_id == SDE_RSC_INVALID_CRTC_ID) {
  1645. return ret;
  1646. }
  1647. ret = _sde_encoder_rsc_client_update_vsync_wait(drm_enc,
  1648. sde_enc, wait_vblank_crtc_id);
  1649. return ret;
  1650. }
  1651. static void _sde_encoder_irq_control(struct drm_encoder *drm_enc, bool enable)
  1652. {
  1653. struct sde_encoder_virt *sde_enc;
  1654. int i;
  1655. if (!drm_enc) {
  1656. SDE_ERROR("invalid encoder\n");
  1657. return;
  1658. }
  1659. sde_enc = to_sde_encoder_virt(drm_enc);
  1660. SDE_DEBUG_ENC(sde_enc, "enable:%d\n", enable);
  1661. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1662. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1663. if (phys && phys->ops.irq_control)
  1664. phys->ops.irq_control(phys, enable);
  1665. }
  1666. }
  1667. /* keep track of the userspace vblank during modeset */
  1668. static void _sde_encoder_modeset_helper_locked(struct drm_encoder *drm_enc,
  1669. u32 sw_event)
  1670. {
  1671. struct sde_encoder_virt *sde_enc;
  1672. bool enable;
  1673. int i;
  1674. if (!drm_enc) {
  1675. SDE_ERROR("invalid encoder\n");
  1676. return;
  1677. }
  1678. sde_enc = to_sde_encoder_virt(drm_enc);
  1679. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, vblank_enabled:%d\n",
  1680. sw_event, sde_enc->vblank_enabled);
  1681. /* nothing to do if vblank not enabled by userspace */
  1682. if (!sde_enc->vblank_enabled)
  1683. return;
  1684. /* disable vblank on pre_modeset */
  1685. if (sw_event == SDE_ENC_RC_EVENT_PRE_MODESET)
  1686. enable = false;
  1687. /* enable vblank on post_modeset */
  1688. else if (sw_event == SDE_ENC_RC_EVENT_POST_MODESET)
  1689. enable = true;
  1690. else
  1691. return;
  1692. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1693. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1694. if (phys && phys->ops.control_vblank_irq)
  1695. phys->ops.control_vblank_irq(phys, enable);
  1696. }
  1697. }
  1698. struct sde_rsc_client *sde_encoder_get_rsc_client(struct drm_encoder *drm_enc)
  1699. {
  1700. struct sde_encoder_virt *sde_enc;
  1701. if (!drm_enc)
  1702. return NULL;
  1703. sde_enc = to_sde_encoder_virt(drm_enc);
  1704. return sde_enc->rsc_client;
  1705. }
  1706. static int _sde_encoder_resource_control_helper(struct drm_encoder *drm_enc,
  1707. bool enable)
  1708. {
  1709. struct msm_drm_private *priv;
  1710. struct sde_kms *sde_kms;
  1711. struct sde_encoder_virt *sde_enc;
  1712. int rc;
  1713. bool is_cmd_mode = false;
  1714. sde_enc = to_sde_encoder_virt(drm_enc);
  1715. priv = drm_enc->dev->dev_private;
  1716. sde_kms = to_sde_kms(priv->kms);
  1717. if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1718. is_cmd_mode = true;
  1719. SDE_DEBUG_ENC(sde_enc, "enable:%d\n", enable);
  1720. SDE_EVT32(DRMID(drm_enc), enable);
  1721. if (!sde_enc->cur_master) {
  1722. SDE_ERROR("encoder master not set\n");
  1723. return -EINVAL;
  1724. }
  1725. if (enable) {
  1726. /* enable SDE core clks */
  1727. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  1728. if (rc < 0) {
  1729. SDE_ERROR("failed to enable power resource %d\n", rc);
  1730. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  1731. return rc;
  1732. }
  1733. sde_enc->elevated_ahb_vote = true;
  1734. /* enable DSI clks */
  1735. rc = sde_connector_clk_ctrl(sde_enc->cur_master->connector,
  1736. true);
  1737. if (rc) {
  1738. SDE_ERROR("failed to enable clk control %d\n", rc);
  1739. pm_runtime_put_sync(drm_enc->dev->dev);
  1740. return rc;
  1741. }
  1742. /* enable all the irq */
  1743. _sde_encoder_irq_control(drm_enc, true);
  1744. if (is_cmd_mode)
  1745. _sde_encoder_pm_qos_add_request(drm_enc, sde_kms);
  1746. } else {
  1747. if (is_cmd_mode)
  1748. _sde_encoder_pm_qos_remove_request(drm_enc, sde_kms);
  1749. /* disable all the irq */
  1750. _sde_encoder_irq_control(drm_enc, false);
  1751. /* disable DSI clks */
  1752. sde_connector_clk_ctrl(sde_enc->cur_master->connector, false);
  1753. /* disable SDE core clks */
  1754. pm_runtime_put_sync(drm_enc->dev->dev);
  1755. }
  1756. return 0;
  1757. }
  1758. static void sde_encoder_misr_configure(struct drm_encoder *drm_enc,
  1759. bool enable, u32 frame_count)
  1760. {
  1761. struct sde_encoder_virt *sde_enc;
  1762. int i;
  1763. if (!drm_enc) {
  1764. SDE_ERROR("invalid encoder\n");
  1765. return;
  1766. }
  1767. sde_enc = to_sde_encoder_virt(drm_enc);
  1768. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1769. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1770. if (!phys || !phys->ops.setup_misr)
  1771. continue;
  1772. phys->ops.setup_misr(phys, enable, frame_count);
  1773. }
  1774. }
  1775. static void sde_encoder_input_event_handler(struct input_handle *handle,
  1776. unsigned int type, unsigned int code, int value)
  1777. {
  1778. struct drm_encoder *drm_enc = NULL;
  1779. struct sde_encoder_virt *sde_enc = NULL;
  1780. struct msm_drm_thread *disp_thread = NULL;
  1781. struct msm_drm_private *priv = NULL;
  1782. if (!handle || !handle->handler || !handle->handler->private) {
  1783. SDE_ERROR("invalid encoder for the input event\n");
  1784. return;
  1785. }
  1786. drm_enc = (struct drm_encoder *)handle->handler->private;
  1787. if (!drm_enc->dev || !drm_enc->dev->dev_private) {
  1788. SDE_ERROR("invalid parameters\n");
  1789. return;
  1790. }
  1791. priv = drm_enc->dev->dev_private;
  1792. sde_enc = to_sde_encoder_virt(drm_enc);
  1793. if (!sde_enc->crtc || (sde_enc->crtc->index
  1794. >= ARRAY_SIZE(priv->disp_thread))) {
  1795. SDE_DEBUG_ENC(sde_enc,
  1796. "invalid cached CRTC: %d or crtc index: %d\n",
  1797. sde_enc->crtc == NULL,
  1798. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  1799. return;
  1800. }
  1801. SDE_EVT32_VERBOSE(DRMID(drm_enc));
  1802. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1803. kthread_queue_work(&disp_thread->worker,
  1804. &sde_enc->input_event_work);
  1805. }
  1806. void sde_encoder_control_idle_pc(struct drm_encoder *drm_enc, bool enable)
  1807. {
  1808. struct sde_encoder_virt *sde_enc;
  1809. if (!drm_enc) {
  1810. SDE_ERROR("invalid encoder\n");
  1811. return;
  1812. }
  1813. sde_enc = to_sde_encoder_virt(drm_enc);
  1814. /* return early if there is no state change */
  1815. if (sde_enc->idle_pc_enabled == enable)
  1816. return;
  1817. sde_enc->idle_pc_enabled = enable;
  1818. SDE_DEBUG("idle-pc state:%d\n", sde_enc->idle_pc_enabled);
  1819. SDE_EVT32(sde_enc->idle_pc_enabled);
  1820. }
  1821. static void _sde_encoder_rc_cancel_delayed(struct sde_encoder_virt *sde_enc,
  1822. u32 sw_event)
  1823. {
  1824. if (kthread_cancel_delayed_work_sync(
  1825. &sde_enc->delayed_off_work))
  1826. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work cancelled\n",
  1827. sw_event);
  1828. }
  1829. static int _sde_encoder_rc_kickoff(struct drm_encoder *drm_enc,
  1830. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1831. {
  1832. int ret = 0;
  1833. /* cancel delayed off work, if any */
  1834. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1835. mutex_lock(&sde_enc->rc_lock);
  1836. /* return if the resource control is already in ON state */
  1837. if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON) {
  1838. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in ON state\n",
  1839. sw_event);
  1840. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1841. SDE_EVTLOG_FUNC_CASE1);
  1842. goto end;
  1843. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_OFF &&
  1844. sde_enc->rc_state != SDE_ENC_RC_STATE_IDLE) {
  1845. SDE_ERROR_ENC(sde_enc, "sw_event:%d, rc in state %d\n",
  1846. sw_event, sde_enc->rc_state);
  1847. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1848. SDE_EVTLOG_ERROR);
  1849. goto end;
  1850. }
  1851. if (is_vid_mode && sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1852. _sde_encoder_irq_control(drm_enc, true);
  1853. } else {
  1854. /* enable all the clks and resources */
  1855. ret = _sde_encoder_resource_control_helper(drm_enc,
  1856. true);
  1857. if (ret) {
  1858. SDE_ERROR_ENC(sde_enc,
  1859. "sw_event:%d, rc in state %d\n",
  1860. sw_event, sde_enc->rc_state);
  1861. SDE_EVT32(DRMID(drm_enc), sw_event,
  1862. sde_enc->rc_state,
  1863. SDE_EVTLOG_ERROR);
  1864. goto end;
  1865. }
  1866. _sde_encoder_update_rsc_client(drm_enc, true);
  1867. }
  1868. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1869. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE1);
  1870. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1871. end:
  1872. mutex_unlock(&sde_enc->rc_lock);
  1873. return ret;
  1874. }
  1875. static int _sde_encoder_rc_frame_done(struct drm_encoder *drm_enc,
  1876. u32 sw_event, struct sde_encoder_virt *sde_enc,
  1877. struct msm_drm_private *priv)
  1878. {
  1879. unsigned int lp, idle_pc_duration;
  1880. struct msm_drm_thread *disp_thread;
  1881. bool autorefresh_enabled = false;
  1882. if (!sde_enc->crtc) {
  1883. SDE_ERROR("invalid crtc, sw_event:%u\n", sw_event);
  1884. return -EINVAL;
  1885. }
  1886. if (sde_enc->crtc->index >= ARRAY_SIZE(priv->disp_thread)) {
  1887. SDE_ERROR("invalid crtc index :%u\n",
  1888. sde_enc->crtc->index);
  1889. return -EINVAL;
  1890. }
  1891. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1892. /*
  1893. * mutex lock is not used as this event happens at interrupt
  1894. * context. And locking is not required as, the other events
  1895. * like KICKOFF and STOP does a wait-for-idle before executing
  1896. * the resource_control
  1897. */
  1898. if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
  1899. SDE_ERROR_ENC(sde_enc, "sw_event:%d,rc:%d-unexpected\n",
  1900. sw_event, sde_enc->rc_state);
  1901. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1902. SDE_EVTLOG_ERROR);
  1903. return -EINVAL;
  1904. }
  1905. /*
  1906. * schedule off work item only when there are no
  1907. * frames pending
  1908. */
  1909. if (sde_crtc_frame_pending(sde_enc->crtc) > 1) {
  1910. SDE_DEBUG_ENC(sde_enc, "skip schedule work");
  1911. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1912. SDE_EVTLOG_FUNC_CASE2);
  1913. return 0;
  1914. }
  1915. /* schedule delayed off work if autorefresh is disabled */
  1916. if (sde_enc->cur_master &&
  1917. sde_enc->cur_master->ops.is_autorefresh_enabled)
  1918. autorefresh_enabled =
  1919. sde_enc->cur_master->ops.is_autorefresh_enabled(
  1920. sde_enc->cur_master);
  1921. /* set idle timeout based on master connector's lp value */
  1922. if (sde_enc->cur_master)
  1923. lp = sde_connector_get_lp(
  1924. sde_enc->cur_master->connector);
  1925. else
  1926. lp = SDE_MODE_DPMS_ON;
  1927. if (lp == SDE_MODE_DPMS_LP2)
  1928. idle_pc_duration = IDLE_SHORT_TIMEOUT;
  1929. else
  1930. idle_pc_duration = IDLE_POWERCOLLAPSE_DURATION;
  1931. if (!autorefresh_enabled)
  1932. kthread_mod_delayed_work(
  1933. &disp_thread->worker,
  1934. &sde_enc->delayed_off_work,
  1935. msecs_to_jiffies(idle_pc_duration));
  1936. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1937. autorefresh_enabled,
  1938. idle_pc_duration, SDE_EVTLOG_FUNC_CASE2);
  1939. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work scheduled\n",
  1940. sw_event);
  1941. return 0;
  1942. }
  1943. static int _sde_encoder_rc_pre_stop(struct drm_encoder *drm_enc,
  1944. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1945. {
  1946. /* cancel delayed off work, if any */
  1947. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1948. mutex_lock(&sde_enc->rc_lock);
  1949. if (is_vid_mode &&
  1950. sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1951. _sde_encoder_irq_control(drm_enc, true);
  1952. }
  1953. /* skip if is already OFF or IDLE, resources are off already */
  1954. else if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF ||
  1955. sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1956. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in %d state\n",
  1957. sw_event, sde_enc->rc_state);
  1958. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1959. SDE_EVTLOG_FUNC_CASE3);
  1960. goto end;
  1961. }
  1962. /**
  1963. * IRQs are still enabled currently, which allows wait for
  1964. * VBLANK which RSC may require to correctly transition to OFF
  1965. */
  1966. _sde_encoder_update_rsc_client(drm_enc, false);
  1967. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1968. SDE_ENC_RC_STATE_PRE_OFF,
  1969. SDE_EVTLOG_FUNC_CASE3);
  1970. sde_enc->rc_state = SDE_ENC_RC_STATE_PRE_OFF;
  1971. end:
  1972. mutex_unlock(&sde_enc->rc_lock);
  1973. return 0;
  1974. }
  1975. static int _sde_encoder_rc_stop(struct drm_encoder *drm_enc,
  1976. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1977. {
  1978. int ret = 0;
  1979. /* cancel vsync event work and timer */
  1980. kthread_cancel_work_sync(&sde_enc->vsync_event_work);
  1981. if (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DSI)
  1982. del_timer_sync(&sde_enc->vsync_event_timer);
  1983. mutex_lock(&sde_enc->rc_lock);
  1984. /* return if the resource control is already in OFF state */
  1985. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1986. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1987. sw_event);
  1988. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1989. SDE_EVTLOG_FUNC_CASE4);
  1990. goto end;
  1991. } else if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON ||
  1992. sde_enc->rc_state == SDE_ENC_RC_STATE_MODESET) {
  1993. SDE_ERROR_ENC(sde_enc, "sw_event:%d, rc in state %d\n",
  1994. sw_event, sde_enc->rc_state);
  1995. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1996. SDE_EVTLOG_ERROR);
  1997. ret = -EINVAL;
  1998. goto end;
  1999. }
  2000. /**
  2001. * expect to arrive here only if in either idle state or pre-off
  2002. * and in IDLE state the resources are already disabled
  2003. */
  2004. if (sde_enc->rc_state == SDE_ENC_RC_STATE_PRE_OFF)
  2005. _sde_encoder_resource_control_helper(drm_enc, false);
  2006. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  2007. SDE_ENC_RC_STATE_OFF, SDE_EVTLOG_FUNC_CASE4);
  2008. sde_enc->rc_state = SDE_ENC_RC_STATE_OFF;
  2009. end:
  2010. mutex_unlock(&sde_enc->rc_lock);
  2011. return ret;
  2012. }
  2013. static int _sde_encoder_rc_pre_modeset(struct drm_encoder *drm_enc,
  2014. u32 sw_event, struct sde_encoder_virt *sde_enc)
  2015. {
  2016. int ret = 0;
  2017. /* cancel delayed off work, if any */
  2018. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  2019. mutex_lock(&sde_enc->rc_lock);
  2020. /* return if the resource control is already in ON state */
  2021. if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
  2022. /* enable all the clks and resources */
  2023. ret = _sde_encoder_resource_control_helper(drm_enc,
  2024. true);
  2025. if (ret) {
  2026. SDE_ERROR_ENC(sde_enc,
  2027. "sw_event:%d, rc in state %d\n",
  2028. sw_event, sde_enc->rc_state);
  2029. SDE_EVT32(DRMID(drm_enc), sw_event,
  2030. sde_enc->rc_state,
  2031. SDE_EVTLOG_ERROR);
  2032. goto end;
  2033. }
  2034. _sde_encoder_update_rsc_client(drm_enc, true);
  2035. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  2036. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE5);
  2037. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  2038. }
  2039. ret = sde_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
  2040. if (ret && ret != -EWOULDBLOCK) {
  2041. SDE_ERROR_ENC(sde_enc,
  2042. "wait for commit done returned %d\n",
  2043. ret);
  2044. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  2045. ret, SDE_EVTLOG_ERROR);
  2046. ret = -EINVAL;
  2047. goto end;
  2048. }
  2049. _sde_encoder_irq_control(drm_enc, false);
  2050. _sde_encoder_modeset_helper_locked(drm_enc, sw_event);
  2051. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  2052. SDE_ENC_RC_STATE_MODESET, SDE_EVTLOG_FUNC_CASE5);
  2053. sde_enc->rc_state = SDE_ENC_RC_STATE_MODESET;
  2054. end:
  2055. mutex_unlock(&sde_enc->rc_lock);
  2056. return ret;
  2057. }
  2058. static int _sde_encoder_rc_post_modeset(struct drm_encoder *drm_enc,
  2059. u32 sw_event, struct sde_encoder_virt *sde_enc)
  2060. {
  2061. int ret = 0;
  2062. mutex_lock(&sde_enc->rc_lock);
  2063. /* return if the resource control is already in ON state */
  2064. if (sde_enc->rc_state != SDE_ENC_RC_STATE_MODESET) {
  2065. SDE_ERROR_ENC(sde_enc,
  2066. "sw_event:%d, rc:%d !MODESET state\n",
  2067. sw_event, sde_enc->rc_state);
  2068. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  2069. SDE_EVTLOG_ERROR);
  2070. ret = -EINVAL;
  2071. goto end;
  2072. }
  2073. _sde_encoder_modeset_helper_locked(drm_enc, sw_event);
  2074. _sde_encoder_irq_control(drm_enc, true);
  2075. _sde_encoder_update_rsc_client(drm_enc, true);
  2076. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  2077. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE6);
  2078. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  2079. end:
  2080. mutex_unlock(&sde_enc->rc_lock);
  2081. return ret;
  2082. }
  2083. static int _sde_encoder_rc_idle(struct drm_encoder *drm_enc,
  2084. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  2085. {
  2086. mutex_lock(&sde_enc->rc_lock);
  2087. if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
  2088. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc:%d !ON state\n",
  2089. sw_event, sde_enc->rc_state);
  2090. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  2091. SDE_EVTLOG_ERROR);
  2092. goto end;
  2093. } else if (sde_crtc_frame_pending(sde_enc->crtc) > 1) {
  2094. SDE_ERROR_ENC(sde_enc, "skip idle entry");
  2095. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  2096. sde_crtc_frame_pending(sde_enc->crtc),
  2097. SDE_EVTLOG_ERROR);
  2098. goto end;
  2099. }
  2100. if (is_vid_mode) {
  2101. _sde_encoder_irq_control(drm_enc, false);
  2102. } else {
  2103. /* disable all the clks and resources */
  2104. _sde_encoder_update_rsc_client(drm_enc, false);
  2105. _sde_encoder_resource_control_helper(drm_enc, false);
  2106. }
  2107. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  2108. SDE_ENC_RC_STATE_IDLE, SDE_EVTLOG_FUNC_CASE7);
  2109. sde_enc->rc_state = SDE_ENC_RC_STATE_IDLE;
  2110. end:
  2111. mutex_unlock(&sde_enc->rc_lock);
  2112. return 0;
  2113. }
  2114. static int _sde_encoder_rc_early_wakeup(struct drm_encoder *drm_enc,
  2115. u32 sw_event, struct sde_encoder_virt *sde_enc,
  2116. struct msm_drm_private *priv, bool is_vid_mode)
  2117. {
  2118. bool autorefresh_enabled = false;
  2119. struct msm_drm_thread *disp_thread;
  2120. int ret = 0;
  2121. if (!sde_enc->crtc ||
  2122. sde_enc->crtc->index >= ARRAY_SIZE(priv->disp_thread)) {
  2123. SDE_DEBUG_ENC(sde_enc,
  2124. "invalid crtc:%d or crtc index:%d , sw_event:%u\n",
  2125. sde_enc->crtc == NULL,
  2126. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL,
  2127. sw_event);
  2128. return -EINVAL;
  2129. }
  2130. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  2131. mutex_lock(&sde_enc->rc_lock);
  2132. if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON) {
  2133. if (sde_enc->cur_master &&
  2134. sde_enc->cur_master->ops.is_autorefresh_enabled)
  2135. autorefresh_enabled =
  2136. sde_enc->cur_master->ops.is_autorefresh_enabled(
  2137. sde_enc->cur_master);
  2138. if (autorefresh_enabled) {
  2139. SDE_DEBUG_ENC(sde_enc,
  2140. "not handling early wakeup since auto refresh is enabled\n");
  2141. goto end;
  2142. }
  2143. if (!sde_crtc_frame_pending(sde_enc->crtc))
  2144. kthread_mod_delayed_work(&disp_thread->worker,
  2145. &sde_enc->delayed_off_work,
  2146. msecs_to_jiffies(
  2147. IDLE_POWERCOLLAPSE_DURATION));
  2148. } else if (sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  2149. /* enable all the clks and resources */
  2150. ret = _sde_encoder_resource_control_helper(drm_enc,
  2151. true);
  2152. if (ret) {
  2153. SDE_ERROR_ENC(sde_enc,
  2154. "sw_event:%d, rc in state %d\n",
  2155. sw_event, sde_enc->rc_state);
  2156. SDE_EVT32(DRMID(drm_enc), sw_event,
  2157. sde_enc->rc_state,
  2158. SDE_EVTLOG_ERROR);
  2159. goto end;
  2160. }
  2161. _sde_encoder_update_rsc_client(drm_enc, true);
  2162. /*
  2163. * In some cases, commit comes with slight delay
  2164. * (> 80 ms)after early wake up, prevent clock switch
  2165. * off to avoid jank in next update. So, increase the
  2166. * command mode idle timeout sufficiently to prevent
  2167. * such case.
  2168. */
  2169. kthread_mod_delayed_work(&disp_thread->worker,
  2170. &sde_enc->delayed_off_work,
  2171. msecs_to_jiffies(
  2172. IDLE_POWERCOLLAPSE_IN_EARLY_WAKEUP));
  2173. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  2174. }
  2175. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  2176. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE8);
  2177. end:
  2178. mutex_unlock(&sde_enc->rc_lock);
  2179. return ret;
  2180. }
  2181. static int sde_encoder_resource_control(struct drm_encoder *drm_enc,
  2182. u32 sw_event)
  2183. {
  2184. struct sde_encoder_virt *sde_enc;
  2185. struct msm_drm_private *priv;
  2186. int ret = 0;
  2187. bool is_vid_mode = false;
  2188. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  2189. SDE_ERROR("invalid encoder parameters, sw_event:%u\n",
  2190. sw_event);
  2191. return -EINVAL;
  2192. }
  2193. sde_enc = to_sde_encoder_virt(drm_enc);
  2194. priv = drm_enc->dev->dev_private;
  2195. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_VIDEO_MODE))
  2196. is_vid_mode = true;
  2197. /*
  2198. * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
  2199. * events and return early for other events (ie wb display).
  2200. */
  2201. if (!sde_enc->idle_pc_enabled &&
  2202. (sw_event != SDE_ENC_RC_EVENT_KICKOFF &&
  2203. sw_event != SDE_ENC_RC_EVENT_PRE_MODESET &&
  2204. sw_event != SDE_ENC_RC_EVENT_POST_MODESET &&
  2205. sw_event != SDE_ENC_RC_EVENT_STOP &&
  2206. sw_event != SDE_ENC_RC_EVENT_PRE_STOP))
  2207. return 0;
  2208. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, idle_pc:%d\n",
  2209. sw_event, sde_enc->idle_pc_enabled);
  2210. SDE_EVT32_VERBOSE(DRMID(drm_enc), sw_event, sde_enc->idle_pc_enabled,
  2211. sde_enc->rc_state, SDE_EVTLOG_FUNC_ENTRY);
  2212. switch (sw_event) {
  2213. case SDE_ENC_RC_EVENT_KICKOFF:
  2214. ret = _sde_encoder_rc_kickoff(drm_enc, sw_event, sde_enc,
  2215. is_vid_mode);
  2216. break;
  2217. case SDE_ENC_RC_EVENT_FRAME_DONE:
  2218. ret = _sde_encoder_rc_frame_done(drm_enc, sw_event, sde_enc,
  2219. priv);
  2220. break;
  2221. case SDE_ENC_RC_EVENT_PRE_STOP:
  2222. ret = _sde_encoder_rc_pre_stop(drm_enc, sw_event, sde_enc,
  2223. is_vid_mode);
  2224. break;
  2225. case SDE_ENC_RC_EVENT_STOP:
  2226. ret = _sde_encoder_rc_stop(drm_enc, sw_event, sde_enc);
  2227. break;
  2228. case SDE_ENC_RC_EVENT_PRE_MODESET:
  2229. ret = _sde_encoder_rc_pre_modeset(drm_enc, sw_event, sde_enc);
  2230. break;
  2231. case SDE_ENC_RC_EVENT_POST_MODESET:
  2232. ret = _sde_encoder_rc_post_modeset(drm_enc, sw_event, sde_enc);
  2233. break;
  2234. case SDE_ENC_RC_EVENT_ENTER_IDLE:
  2235. ret = _sde_encoder_rc_idle(drm_enc, sw_event, sde_enc,
  2236. is_vid_mode);
  2237. break;
  2238. case SDE_ENC_RC_EVENT_EARLY_WAKEUP:
  2239. ret = _sde_encoder_rc_early_wakeup(drm_enc, sw_event, sde_enc,
  2240. priv, is_vid_mode);
  2241. break;
  2242. default:
  2243. SDE_EVT32(DRMID(drm_enc), sw_event, SDE_EVTLOG_ERROR);
  2244. SDE_ERROR("unexpected sw_event: %d\n", sw_event);
  2245. break;
  2246. }
  2247. SDE_EVT32_VERBOSE(DRMID(drm_enc), sw_event, sde_enc->idle_pc_enabled,
  2248. sde_enc->rc_state, SDE_EVTLOG_FUNC_EXIT);
  2249. return ret;
  2250. }
  2251. static void sde_encoder_virt_mode_switch(enum sde_intf_mode intf_mode,
  2252. struct sde_encoder_virt *sde_enc,
  2253. struct drm_display_mode *adj_mode)
  2254. {
  2255. int i = 0;
  2256. if (intf_mode == INTF_MODE_CMD) {
  2257. for (i = 0; i < sde_enc->num_phys_encs; i++)
  2258. sde_enc->phys_encs[i] = sde_enc->phys_vid_encs[i];
  2259. sde_enc->disp_info.curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  2260. SDE_DEBUG_ENC(sde_enc, "switch to video physical encoder\n");
  2261. SDE_EVT32(DRMID(&sde_enc->base), intf_mode,
  2262. msm_is_mode_seamless_poms(adj_mode),
  2263. SDE_EVTLOG_FUNC_CASE1);
  2264. }
  2265. if (intf_mode == INTF_MODE_VIDEO) {
  2266. for (i = 0; i < sde_enc->num_phys_encs; i++)
  2267. sde_enc->phys_encs[i] = sde_enc->phys_cmd_encs[i];
  2268. sde_enc->disp_info.curr_panel_mode = MSM_DISPLAY_CMD_MODE;
  2269. SDE_EVT32(DRMID(&sde_enc->base), intf_mode,
  2270. msm_is_mode_seamless_poms(adj_mode),
  2271. SDE_EVTLOG_FUNC_CASE2);
  2272. SDE_DEBUG_ENC(sde_enc, "switch to command physical encoder\n");
  2273. }
  2274. }
  2275. static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc,
  2276. struct drm_display_mode *mode,
  2277. struct drm_display_mode *adj_mode)
  2278. {
  2279. struct sde_encoder_virt *sde_enc;
  2280. struct msm_drm_private *priv;
  2281. struct sde_kms *sde_kms;
  2282. struct list_head *connector_list;
  2283. struct drm_connector *conn = NULL, *conn_iter;
  2284. struct sde_connector_state *sde_conn_state = NULL;
  2285. struct sde_connector *sde_conn = NULL;
  2286. struct sde_rm_hw_iter dsc_iter, pp_iter;
  2287. struct sde_rm_hw_request request_hw;
  2288. enum sde_intf_mode intf_mode;
  2289. int i = 0, ret;
  2290. if (!drm_enc) {
  2291. SDE_ERROR("invalid encoder\n");
  2292. return;
  2293. }
  2294. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  2295. SDE_ERROR("power resource is not enabled\n");
  2296. return;
  2297. }
  2298. sde_enc = to_sde_encoder_virt(drm_enc);
  2299. SDE_DEBUG_ENC(sde_enc, "\n");
  2300. priv = drm_enc->dev->dev_private;
  2301. sde_kms = to_sde_kms(priv->kms);
  2302. connector_list = &sde_kms->dev->mode_config.connector_list;
  2303. SDE_EVT32(DRMID(drm_enc));
  2304. /*
  2305. * cache the crtc in sde_enc on enable for duration of use case
  2306. * for correctly servicing asynchronous irq events and timers
  2307. */
  2308. if (!drm_enc->crtc) {
  2309. SDE_ERROR("invalid crtc\n");
  2310. return;
  2311. }
  2312. sde_enc->crtc = drm_enc->crtc;
  2313. list_for_each_entry(conn_iter, connector_list, head)
  2314. if (conn_iter->encoder == drm_enc)
  2315. conn = conn_iter;
  2316. if (!conn) {
  2317. SDE_ERROR_ENC(sde_enc, "failed to find attached connector\n");
  2318. return;
  2319. } else if (!conn->state) {
  2320. SDE_ERROR_ENC(sde_enc, "invalid connector state\n");
  2321. return;
  2322. }
  2323. sde_conn = to_sde_connector(conn);
  2324. sde_conn_state = to_sde_connector_state(conn->state);
  2325. if (sde_conn && sde_conn_state) {
  2326. ret = sde_conn->ops.get_mode_info(&sde_conn->base, adj_mode,
  2327. &sde_conn_state->mode_info,
  2328. sde_kms->catalog->max_mixer_width,
  2329. sde_conn->display);
  2330. if (ret) {
  2331. SDE_ERROR_ENC(sde_enc,
  2332. "failed to get mode info from the display\n");
  2333. return;
  2334. }
  2335. }
  2336. intf_mode = sde_encoder_get_intf_mode(drm_enc);
  2337. /* Switch pysical encoder */
  2338. if (msm_is_mode_seamless_poms(adj_mode))
  2339. sde_encoder_virt_mode_switch(intf_mode, sde_enc, adj_mode);
  2340. /* release resources before seamless mode change */
  2341. if (msm_is_mode_seamless_dms(adj_mode)) {
  2342. /* restore resource state before releasing them */
  2343. ret = sde_encoder_resource_control(drm_enc,
  2344. SDE_ENC_RC_EVENT_PRE_MODESET);
  2345. if (ret) {
  2346. SDE_ERROR_ENC(sde_enc,
  2347. "sde resource control failed: %d\n",
  2348. ret);
  2349. return;
  2350. }
  2351. /*
  2352. * Disable dsc before switch the mode and after pre_modeset,
  2353. * to guarantee that previous kickoff finished.
  2354. */
  2355. _sde_encoder_dsc_disable(sde_enc);
  2356. }
  2357. /* Reserve dynamic resources now. Indicating non-AtomicTest phase */
  2358. ret = sde_rm_reserve(&sde_kms->rm, drm_enc, drm_enc->crtc->state,
  2359. conn->state, false);
  2360. if (ret) {
  2361. SDE_ERROR_ENC(sde_enc,
  2362. "failed to reserve hw resources, %d\n", ret);
  2363. return;
  2364. }
  2365. sde_rm_init_hw_iter(&pp_iter, drm_enc->base.id, SDE_HW_BLK_PINGPONG);
  2366. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  2367. sde_enc->hw_pp[i] = NULL;
  2368. if (!sde_rm_get_hw(&sde_kms->rm, &pp_iter))
  2369. break;
  2370. sde_enc->hw_pp[i] = (struct sde_hw_pingpong *) pp_iter.hw;
  2371. }
  2372. sde_rm_init_hw_iter(&dsc_iter, drm_enc->base.id, SDE_HW_BLK_DSC);
  2373. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  2374. sde_enc->hw_dsc[i] = NULL;
  2375. if (!sde_rm_get_hw(&sde_kms->rm, &dsc_iter))
  2376. break;
  2377. sde_enc->hw_dsc[i] = (struct sde_hw_dsc *) dsc_iter.hw;
  2378. }
  2379. /* Get PP for DSC configuration */
  2380. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  2381. sde_enc->hw_dsc_pp[i] = NULL;
  2382. if (!sde_enc->hw_dsc[i])
  2383. continue;
  2384. request_hw.id = sde_enc->hw_dsc[i]->base.id;
  2385. request_hw.type = SDE_HW_BLK_PINGPONG;
  2386. if (!sde_rm_request_hw_blk(&sde_kms->rm, &request_hw))
  2387. break;
  2388. sde_enc->hw_dsc_pp[i] =
  2389. (struct sde_hw_pingpong *) request_hw.hw;
  2390. }
  2391. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2392. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2393. if (phys) {
  2394. if (!sde_enc->hw_pp[i] && sde_enc->topology.num_intf) {
  2395. SDE_ERROR_ENC(sde_enc,
  2396. "invalid pingpong block for the encoder\n");
  2397. return;
  2398. }
  2399. phys->hw_pp = sde_enc->hw_pp[i];
  2400. phys->connector = conn->state->connector;
  2401. if (phys->ops.mode_set)
  2402. phys->ops.mode_set(phys, mode, adj_mode);
  2403. }
  2404. }
  2405. /* update resources after seamless mode change */
  2406. if (msm_is_mode_seamless_dms(adj_mode))
  2407. sde_encoder_resource_control(&sde_enc->base,
  2408. SDE_ENC_RC_EVENT_POST_MODESET);
  2409. }
  2410. void sde_encoder_control_te(struct drm_encoder *drm_enc, bool enable)
  2411. {
  2412. struct sde_encoder_virt *sde_enc;
  2413. struct sde_encoder_phys *phys;
  2414. int i;
  2415. if (!drm_enc) {
  2416. SDE_ERROR("invalid parameters\n");
  2417. return;
  2418. }
  2419. sde_enc = to_sde_encoder_virt(drm_enc);
  2420. if (!sde_enc) {
  2421. SDE_ERROR("invalid sde encoder\n");
  2422. return;
  2423. }
  2424. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2425. phys = sde_enc->phys_encs[i];
  2426. if (phys && phys->ops.control_te)
  2427. phys->ops.control_te(phys, enable);
  2428. }
  2429. }
  2430. static int _sde_encoder_input_connect(struct input_handler *handler,
  2431. struct input_dev *dev, const struct input_device_id *id)
  2432. {
  2433. struct input_handle *handle;
  2434. int rc = 0;
  2435. handle = kzalloc(sizeof(*handle), GFP_KERNEL);
  2436. if (!handle)
  2437. return -ENOMEM;
  2438. handle->dev = dev;
  2439. handle->handler = handler;
  2440. handle->name = handler->name;
  2441. rc = input_register_handle(handle);
  2442. if (rc) {
  2443. pr_err("failed to register input handle\n");
  2444. goto error;
  2445. }
  2446. rc = input_open_device(handle);
  2447. if (rc) {
  2448. pr_err("failed to open input device\n");
  2449. goto error_unregister;
  2450. }
  2451. return 0;
  2452. error_unregister:
  2453. input_unregister_handle(handle);
  2454. error:
  2455. kfree(handle);
  2456. return rc;
  2457. }
  2458. static void _sde_encoder_input_disconnect(struct input_handle *handle)
  2459. {
  2460. input_close_device(handle);
  2461. input_unregister_handle(handle);
  2462. kfree(handle);
  2463. }
  2464. /**
  2465. * Structure for specifying event parameters on which to receive callbacks.
  2466. * This structure will trigger a callback in case of a touch event (specified by
  2467. * EV_ABS) where there is a change in X and Y coordinates,
  2468. */
  2469. static const struct input_device_id sde_input_ids[] = {
  2470. {
  2471. .flags = INPUT_DEVICE_ID_MATCH_EVBIT,
  2472. .evbit = { BIT_MASK(EV_ABS) },
  2473. .absbit = { [BIT_WORD(ABS_MT_POSITION_X)] =
  2474. BIT_MASK(ABS_MT_POSITION_X) |
  2475. BIT_MASK(ABS_MT_POSITION_Y) },
  2476. },
  2477. { },
  2478. };
  2479. static int _sde_encoder_input_handler_register(
  2480. struct input_handler *input_handler)
  2481. {
  2482. int rc = 0;
  2483. rc = input_register_handler(input_handler);
  2484. if (rc) {
  2485. pr_err("input_register_handler failed, rc= %d\n", rc);
  2486. kfree(input_handler);
  2487. return rc;
  2488. }
  2489. return rc;
  2490. }
  2491. static int _sde_encoder_input_handler(
  2492. struct sde_encoder_virt *sde_enc)
  2493. {
  2494. struct input_handler *input_handler = NULL;
  2495. int rc = 0;
  2496. if (sde_enc->input_handler) {
  2497. SDE_ERROR_ENC(sde_enc,
  2498. "input_handle is active. unexpected\n");
  2499. return -EINVAL;
  2500. }
  2501. input_handler = kzalloc(sizeof(*sde_enc->input_handler), GFP_KERNEL);
  2502. if (!input_handler)
  2503. return -ENOMEM;
  2504. input_handler->event = sde_encoder_input_event_handler;
  2505. input_handler->connect = _sde_encoder_input_connect;
  2506. input_handler->disconnect = _sde_encoder_input_disconnect;
  2507. input_handler->name = "sde";
  2508. input_handler->id_table = sde_input_ids;
  2509. input_handler->private = sde_enc;
  2510. sde_enc->input_handler = input_handler;
  2511. return rc;
  2512. }
  2513. static void _sde_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
  2514. {
  2515. struct sde_encoder_virt *sde_enc = NULL;
  2516. struct msm_drm_private *priv;
  2517. struct sde_kms *sde_kms;
  2518. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  2519. SDE_ERROR("invalid parameters\n");
  2520. return;
  2521. }
  2522. priv = drm_enc->dev->dev_private;
  2523. sde_kms = to_sde_kms(priv->kms);
  2524. if (!sde_kms) {
  2525. SDE_ERROR("invalid sde_kms\n");
  2526. return;
  2527. }
  2528. sde_enc = to_sde_encoder_virt(drm_enc);
  2529. if (!sde_enc || !sde_enc->cur_master) {
  2530. SDE_DEBUG("invalid sde encoder/master\n");
  2531. return;
  2532. }
  2533. if (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DisplayPort &&
  2534. sde_enc->cur_master->hw_mdptop &&
  2535. sde_enc->cur_master->hw_mdptop->ops.intf_audio_select)
  2536. sde_enc->cur_master->hw_mdptop->ops.intf_audio_select(
  2537. sde_enc->cur_master->hw_mdptop);
  2538. if (sde_enc->cur_master->hw_mdptop &&
  2539. sde_enc->cur_master->hw_mdptop->ops.reset_ubwc)
  2540. sde_enc->cur_master->hw_mdptop->ops.reset_ubwc(
  2541. sde_enc->cur_master->hw_mdptop,
  2542. sde_kms->catalog);
  2543. if (sde_enc->cur_master->hw_ctl &&
  2544. sde_enc->cur_master->hw_ctl->ops.setup_intf_cfg_v1 &&
  2545. !sde_enc->cur_master->cont_splash_enabled)
  2546. sde_enc->cur_master->hw_ctl->ops.setup_intf_cfg_v1(
  2547. sde_enc->cur_master->hw_ctl,
  2548. &sde_enc->cur_master->intf_cfg_v1);
  2549. _sde_encoder_update_vsync_source(sde_enc, &sde_enc->disp_info, false);
  2550. sde_encoder_control_te(drm_enc, true);
  2551. memset(&sde_enc->prv_conn_roi, 0, sizeof(sde_enc->prv_conn_roi));
  2552. memset(&sde_enc->cur_conn_roi, 0, sizeof(sde_enc->cur_conn_roi));
  2553. }
  2554. void sde_encoder_virt_restore(struct drm_encoder *drm_enc)
  2555. {
  2556. struct sde_encoder_virt *sde_enc = NULL;
  2557. int i;
  2558. if (!drm_enc) {
  2559. SDE_ERROR("invalid encoder\n");
  2560. return;
  2561. }
  2562. sde_enc = to_sde_encoder_virt(drm_enc);
  2563. if (sde_enc->cur_master)
  2564. memset(&sde_enc->cur_master->intf_cfg_v1, 0,
  2565. sizeof(sde_enc->cur_master->intf_cfg_v1));
  2566. sde_enc->idle_pc_restore = true;
  2567. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2568. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2569. if (!phys)
  2570. continue;
  2571. if (phys->hw_ctl && phys->hw_ctl->ops.clear_pending_flush)
  2572. phys->hw_ctl->ops.clear_pending_flush(phys->hw_ctl);
  2573. if ((phys != sde_enc->cur_master) && phys->ops.restore)
  2574. phys->ops.restore(phys);
  2575. }
  2576. if (sde_enc->cur_master && sde_enc->cur_master->ops.restore)
  2577. sde_enc->cur_master->ops.restore(sde_enc->cur_master);
  2578. _sde_encoder_virt_enable_helper(drm_enc);
  2579. }
  2580. static void sde_encoder_off_work(struct kthread_work *work)
  2581. {
  2582. struct sde_encoder_virt *sde_enc = container_of(work,
  2583. struct sde_encoder_virt, delayed_off_work.work);
  2584. struct drm_encoder *drm_enc;
  2585. if (!sde_enc) {
  2586. SDE_ERROR("invalid sde encoder\n");
  2587. return;
  2588. }
  2589. drm_enc = &sde_enc->base;
  2590. SDE_ATRACE_BEGIN("sde_encoder_off_work");
  2591. sde_encoder_idle_request(drm_enc);
  2592. SDE_ATRACE_END("sde_encoder_off_work");
  2593. }
  2594. static void sde_encoder_virt_enable(struct drm_encoder *drm_enc)
  2595. {
  2596. struct sde_encoder_virt *sde_enc = NULL;
  2597. int i, ret = 0;
  2598. struct msm_compression_info *comp_info = NULL;
  2599. struct drm_display_mode *cur_mode = NULL;
  2600. struct msm_display_info *disp_info;
  2601. if (!drm_enc) {
  2602. SDE_ERROR("invalid encoder\n");
  2603. return;
  2604. }
  2605. sde_enc = to_sde_encoder_virt(drm_enc);
  2606. disp_info = &sde_enc->disp_info;
  2607. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  2608. SDE_ERROR("power resource is not enabled\n");
  2609. return;
  2610. }
  2611. if (drm_enc->crtc && !sde_enc->crtc)
  2612. sde_enc->crtc = drm_enc->crtc;
  2613. comp_info = &sde_enc->mode_info.comp_info;
  2614. cur_mode = &sde_enc->base.crtc->state->adjusted_mode;
  2615. SDE_DEBUG_ENC(sde_enc, "\n");
  2616. SDE_EVT32(DRMID(drm_enc), cur_mode->hdisplay, cur_mode->vdisplay);
  2617. sde_enc->cur_master = NULL;
  2618. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2619. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2620. if (phys && phys->ops.is_master && phys->ops.is_master(phys)) {
  2621. SDE_DEBUG_ENC(sde_enc, "master is now idx %d\n", i);
  2622. sde_enc->cur_master = phys;
  2623. break;
  2624. }
  2625. }
  2626. if (!sde_enc->cur_master) {
  2627. SDE_ERROR("virt encoder has no master! num_phys %d\n", i);
  2628. return;
  2629. }
  2630. /* register input handler if not already registered */
  2631. if (sde_enc->input_handler && !msm_is_mode_seamless_dms(cur_mode)) {
  2632. ret = _sde_encoder_input_handler_register(
  2633. sde_enc->input_handler);
  2634. if (ret)
  2635. SDE_ERROR(
  2636. "input handler registration failed, rc = %d\n", ret);
  2637. }
  2638. if (!(msm_is_mode_seamless_vrr(cur_mode)
  2639. || msm_is_mode_seamless_dms(cur_mode)))
  2640. kthread_init_delayed_work(&sde_enc->delayed_off_work,
  2641. sde_encoder_off_work);
  2642. ret = sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_KICKOFF);
  2643. if (ret) {
  2644. SDE_ERROR_ENC(sde_enc, "sde resource control failed: %d\n",
  2645. ret);
  2646. return;
  2647. }
  2648. memset(&sde_enc->cur_master->intf_cfg_v1, 0,
  2649. sizeof(sde_enc->cur_master->intf_cfg_v1));
  2650. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2651. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2652. if (!phys)
  2653. continue;
  2654. phys->comp_type = comp_info->comp_type;
  2655. phys->comp_ratio = comp_info->comp_ratio;
  2656. phys->wide_bus_en = sde_enc->mode_info.wide_bus_en;
  2657. phys->frame_trigger_mode = sde_enc->frame_trigger_mode;
  2658. if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC) {
  2659. phys->dsc_extra_pclk_cycle_cnt =
  2660. comp_info->dsc_info.pclk_per_line;
  2661. phys->dsc_extra_disp_width =
  2662. comp_info->dsc_info.extra_width;
  2663. }
  2664. if (phys != sde_enc->cur_master) {
  2665. /**
  2666. * on DMS request, the encoder will be enabled
  2667. * already. Invoke restore to reconfigure the
  2668. * new mode.
  2669. */
  2670. if (msm_is_mode_seamless_dms(cur_mode) &&
  2671. phys->ops.restore)
  2672. phys->ops.restore(phys);
  2673. else if (phys->ops.enable)
  2674. phys->ops.enable(phys);
  2675. }
  2676. if (sde_enc->misr_enable && phys->ops.setup_misr &&
  2677. (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE)))
  2678. phys->ops.setup_misr(phys, true,
  2679. sde_enc->misr_frame_count);
  2680. }
  2681. if (msm_is_mode_seamless_dms(cur_mode) &&
  2682. sde_enc->cur_master->ops.restore)
  2683. sde_enc->cur_master->ops.restore(sde_enc->cur_master);
  2684. else if (sde_enc->cur_master->ops.enable)
  2685. sde_enc->cur_master->ops.enable(sde_enc->cur_master);
  2686. _sde_encoder_virt_enable_helper(drm_enc);
  2687. }
  2688. static void sde_encoder_virt_disable(struct drm_encoder *drm_enc)
  2689. {
  2690. struct sde_encoder_virt *sde_enc = NULL;
  2691. struct msm_drm_private *priv;
  2692. struct sde_kms *sde_kms;
  2693. enum sde_intf_mode intf_mode;
  2694. int i = 0;
  2695. if (!drm_enc) {
  2696. SDE_ERROR("invalid encoder\n");
  2697. return;
  2698. } else if (!drm_enc->dev) {
  2699. SDE_ERROR("invalid dev\n");
  2700. return;
  2701. } else if (!drm_enc->dev->dev_private) {
  2702. SDE_ERROR("invalid dev_private\n");
  2703. return;
  2704. }
  2705. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  2706. SDE_ERROR("power resource is not enabled\n");
  2707. return;
  2708. }
  2709. sde_enc = to_sde_encoder_virt(drm_enc);
  2710. SDE_DEBUG_ENC(sde_enc, "\n");
  2711. priv = drm_enc->dev->dev_private;
  2712. sde_kms = to_sde_kms(priv->kms);
  2713. intf_mode = sde_encoder_get_intf_mode(drm_enc);
  2714. SDE_EVT32(DRMID(drm_enc));
  2715. /* wait for idle */
  2716. sde_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
  2717. if (sde_enc->input_handler)
  2718. input_unregister_handler(sde_enc->input_handler);
  2719. /*
  2720. * For primary command mode and video mode encoders, execute the
  2721. * resource control pre-stop operations before the physical encoders
  2722. * are disabled, to allow the rsc to transition its states properly.
  2723. *
  2724. * For other encoder types, rsc should not be enabled until after
  2725. * they have been fully disabled, so delay the pre-stop operations
  2726. * until after the physical disable calls have returned.
  2727. */
  2728. if (sde_enc->disp_info.display_type == SDE_CONNECTOR_PRIMARY &&
  2729. (intf_mode == INTF_MODE_CMD || intf_mode == INTF_MODE_VIDEO)) {
  2730. sde_encoder_resource_control(drm_enc,
  2731. SDE_ENC_RC_EVENT_PRE_STOP);
  2732. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2733. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2734. if (phys && phys->ops.disable)
  2735. phys->ops.disable(phys);
  2736. }
  2737. } else {
  2738. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2739. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2740. if (phys && phys->ops.disable)
  2741. phys->ops.disable(phys);
  2742. }
  2743. sde_encoder_resource_control(drm_enc,
  2744. SDE_ENC_RC_EVENT_PRE_STOP);
  2745. }
  2746. /*
  2747. * disable dsc after the transfer is complete (for command mode)
  2748. * and after physical encoder is disabled, to make sure timing
  2749. * engine is already disabled (for video mode).
  2750. */
  2751. _sde_encoder_dsc_disable(sde_enc);
  2752. sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_STOP);
  2753. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2754. if (sde_enc->phys_encs[i]) {
  2755. sde_enc->phys_encs[i]->cont_splash_enabled = false;
  2756. sde_enc->phys_encs[i]->cont_splash_single_flush = 0;
  2757. sde_enc->phys_encs[i]->connector = NULL;
  2758. }
  2759. }
  2760. sde_enc->cur_master = NULL;
  2761. /*
  2762. * clear the cached crtc in sde_enc on use case finish, after all the
  2763. * outstanding events and timers have been completed
  2764. */
  2765. sde_enc->crtc = NULL;
  2766. memset(&sde_enc->mode_info, 0, sizeof(sde_enc->mode_info));
  2767. SDE_DEBUG_ENC(sde_enc, "encoder disabled\n");
  2768. sde_rm_release(&sde_kms->rm, drm_enc, false);
  2769. }
  2770. void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,
  2771. struct sde_encoder_phys_wb *wb_enc)
  2772. {
  2773. struct sde_encoder_virt *sde_enc;
  2774. if (wb_enc) {
  2775. if (sde_encoder_helper_reset_mixers(phys_enc, NULL))
  2776. return;
  2777. if (wb_enc->hw_wb->ops.bind_pingpong_blk) {
  2778. wb_enc->hw_wb->ops.bind_pingpong_blk(wb_enc->hw_wb,
  2779. false, phys_enc->hw_pp->idx);
  2780. if (phys_enc->hw_ctl->ops.update_bitmask_wb)
  2781. phys_enc->hw_ctl->ops.update_bitmask_wb(
  2782. phys_enc->hw_ctl,
  2783. wb_enc->hw_wb->idx, true);
  2784. }
  2785. } else {
  2786. if (phys_enc->hw_intf->ops.bind_pingpong_blk) {
  2787. phys_enc->hw_intf->ops.bind_pingpong_blk(
  2788. phys_enc->hw_intf, false,
  2789. phys_enc->hw_pp->idx);
  2790. if (phys_enc->hw_ctl->ops.update_bitmask_intf)
  2791. phys_enc->hw_ctl->ops.update_bitmask_intf(
  2792. phys_enc->hw_ctl,
  2793. phys_enc->hw_intf->idx, true);
  2794. }
  2795. }
  2796. if (phys_enc->hw_pp && phys_enc->hw_pp->ops.reset_3d_mode) {
  2797. phys_enc->hw_pp->ops.reset_3d_mode(phys_enc->hw_pp);
  2798. if (phys_enc->hw_ctl->ops.update_bitmask_merge3d &&
  2799. phys_enc->hw_pp->merge_3d)
  2800. phys_enc->hw_ctl->ops.update_bitmask_merge3d(
  2801. phys_enc->hw_ctl,
  2802. phys_enc->hw_pp->merge_3d->idx, true);
  2803. }
  2804. if (phys_enc->hw_cdm && phys_enc->hw_cdm->ops.bind_pingpong_blk &&
  2805. phys_enc->hw_pp) {
  2806. phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm,
  2807. false, phys_enc->hw_pp->idx);
  2808. if (phys_enc->hw_ctl->ops.update_bitmask_cdm)
  2809. phys_enc->hw_ctl->ops.update_bitmask_cdm(
  2810. phys_enc->hw_ctl,
  2811. phys_enc->hw_cdm->idx, true);
  2812. }
  2813. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  2814. if (phys_enc == sde_enc->cur_master && phys_enc->hw_pp &&
  2815. phys_enc->hw_ctl->ops.reset_post_disable)
  2816. phys_enc->hw_ctl->ops.reset_post_disable(
  2817. phys_enc->hw_ctl, &phys_enc->intf_cfg_v1,
  2818. phys_enc->hw_pp->merge_3d ?
  2819. phys_enc->hw_pp->merge_3d->idx : 0);
  2820. phys_enc->hw_ctl->ops.trigger_flush(phys_enc->hw_ctl);
  2821. phys_enc->hw_ctl->ops.trigger_start(phys_enc->hw_ctl);
  2822. }
  2823. static enum sde_intf sde_encoder_get_intf(struct sde_mdss_cfg *catalog,
  2824. enum sde_intf_type type, u32 controller_id)
  2825. {
  2826. int i = 0;
  2827. for (i = 0; i < catalog->intf_count; i++) {
  2828. if (catalog->intf[i].type == type
  2829. && catalog->intf[i].controller_id == controller_id) {
  2830. return catalog->intf[i].id;
  2831. }
  2832. }
  2833. return INTF_MAX;
  2834. }
  2835. static enum sde_wb sde_encoder_get_wb(struct sde_mdss_cfg *catalog,
  2836. enum sde_intf_type type, u32 controller_id)
  2837. {
  2838. if (controller_id < catalog->wb_count)
  2839. return catalog->wb[controller_id].id;
  2840. return WB_MAX;
  2841. }
  2842. void sde_encoder_perf_uidle_status(struct sde_kms *sde_kms,
  2843. struct drm_crtc *crtc)
  2844. {
  2845. struct sde_hw_uidle *uidle;
  2846. struct sde_uidle_cntr cntr;
  2847. struct sde_uidle_status status;
  2848. if (!sde_kms || !crtc || !sde_kms->hw_uidle) {
  2849. pr_err("invalid params %d %d\n",
  2850. !sde_kms, !crtc);
  2851. return;
  2852. }
  2853. /* check if perf counters are enabled and setup */
  2854. if (!sde_kms->catalog->uidle_cfg.perf_cntr_en)
  2855. return;
  2856. uidle = sde_kms->hw_uidle;
  2857. if ((sde_kms->catalog->uidle_cfg.debugfs_perf & SDE_PERF_UIDLE_STATUS)
  2858. && uidle->ops.uidle_get_status) {
  2859. uidle->ops.uidle_get_status(uidle, &status);
  2860. trace_sde_perf_uidle_status(
  2861. crtc->base.id,
  2862. status.uidle_danger_status_0,
  2863. status.uidle_danger_status_1,
  2864. status.uidle_safe_status_0,
  2865. status.uidle_safe_status_1,
  2866. status.uidle_idle_status_0,
  2867. status.uidle_idle_status_1,
  2868. status.uidle_fal_status_0,
  2869. status.uidle_fal_status_1);
  2870. }
  2871. if ((sde_kms->catalog->uidle_cfg.debugfs_perf & SDE_PERF_UIDLE_CNT)
  2872. && uidle->ops.uidle_get_cntr) {
  2873. uidle->ops.uidle_get_cntr(uidle, &cntr);
  2874. trace_sde_perf_uidle_cntr(
  2875. crtc->base.id,
  2876. cntr.fal1_gate_cntr,
  2877. cntr.fal10_gate_cntr,
  2878. cntr.fal_wait_gate_cntr,
  2879. cntr.fal1_num_transitions_cntr,
  2880. cntr.fal10_num_transitions_cntr,
  2881. cntr.min_gate_cntr,
  2882. cntr.max_gate_cntr);
  2883. }
  2884. }
  2885. static void sde_encoder_vblank_callback(struct drm_encoder *drm_enc,
  2886. struct sde_encoder_phys *phy_enc)
  2887. {
  2888. struct sde_encoder_virt *sde_enc = NULL;
  2889. unsigned long lock_flags;
  2890. if (!drm_enc || !phy_enc)
  2891. return;
  2892. SDE_ATRACE_BEGIN("encoder_vblank_callback");
  2893. sde_enc = to_sde_encoder_virt(drm_enc);
  2894. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2895. if (sde_enc->crtc_vblank_cb)
  2896. sde_enc->crtc_vblank_cb(sde_enc->crtc_vblank_cb_data);
  2897. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2898. if (phy_enc->sde_kms &&
  2899. phy_enc->sde_kms->catalog->uidle_cfg.debugfs_perf)
  2900. sde_encoder_perf_uidle_status(phy_enc->sde_kms, sde_enc->crtc);
  2901. atomic_inc(&phy_enc->vsync_cnt);
  2902. SDE_ATRACE_END("encoder_vblank_callback");
  2903. }
  2904. static void sde_encoder_underrun_callback(struct drm_encoder *drm_enc,
  2905. struct sde_encoder_phys *phy_enc)
  2906. {
  2907. if (!phy_enc)
  2908. return;
  2909. SDE_ATRACE_BEGIN("encoder_underrun_callback");
  2910. atomic_inc(&phy_enc->underrun_cnt);
  2911. SDE_EVT32(DRMID(drm_enc), atomic_read(&phy_enc->underrun_cnt));
  2912. trace_sde_encoder_underrun(DRMID(drm_enc),
  2913. atomic_read(&phy_enc->underrun_cnt));
  2914. SDE_DBG_CTRL("stop_ftrace");
  2915. SDE_DBG_CTRL("panic_underrun");
  2916. SDE_ATRACE_END("encoder_underrun_callback");
  2917. }
  2918. void sde_encoder_register_vblank_callback(struct drm_encoder *drm_enc,
  2919. void (*vbl_cb)(void *), void *vbl_data)
  2920. {
  2921. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2922. unsigned long lock_flags;
  2923. bool enable;
  2924. int i;
  2925. enable = vbl_cb ? true : false;
  2926. if (!drm_enc) {
  2927. SDE_ERROR("invalid encoder\n");
  2928. return;
  2929. }
  2930. SDE_DEBUG_ENC(sde_enc, "\n");
  2931. SDE_EVT32(DRMID(drm_enc), enable);
  2932. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2933. sde_enc->crtc_vblank_cb = vbl_cb;
  2934. sde_enc->crtc_vblank_cb_data = vbl_data;
  2935. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2936. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2937. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2938. if (phys && phys->ops.control_vblank_irq)
  2939. phys->ops.control_vblank_irq(phys, enable);
  2940. }
  2941. sde_enc->vblank_enabled = enable;
  2942. }
  2943. void sde_encoder_register_frame_event_callback(struct drm_encoder *drm_enc,
  2944. void (*frame_event_cb)(void *, u32 event),
  2945. struct drm_crtc *crtc)
  2946. {
  2947. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2948. unsigned long lock_flags;
  2949. bool enable;
  2950. enable = frame_event_cb ? true : false;
  2951. if (!drm_enc) {
  2952. SDE_ERROR("invalid encoder\n");
  2953. return;
  2954. }
  2955. SDE_DEBUG_ENC(sde_enc, "\n");
  2956. SDE_EVT32(DRMID(drm_enc), enable, 0);
  2957. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2958. sde_enc->crtc_frame_event_cb = frame_event_cb;
  2959. sde_enc->crtc_frame_event_cb_data.crtc = crtc;
  2960. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2961. }
  2962. static void sde_encoder_frame_done_callback(
  2963. struct drm_encoder *drm_enc,
  2964. struct sde_encoder_phys *ready_phys, u32 event)
  2965. {
  2966. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2967. unsigned int i;
  2968. bool trigger = true;
  2969. bool is_cmd_mode = false;
  2970. enum sde_rm_topology_name topology = SDE_RM_TOPOLOGY_NONE;
  2971. if (!drm_enc || !sde_enc->cur_master) {
  2972. SDE_ERROR("invalid param: drm_enc %pK, cur_master %pK\n",
  2973. drm_enc, drm_enc ? sde_enc->cur_master : 0);
  2974. return;
  2975. }
  2976. sde_enc->crtc_frame_event_cb_data.connector =
  2977. sde_enc->cur_master->connector;
  2978. if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  2979. is_cmd_mode = true;
  2980. if (event & (SDE_ENCODER_FRAME_EVENT_DONE
  2981. | SDE_ENCODER_FRAME_EVENT_ERROR
  2982. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD) && is_cmd_mode) {
  2983. if (ready_phys->connector)
  2984. topology = sde_connector_get_topology_name(
  2985. ready_phys->connector);
  2986. /* One of the physical encoders has become idle */
  2987. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2988. if ((sde_enc->phys_encs[i] == ready_phys) ||
  2989. (event & SDE_ENCODER_FRAME_EVENT_ERROR)) {
  2990. SDE_EVT32_VERBOSE(DRMID(drm_enc), i,
  2991. atomic_read(&sde_enc->frame_done_cnt[i]));
  2992. if (!atomic_add_unless(
  2993. &sde_enc->frame_done_cnt[i], 1, 1)) {
  2994. SDE_EVT32(DRMID(drm_enc), event,
  2995. ready_phys->intf_idx,
  2996. SDE_EVTLOG_ERROR);
  2997. SDE_ERROR_ENC(sde_enc,
  2998. "intf idx:%d, event:%d\n",
  2999. ready_phys->intf_idx, event);
  3000. return;
  3001. }
  3002. }
  3003. if (topology != SDE_RM_TOPOLOGY_PPSPLIT &&
  3004. atomic_read(&sde_enc->frame_done_cnt[i]) != 1)
  3005. trigger = false;
  3006. }
  3007. if (trigger) {
  3008. sde_encoder_resource_control(drm_enc,
  3009. SDE_ENC_RC_EVENT_FRAME_DONE);
  3010. if (sde_enc->crtc_frame_event_cb)
  3011. sde_enc->crtc_frame_event_cb(
  3012. &sde_enc->crtc_frame_event_cb_data,
  3013. event);
  3014. for (i = 0; i < sde_enc->num_phys_encs; i++)
  3015. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  3016. }
  3017. } else if (sde_enc->crtc_frame_event_cb) {
  3018. if (!is_cmd_mode)
  3019. sde_encoder_resource_control(drm_enc,
  3020. SDE_ENC_RC_EVENT_FRAME_DONE);
  3021. sde_enc->crtc_frame_event_cb(
  3022. &sde_enc->crtc_frame_event_cb_data, event);
  3023. }
  3024. }
  3025. static void sde_encoder_get_qsync_fps_callback(
  3026. struct drm_encoder *drm_enc,
  3027. u32 *qsync_fps)
  3028. {
  3029. struct msm_display_info *disp_info;
  3030. struct sde_encoder_virt *sde_enc;
  3031. if (!qsync_fps)
  3032. return;
  3033. *qsync_fps = 0;
  3034. if (!drm_enc) {
  3035. SDE_ERROR("invalid drm encoder\n");
  3036. return;
  3037. }
  3038. sde_enc = to_sde_encoder_virt(drm_enc);
  3039. disp_info = &sde_enc->disp_info;
  3040. *qsync_fps = disp_info->qsync_min_fps;
  3041. }
  3042. int sde_encoder_idle_request(struct drm_encoder *drm_enc)
  3043. {
  3044. struct sde_encoder_virt *sde_enc;
  3045. if (!drm_enc) {
  3046. SDE_ERROR("invalid drm encoder\n");
  3047. return -EINVAL;
  3048. }
  3049. sde_enc = to_sde_encoder_virt(drm_enc);
  3050. sde_encoder_resource_control(&sde_enc->base,
  3051. SDE_ENC_RC_EVENT_ENTER_IDLE);
  3052. return 0;
  3053. }
  3054. /**
  3055. * _sde_encoder_trigger_flush - trigger flush for a physical encoder
  3056. * drm_enc: Pointer to drm encoder structure
  3057. * phys: Pointer to physical encoder structure
  3058. * extra_flush: Additional bit mask to include in flush trigger
  3059. */
  3060. static inline void _sde_encoder_trigger_flush(struct drm_encoder *drm_enc,
  3061. struct sde_encoder_phys *phys,
  3062. struct sde_ctl_flush_cfg *extra_flush)
  3063. {
  3064. struct sde_hw_ctl *ctl;
  3065. unsigned long lock_flags;
  3066. struct sde_encoder_virt *sde_enc;
  3067. int pend_ret_fence_cnt;
  3068. struct sde_connector *c_conn;
  3069. if (!drm_enc || !phys) {
  3070. SDE_ERROR("invalid argument(s), drm_enc %d, phys_enc %d\n",
  3071. !drm_enc, !phys);
  3072. return;
  3073. }
  3074. sde_enc = to_sde_encoder_virt(drm_enc);
  3075. c_conn = to_sde_connector(phys->connector);
  3076. if (!phys->hw_pp) {
  3077. SDE_ERROR("invalid pingpong hw\n");
  3078. return;
  3079. }
  3080. ctl = phys->hw_ctl;
  3081. if (!ctl || !phys->ops.trigger_flush) {
  3082. SDE_ERROR("missing ctl/trigger cb\n");
  3083. return;
  3084. }
  3085. if (phys->split_role == ENC_ROLE_SKIP) {
  3086. SDE_DEBUG_ENC(to_sde_encoder_virt(phys->parent),
  3087. "skip flush pp%d ctl%d\n",
  3088. phys->hw_pp->idx - PINGPONG_0,
  3089. ctl->idx - CTL_0);
  3090. return;
  3091. }
  3092. /* update pending counts and trigger kickoff ctl flush atomically */
  3093. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  3094. if (phys->ops.is_master && phys->ops.is_master(phys))
  3095. atomic_inc(&phys->pending_retire_fence_cnt);
  3096. pend_ret_fence_cnt = atomic_read(&phys->pending_retire_fence_cnt);
  3097. if (phys->hw_intf && phys->hw_intf->cap->type == INTF_DP &&
  3098. ctl->ops.update_bitmask_periph) {
  3099. /* perform peripheral flush on every frame update for dp dsc */
  3100. if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC &&
  3101. phys->comp_ratio && c_conn->ops.update_pps) {
  3102. c_conn->ops.update_pps(phys->connector, NULL,
  3103. c_conn->display);
  3104. ctl->ops.update_bitmask_periph(ctl,
  3105. phys->hw_intf->idx, 1);
  3106. }
  3107. if (sde_enc->dynamic_hdr_updated)
  3108. ctl->ops.update_bitmask_periph(ctl,
  3109. phys->hw_intf->idx, 1);
  3110. }
  3111. if ((extra_flush && extra_flush->pending_flush_mask)
  3112. && ctl->ops.update_pending_flush)
  3113. ctl->ops.update_pending_flush(ctl, extra_flush);
  3114. phys->ops.trigger_flush(phys);
  3115. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  3116. if (ctl->ops.get_pending_flush) {
  3117. struct sde_ctl_flush_cfg pending_flush = {0,};
  3118. ctl->ops.get_pending_flush(ctl, &pending_flush);
  3119. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0,
  3120. ctl->idx - CTL_0,
  3121. pending_flush.pending_flush_mask,
  3122. pend_ret_fence_cnt);
  3123. } else {
  3124. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0,
  3125. ctl->idx - CTL_0,
  3126. pend_ret_fence_cnt);
  3127. }
  3128. }
  3129. /**
  3130. * _sde_encoder_trigger_start - trigger start for a physical encoder
  3131. * phys: Pointer to physical encoder structure
  3132. */
  3133. static inline void _sde_encoder_trigger_start(struct sde_encoder_phys *phys)
  3134. {
  3135. struct sde_hw_ctl *ctl;
  3136. struct sde_encoder_virt *sde_enc;
  3137. if (!phys) {
  3138. SDE_ERROR("invalid argument(s)\n");
  3139. return;
  3140. }
  3141. if (!phys->hw_pp) {
  3142. SDE_ERROR("invalid pingpong hw\n");
  3143. return;
  3144. }
  3145. if (!phys->parent) {
  3146. SDE_ERROR("invalid parent\n");
  3147. return;
  3148. }
  3149. /* avoid ctrl start for encoder in clone mode */
  3150. if (phys->in_clone_mode)
  3151. return;
  3152. ctl = phys->hw_ctl;
  3153. sde_enc = to_sde_encoder_virt(phys->parent);
  3154. if (phys->split_role == ENC_ROLE_SKIP) {
  3155. SDE_DEBUG_ENC(sde_enc,
  3156. "skip start pp%d ctl%d\n",
  3157. phys->hw_pp->idx - PINGPONG_0,
  3158. ctl->idx - CTL_0);
  3159. return;
  3160. }
  3161. if (phys->ops.trigger_start && phys->enable_state != SDE_ENC_DISABLED)
  3162. phys->ops.trigger_start(phys);
  3163. }
  3164. void sde_encoder_helper_trigger_flush(struct sde_encoder_phys *phys_enc)
  3165. {
  3166. struct sde_hw_ctl *ctl;
  3167. if (!phys_enc) {
  3168. SDE_ERROR("invalid encoder\n");
  3169. return;
  3170. }
  3171. ctl = phys_enc->hw_ctl;
  3172. if (ctl && ctl->ops.trigger_flush)
  3173. ctl->ops.trigger_flush(ctl);
  3174. }
  3175. void sde_encoder_helper_trigger_start(struct sde_encoder_phys *phys_enc)
  3176. {
  3177. struct sde_hw_ctl *ctl;
  3178. if (!phys_enc) {
  3179. SDE_ERROR("invalid encoder\n");
  3180. return;
  3181. }
  3182. ctl = phys_enc->hw_ctl;
  3183. if (ctl && ctl->ops.trigger_start) {
  3184. ctl->ops.trigger_start(ctl);
  3185. SDE_EVT32(DRMID(phys_enc->parent), ctl->idx - CTL_0);
  3186. }
  3187. }
  3188. void sde_encoder_helper_hw_reset(struct sde_encoder_phys *phys_enc)
  3189. {
  3190. struct sde_encoder_virt *sde_enc;
  3191. struct sde_connector *sde_con;
  3192. void *sde_con_disp;
  3193. struct sde_hw_ctl *ctl;
  3194. int rc;
  3195. if (!phys_enc) {
  3196. SDE_ERROR("invalid encoder\n");
  3197. return;
  3198. }
  3199. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  3200. ctl = phys_enc->hw_ctl;
  3201. if (!ctl || !ctl->ops.reset)
  3202. return;
  3203. SDE_DEBUG_ENC(sde_enc, "ctl %d reset\n", ctl->idx);
  3204. SDE_EVT32(DRMID(phys_enc->parent), ctl->idx);
  3205. if (phys_enc->ops.is_master && phys_enc->ops.is_master(phys_enc) &&
  3206. phys_enc->connector) {
  3207. sde_con = to_sde_connector(phys_enc->connector);
  3208. sde_con_disp = sde_connector_get_display(phys_enc->connector);
  3209. if (sde_con->ops.soft_reset) {
  3210. rc = sde_con->ops.soft_reset(sde_con_disp);
  3211. if (rc) {
  3212. SDE_ERROR_ENC(sde_enc,
  3213. "connector soft reset failure\n");
  3214. SDE_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus",
  3215. "panic");
  3216. }
  3217. }
  3218. }
  3219. phys_enc->enable_state = SDE_ENC_ENABLED;
  3220. }
  3221. /**
  3222. * _sde_encoder_kickoff_phys - handle physical encoder kickoff
  3223. * Iterate through the physical encoders and perform consolidated flush
  3224. * and/or control start triggering as needed. This is done in the virtual
  3225. * encoder rather than the individual physical ones in order to handle
  3226. * use cases that require visibility into multiple physical encoders at
  3227. * a time.
  3228. * sde_enc: Pointer to virtual encoder structure
  3229. */
  3230. static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc)
  3231. {
  3232. struct sde_hw_ctl *ctl;
  3233. uint32_t i;
  3234. struct sde_ctl_flush_cfg pending_flush = {0,};
  3235. u32 pending_kickoff_cnt;
  3236. struct msm_drm_private *priv = NULL;
  3237. struct sde_kms *sde_kms = NULL;
  3238. bool is_vid_mode = false;
  3239. struct sde_crtc_misr_info crtc_misr_info = {false, 0};
  3240. if (!sde_enc) {
  3241. SDE_ERROR("invalid encoder\n");
  3242. return;
  3243. }
  3244. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_VIDEO_MODE))
  3245. is_vid_mode = true;
  3246. /* don't perform flush/start operations for slave encoders */
  3247. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3248. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3249. enum sde_rm_topology_name topology = SDE_RM_TOPOLOGY_NONE;
  3250. if (!phys || phys->enable_state == SDE_ENC_DISABLED)
  3251. continue;
  3252. ctl = phys->hw_ctl;
  3253. if (!ctl)
  3254. continue;
  3255. if (phys->connector)
  3256. topology = sde_connector_get_topology_name(
  3257. phys->connector);
  3258. if (!phys->ops.needs_single_flush ||
  3259. !phys->ops.needs_single_flush(phys)) {
  3260. if (ctl->ops.reg_dma_flush)
  3261. ctl->ops.reg_dma_flush(ctl, is_vid_mode);
  3262. _sde_encoder_trigger_flush(&sde_enc->base, phys, 0x0);
  3263. } else if (ctl->ops.get_pending_flush) {
  3264. ctl->ops.get_pending_flush(ctl, &pending_flush);
  3265. }
  3266. }
  3267. /* for split flush, combine pending flush masks and send to master */
  3268. if (pending_flush.pending_flush_mask && sde_enc->cur_master) {
  3269. ctl = sde_enc->cur_master->hw_ctl;
  3270. if (ctl->ops.reg_dma_flush)
  3271. ctl->ops.reg_dma_flush(ctl, is_vid_mode);
  3272. _sde_encoder_trigger_flush(&sde_enc->base, sde_enc->cur_master,
  3273. &pending_flush);
  3274. }
  3275. /* update pending_kickoff_cnt AFTER flush but before trigger start */
  3276. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3277. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3278. if (!phys || phys->enable_state == SDE_ENC_DISABLED)
  3279. continue;
  3280. if (!phys->ops.needs_single_flush ||
  3281. !phys->ops.needs_single_flush(phys)) {
  3282. pending_kickoff_cnt =
  3283. sde_encoder_phys_inc_pending(phys);
  3284. SDE_EVT32(pending_kickoff_cnt, SDE_EVTLOG_FUNC_CASE1);
  3285. } else {
  3286. pending_kickoff_cnt =
  3287. sde_encoder_phys_inc_pending(phys);
  3288. SDE_EVT32(pending_kickoff_cnt,
  3289. pending_flush.pending_flush_mask,
  3290. SDE_EVTLOG_FUNC_CASE2);
  3291. }
  3292. }
  3293. if (sde_enc->misr_enable)
  3294. sde_encoder_misr_configure(&sde_enc->base, true,
  3295. sde_enc->misr_frame_count);
  3296. sde_crtc_get_misr_info(sde_enc->crtc, &crtc_misr_info);
  3297. if (crtc_misr_info.misr_enable)
  3298. sde_crtc_misr_setup(sde_enc->crtc, true,
  3299. crtc_misr_info.misr_frame_count);
  3300. _sde_encoder_trigger_start(sde_enc->cur_master);
  3301. if (sde_enc->elevated_ahb_vote) {
  3302. priv = sde_enc->base.dev->dev_private;
  3303. if (priv != NULL) {
  3304. sde_kms = to_sde_kms(priv->kms);
  3305. if (sde_kms != NULL) {
  3306. sde_power_scale_reg_bus(&priv->phandle,
  3307. VOTE_INDEX_LOW,
  3308. false);
  3309. }
  3310. }
  3311. sde_enc->elevated_ahb_vote = false;
  3312. }
  3313. }
  3314. static void _sde_encoder_ppsplit_swap_intf_for_right_only_update(
  3315. struct drm_encoder *drm_enc,
  3316. unsigned long *affected_displays,
  3317. int num_active_phys)
  3318. {
  3319. struct sde_encoder_virt *sde_enc;
  3320. struct sde_encoder_phys *master;
  3321. enum sde_rm_topology_name topology;
  3322. bool is_right_only;
  3323. if (!drm_enc || !affected_displays)
  3324. return;
  3325. sde_enc = to_sde_encoder_virt(drm_enc);
  3326. master = sde_enc->cur_master;
  3327. if (!master || !master->connector)
  3328. return;
  3329. topology = sde_connector_get_topology_name(master->connector);
  3330. if (topology != SDE_RM_TOPOLOGY_PPSPLIT)
  3331. return;
  3332. /*
  3333. * For pingpong split, the slave pingpong won't generate IRQs. For
  3334. * right-only updates, we can't swap pingpongs, or simply swap the
  3335. * master/slave assignment, we actually have to swap the interfaces
  3336. * so that the master physical encoder will use a pingpong/interface
  3337. * that generates irqs on which to wait.
  3338. */
  3339. is_right_only = !test_bit(0, affected_displays) &&
  3340. test_bit(1, affected_displays);
  3341. if (is_right_only && !sde_enc->intfs_swapped) {
  3342. /* right-only update swap interfaces */
  3343. swap(sde_enc->phys_encs[0]->intf_idx,
  3344. sde_enc->phys_encs[1]->intf_idx);
  3345. sde_enc->intfs_swapped = true;
  3346. } else if (!is_right_only && sde_enc->intfs_swapped) {
  3347. /* left-only or full update, swap back */
  3348. swap(sde_enc->phys_encs[0]->intf_idx,
  3349. sde_enc->phys_encs[1]->intf_idx);
  3350. sde_enc->intfs_swapped = false;
  3351. }
  3352. SDE_DEBUG_ENC(sde_enc,
  3353. "right_only %d swapped %d phys0->intf%d, phys1->intf%d\n",
  3354. is_right_only, sde_enc->intfs_swapped,
  3355. sde_enc->phys_encs[0]->intf_idx - INTF_0,
  3356. sde_enc->phys_encs[1]->intf_idx - INTF_0);
  3357. SDE_EVT32(DRMID(drm_enc), is_right_only, sde_enc->intfs_swapped,
  3358. sde_enc->phys_encs[0]->intf_idx - INTF_0,
  3359. sde_enc->phys_encs[1]->intf_idx - INTF_0,
  3360. *affected_displays);
  3361. /* ppsplit always uses master since ppslave invalid for irqs*/
  3362. if (num_active_phys == 1)
  3363. *affected_displays = BIT(0);
  3364. }
  3365. static void _sde_encoder_update_master(struct drm_encoder *drm_enc,
  3366. struct sde_encoder_kickoff_params *params)
  3367. {
  3368. struct sde_encoder_virt *sde_enc;
  3369. struct sde_encoder_phys *phys;
  3370. int i, num_active_phys;
  3371. bool master_assigned = false;
  3372. if (!drm_enc || !params)
  3373. return;
  3374. sde_enc = to_sde_encoder_virt(drm_enc);
  3375. if (sde_enc->num_phys_encs <= 1)
  3376. return;
  3377. /* count bits set */
  3378. num_active_phys = hweight_long(params->affected_displays);
  3379. SDE_DEBUG_ENC(sde_enc, "affected_displays 0x%lx num_active_phys %d\n",
  3380. params->affected_displays, num_active_phys);
  3381. SDE_EVT32_VERBOSE(DRMID(drm_enc), params->affected_displays,
  3382. num_active_phys);
  3383. /* for left/right only update, ppsplit master switches interface */
  3384. _sde_encoder_ppsplit_swap_intf_for_right_only_update(drm_enc,
  3385. &params->affected_displays, num_active_phys);
  3386. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3387. enum sde_enc_split_role prv_role, new_role;
  3388. bool active = false;
  3389. phys = sde_enc->phys_encs[i];
  3390. if (!phys || !phys->ops.update_split_role || !phys->hw_pp)
  3391. continue;
  3392. active = test_bit(i, &params->affected_displays);
  3393. prv_role = phys->split_role;
  3394. if (active && num_active_phys == 1)
  3395. new_role = ENC_ROLE_SOLO;
  3396. else if (active && !master_assigned)
  3397. new_role = ENC_ROLE_MASTER;
  3398. else if (active)
  3399. new_role = ENC_ROLE_SLAVE;
  3400. else
  3401. new_role = ENC_ROLE_SKIP;
  3402. phys->ops.update_split_role(phys, new_role);
  3403. if (new_role == ENC_ROLE_SOLO || new_role == ENC_ROLE_MASTER) {
  3404. sde_enc->cur_master = phys;
  3405. master_assigned = true;
  3406. }
  3407. SDE_DEBUG_ENC(sde_enc, "pp %d role prv %d new %d active %d\n",
  3408. phys->hw_pp->idx - PINGPONG_0, prv_role,
  3409. phys->split_role, active);
  3410. SDE_EVT32(DRMID(drm_enc), params->affected_displays,
  3411. phys->hw_pp->idx - PINGPONG_0, prv_role,
  3412. phys->split_role, active, num_active_phys);
  3413. }
  3414. }
  3415. bool sde_encoder_check_curr_mode(struct drm_encoder *drm_enc, u32 mode)
  3416. {
  3417. struct sde_encoder_virt *sde_enc;
  3418. struct msm_display_info *disp_info;
  3419. if (!drm_enc) {
  3420. SDE_ERROR("invalid encoder\n");
  3421. return false;
  3422. }
  3423. sde_enc = to_sde_encoder_virt(drm_enc);
  3424. disp_info = &sde_enc->disp_info;
  3425. return (disp_info->curr_panel_mode == mode);
  3426. }
  3427. void sde_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
  3428. {
  3429. struct sde_encoder_virt *sde_enc;
  3430. struct sde_encoder_phys *phys;
  3431. unsigned int i;
  3432. struct sde_hw_ctl *ctl;
  3433. struct msm_display_info *disp_info;
  3434. if (!drm_enc) {
  3435. SDE_ERROR("invalid encoder\n");
  3436. return;
  3437. }
  3438. sde_enc = to_sde_encoder_virt(drm_enc);
  3439. disp_info = &sde_enc->disp_info;
  3440. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3441. phys = sde_enc->phys_encs[i];
  3442. if (phys && phys->hw_ctl) {
  3443. ctl = phys->hw_ctl;
  3444. /*
  3445. * avoid clearing the pending flush during the first
  3446. * frame update after idle power collpase as the
  3447. * restore path would have updated the pending flush
  3448. */
  3449. if (!sde_enc->idle_pc_restore &&
  3450. ctl->ops.clear_pending_flush)
  3451. ctl->ops.clear_pending_flush(ctl);
  3452. /* update only for command mode primary ctl */
  3453. if ((phys == sde_enc->cur_master) &&
  3454. (sde_encoder_check_curr_mode(drm_enc,
  3455. MSM_DISPLAY_CMD_MODE))
  3456. && ctl->ops.trigger_pending)
  3457. ctl->ops.trigger_pending(ctl);
  3458. }
  3459. }
  3460. sde_enc->idle_pc_restore = false;
  3461. }
  3462. static void _sde_encoder_setup_dither(struct sde_encoder_phys *phys)
  3463. {
  3464. void *dither_cfg;
  3465. int ret = 0, i = 0;
  3466. size_t len = 0;
  3467. enum sde_rm_topology_name topology;
  3468. struct drm_encoder *drm_enc;
  3469. struct msm_display_dsc_info *dsc = NULL;
  3470. struct sde_encoder_virt *sde_enc;
  3471. struct sde_hw_pingpong *hw_pp;
  3472. if (!phys || !phys->connector || !phys->hw_pp ||
  3473. !phys->hw_pp->ops.setup_dither || !phys->parent)
  3474. return;
  3475. topology = sde_connector_get_topology_name(phys->connector);
  3476. if ((topology == SDE_RM_TOPOLOGY_PPSPLIT) &&
  3477. (phys->split_role == ENC_ROLE_SLAVE))
  3478. return;
  3479. drm_enc = phys->parent;
  3480. sde_enc = to_sde_encoder_virt(drm_enc);
  3481. dsc = &sde_enc->mode_info.comp_info.dsc_info;
  3482. /* disable dither for 10 bpp or 10bpc dsc config */
  3483. if (dsc->bpp == 10 || dsc->bpc == 10) {
  3484. phys->hw_pp->ops.setup_dither(phys->hw_pp, NULL, 0);
  3485. return;
  3486. }
  3487. ret = sde_connector_get_dither_cfg(phys->connector,
  3488. phys->connector->state, &dither_cfg, &len);
  3489. if (ret)
  3490. return;
  3491. if (TOPOLOGY_DUALPIPE_MERGE_MODE(topology)) {
  3492. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  3493. hw_pp = sde_enc->hw_pp[i];
  3494. if (hw_pp) {
  3495. phys->hw_pp->ops.setup_dither(hw_pp, dither_cfg,
  3496. len);
  3497. }
  3498. }
  3499. } else {
  3500. phys->hw_pp->ops.setup_dither(phys->hw_pp, dither_cfg, len);
  3501. }
  3502. }
  3503. static u32 _sde_encoder_calculate_linetime(struct sde_encoder_virt *sde_enc,
  3504. struct drm_display_mode *mode)
  3505. {
  3506. u64 pclk_rate;
  3507. u32 pclk_period;
  3508. u32 line_time;
  3509. /*
  3510. * For linetime calculation, only operate on master encoder.
  3511. */
  3512. if (!sde_enc->cur_master)
  3513. return 0;
  3514. if (!sde_enc->cur_master->ops.get_line_count) {
  3515. SDE_ERROR("get_line_count function not defined\n");
  3516. return 0;
  3517. }
  3518. pclk_rate = mode->clock; /* pixel clock in kHz */
  3519. if (pclk_rate == 0) {
  3520. SDE_ERROR("pclk is 0, cannot calculate line time\n");
  3521. return 0;
  3522. }
  3523. pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate);
  3524. if (pclk_period == 0) {
  3525. SDE_ERROR("pclk period is 0\n");
  3526. return 0;
  3527. }
  3528. /*
  3529. * Line time calculation based on Pixel clock and HTOTAL.
  3530. * Final unit is in ns.
  3531. */
  3532. line_time = (pclk_period * mode->htotal) / 1000;
  3533. if (line_time == 0) {
  3534. SDE_ERROR("line time calculation is 0\n");
  3535. return 0;
  3536. }
  3537. SDE_DEBUG_ENC(sde_enc,
  3538. "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n",
  3539. pclk_rate, pclk_period, line_time);
  3540. return line_time;
  3541. }
  3542. static int _sde_encoder_wakeup_time(struct drm_encoder *drm_enc,
  3543. ktime_t *wakeup_time)
  3544. {
  3545. struct drm_display_mode *mode;
  3546. struct sde_encoder_virt *sde_enc;
  3547. u32 cur_line;
  3548. u32 line_time;
  3549. u32 vtotal, time_to_vsync;
  3550. ktime_t cur_time;
  3551. sde_enc = to_sde_encoder_virt(drm_enc);
  3552. if (!sde_enc || !sde_enc->cur_master) {
  3553. SDE_ERROR("invalid sde encoder/master\n");
  3554. return -EINVAL;
  3555. }
  3556. mode = &sde_enc->cur_master->cached_mode;
  3557. line_time = _sde_encoder_calculate_linetime(sde_enc, mode);
  3558. if (!line_time)
  3559. return -EINVAL;
  3560. cur_line = sde_enc->cur_master->ops.get_line_count(sde_enc->cur_master);
  3561. vtotal = mode->vtotal;
  3562. if (cur_line >= vtotal)
  3563. time_to_vsync = line_time * vtotal;
  3564. else
  3565. time_to_vsync = line_time * (vtotal - cur_line);
  3566. if (time_to_vsync == 0) {
  3567. SDE_ERROR("time to vsync should not be zero, vtotal=%d\n",
  3568. vtotal);
  3569. return -EINVAL;
  3570. }
  3571. cur_time = ktime_get();
  3572. *wakeup_time = ktime_add_ns(cur_time, time_to_vsync);
  3573. SDE_DEBUG_ENC(sde_enc,
  3574. "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n",
  3575. cur_line, vtotal, time_to_vsync,
  3576. ktime_to_ms(cur_time),
  3577. ktime_to_ms(*wakeup_time));
  3578. return 0;
  3579. }
  3580. static void sde_encoder_vsync_event_handler(struct timer_list *t)
  3581. {
  3582. struct drm_encoder *drm_enc;
  3583. struct sde_encoder_virt *sde_enc =
  3584. from_timer(sde_enc, t, vsync_event_timer);
  3585. struct msm_drm_private *priv;
  3586. struct msm_drm_thread *event_thread;
  3587. if (!sde_enc || !sde_enc->crtc) {
  3588. SDE_ERROR("invalid encoder parameters %d\n", !sde_enc);
  3589. return;
  3590. }
  3591. drm_enc = &sde_enc->base;
  3592. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  3593. SDE_ERROR("invalid encoder parameters\n");
  3594. return;
  3595. }
  3596. priv = drm_enc->dev->dev_private;
  3597. if (sde_enc->crtc->index >= ARRAY_SIZE(priv->event_thread)) {
  3598. SDE_ERROR("invalid crtc index:%u\n",
  3599. sde_enc->crtc->index);
  3600. return;
  3601. }
  3602. event_thread = &priv->event_thread[sde_enc->crtc->index];
  3603. if (!event_thread) {
  3604. SDE_ERROR("event_thread not found for crtc:%d\n",
  3605. sde_enc->crtc->index);
  3606. return;
  3607. }
  3608. kthread_queue_work(&event_thread->worker,
  3609. &sde_enc->vsync_event_work);
  3610. }
  3611. static void sde_encoder_esd_trigger_work_handler(struct kthread_work *work)
  3612. {
  3613. struct sde_encoder_virt *sde_enc = container_of(work,
  3614. struct sde_encoder_virt, esd_trigger_work);
  3615. if (!sde_enc) {
  3616. SDE_ERROR("invalid sde encoder\n");
  3617. return;
  3618. }
  3619. sde_encoder_resource_control(&sde_enc->base,
  3620. SDE_ENC_RC_EVENT_KICKOFF);
  3621. }
  3622. static void sde_encoder_input_event_work_handler(struct kthread_work *work)
  3623. {
  3624. struct sde_encoder_virt *sde_enc = container_of(work,
  3625. struct sde_encoder_virt, input_event_work);
  3626. if (!sde_enc) {
  3627. SDE_ERROR("invalid sde encoder\n");
  3628. return;
  3629. }
  3630. sde_encoder_resource_control(&sde_enc->base,
  3631. SDE_ENC_RC_EVENT_EARLY_WAKEUP);
  3632. }
  3633. static void sde_encoder_vsync_event_work_handler(struct kthread_work *work)
  3634. {
  3635. struct sde_encoder_virt *sde_enc = container_of(work,
  3636. struct sde_encoder_virt, vsync_event_work);
  3637. bool autorefresh_enabled = false;
  3638. int rc = 0;
  3639. ktime_t wakeup_time;
  3640. struct drm_encoder *drm_enc;
  3641. if (!sde_enc) {
  3642. SDE_ERROR("invalid sde encoder\n");
  3643. return;
  3644. }
  3645. drm_enc = &sde_enc->base;
  3646. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  3647. if (rc < 0) {
  3648. SDE_ERROR_ENC(sde_enc, "sde enc power enabled failed:%d\n", rc);
  3649. return;
  3650. }
  3651. if (sde_enc->cur_master &&
  3652. sde_enc->cur_master->ops.is_autorefresh_enabled)
  3653. autorefresh_enabled =
  3654. sde_enc->cur_master->ops.is_autorefresh_enabled(
  3655. sde_enc->cur_master);
  3656. /* Update timer if autorefresh is enabled else return */
  3657. if (!autorefresh_enabled)
  3658. goto exit;
  3659. rc = _sde_encoder_wakeup_time(&sde_enc->base, &wakeup_time);
  3660. if (rc)
  3661. goto exit;
  3662. SDE_EVT32_VERBOSE(ktime_to_ms(wakeup_time));
  3663. mod_timer(&sde_enc->vsync_event_timer,
  3664. nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
  3665. exit:
  3666. pm_runtime_put_sync(drm_enc->dev->dev);
  3667. }
  3668. int sde_encoder_poll_line_counts(struct drm_encoder *drm_enc)
  3669. {
  3670. static const uint64_t timeout_us = 50000;
  3671. static const uint64_t sleep_us = 20;
  3672. struct sde_encoder_virt *sde_enc;
  3673. ktime_t cur_ktime, exp_ktime;
  3674. uint32_t line_count, tmp, i;
  3675. if (!drm_enc) {
  3676. SDE_ERROR("invalid encoder\n");
  3677. return -EINVAL;
  3678. }
  3679. sde_enc = to_sde_encoder_virt(drm_enc);
  3680. if (!sde_enc->cur_master ||
  3681. !sde_enc->cur_master->ops.get_line_count) {
  3682. SDE_DEBUG_ENC(sde_enc, "can't get master line count\n");
  3683. SDE_EVT32(DRMID(drm_enc), SDE_EVTLOG_ERROR);
  3684. return -EINVAL;
  3685. }
  3686. exp_ktime = ktime_add_ms(ktime_get(), timeout_us / 1000);
  3687. line_count = sde_enc->cur_master->ops.get_line_count(
  3688. sde_enc->cur_master);
  3689. for (i = 0; i < (timeout_us * 2 / sleep_us); ++i) {
  3690. tmp = line_count;
  3691. line_count = sde_enc->cur_master->ops.get_line_count(
  3692. sde_enc->cur_master);
  3693. if (line_count < tmp) {
  3694. SDE_EVT32(DRMID(drm_enc), line_count);
  3695. return 0;
  3696. }
  3697. cur_ktime = ktime_get();
  3698. if (ktime_compare_safe(exp_ktime, cur_ktime) <= 0)
  3699. break;
  3700. usleep_range(sleep_us / 2, sleep_us);
  3701. }
  3702. SDE_EVT32(DRMID(drm_enc), line_count, SDE_EVTLOG_ERROR);
  3703. return -ETIMEDOUT;
  3704. }
  3705. static int _helper_flush_qsync(struct sde_encoder_phys *phys_enc)
  3706. {
  3707. struct drm_encoder *drm_enc;
  3708. struct sde_rm_hw_iter rm_iter;
  3709. bool lm_valid = false;
  3710. bool intf_valid = false;
  3711. if (!phys_enc || !phys_enc->parent) {
  3712. SDE_ERROR("invalid encoder\n");
  3713. return -EINVAL;
  3714. }
  3715. drm_enc = phys_enc->parent;
  3716. /* Flush the interfaces for AVR update or Qsync with INTF TE */
  3717. if (phys_enc->intf_mode == INTF_MODE_VIDEO ||
  3718. (phys_enc->intf_mode == INTF_MODE_CMD &&
  3719. phys_enc->has_intf_te)) {
  3720. sde_rm_init_hw_iter(&rm_iter, drm_enc->base.id,
  3721. SDE_HW_BLK_INTF);
  3722. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &rm_iter)) {
  3723. struct sde_hw_intf *hw_intf =
  3724. (struct sde_hw_intf *)rm_iter.hw;
  3725. if (!hw_intf)
  3726. continue;
  3727. if (phys_enc->hw_ctl->ops.update_bitmask_intf)
  3728. phys_enc->hw_ctl->ops.update_bitmask_intf(
  3729. phys_enc->hw_ctl,
  3730. hw_intf->idx, 1);
  3731. intf_valid = true;
  3732. }
  3733. if (!intf_valid) {
  3734. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc),
  3735. "intf not found to flush\n");
  3736. return -EFAULT;
  3737. }
  3738. } else {
  3739. sde_rm_init_hw_iter(&rm_iter, drm_enc->base.id, SDE_HW_BLK_LM);
  3740. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &rm_iter)) {
  3741. struct sde_hw_mixer *hw_lm =
  3742. (struct sde_hw_mixer *)rm_iter.hw;
  3743. if (!hw_lm)
  3744. continue;
  3745. /* update LM flush for HW without INTF TE */
  3746. if (phys_enc->hw_ctl->ops.update_bitmask_mixer)
  3747. phys_enc->hw_ctl->ops.update_bitmask_mixer(
  3748. phys_enc->hw_ctl,
  3749. hw_lm->idx, 1);
  3750. lm_valid = true;
  3751. }
  3752. if (!lm_valid) {
  3753. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc),
  3754. "lm not found to flush\n");
  3755. return -EFAULT;
  3756. }
  3757. }
  3758. return 0;
  3759. }
  3760. static bool _sde_encoder_dsc_is_dirty(struct sde_encoder_virt *sde_enc)
  3761. {
  3762. int i;
  3763. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  3764. /**
  3765. * This dirty_dsc_hw field is set during DSC disable to
  3766. * indicate which DSC blocks need to be flushed
  3767. */
  3768. if (sde_enc->dirty_dsc_ids[i])
  3769. return true;
  3770. }
  3771. return false;
  3772. }
  3773. static void _helper_flush_dsc(struct sde_encoder_virt *sde_enc)
  3774. {
  3775. int i;
  3776. struct sde_hw_ctl *hw_ctl = NULL;
  3777. enum sde_dsc dsc_idx;
  3778. if (sde_enc->cur_master)
  3779. hw_ctl = sde_enc->cur_master->hw_ctl;
  3780. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  3781. dsc_idx = sde_enc->dirty_dsc_ids[i];
  3782. if (dsc_idx && hw_ctl && hw_ctl->ops.update_bitmask_dsc)
  3783. hw_ctl->ops.update_bitmask_dsc(hw_ctl, dsc_idx, 1);
  3784. sde_enc->dirty_dsc_ids[i] = DSC_NONE;
  3785. }
  3786. }
  3787. static void _sde_encoder_helper_hdr_plus_mempool_update(
  3788. struct sde_encoder_virt *sde_enc)
  3789. {
  3790. struct sde_connector_dyn_hdr_metadata *dhdr_meta = NULL;
  3791. struct sde_hw_mdp *mdptop = NULL;
  3792. sde_enc->dynamic_hdr_updated = false;
  3793. if (sde_enc->cur_master) {
  3794. mdptop = sde_enc->cur_master->hw_mdptop;
  3795. dhdr_meta = sde_connector_get_dyn_hdr_meta(
  3796. sde_enc->cur_master->connector);
  3797. }
  3798. if (!mdptop || !dhdr_meta || !dhdr_meta->dynamic_hdr_update)
  3799. return;
  3800. if (mdptop->ops.set_hdr_plus_metadata) {
  3801. sde_enc->dynamic_hdr_updated = true;
  3802. mdptop->ops.set_hdr_plus_metadata(
  3803. mdptop, dhdr_meta->dynamic_hdr_payload,
  3804. dhdr_meta->dynamic_hdr_payload_size,
  3805. sde_enc->cur_master->intf_idx == INTF_0 ?
  3806. 0 : 1);
  3807. }
  3808. }
  3809. static void _sde_encoder_needs_hw_reset(struct drm_encoder *drm_enc,
  3810. int ln_cnt1)
  3811. {
  3812. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  3813. struct sde_encoder_phys *phys;
  3814. int ln_cnt2, i;
  3815. /* query line count before cur_master is updated */
  3816. if (sde_enc->cur_master && sde_enc->cur_master->ops.get_wr_line_count)
  3817. ln_cnt2 = sde_enc->cur_master->ops.get_wr_line_count(
  3818. sde_enc->cur_master);
  3819. else
  3820. ln_cnt2 = -EINVAL;
  3821. SDE_EVT32(DRMID(drm_enc), ln_cnt1, ln_cnt2);
  3822. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3823. phys = sde_enc->phys_encs[i];
  3824. if (phys && phys->ops.hw_reset)
  3825. phys->ops.hw_reset(phys);
  3826. }
  3827. }
  3828. int sde_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc,
  3829. struct sde_encoder_kickoff_params *params)
  3830. {
  3831. struct sde_encoder_virt *sde_enc;
  3832. struct sde_encoder_phys *phys;
  3833. struct sde_kms *sde_kms = NULL;
  3834. struct msm_drm_private *priv = NULL;
  3835. bool needs_hw_reset = false;
  3836. int ln_cnt1 = -EINVAL, i, rc, ret = 0;
  3837. struct msm_display_info *disp_info;
  3838. if (!drm_enc || !params || !drm_enc->dev ||
  3839. !drm_enc->dev->dev_private) {
  3840. SDE_ERROR("invalid args\n");
  3841. return -EINVAL;
  3842. }
  3843. sde_enc = to_sde_encoder_virt(drm_enc);
  3844. priv = drm_enc->dev->dev_private;
  3845. sde_kms = to_sde_kms(priv->kms);
  3846. disp_info = &sde_enc->disp_info;
  3847. SDE_DEBUG_ENC(sde_enc, "\n");
  3848. SDE_EVT32(DRMID(drm_enc));
  3849. /* save this for later, in case of errors */
  3850. if (sde_enc->cur_master && sde_enc->cur_master->ops.get_wr_line_count)
  3851. ln_cnt1 = sde_enc->cur_master->ops.get_wr_line_count(
  3852. sde_enc->cur_master);
  3853. /* update the qsync parameters for the current frame */
  3854. if (sde_enc->cur_master)
  3855. sde_connector_set_qsync_params(
  3856. sde_enc->cur_master->connector);
  3857. if (sde_enc->cur_master && sde_enc->cur_master->connector &&
  3858. sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  3859. sde_enc->frame_trigger_mode = sde_connector_get_property(
  3860. sde_enc->cur_master->connector->state,
  3861. CONNECTOR_PROP_CMD_FRAME_TRIGGER_MODE);
  3862. _sde_encoder_helper_hdr_plus_mempool_update(sde_enc);
  3863. /* prepare for next kickoff, may include waiting on previous kickoff */
  3864. SDE_ATRACE_BEGIN("sde_encoder_prepare_for_kickoff");
  3865. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3866. phys = sde_enc->phys_encs[i];
  3867. params->frame_trigger_mode = sde_enc->frame_trigger_mode;
  3868. params->recovery_events_enabled =
  3869. sde_enc->recovery_events_enabled;
  3870. if (phys) {
  3871. if (phys->ops.prepare_for_kickoff) {
  3872. rc = phys->ops.prepare_for_kickoff(
  3873. phys, params);
  3874. if (rc)
  3875. ret = rc;
  3876. }
  3877. if (phys->enable_state == SDE_ENC_ERR_NEEDS_HW_RESET)
  3878. needs_hw_reset = true;
  3879. _sde_encoder_setup_dither(phys);
  3880. if (sde_enc->cur_master &&
  3881. sde_connector_is_qsync_updated(
  3882. sde_enc->cur_master->connector)) {
  3883. _helper_flush_qsync(phys);
  3884. }
  3885. }
  3886. }
  3887. rc = sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_KICKOFF);
  3888. if (rc) {
  3889. SDE_ERROR_ENC(sde_enc, "resource kickoff failed rc %d\n", rc);
  3890. ret = rc;
  3891. goto end;
  3892. }
  3893. /* if any phys needs reset, reset all phys, in-order */
  3894. if (needs_hw_reset)
  3895. _sde_encoder_needs_hw_reset(drm_enc, ln_cnt1);
  3896. _sde_encoder_update_master(drm_enc, params);
  3897. _sde_encoder_update_roi(drm_enc);
  3898. if (sde_enc->cur_master && sde_enc->cur_master->connector) {
  3899. rc = sde_connector_pre_kickoff(sde_enc->cur_master->connector);
  3900. if (rc) {
  3901. SDE_ERROR_ENC(sde_enc, "kickoff conn%d failed rc %d\n",
  3902. sde_enc->cur_master->connector->base.id,
  3903. rc);
  3904. ret = rc;
  3905. }
  3906. }
  3907. if (_sde_encoder_is_dsc_enabled(drm_enc) && sde_enc->cur_master &&
  3908. !sde_enc->cur_master->cont_splash_enabled) {
  3909. rc = _sde_encoder_dsc_setup(sde_enc, params);
  3910. if (rc) {
  3911. SDE_ERROR_ENC(sde_enc, "failed to setup DSC: %d\n", rc);
  3912. ret = rc;
  3913. }
  3914. } else if (_sde_encoder_dsc_is_dirty(sde_enc)) {
  3915. _helper_flush_dsc(sde_enc);
  3916. }
  3917. end:
  3918. SDE_ATRACE_END("sde_encoder_prepare_for_kickoff");
  3919. return ret;
  3920. }
  3921. /**
  3922. * _sde_encoder_reset_ctl_hw - reset h/w configuration for all ctl's associated
  3923. * with the specified encoder, and unstage all pipes from it
  3924. * @encoder: encoder pointer
  3925. * Returns: 0 on success
  3926. */
  3927. static int _sde_encoder_reset_ctl_hw(struct drm_encoder *drm_enc)
  3928. {
  3929. struct sde_encoder_virt *sde_enc;
  3930. struct sde_encoder_phys *phys;
  3931. unsigned int i;
  3932. int rc = 0;
  3933. if (!drm_enc) {
  3934. SDE_ERROR("invalid encoder\n");
  3935. return -EINVAL;
  3936. }
  3937. sde_enc = to_sde_encoder_virt(drm_enc);
  3938. SDE_ATRACE_BEGIN("encoder_release_lm");
  3939. SDE_DEBUG_ENC(sde_enc, "\n");
  3940. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3941. phys = sde_enc->phys_encs[i];
  3942. if (!phys)
  3943. continue;
  3944. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0);
  3945. rc = sde_encoder_helper_reset_mixers(phys, NULL);
  3946. if (rc)
  3947. SDE_EVT32(DRMID(drm_enc), rc, SDE_EVTLOG_ERROR);
  3948. }
  3949. SDE_ATRACE_END("encoder_release_lm");
  3950. return rc;
  3951. }
  3952. void sde_encoder_kickoff(struct drm_encoder *drm_enc, bool is_error)
  3953. {
  3954. struct sde_encoder_virt *sde_enc;
  3955. struct sde_encoder_phys *phys;
  3956. ktime_t wakeup_time;
  3957. unsigned int i;
  3958. if (!drm_enc) {
  3959. SDE_ERROR("invalid encoder\n");
  3960. return;
  3961. }
  3962. SDE_ATRACE_BEGIN("encoder_kickoff");
  3963. sde_enc = to_sde_encoder_virt(drm_enc);
  3964. SDE_DEBUG_ENC(sde_enc, "\n");
  3965. /* create a 'no pipes' commit to release buffers on errors */
  3966. if (is_error)
  3967. _sde_encoder_reset_ctl_hw(drm_enc);
  3968. /* All phys encs are ready to go, trigger the kickoff */
  3969. _sde_encoder_kickoff_phys(sde_enc);
  3970. /* allow phys encs to handle any post-kickoff business */
  3971. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3972. phys = sde_enc->phys_encs[i];
  3973. if (phys && phys->ops.handle_post_kickoff)
  3974. phys->ops.handle_post_kickoff(phys);
  3975. }
  3976. if (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DSI &&
  3977. !_sde_encoder_wakeup_time(drm_enc, &wakeup_time)) {
  3978. SDE_EVT32_VERBOSE(ktime_to_ms(wakeup_time));
  3979. mod_timer(&sde_enc->vsync_event_timer,
  3980. nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
  3981. }
  3982. SDE_ATRACE_END("encoder_kickoff");
  3983. }
  3984. void sde_encoder_helper_get_pp_line_count(struct drm_encoder *drm_enc,
  3985. struct sde_hw_pp_vsync_info *info)
  3986. {
  3987. struct sde_encoder_virt *sde_enc;
  3988. struct sde_encoder_phys *phys;
  3989. int i, ret;
  3990. if (!drm_enc || !info)
  3991. return;
  3992. sde_enc = to_sde_encoder_virt(drm_enc);
  3993. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3994. phys = sde_enc->phys_encs[i];
  3995. if (phys && phys->hw_intf && phys->hw_pp
  3996. && phys->hw_intf->ops.get_vsync_info) {
  3997. ret = phys->hw_intf->ops.get_vsync_info(
  3998. phys->hw_intf, &info[i]);
  3999. if (!ret) {
  4000. info[i].pp_idx = phys->hw_pp->idx - PINGPONG_0;
  4001. info[i].intf_idx = phys->hw_intf->idx - INTF_0;
  4002. }
  4003. }
  4004. }
  4005. }
  4006. int sde_encoder_helper_reset_mixers(struct sde_encoder_phys *phys_enc,
  4007. struct drm_framebuffer *fb)
  4008. {
  4009. struct drm_encoder *drm_enc;
  4010. struct sde_hw_mixer_cfg mixer;
  4011. struct sde_rm_hw_iter lm_iter;
  4012. bool lm_valid = false;
  4013. if (!phys_enc || !phys_enc->parent) {
  4014. SDE_ERROR("invalid encoder\n");
  4015. return -EINVAL;
  4016. }
  4017. drm_enc = phys_enc->parent;
  4018. memset(&mixer, 0, sizeof(mixer));
  4019. /* reset associated CTL/LMs */
  4020. if (phys_enc->hw_ctl->ops.clear_all_blendstages)
  4021. phys_enc->hw_ctl->ops.clear_all_blendstages(phys_enc->hw_ctl);
  4022. sde_rm_init_hw_iter(&lm_iter, drm_enc->base.id, SDE_HW_BLK_LM);
  4023. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &lm_iter)) {
  4024. struct sde_hw_mixer *hw_lm = (struct sde_hw_mixer *)lm_iter.hw;
  4025. if (!hw_lm)
  4026. continue;
  4027. /* need to flush LM to remove it */
  4028. if (phys_enc->hw_ctl->ops.update_bitmask_mixer)
  4029. phys_enc->hw_ctl->ops.update_bitmask_mixer(
  4030. phys_enc->hw_ctl,
  4031. hw_lm->idx, 1);
  4032. if (fb) {
  4033. /* assume a single LM if targeting a frame buffer */
  4034. if (lm_valid)
  4035. continue;
  4036. mixer.out_height = fb->height;
  4037. mixer.out_width = fb->width;
  4038. if (hw_lm->ops.setup_mixer_out)
  4039. hw_lm->ops.setup_mixer_out(hw_lm, &mixer);
  4040. }
  4041. lm_valid = true;
  4042. /* only enable border color on LM */
  4043. if (phys_enc->hw_ctl->ops.setup_blendstage)
  4044. phys_enc->hw_ctl->ops.setup_blendstage(
  4045. phys_enc->hw_ctl, hw_lm->idx, NULL);
  4046. }
  4047. if (!lm_valid) {
  4048. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc), "lm not found\n");
  4049. return -EFAULT;
  4050. }
  4051. return 0;
  4052. }
  4053. void sde_encoder_prepare_commit(struct drm_encoder *drm_enc)
  4054. {
  4055. struct sde_encoder_virt *sde_enc;
  4056. struct sde_encoder_phys *phys;
  4057. int i;
  4058. if (!drm_enc) {
  4059. SDE_ERROR("invalid encoder\n");
  4060. return;
  4061. }
  4062. sde_enc = to_sde_encoder_virt(drm_enc);
  4063. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4064. phys = sde_enc->phys_encs[i];
  4065. if (phys && phys->ops.prepare_commit)
  4066. phys->ops.prepare_commit(phys);
  4067. }
  4068. }
  4069. void sde_encoder_helper_setup_misr(struct sde_encoder_phys *phys_enc,
  4070. bool enable, u32 frame_count)
  4071. {
  4072. if (!phys_enc)
  4073. return;
  4074. if (phys_enc->hw_intf && phys_enc->hw_intf->ops.setup_misr)
  4075. phys_enc->hw_intf->ops.setup_misr(phys_enc->hw_intf,
  4076. enable, frame_count);
  4077. }
  4078. int sde_encoder_helper_collect_misr(struct sde_encoder_phys *phys_enc,
  4079. bool nonblock, u32 *misr_value)
  4080. {
  4081. if (!phys_enc)
  4082. return -EINVAL;
  4083. return phys_enc->hw_intf && phys_enc->hw_intf->ops.collect_misr ?
  4084. phys_enc->hw_intf->ops.collect_misr(phys_enc->hw_intf,
  4085. nonblock, misr_value) : -ENOTSUPP;
  4086. }
  4087. #ifdef CONFIG_DEBUG_FS
  4088. static int _sde_encoder_status_show(struct seq_file *s, void *data)
  4089. {
  4090. struct sde_encoder_virt *sde_enc;
  4091. int i;
  4092. if (!s || !s->private)
  4093. return -EINVAL;
  4094. sde_enc = s->private;
  4095. mutex_lock(&sde_enc->enc_lock);
  4096. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4097. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4098. if (!phys)
  4099. continue;
  4100. seq_printf(s, "intf:%d vsync:%8d underrun:%8d ",
  4101. phys->intf_idx - INTF_0,
  4102. atomic_read(&phys->vsync_cnt),
  4103. atomic_read(&phys->underrun_cnt));
  4104. switch (phys->intf_mode) {
  4105. case INTF_MODE_VIDEO:
  4106. seq_puts(s, "mode: video\n");
  4107. break;
  4108. case INTF_MODE_CMD:
  4109. seq_puts(s, "mode: command\n");
  4110. break;
  4111. case INTF_MODE_WB_BLOCK:
  4112. seq_puts(s, "mode: wb block\n");
  4113. break;
  4114. case INTF_MODE_WB_LINE:
  4115. seq_puts(s, "mode: wb line\n");
  4116. break;
  4117. default:
  4118. seq_puts(s, "mode: ???\n");
  4119. break;
  4120. }
  4121. }
  4122. mutex_unlock(&sde_enc->enc_lock);
  4123. return 0;
  4124. }
  4125. static int _sde_encoder_debugfs_status_open(struct inode *inode,
  4126. struct file *file)
  4127. {
  4128. return single_open(file, _sde_encoder_status_show, inode->i_private);
  4129. }
  4130. static ssize_t _sde_encoder_misr_setup(struct file *file,
  4131. const char __user *user_buf, size_t count, loff_t *ppos)
  4132. {
  4133. struct sde_encoder_virt *sde_enc;
  4134. int rc;
  4135. char buf[MISR_BUFF_SIZE + 1];
  4136. size_t buff_copy;
  4137. u32 frame_count, enable;
  4138. struct msm_drm_private *priv = NULL;
  4139. struct sde_kms *sde_kms = NULL;
  4140. struct drm_encoder *drm_enc;
  4141. if (!file || !file->private_data)
  4142. return -EINVAL;
  4143. sde_enc = file->private_data;
  4144. priv = sde_enc->base.dev->dev_private;
  4145. if (!sde_enc || !priv || !priv->kms)
  4146. return -EINVAL;
  4147. sde_kms = to_sde_kms(priv->kms);
  4148. drm_enc = &sde_enc->base;
  4149. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  4150. SDE_DEBUG_ENC(sde_enc, "misr enable/disable not allowed\n");
  4151. return -ENOTSUPP;
  4152. }
  4153. buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
  4154. if (copy_from_user(buf, user_buf, buff_copy))
  4155. return -EINVAL;
  4156. buf[buff_copy] = 0; /* end of string */
  4157. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
  4158. return -EINVAL;
  4159. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  4160. if (rc < 0)
  4161. return rc;
  4162. sde_enc->misr_enable = enable;
  4163. sde_enc->misr_frame_count = frame_count;
  4164. sde_encoder_misr_configure(&sde_enc->base, enable, frame_count);
  4165. pm_runtime_put_sync(drm_enc->dev->dev);
  4166. return count;
  4167. }
  4168. static ssize_t _sde_encoder_misr_read(struct file *file,
  4169. char __user *user_buff, size_t count, loff_t *ppos)
  4170. {
  4171. struct sde_encoder_virt *sde_enc;
  4172. struct msm_drm_private *priv = NULL;
  4173. struct sde_kms *sde_kms = NULL;
  4174. struct drm_encoder *drm_enc;
  4175. int i = 0, len = 0;
  4176. char buf[MISR_BUFF_SIZE + 1] = {'\0'};
  4177. int rc;
  4178. if (*ppos)
  4179. return 0;
  4180. if (!file || !file->private_data)
  4181. return -EINVAL;
  4182. sde_enc = file->private_data;
  4183. priv = sde_enc->base.dev->dev_private;
  4184. if (priv != NULL)
  4185. sde_kms = to_sde_kms(priv->kms);
  4186. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  4187. SDE_DEBUG_ENC(sde_enc, "misr read not allowed\n");
  4188. return -ENOTSUPP;
  4189. }
  4190. drm_enc = &sde_enc->base;
  4191. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  4192. if (rc < 0)
  4193. return rc;
  4194. if (!sde_enc->misr_enable) {
  4195. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4196. "disabled\n");
  4197. goto buff_check;
  4198. }
  4199. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4200. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4201. u32 misr_value = 0;
  4202. if (!phys || !phys->ops.collect_misr) {
  4203. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4204. "invalid\n");
  4205. SDE_ERROR_ENC(sde_enc, "invalid misr ops\n");
  4206. continue;
  4207. }
  4208. rc = phys->ops.collect_misr(phys, false, &misr_value);
  4209. if (rc) {
  4210. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4211. "invalid\n");
  4212. SDE_ERROR_ENC(sde_enc, "failed to collect misr %d\n",
  4213. rc);
  4214. continue;
  4215. } else {
  4216. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4217. "Intf idx:%d\n",
  4218. phys->intf_idx - INTF_0);
  4219. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4220. "0x%x\n", misr_value);
  4221. }
  4222. }
  4223. buff_check:
  4224. if (count <= len) {
  4225. len = 0;
  4226. goto end;
  4227. }
  4228. if (copy_to_user(user_buff, buf, len)) {
  4229. len = -EFAULT;
  4230. goto end;
  4231. }
  4232. *ppos += len; /* increase offset */
  4233. end:
  4234. pm_runtime_put_sync(drm_enc->dev->dev);
  4235. return len;
  4236. }
  4237. static int _sde_encoder_init_debugfs(struct drm_encoder *drm_enc)
  4238. {
  4239. struct sde_encoder_virt *sde_enc;
  4240. struct msm_drm_private *priv;
  4241. struct sde_kms *sde_kms;
  4242. int i;
  4243. static const struct file_operations debugfs_status_fops = {
  4244. .open = _sde_encoder_debugfs_status_open,
  4245. .read = seq_read,
  4246. .llseek = seq_lseek,
  4247. .release = single_release,
  4248. };
  4249. static const struct file_operations debugfs_misr_fops = {
  4250. .open = simple_open,
  4251. .read = _sde_encoder_misr_read,
  4252. .write = _sde_encoder_misr_setup,
  4253. };
  4254. char name[SDE_NAME_SIZE];
  4255. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  4256. SDE_ERROR("invalid encoder or kms\n");
  4257. return -EINVAL;
  4258. }
  4259. sde_enc = to_sde_encoder_virt(drm_enc);
  4260. priv = drm_enc->dev->dev_private;
  4261. sde_kms = to_sde_kms(priv->kms);
  4262. snprintf(name, SDE_NAME_SIZE, "encoder%u", drm_enc->base.id);
  4263. /* create overall sub-directory for the encoder */
  4264. sde_enc->debugfs_root = debugfs_create_dir(name,
  4265. drm_enc->dev->primary->debugfs_root);
  4266. if (!sde_enc->debugfs_root)
  4267. return -ENOMEM;
  4268. /* don't error check these */
  4269. debugfs_create_file("status", 0400,
  4270. sde_enc->debugfs_root, sde_enc, &debugfs_status_fops);
  4271. debugfs_create_file("misr_data", 0600,
  4272. sde_enc->debugfs_root, sde_enc, &debugfs_misr_fops);
  4273. debugfs_create_bool("idle_power_collapse", 0600, sde_enc->debugfs_root,
  4274. &sde_enc->idle_pc_enabled);
  4275. debugfs_create_u32("frame_trigger_mode", 0400, sde_enc->debugfs_root,
  4276. &sde_enc->frame_trigger_mode);
  4277. for (i = 0; i < sde_enc->num_phys_encs; i++)
  4278. if (sde_enc->phys_encs[i] &&
  4279. sde_enc->phys_encs[i]->ops.late_register)
  4280. sde_enc->phys_encs[i]->ops.late_register(
  4281. sde_enc->phys_encs[i],
  4282. sde_enc->debugfs_root);
  4283. return 0;
  4284. }
  4285. static void _sde_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
  4286. {
  4287. struct sde_encoder_virt *sde_enc;
  4288. if (!drm_enc)
  4289. return;
  4290. sde_enc = to_sde_encoder_virt(drm_enc);
  4291. debugfs_remove_recursive(sde_enc->debugfs_root);
  4292. }
  4293. #else
  4294. static int _sde_encoder_init_debugfs(struct drm_encoder *drm_enc)
  4295. {
  4296. return 0;
  4297. }
  4298. static void _sde_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
  4299. {
  4300. }
  4301. #endif
  4302. static int sde_encoder_late_register(struct drm_encoder *encoder)
  4303. {
  4304. return _sde_encoder_init_debugfs(encoder);
  4305. }
  4306. static void sde_encoder_early_unregister(struct drm_encoder *encoder)
  4307. {
  4308. _sde_encoder_destroy_debugfs(encoder);
  4309. }
  4310. static int sde_encoder_virt_add_phys_encs(
  4311. struct msm_display_info *disp_info,
  4312. struct sde_encoder_virt *sde_enc,
  4313. struct sde_enc_phys_init_params *params)
  4314. {
  4315. struct sde_encoder_phys *enc = NULL;
  4316. u32 display_caps = disp_info->capabilities;
  4317. SDE_DEBUG_ENC(sde_enc, "\n");
  4318. /*
  4319. * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
  4320. * in this function, check up-front.
  4321. */
  4322. if (sde_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
  4323. ARRAY_SIZE(sde_enc->phys_encs)) {
  4324. SDE_ERROR_ENC(sde_enc, "too many physical encoders %d\n",
  4325. sde_enc->num_phys_encs);
  4326. return -EINVAL;
  4327. }
  4328. if (display_caps & MSM_DISPLAY_CAP_VID_MODE) {
  4329. enc = sde_encoder_phys_vid_init(params);
  4330. if (IS_ERR_OR_NULL(enc)) {
  4331. SDE_ERROR_ENC(sde_enc, "failed to init vid enc: %ld\n",
  4332. PTR_ERR(enc));
  4333. return !enc ? -EINVAL : PTR_ERR(enc);
  4334. }
  4335. sde_enc->phys_vid_encs[sde_enc->num_phys_encs] = enc;
  4336. }
  4337. if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) {
  4338. enc = sde_encoder_phys_cmd_init(params);
  4339. if (IS_ERR_OR_NULL(enc)) {
  4340. SDE_ERROR_ENC(sde_enc, "failed to init cmd enc: %ld\n",
  4341. PTR_ERR(enc));
  4342. return !enc ? -EINVAL : PTR_ERR(enc);
  4343. }
  4344. sde_enc->phys_cmd_encs[sde_enc->num_phys_encs] = enc;
  4345. }
  4346. if (disp_info->curr_panel_mode == MSM_DISPLAY_VIDEO_MODE)
  4347. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  4348. sde_enc->phys_vid_encs[sde_enc->num_phys_encs];
  4349. else
  4350. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  4351. sde_enc->phys_cmd_encs[sde_enc->num_phys_encs];
  4352. ++sde_enc->num_phys_encs;
  4353. return 0;
  4354. }
  4355. static int sde_encoder_virt_add_phys_enc_wb(struct sde_encoder_virt *sde_enc,
  4356. struct sde_enc_phys_init_params *params)
  4357. {
  4358. struct sde_encoder_phys *enc = NULL;
  4359. if (!sde_enc) {
  4360. SDE_ERROR("invalid encoder\n");
  4361. return -EINVAL;
  4362. }
  4363. SDE_DEBUG_ENC(sde_enc, "\n");
  4364. if (sde_enc->num_phys_encs + 1 >= ARRAY_SIZE(sde_enc->phys_encs)) {
  4365. SDE_ERROR_ENC(sde_enc, "too many physical encoders %d\n",
  4366. sde_enc->num_phys_encs);
  4367. return -EINVAL;
  4368. }
  4369. enc = sde_encoder_phys_wb_init(params);
  4370. if (IS_ERR_OR_NULL(enc)) {
  4371. SDE_ERROR_ENC(sde_enc, "failed to init wb enc: %ld\n",
  4372. PTR_ERR(enc));
  4373. return !enc ? -EINVAL : PTR_ERR(enc);
  4374. }
  4375. sde_enc->phys_encs[sde_enc->num_phys_encs] = enc;
  4376. ++sde_enc->num_phys_encs;
  4377. return 0;
  4378. }
  4379. static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc,
  4380. struct sde_kms *sde_kms,
  4381. struct msm_display_info *disp_info,
  4382. int *drm_enc_mode)
  4383. {
  4384. int ret = 0;
  4385. int i = 0;
  4386. enum sde_intf_type intf_type;
  4387. struct sde_encoder_virt_ops parent_ops = {
  4388. sde_encoder_vblank_callback,
  4389. sde_encoder_underrun_callback,
  4390. sde_encoder_frame_done_callback,
  4391. sde_encoder_get_qsync_fps_callback,
  4392. };
  4393. struct sde_enc_phys_init_params phys_params;
  4394. if (!sde_enc || !sde_kms) {
  4395. SDE_ERROR("invalid arg(s), enc %d kms %d\n",
  4396. !sde_enc, !sde_kms);
  4397. return -EINVAL;
  4398. }
  4399. memset(&phys_params, 0, sizeof(phys_params));
  4400. phys_params.sde_kms = sde_kms;
  4401. phys_params.parent = &sde_enc->base;
  4402. phys_params.parent_ops = parent_ops;
  4403. phys_params.enc_spinlock = &sde_enc->enc_spinlock;
  4404. phys_params.vblank_ctl_lock = &sde_enc->vblank_ctl_lock;
  4405. SDE_DEBUG("\n");
  4406. if (disp_info->intf_type == DRM_MODE_CONNECTOR_DSI) {
  4407. *drm_enc_mode = DRM_MODE_ENCODER_DSI;
  4408. intf_type = INTF_DSI;
  4409. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_HDMIA) {
  4410. *drm_enc_mode = DRM_MODE_ENCODER_TMDS;
  4411. intf_type = INTF_HDMI;
  4412. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_DisplayPort) {
  4413. if (disp_info->capabilities & MSM_DISPLAY_CAP_MST_MODE)
  4414. *drm_enc_mode = DRM_MODE_ENCODER_DPMST;
  4415. else
  4416. *drm_enc_mode = DRM_MODE_ENCODER_TMDS;
  4417. intf_type = INTF_DP;
  4418. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_VIRTUAL) {
  4419. *drm_enc_mode = DRM_MODE_ENCODER_VIRTUAL;
  4420. intf_type = INTF_WB;
  4421. } else {
  4422. SDE_ERROR_ENC(sde_enc, "unsupported display interface type\n");
  4423. return -EINVAL;
  4424. }
  4425. WARN_ON(disp_info->num_of_h_tiles < 1);
  4426. sde_enc->display_num_of_h_tiles = disp_info->num_of_h_tiles;
  4427. sde_enc->te_source = disp_info->te_source;
  4428. SDE_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
  4429. if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
  4430. (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE))
  4431. sde_enc->idle_pc_enabled = sde_kms->catalog->has_idle_pc;
  4432. mutex_lock(&sde_enc->enc_lock);
  4433. for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
  4434. /*
  4435. * Left-most tile is at index 0, content is controller id
  4436. * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
  4437. * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
  4438. */
  4439. u32 controller_id = disp_info->h_tile_instance[i];
  4440. if (disp_info->num_of_h_tiles > 1) {
  4441. if (i == 0)
  4442. phys_params.split_role = ENC_ROLE_MASTER;
  4443. else
  4444. phys_params.split_role = ENC_ROLE_SLAVE;
  4445. } else {
  4446. phys_params.split_role = ENC_ROLE_SOLO;
  4447. }
  4448. SDE_DEBUG("h_tile_instance %d = %d, split_role %d\n",
  4449. i, controller_id, phys_params.split_role);
  4450. if (sde_enc->ops.phys_init) {
  4451. struct sde_encoder_phys *enc;
  4452. enc = sde_enc->ops.phys_init(intf_type,
  4453. controller_id,
  4454. &phys_params);
  4455. if (enc) {
  4456. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  4457. enc;
  4458. ++sde_enc->num_phys_encs;
  4459. } else
  4460. SDE_ERROR_ENC(sde_enc,
  4461. "failed to add phys encs\n");
  4462. continue;
  4463. }
  4464. if (intf_type == INTF_WB) {
  4465. phys_params.intf_idx = INTF_MAX;
  4466. phys_params.wb_idx = sde_encoder_get_wb(
  4467. sde_kms->catalog,
  4468. intf_type, controller_id);
  4469. if (phys_params.wb_idx == WB_MAX) {
  4470. SDE_ERROR_ENC(sde_enc,
  4471. "could not get wb: type %d, id %d\n",
  4472. intf_type, controller_id);
  4473. ret = -EINVAL;
  4474. }
  4475. } else {
  4476. phys_params.wb_idx = WB_MAX;
  4477. phys_params.intf_idx = sde_encoder_get_intf(
  4478. sde_kms->catalog, intf_type,
  4479. controller_id);
  4480. if (phys_params.intf_idx == INTF_MAX) {
  4481. SDE_ERROR_ENC(sde_enc,
  4482. "could not get wb: type %d, id %d\n",
  4483. intf_type, controller_id);
  4484. ret = -EINVAL;
  4485. }
  4486. }
  4487. if (!ret) {
  4488. if (intf_type == INTF_WB)
  4489. ret = sde_encoder_virt_add_phys_enc_wb(sde_enc,
  4490. &phys_params);
  4491. else
  4492. ret = sde_encoder_virt_add_phys_encs(
  4493. disp_info,
  4494. sde_enc,
  4495. &phys_params);
  4496. if (ret)
  4497. SDE_ERROR_ENC(sde_enc,
  4498. "failed to add phys encs\n");
  4499. }
  4500. }
  4501. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4502. struct sde_encoder_phys *vid_phys = sde_enc->phys_vid_encs[i];
  4503. struct sde_encoder_phys *cmd_phys = sde_enc->phys_cmd_encs[i];
  4504. if (vid_phys) {
  4505. atomic_set(&vid_phys->vsync_cnt, 0);
  4506. atomic_set(&vid_phys->underrun_cnt, 0);
  4507. }
  4508. if (cmd_phys) {
  4509. atomic_set(&cmd_phys->vsync_cnt, 0);
  4510. atomic_set(&cmd_phys->underrun_cnt, 0);
  4511. }
  4512. }
  4513. mutex_unlock(&sde_enc->enc_lock);
  4514. return ret;
  4515. }
  4516. static const struct drm_encoder_helper_funcs sde_encoder_helper_funcs = {
  4517. .mode_set = sde_encoder_virt_mode_set,
  4518. .disable = sde_encoder_virt_disable,
  4519. .enable = sde_encoder_virt_enable,
  4520. .atomic_check = sde_encoder_virt_atomic_check,
  4521. };
  4522. static const struct drm_encoder_funcs sde_encoder_funcs = {
  4523. .destroy = sde_encoder_destroy,
  4524. .late_register = sde_encoder_late_register,
  4525. .early_unregister = sde_encoder_early_unregister,
  4526. };
  4527. struct drm_encoder *sde_encoder_init_with_ops(
  4528. struct drm_device *dev,
  4529. struct msm_display_info *disp_info,
  4530. const struct sde_encoder_ops *ops)
  4531. {
  4532. struct msm_drm_private *priv = dev->dev_private;
  4533. struct sde_kms *sde_kms = to_sde_kms(priv->kms);
  4534. struct drm_encoder *drm_enc = NULL;
  4535. struct sde_encoder_virt *sde_enc = NULL;
  4536. int drm_enc_mode = DRM_MODE_ENCODER_NONE;
  4537. char name[SDE_NAME_SIZE];
  4538. int ret = 0, i, intf_index = INTF_MAX;
  4539. struct sde_encoder_phys *phys = NULL;
  4540. sde_enc = kzalloc(sizeof(*sde_enc), GFP_KERNEL);
  4541. if (!sde_enc) {
  4542. ret = -ENOMEM;
  4543. goto fail;
  4544. }
  4545. if (ops)
  4546. sde_enc->ops = *ops;
  4547. mutex_init(&sde_enc->enc_lock);
  4548. ret = sde_encoder_setup_display(sde_enc, sde_kms, disp_info,
  4549. &drm_enc_mode);
  4550. if (ret)
  4551. goto fail;
  4552. sde_enc->cur_master = NULL;
  4553. spin_lock_init(&sde_enc->enc_spinlock);
  4554. mutex_init(&sde_enc->vblank_ctl_lock);
  4555. for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
  4556. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  4557. drm_enc = &sde_enc->base;
  4558. drm_encoder_init(dev, drm_enc, &sde_encoder_funcs, drm_enc_mode, NULL);
  4559. drm_encoder_helper_add(drm_enc, &sde_encoder_helper_funcs);
  4560. if (disp_info->intf_type == DRM_MODE_CONNECTOR_DSI)
  4561. timer_setup(&sde_enc->vsync_event_timer,
  4562. sde_encoder_vsync_event_handler, 0);
  4563. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4564. phys = sde_enc->phys_encs[i];
  4565. if (!phys)
  4566. continue;
  4567. if (phys->ops.is_master && phys->ops.is_master(phys))
  4568. intf_index = phys->intf_idx - INTF_0;
  4569. }
  4570. snprintf(name, SDE_NAME_SIZE, "rsc_enc%u", drm_enc->base.id);
  4571. sde_enc->rsc_client = sde_rsc_client_create(SDE_RSC_INDEX, name,
  4572. (disp_info->display_type == SDE_CONNECTOR_PRIMARY) ?
  4573. SDE_RSC_PRIMARY_DISP_CLIENT :
  4574. SDE_RSC_EXTERNAL_DISP_CLIENT, intf_index + 1);
  4575. if (IS_ERR_OR_NULL(sde_enc->rsc_client)) {
  4576. SDE_DEBUG("sde rsc client create failed :%ld\n",
  4577. PTR_ERR(sde_enc->rsc_client));
  4578. sde_enc->rsc_client = NULL;
  4579. }
  4580. if (disp_info->curr_panel_mode == MSM_DISPLAY_CMD_MODE) {
  4581. ret = _sde_encoder_input_handler(sde_enc);
  4582. if (ret)
  4583. SDE_ERROR(
  4584. "input handler registration failed, rc = %d\n", ret);
  4585. }
  4586. mutex_init(&sde_enc->rc_lock);
  4587. kthread_init_delayed_work(&sde_enc->delayed_off_work,
  4588. sde_encoder_off_work);
  4589. sde_enc->vblank_enabled = false;
  4590. kthread_init_work(&sde_enc->vsync_event_work,
  4591. sde_encoder_vsync_event_work_handler);
  4592. kthread_init_work(&sde_enc->input_event_work,
  4593. sde_encoder_input_event_work_handler);
  4594. kthread_init_work(&sde_enc->esd_trigger_work,
  4595. sde_encoder_esd_trigger_work_handler);
  4596. memcpy(&sde_enc->disp_info, disp_info, sizeof(*disp_info));
  4597. SDE_DEBUG_ENC(sde_enc, "created\n");
  4598. return drm_enc;
  4599. fail:
  4600. SDE_ERROR("failed to create encoder\n");
  4601. if (drm_enc)
  4602. sde_encoder_destroy(drm_enc);
  4603. return ERR_PTR(ret);
  4604. }
  4605. struct drm_encoder *sde_encoder_init(
  4606. struct drm_device *dev,
  4607. struct msm_display_info *disp_info)
  4608. {
  4609. return sde_encoder_init_with_ops(dev, disp_info, NULL);
  4610. }
  4611. int sde_encoder_wait_for_event(struct drm_encoder *drm_enc,
  4612. enum msm_event_wait event)
  4613. {
  4614. int (*fn_wait)(struct sde_encoder_phys *phys_enc) = NULL;
  4615. struct sde_encoder_virt *sde_enc = NULL;
  4616. int i, ret = 0;
  4617. char atrace_buf[32];
  4618. if (!drm_enc) {
  4619. SDE_ERROR("invalid encoder\n");
  4620. return -EINVAL;
  4621. }
  4622. sde_enc = to_sde_encoder_virt(drm_enc);
  4623. SDE_DEBUG_ENC(sde_enc, "\n");
  4624. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4625. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4626. switch (event) {
  4627. case MSM_ENC_COMMIT_DONE:
  4628. fn_wait = phys->ops.wait_for_commit_done;
  4629. break;
  4630. case MSM_ENC_TX_COMPLETE:
  4631. fn_wait = phys->ops.wait_for_tx_complete;
  4632. break;
  4633. case MSM_ENC_VBLANK:
  4634. fn_wait = phys->ops.wait_for_vblank;
  4635. break;
  4636. case MSM_ENC_ACTIVE_REGION:
  4637. fn_wait = phys->ops.wait_for_active;
  4638. break;
  4639. default:
  4640. SDE_ERROR_ENC(sde_enc, "unknown wait event %d\n",
  4641. event);
  4642. return -EINVAL;
  4643. }
  4644. if (phys && fn_wait) {
  4645. snprintf(atrace_buf, sizeof(atrace_buf),
  4646. "wait_completion_event_%d", event);
  4647. SDE_ATRACE_BEGIN(atrace_buf);
  4648. ret = fn_wait(phys);
  4649. SDE_ATRACE_END(atrace_buf);
  4650. if (ret)
  4651. return ret;
  4652. }
  4653. }
  4654. return ret;
  4655. }
  4656. u32 sde_encoder_get_fps(struct drm_encoder *drm_enc)
  4657. {
  4658. struct sde_encoder_virt *sde_enc;
  4659. if (!drm_enc) {
  4660. SDE_ERROR("invalid encoder\n");
  4661. return 0;
  4662. }
  4663. sde_enc = to_sde_encoder_virt(drm_enc);
  4664. return sde_enc->mode_info.frame_rate;
  4665. }
  4666. enum sde_intf_mode sde_encoder_get_intf_mode(struct drm_encoder *encoder)
  4667. {
  4668. struct sde_encoder_virt *sde_enc = NULL;
  4669. int i;
  4670. if (!encoder) {
  4671. SDE_ERROR("invalid encoder\n");
  4672. return INTF_MODE_NONE;
  4673. }
  4674. sde_enc = to_sde_encoder_virt(encoder);
  4675. if (sde_enc->cur_master)
  4676. return sde_enc->cur_master->intf_mode;
  4677. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4678. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4679. if (phys)
  4680. return phys->intf_mode;
  4681. }
  4682. return INTF_MODE_NONE;
  4683. }
  4684. static void _sde_encoder_cache_hw_res_cont_splash(
  4685. struct drm_encoder *encoder,
  4686. struct sde_kms *sde_kms)
  4687. {
  4688. int i, idx;
  4689. struct sde_encoder_virt *sde_enc;
  4690. struct sde_encoder_phys *phys_enc;
  4691. struct sde_rm_hw_iter dsc_iter, pp_iter, ctl_iter, intf_iter;
  4692. sde_enc = to_sde_encoder_virt(encoder);
  4693. sde_rm_init_hw_iter(&pp_iter, encoder->base.id, SDE_HW_BLK_PINGPONG);
  4694. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  4695. sde_enc->hw_pp[i] = NULL;
  4696. if (!sde_rm_get_hw(&sde_kms->rm, &pp_iter))
  4697. break;
  4698. sde_enc->hw_pp[i] = (struct sde_hw_pingpong *) pp_iter.hw;
  4699. }
  4700. sde_rm_init_hw_iter(&dsc_iter, encoder->base.id, SDE_HW_BLK_DSC);
  4701. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  4702. sde_enc->hw_dsc[i] = NULL;
  4703. if (!sde_rm_get_hw(&sde_kms->rm, &dsc_iter))
  4704. break;
  4705. sde_enc->hw_dsc[i] = (struct sde_hw_dsc *) dsc_iter.hw;
  4706. }
  4707. /*
  4708. * If we have multiple phys encoders with one controller, make
  4709. * sure to populate the controller pointer in both phys encoders.
  4710. */
  4711. for (idx = 0; idx < sde_enc->num_phys_encs; idx++) {
  4712. phys_enc = sde_enc->phys_encs[idx];
  4713. phys_enc->hw_ctl = NULL;
  4714. sde_rm_init_hw_iter(&ctl_iter, encoder->base.id,
  4715. SDE_HW_BLK_CTL);
  4716. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4717. if (sde_rm_get_hw(&sde_kms->rm, &ctl_iter)) {
  4718. phys_enc->hw_ctl =
  4719. (struct sde_hw_ctl *) ctl_iter.hw;
  4720. pr_debug("HW CTL intf_idx:%d hw_ctl:[0x%pK]\n",
  4721. phys_enc->intf_idx, phys_enc->hw_ctl);
  4722. }
  4723. }
  4724. }
  4725. sde_rm_init_hw_iter(&intf_iter, encoder->base.id, SDE_HW_BLK_INTF);
  4726. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4727. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4728. phys->hw_intf = NULL;
  4729. if (!sde_rm_get_hw(&sde_kms->rm, &intf_iter))
  4730. break;
  4731. phys->hw_intf = (struct sde_hw_intf *) intf_iter.hw;
  4732. }
  4733. }
  4734. /**
  4735. * sde_encoder_update_caps_for_cont_splash - update encoder settings during
  4736. * device bootup when cont_splash is enabled
  4737. * @drm_enc: Pointer to drm encoder structure
  4738. * @splash_display: Pointer to sde_splash_display corresponding to this encoder
  4739. * @enable: boolean indicates enable or displae state of splash
  4740. * @Return: true if successful in updating the encoder structure
  4741. */
  4742. int sde_encoder_update_caps_for_cont_splash(struct drm_encoder *encoder,
  4743. struct sde_splash_display *splash_display, bool enable)
  4744. {
  4745. struct sde_encoder_virt *sde_enc;
  4746. struct msm_drm_private *priv;
  4747. struct sde_kms *sde_kms;
  4748. struct drm_connector *conn = NULL;
  4749. struct sde_connector *sde_conn = NULL;
  4750. struct sde_connector_state *sde_conn_state = NULL;
  4751. struct drm_display_mode *drm_mode = NULL;
  4752. struct sde_encoder_phys *phys_enc;
  4753. int ret = 0, i;
  4754. if (!encoder) {
  4755. SDE_ERROR("invalid drm enc\n");
  4756. return -EINVAL;
  4757. }
  4758. if (!encoder->dev || !encoder->dev->dev_private) {
  4759. SDE_ERROR("drm device invalid\n");
  4760. return -EINVAL;
  4761. }
  4762. priv = encoder->dev->dev_private;
  4763. if (!priv->kms) {
  4764. SDE_ERROR("invalid kms\n");
  4765. return -EINVAL;
  4766. }
  4767. sde_kms = to_sde_kms(priv->kms);
  4768. sde_enc = to_sde_encoder_virt(encoder);
  4769. if (!priv->num_connectors) {
  4770. SDE_ERROR_ENC(sde_enc, "No connectors registered\n");
  4771. return -EINVAL;
  4772. }
  4773. SDE_DEBUG_ENC(sde_enc,
  4774. "num of connectors: %d\n", priv->num_connectors);
  4775. SDE_DEBUG_ENC(sde_enc, "enable: %d\n", enable);
  4776. if (!enable) {
  4777. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4778. phys_enc = sde_enc->phys_encs[i];
  4779. if (phys_enc)
  4780. phys_enc->cont_splash_enabled = false;
  4781. }
  4782. return ret;
  4783. }
  4784. if (!splash_display) {
  4785. SDE_ERROR_ENC(sde_enc, "invalid splash data\n");
  4786. return -EINVAL;
  4787. }
  4788. for (i = 0; i < priv->num_connectors; i++) {
  4789. SDE_DEBUG_ENC(sde_enc, "connector id: %d\n",
  4790. priv->connectors[i]->base.id);
  4791. sde_conn = to_sde_connector(priv->connectors[i]);
  4792. if (!sde_conn->encoder) {
  4793. SDE_DEBUG_ENC(sde_enc,
  4794. "encoder not attached to connector\n");
  4795. continue;
  4796. }
  4797. if (sde_conn->encoder->base.id
  4798. == encoder->base.id) {
  4799. conn = (priv->connectors[i]);
  4800. break;
  4801. }
  4802. }
  4803. if (!conn || !conn->state) {
  4804. SDE_ERROR_ENC(sde_enc, "connector not found\n");
  4805. return -EINVAL;
  4806. }
  4807. sde_conn_state = to_sde_connector_state(conn->state);
  4808. if (!sde_conn->ops.get_mode_info) {
  4809. SDE_ERROR_ENC(sde_enc, "conn: get_mode_info ops not found\n");
  4810. return -EINVAL;
  4811. }
  4812. ret = sde_conn->ops.get_mode_info(&sde_conn->base,
  4813. &encoder->crtc->state->adjusted_mode,
  4814. &sde_conn_state->mode_info,
  4815. sde_kms->catalog->max_mixer_width,
  4816. sde_conn->display);
  4817. if (ret) {
  4818. SDE_ERROR_ENC(sde_enc,
  4819. "conn: ->get_mode_info failed. ret=%d\n", ret);
  4820. return ret;
  4821. }
  4822. ret = sde_rm_reserve(&sde_kms->rm, encoder, encoder->crtc->state,
  4823. conn->state, false);
  4824. if (ret) {
  4825. SDE_ERROR_ENC(sde_enc,
  4826. "failed to reserve hw resources, %d\n", ret);
  4827. return ret;
  4828. }
  4829. if (sde_conn->encoder) {
  4830. conn->state->best_encoder = sde_conn->encoder;
  4831. SDE_DEBUG_ENC(sde_enc,
  4832. "configured cstate->best_encoder to ID = %d\n",
  4833. conn->state->best_encoder->base.id);
  4834. } else {
  4835. SDE_ERROR_ENC(sde_enc, "No encoder mapped to connector=%d\n",
  4836. conn->base.id);
  4837. }
  4838. SDE_DEBUG_ENC(sde_enc, "connector topology = %llu\n",
  4839. sde_connector_get_topology_name(conn));
  4840. drm_mode = &encoder->crtc->state->adjusted_mode;
  4841. SDE_DEBUG_ENC(sde_enc, "hdisplay = %d, vdisplay = %d\n",
  4842. drm_mode->hdisplay, drm_mode->vdisplay);
  4843. drm_set_preferred_mode(conn, drm_mode->hdisplay, drm_mode->vdisplay);
  4844. if (encoder->bridge) {
  4845. SDE_DEBUG_ENC(sde_enc, "Bridge mapped to encoder\n");
  4846. /*
  4847. * For cont-splash use case, we update the mode
  4848. * configurations manually. This will skip the
  4849. * usually mode set call when actual frame is
  4850. * pushed from framework. The bridge needs to
  4851. * be updated with the current drm mode by
  4852. * calling the bridge mode set ops.
  4853. */
  4854. if (encoder->bridge->funcs) {
  4855. SDE_DEBUG_ENC(sde_enc, "calling mode_set\n");
  4856. encoder->bridge->funcs->mode_set(encoder->bridge,
  4857. drm_mode, drm_mode);
  4858. }
  4859. } else {
  4860. SDE_ERROR_ENC(sde_enc, "No bridge attached to encoder\n");
  4861. }
  4862. _sde_encoder_cache_hw_res_cont_splash(encoder, sde_kms);
  4863. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4864. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4865. if (!phys) {
  4866. SDE_ERROR_ENC(sde_enc,
  4867. "phys encoders not initialized\n");
  4868. return -EINVAL;
  4869. }
  4870. /* update connector for master and slave phys encoders */
  4871. phys->connector = conn;
  4872. phys->cont_splash_enabled = true;
  4873. phys->cont_splash_single_flush =
  4874. splash_display->single_flush_en;
  4875. phys->hw_pp = sde_enc->hw_pp[i];
  4876. if (phys->ops.cont_splash_mode_set)
  4877. phys->ops.cont_splash_mode_set(phys, drm_mode);
  4878. if (phys->ops.is_master && phys->ops.is_master(phys))
  4879. sde_enc->cur_master = phys;
  4880. }
  4881. return ret;
  4882. }
  4883. int sde_encoder_display_failure_notification(struct drm_encoder *enc,
  4884. bool skip_pre_kickoff)
  4885. {
  4886. struct msm_drm_thread *event_thread = NULL;
  4887. struct msm_drm_private *priv = NULL;
  4888. struct sde_encoder_virt *sde_enc = NULL;
  4889. if (!enc || !enc->dev || !enc->dev->dev_private) {
  4890. SDE_ERROR("invalid parameters\n");
  4891. return -EINVAL;
  4892. }
  4893. priv = enc->dev->dev_private;
  4894. sde_enc = to_sde_encoder_virt(enc);
  4895. if (!sde_enc->crtc || (sde_enc->crtc->index
  4896. >= ARRAY_SIZE(priv->event_thread))) {
  4897. SDE_DEBUG_ENC(sde_enc,
  4898. "invalid cached CRTC: %d or crtc index: %d\n",
  4899. sde_enc->crtc == NULL,
  4900. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  4901. return -EINVAL;
  4902. }
  4903. SDE_EVT32_VERBOSE(DRMID(enc));
  4904. event_thread = &priv->event_thread[sde_enc->crtc->index];
  4905. if (!skip_pre_kickoff) {
  4906. kthread_queue_work(&event_thread->worker,
  4907. &sde_enc->esd_trigger_work);
  4908. kthread_flush_work(&sde_enc->esd_trigger_work);
  4909. }
  4910. /**
  4911. * panel may stop generating te signal (vsync) during esd failure. rsc
  4912. * hardware may hang without vsync. Avoid rsc hang by generating the
  4913. * vsync from watchdog timer instead of panel.
  4914. */
  4915. _sde_encoder_switch_to_watchdog_vsync(enc);
  4916. if (!skip_pre_kickoff)
  4917. sde_encoder_wait_for_event(enc, MSM_ENC_TX_COMPLETE);
  4918. return 0;
  4919. }
  4920. bool sde_encoder_recovery_events_enabled(struct drm_encoder *encoder)
  4921. {
  4922. struct sde_encoder_virt *sde_enc;
  4923. if (!encoder) {
  4924. SDE_ERROR("invalid drm enc\n");
  4925. return false;
  4926. }
  4927. sde_enc = to_sde_encoder_virt(encoder);
  4928. return sde_enc->recovery_events_enabled;
  4929. }
  4930. void sde_encoder_recovery_events_handler(struct drm_encoder *encoder,
  4931. bool enabled)
  4932. {
  4933. struct sde_encoder_virt *sde_enc;
  4934. if (!encoder) {
  4935. SDE_ERROR("invalid drm enc\n");
  4936. return;
  4937. }
  4938. sde_enc = to_sde_encoder_virt(encoder);
  4939. sde_enc->recovery_events_enabled = enabled;
  4940. }