wcd938x.c 118 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "wcd938x-registers.h"
  23. #include "wcd938x.h"
  24. #include "internal.h"
  25. #define NUM_SWRS_DT_PARAMS 5
  26. #define WCD938X_VARIANT_ENTRY_SIZE 32
  27. #define WCD938X_VERSION_1_0 1
  28. #define WCD938X_VERSION_ENTRY_SIZE 32
  29. #define EAR_RX_PATH_AUX 1
  30. #define ADC_MODE_VAL_HIFI 0x01
  31. #define ADC_MODE_VAL_LO_HIF 0x02
  32. #define ADC_MODE_VAL_NORMAL 0x03
  33. #define ADC_MODE_VAL_LP 0x05
  34. #define ADC_MODE_VAL_ULP1 0x09
  35. #define ADC_MODE_VAL_ULP2 0x0B
  36. #define NUM_ATTEMPTS 5
  37. #define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
  38. #define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone"
  39. #define DAPM_MICBIAS3_STANDALONE "MIC BIAS3 Standalone"
  40. #define DAPM_MICBIAS4_STANDALONE "MIC BIAS4 Standalone"
  41. #define WCD938X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  42. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  43. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  44. SNDRV_PCM_RATE_384000)
  45. /* Fractional Rates */
  46. #define WCD938X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  47. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  48. #define WCD938X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  49. SNDRV_PCM_FMTBIT_S24_LE |\
  50. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  51. enum {
  52. CODEC_TX = 0,
  53. CODEC_RX,
  54. };
  55. enum {
  56. WCD_ADC1 = 0,
  57. WCD_ADC2,
  58. WCD_ADC3,
  59. WCD_ADC4,
  60. ALLOW_BUCK_DISABLE,
  61. HPH_COMP_DELAY,
  62. HPH_PA_DELAY,
  63. AMIC2_BCS_ENABLE,
  64. };
  65. enum {
  66. ADC_MODE_INVALID = 0,
  67. ADC_MODE_HIFI,
  68. ADC_MODE_LO_HIF,
  69. ADC_MODE_NORMAL,
  70. ADC_MODE_LP,
  71. ADC_MODE_ULP1,
  72. ADC_MODE_ULP2,
  73. };
  74. static u8 tx_mode_bit[] = {
  75. [ADC_MODE_INVALID] = 0x00,
  76. [ADC_MODE_HIFI] = 0x01,
  77. [ADC_MODE_LO_HIF] = 0x02,
  78. [ADC_MODE_NORMAL] = 0x04,
  79. [ADC_MODE_LP] = 0x08,
  80. [ADC_MODE_ULP1] = 0x10,
  81. [ADC_MODE_ULP2] = 0x20,
  82. };
  83. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  84. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  85. static int wcd938x_handle_post_irq(void *data);
  86. static int wcd938x_reset(struct device *dev);
  87. static int wcd938x_reset_low(struct device *dev);
  88. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  89. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  90. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  91. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  92. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  93. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  94. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  95. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  96. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  97. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  98. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  99. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  100. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  101. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  102. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  103. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  104. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  105. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  106. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  107. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  108. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  109. };
  110. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  111. .name = "wcd938x",
  112. .irqs = wcd938x_irqs,
  113. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  114. .num_regs = 3,
  115. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  116. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  117. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  118. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  119. .use_ack = 1,
  120. .runtime_pm = false,
  121. .handle_post_irq = wcd938x_handle_post_irq,
  122. .irq_drv_data = NULL,
  123. };
  124. static int wcd938x_handle_post_irq(void *data)
  125. {
  126. struct wcd938x_priv *wcd938x = data;
  127. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  128. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  129. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  130. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  131. wcd938x->tx_swr_dev->slave_irq_pending =
  132. ((sts1 || sts2 || sts3) ? true : false);
  133. return IRQ_HANDLED;
  134. }
  135. static int wcd938x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  136. {
  137. int ret = 0;
  138. int bank = 0;
  139. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  140. if (ret)
  141. return -EINVAL;
  142. return ((bank & 0x40) ? 1: 0);
  143. }
  144. static int wcd938x_get_clk_rate(int mode)
  145. {
  146. int rate;
  147. switch (mode) {
  148. case ADC_MODE_ULP2:
  149. rate = SWR_CLK_RATE_0P6MHZ;
  150. break;
  151. case ADC_MODE_ULP1:
  152. rate = SWR_CLK_RATE_1P2MHZ;
  153. break;
  154. case ADC_MODE_LP:
  155. rate = SWR_CLK_RATE_4P8MHZ;
  156. break;
  157. case ADC_MODE_NORMAL:
  158. case ADC_MODE_LO_HIF:
  159. case ADC_MODE_HIFI:
  160. case ADC_MODE_INVALID:
  161. default:
  162. rate = SWR_CLK_RATE_9P6MHZ;
  163. break;
  164. }
  165. return rate;
  166. }
  167. static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component,
  168. int rate, int bank)
  169. {
  170. u8 mask = (bank ? 0xF0 : 0x0F);
  171. u8 val = 0;
  172. switch (rate) {
  173. case SWR_CLK_RATE_0P6MHZ:
  174. val = (bank ? 0x60 : 0x06);
  175. break;
  176. case SWR_CLK_RATE_1P2MHZ:
  177. val = (bank ? 0x50 : 0x05);
  178. break;
  179. case SWR_CLK_RATE_2P4MHZ:
  180. val = (bank ? 0x30 : 0x03);
  181. break;
  182. case SWR_CLK_RATE_4P8MHZ:
  183. val = (bank ? 0x10 : 0x01);
  184. break;
  185. case SWR_CLK_RATE_9P6MHZ:
  186. default:
  187. val = 0x00;
  188. break;
  189. }
  190. snd_soc_component_update_bits(component,
  191. WCD938X_DIGITAL_SWR_TX_CLK_RATE,
  192. mask, val);
  193. return 0;
  194. }
  195. static int wcd938x_init_reg(struct snd_soc_component *component)
  196. {
  197. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  198. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  199. /* 1 msec delay as per HW requirement */
  200. usleep_range(1000, 1010);
  201. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  202. /* 1 msec delay as per HW requirement */
  203. usleep_range(1000, 1010);
  204. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  205. 0x10, 0x00);
  206. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  207. 0xF0, 0x80);
  208. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  209. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  210. /* 10 msec delay as per HW requirement */
  211. usleep_range(10000, 10010);
  212. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  213. snd_soc_component_update_bits(component,
  214. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  215. 0xF0, 0x00);
  216. snd_soc_component_update_bits(component,
  217. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  218. 0x1F, 0x15);
  219. snd_soc_component_update_bits(component,
  220. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  221. 0x1F, 0x15);
  222. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  223. 0xC0, 0x80);
  224. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  225. 0x02, 0x02);
  226. snd_soc_component_update_bits(component,
  227. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  228. 0xFF, 0x14);
  229. snd_soc_component_update_bits(component,
  230. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  231. 0x1F, 0x08);
  232. snd_soc_component_update_bits(component,
  233. WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
  234. snd_soc_component_update_bits(component,
  235. WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
  236. snd_soc_component_update_bits(component,
  237. WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
  238. snd_soc_component_update_bits(component,
  239. WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
  240. snd_soc_component_update_bits(component,
  241. WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
  242. snd_soc_component_update_bits(component,
  243. WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
  244. snd_soc_component_update_bits(component,
  245. WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
  246. snd_soc_component_update_bits(component,
  247. WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
  248. snd_soc_component_update_bits(component,
  249. WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
  250. snd_soc_component_update_bits(component,
  251. WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
  252. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E,
  253. ((snd_soc_component_read32(component,
  254. WCD938X_DIGITAL_EFUSE_REG_30) & 0x07) << 1));
  255. return 0;
  256. }
  257. static int wcd938x_set_port_params(struct snd_soc_component *component,
  258. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  259. u8 *ch_mask, u32 *ch_rate,
  260. u8 *port_type, u8 path)
  261. {
  262. int i, j;
  263. u8 num_ports = 0;
  264. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  265. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  266. switch (path) {
  267. case CODEC_RX:
  268. map = &wcd938x->rx_port_mapping;
  269. num_ports = wcd938x->num_rx_ports;
  270. break;
  271. case CODEC_TX:
  272. map = &wcd938x->tx_port_mapping;
  273. num_ports = wcd938x->num_tx_ports;
  274. break;
  275. default:
  276. dev_err(component->dev, "%s Invalid path selected %u\n",
  277. __func__, path);
  278. return -EINVAL;
  279. }
  280. for (i = 0; i <= num_ports; i++) {
  281. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  282. if ((*map)[i][j].slave_port_type == slv_prt_type)
  283. goto found;
  284. }
  285. }
  286. found:
  287. if (i > num_ports || j == MAX_CH_PER_PORT) {
  288. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  289. __func__, slv_prt_type);
  290. return -EINVAL;
  291. }
  292. *port_id = i;
  293. *num_ch = (*map)[i][j].num_ch;
  294. *ch_mask = (*map)[i][j].ch_mask;
  295. *ch_rate = (*map)[i][j].ch_rate;
  296. *port_type = (*map)[i][j].master_port_type;
  297. return 0;
  298. }
  299. static int wcd938x_parse_port_mapping(struct device *dev,
  300. char *prop, u8 path)
  301. {
  302. u32 *dt_array, map_size, map_length;
  303. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  304. u32 slave_port_type, master_port_type;
  305. u32 i, ch_iter = 0;
  306. int ret = 0;
  307. u8 *num_ports = NULL;
  308. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  309. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  310. switch (path) {
  311. case CODEC_RX:
  312. map = &wcd938x->rx_port_mapping;
  313. num_ports = &wcd938x->num_rx_ports;
  314. break;
  315. case CODEC_TX:
  316. map = &wcd938x->tx_port_mapping;
  317. num_ports = &wcd938x->num_tx_ports;
  318. break;
  319. default:
  320. dev_err(dev, "%s Invalid path selected %u\n",
  321. __func__, path);
  322. return -EINVAL;
  323. }
  324. if (!of_find_property(dev->of_node, prop,
  325. &map_size)) {
  326. dev_err(dev, "missing port mapping prop %s\n", prop);
  327. ret = -EINVAL;
  328. goto err_port_map;
  329. }
  330. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  331. dt_array = kzalloc(map_size, GFP_KERNEL);
  332. if (!dt_array) {
  333. ret = -ENOMEM;
  334. goto err_alloc;
  335. }
  336. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  337. NUM_SWRS_DT_PARAMS * map_length);
  338. if (ret) {
  339. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  340. __func__, prop);
  341. goto err_pdata_fail;
  342. }
  343. for (i = 0; i < map_length; i++) {
  344. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  345. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  346. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  347. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  348. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  349. if (port_num != old_port_num)
  350. ch_iter = 0;
  351. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  352. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  353. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  354. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  355. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  356. old_port_num = port_num;
  357. }
  358. *num_ports = port_num;
  359. kfree(dt_array);
  360. return 0;
  361. err_pdata_fail:
  362. kfree(dt_array);
  363. err_alloc:
  364. err_port_map:
  365. return ret;
  366. }
  367. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  368. u8 slv_port_type, int clk_rate,
  369. u8 enable)
  370. {
  371. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  372. u8 port_id, num_ch, ch_mask;
  373. u8 ch_type = 0;
  374. u32 ch_rate;
  375. int slave_ch_idx;
  376. u8 num_port = 1;
  377. int ret = 0;
  378. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  379. &num_ch, &ch_mask, &ch_rate,
  380. &ch_type, CODEC_TX);
  381. if (ret)
  382. return ret;
  383. if (clk_rate)
  384. ch_rate = clk_rate;
  385. slave_ch_idx = wcd938x_slave_get_slave_ch_val(slv_port_type);
  386. if (slave_ch_idx != -EINVAL)
  387. ch_type = wcd938x->tx_master_ch_map[slave_ch_idx];
  388. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  389. __func__, slave_ch_idx, ch_type);
  390. if (enable)
  391. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  392. num_port, &ch_mask, &ch_rate,
  393. &num_ch, &ch_type);
  394. else
  395. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  396. num_port, &ch_mask, &ch_type);
  397. return ret;
  398. }
  399. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  400. u8 slv_port_type, u8 enable)
  401. {
  402. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  403. u8 port_id, num_ch, ch_mask, port_type;
  404. u32 ch_rate;
  405. u8 num_port = 1;
  406. int ret = 0;
  407. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  408. &num_ch, &ch_mask, &ch_rate,
  409. &port_type, CODEC_RX);
  410. if (ret)
  411. return ret;
  412. if (enable)
  413. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  414. num_port, &ch_mask, &ch_rate,
  415. &num_ch, &port_type);
  416. else
  417. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  418. num_port, &ch_mask, &port_type);
  419. return ret;
  420. }
  421. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  422. {
  423. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  424. if (wcd938x->rx_clk_cnt == 0) {
  425. snd_soc_component_update_bits(component,
  426. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  427. snd_soc_component_update_bits(component,
  428. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  429. snd_soc_component_update_bits(component,
  430. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  431. snd_soc_component_update_bits(component,
  432. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  433. snd_soc_component_update_bits(component,
  434. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  435. snd_soc_component_update_bits(component,
  436. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  437. snd_soc_component_update_bits(component,
  438. WCD938X_AUX_AUXPA, 0x10, 0x10);
  439. }
  440. wcd938x->rx_clk_cnt++;
  441. return 0;
  442. }
  443. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  444. {
  445. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  446. wcd938x->rx_clk_cnt--;
  447. if (wcd938x->rx_clk_cnt == 0) {
  448. snd_soc_component_update_bits(component,
  449. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  450. snd_soc_component_update_bits(component,
  451. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  452. snd_soc_component_update_bits(component,
  453. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  454. snd_soc_component_update_bits(component,
  455. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  456. snd_soc_component_update_bits(component,
  457. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  458. }
  459. return 0;
  460. }
  461. /*
  462. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  463. * @component: handle to snd_soc_component *
  464. *
  465. * return wcd938x_mbhc handle or error code in case of failure
  466. */
  467. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  468. {
  469. struct wcd938x_priv *wcd938x;
  470. if (!component) {
  471. pr_err("%s: Invalid params, NULL component\n", __func__);
  472. return NULL;
  473. }
  474. wcd938x = snd_soc_component_get_drvdata(component);
  475. if (!wcd938x) {
  476. pr_err("%s: wcd938x is NULL\n", __func__);
  477. return NULL;
  478. }
  479. return wcd938x->mbhc;
  480. }
  481. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  482. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  483. struct snd_kcontrol *kcontrol,
  484. int event)
  485. {
  486. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  487. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  488. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  489. w->name, event);
  490. switch (event) {
  491. case SND_SOC_DAPM_PRE_PMU:
  492. wcd938x_rx_clk_enable(component);
  493. snd_soc_component_update_bits(component,
  494. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  495. snd_soc_component_update_bits(component,
  496. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  497. snd_soc_component_update_bits(component,
  498. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  499. break;
  500. case SND_SOC_DAPM_POST_PMU:
  501. snd_soc_component_update_bits(component,
  502. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  503. if (wcd938x->comp1_enable) {
  504. snd_soc_component_update_bits(component,
  505. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  506. /* 5msec compander delay as per HW requirement */
  507. if (!wcd938x->comp2_enable ||
  508. (snd_soc_component_read32(component,
  509. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  510. usleep_range(5000, 5010);
  511. snd_soc_component_update_bits(component,
  512. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  513. } else {
  514. snd_soc_component_update_bits(component,
  515. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  516. 0x02, 0x00);
  517. snd_soc_component_update_bits(component,
  518. WCD938X_HPH_L_EN, 0x20, 0x20);
  519. }
  520. break;
  521. case SND_SOC_DAPM_POST_PMD:
  522. snd_soc_component_update_bits(component,
  523. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  524. 0x0F, 0x01);
  525. break;
  526. }
  527. return 0;
  528. }
  529. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  530. struct snd_kcontrol *kcontrol,
  531. int event)
  532. {
  533. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  534. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  535. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  536. w->name, event);
  537. switch (event) {
  538. case SND_SOC_DAPM_PRE_PMU:
  539. wcd938x_rx_clk_enable(component);
  540. snd_soc_component_update_bits(component,
  541. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  542. snd_soc_component_update_bits(component,
  543. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  544. snd_soc_component_update_bits(component,
  545. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  546. break;
  547. case SND_SOC_DAPM_POST_PMU:
  548. snd_soc_component_update_bits(component,
  549. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  550. if (wcd938x->comp2_enable) {
  551. snd_soc_component_update_bits(component,
  552. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  553. /* 5msec compander delay as per HW requirement */
  554. if (!wcd938x->comp1_enable ||
  555. (snd_soc_component_read32(component,
  556. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  557. usleep_range(5000, 5010);
  558. snd_soc_component_update_bits(component,
  559. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  560. } else {
  561. snd_soc_component_update_bits(component,
  562. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  563. 0x01, 0x00);
  564. snd_soc_component_update_bits(component,
  565. WCD938X_HPH_R_EN, 0x20, 0x20);
  566. }
  567. break;
  568. case SND_SOC_DAPM_POST_PMD:
  569. snd_soc_component_update_bits(component,
  570. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  571. 0x0F, 0x01);
  572. break;
  573. }
  574. return 0;
  575. }
  576. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  577. struct snd_kcontrol *kcontrol,
  578. int event)
  579. {
  580. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  581. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  582. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  583. w->name, event);
  584. switch (event) {
  585. case SND_SOC_DAPM_PRE_PMU:
  586. wcd938x_rx_clk_enable(component);
  587. wcd938x->ear_rx_path =
  588. snd_soc_component_read32(
  589. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  590. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  591. snd_soc_component_update_bits(component,
  592. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x00);
  593. snd_soc_component_update_bits(component,
  594. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  595. snd_soc_component_update_bits(component,
  596. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  597. snd_soc_component_update_bits(component,
  598. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  599. } else {
  600. snd_soc_component_update_bits(component,
  601. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  602. snd_soc_component_update_bits(component,
  603. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  604. snd_soc_component_update_bits(component,
  605. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  606. }
  607. /* 5 msec delay as per HW requirement */
  608. usleep_range(5000, 5010);
  609. if (wcd938x->flyback_cur_det_disable == 0)
  610. snd_soc_component_update_bits(component,
  611. WCD938X_FLYBACK_EN,
  612. 0x04, 0x00);
  613. wcd938x->flyback_cur_det_disable++;
  614. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  615. WCD_CLSH_EVENT_PRE_DAC,
  616. WCD_CLSH_STATE_EAR,
  617. wcd938x->hph_mode);
  618. break;
  619. case SND_SOC_DAPM_POST_PMD:
  620. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  621. snd_soc_component_update_bits(component,
  622. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x00);
  623. snd_soc_component_update_bits(component,
  624. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  625. } else {
  626. snd_soc_component_update_bits(component,
  627. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x00);
  628. snd_soc_component_update_bits(component,
  629. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x00);
  630. snd_soc_component_update_bits(component,
  631. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x00);
  632. }
  633. snd_soc_component_update_bits(component,
  634. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  635. snd_soc_component_update_bits(component,
  636. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x80);
  637. break;
  638. };
  639. return 0;
  640. }
  641. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  642. struct snd_kcontrol *kcontrol,
  643. int event)
  644. {
  645. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  646. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  647. int ret = 0;
  648. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  649. w->name, event);
  650. switch (event) {
  651. case SND_SOC_DAPM_PRE_PMU:
  652. wcd938x_rx_clk_enable(component);
  653. snd_soc_component_update_bits(component,
  654. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  655. snd_soc_component_update_bits(component,
  656. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  657. snd_soc_component_update_bits(component,
  658. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  659. if (wcd938x->flyback_cur_det_disable == 0)
  660. snd_soc_component_update_bits(component,
  661. WCD938X_FLYBACK_EN,
  662. 0x04, 0x00);
  663. wcd938x->flyback_cur_det_disable++;
  664. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  665. WCD_CLSH_EVENT_PRE_DAC,
  666. WCD_CLSH_STATE_AUX,
  667. wcd938x->hph_mode);
  668. break;
  669. case SND_SOC_DAPM_POST_PMD:
  670. snd_soc_component_update_bits(component,
  671. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  672. break;
  673. };
  674. return ret;
  675. }
  676. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  677. struct snd_kcontrol *kcontrol,
  678. int event)
  679. {
  680. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  681. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  682. int ret = 0;
  683. int hph_mode = wcd938x->hph_mode;
  684. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  685. w->name, event);
  686. switch (event) {
  687. case SND_SOC_DAPM_PRE_PMU:
  688. if (wcd938x->ldoh)
  689. snd_soc_component_update_bits(component,
  690. WCD938X_LDOH_MODE,
  691. 0x80, 0x80);
  692. if (wcd938x->update_wcd_event)
  693. wcd938x->update_wcd_event(wcd938x->handle,
  694. WCD_BOLERO_EVT_RX_MUTE,
  695. (WCD_RX2 << 0x10 | 0x1));
  696. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  697. wcd938x->rx_swr_dev->dev_num,
  698. true);
  699. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  700. WCD_CLSH_EVENT_PRE_DAC,
  701. WCD_CLSH_STATE_HPHR,
  702. hph_mode);
  703. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  704. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  705. hph_mode == CLS_H_ULP) {
  706. snd_soc_component_update_bits(component,
  707. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  708. }
  709. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  710. 0x10, 0x10);
  711. wcd_clsh_set_hph_mode(component, hph_mode);
  712. /* 100 usec delay as per HW requirement */
  713. usleep_range(100, 110);
  714. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  715. snd_soc_component_update_bits(component,
  716. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  717. break;
  718. case SND_SOC_DAPM_POST_PMU:
  719. /*
  720. * 7ms sleep is required if compander is enabled as per
  721. * HW requirement. If compander is disabled, then
  722. * 20ms delay is required.
  723. */
  724. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  725. if (!wcd938x->comp2_enable)
  726. usleep_range(20000, 20100);
  727. else
  728. usleep_range(7000, 7100);
  729. if (hph_mode == CLS_H_LP ||
  730. hph_mode == CLS_H_LOHIFI ||
  731. hph_mode == CLS_H_ULP)
  732. snd_soc_component_update_bits(component,
  733. WCD938X_HPH_REFBUFF_LP_CTL, 0x01,
  734. 0x00);
  735. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  736. }
  737. snd_soc_component_update_bits(component,
  738. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  739. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  740. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  741. snd_soc_component_update_bits(component,
  742. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  743. if (wcd938x->update_wcd_event)
  744. wcd938x->update_wcd_event(wcd938x->handle,
  745. WCD_BOLERO_EVT_RX_MUTE,
  746. (WCD_RX2 << 0x10));
  747. wcd_enable_irq(&wcd938x->irq_info,
  748. WCD938X_IRQ_HPHR_PDM_WD_INT);
  749. break;
  750. case SND_SOC_DAPM_PRE_PMD:
  751. if (wcd938x->update_wcd_event)
  752. wcd938x->update_wcd_event(wcd938x->handle,
  753. WCD_BOLERO_EVT_RX_MUTE,
  754. (WCD_RX2 << 0x10 | 0x1));
  755. wcd_disable_irq(&wcd938x->irq_info,
  756. WCD938X_IRQ_HPHR_PDM_WD_INT);
  757. if (wcd938x->update_wcd_event && wcd938x->comp2_enable)
  758. wcd938x->update_wcd_event(wcd938x->handle,
  759. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  760. (WCD_RX2 << 0x10));
  761. /*
  762. * 7ms sleep is required if compander is enabled as per
  763. * HW requirement. If compander is disabled, then
  764. * 20ms delay is required.
  765. */
  766. if (!wcd938x->comp2_enable)
  767. usleep_range(20000, 20100);
  768. else
  769. usleep_range(7000, 7100);
  770. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  771. 0x40, 0x00);
  772. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  773. WCD_EVENT_PRE_HPHR_PA_OFF,
  774. &wcd938x->mbhc->wcd_mbhc);
  775. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  776. break;
  777. case SND_SOC_DAPM_POST_PMD:
  778. /*
  779. * 7ms sleep is required if compander is enabled as per
  780. * HW requirement. If compander is disabled, then
  781. * 20ms delay is required.
  782. */
  783. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  784. if (!wcd938x->comp2_enable)
  785. usleep_range(20000, 20100);
  786. else
  787. usleep_range(7000, 7100);
  788. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  789. }
  790. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  791. WCD_EVENT_POST_HPHR_PA_OFF,
  792. &wcd938x->mbhc->wcd_mbhc);
  793. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  794. 0x10, 0x00);
  795. snd_soc_component_update_bits(component,
  796. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  797. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  798. WCD_CLSH_EVENT_POST_PA,
  799. WCD_CLSH_STATE_HPHR,
  800. hph_mode);
  801. if (wcd938x->ldoh)
  802. snd_soc_component_update_bits(component,
  803. WCD938X_LDOH_MODE,
  804. 0x80, 0x00);
  805. break;
  806. };
  807. return ret;
  808. }
  809. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  810. struct snd_kcontrol *kcontrol,
  811. int event)
  812. {
  813. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  814. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  815. int ret = 0;
  816. int hph_mode = wcd938x->hph_mode;
  817. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  818. w->name, event);
  819. switch (event) {
  820. case SND_SOC_DAPM_PRE_PMU:
  821. if (wcd938x->ldoh)
  822. snd_soc_component_update_bits(component,
  823. WCD938X_LDOH_MODE,
  824. 0x80, 0x80);
  825. if (wcd938x->update_wcd_event)
  826. wcd938x->update_wcd_event(wcd938x->handle,
  827. WCD_BOLERO_EVT_RX_MUTE,
  828. (WCD_RX1 << 0x10 | 0x01));
  829. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  830. wcd938x->rx_swr_dev->dev_num,
  831. true);
  832. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  833. WCD_CLSH_EVENT_PRE_DAC,
  834. WCD_CLSH_STATE_HPHL,
  835. hph_mode);
  836. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  837. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  838. hph_mode == CLS_H_ULP) {
  839. snd_soc_component_update_bits(component,
  840. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  841. }
  842. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  843. 0x20, 0x20);
  844. wcd_clsh_set_hph_mode(component, hph_mode);
  845. /* 100 usec delay as per HW requirement */
  846. usleep_range(100, 110);
  847. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  848. snd_soc_component_update_bits(component,
  849. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  850. break;
  851. case SND_SOC_DAPM_POST_PMU:
  852. /*
  853. * 7ms sleep is required if compander is enabled as per
  854. * HW requirement. If compander is disabled, then
  855. * 20ms delay is required.
  856. */
  857. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  858. if (!wcd938x->comp1_enable)
  859. usleep_range(20000, 20100);
  860. else
  861. usleep_range(7000, 7100);
  862. if (hph_mode == CLS_H_LP ||
  863. hph_mode == CLS_H_LOHIFI ||
  864. hph_mode == CLS_H_ULP)
  865. snd_soc_component_update_bits(component,
  866. WCD938X_HPH_REFBUFF_LP_CTL,
  867. 0x01, 0x00);
  868. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  869. }
  870. snd_soc_component_update_bits(component,
  871. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  872. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  873. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  874. snd_soc_component_update_bits(component,
  875. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  876. if (wcd938x->update_wcd_event)
  877. wcd938x->update_wcd_event(wcd938x->handle,
  878. WCD_BOLERO_EVT_RX_MUTE,
  879. (WCD_RX1 << 0x10));
  880. wcd_enable_irq(&wcd938x->irq_info,
  881. WCD938X_IRQ_HPHL_PDM_WD_INT);
  882. break;
  883. case SND_SOC_DAPM_PRE_PMD:
  884. if (wcd938x->update_wcd_event)
  885. wcd938x->update_wcd_event(wcd938x->handle,
  886. WCD_BOLERO_EVT_RX_MUTE,
  887. (WCD_RX1 << 0x10 | 0x1));
  888. wcd_disable_irq(&wcd938x->irq_info,
  889. WCD938X_IRQ_HPHL_PDM_WD_INT);
  890. if (wcd938x->update_wcd_event && wcd938x->comp1_enable)
  891. wcd938x->update_wcd_event(wcd938x->handle,
  892. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  893. (WCD_RX1 << 0x10));
  894. /*
  895. * 7ms sleep is required if compander is enabled as per
  896. * HW requirement. If compander is disabled, then
  897. * 20ms delay is required.
  898. */
  899. if (!wcd938x->comp1_enable)
  900. usleep_range(20000, 20100);
  901. else
  902. usleep_range(7000, 7100);
  903. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  904. 0x80, 0x00);
  905. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  906. WCD_EVENT_PRE_HPHL_PA_OFF,
  907. &wcd938x->mbhc->wcd_mbhc);
  908. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  909. break;
  910. case SND_SOC_DAPM_POST_PMD:
  911. /*
  912. * 7ms sleep is required if compander is enabled as per
  913. * HW requirement. If compander is disabled, then
  914. * 20ms delay is required.
  915. */
  916. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  917. if (!wcd938x->comp1_enable)
  918. usleep_range(21000, 21100);
  919. else
  920. usleep_range(7000, 7100);
  921. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  922. }
  923. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  924. WCD_EVENT_POST_HPHL_PA_OFF,
  925. &wcd938x->mbhc->wcd_mbhc);
  926. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  927. 0x20, 0x00);
  928. snd_soc_component_update_bits(component,
  929. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  930. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  931. WCD_CLSH_EVENT_POST_PA,
  932. WCD_CLSH_STATE_HPHL,
  933. hph_mode);
  934. if (wcd938x->ldoh)
  935. snd_soc_component_update_bits(component,
  936. WCD938X_LDOH_MODE,
  937. 0x80, 0x00);
  938. break;
  939. };
  940. return ret;
  941. }
  942. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  943. struct snd_kcontrol *kcontrol,
  944. int event)
  945. {
  946. struct snd_soc_component *component =
  947. snd_soc_dapm_to_component(w->dapm);
  948. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  949. int hph_mode = wcd938x->hph_mode;
  950. int ret = 0;
  951. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  952. w->name, event);
  953. switch (event) {
  954. case SND_SOC_DAPM_PRE_PMU:
  955. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  956. wcd938x->rx_swr_dev->dev_num,
  957. true);
  958. snd_soc_component_update_bits(component,
  959. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  960. break;
  961. case SND_SOC_DAPM_POST_PMU:
  962. /* 1 msec delay as per HW requirement */
  963. usleep_range(1000, 1010);
  964. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  965. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  966. snd_soc_component_update_bits(component,
  967. WCD938X_ANA_RX_SUPPLIES,
  968. 0x02, 0x02);
  969. if (wcd938x->update_wcd_event)
  970. wcd938x->update_wcd_event(wcd938x->handle,
  971. WCD_BOLERO_EVT_RX_MUTE,
  972. (WCD_RX3 << 0x10));
  973. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  974. break;
  975. case SND_SOC_DAPM_PRE_PMD:
  976. wcd_disable_irq(&wcd938x->irq_info,
  977. WCD938X_IRQ_AUX_PDM_WD_INT);
  978. if (wcd938x->update_wcd_event)
  979. wcd938x->update_wcd_event(wcd938x->handle,
  980. WCD_BOLERO_EVT_RX_MUTE,
  981. (WCD_RX3 << 0x10 | 0x1));
  982. break;
  983. case SND_SOC_DAPM_POST_PMD:
  984. /* 1 msec delay as per HW requirement */
  985. usleep_range(1000, 1010);
  986. snd_soc_component_update_bits(component,
  987. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  988. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  989. WCD_CLSH_EVENT_POST_PA,
  990. WCD_CLSH_STATE_AUX,
  991. hph_mode);
  992. wcd938x->flyback_cur_det_disable--;
  993. if (wcd938x->flyback_cur_det_disable == 0)
  994. snd_soc_component_update_bits(component,
  995. WCD938X_FLYBACK_EN,
  996. 0x04, 0x04);
  997. break;
  998. };
  999. return ret;
  1000. }
  1001. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1002. struct snd_kcontrol *kcontrol,
  1003. int event)
  1004. {
  1005. struct snd_soc_component *component =
  1006. snd_soc_dapm_to_component(w->dapm);
  1007. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1008. int hph_mode = wcd938x->hph_mode;
  1009. int ret = 0;
  1010. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1011. w->name, event);
  1012. switch (event) {
  1013. case SND_SOC_DAPM_PRE_PMU:
  1014. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  1015. wcd938x->rx_swr_dev->dev_num,
  1016. true);
  1017. /*
  1018. * Enable watchdog interrupt for HPHL or AUX
  1019. * depending on mux value
  1020. */
  1021. wcd938x->ear_rx_path =
  1022. snd_soc_component_read32(
  1023. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  1024. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1025. snd_soc_component_update_bits(component,
  1026. WCD938X_DIGITAL_PDM_WD_CTL2,
  1027. 0x05, 0x05);
  1028. else
  1029. snd_soc_component_update_bits(component,
  1030. WCD938X_DIGITAL_PDM_WD_CTL0,
  1031. 0x17, 0x13);
  1032. if (!wcd938x->comp1_enable)
  1033. snd_soc_component_update_bits(component,
  1034. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  1035. break;
  1036. case SND_SOC_DAPM_POST_PMU:
  1037. /* 6 msec delay as per HW requirement */
  1038. usleep_range(6000, 6010);
  1039. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1040. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1041. snd_soc_component_update_bits(component,
  1042. WCD938X_ANA_RX_SUPPLIES,
  1043. 0x02, 0x02);
  1044. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1045. if (wcd938x->update_wcd_event)
  1046. wcd938x->update_wcd_event(wcd938x->handle,
  1047. WCD_BOLERO_EVT_RX_MUTE,
  1048. (WCD_RX3 << 0x10));
  1049. wcd_enable_irq(&wcd938x->irq_info,
  1050. WCD938X_IRQ_AUX_PDM_WD_INT);
  1051. } else {
  1052. if (wcd938x->update_wcd_event)
  1053. wcd938x->update_wcd_event(wcd938x->handle,
  1054. WCD_BOLERO_EVT_RX_MUTE,
  1055. (WCD_RX1 << 0x10));
  1056. wcd_enable_irq(&wcd938x->irq_info,
  1057. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1058. }
  1059. break;
  1060. case SND_SOC_DAPM_PRE_PMD:
  1061. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1062. wcd_disable_irq(&wcd938x->irq_info,
  1063. WCD938X_IRQ_AUX_PDM_WD_INT);
  1064. if (wcd938x->update_wcd_event)
  1065. wcd938x->update_wcd_event(wcd938x->handle,
  1066. WCD_BOLERO_EVT_RX_MUTE,
  1067. (WCD_RX3 << 0x10 | 0x1));
  1068. } else {
  1069. wcd_disable_irq(&wcd938x->irq_info,
  1070. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1071. if (wcd938x->update_wcd_event)
  1072. wcd938x->update_wcd_event(wcd938x->handle,
  1073. WCD_BOLERO_EVT_RX_MUTE,
  1074. (WCD_RX1 << 0x10 | 0x1));
  1075. }
  1076. break;
  1077. case SND_SOC_DAPM_POST_PMD:
  1078. if (!wcd938x->comp1_enable)
  1079. snd_soc_component_update_bits(component,
  1080. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  1081. /* 7 msec delay as per HW requirement */
  1082. usleep_range(7000, 7010);
  1083. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1084. snd_soc_component_update_bits(component,
  1085. WCD938X_DIGITAL_PDM_WD_CTL2,
  1086. 0x05, 0x00);
  1087. else
  1088. snd_soc_component_update_bits(component,
  1089. WCD938X_DIGITAL_PDM_WD_CTL0,
  1090. 0x17, 0x00);
  1091. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1092. WCD_CLSH_EVENT_POST_PA,
  1093. WCD_CLSH_STATE_EAR,
  1094. hph_mode);
  1095. wcd938x->flyback_cur_det_disable--;
  1096. if (wcd938x->flyback_cur_det_disable == 0)
  1097. snd_soc_component_update_bits(component,
  1098. WCD938X_FLYBACK_EN,
  1099. 0x04, 0x04);
  1100. break;
  1101. };
  1102. return ret;
  1103. }
  1104. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  1105. struct snd_kcontrol *kcontrol,
  1106. int event)
  1107. {
  1108. struct snd_soc_component *component =
  1109. snd_soc_dapm_to_component(w->dapm);
  1110. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1111. int mode = wcd938x->hph_mode;
  1112. int ret = 0;
  1113. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1114. w->name, event);
  1115. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1116. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1117. wcd938x_rx_connect_port(component, CLSH,
  1118. SND_SOC_DAPM_EVENT_ON(event));
  1119. }
  1120. if (SND_SOC_DAPM_EVENT_OFF(event))
  1121. ret = swr_slvdev_datapath_control(
  1122. wcd938x->rx_swr_dev,
  1123. wcd938x->rx_swr_dev->dev_num,
  1124. false);
  1125. return ret;
  1126. }
  1127. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  1128. struct snd_kcontrol *kcontrol,
  1129. int event)
  1130. {
  1131. struct snd_soc_component *component =
  1132. snd_soc_dapm_to_component(w->dapm);
  1133. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1134. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1135. w->name, event);
  1136. switch (event) {
  1137. case SND_SOC_DAPM_PRE_PMU:
  1138. wcd938x_rx_connect_port(component, HPH_L, true);
  1139. if (wcd938x->comp1_enable)
  1140. wcd938x_rx_connect_port(component, COMP_L, true);
  1141. break;
  1142. case SND_SOC_DAPM_POST_PMD:
  1143. wcd938x_rx_connect_port(component, HPH_L, false);
  1144. if (wcd938x->comp1_enable)
  1145. wcd938x_rx_connect_port(component, COMP_L, false);
  1146. wcd938x_rx_clk_disable(component);
  1147. snd_soc_component_update_bits(component,
  1148. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1149. 0x01, 0x00);
  1150. break;
  1151. };
  1152. return 0;
  1153. }
  1154. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  1155. struct snd_kcontrol *kcontrol, int event)
  1156. {
  1157. struct snd_soc_component *component =
  1158. snd_soc_dapm_to_component(w->dapm);
  1159. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1160. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1161. w->name, event);
  1162. switch (event) {
  1163. case SND_SOC_DAPM_PRE_PMU:
  1164. wcd938x_rx_connect_port(component, HPH_R, true);
  1165. if (wcd938x->comp2_enable)
  1166. wcd938x_rx_connect_port(component, COMP_R, true);
  1167. break;
  1168. case SND_SOC_DAPM_POST_PMD:
  1169. wcd938x_rx_connect_port(component, HPH_R, false);
  1170. if (wcd938x->comp2_enable)
  1171. wcd938x_rx_connect_port(component, COMP_R, false);
  1172. wcd938x_rx_clk_disable(component);
  1173. snd_soc_component_update_bits(component,
  1174. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1175. 0x02, 0x00);
  1176. break;
  1177. };
  1178. return 0;
  1179. }
  1180. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  1181. struct snd_kcontrol *kcontrol,
  1182. int event)
  1183. {
  1184. struct snd_soc_component *component =
  1185. snd_soc_dapm_to_component(w->dapm);
  1186. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1187. w->name, event);
  1188. switch (event) {
  1189. case SND_SOC_DAPM_PRE_PMU:
  1190. wcd938x_rx_connect_port(component, LO, true);
  1191. break;
  1192. case SND_SOC_DAPM_POST_PMD:
  1193. wcd938x_rx_connect_port(component, LO, false);
  1194. /* 6 msec delay as per HW requirement */
  1195. usleep_range(6000, 6010);
  1196. wcd938x_rx_clk_disable(component);
  1197. snd_soc_component_update_bits(component,
  1198. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1199. break;
  1200. }
  1201. return 0;
  1202. }
  1203. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1204. struct snd_kcontrol *kcontrol,
  1205. int event)
  1206. {
  1207. struct snd_soc_component *component =
  1208. snd_soc_dapm_to_component(w->dapm);
  1209. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1210. u16 dmic_clk_reg, dmic_clk_en_reg;
  1211. s32 *dmic_clk_cnt;
  1212. u8 dmic_ctl_shift = 0;
  1213. u8 dmic_clk_shift = 0;
  1214. u8 dmic_clk_mask = 0;
  1215. u16 dmic2_left_en = 0;
  1216. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1217. w->name, event);
  1218. switch (w->shift) {
  1219. case 0:
  1220. case 1:
  1221. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  1222. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1223. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  1224. dmic_clk_mask = 0x0F;
  1225. dmic_clk_shift = 0x00;
  1226. dmic_ctl_shift = 0x00;
  1227. break;
  1228. case 2:
  1229. dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1230. case 3:
  1231. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  1232. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1233. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1234. dmic_clk_mask = 0xF0;
  1235. dmic_clk_shift = 0x04;
  1236. dmic_ctl_shift = 0x01;
  1237. break;
  1238. case 4:
  1239. case 5:
  1240. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  1241. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1242. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  1243. dmic_clk_mask = 0x0F;
  1244. dmic_clk_shift = 0x00;
  1245. dmic_ctl_shift = 0x02;
  1246. break;
  1247. case 6:
  1248. case 7:
  1249. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  1250. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1251. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  1252. dmic_clk_mask = 0xF0;
  1253. dmic_clk_shift = 0x04;
  1254. dmic_ctl_shift = 0x03;
  1255. break;
  1256. default:
  1257. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1258. __func__);
  1259. return -EINVAL;
  1260. };
  1261. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1262. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1263. switch (event) {
  1264. case SND_SOC_DAPM_PRE_PMU:
  1265. snd_soc_component_update_bits(component,
  1266. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1267. (0x01 << dmic_ctl_shift), 0x00);
  1268. /* 250us sleep as per HW requirement */
  1269. usleep_range(250, 260);
  1270. if (dmic2_left_en)
  1271. snd_soc_component_update_bits(component,
  1272. dmic2_left_en, 0x80, 0x80);
  1273. /* Setting DMIC clock rate to 2.4MHz */
  1274. snd_soc_component_update_bits(component,
  1275. dmic_clk_reg, dmic_clk_mask,
  1276. (0x03 << dmic_clk_shift));
  1277. snd_soc_component_update_bits(component,
  1278. dmic_clk_en_reg, 0x08, 0x08);
  1279. /* enable clock scaling */
  1280. snd_soc_component_update_bits(component,
  1281. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  1282. wcd938x_tx_connect_port(component, DMIC0 + (w->shift),
  1283. SWR_CLK_RATE_2P4MHZ, true);
  1284. break;
  1285. case SND_SOC_DAPM_POST_PMD:
  1286. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), 0,
  1287. false);
  1288. snd_soc_component_update_bits(component,
  1289. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1290. (0x01 << dmic_ctl_shift),
  1291. (0x01 << dmic_ctl_shift));
  1292. if (dmic2_left_en)
  1293. snd_soc_component_update_bits(component,
  1294. dmic2_left_en, 0x80, 0x00);
  1295. snd_soc_component_update_bits(component,
  1296. dmic_clk_en_reg, 0x08, 0x00);
  1297. break;
  1298. };
  1299. return 0;
  1300. }
  1301. /*
  1302. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1303. * @micb_mv: micbias in mv
  1304. *
  1305. * return register value converted
  1306. */
  1307. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1308. {
  1309. /* min micbias voltage is 1V and maximum is 2.85V */
  1310. if (micb_mv < 1000 || micb_mv > 2850) {
  1311. pr_err("%s: unsupported micbias voltage\n", __func__);
  1312. return -EINVAL;
  1313. }
  1314. return (micb_mv - 1000) / 50;
  1315. }
  1316. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1317. /*
  1318. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1319. * @component: handle to snd_soc_component *
  1320. * @req_volt: micbias voltage to be set
  1321. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1322. *
  1323. * return 0 if adjustment is success or error code in case of failure
  1324. */
  1325. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1326. int req_volt, int micb_num)
  1327. {
  1328. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1329. int cur_vout_ctl, req_vout_ctl;
  1330. int micb_reg, micb_val, micb_en;
  1331. int ret = 0;
  1332. switch (micb_num) {
  1333. case MIC_BIAS_1:
  1334. micb_reg = WCD938X_ANA_MICB1;
  1335. break;
  1336. case MIC_BIAS_2:
  1337. micb_reg = WCD938X_ANA_MICB2;
  1338. break;
  1339. case MIC_BIAS_3:
  1340. micb_reg = WCD938X_ANA_MICB3;
  1341. break;
  1342. case MIC_BIAS_4:
  1343. micb_reg = WCD938X_ANA_MICB4;
  1344. break;
  1345. default:
  1346. return -EINVAL;
  1347. }
  1348. mutex_lock(&wcd938x->micb_lock);
  1349. /*
  1350. * If requested micbias voltage is same as current micbias
  1351. * voltage, then just return. Otherwise, adjust voltage as
  1352. * per requested value. If micbias is already enabled, then
  1353. * to avoid slow micbias ramp-up or down enable pull-up
  1354. * momentarily, change the micbias value and then re-enable
  1355. * micbias.
  1356. */
  1357. micb_val = snd_soc_component_read32(component, micb_reg);
  1358. micb_en = (micb_val & 0xC0) >> 6;
  1359. cur_vout_ctl = micb_val & 0x3F;
  1360. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1361. if (req_vout_ctl < 0) {
  1362. ret = -EINVAL;
  1363. goto exit;
  1364. }
  1365. if (cur_vout_ctl == req_vout_ctl) {
  1366. ret = 0;
  1367. goto exit;
  1368. }
  1369. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1370. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1371. req_volt, micb_en);
  1372. if (micb_en == 0x1)
  1373. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1374. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1375. if (micb_en == 0x1) {
  1376. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1377. /*
  1378. * Add 2ms delay as per HW requirement after enabling
  1379. * micbias
  1380. */
  1381. usleep_range(2000, 2100);
  1382. }
  1383. exit:
  1384. mutex_unlock(&wcd938x->micb_lock);
  1385. return ret;
  1386. }
  1387. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1388. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1389. struct snd_kcontrol *kcontrol,
  1390. int event)
  1391. {
  1392. struct snd_soc_component *component =
  1393. snd_soc_dapm_to_component(w->dapm);
  1394. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1395. int ret = 0;
  1396. int bank = 0;
  1397. u8 mode = 0;
  1398. int i = 0;
  1399. int rate = 0;
  1400. bank = (wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1401. wcd938x->tx_swr_dev->dev_num) ? 0 : 1);
  1402. switch (event) {
  1403. case SND_SOC_DAPM_PRE_PMU:
  1404. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1405. if (test_bit(WCD_ADC1, &wcd938x->status_mask))
  1406. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
  1407. if (test_bit(WCD_ADC2, &wcd938x->status_mask))
  1408. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
  1409. if (test_bit(WCD_ADC3, &wcd938x->status_mask))
  1410. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
  1411. if (test_bit(WCD_ADC4, &wcd938x->status_mask))
  1412. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
  1413. if (mode != 0) {
  1414. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1415. if (mode & (1 << i)) {
  1416. i++;
  1417. break;
  1418. }
  1419. }
  1420. }
  1421. rate = wcd938x_get_clk_rate(i);
  1422. wcd938x_set_swr_clk_rate(component, rate, bank);
  1423. }
  1424. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1425. wcd938x->tx_swr_dev->dev_num,
  1426. true);
  1427. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1428. /* Copy clk settings to active bank */
  1429. wcd938x_set_swr_clk_rate(component, rate, !bank);
  1430. }
  1431. break;
  1432. case SND_SOC_DAPM_POST_PMD:
  1433. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1434. rate = wcd938x_get_clk_rate(ADC_MODE_INVALID);
  1435. wcd938x_set_swr_clk_rate(component, rate, !bank);
  1436. }
  1437. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1438. wcd938x->tx_swr_dev->dev_num,
  1439. false);
  1440. if (strnstr(w->name, "ADC", sizeof("ADC")))
  1441. wcd938x_set_swr_clk_rate(component, rate, bank);
  1442. break;
  1443. };
  1444. return ret;
  1445. }
  1446. static int wcd938x_get_adc_mode(int val)
  1447. {
  1448. int ret = 0;
  1449. switch (val) {
  1450. case ADC_MODE_INVALID:
  1451. ret = ADC_MODE_VAL_NORMAL;
  1452. break;
  1453. case ADC_MODE_HIFI:
  1454. ret = ADC_MODE_VAL_HIFI;
  1455. break;
  1456. case ADC_MODE_LO_HIF:
  1457. ret = ADC_MODE_VAL_LO_HIF;
  1458. break;
  1459. case ADC_MODE_NORMAL:
  1460. ret = ADC_MODE_VAL_NORMAL;
  1461. break;
  1462. case ADC_MODE_LP:
  1463. ret = ADC_MODE_VAL_LP;
  1464. break;
  1465. case ADC_MODE_ULP1:
  1466. ret = ADC_MODE_VAL_ULP1;
  1467. break;
  1468. case ADC_MODE_ULP2:
  1469. ret = ADC_MODE_VAL_ULP2;
  1470. break;
  1471. default:
  1472. ret = -EINVAL;
  1473. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1474. break;
  1475. }
  1476. return ret;
  1477. }
  1478. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1479. struct snd_kcontrol *kcontrol,
  1480. int event){
  1481. struct snd_soc_component *component =
  1482. snd_soc_dapm_to_component(w->dapm);
  1483. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1484. int clk_rate = 0;
  1485. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1486. w->name, event);
  1487. switch (event) {
  1488. case SND_SOC_DAPM_PRE_PMU:
  1489. snd_soc_component_update_bits(component,
  1490. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1491. snd_soc_component_update_bits(component,
  1492. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1493. set_bit(w->shift, &wcd938x->status_mask);
  1494. clk_rate = wcd938x_get_clk_rate(wcd938x->tx_mode[w->shift]);
  1495. /* Enable BCS for Headset mic */
  1496. if (w->shift == 1 && !(snd_soc_component_read32(component,
  1497. WCD938X_TX_NEW_AMIC_MUX_CFG) & 0x80)) {
  1498. if (!wcd938x->bcs_dis)
  1499. wcd938x_tx_connect_port(component, MBHC,
  1500. SWR_CLK_RATE_4P8MHZ, true);
  1501. set_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1502. }
  1503. wcd938x_tx_connect_port(component, ADC1 + (w->shift), clk_rate,
  1504. true);
  1505. break;
  1506. case SND_SOC_DAPM_POST_PMD:
  1507. wcd938x_tx_connect_port(component, ADC1 + (w->shift), 0, false);
  1508. if (w->shift == 1 &&
  1509. test_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask)) {
  1510. if (!wcd938x->bcs_dis)
  1511. wcd938x_tx_connect_port(component, MBHC, 0,
  1512. false);
  1513. clear_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1514. }
  1515. snd_soc_component_update_bits(component,
  1516. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1517. clear_bit(w->shift, &wcd938x->status_mask);
  1518. break;
  1519. };
  1520. return 0;
  1521. }
  1522. void wcd938x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1523. bool bcs_disable)
  1524. {
  1525. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1526. if (wcd938x->update_wcd_event) {
  1527. if (bcs_disable)
  1528. wcd938x->update_wcd_event(wcd938x->handle,
  1529. WCD_BOLERO_EVT_BCS_CLK_OFF, 0);
  1530. else
  1531. wcd938x->update_wcd_event(wcd938x->handle,
  1532. WCD_BOLERO_EVT_BCS_CLK_OFF, 1);
  1533. }
  1534. }
  1535. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1536. int channel, int mode)
  1537. {
  1538. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1539. int ret = 0;
  1540. switch (channel) {
  1541. case 0:
  1542. reg = WCD938X_ANA_TX_CH2;
  1543. mask = 0x40;
  1544. break;
  1545. case 1:
  1546. reg = WCD938X_ANA_TX_CH2;
  1547. mask = 0x20;
  1548. break;
  1549. case 2:
  1550. reg = WCD938X_ANA_TX_CH4;
  1551. mask = 0x40;
  1552. break;
  1553. case 3:
  1554. reg = WCD938X_ANA_TX_CH4;
  1555. mask = 0x20;
  1556. break;
  1557. default:
  1558. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1559. ret = -EINVAL;
  1560. break;
  1561. }
  1562. if (!mode)
  1563. val = 0x00;
  1564. else
  1565. val = mask;
  1566. if (!ret)
  1567. snd_soc_component_update_bits(component, reg, mask, val);
  1568. return ret;
  1569. }
  1570. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1571. struct snd_kcontrol *kcontrol, int event)
  1572. {
  1573. struct snd_soc_component *component =
  1574. snd_soc_dapm_to_component(w->dapm);
  1575. int mode;
  1576. int ret = 0;
  1577. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1578. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1579. w->name, event);
  1580. switch (event) {
  1581. case SND_SOC_DAPM_PRE_PMU:
  1582. snd_soc_component_update_bits(component,
  1583. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1584. snd_soc_component_update_bits(component,
  1585. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1586. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1587. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1588. if (mode < 0) {
  1589. dev_info(component->dev,
  1590. "%s: invalid mode, setting to normal mode\n",
  1591. __func__);
  1592. mode = ADC_MODE_VAL_NORMAL;
  1593. }
  1594. switch (w->shift) {
  1595. case 0:
  1596. snd_soc_component_update_bits(component,
  1597. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1598. mode);
  1599. snd_soc_component_update_bits(component,
  1600. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x10);
  1601. break;
  1602. case 1:
  1603. snd_soc_component_update_bits(component,
  1604. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1605. mode << 4);
  1606. snd_soc_component_update_bits(component,
  1607. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x20);
  1608. break;
  1609. case 2:
  1610. snd_soc_component_update_bits(component,
  1611. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1612. mode);
  1613. snd_soc_component_update_bits(component,
  1614. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
  1615. break;
  1616. case 3:
  1617. snd_soc_component_update_bits(component,
  1618. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1619. mode << 4);
  1620. snd_soc_component_update_bits(component,
  1621. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1622. break;
  1623. default:
  1624. break;
  1625. }
  1626. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1627. break;
  1628. case SND_SOC_DAPM_POST_PMD:
  1629. switch (w->shift) {
  1630. case 0:
  1631. snd_soc_component_update_bits(component,
  1632. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1633. 0x00);
  1634. snd_soc_component_update_bits(component,
  1635. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1636. break;
  1637. case 1:
  1638. snd_soc_component_update_bits(component,
  1639. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1640. 0x00);
  1641. snd_soc_component_update_bits(component,
  1642. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x00);
  1643. break;
  1644. case 2:
  1645. snd_soc_component_update_bits(component,
  1646. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1647. 0x00);
  1648. snd_soc_component_update_bits(component,
  1649. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x00);
  1650. break;
  1651. case 3:
  1652. snd_soc_component_update_bits(component,
  1653. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1654. 0x00);
  1655. snd_soc_component_update_bits(component,
  1656. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1657. break;
  1658. default:
  1659. break;
  1660. }
  1661. snd_soc_component_update_bits(component,
  1662. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1663. break;
  1664. };
  1665. return ret;
  1666. }
  1667. int wcd938x_micbias_control(struct snd_soc_component *component,
  1668. int micb_num, int req, bool is_dapm)
  1669. {
  1670. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1671. int micb_index = micb_num - 1;
  1672. u16 micb_reg;
  1673. int pre_off_event = 0, post_off_event = 0;
  1674. int post_on_event = 0, post_dapm_off = 0;
  1675. int post_dapm_on = 0;
  1676. int ret = 0;
  1677. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1678. dev_err(component->dev,
  1679. "%s: Invalid micbias index, micb_ind:%d\n",
  1680. __func__, micb_index);
  1681. return -EINVAL;
  1682. }
  1683. if (NULL == wcd938x) {
  1684. dev_err(component->dev,
  1685. "%s: wcd938x private data is NULL\n", __func__);
  1686. return -EINVAL;
  1687. }
  1688. switch (micb_num) {
  1689. case MIC_BIAS_1:
  1690. micb_reg = WCD938X_ANA_MICB1;
  1691. break;
  1692. case MIC_BIAS_2:
  1693. micb_reg = WCD938X_ANA_MICB2;
  1694. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1695. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1696. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1697. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1698. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1699. break;
  1700. case MIC_BIAS_3:
  1701. micb_reg = WCD938X_ANA_MICB3;
  1702. break;
  1703. case MIC_BIAS_4:
  1704. micb_reg = WCD938X_ANA_MICB4;
  1705. break;
  1706. default:
  1707. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1708. __func__, micb_num);
  1709. return -EINVAL;
  1710. };
  1711. mutex_lock(&wcd938x->micb_lock);
  1712. switch (req) {
  1713. case MICB_PULLUP_ENABLE:
  1714. if (!wcd938x->dev_up) {
  1715. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1716. __func__, req);
  1717. ret = -ENODEV;
  1718. goto done;
  1719. }
  1720. wcd938x->pullup_ref[micb_index]++;
  1721. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1722. (wcd938x->micb_ref[micb_index] == 0))
  1723. snd_soc_component_update_bits(component, micb_reg,
  1724. 0xC0, 0x80);
  1725. break;
  1726. case MICB_PULLUP_DISABLE:
  1727. if (wcd938x->pullup_ref[micb_index] > 0)
  1728. wcd938x->pullup_ref[micb_index]--;
  1729. if (!wcd938x->dev_up) {
  1730. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1731. __func__, req);
  1732. ret = -ENODEV;
  1733. goto done;
  1734. }
  1735. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1736. (wcd938x->micb_ref[micb_index] == 0))
  1737. snd_soc_component_update_bits(component, micb_reg,
  1738. 0xC0, 0x00);
  1739. break;
  1740. case MICB_ENABLE:
  1741. if (!wcd938x->dev_up) {
  1742. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1743. __func__, req);
  1744. ret = -ENODEV;
  1745. goto done;
  1746. }
  1747. wcd938x->micb_ref[micb_index]++;
  1748. if (wcd938x->micb_ref[micb_index] == 1) {
  1749. snd_soc_component_update_bits(component,
  1750. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1751. snd_soc_component_update_bits(component,
  1752. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1753. snd_soc_component_update_bits(component,
  1754. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1755. snd_soc_component_update_bits(component,
  1756. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1757. snd_soc_component_update_bits(component,
  1758. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1759. snd_soc_component_update_bits(component,
  1760. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1761. snd_soc_component_update_bits(component,
  1762. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1763. snd_soc_component_update_bits(component,
  1764. micb_reg, 0xC0, 0x40);
  1765. if (post_on_event)
  1766. blocking_notifier_call_chain(
  1767. &wcd938x->mbhc->notifier,
  1768. post_on_event,
  1769. &wcd938x->mbhc->wcd_mbhc);
  1770. }
  1771. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1772. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1773. post_dapm_on,
  1774. &wcd938x->mbhc->wcd_mbhc);
  1775. break;
  1776. case MICB_DISABLE:
  1777. if (wcd938x->micb_ref[micb_index] > 0)
  1778. wcd938x->micb_ref[micb_index]--;
  1779. if (!wcd938x->dev_up) {
  1780. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1781. __func__, req);
  1782. ret = -ENODEV;
  1783. goto done;
  1784. }
  1785. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1786. (wcd938x->pullup_ref[micb_index] > 0))
  1787. snd_soc_component_update_bits(component, micb_reg,
  1788. 0xC0, 0x80);
  1789. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1790. (wcd938x->pullup_ref[micb_index] == 0)) {
  1791. if (pre_off_event && wcd938x->mbhc)
  1792. blocking_notifier_call_chain(
  1793. &wcd938x->mbhc->notifier,
  1794. pre_off_event,
  1795. &wcd938x->mbhc->wcd_mbhc);
  1796. snd_soc_component_update_bits(component, micb_reg,
  1797. 0xC0, 0x00);
  1798. if (post_off_event && wcd938x->mbhc)
  1799. blocking_notifier_call_chain(
  1800. &wcd938x->mbhc->notifier,
  1801. post_off_event,
  1802. &wcd938x->mbhc->wcd_mbhc);
  1803. }
  1804. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1805. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1806. post_dapm_off,
  1807. &wcd938x->mbhc->wcd_mbhc);
  1808. break;
  1809. };
  1810. dev_dbg(component->dev,
  1811. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1812. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1813. wcd938x->pullup_ref[micb_index]);
  1814. done:
  1815. mutex_unlock(&wcd938x->micb_lock);
  1816. return ret;
  1817. }
  1818. EXPORT_SYMBOL(wcd938x_micbias_control);
  1819. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1820. {
  1821. int ret = 0;
  1822. uint8_t devnum = 0;
  1823. int num_retry = NUM_ATTEMPTS;
  1824. do {
  1825. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1826. if (ret) {
  1827. dev_err(&swr_dev->dev,
  1828. "%s get devnum %d for dev addr %lx failed\n",
  1829. __func__, devnum, swr_dev->addr);
  1830. /* retry after 1ms */
  1831. usleep_range(1000, 1010);
  1832. }
  1833. } while (ret && --num_retry);
  1834. swr_dev->dev_num = devnum;
  1835. return 0;
  1836. }
  1837. static int wcd938x_event_notify(struct notifier_block *block,
  1838. unsigned long val,
  1839. void *data)
  1840. {
  1841. u16 event = (val & 0xffff);
  1842. int ret = 0;
  1843. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1844. struct snd_soc_component *component = wcd938x->component;
  1845. struct wcd_mbhc *mbhc;
  1846. switch (event) {
  1847. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1848. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  1849. snd_soc_component_update_bits(component,
  1850. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1851. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1852. }
  1853. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  1854. snd_soc_component_update_bits(component,
  1855. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1856. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1857. }
  1858. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  1859. snd_soc_component_update_bits(component,
  1860. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  1861. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1862. }
  1863. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  1864. snd_soc_component_update_bits(component,
  1865. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  1866. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1867. }
  1868. break;
  1869. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1870. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1871. 0xC0, 0x00);
  1872. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1873. 0x80, 0x00);
  1874. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1875. 0x80, 0x00);
  1876. break;
  1877. case BOLERO_WCD_EVT_SSR_DOWN:
  1878. wcd938x->dev_up = false;
  1879. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = true;
  1880. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1881. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  1882. wcd938x_reset_low(wcd938x->dev);
  1883. break;
  1884. case BOLERO_WCD_EVT_SSR_UP:
  1885. wcd938x_reset(wcd938x->dev);
  1886. /* allow reset to take effect */
  1887. usleep_range(10000, 10010);
  1888. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  1889. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  1890. wcd938x_init_reg(component);
  1891. regcache_mark_dirty(wcd938x->regmap);
  1892. regcache_sync(wcd938x->regmap);
  1893. /* Initialize MBHC module */
  1894. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1895. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  1896. if (ret) {
  1897. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1898. __func__);
  1899. } else {
  1900. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1901. }
  1902. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = false;
  1903. wcd938x->dev_up = true;
  1904. break;
  1905. case BOLERO_WCD_EVT_CLK_NOTIFY:
  1906. snd_soc_component_update_bits(component,
  1907. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  1908. ((val >> 0x10) << 0x01));
  1909. break;
  1910. default:
  1911. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  1912. break;
  1913. }
  1914. return 0;
  1915. }
  1916. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1917. int event)
  1918. {
  1919. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1920. int micb_num;
  1921. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1922. __func__, w->name, event);
  1923. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1924. micb_num = MIC_BIAS_1;
  1925. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1926. micb_num = MIC_BIAS_2;
  1927. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1928. micb_num = MIC_BIAS_3;
  1929. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  1930. micb_num = MIC_BIAS_4;
  1931. else
  1932. return -EINVAL;
  1933. switch (event) {
  1934. case SND_SOC_DAPM_PRE_PMU:
  1935. wcd938x_micbias_control(component, micb_num,
  1936. MICB_ENABLE, true);
  1937. break;
  1938. case SND_SOC_DAPM_POST_PMU:
  1939. /* 1 msec delay as per HW requirement */
  1940. usleep_range(1000, 1100);
  1941. break;
  1942. case SND_SOC_DAPM_POST_PMD:
  1943. wcd938x_micbias_control(component, micb_num,
  1944. MICB_DISABLE, true);
  1945. break;
  1946. };
  1947. return 0;
  1948. }
  1949. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1950. struct snd_kcontrol *kcontrol,
  1951. int event)
  1952. {
  1953. return __wcd938x_codec_enable_micbias(w, event);
  1954. }
  1955. static int __wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1956. int event)
  1957. {
  1958. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1959. int micb_num;
  1960. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1961. __func__, w->name, event);
  1962. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1963. micb_num = MIC_BIAS_1;
  1964. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1965. micb_num = MIC_BIAS_2;
  1966. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1967. micb_num = MIC_BIAS_3;
  1968. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  1969. micb_num = MIC_BIAS_4;
  1970. else
  1971. return -EINVAL;
  1972. switch (event) {
  1973. case SND_SOC_DAPM_PRE_PMU:
  1974. wcd938x_micbias_control(component, micb_num,
  1975. MICB_PULLUP_ENABLE, true);
  1976. break;
  1977. case SND_SOC_DAPM_POST_PMU:
  1978. /* 1 msec delay as per HW requirement */
  1979. usleep_range(1000, 1100);
  1980. break;
  1981. case SND_SOC_DAPM_POST_PMD:
  1982. wcd938x_micbias_control(component, micb_num,
  1983. MICB_PULLUP_DISABLE, true);
  1984. break;
  1985. };
  1986. return 0;
  1987. }
  1988. static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1989. struct snd_kcontrol *kcontrol,
  1990. int event)
  1991. {
  1992. return __wcd938x_codec_enable_micbias_pullup(w, event);
  1993. }
  1994. static int wcd938x_wakeup(void *handle, bool enable)
  1995. {
  1996. struct wcd938x_priv *priv;
  1997. int ret = 0;
  1998. if (!handle) {
  1999. pr_err("%s: NULL handle\n", __func__);
  2000. return -EINVAL;
  2001. }
  2002. priv = (struct wcd938x_priv *)handle;
  2003. if (!priv->tx_swr_dev) {
  2004. pr_err("%s: tx swr dev is NULL\n", __func__);
  2005. return -EINVAL;
  2006. }
  2007. mutex_lock(&priv->wakeup_lock);
  2008. if (enable)
  2009. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2010. else
  2011. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2012. mutex_unlock(&priv->wakeup_lock);
  2013. return ret;
  2014. }
  2015. static int wcd938x_codec_force_enable_micbias(struct snd_soc_dapm_widget *w,
  2016. struct snd_kcontrol *kcontrol,
  2017. int event)
  2018. {
  2019. int ret = 0;
  2020. struct snd_soc_component *component =
  2021. snd_soc_dapm_to_component(w->dapm);
  2022. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2023. switch (event) {
  2024. case SND_SOC_DAPM_PRE_PMU:
  2025. wcd938x_wakeup(wcd938x, true);
  2026. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_PRE_PMU);
  2027. wcd938x_wakeup(wcd938x, false);
  2028. break;
  2029. case SND_SOC_DAPM_POST_PMD:
  2030. wcd938x_wakeup(wcd938x, true);
  2031. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_POST_PMD);
  2032. wcd938x_wakeup(wcd938x, false);
  2033. break;
  2034. }
  2035. return ret;
  2036. }
  2037. static int wcd938x_enable_micbias(struct wcd938x_priv *wcd938x,
  2038. int micb_num, int req)
  2039. {
  2040. int micb_index = micb_num - 1;
  2041. u16 micb_reg;
  2042. if (NULL == wcd938x) {
  2043. pr_err("%s: wcd938x private data is NULL\n", __func__);
  2044. return -EINVAL;
  2045. }
  2046. switch (micb_num) {
  2047. case MIC_BIAS_1:
  2048. micb_reg = WCD938X_ANA_MICB1;
  2049. break;
  2050. case MIC_BIAS_2:
  2051. micb_reg = WCD938X_ANA_MICB2;
  2052. break;
  2053. case MIC_BIAS_3:
  2054. micb_reg = WCD938X_ANA_MICB3;
  2055. break;
  2056. case MIC_BIAS_4:
  2057. micb_reg = WCD938X_ANA_MICB4;
  2058. break;
  2059. default:
  2060. pr_err("%s: Invalid micbias number: %d\n", __func__, micb_num);
  2061. return -EINVAL;
  2062. };
  2063. mutex_lock(&wcd938x->micb_lock);
  2064. switch (req) {
  2065. case MICB_ENABLE:
  2066. wcd938x->micb_ref[micb_index]++;
  2067. if (wcd938x->micb_ref[micb_index] == 1) {
  2068. regmap_update_bits(wcd938x->regmap,
  2069. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  2070. regmap_update_bits(wcd938x->regmap,
  2071. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  2072. regmap_update_bits(wcd938x->regmap,
  2073. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  2074. regmap_update_bits(wcd938x->regmap,
  2075. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  2076. regmap_update_bits(wcd938x->regmap,
  2077. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  2078. regmap_update_bits(wcd938x->regmap,
  2079. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  2080. regmap_update_bits(wcd938x->regmap,
  2081. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  2082. regmap_update_bits(wcd938x->regmap,
  2083. micb_reg, 0xC0, 0x40);
  2084. regmap_update_bits(wcd938x->regmap, micb_reg, 0x3F, 0x10);
  2085. }
  2086. break;
  2087. case MICB_PULLUP_ENABLE:
  2088. wcd938x->pullup_ref[micb_index]++;
  2089. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  2090. (wcd938x->micb_ref[micb_index] == 0))
  2091. regmap_update_bits(wcd938x->regmap, micb_reg,
  2092. 0xC0, 0x80);
  2093. break;
  2094. case MICB_PULLUP_DISABLE:
  2095. if (wcd938x->pullup_ref[micb_index] > 0)
  2096. wcd938x->pullup_ref[micb_index]--;
  2097. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  2098. (wcd938x->micb_ref[micb_index] == 0))
  2099. regmap_update_bits(wcd938x->regmap, micb_reg,
  2100. 0xC0, 0x00);
  2101. break;
  2102. case MICB_DISABLE:
  2103. if (wcd938x->micb_ref[micb_index] > 0)
  2104. wcd938x->micb_ref[micb_index]--;
  2105. if ((wcd938x->micb_ref[micb_index] == 0) &&
  2106. (wcd938x->pullup_ref[micb_index] > 0))
  2107. regmap_update_bits(wcd938x->regmap, micb_reg,
  2108. 0xC0, 0x80);
  2109. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  2110. (wcd938x->pullup_ref[micb_index] == 0))
  2111. regmap_update_bits(wcd938x->regmap, micb_reg,
  2112. 0xC0, 0x00);
  2113. break;
  2114. };
  2115. mutex_unlock(&wcd938x->micb_lock);
  2116. return 0;
  2117. }
  2118. int wcd938x_codec_force_enable_micbias_v2(struct snd_soc_component *component,
  2119. int event, int micb_num)
  2120. {
  2121. struct wcd938x_priv *wcd938x_priv = NULL;
  2122. if(NULL == component) {
  2123. pr_err("%s: wcd938x component is NULL\n", __func__);
  2124. return -EINVAL;
  2125. }
  2126. if(event != SND_SOC_DAPM_PRE_PMU && event != SND_SOC_DAPM_POST_PMD) {
  2127. pr_err("%s: invalid event: %d\n", __func__, event);
  2128. return -EINVAL;
  2129. }
  2130. if(micb_num < MIC_BIAS_1 || micb_num > MIC_BIAS_4) {
  2131. pr_err("%s: invalid mic bias num: %d\n", __func__, micb_num);
  2132. return -EINVAL;
  2133. }
  2134. wcd938x_priv = snd_soc_component_get_drvdata(component);
  2135. switch (event) {
  2136. case SND_SOC_DAPM_PRE_PMU:
  2137. wcd938x_wakeup(wcd938x_priv, true);
  2138. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_ENABLE);
  2139. wcd938x_wakeup(wcd938x_priv, false);
  2140. break;
  2141. case SND_SOC_DAPM_POST_PMD:
  2142. wcd938x_wakeup(wcd938x_priv, true);
  2143. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_DISABLE);
  2144. wcd938x_wakeup(wcd938x_priv, false);
  2145. break;
  2146. }
  2147. return 0;
  2148. }
  2149. EXPORT_SYMBOL(wcd938x_codec_force_enable_micbias_v2);
  2150. static inline int wcd938x_tx_path_get(const char *wname,
  2151. unsigned int *path_num)
  2152. {
  2153. int ret = 0;
  2154. char *widget_name = NULL;
  2155. char *w_name = NULL;
  2156. char *path_num_char = NULL;
  2157. char *path_name = NULL;
  2158. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2159. if (!widget_name)
  2160. return -EINVAL;
  2161. w_name = widget_name;
  2162. path_name = strsep(&widget_name, " ");
  2163. if (!path_name) {
  2164. pr_err("%s: Invalid widget name = %s\n",
  2165. __func__, widget_name);
  2166. ret = -EINVAL;
  2167. goto err;
  2168. }
  2169. path_num_char = strpbrk(path_name, "0123");
  2170. if (!path_num_char) {
  2171. pr_err("%s: tx path index not found\n",
  2172. __func__);
  2173. ret = -EINVAL;
  2174. goto err;
  2175. }
  2176. ret = kstrtouint(path_num_char, 10, path_num);
  2177. if (ret < 0)
  2178. pr_err("%s: Invalid tx path = %s\n",
  2179. __func__, w_name);
  2180. err:
  2181. kfree(w_name);
  2182. return ret;
  2183. }
  2184. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  2185. struct snd_ctl_elem_value *ucontrol)
  2186. {
  2187. struct snd_soc_component *component =
  2188. snd_soc_kcontrol_component(kcontrol);
  2189. struct wcd938x_priv *wcd938x = NULL;
  2190. int ret = 0;
  2191. unsigned int path = 0;
  2192. if (!component)
  2193. return -EINVAL;
  2194. wcd938x = snd_soc_component_get_drvdata(component);
  2195. if (!wcd938x)
  2196. return -EINVAL;
  2197. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2198. if (ret < 0)
  2199. return ret;
  2200. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  2201. return 0;
  2202. }
  2203. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  2204. struct snd_ctl_elem_value *ucontrol)
  2205. {
  2206. struct snd_soc_component *component =
  2207. snd_soc_kcontrol_component(kcontrol);
  2208. struct wcd938x_priv *wcd938x = NULL;
  2209. u32 mode_val;
  2210. unsigned int path = 0;
  2211. int ret = 0;
  2212. if (!component)
  2213. return -EINVAL;
  2214. wcd938x = snd_soc_component_get_drvdata(component);
  2215. if (!wcd938x)
  2216. return -EINVAL;
  2217. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2218. if (ret)
  2219. return ret;
  2220. mode_val = ucontrol->value.enumerated.item[0];
  2221. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2222. wcd938x->tx_mode[path] = mode_val;
  2223. return 0;
  2224. }
  2225. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2226. struct snd_ctl_elem_value *ucontrol)
  2227. {
  2228. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2229. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2230. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  2231. return 0;
  2232. }
  2233. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2234. struct snd_ctl_elem_value *ucontrol)
  2235. {
  2236. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2237. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2238. u32 mode_val;
  2239. mode_val = ucontrol->value.enumerated.item[0];
  2240. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2241. if (wcd938x->variant == WCD9380) {
  2242. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  2243. dev_info(component->dev,
  2244. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  2245. __func__);
  2246. mode_val = CLS_H_ULP;
  2247. }
  2248. }
  2249. if (mode_val == CLS_H_NORMAL) {
  2250. dev_info(component->dev,
  2251. "%s:Invalid HPH Mode, default to class_AB\n",
  2252. __func__);
  2253. mode_val = CLS_H_ULP;
  2254. }
  2255. wcd938x->hph_mode = mode_val;
  2256. return 0;
  2257. }
  2258. static int wcd938x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  2259. struct snd_ctl_elem_value *ucontrol)
  2260. {
  2261. u8 ear_pa_gain = 0;
  2262. struct snd_soc_component *component =
  2263. snd_soc_kcontrol_component(kcontrol);
  2264. ear_pa_gain = snd_soc_component_read32(component,
  2265. WCD938X_ANA_EAR_COMPANDER_CTL);
  2266. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  2267. ucontrol->value.integer.value[0] = ear_pa_gain;
  2268. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  2269. ear_pa_gain);
  2270. return 0;
  2271. }
  2272. static int wcd938x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  2273. struct snd_ctl_elem_value *ucontrol)
  2274. {
  2275. u8 ear_pa_gain = 0;
  2276. struct snd_soc_component *component =
  2277. snd_soc_kcontrol_component(kcontrol);
  2278. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2279. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2280. __func__, ucontrol->value.integer.value[0]);
  2281. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  2282. if (!wcd938x->comp1_enable) {
  2283. snd_soc_component_update_bits(component,
  2284. WCD938X_ANA_EAR_COMPANDER_CTL,
  2285. 0x7C, ear_pa_gain);
  2286. }
  2287. return 0;
  2288. }
  2289. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  2290. struct snd_ctl_elem_value *ucontrol)
  2291. {
  2292. struct snd_soc_component *component =
  2293. snd_soc_kcontrol_component(kcontrol);
  2294. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2295. bool hphr;
  2296. struct soc_multi_mixer_control *mc;
  2297. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2298. hphr = mc->shift;
  2299. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  2300. wcd938x->comp1_enable;
  2301. return 0;
  2302. }
  2303. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  2304. struct snd_ctl_elem_value *ucontrol)
  2305. {
  2306. struct snd_soc_component *component =
  2307. snd_soc_kcontrol_component(kcontrol);
  2308. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2309. int value = ucontrol->value.integer.value[0];
  2310. bool hphr;
  2311. struct soc_multi_mixer_control *mc;
  2312. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2313. hphr = mc->shift;
  2314. if (hphr)
  2315. wcd938x->comp2_enable = value;
  2316. else
  2317. wcd938x->comp1_enable = value;
  2318. return 0;
  2319. }
  2320. static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
  2321. struct snd_ctl_elem_value *ucontrol)
  2322. {
  2323. struct snd_soc_component *component =
  2324. snd_soc_kcontrol_component(kcontrol);
  2325. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2326. ucontrol->value.integer.value[0] = wcd938x->ldoh;
  2327. return 0;
  2328. }
  2329. static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
  2330. struct snd_ctl_elem_value *ucontrol)
  2331. {
  2332. struct snd_soc_component *component =
  2333. snd_soc_kcontrol_component(kcontrol);
  2334. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2335. wcd938x->ldoh = ucontrol->value.integer.value[0];
  2336. return 0;
  2337. }
  2338. const char * const tx_master_ch_text[] = {
  2339. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  2340. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  2341. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  2342. "SWRM_PCM_IN",
  2343. };
  2344. const struct soc_enum tx_master_ch_enum =
  2345. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2346. tx_master_ch_text);
  2347. static void wcd938x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2348. {
  2349. u8 ch_type = 0;
  2350. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2351. ch_type = ADC1;
  2352. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2353. ch_type = ADC2;
  2354. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2355. ch_type = ADC3;
  2356. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2357. ch_type = ADC4;
  2358. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2359. ch_type = DMIC0;
  2360. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2361. ch_type = DMIC1;
  2362. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2363. ch_type = MBHC;
  2364. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2365. ch_type = DMIC2;
  2366. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2367. ch_type = DMIC3;
  2368. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2369. ch_type = DMIC4;
  2370. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2371. ch_type = DMIC5;
  2372. else if (strnstr(wname, "DMIC6", sizeof("DMIC6")))
  2373. ch_type = DMIC6;
  2374. else if (strnstr(wname, "DMIC7", sizeof("DMIC7")))
  2375. ch_type = DMIC7;
  2376. else
  2377. pr_err("%s: port name: %s is not listed\n", __func__, wname);
  2378. if (ch_type)
  2379. *ch_idx = wcd938x_slave_get_slave_ch_val(ch_type);
  2380. else
  2381. *ch_idx = -EINVAL;
  2382. }
  2383. static int wcd938x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2384. struct snd_ctl_elem_value *ucontrol)
  2385. {
  2386. struct snd_soc_component *component =
  2387. snd_soc_kcontrol_component(kcontrol);
  2388. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2389. int slave_ch_idx;
  2390. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2391. if (slave_ch_idx != -EINVAL)
  2392. ucontrol->value.integer.value[0] =
  2393. wcd938x_slave_get_master_ch_val(
  2394. wcd938x->tx_master_ch_map[slave_ch_idx]);
  2395. return 0;
  2396. }
  2397. static int wcd938x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2398. struct snd_ctl_elem_value *ucontrol)
  2399. {
  2400. struct snd_soc_component *component =
  2401. snd_soc_kcontrol_component(kcontrol);
  2402. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2403. int slave_ch_idx;
  2404. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2405. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2406. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2407. __func__, ucontrol->value.enumerated.item[0]);
  2408. if (slave_ch_idx != -EINVAL)
  2409. wcd938x->tx_master_ch_map[slave_ch_idx] =
  2410. wcd938x_slave_get_master_ch(
  2411. ucontrol->value.enumerated.item[0]);
  2412. return 0;
  2413. }
  2414. static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol,
  2415. struct snd_ctl_elem_value *ucontrol)
  2416. {
  2417. struct snd_soc_component *component =
  2418. snd_soc_kcontrol_component(kcontrol);
  2419. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2420. ucontrol->value.integer.value[0] = wcd938x->bcs_dis;
  2421. return 0;
  2422. }
  2423. static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol,
  2424. struct snd_ctl_elem_value *ucontrol)
  2425. {
  2426. struct snd_soc_component *component =
  2427. snd_soc_kcontrol_component(kcontrol);
  2428. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2429. wcd938x->bcs_dis = ucontrol->value.integer.value[0];
  2430. return 0;
  2431. }
  2432. static const char * const tx_mode_mux_text_wcd9380[] = {
  2433. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2434. };
  2435. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  2436. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  2437. tx_mode_mux_text_wcd9380);
  2438. static const char * const tx_mode_mux_text[] = {
  2439. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2440. "ADC_ULP1", "ADC_ULP2",
  2441. };
  2442. static const struct soc_enum tx_mode_mux_enum =
  2443. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2444. tx_mode_mux_text);
  2445. static const char * const rx_hph_mode_mux_text_wcd9380[] = {
  2446. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  2447. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  2448. "CLS_AB_LOHIFI",
  2449. };
  2450. static const char * const wcd938x_ear_pa_gain_text[] = {
  2451. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  2452. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  2453. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  2454. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  2455. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  2456. };
  2457. static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
  2458. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
  2459. rx_hph_mode_mux_text_wcd9380);
  2460. static SOC_ENUM_SINGLE_EXT_DECL(wcd938x_ear_pa_gain_enum,
  2461. wcd938x_ear_pa_gain_text);
  2462. static const char * const rx_hph_mode_mux_text[] = {
  2463. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2464. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2465. };
  2466. static const struct soc_enum rx_hph_mode_mux_enum =
  2467. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2468. rx_hph_mode_mux_text);
  2469. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  2470. SOC_ENUM_EXT("EAR PA GAIN", wcd938x_ear_pa_gain_enum,
  2471. wcd938x_ear_pa_gain_get, wcd938x_ear_pa_gain_put),
  2472. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
  2473. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2474. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  2475. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2476. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  2477. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2478. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  2479. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2480. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  2481. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2482. };
  2483. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  2484. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2485. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2486. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2487. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2488. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2489. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2490. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2491. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2492. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  2493. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2494. };
  2495. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  2496. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2497. wcd938x_get_compander, wcd938x_set_compander),
  2498. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2499. wcd938x_get_compander, wcd938x_set_compander),
  2500. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  2501. wcd938x_ldoh_get, wcd938x_ldoh_put),
  2502. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2503. wcd938x_bcs_get, wcd938x_bcs_put),
  2504. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  2505. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  2506. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  2507. analog_gain),
  2508. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  2509. analog_gain),
  2510. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  2511. analog_gain),
  2512. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  2513. analog_gain),
  2514. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2515. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2516. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2517. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2518. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2519. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2520. SOC_ENUM_EXT("ADC4 ChMap", tx_master_ch_enum,
  2521. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2522. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2523. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2524. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2525. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2526. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2527. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2528. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2529. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2530. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2531. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2532. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2533. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2534. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2535. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2536. SOC_ENUM_EXT("DMIC6 ChMap", tx_master_ch_enum,
  2537. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2538. SOC_ENUM_EXT("DMIC7 ChMap", tx_master_ch_enum,
  2539. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2540. };
  2541. static const struct snd_kcontrol_new adc1_switch[] = {
  2542. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2543. };
  2544. static const struct snd_kcontrol_new adc2_switch[] = {
  2545. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2546. };
  2547. static const struct snd_kcontrol_new adc3_switch[] = {
  2548. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2549. };
  2550. static const struct snd_kcontrol_new adc4_switch[] = {
  2551. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2552. };
  2553. static const struct snd_kcontrol_new dmic1_switch[] = {
  2554. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2555. };
  2556. static const struct snd_kcontrol_new dmic2_switch[] = {
  2557. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2558. };
  2559. static const struct snd_kcontrol_new dmic3_switch[] = {
  2560. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2561. };
  2562. static const struct snd_kcontrol_new dmic4_switch[] = {
  2563. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2564. };
  2565. static const struct snd_kcontrol_new dmic5_switch[] = {
  2566. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2567. };
  2568. static const struct snd_kcontrol_new dmic6_switch[] = {
  2569. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2570. };
  2571. static const struct snd_kcontrol_new dmic7_switch[] = {
  2572. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2573. };
  2574. static const struct snd_kcontrol_new dmic8_switch[] = {
  2575. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2576. };
  2577. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2578. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2579. };
  2580. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2581. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2582. };
  2583. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2584. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2585. };
  2586. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2587. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2588. };
  2589. static const char * const adc2_mux_text[] = {
  2590. "INP2", "INP3"
  2591. };
  2592. static const struct soc_enum adc2_enum =
  2593. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  2594. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2595. static const struct snd_kcontrol_new tx_adc2_mux =
  2596. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2597. static const char * const adc3_mux_text[] = {
  2598. "INP4", "INP6"
  2599. };
  2600. static const struct soc_enum adc3_enum =
  2601. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  2602. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2603. static const struct snd_kcontrol_new tx_adc3_mux =
  2604. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2605. static const char * const adc4_mux_text[] = {
  2606. "INP5", "INP7"
  2607. };
  2608. static const struct soc_enum adc4_enum =
  2609. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  2610. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  2611. static const struct snd_kcontrol_new tx_adc4_mux =
  2612. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  2613. static const char * const rdac3_mux_text[] = {
  2614. "RX1", "RX3"
  2615. };
  2616. static const char * const hdr12_mux_text[] = {
  2617. "NO_HDR12", "HDR12"
  2618. };
  2619. static const struct soc_enum hdr12_enum =
  2620. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  2621. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  2622. static const struct snd_kcontrol_new tx_hdr12_mux =
  2623. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  2624. static const char * const hdr34_mux_text[] = {
  2625. "NO_HDR34", "HDR34"
  2626. };
  2627. static const struct soc_enum hdr34_enum =
  2628. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  2629. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  2630. static const struct snd_kcontrol_new tx_hdr34_mux =
  2631. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  2632. static const struct soc_enum rdac3_enum =
  2633. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2634. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2635. static const struct snd_kcontrol_new rx_rdac3_mux =
  2636. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2637. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  2638. /*input widgets*/
  2639. SND_SOC_DAPM_INPUT("AMIC1"),
  2640. SND_SOC_DAPM_INPUT("AMIC2"),
  2641. SND_SOC_DAPM_INPUT("AMIC3"),
  2642. SND_SOC_DAPM_INPUT("AMIC4"),
  2643. SND_SOC_DAPM_INPUT("AMIC5"),
  2644. SND_SOC_DAPM_INPUT("AMIC6"),
  2645. SND_SOC_DAPM_INPUT("AMIC7"),
  2646. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2647. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2648. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2649. /*tx widgets*/
  2650. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2651. wcd938x_codec_enable_adc,
  2652. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2653. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2654. wcd938x_codec_enable_adc,
  2655. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2656. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2657. wcd938x_codec_enable_adc,
  2658. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2659. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  2660. wcd938x_codec_enable_adc,
  2661. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2662. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2663. wcd938x_codec_enable_dmic,
  2664. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2665. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2666. wcd938x_codec_enable_dmic,
  2667. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2668. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2669. wcd938x_codec_enable_dmic,
  2670. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2671. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2672. wcd938x_codec_enable_dmic,
  2673. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2674. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2675. wcd938x_codec_enable_dmic,
  2676. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2677. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2678. wcd938x_codec_enable_dmic,
  2679. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2680. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  2681. wcd938x_codec_enable_dmic,
  2682. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2683. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  2684. wcd938x_codec_enable_dmic,
  2685. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2686. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2687. NULL, 0, wcd938x_enable_req,
  2688. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2689. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  2690. NULL, 0, wcd938x_enable_req,
  2691. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2692. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  2693. NULL, 0, wcd938x_enable_req,
  2694. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2695. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  2696. NULL, 0, wcd938x_enable_req,
  2697. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2698. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2699. &tx_adc2_mux),
  2700. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2701. &tx_adc3_mux),
  2702. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  2703. &tx_adc4_mux),
  2704. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  2705. &tx_hdr12_mux),
  2706. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  2707. &tx_hdr34_mux),
  2708. /*tx mixers*/
  2709. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  2710. adc1_switch, ARRAY_SIZE(adc1_switch),
  2711. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2712. SND_SOC_DAPM_POST_PMD),
  2713. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  2714. adc2_switch, ARRAY_SIZE(adc2_switch),
  2715. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2716. SND_SOC_DAPM_POST_PMD),
  2717. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  2718. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  2719. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2720. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
  2721. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  2722. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2723. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2724. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2725. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2726. SND_SOC_DAPM_POST_PMD),
  2727. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  2728. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2729. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2730. SND_SOC_DAPM_POST_PMD),
  2731. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  2732. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2733. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2734. SND_SOC_DAPM_POST_PMD),
  2735. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  2736. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2737. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2738. SND_SOC_DAPM_POST_PMD),
  2739. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  2740. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2741. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2742. SND_SOC_DAPM_POST_PMD),
  2743. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  2744. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2745. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2746. SND_SOC_DAPM_POST_PMD),
  2747. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0,
  2748. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  2749. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2750. SND_SOC_DAPM_POST_PMD),
  2751. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0,
  2752. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  2753. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2754. SND_SOC_DAPM_POST_PMD),
  2755. /* micbias widgets*/
  2756. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2757. wcd938x_codec_enable_micbias,
  2758. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2759. SND_SOC_DAPM_POST_PMD),
  2760. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2761. wcd938x_codec_enable_micbias,
  2762. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2763. SND_SOC_DAPM_POST_PMD),
  2764. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2765. wcd938x_codec_enable_micbias,
  2766. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2767. SND_SOC_DAPM_POST_PMD),
  2768. SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2769. wcd938x_codec_enable_micbias,
  2770. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2771. SND_SOC_DAPM_POST_PMD),
  2772. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0,
  2773. wcd938x_codec_force_enable_micbias,
  2774. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2775. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS2_STANDALONE, SND_SOC_NOPM, 0, 0,
  2776. wcd938x_codec_force_enable_micbias,
  2777. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2778. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS3_STANDALONE, SND_SOC_NOPM, 0, 0,
  2779. wcd938x_codec_force_enable_micbias,
  2780. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2781. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS4_STANDALONE, SND_SOC_NOPM, 0, 0,
  2782. wcd938x_codec_force_enable_micbias,
  2783. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2784. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2785. wcd938x_enable_clsh,
  2786. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2787. /*rx widgets*/
  2788. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  2789. wcd938x_codec_enable_ear_pa,
  2790. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2791. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2792. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  2793. wcd938x_codec_enable_aux_pa,
  2794. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2795. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2796. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  2797. wcd938x_codec_enable_hphl_pa,
  2798. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2799. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2800. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  2801. wcd938x_codec_enable_hphr_pa,
  2802. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2803. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2804. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2805. wcd938x_codec_hphl_dac_event,
  2806. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2807. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2808. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2809. wcd938x_codec_hphr_dac_event,
  2810. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2811. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2812. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2813. wcd938x_codec_ear_dac_event,
  2814. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2815. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2816. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2817. wcd938x_codec_aux_dac_event,
  2818. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2819. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2820. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2821. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2822. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2823. SND_SOC_DAPM_POST_PMD),
  2824. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2825. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2826. SND_SOC_DAPM_POST_PMD),
  2827. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2828. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2829. SND_SOC_DAPM_POST_PMD),
  2830. /* rx mixer widgets*/
  2831. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2832. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2833. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2834. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2835. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2836. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2837. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2838. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2839. /*output widgets tx*/
  2840. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  2841. /*output widgets rx*/
  2842. SND_SOC_DAPM_OUTPUT("EAR"),
  2843. SND_SOC_DAPM_OUTPUT("AUX"),
  2844. SND_SOC_DAPM_OUTPUT("HPHL"),
  2845. SND_SOC_DAPM_OUTPUT("HPHR"),
  2846. /* micbias pull up widgets*/
  2847. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2848. wcd938x_codec_enable_micbias_pullup,
  2849. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2850. SND_SOC_DAPM_POST_PMD),
  2851. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2852. wcd938x_codec_enable_micbias_pullup,
  2853. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2854. SND_SOC_DAPM_POST_PMD),
  2855. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2856. wcd938x_codec_enable_micbias_pullup,
  2857. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2858. SND_SOC_DAPM_POST_PMD),
  2859. SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2860. wcd938x_codec_enable_micbias_pullup,
  2861. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2862. SND_SOC_DAPM_POST_PMD),
  2863. };
  2864. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  2865. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  2866. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2867. {"ADC1 REQ", NULL, "ADC1"},
  2868. {"ADC1", NULL, "AMIC1"},
  2869. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  2870. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2871. {"ADC2 REQ", NULL, "ADC2"},
  2872. {"ADC2", NULL, "HDR12 MUX"},
  2873. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  2874. {"HDR12 MUX", "HDR12", "AMIC1"},
  2875. {"ADC2 MUX", "INP3", "AMIC3"},
  2876. {"ADC2 MUX", "INP2", "AMIC2"},
  2877. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  2878. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2879. {"ADC3 REQ", NULL, "ADC3"},
  2880. {"ADC3", NULL, "HDR34 MUX"},
  2881. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  2882. {"HDR34 MUX", "HDR34", "AMIC5"},
  2883. {"ADC3 MUX", "INP4", "AMIC4"},
  2884. {"ADC3 MUX", "INP6", "AMIC6"},
  2885. {"WCD_TX_OUTPUT", NULL, "ADC4_MIXER"},
  2886. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  2887. {"ADC4 REQ", NULL, "ADC4"},
  2888. {"ADC4", NULL, "ADC4 MUX"},
  2889. {"ADC4 MUX", "INP5", "AMIC5"},
  2890. {"ADC4 MUX", "INP7", "AMIC7"},
  2891. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  2892. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2893. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  2894. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2895. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  2896. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2897. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  2898. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2899. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  2900. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2901. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  2902. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2903. {"WCD_TX_OUTPUT", NULL, "DMIC7_MIXER"},
  2904. {"DMIC7_MIXER", "Switch", "DMIC7"},
  2905. {"WCD_TX_OUTPUT", NULL, "DMIC8_MIXER"},
  2906. {"DMIC8_MIXER", "Switch", "DMIC8"},
  2907. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2908. {"RX1", NULL, "IN1_HPHL"},
  2909. {"RDAC1", NULL, "RX1"},
  2910. {"HPHL_RDAC", "Switch", "RDAC1"},
  2911. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2912. {"HPHL", NULL, "HPHL PGA"},
  2913. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2914. {"RX2", NULL, "IN2_HPHR"},
  2915. {"RDAC2", NULL, "RX2"},
  2916. {"HPHR_RDAC", "Switch", "RDAC2"},
  2917. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2918. {"HPHR", NULL, "HPHR PGA"},
  2919. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2920. {"RX3", NULL, "IN3_AUX"},
  2921. {"RDAC4", NULL, "RX3"},
  2922. {"AUX_RDAC", "Switch", "RDAC4"},
  2923. {"AUX PGA", NULL, "AUX_RDAC"},
  2924. {"AUX", NULL, "AUX PGA"},
  2925. {"RDAC3_MUX", "RX3", "RX3"},
  2926. {"RDAC3_MUX", "RX1", "RX1"},
  2927. {"RDAC3", NULL, "RDAC3_MUX"},
  2928. {"EAR_RDAC", "Switch", "RDAC3"},
  2929. {"EAR PGA", NULL, "EAR_RDAC"},
  2930. {"EAR", NULL, "EAR PGA"},
  2931. };
  2932. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  2933. void *file_private_data,
  2934. struct file *file,
  2935. char __user *buf, size_t count,
  2936. loff_t pos)
  2937. {
  2938. struct wcd938x_priv *priv;
  2939. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  2940. int len = 0;
  2941. priv = (struct wcd938x_priv *) entry->private_data;
  2942. if (!priv) {
  2943. pr_err("%s: wcd938x priv is null\n", __func__);
  2944. return -EINVAL;
  2945. }
  2946. switch (priv->version) {
  2947. case WCD938X_VERSION_1_0:
  2948. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  2949. break;
  2950. default:
  2951. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2952. }
  2953. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2954. }
  2955. static struct snd_info_entry_ops wcd938x_info_ops = {
  2956. .read = wcd938x_version_read,
  2957. };
  2958. static ssize_t wcd938x_variant_read(struct snd_info_entry *entry,
  2959. void *file_private_data,
  2960. struct file *file,
  2961. char __user *buf, size_t count,
  2962. loff_t pos)
  2963. {
  2964. struct wcd938x_priv *priv;
  2965. char buffer[WCD938X_VARIANT_ENTRY_SIZE];
  2966. int len = 0;
  2967. priv = (struct wcd938x_priv *) entry->private_data;
  2968. if (!priv) {
  2969. pr_err("%s: wcd938x priv is null\n", __func__);
  2970. return -EINVAL;
  2971. }
  2972. switch (priv->variant) {
  2973. case WCD9380:
  2974. len = snprintf(buffer, sizeof(buffer), "WCD9380\n");
  2975. break;
  2976. case WCD9385:
  2977. len = snprintf(buffer, sizeof(buffer), "WCD9385\n");
  2978. break;
  2979. default:
  2980. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2981. }
  2982. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2983. }
  2984. static struct snd_info_entry_ops wcd938x_variant_ops = {
  2985. .read = wcd938x_variant_read,
  2986. };
  2987. /*
  2988. * wcd938x_get_codec_variant
  2989. * @component: component instance
  2990. *
  2991. * Return: codec variant or -EINVAL in error.
  2992. */
  2993. int wcd938x_get_codec_variant(struct snd_soc_component *component)
  2994. {
  2995. struct wcd938x_priv *priv = NULL;
  2996. if (!component)
  2997. return -EINVAL;
  2998. priv = snd_soc_component_get_drvdata(component);
  2999. if (!priv) {
  3000. dev_err(component->dev,
  3001. "%s:wcd938x not probed\n", __func__);
  3002. return 0;
  3003. }
  3004. return priv->variant;
  3005. }
  3006. EXPORT_SYMBOL(wcd938x_get_codec_variant);
  3007. /*
  3008. * wcd938x_info_create_codec_entry - creates wcd938x module
  3009. * @codec_root: The parent directory
  3010. * @component: component instance
  3011. *
  3012. * Creates wcd938x module, variant and version entry under the given
  3013. * parent directory.
  3014. *
  3015. * Return: 0 on success or negative error code on failure.
  3016. */
  3017. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  3018. struct snd_soc_component *component)
  3019. {
  3020. struct snd_info_entry *version_entry;
  3021. struct snd_info_entry *variant_entry;
  3022. struct wcd938x_priv *priv;
  3023. struct snd_soc_card *card;
  3024. if (!codec_root || !component)
  3025. return -EINVAL;
  3026. priv = snd_soc_component_get_drvdata(component);
  3027. if (priv->entry) {
  3028. dev_dbg(priv->dev,
  3029. "%s:wcd938x module already created\n", __func__);
  3030. return 0;
  3031. }
  3032. card = component->card;
  3033. priv->entry = snd_info_create_module_entry(codec_root->module,
  3034. "wcd938x", codec_root);
  3035. if (!priv->entry) {
  3036. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  3037. __func__);
  3038. return -ENOMEM;
  3039. }
  3040. priv->entry->mode = S_IFDIR | 0555;
  3041. if (snd_info_register(priv->entry) < 0) {
  3042. snd_info_free_entry(priv->entry);
  3043. return -ENOMEM;
  3044. }
  3045. version_entry = snd_info_create_card_entry(card->snd_card,
  3046. "version",
  3047. priv->entry);
  3048. if (!version_entry) {
  3049. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  3050. __func__);
  3051. snd_info_free_entry(priv->entry);
  3052. return -ENOMEM;
  3053. }
  3054. version_entry->private_data = priv;
  3055. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  3056. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3057. version_entry->c.ops = &wcd938x_info_ops;
  3058. if (snd_info_register(version_entry) < 0) {
  3059. snd_info_free_entry(version_entry);
  3060. snd_info_free_entry(priv->entry);
  3061. return -ENOMEM;
  3062. }
  3063. priv->version_entry = version_entry;
  3064. variant_entry = snd_info_create_card_entry(card->snd_card,
  3065. "variant",
  3066. priv->entry);
  3067. if (!variant_entry) {
  3068. dev_dbg(component->dev, "%s: failed to create wcd938x variant entry\n",
  3069. __func__);
  3070. snd_info_free_entry(version_entry);
  3071. snd_info_free_entry(priv->entry);
  3072. return -ENOMEM;
  3073. }
  3074. variant_entry->private_data = priv;
  3075. variant_entry->size = WCD938X_VARIANT_ENTRY_SIZE;
  3076. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  3077. variant_entry->c.ops = &wcd938x_variant_ops;
  3078. if (snd_info_register(variant_entry) < 0) {
  3079. snd_info_free_entry(variant_entry);
  3080. snd_info_free_entry(version_entry);
  3081. snd_info_free_entry(priv->entry);
  3082. return -ENOMEM;
  3083. }
  3084. priv->variant_entry = variant_entry;
  3085. return 0;
  3086. }
  3087. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  3088. static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x,
  3089. struct wcd938x_pdata *pdata)
  3090. {
  3091. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  3092. int rc = 0;
  3093. if (!pdata) {
  3094. dev_err(wcd938x->dev, "%s: NULL pdata\n", __func__);
  3095. return -ENODEV;
  3096. }
  3097. /* set micbias voltage */
  3098. vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  3099. vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  3100. vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  3101. vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  3102. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  3103. vout_ctl_4 < 0) {
  3104. rc = -EINVAL;
  3105. goto done;
  3106. }
  3107. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 0x3F,
  3108. vout_ctl_1);
  3109. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 0x3F,
  3110. vout_ctl_2);
  3111. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 0x3F,
  3112. vout_ctl_3);
  3113. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 0x3F,
  3114. vout_ctl_4);
  3115. done:
  3116. return rc;
  3117. }
  3118. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  3119. {
  3120. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3121. struct snd_soc_dapm_context *dapm =
  3122. snd_soc_component_get_dapm(component);
  3123. int variant;
  3124. int ret = -EINVAL;
  3125. dev_info(component->dev, "%s()\n", __func__);
  3126. wcd938x = snd_soc_component_get_drvdata(component);
  3127. if (!wcd938x)
  3128. return -EINVAL;
  3129. wcd938x->component = component;
  3130. snd_soc_component_init_regmap(component, wcd938x->regmap);
  3131. variant = (snd_soc_component_read32(component,
  3132. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  3133. wcd938x->variant = variant;
  3134. wcd938x->fw_data = devm_kzalloc(component->dev,
  3135. sizeof(*(wcd938x->fw_data)),
  3136. GFP_KERNEL);
  3137. if (!wcd938x->fw_data) {
  3138. dev_err(component->dev, "Failed to allocate fw_data\n");
  3139. ret = -ENOMEM;
  3140. goto err;
  3141. }
  3142. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  3143. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  3144. WCD9XXX_CODEC_HWDEP_NODE, component);
  3145. if (ret < 0) {
  3146. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  3147. goto err_hwdep;
  3148. }
  3149. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  3150. if (ret) {
  3151. pr_err("%s: mbhc initialization failed\n", __func__);
  3152. goto err_hwdep;
  3153. }
  3154. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3155. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3156. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3157. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3158. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  3159. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  3160. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  3161. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  3162. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3163. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3164. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3165. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3166. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3167. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3168. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3169. snd_soc_dapm_sync(dapm);
  3170. wcd_cls_h_init(&wcd938x->clsh_info);
  3171. wcd938x_init_reg(component);
  3172. if (wcd938x->variant == WCD9380) {
  3173. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  3174. ARRAY_SIZE(wcd9380_snd_controls));
  3175. if (ret < 0) {
  3176. dev_err(component->dev,
  3177. "%s: Failed to add snd ctrls for variant: %d\n",
  3178. __func__, wcd938x->variant);
  3179. goto err_hwdep;
  3180. }
  3181. }
  3182. if (wcd938x->variant == WCD9385) {
  3183. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  3184. ARRAY_SIZE(wcd9385_snd_controls));
  3185. if (ret < 0) {
  3186. dev_err(component->dev,
  3187. "%s: Failed to add snd ctrls for variant: %d\n",
  3188. __func__, wcd938x->variant);
  3189. goto err_hwdep;
  3190. }
  3191. }
  3192. wcd938x->version = WCD938X_VERSION_1_0;
  3193. /* Register event notifier */
  3194. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  3195. if (wcd938x->register_notifier) {
  3196. ret = wcd938x->register_notifier(wcd938x->handle,
  3197. &wcd938x->nblock,
  3198. true);
  3199. if (ret) {
  3200. dev_err(component->dev,
  3201. "%s: Failed to register notifier %d\n",
  3202. __func__, ret);
  3203. return ret;
  3204. }
  3205. }
  3206. wcd938x->dev_up = true;
  3207. return ret;
  3208. err_hwdep:
  3209. wcd938x->fw_data = NULL;
  3210. err:
  3211. return ret;
  3212. }
  3213. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  3214. {
  3215. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3216. if (!wcd938x) {
  3217. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  3218. __func__);
  3219. return;
  3220. }
  3221. if (wcd938x->register_notifier)
  3222. wcd938x->register_notifier(wcd938x->handle,
  3223. &wcd938x->nblock,
  3224. false);
  3225. }
  3226. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  3227. .name = WCD938X_DRV_NAME,
  3228. .probe = wcd938x_soc_codec_probe,
  3229. .remove = wcd938x_soc_codec_remove,
  3230. .controls = wcd938x_snd_controls,
  3231. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  3232. .dapm_widgets = wcd938x_dapm_widgets,
  3233. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  3234. .dapm_routes = wcd938x_audio_map,
  3235. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  3236. };
  3237. static int wcd938x_reset(struct device *dev)
  3238. {
  3239. struct wcd938x_priv *wcd938x = NULL;
  3240. int rc = 0;
  3241. int value = 0;
  3242. if (!dev)
  3243. return -ENODEV;
  3244. wcd938x = dev_get_drvdata(dev);
  3245. if (!wcd938x)
  3246. return -EINVAL;
  3247. if (!wcd938x->rst_np) {
  3248. dev_err(dev, "%s: reset gpio device node not specified\n",
  3249. __func__);
  3250. return -EINVAL;
  3251. }
  3252. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  3253. if (value > 0)
  3254. return 0;
  3255. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3256. if (rc) {
  3257. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3258. __func__);
  3259. return rc;
  3260. }
  3261. /* 20us sleep required after pulling the reset gpio to LOW */
  3262. usleep_range(20, 30);
  3263. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  3264. if (rc) {
  3265. dev_err(dev, "%s: wcd active state request fail!\n",
  3266. __func__);
  3267. return rc;
  3268. }
  3269. /* 20us sleep required after pulling the reset gpio to HIGH */
  3270. usleep_range(20, 30);
  3271. return rc;
  3272. }
  3273. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  3274. u32 *val)
  3275. {
  3276. int rc = 0;
  3277. rc = of_property_read_u32(dev->of_node, name, val);
  3278. if (rc)
  3279. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3280. __func__, name, dev->of_node->full_name);
  3281. return rc;
  3282. }
  3283. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  3284. struct wcd938x_micbias_setting *mb)
  3285. {
  3286. u32 prop_val = 0;
  3287. int rc = 0;
  3288. /* MB1 */
  3289. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3290. NULL)) {
  3291. rc = wcd938x_read_of_property_u32(dev,
  3292. "qcom,cdc-micbias1-mv",
  3293. &prop_val);
  3294. if (!rc)
  3295. mb->micb1_mv = prop_val;
  3296. } else {
  3297. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3298. __func__);
  3299. }
  3300. /* MB2 */
  3301. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3302. NULL)) {
  3303. rc = wcd938x_read_of_property_u32(dev,
  3304. "qcom,cdc-micbias2-mv",
  3305. &prop_val);
  3306. if (!rc)
  3307. mb->micb2_mv = prop_val;
  3308. } else {
  3309. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3310. __func__);
  3311. }
  3312. /* MB3 */
  3313. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3314. NULL)) {
  3315. rc = wcd938x_read_of_property_u32(dev,
  3316. "qcom,cdc-micbias3-mv",
  3317. &prop_val);
  3318. if (!rc)
  3319. mb->micb3_mv = prop_val;
  3320. } else {
  3321. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3322. __func__);
  3323. }
  3324. /* MB4 */
  3325. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  3326. NULL)) {
  3327. rc = wcd938x_read_of_property_u32(dev,
  3328. "qcom,cdc-micbias4-mv",
  3329. &prop_val);
  3330. if (!rc)
  3331. mb->micb4_mv = prop_val;
  3332. } else {
  3333. dev_info(dev, "%s: Micbias4 DT property not found\n",
  3334. __func__);
  3335. }
  3336. }
  3337. static int wcd938x_reset_low(struct device *dev)
  3338. {
  3339. struct wcd938x_priv *wcd938x = NULL;
  3340. int rc = 0;
  3341. if (!dev)
  3342. return -ENODEV;
  3343. wcd938x = dev_get_drvdata(dev);
  3344. if (!wcd938x)
  3345. return -EINVAL;
  3346. if (!wcd938x->rst_np) {
  3347. dev_err(dev, "%s: reset gpio device node not specified\n",
  3348. __func__);
  3349. return -EINVAL;
  3350. }
  3351. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3352. if (rc) {
  3353. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3354. __func__);
  3355. return rc;
  3356. }
  3357. /* 20us sleep required after pulling the reset gpio to LOW */
  3358. usleep_range(20, 30);
  3359. return rc;
  3360. }
  3361. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  3362. {
  3363. struct wcd938x_pdata *pdata = NULL;
  3364. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  3365. GFP_KERNEL);
  3366. if (!pdata)
  3367. return NULL;
  3368. pdata->rst_np = of_parse_phandle(dev->of_node,
  3369. "qcom,wcd-rst-gpio-node", 0);
  3370. if (!pdata->rst_np) {
  3371. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3372. __func__, "qcom,wcd-rst-gpio-node",
  3373. dev->of_node->full_name);
  3374. return NULL;
  3375. }
  3376. /* Parse power supplies */
  3377. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3378. &pdata->num_supplies);
  3379. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3380. dev_err(dev, "%s: no power supplies defined for codec\n",
  3381. __func__);
  3382. return NULL;
  3383. }
  3384. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3385. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3386. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  3387. return pdata;
  3388. }
  3389. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  3390. {
  3391. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  3392. __func__, irq);
  3393. return IRQ_HANDLED;
  3394. }
  3395. static struct snd_soc_dai_driver wcd938x_dai[] = {
  3396. {
  3397. .name = "wcd938x_cdc",
  3398. .playback = {
  3399. .stream_name = "WCD938X_AIF Playback",
  3400. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3401. .formats = WCD938X_FORMATS,
  3402. .rate_max = 192000,
  3403. .rate_min = 8000,
  3404. .channels_min = 1,
  3405. .channels_max = 4,
  3406. },
  3407. .capture = {
  3408. .stream_name = "WCD938X_AIF Capture",
  3409. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3410. .formats = WCD938X_FORMATS,
  3411. .rate_max = 192000,
  3412. .rate_min = 8000,
  3413. .channels_min = 1,
  3414. .channels_max = 4,
  3415. },
  3416. },
  3417. };
  3418. static int wcd938x_bind(struct device *dev)
  3419. {
  3420. int ret = 0, i = 0;
  3421. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  3422. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3423. /*
  3424. * Add 5msec delay to provide sufficient time for
  3425. * soundwire auto enumeration of slave devices as
  3426. * as per HW requirement.
  3427. */
  3428. usleep_range(5000, 5010);
  3429. ret = component_bind_all(dev, wcd938x);
  3430. if (ret) {
  3431. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3432. __func__, ret);
  3433. return ret;
  3434. }
  3435. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3436. if (!wcd938x->rx_swr_dev) {
  3437. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3438. __func__);
  3439. ret = -ENODEV;
  3440. goto err;
  3441. }
  3442. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3443. if (!wcd938x->tx_swr_dev) {
  3444. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3445. __func__);
  3446. ret = -ENODEV;
  3447. goto err;
  3448. }
  3449. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  3450. &wcd938x_regmap_config);
  3451. if (!wcd938x->regmap) {
  3452. dev_err(dev, "%s: Regmap init failed\n",
  3453. __func__);
  3454. goto err;
  3455. }
  3456. /* Set all interupts as edge triggered */
  3457. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  3458. regmap_write(wcd938x->regmap,
  3459. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  3460. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  3461. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  3462. wcd938x->irq_info.codec_name = "WCD938X";
  3463. wcd938x->irq_info.regmap = wcd938x->regmap;
  3464. wcd938x->irq_info.dev = dev;
  3465. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  3466. if (ret) {
  3467. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  3468. __func__, ret);
  3469. goto err;
  3470. }
  3471. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  3472. ret = wcd938x_set_micbias_data(wcd938x, pdata);
  3473. if (ret < 0) {
  3474. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  3475. goto err_irq;
  3476. }
  3477. /* Request for watchdog interrupt */
  3478. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  3479. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3480. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  3481. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3482. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  3483. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3484. /* Disable watchdog interrupt for HPH and AUX */
  3485. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  3486. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  3487. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  3488. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  3489. wcd938x_dai, ARRAY_SIZE(wcd938x_dai));
  3490. if (ret) {
  3491. dev_err(dev, "%s: Codec registration failed\n",
  3492. __func__);
  3493. goto err_irq;
  3494. }
  3495. return ret;
  3496. err_irq:
  3497. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3498. err:
  3499. component_unbind_all(dev, wcd938x);
  3500. return ret;
  3501. }
  3502. static void wcd938x_unbind(struct device *dev)
  3503. {
  3504. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3505. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT, NULL);
  3506. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT, NULL);
  3507. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT, NULL);
  3508. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3509. snd_soc_unregister_component(dev);
  3510. component_unbind_all(dev, wcd938x);
  3511. }
  3512. static const struct of_device_id wcd938x_dt_match[] = {
  3513. { .compatible = "qcom,wcd938x-codec" },
  3514. {}
  3515. };
  3516. static const struct component_master_ops wcd938x_comp_ops = {
  3517. .bind = wcd938x_bind,
  3518. .unbind = wcd938x_unbind,
  3519. };
  3520. static int wcd938x_compare_of(struct device *dev, void *data)
  3521. {
  3522. return dev->of_node == data;
  3523. }
  3524. static void wcd938x_release_of(struct device *dev, void *data)
  3525. {
  3526. of_node_put(data);
  3527. }
  3528. static int wcd938x_add_slave_components(struct device *dev,
  3529. struct component_match **matchptr)
  3530. {
  3531. struct device_node *np, *rx_node, *tx_node;
  3532. np = dev->of_node;
  3533. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3534. if (!rx_node) {
  3535. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3536. return -ENODEV;
  3537. }
  3538. of_node_get(rx_node);
  3539. component_match_add_release(dev, matchptr,
  3540. wcd938x_release_of,
  3541. wcd938x_compare_of,
  3542. rx_node);
  3543. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3544. if (!tx_node) {
  3545. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3546. return -ENODEV;
  3547. }
  3548. of_node_get(tx_node);
  3549. component_match_add_release(dev, matchptr,
  3550. wcd938x_release_of,
  3551. wcd938x_compare_of,
  3552. tx_node);
  3553. return 0;
  3554. }
  3555. static int wcd938x_probe(struct platform_device *pdev)
  3556. {
  3557. struct component_match *match = NULL;
  3558. struct wcd938x_priv *wcd938x = NULL;
  3559. struct wcd938x_pdata *pdata = NULL;
  3560. struct wcd_ctrl_platform_data *plat_data = NULL;
  3561. struct device *dev = &pdev->dev;
  3562. int ret;
  3563. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  3564. GFP_KERNEL);
  3565. if (!wcd938x)
  3566. return -ENOMEM;
  3567. dev_set_drvdata(dev, wcd938x);
  3568. wcd938x->dev = dev;
  3569. pdata = wcd938x_populate_dt_data(dev);
  3570. if (!pdata) {
  3571. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3572. return -EINVAL;
  3573. }
  3574. dev->platform_data = pdata;
  3575. wcd938x->rst_np = pdata->rst_np;
  3576. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  3577. pdata->regulator, pdata->num_supplies);
  3578. if (!wcd938x->supplies) {
  3579. dev_err(dev, "%s: Cannot init wcd supplies\n",
  3580. __func__);
  3581. return ret;
  3582. }
  3583. plat_data = dev_get_platdata(dev->parent);
  3584. if (!plat_data) {
  3585. dev_err(dev, "%s: platform data from parent is NULL\n",
  3586. __func__);
  3587. return -EINVAL;
  3588. }
  3589. wcd938x->handle = (void *)plat_data->handle;
  3590. if (!wcd938x->handle) {
  3591. dev_err(dev, "%s: handle is NULL\n", __func__);
  3592. return -EINVAL;
  3593. }
  3594. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  3595. if (!wcd938x->update_wcd_event) {
  3596. dev_err(dev, "%s: update_wcd_event api is null!\n",
  3597. __func__);
  3598. return -EINVAL;
  3599. }
  3600. wcd938x->register_notifier = plat_data->register_notifier;
  3601. if (!wcd938x->register_notifier) {
  3602. dev_err(dev, "%s: register_notifier api is null!\n",
  3603. __func__);
  3604. return -EINVAL;
  3605. }
  3606. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  3607. pdata->regulator,
  3608. pdata->num_supplies);
  3609. if (ret) {
  3610. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3611. __func__);
  3612. return ret;
  3613. }
  3614. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  3615. CODEC_RX);
  3616. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  3617. CODEC_TX);
  3618. if (ret) {
  3619. dev_err(dev, "Failed to read port mapping\n");
  3620. goto err;
  3621. }
  3622. mutex_init(&wcd938x->wakeup_lock);
  3623. mutex_init(&wcd938x->micb_lock);
  3624. ret = wcd938x_add_slave_components(dev, &match);
  3625. if (ret)
  3626. goto err_lock_init;
  3627. wcd938x_reset(dev);
  3628. wcd938x->wakeup = wcd938x_wakeup;
  3629. return component_master_add_with_match(dev,
  3630. &wcd938x_comp_ops, match);
  3631. err_lock_init:
  3632. mutex_destroy(&wcd938x->micb_lock);
  3633. mutex_destroy(&wcd938x->wakeup_lock);
  3634. err:
  3635. return ret;
  3636. }
  3637. static int wcd938x_remove(struct platform_device *pdev)
  3638. {
  3639. struct wcd938x_priv *wcd938x = NULL;
  3640. wcd938x = platform_get_drvdata(pdev);
  3641. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  3642. mutex_destroy(&wcd938x->micb_lock);
  3643. mutex_destroy(&wcd938x->wakeup_lock);
  3644. dev_set_drvdata(&pdev->dev, NULL);
  3645. return 0;
  3646. }
  3647. #ifdef CONFIG_PM_SLEEP
  3648. static int wcd938x_suspend(struct device *dev)
  3649. {
  3650. return 0;
  3651. }
  3652. static int wcd938x_resume(struct device *dev)
  3653. {
  3654. return 0;
  3655. }
  3656. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  3657. SET_SYSTEM_SLEEP_PM_OPS(
  3658. wcd938x_suspend,
  3659. wcd938x_resume
  3660. )
  3661. };
  3662. #endif
  3663. static struct platform_driver wcd938x_codec_driver = {
  3664. .probe = wcd938x_probe,
  3665. .remove = wcd938x_remove,
  3666. .driver = {
  3667. .name = "wcd938x_codec",
  3668. .owner = THIS_MODULE,
  3669. .of_match_table = of_match_ptr(wcd938x_dt_match),
  3670. #ifdef CONFIG_PM_SLEEP
  3671. .pm = &wcd938x_dev_pm_ops,
  3672. #endif
  3673. .suppress_bind_attrs = true,
  3674. },
  3675. };
  3676. module_platform_driver(wcd938x_codec_driver);
  3677. MODULE_DESCRIPTION("WCD938X Codec driver");
  3678. MODULE_LICENSE("GPL v2");