internal.h 4.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _WCD938X_INTERNAL_H
  6. #define _WCD938X_INTERNAL_H
  7. #include <asoc/wcd-mbhc-v2.h>
  8. #include <asoc/wcd-irq.h>
  9. #include <asoc/wcd-clsh.h>
  10. #include "wcd938x-mbhc.h"
  11. #include "wcd938x.h"
  12. #define SWR_SCP_CONTROL 0x44
  13. #define SWR_SCP_HOST_CLK_DIV2_CTL_BANK 0xE0
  14. #define WCD938X_MAX_MICBIAS 4
  15. /* Convert from vout ctl to micbias voltage in mV */
  16. #define WCD_VOUT_CTL_TO_MICB(v) (1000 + v * 50)
  17. #define MAX_PORT 8
  18. #define MAX_CH_PER_PORT 8
  19. #define TX_ADC_MAX 4
  20. enum {
  21. TX_HDR12 = 0,
  22. TX_HDR34,
  23. TX_HDR_MAX,
  24. };
  25. extern struct regmap_config wcd938x_regmap_config;
  26. struct codec_port_info {
  27. u32 slave_port_type;
  28. u32 master_port_type;
  29. u32 ch_mask;
  30. u32 num_ch;
  31. u32 ch_rate;
  32. };
  33. struct wcd938x_priv {
  34. struct device *dev;
  35. int variant;
  36. struct snd_soc_component *component;
  37. struct device_node *rst_np;
  38. struct regmap *regmap;
  39. struct swr_device *rx_swr_dev;
  40. struct swr_device *tx_swr_dev;
  41. s32 micb_ref[WCD938X_MAX_MICBIAS];
  42. s32 pullup_ref[WCD938X_MAX_MICBIAS];
  43. struct fw_info *fw_data;
  44. struct device_node *wcd_rst_np;
  45. struct mutex micb_lock;
  46. struct mutex wakeup_lock;
  47. s32 dmic_0_1_clk_cnt;
  48. s32 dmic_2_3_clk_cnt;
  49. s32 dmic_4_5_clk_cnt;
  50. s32 dmic_6_7_clk_cnt;
  51. int hdr_en[TX_HDR_MAX];
  52. /* class h specific info */
  53. struct wcd_clsh_cdc_info clsh_info;
  54. /* mbhc module */
  55. struct wcd938x_mbhc *mbhc;
  56. u32 hph_mode;
  57. u32 tx_mode[TX_ADC_MAX];
  58. bool comp1_enable;
  59. bool comp2_enable;
  60. bool ldoh;
  61. bool bcs_dis;
  62. struct irq_domain *virq;
  63. struct wcd_irq_info irq_info;
  64. u32 rx_clk_cnt;
  65. int num_irq_regs;
  66. /* to track the status */
  67. unsigned long status_mask;
  68. u8 num_tx_ports;
  69. u8 num_rx_ports;
  70. struct codec_port_info
  71. tx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
  72. struct codec_port_info
  73. rx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
  74. struct regulator_bulk_data *supplies;
  75. struct notifier_block nblock;
  76. /* wcd callback to bolero */
  77. void *handle;
  78. int (*update_wcd_event)(void *handle, u16 event, u32 data);
  79. int (*register_notifier)(void *handle,
  80. struct notifier_block *nblock,
  81. bool enable);
  82. int (*wakeup)(void *handle, bool enable);
  83. u32 version;
  84. /* Entry for version info */
  85. struct snd_info_entry *entry;
  86. struct snd_info_entry *version_entry;
  87. struct snd_info_entry *variant_entry;
  88. int flyback_cur_det_disable;
  89. int ear_rx_path;
  90. bool dev_up;
  91. u8 tx_master_ch_map[WCD938X_MAX_SLAVE_CH_TYPES];
  92. };
  93. struct wcd938x_micbias_setting {
  94. u8 ldoh_v;
  95. u32 cfilt1_mv;
  96. u32 micb1_mv;
  97. u32 micb2_mv;
  98. u32 micb3_mv;
  99. u32 micb4_mv;
  100. u8 bias1_cfilt_sel;
  101. };
  102. struct wcd938x_pdata {
  103. struct device_node *rst_np;
  104. struct device_node *rx_slave;
  105. struct device_node *tx_slave;
  106. struct wcd938x_micbias_setting micbias;
  107. struct cdc_regulator *regulator;
  108. int num_supplies;
  109. };
  110. struct wcd_ctrl_platform_data {
  111. void *handle;
  112. int (*update_wcd_event)(void *handle, u16 event, u32 data);
  113. int (*register_notifier)(void *handle,
  114. struct notifier_block *nblock,
  115. bool enable);
  116. };
  117. enum {
  118. WCD_RX1,
  119. WCD_RX2,
  120. WCD_RX3
  121. };
  122. enum {
  123. BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR = 1,
  124. BOLERO_WCD_EVT_PA_OFF_PRE_SSR,
  125. BOLERO_WCD_EVT_SSR_DOWN,
  126. BOLERO_WCD_EVT_SSR_UP,
  127. BOLERO_WCD_EVT_CLK_NOTIFY,
  128. };
  129. enum {
  130. WCD_BOLERO_EVT_RX_MUTE = 1, /* for RX mute/unmute */
  131. WCD_BOLERO_EVT_IMPED_TRUE, /* for imped true */
  132. WCD_BOLERO_EVT_IMPED_FALSE, /* for imped false */
  133. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  134. WCD_BOLERO_EVT_BCS_CLK_OFF,
  135. };
  136. enum {
  137. /* INTR_CTRL_INT_MASK_0 */
  138. WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET = 0,
  139. WCD938X_IRQ_MBHC_BUTTON_PRESS_DET,
  140. WCD938X_IRQ_MBHC_ELECT_INS_REM_DET,
  141. WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
  142. WCD938X_IRQ_MBHC_SW_DET,
  143. WCD938X_IRQ_HPHR_OCP_INT,
  144. WCD938X_IRQ_HPHR_CNP_INT,
  145. WCD938X_IRQ_HPHL_OCP_INT,
  146. /* INTR_CTRL_INT_MASK_1 */
  147. WCD938X_IRQ_HPHL_CNP_INT,
  148. WCD938X_IRQ_EAR_CNP_INT,
  149. WCD938X_IRQ_EAR_SCD_INT,
  150. WCD938X_IRQ_AUX_CNP_INT,
  151. WCD938X_IRQ_AUX_SCD_INT,
  152. WCD938X_IRQ_HPHL_PDM_WD_INT,
  153. WCD938X_IRQ_HPHR_PDM_WD_INT,
  154. WCD938X_IRQ_AUX_PDM_WD_INT,
  155. /* INTR_CTRL_INT_MASK_2 */
  156. WCD938X_IRQ_LDORT_SCD_INT,
  157. WCD938X_IRQ_MBHC_MOISTURE_INT,
  158. WCD938X_IRQ_HPHL_SURGE_DET_INT,
  159. WCD938X_IRQ_HPHR_SURGE_DET_INT,
  160. WCD938X_NUM_IRQS,
  161. };
  162. extern struct wcd938x_mbhc *wcd938x_soc_get_mbhc(
  163. struct snd_soc_component *component);
  164. extern void wcd938x_disable_bcs_before_slow_insert(
  165. struct snd_soc_component *component,
  166. bool bcs_disable);
  167. extern int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  168. int volt, int micb_num);
  169. extern int wcd938x_get_micb_vout_ctl_val(u32 micb_mv);
  170. extern int wcd938x_micbias_control(struct snd_soc_component *component,
  171. int micb_num, int req, bool is_dapm);
  172. #endif /* _WCD938X_INTERNAL_H */