wcd938x.c 97 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "internal.h"
  23. #include "wcd938x-registers.h"
  24. #define WCD938X_DRV_NAME "wcd938x_codec"
  25. #define NUM_SWRS_DT_PARAMS 5
  26. #define WCD938X_VARIANT_ENTRY_SIZE 32
  27. #define WCD938X_VERSION_1_0 1
  28. #define WCD938X_VERSION_ENTRY_SIZE 32
  29. #define EAR_RX_PATH_AUX 1
  30. #define ADC_MODE_VAL_HIFI 0x01
  31. #define ADC_MODE_VAL_LO_HIF 0x02
  32. #define ADC_MODE_VAL_NORMAL 0x03
  33. #define ADC_MODE_VAL_LP 0x05
  34. #define ADC_MODE_VAL_ULP1 0x09
  35. #define ADC_MODE_VAL_ULP2 0x0B
  36. enum {
  37. WCD9380 = 0,
  38. WCD9385 = 5,
  39. };
  40. enum {
  41. CODEC_TX = 0,
  42. CODEC_RX,
  43. };
  44. enum {
  45. WCD_ADC1 = 0,
  46. WCD_ADC2,
  47. WCD_ADC3,
  48. WCD_ADC4,
  49. ALLOW_BUCK_DISABLE,
  50. HPH_COMP_DELAY,
  51. HPH_PA_DELAY,
  52. AMIC2_BCS_ENABLE,
  53. };
  54. enum {
  55. ADC_MODE_INVALID = 0,
  56. ADC_MODE_HIFI,
  57. ADC_MODE_LO_HIF,
  58. ADC_MODE_NORMAL,
  59. ADC_MODE_LP,
  60. ADC_MODE_ULP1,
  61. ADC_MODE_ULP2,
  62. };
  63. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  64. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  65. static int wcd938x_handle_post_irq(void *data);
  66. static int wcd938x_reset(struct device *dev);
  67. static int wcd938x_reset_low(struct device *dev);
  68. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  69. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  70. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  71. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  72. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  73. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  74. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  75. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  76. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  77. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  78. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  79. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  80. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  81. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  82. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  83. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  84. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  85. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  86. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  87. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  88. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  89. };
  90. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  91. .name = "wcd938x",
  92. .irqs = wcd938x_irqs,
  93. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  94. .num_regs = 3,
  95. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  96. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  97. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  98. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  99. .use_ack = 1,
  100. .runtime_pm = false,
  101. .handle_post_irq = wcd938x_handle_post_irq,
  102. .irq_drv_data = NULL,
  103. };
  104. static int wcd938x_handle_post_irq(void *data)
  105. {
  106. struct wcd938x_priv *wcd938x = data;
  107. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  108. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  109. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  110. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  111. wcd938x->tx_swr_dev->slave_irq_pending =
  112. ((sts1 || sts2 || sts3) ? true : false);
  113. return IRQ_HANDLED;
  114. }
  115. static int wcd938x_init_reg(struct snd_soc_component *component)
  116. {
  117. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  118. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  119. /* 1 msec delay as per HW requirement */
  120. usleep_range(1000, 1010);
  121. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  122. /* 1 msec delay as per HW requirement */
  123. usleep_range(1000, 1010);
  124. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  125. 0x10, 0x00);
  126. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  127. 0xF0, 0x80);
  128. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  129. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  130. /* 10 msec delay as per HW requirement */
  131. usleep_range(10000, 10010);
  132. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  133. snd_soc_component_update_bits(component,
  134. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  135. 0xF0, 0x00);
  136. snd_soc_component_update_bits(component,
  137. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  138. 0x1F, 0x15);
  139. snd_soc_component_update_bits(component,
  140. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  141. 0x1F, 0x15);
  142. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  143. 0xC0, 0x80);
  144. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  145. 0x02, 0x02);
  146. snd_soc_component_update_bits(component,
  147. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  148. 0xFF, 0x14);
  149. snd_soc_component_update_bits(component,
  150. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  151. 0x1F, 0x08);
  152. snd_soc_component_update_bits(component,
  153. WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
  154. snd_soc_component_update_bits(component,
  155. WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
  156. snd_soc_component_update_bits(component,
  157. WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
  158. snd_soc_component_update_bits(component,
  159. WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
  160. snd_soc_component_update_bits(component,
  161. WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
  162. return 0;
  163. }
  164. static int wcd938x_set_port_params(struct snd_soc_component *component,
  165. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  166. u8 *ch_mask, u32 *ch_rate,
  167. u8 *port_type, u8 path)
  168. {
  169. int i, j;
  170. u8 num_ports = 0;
  171. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  172. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  173. switch (path) {
  174. case CODEC_RX:
  175. map = &wcd938x->rx_port_mapping;
  176. num_ports = wcd938x->num_rx_ports;
  177. break;
  178. case CODEC_TX:
  179. map = &wcd938x->tx_port_mapping;
  180. num_ports = wcd938x->num_tx_ports;
  181. break;
  182. default:
  183. dev_err(component->dev, "%s Invalid path selected %u\n",
  184. __func__, path);
  185. return -EINVAL;
  186. }
  187. for (i = 0; i <= num_ports; i++) {
  188. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  189. if ((*map)[i][j].slave_port_type == slv_prt_type)
  190. goto found;
  191. }
  192. }
  193. found:
  194. if (i > num_ports || j == MAX_CH_PER_PORT) {
  195. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  196. __func__, slv_prt_type);
  197. return -EINVAL;
  198. }
  199. *port_id = i;
  200. *num_ch = (*map)[i][j].num_ch;
  201. *ch_mask = (*map)[i][j].ch_mask;
  202. *ch_rate = (*map)[i][j].ch_rate;
  203. *port_type = (*map)[i][j].master_port_type;
  204. return 0;
  205. }
  206. static int wcd938x_parse_port_mapping(struct device *dev,
  207. char *prop, u8 path)
  208. {
  209. u32 *dt_array, map_size, map_length;
  210. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  211. u32 slave_port_type, master_port_type;
  212. u32 i, ch_iter = 0;
  213. int ret = 0;
  214. u8 *num_ports = NULL;
  215. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  216. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  217. switch (path) {
  218. case CODEC_RX:
  219. map = &wcd938x->rx_port_mapping;
  220. num_ports = &wcd938x->num_rx_ports;
  221. break;
  222. case CODEC_TX:
  223. map = &wcd938x->tx_port_mapping;
  224. num_ports = &wcd938x->num_tx_ports;
  225. break;
  226. default:
  227. dev_err(dev, "%s Invalid path selected %u\n",
  228. __func__, path);
  229. return -EINVAL;
  230. }
  231. if (!of_find_property(dev->of_node, prop,
  232. &map_size)) {
  233. dev_err(dev, "missing port mapping prop %s\n", prop);
  234. ret = -EINVAL;
  235. goto err_port_map;
  236. }
  237. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  238. dt_array = kzalloc(map_size, GFP_KERNEL);
  239. if (!dt_array) {
  240. ret = -ENOMEM;
  241. goto err_alloc;
  242. }
  243. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  244. NUM_SWRS_DT_PARAMS * map_length);
  245. if (ret) {
  246. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  247. __func__, prop);
  248. goto err_pdata_fail;
  249. }
  250. for (i = 0; i < map_length; i++) {
  251. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  252. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  253. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  254. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  255. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  256. if (port_num != old_port_num)
  257. ch_iter = 0;
  258. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  259. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  260. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  261. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  262. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  263. old_port_num = port_num;
  264. }
  265. *num_ports = port_num;
  266. kfree(dt_array);
  267. return 0;
  268. err_pdata_fail:
  269. kfree(dt_array);
  270. err_alloc:
  271. err_port_map:
  272. return ret;
  273. }
  274. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  275. u8 slv_port_type, u8 enable)
  276. {
  277. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  278. u8 port_id, num_ch, ch_mask, port_type;
  279. u32 ch_rate;
  280. u8 num_port = 1;
  281. int ret = 0;
  282. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  283. &num_ch, &ch_mask, &ch_rate,
  284. &port_type, CODEC_TX);
  285. if (ret)
  286. return ret;
  287. if (enable)
  288. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  289. num_port, &ch_mask, &ch_rate,
  290. &num_ch, &port_type);
  291. else
  292. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  293. num_port, &ch_mask, &port_type);
  294. return ret;
  295. }
  296. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  297. u8 slv_port_type, u8 enable)
  298. {
  299. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  300. u8 port_id, num_ch, ch_mask, port_type;
  301. u32 ch_rate;
  302. u8 num_port = 1;
  303. int ret = 0;
  304. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  305. &num_ch, &ch_mask, &ch_rate,
  306. &port_type, CODEC_RX);
  307. if (ret)
  308. return ret;
  309. if (enable)
  310. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  311. num_port, &ch_mask, &ch_rate,
  312. &num_ch, &port_type);
  313. else
  314. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  315. num_port, &ch_mask, &port_type);
  316. return ret;
  317. }
  318. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  319. {
  320. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  321. if (wcd938x->rx_clk_cnt == 0) {
  322. snd_soc_component_update_bits(component,
  323. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  324. snd_soc_component_update_bits(component,
  325. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  326. snd_soc_component_update_bits(component,
  327. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  328. snd_soc_component_update_bits(component,
  329. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  330. snd_soc_component_update_bits(component,
  331. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  332. snd_soc_component_update_bits(component,
  333. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  334. snd_soc_component_update_bits(component,
  335. WCD938X_AUX_AUXPA, 0x10, 0x10);
  336. }
  337. wcd938x->rx_clk_cnt++;
  338. return 0;
  339. }
  340. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  341. {
  342. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  343. wcd938x->rx_clk_cnt--;
  344. if (wcd938x->rx_clk_cnt == 0) {
  345. snd_soc_component_update_bits(component,
  346. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  347. snd_soc_component_update_bits(component,
  348. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  349. snd_soc_component_update_bits(component,
  350. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  351. snd_soc_component_update_bits(component,
  352. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  353. snd_soc_component_update_bits(component,
  354. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  355. }
  356. return 0;
  357. }
  358. /*
  359. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  360. * @component: handle to snd_soc_component *
  361. *
  362. * return wcd938x_mbhc handle or error code in case of failure
  363. */
  364. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  365. {
  366. struct wcd938x_priv *wcd938x;
  367. if (!component) {
  368. pr_err("%s: Invalid params, NULL component\n", __func__);
  369. return NULL;
  370. }
  371. wcd938x = snd_soc_component_get_drvdata(component);
  372. if (!wcd938x) {
  373. pr_err("%s: wcd938x is NULL\n", __func__);
  374. return NULL;
  375. }
  376. return wcd938x->mbhc;
  377. }
  378. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  379. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  380. struct snd_kcontrol *kcontrol,
  381. int event)
  382. {
  383. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  384. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  385. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  386. w->name, event);
  387. switch (event) {
  388. case SND_SOC_DAPM_PRE_PMU:
  389. wcd938x_rx_clk_enable(component);
  390. snd_soc_component_update_bits(component,
  391. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  392. snd_soc_component_update_bits(component,
  393. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  394. snd_soc_component_update_bits(component,
  395. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  396. break;
  397. case SND_SOC_DAPM_POST_PMU:
  398. snd_soc_component_update_bits(component,
  399. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  400. if (wcd938x->comp1_enable) {
  401. snd_soc_component_update_bits(component,
  402. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  403. /* 5msec compander delay as per HW requirement */
  404. if (!wcd938x->comp2_enable ||
  405. (snd_soc_component_read32(component,
  406. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  407. usleep_range(5000, 5010);
  408. snd_soc_component_update_bits(component,
  409. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  410. } else {
  411. snd_soc_component_update_bits(component,
  412. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  413. 0x02, 0x00);
  414. snd_soc_component_update_bits(component,
  415. WCD938X_HPH_L_EN, 0x20, 0x20);
  416. }
  417. break;
  418. case SND_SOC_DAPM_POST_PMD:
  419. snd_soc_component_update_bits(component,
  420. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  421. 0x0F, 0x01);
  422. break;
  423. }
  424. return 0;
  425. }
  426. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  427. struct snd_kcontrol *kcontrol,
  428. int event)
  429. {
  430. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  431. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  432. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  433. w->name, event);
  434. switch (event) {
  435. case SND_SOC_DAPM_PRE_PMU:
  436. wcd938x_rx_clk_enable(component);
  437. snd_soc_component_update_bits(component,
  438. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  439. snd_soc_component_update_bits(component,
  440. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  441. snd_soc_component_update_bits(component,
  442. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  443. break;
  444. case SND_SOC_DAPM_POST_PMU:
  445. snd_soc_component_update_bits(component,
  446. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  447. if (wcd938x->comp2_enable) {
  448. snd_soc_component_update_bits(component,
  449. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  450. /* 5msec compander delay as per HW requirement */
  451. if (!wcd938x->comp1_enable ||
  452. (snd_soc_component_read32(component,
  453. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  454. usleep_range(5000, 5010);
  455. snd_soc_component_update_bits(component,
  456. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  457. } else {
  458. snd_soc_component_update_bits(component,
  459. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  460. 0x01, 0x00);
  461. snd_soc_component_update_bits(component,
  462. WCD938X_HPH_R_EN, 0x20, 0x20);
  463. }
  464. break;
  465. case SND_SOC_DAPM_POST_PMD:
  466. snd_soc_component_update_bits(component,
  467. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  468. 0x0F, 0x01);
  469. break;
  470. }
  471. return 0;
  472. }
  473. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  474. struct snd_kcontrol *kcontrol,
  475. int event)
  476. {
  477. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  478. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  479. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  480. w->name, event);
  481. switch (event) {
  482. case SND_SOC_DAPM_PRE_PMU:
  483. wcd938x_rx_clk_enable(component);
  484. snd_soc_component_update_bits(component,
  485. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  486. snd_soc_component_update_bits(component,
  487. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  488. snd_soc_component_update_bits(component,
  489. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  490. /* 5 msec delay as per HW requirement */
  491. usleep_range(5000, 5010);
  492. if (wcd938x->flyback_cur_det_disable == 0)
  493. snd_soc_component_update_bits(component,
  494. WCD938X_FLYBACK_EN,
  495. 0x04, 0x00);
  496. wcd938x->flyback_cur_det_disable++;
  497. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  498. WCD_CLSH_EVENT_PRE_DAC,
  499. WCD_CLSH_STATE_EAR,
  500. wcd938x->hph_mode);
  501. break;
  502. case SND_SOC_DAPM_POST_PMD:
  503. break;
  504. };
  505. return 0;
  506. }
  507. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  508. struct snd_kcontrol *kcontrol,
  509. int event)
  510. {
  511. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  512. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  513. int ret = 0;
  514. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  515. w->name, event);
  516. switch (event) {
  517. case SND_SOC_DAPM_PRE_PMU:
  518. wcd938x_rx_clk_enable(component);
  519. snd_soc_component_update_bits(component,
  520. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  521. snd_soc_component_update_bits(component,
  522. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  523. snd_soc_component_update_bits(component,
  524. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  525. if (wcd938x->flyback_cur_det_disable == 0)
  526. snd_soc_component_update_bits(component,
  527. WCD938X_FLYBACK_EN,
  528. 0x04, 0x00);
  529. wcd938x->flyback_cur_det_disable++;
  530. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  531. WCD_CLSH_EVENT_PRE_DAC,
  532. WCD_CLSH_STATE_AUX,
  533. wcd938x->hph_mode);
  534. break;
  535. case SND_SOC_DAPM_POST_PMD:
  536. snd_soc_component_update_bits(component,
  537. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  538. break;
  539. };
  540. return ret;
  541. }
  542. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  543. struct snd_kcontrol *kcontrol,
  544. int event)
  545. {
  546. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  547. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  548. int ret = 0;
  549. int hph_mode = wcd938x->hph_mode;
  550. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  551. w->name, event);
  552. switch (event) {
  553. case SND_SOC_DAPM_PRE_PMU:
  554. if (wcd938x->ldoh)
  555. snd_soc_component_update_bits(component,
  556. WCD938X_LDOH_MODE,
  557. 0x80, 0x80);
  558. if (wcd938x->update_wcd_event)
  559. wcd938x->update_wcd_event(wcd938x->handle,
  560. WCD_BOLERO_EVT_RX_MUTE,
  561. (WCD_RX2 << 0x10 | 0x1));
  562. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  563. wcd938x->rx_swr_dev->dev_num,
  564. true);
  565. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  566. WCD_CLSH_EVENT_PRE_DAC,
  567. WCD_CLSH_STATE_HPHR,
  568. hph_mode);
  569. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  570. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  571. 0x10, 0x10);
  572. wcd_clsh_set_hph_mode(component, hph_mode);
  573. /* 100 usec delay as per HW requirement */
  574. usleep_range(100, 110);
  575. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  576. snd_soc_component_update_bits(component,
  577. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  578. break;
  579. case SND_SOC_DAPM_POST_PMU:
  580. /*
  581. * 7ms sleep is required if compander is enabled as per
  582. * HW requirement. If compander is disabled, then
  583. * 20ms delay is required.
  584. */
  585. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  586. if (!wcd938x->comp2_enable)
  587. usleep_range(20000, 20100);
  588. else
  589. usleep_range(7000, 7100);
  590. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  591. }
  592. snd_soc_component_update_bits(component,
  593. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  594. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  595. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  596. snd_soc_component_update_bits(component,
  597. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  598. if (wcd938x->update_wcd_event)
  599. wcd938x->update_wcd_event(wcd938x->handle,
  600. WCD_BOLERO_EVT_RX_MUTE,
  601. (WCD_RX2 << 0x10));
  602. wcd_enable_irq(&wcd938x->irq_info,
  603. WCD938X_IRQ_HPHR_PDM_WD_INT);
  604. break;
  605. case SND_SOC_DAPM_PRE_PMD:
  606. wcd_disable_irq(&wcd938x->irq_info,
  607. WCD938X_IRQ_HPHR_PDM_WD_INT);
  608. if (wcd938x->update_wcd_event)
  609. wcd938x->update_wcd_event(wcd938x->handle,
  610. WCD_BOLERO_EVT_RX_MUTE,
  611. (WCD_RX2 << 0x10 | 0x1));
  612. if (wcd938x->update_wcd_event)
  613. wcd938x->update_wcd_event(wcd938x->handle,
  614. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  615. (WCD_RX2 << 0x10));
  616. /* 7 msec delay as per HW requirement */
  617. usleep_range(7000, 7100);
  618. if (wcd938x->update_wcd_event)
  619. wcd938x->update_wcd_event(wcd938x->handle,
  620. WCD_BOLERO_EVT_RX_MUTE,
  621. (WCD_RX2 << 0x10 | 0x0));
  622. /* 20 msec delay as per HW requirement */
  623. usleep_range(21000, 21100);
  624. if (wcd938x->update_wcd_event)
  625. wcd938x->update_wcd_event(wcd938x->handle,
  626. WCD_BOLERO_EVT_RX_MUTE,
  627. (WCD_RX2 << 0x10 | 0x1));
  628. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  629. 0x40, 0x00);
  630. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  631. WCD_EVENT_PRE_HPHR_PA_OFF,
  632. &wcd938x->mbhc->wcd_mbhc);
  633. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  634. break;
  635. case SND_SOC_DAPM_POST_PMD:
  636. /*
  637. * 7ms sleep is required if compander is enabled as per
  638. * HW requirement. If compander is disabled, then
  639. * 20ms delay is required.
  640. */
  641. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  642. if (!wcd938x->comp2_enable)
  643. usleep_range(20000, 20100);
  644. else
  645. usleep_range(7000, 7100);
  646. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  647. }
  648. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  649. WCD_EVENT_POST_HPHR_PA_OFF,
  650. &wcd938x->mbhc->wcd_mbhc);
  651. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  652. 0x10, 0x00);
  653. /* 20 msec delay as per HW requirement */
  654. usleep_range(20000, 20100);
  655. snd_soc_component_update_bits(component,
  656. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  657. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  658. WCD_CLSH_EVENT_POST_PA,
  659. WCD_CLSH_STATE_HPHR,
  660. hph_mode);
  661. if (wcd938x->ldoh)
  662. snd_soc_component_update_bits(component,
  663. WCD938X_LDOH_MODE,
  664. 0x80, 0x00);
  665. break;
  666. };
  667. return ret;
  668. }
  669. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  670. struct snd_kcontrol *kcontrol,
  671. int event)
  672. {
  673. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  674. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  675. int ret = 0;
  676. int hph_mode = wcd938x->hph_mode;
  677. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  678. w->name, event);
  679. switch (event) {
  680. case SND_SOC_DAPM_PRE_PMU:
  681. if (wcd938x->ldoh)
  682. snd_soc_component_update_bits(component,
  683. WCD938X_LDOH_MODE,
  684. 0x80, 0x80);
  685. if (wcd938x->update_wcd_event)
  686. wcd938x->update_wcd_event(wcd938x->handle,
  687. WCD_BOLERO_EVT_RX_MUTE,
  688. (WCD_RX1 << 0x10 | 0x01));
  689. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  690. wcd938x->rx_swr_dev->dev_num,
  691. true);
  692. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  693. WCD_CLSH_EVENT_PRE_DAC,
  694. WCD_CLSH_STATE_HPHL,
  695. hph_mode);
  696. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  697. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  698. 0x20, 0x20);
  699. wcd_clsh_set_hph_mode(component, hph_mode);
  700. /* 100 usec delay as per HW requirement */
  701. usleep_range(100, 110);
  702. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  703. snd_soc_component_update_bits(component,
  704. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  705. break;
  706. case SND_SOC_DAPM_POST_PMU:
  707. /*
  708. * 7ms sleep is required if compander is enabled as per
  709. * HW requirement. If compander is disabled, then
  710. * 20ms delay is required.
  711. */
  712. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  713. if (!wcd938x->comp1_enable)
  714. usleep_range(20000, 20100);
  715. else
  716. usleep_range(7000, 7100);
  717. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  718. }
  719. snd_soc_component_update_bits(component,
  720. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  721. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  722. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  723. snd_soc_component_update_bits(component,
  724. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  725. if (wcd938x->update_wcd_event)
  726. wcd938x->update_wcd_event(wcd938x->handle,
  727. WCD_BOLERO_EVT_RX_MUTE,
  728. (WCD_RX1 << 0x10));
  729. wcd_enable_irq(&wcd938x->irq_info,
  730. WCD938X_IRQ_HPHL_PDM_WD_INT);
  731. break;
  732. case SND_SOC_DAPM_PRE_PMD:
  733. wcd_disable_irq(&wcd938x->irq_info,
  734. WCD938X_IRQ_HPHL_PDM_WD_INT);
  735. if (wcd938x->update_wcd_event)
  736. wcd938x->update_wcd_event(wcd938x->handle,
  737. WCD_BOLERO_EVT_RX_MUTE,
  738. (WCD_RX1 << 0x10 | 0x1));
  739. if (wcd938x->update_wcd_event)
  740. wcd938x->update_wcd_event(wcd938x->handle,
  741. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  742. (WCD_RX1 << 0x10));
  743. /* 7 msec delay as per HW requirement */
  744. usleep_range(7000, 7100);
  745. if (wcd938x->update_wcd_event)
  746. wcd938x->update_wcd_event(wcd938x->handle,
  747. WCD_BOLERO_EVT_RX_MUTE,
  748. (WCD_RX1 << 0x10 | 0x0));
  749. /* 20 msec delay as per HW requirement */
  750. usleep_range(21000, 21100);
  751. if (wcd938x->update_wcd_event)
  752. wcd938x->update_wcd_event(wcd938x->handle,
  753. WCD_BOLERO_EVT_RX_MUTE,
  754. (WCD_RX1 << 0x10 | 0x1));
  755. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  756. 0x80, 0x00);
  757. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  758. WCD_EVENT_PRE_HPHL_PA_OFF,
  759. &wcd938x->mbhc->wcd_mbhc);
  760. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  761. break;
  762. case SND_SOC_DAPM_POST_PMD:
  763. /*
  764. * 7ms sleep is required if compander is enabled as per
  765. * HW requirement. If compander is disabled, then
  766. * 20ms delay is required.
  767. */
  768. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  769. if (!wcd938x->comp1_enable)
  770. usleep_range(21000, 21100);
  771. else
  772. usleep_range(7000, 7100);
  773. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  774. }
  775. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  776. WCD_EVENT_POST_HPHL_PA_OFF,
  777. &wcd938x->mbhc->wcd_mbhc);
  778. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  779. 0x20, 0x00);
  780. /* 20 msec delay as per HW requirement */
  781. usleep_range(21000, 21100);
  782. snd_soc_component_update_bits(component,
  783. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  784. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  785. WCD_CLSH_EVENT_POST_PA,
  786. WCD_CLSH_STATE_HPHL,
  787. hph_mode);
  788. if (wcd938x->ldoh)
  789. snd_soc_component_update_bits(component,
  790. WCD938X_LDOH_MODE,
  791. 0x80, 0x00);
  792. break;
  793. };
  794. return ret;
  795. }
  796. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  797. struct snd_kcontrol *kcontrol,
  798. int event)
  799. {
  800. struct snd_soc_component *component =
  801. snd_soc_dapm_to_component(w->dapm);
  802. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  803. int hph_mode = wcd938x->hph_mode;
  804. int ret = 0;
  805. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  806. w->name, event);
  807. switch (event) {
  808. case SND_SOC_DAPM_PRE_PMU:
  809. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  810. wcd938x->rx_swr_dev->dev_num,
  811. true);
  812. snd_soc_component_update_bits(component,
  813. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  814. break;
  815. case SND_SOC_DAPM_POST_PMU:
  816. /* 1 msec delay as per HW requirement */
  817. usleep_range(1000, 1010);
  818. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  819. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  820. snd_soc_component_update_bits(component,
  821. WCD938X_ANA_RX_SUPPLIES,
  822. 0x02, 0x02);
  823. if (wcd938x->update_wcd_event)
  824. wcd938x->update_wcd_event(wcd938x->handle,
  825. WCD_BOLERO_EVT_RX_MUTE,
  826. (WCD_RX3 << 0x10));
  827. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  828. break;
  829. case SND_SOC_DAPM_PRE_PMD:
  830. wcd_disable_irq(&wcd938x->irq_info,
  831. WCD938X_IRQ_AUX_PDM_WD_INT);
  832. if (wcd938x->update_wcd_event)
  833. wcd938x->update_wcd_event(wcd938x->handle,
  834. WCD_BOLERO_EVT_RX_MUTE,
  835. (WCD_RX3 << 0x10 | 0x1));
  836. break;
  837. case SND_SOC_DAPM_POST_PMD:
  838. /* 1 msec delay as per HW requirement */
  839. usleep_range(1000, 1010);
  840. snd_soc_component_update_bits(component,
  841. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  842. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  843. WCD_CLSH_EVENT_POST_PA,
  844. WCD_CLSH_STATE_AUX,
  845. hph_mode);
  846. wcd938x->flyback_cur_det_disable--;
  847. if (wcd938x->flyback_cur_det_disable == 0)
  848. snd_soc_component_update_bits(component,
  849. WCD938X_FLYBACK_EN,
  850. 0x04, 0x04);
  851. break;
  852. };
  853. return ret;
  854. }
  855. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  856. struct snd_kcontrol *kcontrol,
  857. int event)
  858. {
  859. struct snd_soc_component *component =
  860. snd_soc_dapm_to_component(w->dapm);
  861. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  862. int hph_mode = wcd938x->hph_mode;
  863. int ret = 0;
  864. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  865. w->name, event);
  866. switch (event) {
  867. case SND_SOC_DAPM_PRE_PMU:
  868. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  869. wcd938x->rx_swr_dev->dev_num,
  870. true);
  871. /*
  872. * Enable watchdog interrupt for HPHL or AUX
  873. * depending on mux value
  874. */
  875. wcd938x->ear_rx_path =
  876. snd_soc_component_read32(
  877. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  878. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  879. snd_soc_component_update_bits(component,
  880. WCD938X_DIGITAL_PDM_WD_CTL2,
  881. 0x05, 0x05);
  882. else
  883. snd_soc_component_update_bits(component,
  884. WCD938X_DIGITAL_PDM_WD_CTL0,
  885. 0x17, 0x13);
  886. break;
  887. case SND_SOC_DAPM_POST_PMU:
  888. /* 6 msec delay as per HW requirement */
  889. usleep_range(6000, 6010);
  890. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  891. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  892. snd_soc_component_update_bits(component,
  893. WCD938X_ANA_RX_SUPPLIES,
  894. 0x02, 0x02);
  895. if (wcd938x->update_wcd_event)
  896. wcd938x->update_wcd_event(wcd938x->handle,
  897. WCD_BOLERO_EVT_RX_MUTE,
  898. (WCD_RX1 << 0x10));
  899. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  900. wcd_enable_irq(&wcd938x->irq_info,
  901. WCD938X_IRQ_AUX_PDM_WD_INT);
  902. else
  903. wcd_enable_irq(&wcd938x->irq_info,
  904. WCD938X_IRQ_HPHL_PDM_WD_INT);
  905. break;
  906. case SND_SOC_DAPM_PRE_PMD:
  907. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  908. wcd_disable_irq(&wcd938x->irq_info,
  909. WCD938X_IRQ_AUX_PDM_WD_INT);
  910. else
  911. wcd_disable_irq(&wcd938x->irq_info,
  912. WCD938X_IRQ_HPHL_PDM_WD_INT);
  913. if (wcd938x->update_wcd_event)
  914. wcd938x->update_wcd_event(wcd938x->handle,
  915. WCD_BOLERO_EVT_RX_MUTE,
  916. (WCD_RX1 << 0x10 | 0x1));
  917. break;
  918. case SND_SOC_DAPM_POST_PMD:
  919. /* 7 msec delay as per HW requirement */
  920. usleep_range(7000, 7010);
  921. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  922. snd_soc_component_update_bits(component,
  923. WCD938X_DIGITAL_PDM_WD_CTL2,
  924. 0x05, 0x00);
  925. else
  926. snd_soc_component_update_bits(component,
  927. WCD938X_DIGITAL_PDM_WD_CTL0,
  928. 0x17, 0x00);
  929. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  930. WCD_CLSH_EVENT_POST_PA,
  931. WCD_CLSH_STATE_EAR,
  932. hph_mode);
  933. wcd938x->flyback_cur_det_disable--;
  934. if (wcd938x->flyback_cur_det_disable == 0)
  935. snd_soc_component_update_bits(component,
  936. WCD938X_FLYBACK_EN,
  937. 0x04, 0x04);
  938. break;
  939. };
  940. return ret;
  941. }
  942. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  943. struct snd_kcontrol *kcontrol,
  944. int event)
  945. {
  946. struct snd_soc_component *component =
  947. snd_soc_dapm_to_component(w->dapm);
  948. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  949. int mode = wcd938x->hph_mode;
  950. int ret = 0;
  951. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  952. w->name, event);
  953. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  954. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  955. wcd938x_rx_connect_port(component, CLSH,
  956. SND_SOC_DAPM_EVENT_ON(event));
  957. }
  958. if (SND_SOC_DAPM_EVENT_OFF(event))
  959. ret = swr_slvdev_datapath_control(
  960. wcd938x->rx_swr_dev,
  961. wcd938x->rx_swr_dev->dev_num,
  962. false);
  963. return ret;
  964. }
  965. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  966. struct snd_kcontrol *kcontrol,
  967. int event)
  968. {
  969. struct snd_soc_component *component =
  970. snd_soc_dapm_to_component(w->dapm);
  971. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  972. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  973. w->name, event);
  974. switch (event) {
  975. case SND_SOC_DAPM_PRE_PMU:
  976. wcd938x_rx_connect_port(component, HPH_L, true);
  977. if (wcd938x->comp1_enable)
  978. wcd938x_rx_connect_port(component, COMP_L, true);
  979. break;
  980. case SND_SOC_DAPM_POST_PMD:
  981. wcd938x_rx_connect_port(component, HPH_L, false);
  982. if (wcd938x->comp1_enable)
  983. wcd938x_rx_connect_port(component, COMP_L, false);
  984. wcd938x_rx_clk_disable(component);
  985. snd_soc_component_update_bits(component,
  986. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  987. 0x01, 0x00);
  988. break;
  989. };
  990. return 0;
  991. }
  992. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  993. struct snd_kcontrol *kcontrol, int event)
  994. {
  995. struct snd_soc_component *component =
  996. snd_soc_dapm_to_component(w->dapm);
  997. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  998. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  999. w->name, event);
  1000. switch (event) {
  1001. case SND_SOC_DAPM_PRE_PMU:
  1002. wcd938x_rx_connect_port(component, HPH_R, true);
  1003. if (wcd938x->comp2_enable)
  1004. wcd938x_rx_connect_port(component, COMP_R, true);
  1005. break;
  1006. case SND_SOC_DAPM_POST_PMD:
  1007. wcd938x_rx_connect_port(component, HPH_R, false);
  1008. if (wcd938x->comp2_enable)
  1009. wcd938x_rx_connect_port(component, COMP_R, false);
  1010. wcd938x_rx_clk_disable(component);
  1011. snd_soc_component_update_bits(component,
  1012. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1013. 0x02, 0x00);
  1014. break;
  1015. };
  1016. return 0;
  1017. }
  1018. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  1019. struct snd_kcontrol *kcontrol,
  1020. int event)
  1021. {
  1022. struct snd_soc_component *component =
  1023. snd_soc_dapm_to_component(w->dapm);
  1024. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1025. w->name, event);
  1026. switch (event) {
  1027. case SND_SOC_DAPM_PRE_PMU:
  1028. wcd938x_rx_connect_port(component, LO, true);
  1029. break;
  1030. case SND_SOC_DAPM_POST_PMD:
  1031. wcd938x_rx_connect_port(component, LO, false);
  1032. /* 6 msec delay as per HW requirement */
  1033. usleep_range(6000, 6010);
  1034. wcd938x_rx_clk_disable(component);
  1035. snd_soc_component_update_bits(component,
  1036. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1037. break;
  1038. }
  1039. return 0;
  1040. }
  1041. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1042. struct snd_kcontrol *kcontrol,
  1043. int event)
  1044. {
  1045. struct snd_soc_component *component =
  1046. snd_soc_dapm_to_component(w->dapm);
  1047. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1048. u16 dmic_clk_reg, dmic_clk_en_reg;
  1049. s32 *dmic_clk_cnt;
  1050. u8 dmic_ctl_shift = 0;
  1051. u8 dmic_clk_shift = 0;
  1052. u8 dmic_clk_mask = 0;
  1053. u16 dmic2_left_en = 0;
  1054. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1055. w->name, event);
  1056. switch (w->shift) {
  1057. case 0:
  1058. case 1:
  1059. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  1060. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1061. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  1062. dmic_clk_mask = 0x0F;
  1063. dmic_clk_shift = 0x00;
  1064. dmic_ctl_shift = 0x00;
  1065. break;
  1066. case 2:
  1067. dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1068. case 3:
  1069. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  1070. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1071. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1072. dmic_clk_mask = 0xF0;
  1073. dmic_clk_shift = 0x04;
  1074. dmic_ctl_shift = 0x01;
  1075. break;
  1076. case 4:
  1077. case 5:
  1078. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  1079. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1080. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  1081. dmic_clk_mask = 0x0F;
  1082. dmic_clk_shift = 0x00;
  1083. dmic_ctl_shift = 0x02;
  1084. break;
  1085. case 6:
  1086. case 7:
  1087. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  1088. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1089. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  1090. dmic_clk_mask = 0xF0;
  1091. dmic_clk_shift = 0x04;
  1092. dmic_ctl_shift = 0x03;
  1093. break;
  1094. default:
  1095. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1096. __func__);
  1097. return -EINVAL;
  1098. };
  1099. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1100. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1101. switch (event) {
  1102. case SND_SOC_DAPM_PRE_PMU:
  1103. snd_soc_component_update_bits(component,
  1104. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1105. (0x01 << dmic_ctl_shift), 0x00);
  1106. /* 250us sleep as per HW requirement */
  1107. usleep_range(250, 260);
  1108. if (dmic2_left_en)
  1109. snd_soc_component_update_bits(component,
  1110. dmic2_left_en, 0x80, 0x80);
  1111. /* Setting DMIC clock rate to 2.4MHz */
  1112. snd_soc_component_update_bits(component,
  1113. dmic_clk_reg, dmic_clk_mask,
  1114. (0x03 << dmic_clk_shift));
  1115. snd_soc_component_update_bits(component,
  1116. dmic_clk_en_reg, 0x08, 0x08);
  1117. /* enable clock scaling */
  1118. snd_soc_component_update_bits(component,
  1119. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  1120. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1121. break;
  1122. case SND_SOC_DAPM_POST_PMD:
  1123. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1124. snd_soc_component_update_bits(component,
  1125. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1126. (0x01 << dmic_ctl_shift),
  1127. (0x01 << dmic_ctl_shift));
  1128. if (dmic2_left_en)
  1129. snd_soc_component_update_bits(component,
  1130. dmic2_left_en, 0x80, 0x00);
  1131. snd_soc_component_update_bits(component,
  1132. dmic_clk_en_reg, 0x08, 0x00);
  1133. break;
  1134. };
  1135. return 0;
  1136. }
  1137. /*
  1138. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1139. * @micb_mv: micbias in mv
  1140. *
  1141. * return register value converted
  1142. */
  1143. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1144. {
  1145. /* min micbias voltage is 1V and maximum is 2.85V */
  1146. if (micb_mv < 1000 || micb_mv > 2850) {
  1147. pr_err("%s: unsupported micbias voltage\n", __func__);
  1148. return -EINVAL;
  1149. }
  1150. return (micb_mv - 1000) / 50;
  1151. }
  1152. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1153. /*
  1154. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1155. * @component: handle to snd_soc_component *
  1156. * @req_volt: micbias voltage to be set
  1157. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1158. *
  1159. * return 0 if adjustment is success or error code in case of failure
  1160. */
  1161. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1162. int req_volt, int micb_num)
  1163. {
  1164. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1165. int cur_vout_ctl, req_vout_ctl;
  1166. int micb_reg, micb_val, micb_en;
  1167. int ret = 0;
  1168. switch (micb_num) {
  1169. case MIC_BIAS_1:
  1170. micb_reg = WCD938X_ANA_MICB1;
  1171. break;
  1172. case MIC_BIAS_2:
  1173. micb_reg = WCD938X_ANA_MICB2;
  1174. break;
  1175. case MIC_BIAS_3:
  1176. micb_reg = WCD938X_ANA_MICB3;
  1177. break;
  1178. case MIC_BIAS_4:
  1179. micb_reg = WCD938X_ANA_MICB4;
  1180. break;
  1181. default:
  1182. return -EINVAL;
  1183. }
  1184. mutex_lock(&wcd938x->micb_lock);
  1185. /*
  1186. * If requested micbias voltage is same as current micbias
  1187. * voltage, then just return. Otherwise, adjust voltage as
  1188. * per requested value. If micbias is already enabled, then
  1189. * to avoid slow micbias ramp-up or down enable pull-up
  1190. * momentarily, change the micbias value and then re-enable
  1191. * micbias.
  1192. */
  1193. micb_val = snd_soc_component_read32(component, micb_reg);
  1194. micb_en = (micb_val & 0xC0) >> 6;
  1195. cur_vout_ctl = micb_val & 0x3F;
  1196. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1197. if (req_vout_ctl < 0) {
  1198. ret = -EINVAL;
  1199. goto exit;
  1200. }
  1201. if (cur_vout_ctl == req_vout_ctl) {
  1202. ret = 0;
  1203. goto exit;
  1204. }
  1205. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1206. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1207. req_volt, micb_en);
  1208. if (micb_en == 0x1)
  1209. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1210. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1211. if (micb_en == 0x1) {
  1212. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1213. /*
  1214. * Add 2ms delay as per HW requirement after enabling
  1215. * micbias
  1216. */
  1217. usleep_range(2000, 2100);
  1218. }
  1219. exit:
  1220. mutex_unlock(&wcd938x->micb_lock);
  1221. return ret;
  1222. }
  1223. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1224. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1225. struct snd_kcontrol *kcontrol,
  1226. int event)
  1227. {
  1228. struct snd_soc_component *component =
  1229. snd_soc_dapm_to_component(w->dapm);
  1230. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1231. int ret = 0;
  1232. switch (event) {
  1233. case SND_SOC_DAPM_PRE_PMU:
  1234. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1235. wcd938x->tx_swr_dev->dev_num,
  1236. true);
  1237. break;
  1238. case SND_SOC_DAPM_POST_PMD:
  1239. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1240. wcd938x->tx_swr_dev->dev_num,
  1241. false);
  1242. break;
  1243. };
  1244. return ret;
  1245. }
  1246. static int wcd938x_get_adc_mode(int val)
  1247. {
  1248. int ret = 0;
  1249. switch (val) {
  1250. case ADC_MODE_INVALID:
  1251. ret = ADC_MODE_VAL_NORMAL;
  1252. break;
  1253. case ADC_MODE_HIFI:
  1254. ret = ADC_MODE_VAL_HIFI;
  1255. break;
  1256. case ADC_MODE_LO_HIF:
  1257. ret = ADC_MODE_VAL_LO_HIF;
  1258. break;
  1259. case ADC_MODE_NORMAL:
  1260. ret = ADC_MODE_VAL_NORMAL;
  1261. break;
  1262. case ADC_MODE_LP:
  1263. ret = ADC_MODE_VAL_LP;
  1264. break;
  1265. case ADC_MODE_ULP1:
  1266. ret = ADC_MODE_VAL_ULP1;
  1267. break;
  1268. case ADC_MODE_ULP2:
  1269. ret = ADC_MODE_VAL_ULP2;
  1270. break;
  1271. default:
  1272. ret = -EINVAL;
  1273. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1274. break;
  1275. }
  1276. return ret;
  1277. }
  1278. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1279. struct snd_kcontrol *kcontrol,
  1280. int event){
  1281. int mode;
  1282. struct snd_soc_component *component =
  1283. snd_soc_dapm_to_component(w->dapm);
  1284. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1285. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1286. w->name, event);
  1287. switch (event) {
  1288. case SND_SOC_DAPM_PRE_PMU:
  1289. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1290. if (mode < 0) {
  1291. dev_info(component->dev,
  1292. "%s: invalid mode, setting to normal mode\n",
  1293. __func__);
  1294. mode = ADC_MODE_VAL_NORMAL;
  1295. }
  1296. snd_soc_component_update_bits(component,
  1297. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1298. snd_soc_component_update_bits(component,
  1299. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1300. snd_soc_component_update_bits(component,
  1301. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1302. switch (w->shift) {
  1303. case 0:
  1304. snd_soc_component_update_bits(component,
  1305. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1306. mode);
  1307. break;
  1308. case 1:
  1309. snd_soc_component_update_bits(component,
  1310. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1311. mode << 4);
  1312. break;
  1313. case 2:
  1314. snd_soc_component_update_bits(component,
  1315. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1316. mode);
  1317. break;
  1318. case 3:
  1319. snd_soc_component_update_bits(component,
  1320. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1321. mode << 4);
  1322. break;
  1323. default:
  1324. break;
  1325. }
  1326. set_bit(w->shift, &wcd938x->status_mask);
  1327. /* Enable BCS for Headset mic */
  1328. if (w->shift == 1 && !(snd_soc_component_read32(component,
  1329. WCD938X_TX_NEW_AMIC_MUX_CFG) & 0x80)) {
  1330. wcd938x_tx_connect_port(component, MBHC, true);
  1331. set_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1332. }
  1333. wcd938x_tx_connect_port(component, ADC1 + (w->shift), true);
  1334. break;
  1335. case SND_SOC_DAPM_POST_PMD:
  1336. wcd938x_tx_connect_port(component, ADC1 + (w->shift), false);
  1337. if (w->shift == 1 &&
  1338. test_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask)) {
  1339. wcd938x_tx_connect_port(component, MBHC, false);
  1340. clear_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1341. }
  1342. snd_soc_component_update_bits(component,
  1343. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1344. clear_bit(w->shift, &wcd938x->status_mask);
  1345. break;
  1346. };
  1347. return 0;
  1348. }
  1349. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1350. int channel, int mode)
  1351. {
  1352. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1353. int ret = 0;
  1354. switch (channel) {
  1355. case 0:
  1356. reg = WCD938X_ANA_TX_CH2;
  1357. mask = 0x40;
  1358. break;
  1359. case 1:
  1360. reg = WCD938X_ANA_TX_CH2;
  1361. mask = 0x20;
  1362. break;
  1363. case 2:
  1364. reg = WCD938X_ANA_TX_CH4;
  1365. mask = 0x40;
  1366. break;
  1367. case 3:
  1368. reg = WCD938X_ANA_TX_CH4;
  1369. mask = 0x20;
  1370. break;
  1371. default:
  1372. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1373. ret = -EINVAL;
  1374. break;
  1375. }
  1376. if (!mode)
  1377. val = 0x00;
  1378. else
  1379. val = mask;
  1380. if (!ret)
  1381. snd_soc_component_update_bits(component, reg, mask, val);
  1382. return ret;
  1383. }
  1384. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1385. struct snd_kcontrol *kcontrol, int event)
  1386. {
  1387. struct snd_soc_component *component =
  1388. snd_soc_dapm_to_component(w->dapm);
  1389. int ret = 0;
  1390. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1391. w->name, event);
  1392. switch (event) {
  1393. case SND_SOC_DAPM_PRE_PMU:
  1394. snd_soc_component_update_bits(component,
  1395. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1396. snd_soc_component_update_bits(component,
  1397. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1398. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1399. snd_soc_component_update_bits(component,
  1400. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x30, 0x30);
  1401. snd_soc_component_update_bits(component,
  1402. WCD938X_ANA_TX_CH1, 0x80, 0x80);
  1403. snd_soc_component_update_bits(component,
  1404. WCD938X_ANA_TX_CH2, 0x80, 0x80);
  1405. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1406. break;
  1407. case SND_SOC_DAPM_POST_PMD:
  1408. snd_soc_component_update_bits(component,
  1409. WCD938X_ANA_TX_CH1, 0x80, 0x00);
  1410. snd_soc_component_update_bits(component,
  1411. WCD938X_ANA_TX_CH2, 0x80, 0x00);
  1412. snd_soc_component_update_bits(component,
  1413. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1414. snd_soc_component_update_bits(component,
  1415. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1416. snd_soc_component_update_bits(component,
  1417. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1418. break;
  1419. };
  1420. return ret;
  1421. }
  1422. int wcd938x_micbias_control(struct snd_soc_component *component,
  1423. int micb_num, int req, bool is_dapm)
  1424. {
  1425. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1426. int micb_index = micb_num - 1;
  1427. u16 micb_reg;
  1428. int pre_off_event = 0, post_off_event = 0;
  1429. int post_on_event = 0, post_dapm_off = 0;
  1430. int post_dapm_on = 0;
  1431. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1432. dev_err(component->dev,
  1433. "%s: Invalid micbias index, micb_ind:%d\n",
  1434. __func__, micb_index);
  1435. return -EINVAL;
  1436. }
  1437. if (NULL == wcd938x) {
  1438. dev_err(component->dev,
  1439. "%s: wcd938x private data is NULL\n", __func__);
  1440. return -EINVAL;
  1441. }
  1442. switch (micb_num) {
  1443. case MIC_BIAS_1:
  1444. micb_reg = WCD938X_ANA_MICB1;
  1445. break;
  1446. case MIC_BIAS_2:
  1447. micb_reg = WCD938X_ANA_MICB2;
  1448. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1449. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1450. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1451. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1452. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1453. break;
  1454. case MIC_BIAS_3:
  1455. micb_reg = WCD938X_ANA_MICB3;
  1456. break;
  1457. case MIC_BIAS_4:
  1458. micb_reg = WCD938X_ANA_MICB4;
  1459. break;
  1460. default:
  1461. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1462. __func__, micb_num);
  1463. return -EINVAL;
  1464. };
  1465. mutex_lock(&wcd938x->micb_lock);
  1466. switch (req) {
  1467. case MICB_PULLUP_ENABLE:
  1468. wcd938x->pullup_ref[micb_index]++;
  1469. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1470. (wcd938x->micb_ref[micb_index] == 0))
  1471. snd_soc_component_update_bits(component, micb_reg,
  1472. 0xC0, 0x80);
  1473. break;
  1474. case MICB_PULLUP_DISABLE:
  1475. if (wcd938x->pullup_ref[micb_index] > 0)
  1476. wcd938x->pullup_ref[micb_index]--;
  1477. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1478. (wcd938x->micb_ref[micb_index] == 0))
  1479. snd_soc_component_update_bits(component, micb_reg,
  1480. 0xC0, 0x00);
  1481. break;
  1482. case MICB_ENABLE:
  1483. wcd938x->micb_ref[micb_index]++;
  1484. if (wcd938x->micb_ref[micb_index] == 1) {
  1485. snd_soc_component_update_bits(component,
  1486. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1487. snd_soc_component_update_bits(component,
  1488. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1489. snd_soc_component_update_bits(component,
  1490. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1491. snd_soc_component_update_bits(component,
  1492. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1493. snd_soc_component_update_bits(component,
  1494. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1495. snd_soc_component_update_bits(component,
  1496. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1497. snd_soc_component_update_bits(component,
  1498. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1499. snd_soc_component_update_bits(component,
  1500. micb_reg, 0xC0, 0x40);
  1501. if (post_on_event)
  1502. blocking_notifier_call_chain(
  1503. &wcd938x->mbhc->notifier,
  1504. post_on_event,
  1505. &wcd938x->mbhc->wcd_mbhc);
  1506. }
  1507. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1508. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1509. post_dapm_on,
  1510. &wcd938x->mbhc->wcd_mbhc);
  1511. break;
  1512. case MICB_DISABLE:
  1513. if (wcd938x->micb_ref[micb_index] > 0)
  1514. wcd938x->micb_ref[micb_index]--;
  1515. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1516. (wcd938x->pullup_ref[micb_index] > 0))
  1517. snd_soc_component_update_bits(component, micb_reg,
  1518. 0xC0, 0x80);
  1519. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1520. (wcd938x->pullup_ref[micb_index] == 0)) {
  1521. if (pre_off_event && wcd938x->mbhc)
  1522. blocking_notifier_call_chain(
  1523. &wcd938x->mbhc->notifier,
  1524. pre_off_event,
  1525. &wcd938x->mbhc->wcd_mbhc);
  1526. snd_soc_component_update_bits(component, micb_reg,
  1527. 0xC0, 0x00);
  1528. if (post_off_event && wcd938x->mbhc)
  1529. blocking_notifier_call_chain(
  1530. &wcd938x->mbhc->notifier,
  1531. post_off_event,
  1532. &wcd938x->mbhc->wcd_mbhc);
  1533. }
  1534. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1535. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1536. post_dapm_off,
  1537. &wcd938x->mbhc->wcd_mbhc);
  1538. break;
  1539. };
  1540. dev_dbg(component->dev,
  1541. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1542. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1543. wcd938x->pullup_ref[micb_index]);
  1544. mutex_unlock(&wcd938x->micb_lock);
  1545. return 0;
  1546. }
  1547. EXPORT_SYMBOL(wcd938x_micbias_control);
  1548. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1549. {
  1550. int ret = 0;
  1551. uint8_t devnum = 0;
  1552. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1553. if (ret) {
  1554. dev_err(&swr_dev->dev,
  1555. "%s get devnum %d for dev addr %lx failed\n",
  1556. __func__, devnum, swr_dev->addr);
  1557. swr_remove_device(swr_dev);
  1558. return ret;
  1559. }
  1560. swr_dev->dev_num = devnum;
  1561. return 0;
  1562. }
  1563. static int wcd938x_event_notify(struct notifier_block *block,
  1564. unsigned long val,
  1565. void *data)
  1566. {
  1567. u16 event = (val & 0xffff);
  1568. int ret = 0;
  1569. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1570. struct snd_soc_component *component = wcd938x->component;
  1571. struct wcd_mbhc *mbhc;
  1572. switch (event) {
  1573. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1574. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  1575. snd_soc_component_update_bits(component,
  1576. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1577. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1578. }
  1579. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  1580. snd_soc_component_update_bits(component,
  1581. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1582. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1583. }
  1584. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  1585. snd_soc_component_update_bits(component,
  1586. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  1587. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1588. }
  1589. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  1590. snd_soc_component_update_bits(component,
  1591. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  1592. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1593. }
  1594. break;
  1595. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1596. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1597. 0xC0, 0x00);
  1598. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1599. 0x80, 0x00);
  1600. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1601. 0x80, 0x00);
  1602. break;
  1603. case BOLERO_WCD_EVT_SSR_DOWN:
  1604. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1605. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  1606. wcd938x_reset_low(wcd938x->dev);
  1607. break;
  1608. case BOLERO_WCD_EVT_SSR_UP:
  1609. wcd938x_reset(wcd938x->dev);
  1610. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  1611. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  1612. wcd938x_init_reg(component);
  1613. regcache_mark_dirty(wcd938x->regmap);
  1614. regcache_sync(wcd938x->regmap);
  1615. /* Initialize MBHC module */
  1616. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1617. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  1618. if (ret) {
  1619. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1620. __func__);
  1621. } else {
  1622. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1623. }
  1624. break;
  1625. case BOLERO_WCD_EVT_CLK_NOTIFY:
  1626. snd_soc_component_update_bits(component,
  1627. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  1628. ((val >> 0x10) << 0x01));
  1629. break;
  1630. default:
  1631. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  1632. break;
  1633. }
  1634. return 0;
  1635. }
  1636. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1637. int event)
  1638. {
  1639. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1640. int micb_num;
  1641. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1642. __func__, w->name, event);
  1643. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1644. micb_num = MIC_BIAS_1;
  1645. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1646. micb_num = MIC_BIAS_2;
  1647. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1648. micb_num = MIC_BIAS_3;
  1649. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  1650. micb_num = MIC_BIAS_4;
  1651. else
  1652. return -EINVAL;
  1653. switch (event) {
  1654. case SND_SOC_DAPM_PRE_PMU:
  1655. wcd938x_micbias_control(component, micb_num,
  1656. MICB_ENABLE, true);
  1657. break;
  1658. case SND_SOC_DAPM_POST_PMU:
  1659. /* 1 msec delay as per HW requirement */
  1660. usleep_range(1000, 1100);
  1661. break;
  1662. case SND_SOC_DAPM_POST_PMD:
  1663. wcd938x_micbias_control(component, micb_num,
  1664. MICB_DISABLE, true);
  1665. break;
  1666. };
  1667. return 0;
  1668. }
  1669. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1670. struct snd_kcontrol *kcontrol,
  1671. int event)
  1672. {
  1673. return __wcd938x_codec_enable_micbias(w, event);
  1674. }
  1675. static int __wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1676. int event)
  1677. {
  1678. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1679. int micb_num;
  1680. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1681. __func__, w->name, event);
  1682. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1683. micb_num = MIC_BIAS_1;
  1684. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1685. micb_num = MIC_BIAS_2;
  1686. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1687. micb_num = MIC_BIAS_3;
  1688. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  1689. micb_num = MIC_BIAS_4;
  1690. else
  1691. return -EINVAL;
  1692. switch (event) {
  1693. case SND_SOC_DAPM_PRE_PMU:
  1694. wcd938x_micbias_control(component, micb_num,
  1695. MICB_PULLUP_ENABLE, true);
  1696. break;
  1697. case SND_SOC_DAPM_POST_PMU:
  1698. /* 1 msec delay as per HW requirement */
  1699. usleep_range(1000, 1100);
  1700. break;
  1701. case SND_SOC_DAPM_POST_PMD:
  1702. wcd938x_micbias_control(component, micb_num,
  1703. MICB_PULLUP_DISABLE, true);
  1704. break;
  1705. };
  1706. return 0;
  1707. }
  1708. static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1709. struct snd_kcontrol *kcontrol,
  1710. int event)
  1711. {
  1712. return __wcd938x_codec_enable_micbias_pullup(w, event);
  1713. }
  1714. static inline int wcd938x_tx_path_get(const char *wname,
  1715. unsigned int *path_num)
  1716. {
  1717. int ret = 0;
  1718. char *widget_name = NULL;
  1719. char *w_name = NULL;
  1720. char *path_num_char = NULL;
  1721. char *path_name = NULL;
  1722. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  1723. if (!widget_name)
  1724. return -EINVAL;
  1725. w_name = widget_name;
  1726. path_name = strsep(&widget_name, " ");
  1727. if (!path_name) {
  1728. pr_err("%s: Invalid widget name = %s\n",
  1729. __func__, widget_name);
  1730. ret = -EINVAL;
  1731. goto err;
  1732. }
  1733. path_num_char = strpbrk(path_name, "0123");
  1734. if (!path_num_char) {
  1735. pr_err("%s: tx path index not found\n",
  1736. __func__);
  1737. ret = -EINVAL;
  1738. goto err;
  1739. }
  1740. ret = kstrtouint(path_num_char, 10, path_num);
  1741. if (ret < 0)
  1742. pr_err("%s: Invalid tx path = %s\n",
  1743. __func__, w_name);
  1744. err:
  1745. kfree(w_name);
  1746. return ret;
  1747. }
  1748. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  1749. struct snd_ctl_elem_value *ucontrol)
  1750. {
  1751. struct snd_soc_component *component =
  1752. snd_soc_kcontrol_component(kcontrol);
  1753. struct wcd938x_priv *wcd938x = NULL;
  1754. int ret = 0;
  1755. unsigned int path = 0;
  1756. if (!component)
  1757. return -EINVAL;
  1758. wcd938x = snd_soc_component_get_drvdata(component);
  1759. if (!wcd938x)
  1760. return -EINVAL;
  1761. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  1762. if (ret < 0)
  1763. return ret;
  1764. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  1765. return 0;
  1766. }
  1767. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  1768. struct snd_ctl_elem_value *ucontrol)
  1769. {
  1770. struct snd_soc_component *component =
  1771. snd_soc_kcontrol_component(kcontrol);
  1772. struct wcd938x_priv *wcd938x = NULL;
  1773. u32 mode_val;
  1774. unsigned int path = 0;
  1775. int ret = 0;
  1776. if (!component)
  1777. return -EINVAL;
  1778. wcd938x = snd_soc_component_get_drvdata(component);
  1779. if (!wcd938x)
  1780. return -EINVAL;
  1781. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  1782. if (ret)
  1783. return ret;
  1784. mode_val = ucontrol->value.enumerated.item[0];
  1785. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1786. wcd938x->tx_mode[path] = mode_val;
  1787. return 0;
  1788. }
  1789. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1790. struct snd_ctl_elem_value *ucontrol)
  1791. {
  1792. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1793. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1794. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  1795. return 0;
  1796. }
  1797. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1798. struct snd_ctl_elem_value *ucontrol)
  1799. {
  1800. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1801. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1802. u32 mode_val;
  1803. mode_val = ucontrol->value.enumerated.item[0];
  1804. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1805. if (wcd938x->variant == WCD9380) {
  1806. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  1807. dev_info(component->dev,
  1808. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  1809. __func__);
  1810. mode_val = CLS_H_ULP;
  1811. }
  1812. }
  1813. if (mode_val == CLS_H_NORMAL) {
  1814. dev_info(component->dev,
  1815. "%s:Invalid HPH Mode, default to class_AB\n",
  1816. __func__);
  1817. mode_val = CLS_H_ULP;
  1818. }
  1819. wcd938x->hph_mode = mode_val;
  1820. return 0;
  1821. }
  1822. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  1823. struct snd_ctl_elem_value *ucontrol)
  1824. {
  1825. struct snd_soc_component *component =
  1826. snd_soc_kcontrol_component(kcontrol);
  1827. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1828. bool hphr;
  1829. struct soc_multi_mixer_control *mc;
  1830. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1831. hphr = mc->shift;
  1832. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  1833. wcd938x->comp1_enable;
  1834. return 0;
  1835. }
  1836. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  1837. struct snd_ctl_elem_value *ucontrol)
  1838. {
  1839. struct snd_soc_component *component =
  1840. snd_soc_kcontrol_component(kcontrol);
  1841. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1842. int value = ucontrol->value.integer.value[0];
  1843. bool hphr;
  1844. struct soc_multi_mixer_control *mc;
  1845. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1846. hphr = mc->shift;
  1847. if (hphr)
  1848. wcd938x->comp2_enable = value;
  1849. else
  1850. wcd938x->comp1_enable = value;
  1851. return 0;
  1852. }
  1853. static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
  1854. struct snd_ctl_elem_value *ucontrol)
  1855. {
  1856. struct snd_soc_component *component =
  1857. snd_soc_kcontrol_component(kcontrol);
  1858. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1859. ucontrol->value.integer.value[0] = wcd938x->ldoh;
  1860. return 0;
  1861. }
  1862. static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
  1863. struct snd_ctl_elem_value *ucontrol)
  1864. {
  1865. struct snd_soc_component *component =
  1866. snd_soc_kcontrol_component(kcontrol);
  1867. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1868. wcd938x->ldoh = ucontrol->value.integer.value[0];
  1869. return 0;
  1870. }
  1871. static const char * const tx_mode_mux_text_wcd9380[] = {
  1872. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  1873. };
  1874. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  1875. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  1876. tx_mode_mux_text_wcd9380);
  1877. static const char * const tx_mode_mux_text[] = {
  1878. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  1879. "ADC_ULP1", "ADC_ULP2",
  1880. };
  1881. static const struct soc_enum tx_mode_mux_enum =
  1882. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  1883. tx_mode_mux_text);
  1884. static const char * const rx_hph_mode_mux_text_wcd9380[] = {
  1885. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  1886. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  1887. "CLS_AB_LOHIFI",
  1888. };
  1889. static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
  1890. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
  1891. rx_hph_mode_mux_text_wcd9380);
  1892. static const char * const rx_hph_mode_mux_text[] = {
  1893. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1894. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  1895. };
  1896. static const struct soc_enum rx_hph_mode_mux_enum =
  1897. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1898. rx_hph_mode_mux_text);
  1899. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  1900. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
  1901. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  1902. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  1903. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1904. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  1905. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1906. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  1907. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1908. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  1909. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1910. };
  1911. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  1912. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1913. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  1914. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  1915. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1916. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  1917. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1918. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  1919. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1920. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  1921. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1922. };
  1923. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  1924. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1925. wcd938x_get_compander, wcd938x_set_compander),
  1926. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1927. wcd938x_get_compander, wcd938x_set_compander),
  1928. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  1929. wcd938x_ldoh_get, wcd938x_ldoh_put),
  1930. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  1931. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  1932. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  1933. analog_gain),
  1934. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  1935. analog_gain),
  1936. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  1937. analog_gain),
  1938. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  1939. analog_gain),
  1940. };
  1941. static const struct snd_kcontrol_new adc1_switch[] = {
  1942. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1943. };
  1944. static const struct snd_kcontrol_new adc2_switch[] = {
  1945. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1946. };
  1947. static const struct snd_kcontrol_new adc3_switch[] = {
  1948. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1949. };
  1950. static const struct snd_kcontrol_new adc4_switch[] = {
  1951. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1952. };
  1953. static const struct snd_kcontrol_new dmic1_switch[] = {
  1954. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1955. };
  1956. static const struct snd_kcontrol_new dmic2_switch[] = {
  1957. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1958. };
  1959. static const struct snd_kcontrol_new dmic3_switch[] = {
  1960. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1961. };
  1962. static const struct snd_kcontrol_new dmic4_switch[] = {
  1963. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1964. };
  1965. static const struct snd_kcontrol_new dmic5_switch[] = {
  1966. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1967. };
  1968. static const struct snd_kcontrol_new dmic6_switch[] = {
  1969. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1970. };
  1971. static const struct snd_kcontrol_new dmic7_switch[] = {
  1972. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1973. };
  1974. static const struct snd_kcontrol_new dmic8_switch[] = {
  1975. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1976. };
  1977. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  1978. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1979. };
  1980. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  1981. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1982. };
  1983. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  1984. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1985. };
  1986. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  1987. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1988. };
  1989. static const char * const adc2_mux_text[] = {
  1990. "INP2", "INP3"
  1991. };
  1992. static const struct soc_enum adc2_enum =
  1993. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  1994. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  1995. static const struct snd_kcontrol_new tx_adc2_mux =
  1996. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  1997. static const char * const adc3_mux_text[] = {
  1998. "INP4", "INP6"
  1999. };
  2000. static const struct soc_enum adc3_enum =
  2001. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  2002. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2003. static const struct snd_kcontrol_new tx_adc3_mux =
  2004. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2005. static const char * const adc4_mux_text[] = {
  2006. "INP5", "INP7"
  2007. };
  2008. static const struct soc_enum adc4_enum =
  2009. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  2010. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  2011. static const struct snd_kcontrol_new tx_adc4_mux =
  2012. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  2013. static const char * const rdac3_mux_text[] = {
  2014. "RX1", "RX3"
  2015. };
  2016. static const char * const hdr12_mux_text[] = {
  2017. "NO_HDR12", "HDR12"
  2018. };
  2019. static const struct soc_enum hdr12_enum =
  2020. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  2021. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  2022. static const struct snd_kcontrol_new tx_hdr12_mux =
  2023. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  2024. static const char * const hdr34_mux_text[] = {
  2025. "NO_HDR34", "HDR34"
  2026. };
  2027. static const struct soc_enum hdr34_enum =
  2028. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  2029. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  2030. static const struct snd_kcontrol_new tx_hdr34_mux =
  2031. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  2032. static const struct soc_enum rdac3_enum =
  2033. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2034. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2035. static const struct snd_kcontrol_new rx_rdac3_mux =
  2036. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2037. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  2038. /*input widgets*/
  2039. SND_SOC_DAPM_INPUT("AMIC1"),
  2040. SND_SOC_DAPM_INPUT("AMIC2"),
  2041. SND_SOC_DAPM_INPUT("AMIC3"),
  2042. SND_SOC_DAPM_INPUT("AMIC4"),
  2043. SND_SOC_DAPM_INPUT("AMIC5"),
  2044. SND_SOC_DAPM_INPUT("AMIC6"),
  2045. SND_SOC_DAPM_INPUT("AMIC7"),
  2046. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2047. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2048. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2049. /*tx widgets*/
  2050. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2051. wcd938x_codec_enable_adc,
  2052. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2053. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2054. wcd938x_codec_enable_adc,
  2055. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2056. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2057. wcd938x_codec_enable_adc,
  2058. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2059. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  2060. wcd938x_codec_enable_adc,
  2061. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2062. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2063. wcd938x_codec_enable_dmic,
  2064. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2065. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2066. wcd938x_codec_enable_dmic,
  2067. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2068. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2069. wcd938x_codec_enable_dmic,
  2070. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2071. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2072. wcd938x_codec_enable_dmic,
  2073. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2074. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2075. wcd938x_codec_enable_dmic,
  2076. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2077. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2078. wcd938x_codec_enable_dmic,
  2079. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2080. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  2081. wcd938x_codec_enable_dmic,
  2082. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2083. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  2084. wcd938x_codec_enable_dmic,
  2085. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2086. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2087. NULL, 0, wcd938x_enable_req,
  2088. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2089. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  2090. NULL, 0, wcd938x_enable_req,
  2091. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2092. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  2093. NULL, 0, wcd938x_enable_req,
  2094. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2095. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  2096. NULL, 0, wcd938x_enable_req,
  2097. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2098. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2099. &tx_adc2_mux),
  2100. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2101. &tx_adc3_mux),
  2102. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  2103. &tx_adc4_mux),
  2104. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  2105. &tx_hdr12_mux),
  2106. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  2107. &tx_hdr34_mux),
  2108. /*tx mixers*/
  2109. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  2110. adc1_switch, ARRAY_SIZE(adc1_switch),
  2111. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2112. SND_SOC_DAPM_POST_PMD),
  2113. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  2114. adc2_switch, ARRAY_SIZE(adc2_switch),
  2115. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2116. SND_SOC_DAPM_POST_PMD),
  2117. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  2118. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  2119. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2120. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
  2121. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  2122. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2123. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2124. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2125. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2126. SND_SOC_DAPM_POST_PMD),
  2127. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  2128. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2129. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2130. SND_SOC_DAPM_POST_PMD),
  2131. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  2132. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2133. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2134. SND_SOC_DAPM_POST_PMD),
  2135. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  2136. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2137. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2138. SND_SOC_DAPM_POST_PMD),
  2139. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  2140. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2141. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2142. SND_SOC_DAPM_POST_PMD),
  2143. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  2144. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2145. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2146. SND_SOC_DAPM_POST_PMD),
  2147. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0,
  2148. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  2149. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2150. SND_SOC_DAPM_POST_PMD),
  2151. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0,
  2152. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  2153. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2154. SND_SOC_DAPM_POST_PMD),
  2155. /* micbias widgets*/
  2156. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2157. wcd938x_codec_enable_micbias,
  2158. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2159. SND_SOC_DAPM_POST_PMD),
  2160. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2161. wcd938x_codec_enable_micbias,
  2162. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2163. SND_SOC_DAPM_POST_PMD),
  2164. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2165. wcd938x_codec_enable_micbias,
  2166. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2167. SND_SOC_DAPM_POST_PMD),
  2168. SND_SOC_DAPM_MICBIAS_E("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2169. wcd938x_codec_enable_micbias,
  2170. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2171. SND_SOC_DAPM_POST_PMD),
  2172. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2173. wcd938x_enable_clsh,
  2174. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2175. /*rx widgets*/
  2176. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  2177. wcd938x_codec_enable_ear_pa,
  2178. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2179. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2180. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  2181. wcd938x_codec_enable_aux_pa,
  2182. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2183. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2184. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  2185. wcd938x_codec_enable_hphl_pa,
  2186. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2187. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2188. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  2189. wcd938x_codec_enable_hphr_pa,
  2190. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2191. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2192. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2193. wcd938x_codec_hphl_dac_event,
  2194. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2195. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2196. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2197. wcd938x_codec_hphr_dac_event,
  2198. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2199. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2200. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2201. wcd938x_codec_ear_dac_event,
  2202. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2203. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2204. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2205. wcd938x_codec_aux_dac_event,
  2206. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2207. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2208. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2209. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2210. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2211. SND_SOC_DAPM_POST_PMD),
  2212. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2213. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2214. SND_SOC_DAPM_POST_PMD),
  2215. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2216. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2217. SND_SOC_DAPM_POST_PMD),
  2218. /* rx mixer widgets*/
  2219. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2220. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2221. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2222. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2223. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2224. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2225. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2226. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2227. /*output widgets tx*/
  2228. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  2229. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  2230. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  2231. SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
  2232. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  2233. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  2234. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  2235. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  2236. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  2237. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  2238. SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
  2239. SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
  2240. /*output widgets rx*/
  2241. SND_SOC_DAPM_OUTPUT("EAR"),
  2242. SND_SOC_DAPM_OUTPUT("AUX"),
  2243. SND_SOC_DAPM_OUTPUT("HPHL"),
  2244. SND_SOC_DAPM_OUTPUT("HPHR"),
  2245. /* micbias pull up widgets*/
  2246. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2247. wcd938x_codec_enable_micbias_pullup,
  2248. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2249. SND_SOC_DAPM_POST_PMD),
  2250. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2251. wcd938x_codec_enable_micbias_pullup,
  2252. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2253. SND_SOC_DAPM_POST_PMD),
  2254. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2255. wcd938x_codec_enable_micbias_pullup,
  2256. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2257. SND_SOC_DAPM_POST_PMD),
  2258. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2259. wcd938x_codec_enable_micbias_pullup,
  2260. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2261. SND_SOC_DAPM_POST_PMD),
  2262. };
  2263. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  2264. {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
  2265. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2266. {"ADC1 REQ", NULL, "ADC1"},
  2267. {"ADC1", NULL, "AMIC1"},
  2268. {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
  2269. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2270. {"ADC2 REQ", NULL, "ADC2"},
  2271. {"ADC2", NULL, "HDR12 MUX"},
  2272. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  2273. {"HDR12 MUX", "HDR12", "AMIC1"},
  2274. {"ADC2 MUX", "INP3", "AMIC3"},
  2275. {"ADC2 MUX", "INP2", "AMIC2"},
  2276. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  2277. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2278. {"ADC3 REQ", NULL, "ADC3"},
  2279. {"ADC3", NULL, "HDR34 MUX"},
  2280. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  2281. {"HDR34 MUX", "HDR34", "AMIC5"},
  2282. {"ADC3 MUX", "INP4", "AMIC4"},
  2283. {"ADC3 MUX", "INP6", "AMIC6"},
  2284. {"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
  2285. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  2286. {"ADC4 REQ", NULL, "ADC4"},
  2287. {"ADC4", NULL, "ADC4 MUX"},
  2288. {"ADC4 MUX", "INP5", "AMIC5"},
  2289. {"ADC4 MUX", "INP7", "AMIC7"},
  2290. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  2291. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2292. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  2293. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2294. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  2295. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2296. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  2297. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2298. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  2299. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2300. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  2301. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2302. {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
  2303. {"DMIC7_MIXER", "Switch", "DMIC7"},
  2304. {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
  2305. {"DMIC8_MIXER", "Switch", "DMIC8"},
  2306. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2307. {"RX1", NULL, "IN1_HPHL"},
  2308. {"RDAC1", NULL, "RX1"},
  2309. {"HPHL_RDAC", "Switch", "RDAC1"},
  2310. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2311. {"HPHL", NULL, "HPHL PGA"},
  2312. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2313. {"RX2", NULL, "IN2_HPHR"},
  2314. {"RDAC2", NULL, "RX2"},
  2315. {"HPHR_RDAC", "Switch", "RDAC2"},
  2316. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2317. {"HPHR", NULL, "HPHR PGA"},
  2318. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2319. {"RX3", NULL, "IN3_AUX"},
  2320. {"RDAC4", NULL, "RX3"},
  2321. {"AUX_RDAC", "Switch", "RDAC4"},
  2322. {"AUX PGA", NULL, "AUX_RDAC"},
  2323. {"AUX", NULL, "AUX PGA"},
  2324. {"RDAC3_MUX", "RX3", "RX3"},
  2325. {"RDAC3_MUX", "RX1", "RX1"},
  2326. {"RDAC3", NULL, "RDAC3_MUX"},
  2327. {"EAR_RDAC", "Switch", "RDAC3"},
  2328. {"EAR PGA", NULL, "EAR_RDAC"},
  2329. {"EAR", NULL, "EAR PGA"},
  2330. };
  2331. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  2332. void *file_private_data,
  2333. struct file *file,
  2334. char __user *buf, size_t count,
  2335. loff_t pos)
  2336. {
  2337. struct wcd938x_priv *priv;
  2338. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  2339. int len = 0;
  2340. priv = (struct wcd938x_priv *) entry->private_data;
  2341. if (!priv) {
  2342. pr_err("%s: wcd938x priv is null\n", __func__);
  2343. return -EINVAL;
  2344. }
  2345. switch (priv->version) {
  2346. case WCD938X_VERSION_1_0:
  2347. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  2348. break;
  2349. default:
  2350. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2351. }
  2352. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2353. }
  2354. static struct snd_info_entry_ops wcd938x_info_ops = {
  2355. .read = wcd938x_version_read,
  2356. };
  2357. static ssize_t wcd938x_variant_read(struct snd_info_entry *entry,
  2358. void *file_private_data,
  2359. struct file *file,
  2360. char __user *buf, size_t count,
  2361. loff_t pos)
  2362. {
  2363. struct wcd938x_priv *priv;
  2364. char buffer[WCD938X_VARIANT_ENTRY_SIZE];
  2365. int len = 0;
  2366. priv = (struct wcd938x_priv *) entry->private_data;
  2367. if (!priv) {
  2368. pr_err("%s: wcd938x priv is null\n", __func__);
  2369. return -EINVAL;
  2370. }
  2371. switch (priv->variant) {
  2372. case WCD9380:
  2373. len = snprintf(buffer, sizeof(buffer), "WCD9380\n");
  2374. break;
  2375. case WCD9385:
  2376. len = snprintf(buffer, sizeof(buffer), "WCD9385\n");
  2377. break;
  2378. default:
  2379. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2380. }
  2381. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2382. }
  2383. static struct snd_info_entry_ops wcd938x_variant_ops = {
  2384. .read = wcd938x_variant_read,
  2385. };
  2386. /*
  2387. * wcd938x_info_create_codec_entry - creates wcd938x module
  2388. * @codec_root: The parent directory
  2389. * @component: component instance
  2390. *
  2391. * Creates wcd938x module, variant and version entry under the given
  2392. * parent directory.
  2393. *
  2394. * Return: 0 on success or negative error code on failure.
  2395. */
  2396. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2397. struct snd_soc_component *component)
  2398. {
  2399. struct snd_info_entry *version_entry;
  2400. struct snd_info_entry *variant_entry;
  2401. struct wcd938x_priv *priv;
  2402. struct snd_soc_card *card;
  2403. if (!codec_root || !component)
  2404. return -EINVAL;
  2405. priv = snd_soc_component_get_drvdata(component);
  2406. if (priv->entry) {
  2407. dev_dbg(priv->dev,
  2408. "%s:wcd938x module already created\n", __func__);
  2409. return 0;
  2410. }
  2411. card = component->card;
  2412. priv->entry = snd_info_create_subdir(codec_root->module,
  2413. "wcd938x", codec_root);
  2414. if (!priv->entry) {
  2415. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  2416. __func__);
  2417. return -ENOMEM;
  2418. }
  2419. version_entry = snd_info_create_card_entry(card->snd_card,
  2420. "version",
  2421. priv->entry);
  2422. if (!version_entry) {
  2423. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  2424. __func__);
  2425. return -ENOMEM;
  2426. }
  2427. version_entry->private_data = priv;
  2428. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  2429. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2430. version_entry->c.ops = &wcd938x_info_ops;
  2431. if (snd_info_register(version_entry) < 0) {
  2432. snd_info_free_entry(version_entry);
  2433. return -ENOMEM;
  2434. }
  2435. priv->version_entry = version_entry;
  2436. variant_entry = snd_info_create_card_entry(card->snd_card,
  2437. "variant",
  2438. priv->entry);
  2439. if (!variant_entry) {
  2440. dev_dbg(component->dev, "%s: failed to create wcd938x variant entry\n",
  2441. __func__);
  2442. return -ENOMEM;
  2443. }
  2444. variant_entry->private_data = priv;
  2445. variant_entry->size = WCD938X_VARIANT_ENTRY_SIZE;
  2446. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2447. variant_entry->c.ops = &wcd938x_variant_ops;
  2448. if (snd_info_register(variant_entry) < 0) {
  2449. snd_info_free_entry(variant_entry);
  2450. return -ENOMEM;
  2451. }
  2452. priv->variant_entry = variant_entry;
  2453. return 0;
  2454. }
  2455. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  2456. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  2457. {
  2458. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2459. struct snd_soc_dapm_context *dapm =
  2460. snd_soc_component_get_dapm(component);
  2461. int variant;
  2462. int ret = -EINVAL;
  2463. dev_info(component->dev, "%s()\n", __func__);
  2464. wcd938x = snd_soc_component_get_drvdata(component);
  2465. if (!wcd938x)
  2466. return -EINVAL;
  2467. wcd938x->component = component;
  2468. snd_soc_component_init_regmap(component, wcd938x->regmap);
  2469. variant = (snd_soc_component_read32(component,
  2470. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2471. wcd938x->variant = variant;
  2472. wcd938x->fw_data = devm_kzalloc(component->dev,
  2473. sizeof(*(wcd938x->fw_data)),
  2474. GFP_KERNEL);
  2475. if (!wcd938x->fw_data) {
  2476. dev_err(component->dev, "Failed to allocate fw_data\n");
  2477. ret = -ENOMEM;
  2478. goto err;
  2479. }
  2480. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  2481. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  2482. WCD9XXX_CODEC_HWDEP_NODE, component);
  2483. if (ret < 0) {
  2484. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2485. goto err_hwdep;
  2486. }
  2487. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  2488. if (ret) {
  2489. pr_err("%s: mbhc initialization failed\n", __func__);
  2490. goto err_hwdep;
  2491. }
  2492. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2493. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2494. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2495. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2496. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  2497. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  2498. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  2499. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2500. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2501. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2502. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2503. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2504. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2505. snd_soc_dapm_ignore_suspend(dapm, "DMIC7_OUTPUT");
  2506. snd_soc_dapm_ignore_suspend(dapm, "DMIC8_OUTPUT");
  2507. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2508. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2509. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2510. snd_soc_dapm_ignore_suspend(dapm, "ADC4_OUTPUT");
  2511. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2512. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2513. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2514. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2515. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2516. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2517. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2518. snd_soc_dapm_sync(dapm);
  2519. wcd_cls_h_init(&wcd938x->clsh_info);
  2520. wcd938x_init_reg(component);
  2521. if (wcd938x->variant == WCD9380) {
  2522. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  2523. ARRAY_SIZE(wcd9380_snd_controls));
  2524. if (ret < 0) {
  2525. dev_err(component->dev,
  2526. "%s: Failed to add snd ctrls for variant: %d\n",
  2527. __func__, wcd938x->variant);
  2528. goto err_hwdep;
  2529. }
  2530. }
  2531. if (wcd938x->variant == WCD9385) {
  2532. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  2533. ARRAY_SIZE(wcd9385_snd_controls));
  2534. if (ret < 0) {
  2535. dev_err(component->dev,
  2536. "%s: Failed to add snd ctrls for variant: %d\n",
  2537. __func__, wcd938x->variant);
  2538. goto err_hwdep;
  2539. }
  2540. }
  2541. wcd938x->version = WCD938X_VERSION_1_0;
  2542. /* Register event notifier */
  2543. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  2544. if (wcd938x->register_notifier) {
  2545. ret = wcd938x->register_notifier(wcd938x->handle,
  2546. &wcd938x->nblock,
  2547. true);
  2548. if (ret) {
  2549. dev_err(component->dev,
  2550. "%s: Failed to register notifier %d\n",
  2551. __func__, ret);
  2552. return ret;
  2553. }
  2554. }
  2555. return ret;
  2556. err_hwdep:
  2557. wcd938x->fw_data = NULL;
  2558. err:
  2559. return ret;
  2560. }
  2561. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  2562. {
  2563. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2564. if (!wcd938x) {
  2565. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  2566. __func__);
  2567. return;
  2568. }
  2569. if (wcd938x->register_notifier)
  2570. wcd938x->register_notifier(wcd938x->handle,
  2571. &wcd938x->nblock,
  2572. false);
  2573. }
  2574. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  2575. .name = WCD938X_DRV_NAME,
  2576. .probe = wcd938x_soc_codec_probe,
  2577. .remove = wcd938x_soc_codec_remove,
  2578. .controls = wcd938x_snd_controls,
  2579. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  2580. .dapm_widgets = wcd938x_dapm_widgets,
  2581. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  2582. .dapm_routes = wcd938x_audio_map,
  2583. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  2584. };
  2585. static int wcd938x_reset(struct device *dev)
  2586. {
  2587. struct wcd938x_priv *wcd938x = NULL;
  2588. int rc = 0;
  2589. int value = 0;
  2590. if (!dev)
  2591. return -ENODEV;
  2592. wcd938x = dev_get_drvdata(dev);
  2593. if (!wcd938x)
  2594. return -EINVAL;
  2595. if (!wcd938x->rst_np) {
  2596. dev_err(dev, "%s: reset gpio device node not specified\n",
  2597. __func__);
  2598. return -EINVAL;
  2599. }
  2600. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  2601. if (value > 0)
  2602. return 0;
  2603. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2604. if (rc) {
  2605. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2606. __func__);
  2607. return rc;
  2608. }
  2609. /* 20us sleep required after pulling the reset gpio to LOW */
  2610. usleep_range(20, 30);
  2611. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  2612. if (rc) {
  2613. dev_err(dev, "%s: wcd active state request fail!\n",
  2614. __func__);
  2615. return rc;
  2616. }
  2617. /* 20us sleep required after pulling the reset gpio to HIGH */
  2618. usleep_range(20, 30);
  2619. return rc;
  2620. }
  2621. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  2622. u32 *val)
  2623. {
  2624. int rc = 0;
  2625. rc = of_property_read_u32(dev->of_node, name, val);
  2626. if (rc)
  2627. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2628. __func__, name, dev->of_node->full_name);
  2629. return rc;
  2630. }
  2631. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  2632. struct wcd938x_micbias_setting *mb)
  2633. {
  2634. u32 prop_val = 0;
  2635. int rc = 0;
  2636. /* MB1 */
  2637. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2638. NULL)) {
  2639. rc = wcd938x_read_of_property_u32(dev,
  2640. "qcom,cdc-micbias1-mv",
  2641. &prop_val);
  2642. if (!rc)
  2643. mb->micb1_mv = prop_val;
  2644. } else {
  2645. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2646. __func__);
  2647. }
  2648. /* MB2 */
  2649. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2650. NULL)) {
  2651. rc = wcd938x_read_of_property_u32(dev,
  2652. "qcom,cdc-micbias2-mv",
  2653. &prop_val);
  2654. if (!rc)
  2655. mb->micb2_mv = prop_val;
  2656. } else {
  2657. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2658. __func__);
  2659. }
  2660. /* MB3 */
  2661. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2662. NULL)) {
  2663. rc = wcd938x_read_of_property_u32(dev,
  2664. "qcom,cdc-micbias3-mv",
  2665. &prop_val);
  2666. if (!rc)
  2667. mb->micb3_mv = prop_val;
  2668. } else {
  2669. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2670. __func__);
  2671. }
  2672. }
  2673. static int wcd938x_reset_low(struct device *dev)
  2674. {
  2675. struct wcd938x_priv *wcd938x = NULL;
  2676. int rc = 0;
  2677. if (!dev)
  2678. return -ENODEV;
  2679. wcd938x = dev_get_drvdata(dev);
  2680. if (!wcd938x)
  2681. return -EINVAL;
  2682. if (!wcd938x->rst_np) {
  2683. dev_err(dev, "%s: reset gpio device node not specified\n",
  2684. __func__);
  2685. return -EINVAL;
  2686. }
  2687. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2688. if (rc) {
  2689. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2690. __func__);
  2691. return rc;
  2692. }
  2693. /* 20us sleep required after pulling the reset gpio to LOW */
  2694. usleep_range(20, 30);
  2695. return rc;
  2696. }
  2697. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  2698. {
  2699. struct wcd938x_pdata *pdata = NULL;
  2700. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  2701. GFP_KERNEL);
  2702. if (!pdata)
  2703. return NULL;
  2704. pdata->rst_np = of_parse_phandle(dev->of_node,
  2705. "qcom,wcd-rst-gpio-node", 0);
  2706. if (!pdata->rst_np) {
  2707. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2708. __func__, "qcom,wcd-rst-gpio-node",
  2709. dev->of_node->full_name);
  2710. return NULL;
  2711. }
  2712. /* Parse power supplies */
  2713. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2714. &pdata->num_supplies);
  2715. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2716. dev_err(dev, "%s: no power supplies defined for codec\n",
  2717. __func__);
  2718. return NULL;
  2719. }
  2720. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2721. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2722. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  2723. return pdata;
  2724. }
  2725. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  2726. {
  2727. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2728. __func__, irq);
  2729. return IRQ_HANDLED;
  2730. }
  2731. static int wcd938x_bind(struct device *dev)
  2732. {
  2733. int ret = 0, i = 0;
  2734. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  2735. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2736. /*
  2737. * Add 5msec delay to provide sufficient time for
  2738. * soundwire auto enumeration of slave devices as
  2739. * as per HW requirement.
  2740. */
  2741. usleep_range(5000, 5010);
  2742. ret = component_bind_all(dev, wcd938x);
  2743. if (ret) {
  2744. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2745. __func__, ret);
  2746. return ret;
  2747. }
  2748. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2749. if (!wcd938x->rx_swr_dev) {
  2750. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2751. __func__);
  2752. ret = -ENODEV;
  2753. goto err;
  2754. }
  2755. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2756. if (!wcd938x->tx_swr_dev) {
  2757. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2758. __func__);
  2759. ret = -ENODEV;
  2760. goto err;
  2761. }
  2762. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  2763. &wcd938x_regmap_config);
  2764. if (!wcd938x->regmap) {
  2765. dev_err(dev, "%s: Regmap init failed\n",
  2766. __func__);
  2767. goto err;
  2768. }
  2769. /* Set all interupts as edge triggered */
  2770. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  2771. regmap_write(wcd938x->regmap,
  2772. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2773. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  2774. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  2775. wcd938x->irq_info.codec_name = "WCD938X";
  2776. wcd938x->irq_info.regmap = wcd938x->regmap;
  2777. wcd938x->irq_info.dev = dev;
  2778. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  2779. if (ret) {
  2780. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  2781. __func__, ret);
  2782. goto err;
  2783. }
  2784. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  2785. /* Request for watchdog interrupt */
  2786. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  2787. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  2788. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  2789. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  2790. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  2791. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  2792. /* Disable watchdog interrupt for HPH and AUX */
  2793. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  2794. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  2795. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  2796. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  2797. NULL, 0);
  2798. if (ret) {
  2799. dev_err(dev, "%s: Codec registration failed\n",
  2800. __func__);
  2801. goto err_irq;
  2802. }
  2803. return ret;
  2804. err_irq:
  2805. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2806. err:
  2807. component_unbind_all(dev, wcd938x);
  2808. return ret;
  2809. }
  2810. static void wcd938x_unbind(struct device *dev)
  2811. {
  2812. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2813. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT, NULL);
  2814. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT, NULL);
  2815. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT, NULL);
  2816. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2817. snd_soc_unregister_component(dev);
  2818. component_unbind_all(dev, wcd938x);
  2819. }
  2820. static const struct of_device_id wcd938x_dt_match[] = {
  2821. { .compatible = "qcom,wcd938x-codec" },
  2822. {}
  2823. };
  2824. static const struct component_master_ops wcd938x_comp_ops = {
  2825. .bind = wcd938x_bind,
  2826. .unbind = wcd938x_unbind,
  2827. };
  2828. static int wcd938x_compare_of(struct device *dev, void *data)
  2829. {
  2830. return dev->of_node == data;
  2831. }
  2832. static void wcd938x_release_of(struct device *dev, void *data)
  2833. {
  2834. of_node_put(data);
  2835. }
  2836. static int wcd938x_add_slave_components(struct device *dev,
  2837. struct component_match **matchptr)
  2838. {
  2839. struct device_node *np, *rx_node, *tx_node;
  2840. np = dev->of_node;
  2841. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  2842. if (!rx_node) {
  2843. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  2844. return -ENODEV;
  2845. }
  2846. of_node_get(rx_node);
  2847. component_match_add_release(dev, matchptr,
  2848. wcd938x_release_of,
  2849. wcd938x_compare_of,
  2850. rx_node);
  2851. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  2852. if (!tx_node) {
  2853. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  2854. return -ENODEV;
  2855. }
  2856. of_node_get(tx_node);
  2857. component_match_add_release(dev, matchptr,
  2858. wcd938x_release_of,
  2859. wcd938x_compare_of,
  2860. tx_node);
  2861. return 0;
  2862. }
  2863. static int wcd938x_wakeup(void *handle, bool enable)
  2864. {
  2865. struct wcd938x_priv *priv;
  2866. if (!handle) {
  2867. pr_err("%s: NULL handle\n", __func__);
  2868. return -EINVAL;
  2869. }
  2870. priv = (struct wcd938x_priv *)handle;
  2871. if (!priv->tx_swr_dev) {
  2872. pr_err("%s: tx swr dev is NULL\n", __func__);
  2873. return -EINVAL;
  2874. }
  2875. if (enable)
  2876. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2877. else
  2878. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2879. }
  2880. static int wcd938x_probe(struct platform_device *pdev)
  2881. {
  2882. struct component_match *match = NULL;
  2883. struct wcd938x_priv *wcd938x = NULL;
  2884. struct wcd938x_pdata *pdata = NULL;
  2885. struct wcd_ctrl_platform_data *plat_data = NULL;
  2886. struct device *dev = &pdev->dev;
  2887. int ret;
  2888. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  2889. GFP_KERNEL);
  2890. if (!wcd938x)
  2891. return -ENOMEM;
  2892. dev_set_drvdata(dev, wcd938x);
  2893. wcd938x->dev = dev;
  2894. pdata = wcd938x_populate_dt_data(dev);
  2895. if (!pdata) {
  2896. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2897. return -EINVAL;
  2898. }
  2899. dev->platform_data = pdata;
  2900. wcd938x->rst_np = pdata->rst_np;
  2901. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  2902. pdata->regulator, pdata->num_supplies);
  2903. if (!wcd938x->supplies) {
  2904. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2905. __func__);
  2906. return ret;
  2907. }
  2908. plat_data = dev_get_platdata(dev->parent);
  2909. if (!plat_data) {
  2910. dev_err(dev, "%s: platform data from parent is NULL\n",
  2911. __func__);
  2912. return -EINVAL;
  2913. }
  2914. wcd938x->handle = (void *)plat_data->handle;
  2915. if (!wcd938x->handle) {
  2916. dev_err(dev, "%s: handle is NULL\n", __func__);
  2917. return -EINVAL;
  2918. }
  2919. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  2920. if (!wcd938x->update_wcd_event) {
  2921. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2922. __func__);
  2923. return -EINVAL;
  2924. }
  2925. wcd938x->register_notifier = plat_data->register_notifier;
  2926. if (!wcd938x->register_notifier) {
  2927. dev_err(dev, "%s: register_notifier api is null!\n",
  2928. __func__);
  2929. return -EINVAL;
  2930. }
  2931. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  2932. pdata->regulator,
  2933. pdata->num_supplies);
  2934. if (ret) {
  2935. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2936. __func__);
  2937. return ret;
  2938. }
  2939. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  2940. CODEC_RX);
  2941. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  2942. CODEC_TX);
  2943. if (ret) {
  2944. dev_err(dev, "Failed to read port mapping\n");
  2945. goto err;
  2946. }
  2947. mutex_init(&wcd938x->micb_lock);
  2948. ret = wcd938x_add_slave_components(dev, &match);
  2949. if (ret)
  2950. goto err_lock_init;
  2951. wcd938x_reset(dev);
  2952. wcd938x->wakeup = wcd938x_wakeup;
  2953. return component_master_add_with_match(dev,
  2954. &wcd938x_comp_ops, match);
  2955. err_lock_init:
  2956. mutex_destroy(&wcd938x->micb_lock);
  2957. err:
  2958. return ret;
  2959. }
  2960. static int wcd938x_remove(struct platform_device *pdev)
  2961. {
  2962. struct wcd938x_priv *wcd938x = NULL;
  2963. wcd938x = platform_get_drvdata(pdev);
  2964. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  2965. mutex_destroy(&wcd938x->micb_lock);
  2966. dev_set_drvdata(&pdev->dev, NULL);
  2967. return 0;
  2968. }
  2969. #ifdef CONFIG_PM_SLEEP
  2970. static int wcd938x_suspend(struct device *dev)
  2971. {
  2972. return 0;
  2973. }
  2974. static int wcd938x_resume(struct device *dev)
  2975. {
  2976. return 0;
  2977. }
  2978. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  2979. SET_SYSTEM_SLEEP_PM_OPS(
  2980. wcd938x_suspend,
  2981. wcd938x_resume
  2982. )
  2983. };
  2984. #endif
  2985. static struct platform_driver wcd938x_codec_driver = {
  2986. .probe = wcd938x_probe,
  2987. .remove = wcd938x_remove,
  2988. .driver = {
  2989. .name = "wcd938x_codec",
  2990. .owner = THIS_MODULE,
  2991. .of_match_table = of_match_ptr(wcd938x_dt_match),
  2992. #ifdef CONFIG_PM_SLEEP
  2993. .pm = &wcd938x_dev_pm_ops,
  2994. #endif
  2995. .suppress_bind_attrs = true,
  2996. },
  2997. };
  2998. module_platform_driver(wcd938x_codec_driver);
  2999. MODULE_DESCRIPTION("WCD938X Codec driver");
  3000. MODULE_LICENSE("GPL v2");