wcd937x.c 85 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <linux/regmap.h>
  13. #include <linux/pm_runtime.h>
  14. #include <sound/soc.h>
  15. #include <sound/tlv.h>
  16. #include <soc/soundwire.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include "internal.h"
  20. #include "wcd937x.h"
  21. #include <asoc/wcdcal-hwdep.h>
  22. #include "wcd937x-registers.h"
  23. #include <asoc/msm-cdc-pinctrl.h>
  24. #include <dt-bindings/sound/audio-codec-port-types.h>
  25. #include <asoc/msm-cdc-supply.h>
  26. #define DRV_NAME "wcd937x_codec"
  27. #define WCD9370_VARIANT 0
  28. #define WCD9375_VARIANT 5
  29. #define WCD937X_VARIANT_ENTRY_SIZE 32
  30. #define NUM_SWRS_DT_PARAMS 5
  31. #define WCD937X_VERSION_1_0 1
  32. #define WCD937X_VERSION_ENTRY_SIZE 32
  33. #define EAR_RX_PATH_AUX 1
  34. enum {
  35. CODEC_TX = 0,
  36. CODEC_RX,
  37. };
  38. enum {
  39. ALLOW_BUCK_DISABLE,
  40. HPH_COMP_DELAY,
  41. HPH_PA_DELAY,
  42. AMIC2_BCS_ENABLE,
  43. };
  44. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  45. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  46. static int wcd937x_handle_post_irq(void *data);
  47. static int wcd937x_reset(struct device *dev);
  48. static int wcd937x_reset_low(struct device *dev);
  49. static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = {
  50. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  51. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  52. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  53. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  54. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, 0x10),
  55. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, 0x20),
  56. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, 0x40),
  57. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, 0x80),
  58. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, 0x01),
  59. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, 0x02),
  60. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, 0x04),
  61. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, 0x08),
  62. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, 0x10),
  63. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  64. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  65. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  66. REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, 0x01),
  67. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  68. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  69. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  70. };
  71. static struct regmap_irq_chip wcd937x_regmap_irq_chip = {
  72. .name = "wcd937x",
  73. .irqs = wcd937x_irqs,
  74. .num_irqs = ARRAY_SIZE(wcd937x_irqs),
  75. .num_regs = 3,
  76. .status_base = WCD937X_DIGITAL_INTR_STATUS_0,
  77. .mask_base = WCD937X_DIGITAL_INTR_MASK_0,
  78. .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0,
  79. .use_ack = 1,
  80. .type_base = WCD937X_DIGITAL_INTR_LEVEL_0,
  81. .runtime_pm = false,
  82. .handle_post_irq = wcd937x_handle_post_irq,
  83. .irq_drv_data = NULL,
  84. };
  85. static int wcd937x_handle_post_irq(void *data)
  86. {
  87. struct wcd937x_priv *wcd937x = data;
  88. u32 status1 = 0, status2 = 0, status3 = 0;
  89. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_0, &status1);
  90. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_1, &status2);
  91. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_2, &status3);
  92. wcd937x->tx_swr_dev->slave_irq_pending =
  93. ((status1 || status2 || status3) ? true : false);
  94. return IRQ_HANDLED;
  95. }
  96. static int wcd937x_init_reg(struct snd_soc_component *component)
  97. {
  98. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  99. 0x0E, 0x0E);
  100. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  101. 0x80, 0x80);
  102. usleep_range(1000, 1010);
  103. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  104. 0x40, 0x40);
  105. usleep_range(1000, 1010);
  106. snd_soc_component_update_bits(component, WCD937X_LDORXTX_CONFIG,
  107. 0x10, 0x00);
  108. snd_soc_component_update_bits(component, WCD937X_BIAS_VBG_FINE_ADJ,
  109. 0xF0, 0x80);
  110. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  111. 0x80, 0x80);
  112. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  113. 0x40, 0x40);
  114. usleep_range(10000, 10010);
  115. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  116. 0x40, 0x00);
  117. snd_soc_component_update_bits(component,
  118. WCD937X_HPH_SURGE_HPHLR_SURGE_EN,
  119. 0xFF, 0xD9);
  120. snd_soc_component_update_bits(component, WCD937X_MICB1_TEST_CTL_1,
  121. 0xFF, 0xFA);
  122. snd_soc_component_update_bits(component, WCD937X_MICB2_TEST_CTL_1,
  123. 0xFF, 0xFA);
  124. snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_1,
  125. 0xFF, 0xFA);
  126. return 0;
  127. }
  128. static int wcd937x_set_port_params(struct snd_soc_component *component,
  129. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  130. u8 *ch_mask, u32 *ch_rate,
  131. u8 *port_type, u8 path)
  132. {
  133. int i, j;
  134. u8 num_ports = 0;
  135. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  136. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  137. switch (path) {
  138. case CODEC_RX:
  139. map = &wcd937x->rx_port_mapping;
  140. num_ports = wcd937x->num_rx_ports;
  141. break;
  142. case CODEC_TX:
  143. map = &wcd937x->tx_port_mapping;
  144. num_ports = wcd937x->num_tx_ports;
  145. break;
  146. }
  147. for (i = 0; i <= num_ports; i++) {
  148. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  149. if ((*map)[i][j].slave_port_type == slv_prt_type)
  150. goto found;
  151. }
  152. }
  153. found:
  154. if (i > num_ports || j == MAX_CH_PER_PORT) {
  155. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  156. __func__, slv_prt_type);
  157. return -EINVAL;
  158. }
  159. *port_id = i;
  160. *num_ch = (*map)[i][j].num_ch;
  161. *ch_mask = (*map)[i][j].ch_mask;
  162. *ch_rate = (*map)[i][j].ch_rate;
  163. *port_type = (*map)[i][j].master_port_type;
  164. return 0;
  165. }
  166. static int wcd937x_parse_port_mapping(struct device *dev,
  167. char *prop, u8 path)
  168. {
  169. u32 *dt_array, map_size, map_length;
  170. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  171. u32 slave_port_type, master_port_type;
  172. u32 i, ch_iter = 0;
  173. int ret = 0;
  174. u8 *num_ports = NULL;
  175. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  176. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  177. switch (path) {
  178. case CODEC_RX:
  179. map = &wcd937x->rx_port_mapping;
  180. num_ports = &wcd937x->num_rx_ports;
  181. break;
  182. case CODEC_TX:
  183. map = &wcd937x->tx_port_mapping;
  184. num_ports = &wcd937x->num_tx_ports;
  185. break;
  186. }
  187. if (!of_find_property(dev->of_node, prop,
  188. &map_size)) {
  189. dev_err(dev, "missing port mapping prop %s\n", prop);
  190. ret = -EINVAL;
  191. goto err;
  192. }
  193. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  194. dt_array = kzalloc(map_size, GFP_KERNEL);
  195. if (!dt_array) {
  196. ret = -ENOMEM;
  197. goto err;
  198. }
  199. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  200. NUM_SWRS_DT_PARAMS * map_length);
  201. if (ret) {
  202. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  203. __func__, prop);
  204. ret = -EINVAL;
  205. goto err_pdata_fail;
  206. }
  207. for (i = 0; i < map_length; i++) {
  208. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  209. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  210. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  211. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  212. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  213. if (port_num != old_port_num)
  214. ch_iter = 0;
  215. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  216. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  217. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  218. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  219. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  220. old_port_num = port_num;
  221. }
  222. *num_ports = port_num;
  223. kfree(dt_array);
  224. return 0;
  225. err_pdata_fail:
  226. kfree(dt_array);
  227. err:
  228. return ret;
  229. }
  230. static int wcd937x_tx_connect_port(struct snd_soc_component *component,
  231. u8 slv_port_type, u8 enable)
  232. {
  233. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  234. u8 port_id;
  235. u8 num_ch;
  236. u8 ch_mask;
  237. u32 ch_rate;
  238. u8 port_type;
  239. u8 num_port = 1;
  240. int ret = 0;
  241. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  242. &num_ch, &ch_mask, &ch_rate,
  243. &port_type, CODEC_TX);
  244. if (ret)
  245. return ret;
  246. if (enable)
  247. ret = swr_connect_port(wcd937x->tx_swr_dev, &port_id,
  248. num_port, &ch_mask, &ch_rate,
  249. &num_ch, &port_type);
  250. else
  251. ret = swr_disconnect_port(wcd937x->tx_swr_dev, &port_id,
  252. num_port, &ch_mask, &port_type);
  253. return ret;
  254. }
  255. static int wcd937x_rx_connect_port(struct snd_soc_component *component,
  256. u8 slv_port_type, u8 enable)
  257. {
  258. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  259. u8 port_id;
  260. u8 num_ch;
  261. u8 ch_mask;
  262. u32 ch_rate;
  263. u8 port_type;
  264. u8 num_port = 1;
  265. int ret = 0;
  266. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  267. &num_ch, &ch_mask, &ch_rate,
  268. &port_type, CODEC_RX);
  269. if (ret)
  270. return ret;
  271. if (enable)
  272. ret = swr_connect_port(wcd937x->rx_swr_dev, &port_id,
  273. num_port, &ch_mask, &ch_rate,
  274. &num_ch, &port_type);
  275. else
  276. ret = swr_disconnect_port(wcd937x->rx_swr_dev, &port_id,
  277. num_port, &ch_mask, &port_type);
  278. return ret;
  279. }
  280. static int wcd937x_rx_clk_enable(struct snd_soc_component *component)
  281. {
  282. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  283. if (wcd937x->rx_clk_cnt == 0) {
  284. snd_soc_component_update_bits(component,
  285. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x08, 0x08);
  286. snd_soc_component_update_bits(component,
  287. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  288. snd_soc_component_update_bits(component,
  289. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x01);
  290. snd_soc_component_update_bits(component,
  291. WCD937X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  292. snd_soc_component_update_bits(component,
  293. WCD937X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  294. snd_soc_component_update_bits(component,
  295. WCD937X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  296. snd_soc_component_update_bits(component,
  297. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  298. }
  299. wcd937x->rx_clk_cnt++;
  300. return 0;
  301. }
  302. static int wcd937x_rx_clk_disable(struct snd_soc_component *component)
  303. {
  304. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  305. if (wcd937x->rx_clk_cnt == 0) {
  306. dev_dbg(wcd937x->dev, "%s:clk already disabled\n", __func__);
  307. return 0;
  308. }
  309. wcd937x->rx_clk_cnt--;
  310. if (wcd937x->rx_clk_cnt == 0) {
  311. snd_soc_component_update_bits(component,
  312. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x00);
  313. snd_soc_component_update_bits(component,
  314. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  315. 0x02, 0x00);
  316. snd_soc_component_update_bits(component,
  317. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  318. 0x01, 0x00);
  319. }
  320. return 0;
  321. }
  322. /*
  323. * wcd937x_soc_get_mbhc: get wcd937x_mbhc handle of corresponding component
  324. * @component: handle to snd_soc_component *
  325. *
  326. * return wcd937x_mbhc handle or error code in case of failure
  327. */
  328. struct wcd937x_mbhc *wcd937x_soc_get_mbhc(struct snd_soc_component *component)
  329. {
  330. struct wcd937x_priv *wcd937x;
  331. if (!component) {
  332. pr_err("%s: Invalid params, NULL component\n", __func__);
  333. return NULL;
  334. }
  335. wcd937x = snd_soc_component_get_drvdata(component);
  336. if (!wcd937x) {
  337. pr_err("%s: Invalid params, NULL tavil\n", __func__);
  338. return NULL;
  339. }
  340. return wcd937x->mbhc;
  341. }
  342. EXPORT_SYMBOL(wcd937x_soc_get_mbhc);
  343. static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  344. struct snd_kcontrol *kcontrol,
  345. int event)
  346. {
  347. struct snd_soc_component *component =
  348. snd_soc_dapm_to_component(w->dapm);
  349. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  350. int hph_mode = wcd937x->hph_mode;
  351. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  352. w->name, event);
  353. switch (event) {
  354. case SND_SOC_DAPM_PRE_PMU:
  355. wcd937x_rx_clk_enable(component);
  356. snd_soc_component_update_bits(component,
  357. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  358. 0x01, 0x01);
  359. snd_soc_component_update_bits(component,
  360. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  361. 0x04, 0x04);
  362. snd_soc_component_update_bits(component,
  363. WCD937X_HPH_RDAC_CLK_CTL1,
  364. 0x80, 0x00);
  365. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  366. break;
  367. case SND_SOC_DAPM_POST_PMU:
  368. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  369. snd_soc_component_update_bits(component,
  370. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  371. 0x0F, 0x02);
  372. else if (hph_mode == CLS_H_LOHIFI)
  373. snd_soc_component_update_bits(component,
  374. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  375. 0x0F, 0x06);
  376. if (wcd937x->comp1_enable) {
  377. snd_soc_component_update_bits(component,
  378. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  379. 0x02, 0x02);
  380. snd_soc_component_update_bits(component,
  381. WCD937X_HPH_L_EN, 0x20, 0x00);
  382. if (wcd937x->comp2_enable) {
  383. snd_soc_component_update_bits(component,
  384. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  385. 0x01, 0x01);
  386. snd_soc_component_update_bits(component,
  387. WCD937X_HPH_R_EN, 0x20, 0x00);
  388. }
  389. /*
  390. * 5ms sleep is required after COMP is enabled as per
  391. * HW requirement
  392. */
  393. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  394. usleep_range(5000, 5100);
  395. clear_bit(HPH_COMP_DELAY,
  396. &wcd937x->status_mask);
  397. }
  398. } else {
  399. snd_soc_component_update_bits(component,
  400. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  401. 0x02, 0x00);
  402. snd_soc_component_update_bits(component,
  403. WCD937X_HPH_L_EN, 0x20, 0x20);
  404. }
  405. snd_soc_component_update_bits(component,
  406. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  407. break;
  408. case SND_SOC_DAPM_POST_PMD:
  409. snd_soc_component_update_bits(component,
  410. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  411. 0x0F, 0x01);
  412. break;
  413. }
  414. return 0;
  415. }
  416. static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  417. struct snd_kcontrol *kcontrol,
  418. int event)
  419. {
  420. struct snd_soc_component *component =
  421. snd_soc_dapm_to_component(w->dapm);
  422. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  423. int hph_mode = wcd937x->hph_mode;
  424. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  425. w->name, event);
  426. switch (event) {
  427. case SND_SOC_DAPM_PRE_PMU:
  428. wcd937x_rx_clk_enable(component);
  429. snd_soc_component_update_bits(component,
  430. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  431. snd_soc_component_update_bits(component,
  432. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  433. snd_soc_component_update_bits(component,
  434. WCD937X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  435. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  436. break;
  437. case SND_SOC_DAPM_POST_PMU:
  438. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  439. snd_soc_component_update_bits(component,
  440. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  441. 0x0F, 0x02);
  442. else if (hph_mode == CLS_H_LOHIFI)
  443. snd_soc_component_update_bits(component,
  444. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  445. 0x0F, 0x06);
  446. if (wcd937x->comp2_enable) {
  447. snd_soc_component_update_bits(component,
  448. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  449. 0x01, 0x01);
  450. snd_soc_component_update_bits(component,
  451. WCD937X_HPH_R_EN, 0x20, 0x00);
  452. if (wcd937x->comp1_enable) {
  453. snd_soc_component_update_bits(component,
  454. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  455. 0x02, 0x02);
  456. snd_soc_component_update_bits(component,
  457. WCD937X_HPH_L_EN, 0x20, 0x00);
  458. }
  459. /*
  460. * 5ms sleep is required after COMP is enabled as per
  461. * HW requirement
  462. */
  463. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  464. usleep_range(5000, 5100);
  465. clear_bit(HPH_COMP_DELAY,
  466. &wcd937x->status_mask);
  467. }
  468. } else {
  469. snd_soc_component_update_bits(component,
  470. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  471. 0x01, 0x00);
  472. snd_soc_component_update_bits(component,
  473. WCD937X_HPH_R_EN, 0x20, 0x20);
  474. }
  475. snd_soc_component_update_bits(component,
  476. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  477. break;
  478. case SND_SOC_DAPM_POST_PMD:
  479. snd_soc_component_update_bits(component,
  480. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  481. 0x0F, 0x01);
  482. break;
  483. }
  484. return 0;
  485. }
  486. static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  487. struct snd_kcontrol *kcontrol,
  488. int event)
  489. {
  490. struct snd_soc_component *component =
  491. snd_soc_dapm_to_component(w->dapm);
  492. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  493. int hph_mode = wcd937x->hph_mode;
  494. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  495. w->name, event);
  496. switch (event) {
  497. case SND_SOC_DAPM_PRE_PMU:
  498. wcd937x_rx_clk_enable(component);
  499. snd_soc_component_update_bits(component,
  500. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  501. 0x04, 0x04);
  502. snd_soc_component_update_bits(component,
  503. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  504. 0x01, 0x01);
  505. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  506. snd_soc_component_update_bits(component,
  507. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  508. 0x0F, 0x02);
  509. else if (hph_mode == CLS_H_LOHIFI)
  510. snd_soc_component_update_bits(component,
  511. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  512. 0x0F, 0x06);
  513. snd_soc_component_update_bits(component,
  514. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  515. 0x02, 0x02);
  516. usleep_range(5000, 5010);
  517. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  518. 0x04, 0x00);
  519. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  520. WCD_CLSH_EVENT_PRE_DAC,
  521. WCD_CLSH_STATE_EAR,
  522. hph_mode);
  523. break;
  524. case SND_SOC_DAPM_POST_PMD:
  525. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI ||
  526. hph_mode == CLS_H_HIFI)
  527. snd_soc_component_update_bits(component,
  528. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  529. 0x0F, 0x01);
  530. break;
  531. };
  532. return 0;
  533. }
  534. static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  535. struct snd_kcontrol *kcontrol,
  536. int event)
  537. {
  538. struct snd_soc_component *component =
  539. snd_soc_dapm_to_component(w->dapm);
  540. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  541. int hph_mode = wcd937x->hph_mode;
  542. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  543. w->name, event);
  544. switch (event) {
  545. case SND_SOC_DAPM_PRE_PMU:
  546. wcd937x_rx_clk_enable(component);
  547. snd_soc_component_update_bits(component,
  548. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  549. 0x04, 0x04);
  550. snd_soc_component_update_bits(component,
  551. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  552. 0x04, 0x04);
  553. snd_soc_component_update_bits(component,
  554. WCD937X_DIGITAL_CDC_AUX_GAIN_CTL,
  555. 0x01, 0x01);
  556. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  557. WCD_CLSH_EVENT_PRE_DAC,
  558. WCD_CLSH_STATE_AUX,
  559. hph_mode);
  560. break;
  561. case SND_SOC_DAPM_POST_PMD:
  562. wcd937x_rx_clk_disable(component);
  563. snd_soc_component_update_bits(component,
  564. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  565. 0x04, 0x00);
  566. break;
  567. };
  568. return 0;
  569. }
  570. static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  571. struct snd_kcontrol *kcontrol,
  572. int event)
  573. {
  574. struct snd_soc_component *component =
  575. snd_soc_dapm_to_component(w->dapm);
  576. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  577. int ret = 0;
  578. int hph_mode = wcd937x->hph_mode;
  579. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  580. w->name, event);
  581. switch (event) {
  582. case SND_SOC_DAPM_PRE_PMU:
  583. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  584. wcd937x->rx_swr_dev->dev_num,
  585. true);
  586. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  587. WCD_CLSH_EVENT_PRE_DAC,
  588. WCD_CLSH_STATE_HPHR,
  589. hph_mode);
  590. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  591. 0x10, 0x10);
  592. usleep_range(100, 110);
  593. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  594. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  595. wcd937x->rx_swr_dev->dev_num,
  596. true);
  597. snd_soc_component_update_bits(component,
  598. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  599. break;
  600. case SND_SOC_DAPM_POST_PMU:
  601. /*
  602. * 7ms sleep is required after PA is enabled as per
  603. * HW requirement. If compander is disabled, then
  604. * 20ms delay is required.
  605. */
  606. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  607. if (!wcd937x->comp2_enable)
  608. usleep_range(20000, 20100);
  609. else
  610. usleep_range(7000, 7100);
  611. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  612. }
  613. snd_soc_component_update_bits(component,
  614. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  615. 0x02, 0x02);
  616. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  617. snd_soc_component_update_bits(component,
  618. WCD937X_ANA_RX_SUPPLIES,
  619. 0x02, 0x02);
  620. if (wcd937x->update_wcd_event)
  621. wcd937x->update_wcd_event(wcd937x->handle,
  622. WCD_BOLERO_EVT_RX_MUTE,
  623. (WCD_RX2 << 0x10));
  624. wcd_enable_irq(&wcd937x->irq_info,
  625. WCD937X_IRQ_HPHR_PDM_WD_INT);
  626. break;
  627. case SND_SOC_DAPM_PRE_PMD:
  628. wcd_disable_irq(&wcd937x->irq_info,
  629. WCD937X_IRQ_HPHR_PDM_WD_INT);
  630. if (wcd937x->update_wcd_event)
  631. wcd937x->update_wcd_event(wcd937x->handle,
  632. WCD_BOLERO_EVT_RX_MUTE,
  633. (WCD_RX2 << 0x10 | 0x1));
  634. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  635. WCD_EVENT_PRE_HPHR_PA_OFF,
  636. &wcd937x->mbhc->wcd_mbhc);
  637. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  638. break;
  639. case SND_SOC_DAPM_POST_PMD:
  640. /*
  641. * 7ms sleep is required after PA is disabled as per
  642. * HW requirement. If compander is disabled, then
  643. * 20ms delay is required.
  644. */
  645. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  646. if (!wcd937x->comp2_enable)
  647. usleep_range(20000, 20100);
  648. else
  649. usleep_range(7000, 7100);
  650. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  651. }
  652. snd_soc_component_update_bits(component,
  653. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  654. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  655. WCD_EVENT_POST_HPHR_PA_OFF,
  656. &wcd937x->mbhc->wcd_mbhc);
  657. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  658. 0x10, 0x00);
  659. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  660. WCD_CLSH_EVENT_POST_PA,
  661. WCD_CLSH_STATE_HPHR,
  662. hph_mode);
  663. break;
  664. };
  665. return ret;
  666. }
  667. static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  668. struct snd_kcontrol *kcontrol,
  669. int event)
  670. {
  671. struct snd_soc_component *component =
  672. snd_soc_dapm_to_component(w->dapm);
  673. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  674. int ret = 0;
  675. int hph_mode = wcd937x->hph_mode;
  676. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  677. w->name, event);
  678. switch (event) {
  679. case SND_SOC_DAPM_PRE_PMU:
  680. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  681. wcd937x->rx_swr_dev->dev_num,
  682. true);
  683. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  684. WCD_CLSH_EVENT_PRE_DAC,
  685. WCD_CLSH_STATE_HPHL,
  686. hph_mode);
  687. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  688. 0x20, 0x20);
  689. usleep_range(100, 110);
  690. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  691. snd_soc_component_update_bits(component,
  692. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  693. break;
  694. case SND_SOC_DAPM_POST_PMU:
  695. /*
  696. * 7ms sleep is required after PA is enabled as per
  697. * HW requirement. If compander is disabled, then
  698. * 20ms delay is required.
  699. */
  700. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  701. if (!wcd937x->comp1_enable)
  702. usleep_range(20000, 20100);
  703. else
  704. usleep_range(7000, 7100);
  705. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  706. }
  707. snd_soc_component_update_bits(component,
  708. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  709. 0x02, 0x02);
  710. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  711. snd_soc_component_update_bits(component,
  712. WCD937X_ANA_RX_SUPPLIES,
  713. 0x02, 0x02);
  714. if (wcd937x->update_wcd_event)
  715. wcd937x->update_wcd_event(wcd937x->handle,
  716. WCD_BOLERO_EVT_RX_MUTE,
  717. (WCD_RX1 << 0x10));
  718. wcd_enable_irq(&wcd937x->irq_info,
  719. WCD937X_IRQ_HPHL_PDM_WD_INT);
  720. break;
  721. case SND_SOC_DAPM_PRE_PMD:
  722. wcd_disable_irq(&wcd937x->irq_info,
  723. WCD937X_IRQ_HPHL_PDM_WD_INT);
  724. if (wcd937x->update_wcd_event)
  725. wcd937x->update_wcd_event(wcd937x->handle,
  726. WCD_BOLERO_EVT_RX_MUTE,
  727. (WCD_RX1 << 0x10 | 0x1));
  728. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  729. WCD_EVENT_PRE_HPHL_PA_OFF,
  730. &wcd937x->mbhc->wcd_mbhc);
  731. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  732. break;
  733. case SND_SOC_DAPM_POST_PMD:
  734. /*
  735. * 7ms sleep is required after PA is disabled as per
  736. * HW requirement. If compander is disabled, then
  737. * 20ms delay is required.
  738. */
  739. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  740. if (!wcd937x->comp1_enable)
  741. usleep_range(20000, 20100);
  742. else
  743. usleep_range(7000, 7100);
  744. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  745. }
  746. snd_soc_component_update_bits(component,
  747. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  748. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  749. WCD_EVENT_POST_HPHL_PA_OFF,
  750. &wcd937x->mbhc->wcd_mbhc);
  751. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  752. 0x20, 0x00);
  753. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  754. WCD_CLSH_EVENT_POST_PA,
  755. WCD_CLSH_STATE_HPHL,
  756. hph_mode);
  757. break;
  758. };
  759. return ret;
  760. }
  761. static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  762. struct snd_kcontrol *kcontrol,
  763. int event)
  764. {
  765. struct snd_soc_component *component =
  766. snd_soc_dapm_to_component(w->dapm);
  767. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  768. int hph_mode = wcd937x->hph_mode;
  769. int ret = 0;
  770. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  771. w->name, event);
  772. switch (event) {
  773. case SND_SOC_DAPM_PRE_PMU:
  774. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  775. wcd937x->rx_swr_dev->dev_num,
  776. true);
  777. snd_soc_component_update_bits(component,
  778. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  779. break;
  780. case SND_SOC_DAPM_POST_PMU:
  781. usleep_range(1000, 1010);
  782. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  783. snd_soc_component_update_bits(component,
  784. WCD937X_ANA_RX_SUPPLIES,
  785. 0x02, 0x02);
  786. if (wcd937x->update_wcd_event)
  787. wcd937x->update_wcd_event(wcd937x->handle,
  788. WCD_BOLERO_EVT_RX_MUTE,
  789. (WCD_RX3 << 0x10));
  790. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  791. break;
  792. case SND_SOC_DAPM_PRE_PMD:
  793. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  794. if (wcd937x->update_wcd_event)
  795. wcd937x->update_wcd_event(wcd937x->handle,
  796. WCD_BOLERO_EVT_RX_MUTE,
  797. (WCD_RX3 << 0x10 | 0x1));
  798. break;
  799. case SND_SOC_DAPM_POST_PMD:
  800. /* Add delay as per hw requirement */
  801. usleep_range(2000, 2010);
  802. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  803. WCD_CLSH_EVENT_POST_PA,
  804. WCD_CLSH_STATE_AUX,
  805. hph_mode);
  806. snd_soc_component_update_bits(component,
  807. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  808. break;
  809. };
  810. return ret;
  811. }
  812. static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  813. struct snd_kcontrol *kcontrol,
  814. int event)
  815. {
  816. struct snd_soc_component *component =
  817. snd_soc_dapm_to_component(w->dapm);
  818. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  819. int hph_mode = wcd937x->hph_mode;
  820. int ret = 0;
  821. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  822. w->name, event);
  823. switch (event) {
  824. case SND_SOC_DAPM_PRE_PMU:
  825. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  826. wcd937x->rx_swr_dev->dev_num,
  827. true);
  828. /*
  829. * Enable watchdog interrupt for HPHL or AUX
  830. * depending on mux value
  831. */
  832. wcd937x->ear_rx_path =
  833. snd_soc_component_read32(
  834. component, WCD937X_DIGITAL_CDC_EAR_PATH_CTL);
  835. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  836. snd_soc_component_update_bits(component,
  837. WCD937X_DIGITAL_PDM_WD_CTL2,
  838. 0x05, 0x05);
  839. else
  840. snd_soc_component_update_bits(component,
  841. WCD937X_DIGITAL_PDM_WD_CTL0,
  842. 0x17, 0x13);
  843. if (!wcd937x->comp1_enable)
  844. snd_soc_component_update_bits(component,
  845. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  846. break;
  847. case SND_SOC_DAPM_POST_PMU:
  848. usleep_range(6000, 6010);
  849. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  850. snd_soc_component_update_bits(component,
  851. WCD937X_ANA_RX_SUPPLIES,
  852. 0x02, 0x02);
  853. if (wcd937x->update_wcd_event)
  854. wcd937x->update_wcd_event(wcd937x->handle,
  855. WCD_BOLERO_EVT_RX_MUTE,
  856. (WCD_RX1 << 0x10));
  857. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  858. wcd_enable_irq(&wcd937x->irq_info,
  859. WCD937X_IRQ_AUX_PDM_WD_INT);
  860. else
  861. wcd_enable_irq(&wcd937x->irq_info,
  862. WCD937X_IRQ_HPHL_PDM_WD_INT);
  863. break;
  864. case SND_SOC_DAPM_PRE_PMD:
  865. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  866. wcd_disable_irq(&wcd937x->irq_info,
  867. WCD937X_IRQ_AUX_PDM_WD_INT);
  868. else
  869. wcd_disable_irq(&wcd937x->irq_info,
  870. WCD937X_IRQ_HPHL_PDM_WD_INT);
  871. if (wcd937x->update_wcd_event)
  872. wcd937x->update_wcd_event(wcd937x->handle,
  873. WCD_BOLERO_EVT_RX_MUTE,
  874. (WCD_RX1 << 0x10 | 0x1));
  875. break;
  876. case SND_SOC_DAPM_POST_PMD:
  877. if (!wcd937x->comp1_enable)
  878. snd_soc_component_update_bits(component,
  879. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  880. usleep_range(7000, 7010);
  881. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  882. WCD_CLSH_EVENT_POST_PA,
  883. WCD_CLSH_STATE_EAR,
  884. hph_mode);
  885. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  886. 0x04, 0x04);
  887. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  888. snd_soc_component_update_bits(component,
  889. WCD937X_DIGITAL_PDM_WD_CTL2,
  890. 0x05, 0x00);
  891. else
  892. snd_soc_component_update_bits(component,
  893. WCD937X_DIGITAL_PDM_WD_CTL0,
  894. 0x17, 0x00);
  895. break;
  896. };
  897. return ret;
  898. }
  899. static int wcd937x_enable_clsh(struct snd_soc_dapm_widget *w,
  900. struct snd_kcontrol *kcontrol,
  901. int event)
  902. {
  903. struct snd_soc_component *component =
  904. snd_soc_dapm_to_component(w->dapm);
  905. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  906. int mode = wcd937x->hph_mode;
  907. int ret = 0;
  908. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  909. w->name, event);
  910. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  911. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  912. wcd937x_rx_connect_port(component, CLSH,
  913. SND_SOC_DAPM_EVENT_ON(event));
  914. }
  915. if (SND_SOC_DAPM_EVENT_OFF(event))
  916. ret = swr_slvdev_datapath_control(
  917. wcd937x->rx_swr_dev,
  918. wcd937x->rx_swr_dev->dev_num,
  919. false);
  920. return ret;
  921. }
  922. static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w,
  923. struct snd_kcontrol *kcontrol,
  924. int event)
  925. {
  926. struct snd_soc_component *component =
  927. snd_soc_dapm_to_component(w->dapm);
  928. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  929. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  930. w->name, event);
  931. switch (event) {
  932. case SND_SOC_DAPM_PRE_PMU:
  933. wcd937x_rx_connect_port(component, HPH_L, true);
  934. if (wcd937x->comp1_enable)
  935. wcd937x_rx_connect_port(component, COMP_L, true);
  936. break;
  937. case SND_SOC_DAPM_POST_PMD:
  938. wcd937x_rx_connect_port(component, HPH_L, false);
  939. if (wcd937x->comp1_enable)
  940. wcd937x_rx_connect_port(component, COMP_L, false);
  941. wcd937x_rx_clk_disable(component);
  942. snd_soc_component_update_bits(component,
  943. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  944. 0x01, 0x00);
  945. break;
  946. };
  947. return 0;
  948. }
  949. static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w,
  950. struct snd_kcontrol *kcontrol, int event)
  951. {
  952. struct snd_soc_component *component =
  953. snd_soc_dapm_to_component(w->dapm);
  954. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  955. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  956. w->name, event);
  957. switch (event) {
  958. case SND_SOC_DAPM_PRE_PMU:
  959. wcd937x_rx_connect_port(component, HPH_R, true);
  960. if (wcd937x->comp2_enable)
  961. wcd937x_rx_connect_port(component, COMP_R, true);
  962. break;
  963. case SND_SOC_DAPM_POST_PMD:
  964. wcd937x_rx_connect_port(component, HPH_R, false);
  965. if (wcd937x->comp2_enable)
  966. wcd937x_rx_connect_port(component, COMP_R, false);
  967. wcd937x_rx_clk_disable(component);
  968. snd_soc_component_update_bits(component,
  969. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  970. 0x02, 0x00);
  971. break;
  972. };
  973. return 0;
  974. }
  975. static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w,
  976. struct snd_kcontrol *kcontrol,
  977. int event)
  978. {
  979. struct snd_soc_component *component =
  980. snd_soc_dapm_to_component(w->dapm);
  981. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  982. w->name, event);
  983. switch (event) {
  984. case SND_SOC_DAPM_PRE_PMU:
  985. wcd937x_rx_connect_port(component, LO, true);
  986. break;
  987. case SND_SOC_DAPM_POST_PMD:
  988. wcd937x_rx_connect_port(component, LO, false);
  989. usleep_range(6000, 6010);
  990. wcd937x_rx_clk_disable(component);
  991. snd_soc_component_update_bits(component,
  992. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  993. break;
  994. }
  995. return 0;
  996. }
  997. static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  998. struct snd_kcontrol *kcontrol,
  999. int event)
  1000. {
  1001. struct snd_soc_component *component =
  1002. snd_soc_dapm_to_component(w->dapm);
  1003. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1004. u16 dmic_clk_reg;
  1005. s32 *dmic_clk_cnt;
  1006. unsigned int dmic;
  1007. char *wname;
  1008. int ret = 0;
  1009. wname = strpbrk(w->name, "012345");
  1010. if (!wname) {
  1011. dev_err(component->dev, "%s: widget not found\n", __func__);
  1012. return -EINVAL;
  1013. }
  1014. ret = kstrtouint(wname, 10, &dmic);
  1015. if (ret < 0) {
  1016. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  1017. __func__);
  1018. return -EINVAL;
  1019. }
  1020. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1021. w->name, event);
  1022. switch (dmic) {
  1023. case 0:
  1024. case 1:
  1025. dmic_clk_cnt = &(wcd937x->dmic_0_1_clk_cnt);
  1026. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL;
  1027. break;
  1028. case 2:
  1029. case 3:
  1030. dmic_clk_cnt = &(wcd937x->dmic_2_3_clk_cnt);
  1031. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL;
  1032. break;
  1033. case 4:
  1034. case 5:
  1035. dmic_clk_cnt = &(wcd937x->dmic_4_5_clk_cnt);
  1036. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL;
  1037. break;
  1038. default:
  1039. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1040. __func__);
  1041. return -EINVAL;
  1042. };
  1043. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1044. __func__, event, dmic, *dmic_clk_cnt);
  1045. switch (event) {
  1046. case SND_SOC_DAPM_PRE_PMU:
  1047. snd_soc_component_update_bits(component,
  1048. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1049. snd_soc_component_update_bits(component,
  1050. dmic_clk_reg, 0x07, 0x02);
  1051. snd_soc_component_update_bits(component,
  1052. dmic_clk_reg, 0x08, 0x08);
  1053. snd_soc_component_update_bits(component,
  1054. dmic_clk_reg, 0x70, 0x20);
  1055. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1056. break;
  1057. case SND_SOC_DAPM_POST_PMD:
  1058. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1059. break;
  1060. };
  1061. return 0;
  1062. }
  1063. /*
  1064. * wcd937x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1065. * @micb_mv: micbias in mv
  1066. *
  1067. * return register value converted
  1068. */
  1069. int wcd937x_get_micb_vout_ctl_val(u32 micb_mv)
  1070. {
  1071. /* min micbias voltage is 1V and maximum is 2.85V */
  1072. if (micb_mv < 1000 || micb_mv > 2850) {
  1073. pr_err("%s: unsupported micbias voltage\n", __func__);
  1074. return -EINVAL;
  1075. }
  1076. return (micb_mv - 1000) / 50;
  1077. }
  1078. EXPORT_SYMBOL(wcd937x_get_micb_vout_ctl_val);
  1079. /*
  1080. * wcd937x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1081. * @component: handle to snd_soc_component *
  1082. * @req_volt: micbias voltage to be set
  1083. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1084. *
  1085. * return 0 if adjustment is success or error code in case of failure
  1086. */
  1087. int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1088. int req_volt, int micb_num)
  1089. {
  1090. struct wcd937x_priv *wcd937x =
  1091. snd_soc_component_get_drvdata(component);
  1092. int cur_vout_ctl, req_vout_ctl;
  1093. int micb_reg, micb_val, micb_en;
  1094. int ret = 0;
  1095. switch (micb_num) {
  1096. case MIC_BIAS_1:
  1097. micb_reg = WCD937X_ANA_MICB1;
  1098. break;
  1099. case MIC_BIAS_2:
  1100. micb_reg = WCD937X_ANA_MICB2;
  1101. break;
  1102. case MIC_BIAS_3:
  1103. micb_reg = WCD937X_ANA_MICB3;
  1104. break;
  1105. default:
  1106. return -EINVAL;
  1107. }
  1108. mutex_lock(&wcd937x->micb_lock);
  1109. /*
  1110. * If requested micbias voltage is same as current micbias
  1111. * voltage, then just return. Otherwise, adjust voltage as
  1112. * per requested value. If micbias is already enabled, then
  1113. * to avoid slow micbias ramp-up or down enable pull-up
  1114. * momentarily, change the micbias value and then re-enable
  1115. * micbias.
  1116. */
  1117. micb_val = snd_soc_component_read32(component, micb_reg);
  1118. micb_en = (micb_val & 0xC0) >> 6;
  1119. cur_vout_ctl = micb_val & 0x3F;
  1120. req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt);
  1121. if (req_vout_ctl < 0) {
  1122. ret = -EINVAL;
  1123. goto exit;
  1124. }
  1125. if (cur_vout_ctl == req_vout_ctl) {
  1126. ret = 0;
  1127. goto exit;
  1128. }
  1129. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1130. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1131. req_volt, micb_en);
  1132. if (micb_en == 0x1)
  1133. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1134. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1135. if (micb_en == 0x1) {
  1136. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1137. /*
  1138. * Add 2ms delay as per HW requirement after enabling
  1139. * micbias
  1140. */
  1141. usleep_range(2000, 2100);
  1142. }
  1143. exit:
  1144. mutex_unlock(&wcd937x->micb_lock);
  1145. return ret;
  1146. }
  1147. EXPORT_SYMBOL(wcd937x_mbhc_micb_adjust_voltage);
  1148. static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1149. struct snd_kcontrol *kcontrol,
  1150. int event)
  1151. {
  1152. struct snd_soc_component *component =
  1153. snd_soc_dapm_to_component(w->dapm);
  1154. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1155. int ret = 0;
  1156. switch (event) {
  1157. case SND_SOC_DAPM_PRE_PMU:
  1158. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1159. wcd937x->tx_swr_dev->dev_num,
  1160. true);
  1161. break;
  1162. case SND_SOC_DAPM_POST_PMD:
  1163. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1164. wcd937x->tx_swr_dev->dev_num,
  1165. false);
  1166. break;
  1167. };
  1168. return ret;
  1169. }
  1170. static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1171. struct snd_kcontrol *kcontrol,
  1172. int event){
  1173. struct snd_soc_component *component =
  1174. snd_soc_dapm_to_component(w->dapm);
  1175. struct wcd937x_priv *wcd937x =
  1176. snd_soc_component_get_drvdata(component);
  1177. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1178. w->name, event);
  1179. switch (event) {
  1180. case SND_SOC_DAPM_PRE_PMU:
  1181. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1182. wcd937x->ana_clk_count++;
  1183. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1184. snd_soc_component_update_bits(component,
  1185. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1186. snd_soc_component_update_bits(component,
  1187. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1188. snd_soc_component_update_bits(component,
  1189. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1190. /* Enable BCS for Headset mic */
  1191. if (w->shift == 1 && !(snd_soc_component_read32(component,
  1192. WCD937X_TX_NEW_TX_CH2_SEL) & 0x80)) {
  1193. wcd937x_tx_connect_port(codec, MBHC, true);
  1194. set_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1195. }
  1196. wcd937x_tx_connect_port(component, ADC1 + (w->shift), true);
  1197. break;
  1198. case SND_SOC_DAPM_POST_PMD:
  1199. wcd937x_tx_connect_port(component, ADC1 + (w->shift), false);
  1200. if (w->shift == 1 &&
  1201. test_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask)) {
  1202. wcd937x_tx_connect_port(codec, MBHC, false);
  1203. clear_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1204. }
  1205. snd_soc_component_update_bits(component,
  1206. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1207. break;
  1208. };
  1209. return 0;
  1210. }
  1211. static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
  1212. struct snd_kcontrol *kcontrol, int event)
  1213. {
  1214. struct snd_soc_component *component =
  1215. snd_soc_dapm_to_component(w->dapm);
  1216. struct wcd937x_priv *wcd937x =
  1217. snd_soc_component_get_drvdata(component);
  1218. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1219. w->name, event);
  1220. switch (event) {
  1221. case SND_SOC_DAPM_PRE_PMU:
  1222. snd_soc_component_update_bits(component,
  1223. WCD937X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1224. snd_soc_component_update_bits(component,
  1225. WCD937X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1226. snd_soc_component_update_bits(component,
  1227. WCD937X_ANA_TX_CH2, 0x40, 0x40);
  1228. snd_soc_component_update_bits(component,
  1229. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x30, 0x30);
  1230. snd_soc_component_update_bits(component,
  1231. WCD937X_ANA_TX_CH1, 0x80, 0x80);
  1232. snd_soc_component_update_bits(component,
  1233. WCD937X_ANA_TX_CH2, 0x40, 0x00);
  1234. snd_soc_component_update_bits(component,
  1235. WCD937X_ANA_TX_CH2, 0x80, 0x80);
  1236. break;
  1237. case SND_SOC_DAPM_POST_PMD:
  1238. snd_soc_component_update_bits(component,
  1239. WCD937X_ANA_TX_CH1, 0x80, 0x00);
  1240. snd_soc_component_update_bits(component,
  1241. WCD937X_ANA_TX_CH2, 0x80, 0x00);
  1242. snd_soc_component_update_bits(component,
  1243. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1244. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1245. wcd937x->ana_clk_count--;
  1246. if (wcd937x->ana_clk_count <= 0) {
  1247. snd_soc_component_update_bits(component,
  1248. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1249. wcd937x->ana_clk_count = 0;
  1250. }
  1251. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1252. snd_soc_component_update_bits(component,
  1253. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1254. break;
  1255. };
  1256. return 0;
  1257. }
  1258. int wcd937x_micbias_control(struct snd_soc_component *component,
  1259. int micb_num, int req, bool is_dapm)
  1260. {
  1261. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1262. int micb_index = micb_num - 1;
  1263. u16 micb_reg;
  1264. int pre_off_event = 0, post_off_event = 0;
  1265. int post_on_event = 0, post_dapm_off = 0;
  1266. int post_dapm_on = 0;
  1267. if ((micb_index < 0) || (micb_index > WCD937X_MAX_MICBIAS - 1)) {
  1268. dev_err(component->dev, "%s: Invalid micbias index, micb_ind:%d\n",
  1269. __func__, micb_index);
  1270. return -EINVAL;
  1271. }
  1272. switch (micb_num) {
  1273. case MIC_BIAS_1:
  1274. micb_reg = WCD937X_ANA_MICB1;
  1275. break;
  1276. case MIC_BIAS_2:
  1277. micb_reg = WCD937X_ANA_MICB2;
  1278. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1279. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1280. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1281. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1282. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1283. break;
  1284. case MIC_BIAS_3:
  1285. micb_reg = WCD937X_ANA_MICB3;
  1286. break;
  1287. default:
  1288. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1289. __func__, micb_num);
  1290. return -EINVAL;
  1291. };
  1292. mutex_lock(&wcd937x->micb_lock);
  1293. switch (req) {
  1294. case MICB_PULLUP_ENABLE:
  1295. wcd937x->pullup_ref[micb_index]++;
  1296. if ((wcd937x->pullup_ref[micb_index] == 1) &&
  1297. (wcd937x->micb_ref[micb_index] == 0))
  1298. snd_soc_component_update_bits(component, micb_reg,
  1299. 0xC0, 0x80);
  1300. break;
  1301. case MICB_PULLUP_DISABLE:
  1302. if (wcd937x->pullup_ref[micb_index] > 0)
  1303. wcd937x->pullup_ref[micb_index]--;
  1304. if ((wcd937x->pullup_ref[micb_index] == 0) &&
  1305. (wcd937x->micb_ref[micb_index] == 0))
  1306. snd_soc_component_update_bits(component, micb_reg,
  1307. 0xC0, 0x00);
  1308. break;
  1309. case MICB_ENABLE:
  1310. wcd937x->micb_ref[micb_index]++;
  1311. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1312. wcd937x->ana_clk_count++;
  1313. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1314. if (wcd937x->micb_ref[micb_index] == 1) {
  1315. snd_soc_component_update_bits(component,
  1316. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1317. snd_soc_component_update_bits(component,
  1318. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1319. snd_soc_component_update_bits(component,
  1320. WCD937X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1321. snd_soc_component_update_bits(component,
  1322. WCD937X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1323. snd_soc_component_update_bits(component,
  1324. WCD937X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1325. snd_soc_component_update_bits(component,
  1326. micb_reg, 0xC0, 0x40);
  1327. if (post_on_event)
  1328. blocking_notifier_call_chain(
  1329. &wcd937x->mbhc->notifier, post_on_event,
  1330. &wcd937x->mbhc->wcd_mbhc);
  1331. }
  1332. if (is_dapm && post_dapm_on && wcd937x->mbhc)
  1333. blocking_notifier_call_chain(
  1334. &wcd937x->mbhc->notifier, post_dapm_on,
  1335. &wcd937x->mbhc->wcd_mbhc);
  1336. break;
  1337. case MICB_DISABLE:
  1338. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1339. wcd937x->ana_clk_count--;
  1340. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1341. if (wcd937x->micb_ref[micb_index] > 0)
  1342. wcd937x->micb_ref[micb_index]--;
  1343. if ((wcd937x->micb_ref[micb_index] == 0) &&
  1344. (wcd937x->pullup_ref[micb_index] > 0))
  1345. snd_soc_component_update_bits(component, micb_reg,
  1346. 0xC0, 0x80);
  1347. else if ((wcd937x->micb_ref[micb_index] == 0) &&
  1348. (wcd937x->pullup_ref[micb_index] == 0)) {
  1349. if (pre_off_event && wcd937x->mbhc)
  1350. blocking_notifier_call_chain(
  1351. &wcd937x->mbhc->notifier, pre_off_event,
  1352. &wcd937x->mbhc->wcd_mbhc);
  1353. snd_soc_component_update_bits(component, micb_reg,
  1354. 0xC0, 0x00);
  1355. if (post_off_event && wcd937x->mbhc)
  1356. blocking_notifier_call_chain(
  1357. &wcd937x->mbhc->notifier,
  1358. post_off_event,
  1359. &wcd937x->mbhc->wcd_mbhc);
  1360. }
  1361. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1362. if (wcd937x->ana_clk_count <= 0) {
  1363. snd_soc_component_update_bits(component,
  1364. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  1365. 0x10, 0x00);
  1366. wcd937x->ana_clk_count = 0;
  1367. }
  1368. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1369. if (is_dapm && post_dapm_off && wcd937x->mbhc)
  1370. blocking_notifier_call_chain(
  1371. &wcd937x->mbhc->notifier, post_dapm_off,
  1372. &wcd937x->mbhc->wcd_mbhc);
  1373. break;
  1374. };
  1375. dev_dbg(component->dev, "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1376. __func__, micb_num, wcd937x->micb_ref[micb_index],
  1377. wcd937x->pullup_ref[micb_index]);
  1378. mutex_unlock(&wcd937x->micb_lock);
  1379. return 0;
  1380. }
  1381. EXPORT_SYMBOL(wcd937x_micbias_control);
  1382. static int wcd937x_get_logical_addr(struct swr_device *swr_dev)
  1383. {
  1384. int ret = 0;
  1385. uint8_t devnum = 0;
  1386. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1387. if (ret) {
  1388. dev_err(&swr_dev->dev,
  1389. "%s get devnum %d for dev addr %lx failed\n",
  1390. __func__, devnum, swr_dev->addr);
  1391. return ret;
  1392. }
  1393. swr_dev->dev_num = devnum;
  1394. return 0;
  1395. }
  1396. static int wcd937x_event_notify(struct notifier_block *block,
  1397. unsigned long val,
  1398. void *data)
  1399. {
  1400. u16 event = (val & 0xffff);
  1401. u16 amic = (val >> 0x10);
  1402. u16 mask = 0x40, reg = 0x0;
  1403. int ret = 0;
  1404. struct wcd937x_priv *wcd937x = dev_get_drvdata((struct device *)data);
  1405. struct snd_soc_component *component = wcd937x->component;
  1406. struct wcd_mbhc *mbhc;
  1407. switch (event) {
  1408. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1409. if (amic == 0x1 || amic == 0x2)
  1410. reg = WCD937X_ANA_TX_CH2;
  1411. else if (amic == 0x3)
  1412. reg = WCD937X_ANA_TX_CH3_HPF;
  1413. else
  1414. return 0;
  1415. if (amic == 0x2)
  1416. mask = 0x20;
  1417. snd_soc_component_update_bits(component, reg, mask, 0x00);
  1418. break;
  1419. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1420. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  1421. 0xC0, 0x00);
  1422. snd_soc_component_update_bits(component, WCD937X_ANA_EAR,
  1423. 0x80, 0x00);
  1424. snd_soc_component_update_bits(component, WCD937X_AUX_AUXPA,
  1425. 0x80, 0x00);
  1426. break;
  1427. case BOLERO_WCD_EVT_SSR_DOWN:
  1428. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1429. wcd937x_mbhc_ssr_down(wcd937x->mbhc, component);
  1430. wcd937x_reset_low(wcd937x->dev);
  1431. break;
  1432. case BOLERO_WCD_EVT_SSR_UP:
  1433. wcd937x_reset(wcd937x->dev);
  1434. wcd937x_get_logical_addr(wcd937x->tx_swr_dev);
  1435. wcd937x_get_logical_addr(wcd937x->rx_swr_dev);
  1436. regcache_mark_dirty(wcd937x->regmap);
  1437. regcache_sync(wcd937x->regmap);
  1438. /* Enable surge protection */
  1439. snd_soc_component_update_bits(component,
  1440. WCD937X_HPH_SURGE_HPHLR_SURGE_EN,
  1441. 0xFF, 0xD9);
  1442. /* Initialize MBHC module */
  1443. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1444. ret = wcd937x_mbhc_post_ssr_init(wcd937x->mbhc, component);
  1445. if (ret) {
  1446. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1447. __func__);
  1448. } else {
  1449. wcd937x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1450. }
  1451. break;
  1452. default:
  1453. dev_err(component->dev, "%s: invalid event %d\n", __func__,
  1454. event);
  1455. break;
  1456. }
  1457. return 0;
  1458. }
  1459. static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1460. int event)
  1461. {
  1462. struct snd_soc_component *component =
  1463. snd_soc_dapm_to_component(w->dapm);
  1464. int micb_num;
  1465. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1466. __func__, w->name, event);
  1467. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1468. micb_num = MIC_BIAS_1;
  1469. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1470. micb_num = MIC_BIAS_2;
  1471. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1472. micb_num = MIC_BIAS_3;
  1473. else
  1474. return -EINVAL;
  1475. switch (event) {
  1476. case SND_SOC_DAPM_PRE_PMU:
  1477. wcd937x_micbias_control(component, micb_num,
  1478. MICB_ENABLE, true);
  1479. break;
  1480. case SND_SOC_DAPM_POST_PMU:
  1481. usleep_range(1000, 1100);
  1482. break;
  1483. case SND_SOC_DAPM_POST_PMD:
  1484. wcd937x_micbias_control(component, micb_num,
  1485. MICB_DISABLE, true);
  1486. break;
  1487. };
  1488. return 0;
  1489. }
  1490. static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1491. struct snd_kcontrol *kcontrol,
  1492. int event)
  1493. {
  1494. return __wcd937x_codec_enable_micbias(w, event);
  1495. }
  1496. static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1497. struct snd_ctl_elem_value *ucontrol)
  1498. {
  1499. struct snd_soc_component *component =
  1500. snd_soc_kcontrol_component(kcontrol);
  1501. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1502. ucontrol->value.integer.value[0] = wcd937x->hph_mode;
  1503. return 0;
  1504. }
  1505. static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1506. struct snd_ctl_elem_value *ucontrol)
  1507. {
  1508. struct snd_soc_component *component =
  1509. snd_soc_kcontrol_component(kcontrol);
  1510. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1511. u32 mode_val;
  1512. mode_val = ucontrol->value.enumerated.item[0];
  1513. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1514. if (mode_val == 0) {
  1515. dev_warn(component->dev, "%s:Invalid HPH Mode, default to class_AB\n",
  1516. __func__);
  1517. mode_val = 3; /* enum will be updated later */
  1518. }
  1519. wcd937x->hph_mode = mode_val;
  1520. return 0;
  1521. }
  1522. static int wcd937x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  1523. struct snd_ctl_elem_value *ucontrol)
  1524. {
  1525. u8 ear_pa_gain = 0;
  1526. struct snd_soc_component *component =
  1527. snd_soc_kcontrol_component(kcontrol);
  1528. ear_pa_gain = snd_soc_component_read32(component,
  1529. WCD937X_ANA_EAR_COMPANDER_CTL);
  1530. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  1531. ucontrol->value.integer.value[0] = ear_pa_gain;
  1532. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  1533. ear_pa_gain);
  1534. return 0;
  1535. }
  1536. static int wcd937x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  1537. struct snd_ctl_elem_value *ucontrol)
  1538. {
  1539. u8 ear_pa_gain = 0;
  1540. struct snd_soc_component *component =
  1541. snd_soc_kcontrol_component(kcontrol);
  1542. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1543. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1544. __func__, ucontrol->value.integer.value[0]);
  1545. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  1546. if (!wcd937x->comp1_enable) {
  1547. snd_soc_component_update_bits(component,
  1548. WCD937X_ANA_EAR_COMPANDER_CTL,
  1549. 0x7C, ear_pa_gain);
  1550. }
  1551. return 0;
  1552. }
  1553. static int wcd937x_get_compander(struct snd_kcontrol *kcontrol,
  1554. struct snd_ctl_elem_value *ucontrol)
  1555. {
  1556. struct snd_soc_component *component =
  1557. snd_soc_kcontrol_component(kcontrol);
  1558. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1559. bool hphr;
  1560. struct soc_multi_mixer_control *mc;
  1561. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1562. hphr = mc->shift;
  1563. ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable :
  1564. wcd937x->comp1_enable;
  1565. return 0;
  1566. }
  1567. static int wcd937x_set_compander(struct snd_kcontrol *kcontrol,
  1568. struct snd_ctl_elem_value *ucontrol)
  1569. {
  1570. struct snd_soc_component *component =
  1571. snd_soc_kcontrol_component(kcontrol);
  1572. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1573. int value = ucontrol->value.integer.value[0];
  1574. bool hphr;
  1575. struct soc_multi_mixer_control *mc;
  1576. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1577. hphr = mc->shift;
  1578. if (hphr)
  1579. wcd937x->comp2_enable = value;
  1580. else
  1581. wcd937x->comp1_enable = value;
  1582. return 0;
  1583. }
  1584. static int wcd937x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  1585. struct snd_kcontrol *kcontrol,
  1586. int event)
  1587. {
  1588. struct snd_soc_component *component =
  1589. snd_soc_dapm_to_component(w->dapm);
  1590. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1591. struct wcd937x_pdata *pdata = NULL;
  1592. int ret = 0;
  1593. pdata = dev_get_platdata(wcd937x->dev);
  1594. if (!pdata) {
  1595. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  1596. return -EINVAL;
  1597. }
  1598. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1599. w->name, event);
  1600. switch (event) {
  1601. case SND_SOC_DAPM_PRE_PMU:
  1602. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  1603. dev_dbg(component->dev,
  1604. "%s: buck already in enabled state\n",
  1605. __func__);
  1606. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1607. return 0;
  1608. }
  1609. ret = msm_cdc_enable_ondemand_supply(wcd937x->dev,
  1610. wcd937x->supplies,
  1611. pdata->regulator,
  1612. pdata->num_supplies,
  1613. "cdc-vdd-buck");
  1614. if (ret == -EINVAL) {
  1615. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  1616. __func__);
  1617. return ret;
  1618. }
  1619. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1620. /*
  1621. * 200us sleep is required after LDO15 is enabled as per
  1622. * HW requirement
  1623. */
  1624. usleep_range(200, 250);
  1625. break;
  1626. case SND_SOC_DAPM_POST_PMD:
  1627. set_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1628. break;
  1629. }
  1630. return 0;
  1631. }
  1632. static const char * const rx_hph_mode_mux_text[] = {
  1633. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1634. "CLS_H_ULP", "CLS_AB_HIFI",
  1635. };
  1636. static const char * const wcd937x_ear_pa_gain_text[] = {
  1637. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  1638. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  1639. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  1640. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  1641. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  1642. };
  1643. static const struct soc_enum rx_hph_mode_mux_enum =
  1644. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1645. rx_hph_mode_mux_text);
  1646. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_ear_pa_gain_enum,
  1647. wcd937x_ear_pa_gain_text);
  1648. static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
  1649. SOC_ENUM_EXT("EAR PA GAIN", wcd937x_ear_pa_gain_enum,
  1650. wcd937x_ear_pa_gain_get, wcd937x_ear_pa_gain_put),
  1651. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1652. wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put),
  1653. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1654. wcd937x_get_compander, wcd937x_set_compander),
  1655. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1656. wcd937x_get_compander, wcd937x_set_compander),
  1657. SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain),
  1658. SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain),
  1659. SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0,
  1660. analog_gain),
  1661. SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0,
  1662. analog_gain),
  1663. SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0,
  1664. analog_gain),
  1665. };
  1666. static const struct snd_kcontrol_new adc1_switch[] = {
  1667. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1668. };
  1669. static const struct snd_kcontrol_new adc2_switch[] = {
  1670. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1671. };
  1672. static const struct snd_kcontrol_new adc3_switch[] = {
  1673. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1674. };
  1675. static const struct snd_kcontrol_new dmic1_switch[] = {
  1676. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1677. };
  1678. static const struct snd_kcontrol_new dmic2_switch[] = {
  1679. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1680. };
  1681. static const struct snd_kcontrol_new dmic3_switch[] = {
  1682. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1683. };
  1684. static const struct snd_kcontrol_new dmic4_switch[] = {
  1685. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1686. };
  1687. static const struct snd_kcontrol_new dmic5_switch[] = {
  1688. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1689. };
  1690. static const struct snd_kcontrol_new dmic6_switch[] = {
  1691. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1692. };
  1693. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  1694. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1695. };
  1696. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  1697. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1698. };
  1699. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  1700. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1701. };
  1702. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  1703. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1704. };
  1705. static const char * const adc2_mux_text[] = {
  1706. "INP2", "INP3"
  1707. };
  1708. static const char * const rdac3_mux_text[] = {
  1709. "RX1", "RX3"
  1710. };
  1711. static const struct soc_enum adc2_enum =
  1712. SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7,
  1713. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  1714. static const struct soc_enum rdac3_enum =
  1715. SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  1716. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  1717. static const struct snd_kcontrol_new tx_adc2_mux =
  1718. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  1719. static const struct snd_kcontrol_new rx_rdac3_mux =
  1720. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  1721. static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = {
  1722. /*input widgets*/
  1723. SND_SOC_DAPM_INPUT("AMIC1"),
  1724. SND_SOC_DAPM_INPUT("AMIC2"),
  1725. SND_SOC_DAPM_INPUT("AMIC3"),
  1726. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  1727. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  1728. SND_SOC_DAPM_INPUT("IN3_AUX"),
  1729. /*tx widgets*/
  1730. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  1731. wcd937x_codec_enable_adc,
  1732. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1733. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  1734. wcd937x_codec_enable_adc,
  1735. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1736. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  1737. NULL, 0, wcd937x_enable_req,
  1738. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1739. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
  1740. NULL, 0, wcd937x_enable_req,
  1741. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1742. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  1743. &tx_adc2_mux),
  1744. /*tx mixers*/
  1745. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  1746. adc1_switch, ARRAY_SIZE(adc1_switch),
  1747. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1748. SND_SOC_DAPM_POST_PMD),
  1749. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  1750. adc2_switch, ARRAY_SIZE(adc2_switch),
  1751. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1752. SND_SOC_DAPM_POST_PMD),
  1753. /* micbias widgets*/
  1754. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  1755. wcd937x_codec_enable_micbias,
  1756. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1757. SND_SOC_DAPM_POST_PMD),
  1758. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  1759. wcd937x_codec_enable_micbias,
  1760. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1761. SND_SOC_DAPM_POST_PMD),
  1762. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  1763. wcd937x_codec_enable_micbias,
  1764. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1765. SND_SOC_DAPM_POST_PMD),
  1766. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  1767. wcd937x_codec_enable_vdd_buck,
  1768. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1769. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  1770. wcd937x_enable_clsh,
  1771. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1772. /*rx widgets*/
  1773. SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0,
  1774. wcd937x_codec_enable_ear_pa,
  1775. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1776. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1777. SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0,
  1778. wcd937x_codec_enable_aux_pa,
  1779. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1780. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1781. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0,
  1782. wcd937x_codec_enable_hphl_pa,
  1783. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1784. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1785. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0,
  1786. wcd937x_codec_enable_hphr_pa,
  1787. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1788. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1789. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  1790. wcd937x_codec_hphl_dac_event,
  1791. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1792. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1793. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  1794. wcd937x_codec_hphr_dac_event,
  1795. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1796. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1797. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  1798. wcd937x_codec_ear_dac_event,
  1799. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1800. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1801. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  1802. wcd937x_codec_aux_dac_event,
  1803. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1804. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1805. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  1806. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  1807. wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  1808. SND_SOC_DAPM_POST_PMD),
  1809. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  1810. wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  1811. SND_SOC_DAPM_POST_PMD),
  1812. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  1813. wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  1814. SND_SOC_DAPM_POST_PMD),
  1815. /* rx mixer widgets*/
  1816. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  1817. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  1818. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  1819. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  1820. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  1821. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  1822. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  1823. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  1824. /*output widgets tx*/
  1825. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  1826. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  1827. /*output widgets rx*/
  1828. SND_SOC_DAPM_OUTPUT("EAR"),
  1829. SND_SOC_DAPM_OUTPUT("AUX"),
  1830. SND_SOC_DAPM_OUTPUT("HPHL"),
  1831. SND_SOC_DAPM_OUTPUT("HPHR"),
  1832. };
  1833. static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = {
  1834. /*input widgets*/
  1835. SND_SOC_DAPM_INPUT("AMIC4"),
  1836. /*tx widgets*/
  1837. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  1838. wcd937x_codec_enable_adc,
  1839. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1840. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
  1841. NULL, 0, wcd937x_enable_req,
  1842. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1843. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  1844. wcd937x_codec_enable_dmic,
  1845. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1846. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  1847. wcd937x_codec_enable_dmic,
  1848. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1849. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  1850. wcd937x_codec_enable_dmic,
  1851. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1852. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  1853. wcd937x_codec_enable_dmic,
  1854. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1855. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  1856. wcd937x_codec_enable_dmic,
  1857. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1858. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  1859. wcd937x_codec_enable_dmic,
  1860. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1861. /*tx mixer widgets*/
  1862. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  1863. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  1864. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1865. SND_SOC_DAPM_POST_PMD),
  1866. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  1867. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  1868. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1869. SND_SOC_DAPM_POST_PMD),
  1870. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  1871. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  1872. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1873. SND_SOC_DAPM_POST_PMD),
  1874. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  1875. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  1876. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1877. SND_SOC_DAPM_POST_PMD),
  1878. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  1879. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  1880. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1881. SND_SOC_DAPM_POST_PMD),
  1882. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  1883. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  1884. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1885. SND_SOC_DAPM_POST_PMD),
  1886. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  1887. ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl,
  1888. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1889. /*output widgets*/
  1890. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  1891. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  1892. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  1893. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  1894. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  1895. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  1896. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  1897. };
  1898. static const struct snd_soc_dapm_route wcd937x_audio_map[] = {
  1899. {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
  1900. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  1901. {"ADC1 REQ", NULL, "ADC1"},
  1902. {"ADC1", NULL, "AMIC1"},
  1903. {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
  1904. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  1905. {"ADC2 REQ", NULL, "ADC2"},
  1906. {"ADC2", NULL, "ADC2 MUX"},
  1907. {"ADC2 MUX", "INP3", "AMIC3"},
  1908. {"ADC2 MUX", "INP2", "AMIC2"},
  1909. {"IN1_HPHL", NULL, "VDD_BUCK"},
  1910. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  1911. {"RX1", NULL, "IN1_HPHL"},
  1912. {"RDAC1", NULL, "RX1"},
  1913. {"HPHL_RDAC", "Switch", "RDAC1"},
  1914. {"HPHL PGA", NULL, "HPHL_RDAC"},
  1915. {"HPHL", NULL, "HPHL PGA"},
  1916. {"IN2_HPHR", NULL, "VDD_BUCK"},
  1917. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  1918. {"RX2", NULL, "IN2_HPHR"},
  1919. {"RDAC2", NULL, "RX2"},
  1920. {"HPHR_RDAC", "Switch", "RDAC2"},
  1921. {"HPHR PGA", NULL, "HPHR_RDAC"},
  1922. {"HPHR", NULL, "HPHR PGA"},
  1923. {"IN3_AUX", NULL, "VDD_BUCK"},
  1924. {"IN3_AUX", NULL, "CLS_H_PORT"},
  1925. {"RX3", NULL, "IN3_AUX"},
  1926. {"RDAC4", NULL, "RX3"},
  1927. {"AUX_RDAC", "Switch", "RDAC4"},
  1928. {"AUX PGA", NULL, "AUX_RDAC"},
  1929. {"AUX", NULL, "AUX PGA"},
  1930. {"RDAC3_MUX", "RX3", "RX3"},
  1931. {"RDAC3_MUX", "RX1", "RX1"},
  1932. {"RDAC3", NULL, "RDAC3_MUX"},
  1933. {"EAR_RDAC", "Switch", "RDAC3"},
  1934. {"EAR PGA", NULL, "EAR_RDAC"},
  1935. {"EAR", NULL, "EAR PGA"},
  1936. };
  1937. static const struct snd_soc_dapm_route wcd9375_audio_map[] = {
  1938. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  1939. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  1940. {"ADC3 REQ", NULL, "ADC3"},
  1941. {"ADC3", NULL, "AMIC4"},
  1942. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  1943. {"DMIC1_MIXER", "Switch", "DMIC1"},
  1944. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  1945. {"DMIC2_MIXER", "Switch", "DMIC2"},
  1946. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  1947. {"DMIC3_MIXER", "Switch", "DMIC3"},
  1948. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  1949. {"DMIC4_MIXER", "Switch", "DMIC4"},
  1950. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  1951. {"DMIC5_MIXER", "Switch", "DMIC5"},
  1952. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  1953. {"DMIC6_MIXER", "Switch", "DMIC6"},
  1954. };
  1955. static ssize_t wcd937x_version_read(struct snd_info_entry *entry,
  1956. void *file_private_data,
  1957. struct file *file,
  1958. char __user *buf, size_t count,
  1959. loff_t pos)
  1960. {
  1961. struct wcd937x_priv *priv;
  1962. char buffer[WCD937X_VERSION_ENTRY_SIZE];
  1963. int len = 0;
  1964. priv = (struct wcd937x_priv *) entry->private_data;
  1965. if (!priv) {
  1966. pr_err("%s: wcd937x priv is null\n", __func__);
  1967. return -EINVAL;
  1968. }
  1969. switch (priv->version) {
  1970. case WCD937X_VERSION_1_0:
  1971. len = snprintf(buffer, sizeof(buffer), "WCD937X_1_0\n");
  1972. break;
  1973. default:
  1974. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  1975. }
  1976. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  1977. }
  1978. static struct snd_info_entry_ops wcd937x_info_ops = {
  1979. .read = wcd937x_version_read,
  1980. };
  1981. static ssize_t wcd937x_variant_read(struct snd_info_entry *entry,
  1982. void *file_private_data,
  1983. struct file *file,
  1984. char __user *buf, size_t count,
  1985. loff_t pos)
  1986. {
  1987. struct wcd937x_priv *priv;
  1988. char buffer[WCD937X_VARIANT_ENTRY_SIZE];
  1989. int len = 0;
  1990. priv = (struct wcd937x_priv *) entry->private_data;
  1991. if (!priv) {
  1992. pr_err("%s: wcd937x priv is null\n", __func__);
  1993. return -EINVAL;
  1994. }
  1995. switch (priv->variant) {
  1996. case WCD9370_VARIANT:
  1997. len = snprintf(buffer, sizeof(buffer), "WCD9370\n");
  1998. break;
  1999. case WCD9375_VARIANT:
  2000. len = snprintf(buffer, sizeof(buffer), "WCD9375\n");
  2001. break;
  2002. default:
  2003. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2004. }
  2005. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2006. }
  2007. static struct snd_info_entry_ops wcd937x_variant_ops = {
  2008. .read = wcd937x_variant_read,
  2009. };
  2010. /*
  2011. * wcd937x_info_create_codec_entry - creates wcd937x module
  2012. * @codec_root: The parent directory
  2013. * @component: component instance
  2014. *
  2015. * Creates wcd937x module, variant and version entry under the given
  2016. * parent directory.
  2017. *
  2018. * Return: 0 on success or negative error code on failure.
  2019. */
  2020. int wcd937x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2021. struct snd_soc_component *component)
  2022. {
  2023. struct snd_info_entry *version_entry;
  2024. struct snd_info_entry *variant_entry;
  2025. struct wcd937x_priv *priv;
  2026. struct snd_soc_card *card;
  2027. if (!codec_root || !component)
  2028. return -EINVAL;
  2029. priv = snd_soc_component_get_drvdata(component);
  2030. if (priv->entry) {
  2031. dev_dbg(priv->dev,
  2032. "%s:wcd937x module already created\n", __func__);
  2033. return 0;
  2034. }
  2035. card = component->card;
  2036. priv->entry = snd_info_create_subdir(codec_root->module,
  2037. "wcd937x", codec_root);
  2038. if (!priv->entry) {
  2039. dev_dbg(component->dev, "%s: failed to create wcd937x entry\n",
  2040. __func__);
  2041. return -ENOMEM;
  2042. }
  2043. version_entry = snd_info_create_card_entry(card->snd_card,
  2044. "version",
  2045. priv->entry);
  2046. if (!version_entry) {
  2047. dev_dbg(component->dev, "%s: failed to create wcd937x version entry\n",
  2048. __func__);
  2049. return -ENOMEM;
  2050. }
  2051. version_entry->private_data = priv;
  2052. version_entry->size = WCD937X_VERSION_ENTRY_SIZE;
  2053. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2054. version_entry->c.ops = &wcd937x_info_ops;
  2055. if (snd_info_register(version_entry) < 0) {
  2056. snd_info_free_entry(version_entry);
  2057. return -ENOMEM;
  2058. }
  2059. priv->version_entry = version_entry;
  2060. variant_entry = snd_info_create_card_entry(card->snd_card,
  2061. "variant",
  2062. priv->entry);
  2063. if (!variant_entry) {
  2064. dev_dbg(codec->dev, "%s: failed to create wcd937x variant entry\n",
  2065. __func__);
  2066. return -ENOMEM;
  2067. }
  2068. variant_entry->private_data = priv;
  2069. variant_entry->size = WCD937X_VARIANT_ENTRY_SIZE;
  2070. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2071. variant_entry->c.ops = &wcd937x_variant_ops;
  2072. if (snd_info_register(variant_entry) < 0) {
  2073. snd_info_free_entry(variant_entry);
  2074. return -ENOMEM;
  2075. }
  2076. priv->variant_entry = variant_entry;
  2077. return 0;
  2078. }
  2079. EXPORT_SYMBOL(wcd937x_info_create_codec_entry);
  2080. static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x,
  2081. struct wcd937x_pdata *pdata)
  2082. {
  2083. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0;
  2084. int rc = 0;
  2085. if (!pdata) {
  2086. dev_err(wcd937x->dev, "%s: NULL pdata\n", __func__);
  2087. return -ENODEV;
  2088. }
  2089. /* set micbias voltage */
  2090. vout_ctl_1 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  2091. vout_ctl_2 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  2092. vout_ctl_3 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  2093. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0) {
  2094. rc = -EINVAL;
  2095. goto done;
  2096. }
  2097. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, 0x3F,
  2098. vout_ctl_1);
  2099. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, 0x3F,
  2100. vout_ctl_2);
  2101. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, 0x3F,
  2102. vout_ctl_3);
  2103. done:
  2104. return rc;
  2105. }
  2106. static int wcd937x_soc_codec_probe(struct snd_soc_component *component)
  2107. {
  2108. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2109. struct snd_soc_dapm_context *dapm =
  2110. snd_soc_component_get_dapm(component);
  2111. int variant;
  2112. int ret = -EINVAL;
  2113. dev_info(component->dev, "%s()\n", __func__);
  2114. wcd937x = snd_soc_component_get_drvdata(component);
  2115. if (!wcd937x)
  2116. return -EINVAL;
  2117. wcd937x->component = component;
  2118. variant = (snd_soc_component_read32(
  2119. component, WCD937X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2120. wcd937x->variant = variant;
  2121. wcd937x->fw_data = devm_kzalloc(component->dev,
  2122. sizeof(*(wcd937x->fw_data)),
  2123. GFP_KERNEL);
  2124. if (!wcd937x->fw_data) {
  2125. dev_err(component->dev, "Failed to allocate fw_data\n");
  2126. ret = -ENOMEM;
  2127. goto err;
  2128. }
  2129. set_bit(WCD9XXX_MBHC_CAL, wcd937x->fw_data->cal_bit);
  2130. ret = wcd_cal_create_hwdep(wcd937x->fw_data,
  2131. WCD9XXX_CODEC_HWDEP_NODE, component);
  2132. if (ret < 0) {
  2133. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2134. goto err_hwdep;
  2135. }
  2136. ret = wcd937x_mbhc_init(&wcd937x->mbhc, component, wcd937x->fw_data);
  2137. if (ret) {
  2138. pr_err("%s: mbhc initialization failed\n", __func__);
  2139. goto err_hwdep;
  2140. }
  2141. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2142. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2143. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2144. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2145. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2146. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2147. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2148. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2149. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2150. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2151. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2152. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2153. snd_soc_dapm_sync(dapm);
  2154. wcd_cls_h_init(&wcd937x->clsh_info);
  2155. wcd937x_init_reg(component);
  2156. if (wcd937x->variant == WCD9375_VARIANT) {
  2157. ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets,
  2158. ARRAY_SIZE(wcd9375_dapm_widgets));
  2159. if (ret < 0) {
  2160. dev_err(component->dev, "%s: Failed to add snd_ctls\n",
  2161. __func__);
  2162. goto err_hwdep;
  2163. }
  2164. ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map,
  2165. ARRAY_SIZE(wcd9375_audio_map));
  2166. if (ret < 0) {
  2167. dev_err(component->dev, "%s: Failed to add routes\n",
  2168. __func__);
  2169. goto err_hwdep;
  2170. }
  2171. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2172. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2173. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2174. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2175. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2176. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2177. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2178. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2179. snd_soc_dapm_sync(dapm);
  2180. }
  2181. wcd937x->version = WCD937X_VERSION_1_0;
  2182. /* Register event notifier */
  2183. wcd937x->nblock.notifier_call = wcd937x_event_notify;
  2184. if (wcd937x->register_notifier) {
  2185. ret = wcd937x->register_notifier(wcd937x->handle,
  2186. &wcd937x->nblock,
  2187. true);
  2188. if (ret) {
  2189. dev_err(component->dev,
  2190. "%s: Failed to register notifier %d\n",
  2191. __func__, ret);
  2192. return ret;
  2193. }
  2194. }
  2195. return ret;
  2196. err_hwdep:
  2197. wcd937x->fw_data = NULL;
  2198. err:
  2199. return ret;
  2200. }
  2201. static void wcd937x_soc_codec_remove(struct snd_soc_component *component)
  2202. {
  2203. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2204. if (!wcd937x)
  2205. return;
  2206. if (wcd937x->register_notifier)
  2207. wcd937x->register_notifier(wcd937x->handle,
  2208. &wcd937x->nblock,
  2209. false);
  2210. return;
  2211. }
  2212. static const struct snd_soc_component_driver soc_codec_dev_wcd937x = {
  2213. .name = DRV_NAME,
  2214. .probe = wcd937x_soc_codec_probe,
  2215. .remove = wcd937x_soc_codec_remove,
  2216. .controls = wcd937x_snd_controls,
  2217. .num_controls = ARRAY_SIZE(wcd937x_snd_controls),
  2218. .dapm_widgets = wcd937x_dapm_widgets,
  2219. .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets),
  2220. .dapm_routes = wcd937x_audio_map,
  2221. .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map),
  2222. };
  2223. #ifdef CONFIG_PM_SLEEP
  2224. static int wcd937x_suspend(struct device *dev)
  2225. {
  2226. struct wcd937x_priv *wcd937x = NULL;
  2227. int ret = 0;
  2228. struct wcd937x_pdata *pdata = NULL;
  2229. if (!dev)
  2230. return -ENODEV;
  2231. wcd937x = dev_get_drvdata(dev);
  2232. if (!wcd937x)
  2233. return -EINVAL;
  2234. pdata = dev_get_platdata(wcd937x->dev);
  2235. if (!pdata) {
  2236. dev_err(dev, "%s: pdata is NULL\n", __func__);
  2237. return -EINVAL;
  2238. }
  2239. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  2240. ret = msm_cdc_disable_ondemand_supply(wcd937x->dev,
  2241. wcd937x->supplies,
  2242. pdata->regulator,
  2243. pdata->num_supplies,
  2244. "cdc-vdd-buck");
  2245. if (ret == -EINVAL) {
  2246. dev_err(dev, "%s: vdd buck is not disabled\n",
  2247. __func__);
  2248. return 0;
  2249. }
  2250. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  2251. }
  2252. return 0;
  2253. }
  2254. static int wcd937x_resume(struct device *dev)
  2255. {
  2256. return 0;
  2257. }
  2258. #endif
  2259. static int wcd937x_reset(struct device *dev)
  2260. {
  2261. struct wcd937x_priv *wcd937x = NULL;
  2262. int rc = 0;
  2263. int value = 0;
  2264. if (!dev)
  2265. return -ENODEV;
  2266. wcd937x = dev_get_drvdata(dev);
  2267. if (!wcd937x)
  2268. return -EINVAL;
  2269. if (!wcd937x->rst_np) {
  2270. dev_err(dev, "%s: reset gpio device node not specified\n",
  2271. __func__);
  2272. return -EINVAL;
  2273. }
  2274. value = msm_cdc_pinctrl_get_state(wcd937x->rst_np);
  2275. if (value > 0)
  2276. return 0;
  2277. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2278. if (rc) {
  2279. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2280. __func__);
  2281. return rc;
  2282. }
  2283. /* 20ms sleep required after pulling the reset gpio to LOW */
  2284. usleep_range(20, 30);
  2285. rc = msm_cdc_pinctrl_select_active_state(wcd937x->rst_np);
  2286. if (rc) {
  2287. dev_err(dev, "%s: wcd active state request fail!\n",
  2288. __func__);
  2289. return rc;
  2290. }
  2291. /* 20ms sleep required after pulling the reset gpio to HIGH */
  2292. usleep_range(20, 30);
  2293. return rc;
  2294. }
  2295. static int wcd937x_read_of_property_u32(struct device *dev, const char *name,
  2296. u32 *val)
  2297. {
  2298. int rc = 0;
  2299. rc = of_property_read_u32(dev->of_node, name, val);
  2300. if (rc)
  2301. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2302. __func__, name, dev->of_node->full_name);
  2303. return rc;
  2304. }
  2305. static void wcd937x_dt_parse_micbias_info(struct device *dev,
  2306. struct wcd937x_micbias_setting *mb)
  2307. {
  2308. u32 prop_val = 0;
  2309. int rc = 0;
  2310. /* MB1 */
  2311. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2312. NULL)) {
  2313. rc = wcd937x_read_of_property_u32(dev,
  2314. "qcom,cdc-micbias1-mv",
  2315. &prop_val);
  2316. if (!rc)
  2317. mb->micb1_mv = prop_val;
  2318. } else {
  2319. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2320. __func__);
  2321. }
  2322. /* MB2 */
  2323. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2324. NULL)) {
  2325. rc = wcd937x_read_of_property_u32(dev,
  2326. "qcom,cdc-micbias2-mv",
  2327. &prop_val);
  2328. if (!rc)
  2329. mb->micb2_mv = prop_val;
  2330. } else {
  2331. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2332. __func__);
  2333. }
  2334. /* MB3 */
  2335. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2336. NULL)) {
  2337. rc = wcd937x_read_of_property_u32(dev,
  2338. "qcom,cdc-micbias3-mv",
  2339. &prop_val);
  2340. if (!rc)
  2341. mb->micb3_mv = prop_val;
  2342. } else {
  2343. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2344. __func__);
  2345. }
  2346. }
  2347. static int wcd937x_reset_low(struct device *dev)
  2348. {
  2349. struct wcd937x_priv *wcd937x = NULL;
  2350. int rc = 0;
  2351. if (!dev)
  2352. return -ENODEV;
  2353. wcd937x = dev_get_drvdata(dev);
  2354. if (!wcd937x)
  2355. return -EINVAL;
  2356. if (!wcd937x->rst_np) {
  2357. dev_err(dev, "%s: reset gpio device node not specified\n",
  2358. __func__);
  2359. return -EINVAL;
  2360. }
  2361. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2362. if (rc) {
  2363. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2364. __func__);
  2365. return rc;
  2366. }
  2367. /* 20ms sleep required after pulling the reset gpio to LOW */
  2368. usleep_range(20, 30);
  2369. return rc;
  2370. }
  2371. struct wcd937x_pdata *wcd937x_populate_dt_data(struct device *dev)
  2372. {
  2373. struct wcd937x_pdata *pdata = NULL;
  2374. pdata = kzalloc(sizeof(struct wcd937x_pdata),
  2375. GFP_KERNEL);
  2376. if (!pdata)
  2377. return NULL;
  2378. pdata->rst_np = of_parse_phandle(dev->of_node,
  2379. "qcom,wcd-rst-gpio-node", 0);
  2380. if (!pdata->rst_np) {
  2381. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2382. __func__, "qcom,wcd-rst-gpio-node",
  2383. dev->of_node->full_name);
  2384. return NULL;
  2385. }
  2386. /* Parse power supplies */
  2387. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2388. &pdata->num_supplies);
  2389. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2390. dev_err(dev, "%s: no power supplies defined for codec\n",
  2391. __func__);
  2392. return NULL;
  2393. }
  2394. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2395. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2396. wcd937x_dt_parse_micbias_info(dev, &pdata->micbias);
  2397. return pdata;
  2398. }
  2399. static int wcd937x_wakeup(void *handle, bool enable)
  2400. {
  2401. struct wcd937x_priv *priv;
  2402. if (!handle) {
  2403. pr_err("%s: NULL handle\n", __func__);
  2404. return -EINVAL;
  2405. }
  2406. priv = (struct wcd937x_priv *)handle;
  2407. if (!priv->tx_swr_dev) {
  2408. pr_err("%s: tx swr dev is NULL\n", __func__);
  2409. return -EINVAL;
  2410. }
  2411. if (enable)
  2412. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2413. else
  2414. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2415. }
  2416. static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data)
  2417. {
  2418. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2419. __func__, irq);
  2420. return IRQ_HANDLED;
  2421. }
  2422. static int wcd937x_bind(struct device *dev)
  2423. {
  2424. int ret = 0, i = 0;
  2425. struct wcd937x_priv *wcd937x = NULL;
  2426. struct wcd937x_pdata *pdata = NULL;
  2427. struct wcd_ctrl_platform_data *plat_data = NULL;
  2428. wcd937x = kzalloc(sizeof(struct wcd937x_priv), GFP_KERNEL);
  2429. if (!wcd937x)
  2430. return -ENOMEM;
  2431. dev_set_drvdata(dev, wcd937x);
  2432. pdata = wcd937x_populate_dt_data(dev);
  2433. if (!pdata) {
  2434. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2435. return -EINVAL;
  2436. }
  2437. wcd937x->dev = dev;
  2438. wcd937x->dev->platform_data = pdata;
  2439. wcd937x->rst_np = pdata->rst_np;
  2440. ret = msm_cdc_init_supplies(dev, &wcd937x->supplies,
  2441. pdata->regulator, pdata->num_supplies);
  2442. if (!wcd937x->supplies) {
  2443. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2444. __func__);
  2445. goto err_bind_all;
  2446. }
  2447. plat_data = dev_get_platdata(dev->parent);
  2448. if (!plat_data) {
  2449. dev_err(dev, "%s: platform data from parent is NULL\n",
  2450. __func__);
  2451. ret = -EINVAL;
  2452. goto err_bind_all;
  2453. }
  2454. wcd937x->handle = (void *)plat_data->handle;
  2455. if (!wcd937x->handle) {
  2456. dev_err(dev, "%s: handle is NULL\n", __func__);
  2457. ret = -EINVAL;
  2458. goto err_bind_all;
  2459. }
  2460. wcd937x->update_wcd_event = plat_data->update_wcd_event;
  2461. if (!wcd937x->update_wcd_event) {
  2462. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2463. __func__);
  2464. ret = -EINVAL;
  2465. goto err_bind_all;
  2466. }
  2467. wcd937x->register_notifier = plat_data->register_notifier;
  2468. if (!wcd937x->register_notifier) {
  2469. dev_err(dev, "%s: register_notifier api is null!\n",
  2470. __func__);
  2471. ret = -EINVAL;
  2472. goto err_bind_all;
  2473. }
  2474. ret = msm_cdc_enable_static_supplies(dev, wcd937x->supplies,
  2475. pdata->regulator,
  2476. pdata->num_supplies);
  2477. if (ret) {
  2478. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2479. __func__);
  2480. goto err_bind_all;
  2481. }
  2482. wcd937x_reset(dev);
  2483. /*
  2484. * Add 5msec delay to provide sufficient time for
  2485. * soundwire auto enumeration of slave devices as
  2486. * as per HW requirement.
  2487. */
  2488. usleep_range(5000, 5010);
  2489. wcd937x->wakeup = wcd937x_wakeup;
  2490. ret = component_bind_all(dev, wcd937x);
  2491. if (ret) {
  2492. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2493. __func__, ret);
  2494. goto err_bind_all;
  2495. }
  2496. ret = wcd937x_parse_port_mapping(dev, "qcom,rx_swr_ch_map", CODEC_RX);
  2497. ret |= wcd937x_parse_port_mapping(dev, "qcom,tx_swr_ch_map", CODEC_TX);
  2498. if (ret) {
  2499. dev_err(dev, "Failed to read port mapping\n");
  2500. goto err;
  2501. }
  2502. wcd937x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2503. if (!wcd937x->rx_swr_dev) {
  2504. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2505. __func__);
  2506. ret = -ENODEV;
  2507. goto err;
  2508. }
  2509. wcd937x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2510. if (!wcd937x->tx_swr_dev) {
  2511. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2512. __func__);
  2513. ret = -ENODEV;
  2514. goto err;
  2515. }
  2516. wcd937x->regmap = devm_regmap_init_swr(wcd937x->tx_swr_dev,
  2517. &wcd937x_regmap_config);
  2518. if (!wcd937x->regmap) {
  2519. dev_err(dev, "%s: Regmap init failed\n",
  2520. __func__);
  2521. goto err;
  2522. }
  2523. /* Set all interupts as edge triggered */
  2524. for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++)
  2525. regmap_write(wcd937x->regmap,
  2526. (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2527. wcd937x_regmap_irq_chip.irq_drv_data = wcd937x;
  2528. wcd937x->irq_info.wcd_regmap_irq_chip = &wcd937x_regmap_irq_chip;
  2529. wcd937x->irq_info.codec_name = "WCD937X";
  2530. wcd937x->irq_info.regmap = wcd937x->regmap;
  2531. wcd937x->irq_info.dev = dev;
  2532. ret = wcd_irq_init(&wcd937x->irq_info, &wcd937x->virq);
  2533. if (ret) {
  2534. dev_err(dev, "%s: IRQ init failed: %d\n",
  2535. __func__, ret);
  2536. goto err;
  2537. }
  2538. wcd937x->tx_swr_dev->slave_irq = wcd937x->virq;
  2539. ret = wcd937x_set_micbias_data(wcd937x, pdata);
  2540. if (ret < 0) {
  2541. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  2542. goto err_irq;
  2543. }
  2544. mutex_init(&wcd937x->micb_lock);
  2545. mutex_init(&wcd937x->ana_tx_clk_lock);
  2546. /* Request for watchdog interrupt */
  2547. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT,
  2548. "HPHR PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2549. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT,
  2550. "HPHL PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2551. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT,
  2552. "AUX PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2553. /* Disable watchdog interrupt for HPH and AUX */
  2554. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT);
  2555. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT);
  2556. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  2557. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x,
  2558. NULL, 0);
  2559. if (ret) {
  2560. dev_err(dev, "%s: Codec registration failed\n",
  2561. __func__);
  2562. goto err_irq;
  2563. }
  2564. return ret;
  2565. err_irq:
  2566. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2567. err:
  2568. component_unbind_all(dev, wcd937x);
  2569. err_bind_all:
  2570. dev_set_drvdata(dev, NULL);
  2571. kfree(pdata);
  2572. kfree(wcd937x);
  2573. return ret;
  2574. }
  2575. static void wcd937x_unbind(struct device *dev)
  2576. {
  2577. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  2578. struct wcd937x_pdata *pdata = dev_get_platdata(wcd937x->dev);
  2579. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2580. snd_soc_unregister_component(dev);
  2581. component_unbind_all(dev, wcd937x);
  2582. mutex_destroy(&wcd937x->micb_lock);
  2583. mutex_destroy(&wcd937x->ana_tx_clk_lock);
  2584. dev_set_drvdata(dev, NULL);
  2585. kfree(pdata);
  2586. kfree(wcd937x);
  2587. }
  2588. static const struct of_device_id wcd937x_dt_match[] = {
  2589. { .compatible = "qcom,wcd937x-codec" },
  2590. {}
  2591. };
  2592. static const struct component_master_ops wcd937x_comp_ops = {
  2593. .bind = wcd937x_bind,
  2594. .unbind = wcd937x_unbind,
  2595. };
  2596. static int wcd937x_compare_of(struct device *dev, void *data)
  2597. {
  2598. return dev->of_node == data;
  2599. }
  2600. static void wcd937x_release_of(struct device *dev, void *data)
  2601. {
  2602. of_node_put(data);
  2603. }
  2604. static int wcd937x_add_slave_components(struct device *dev,
  2605. struct component_match **matchptr)
  2606. {
  2607. struct device_node *np, *rx_node, *tx_node;
  2608. np = dev->of_node;
  2609. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  2610. if (!rx_node) {
  2611. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  2612. return -ENODEV;
  2613. }
  2614. of_node_get(rx_node);
  2615. component_match_add_release(dev, matchptr,
  2616. wcd937x_release_of,
  2617. wcd937x_compare_of,
  2618. rx_node);
  2619. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  2620. if (!tx_node) {
  2621. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  2622. return -ENODEV;
  2623. }
  2624. of_node_get(tx_node);
  2625. component_match_add_release(dev, matchptr,
  2626. wcd937x_release_of,
  2627. wcd937x_compare_of,
  2628. tx_node);
  2629. return 0;
  2630. }
  2631. static int wcd937x_probe(struct platform_device *pdev)
  2632. {
  2633. struct component_match *match = NULL;
  2634. int ret;
  2635. ret = wcd937x_add_slave_components(&pdev->dev, &match);
  2636. if (ret)
  2637. return ret;
  2638. return component_master_add_with_match(&pdev->dev,
  2639. &wcd937x_comp_ops, match);
  2640. }
  2641. static int wcd937x_remove(struct platform_device *pdev)
  2642. {
  2643. component_master_del(&pdev->dev, &wcd937x_comp_ops);
  2644. dev_set_drvdata(&pdev->dev, NULL);
  2645. return 0;
  2646. }
  2647. #ifdef CONFIG_PM_SLEEP
  2648. static const struct dev_pm_ops wcd937x_dev_pm_ops = {
  2649. SET_SYSTEM_SLEEP_PM_OPS(
  2650. wcd937x_suspend,
  2651. wcd937x_resume
  2652. )
  2653. };
  2654. #endif
  2655. static struct platform_driver wcd937x_codec_driver = {
  2656. .probe = wcd937x_probe,
  2657. .remove = wcd937x_remove,
  2658. .driver = {
  2659. .name = "wcd937x_codec",
  2660. .owner = THIS_MODULE,
  2661. .of_match_table = of_match_ptr(wcd937x_dt_match),
  2662. #ifdef CONFIG_PM_SLEEP
  2663. .pm = &wcd937x_dev_pm_ops,
  2664. #endif
  2665. .suppress_bind_attrs = true,
  2666. },
  2667. };
  2668. module_platform_driver(wcd937x_codec_driver);
  2669. MODULE_DESCRIPTION("WCD937X Codec driver");
  2670. MODULE_LICENSE("GPL v2");