sde_encoder_phys_wb.c 59 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  6. #include <linux/debugfs.h>
  7. #include <drm/sde_drm.h>
  8. #include "sde_encoder_phys.h"
  9. #include "sde_formats.h"
  10. #include "sde_hw_top.h"
  11. #include "sde_hw_interrupts.h"
  12. #include "sde_core_irq.h"
  13. #include "sde_wb.h"
  14. #include "sde_vbif.h"
  15. #include "sde_crtc.h"
  16. #define to_sde_encoder_phys_wb(x) \
  17. container_of(x, struct sde_encoder_phys_wb, base)
  18. #define WBID(wb_enc) \
  19. ((wb_enc && wb_enc->wb_dev) ? wb_enc->wb_dev->wb_idx - WB_0 : -1)
  20. #define TO_S15D16(_x_) ((_x_) << 7)
  21. #define SDE_WB_MAX_LINEWIDTH(fmt, wb_cfg) \
  22. (SDE_FORMAT_IS_UBWC(fmt) ? wb_cfg->sblk->maxlinewidth : \
  23. wb_cfg->sblk->maxlinewidth_linear)
  24. static const u32 cwb_irq_tbl[PINGPONG_MAX] = {SDE_NONE, INTR_IDX_PP1_OVFL,
  25. INTR_IDX_PP2_OVFL, INTR_IDX_PP3_OVFL, INTR_IDX_PP4_OVFL,
  26. INTR_IDX_PP5_OVFL, SDE_NONE, SDE_NONE};
  27. static const u32 dcwb_irq_tbl[PINGPONG_MAX] = {SDE_NONE, SDE_NONE,
  28. SDE_NONE, SDE_NONE, SDE_NONE, SDE_NONE,
  29. INTR_IDX_PP_CWB_OVFL, SDE_NONE};
  30. /**
  31. * sde_rgb2yuv_601l - rgb to yuv color space conversion matrix
  32. *
  33. */
  34. static struct sde_csc_cfg sde_encoder_phys_wb_rgb2yuv_601l = {
  35. {
  36. TO_S15D16(0x0083), TO_S15D16(0x0102), TO_S15D16(0x0032),
  37. TO_S15D16(0x1fb5), TO_S15D16(0x1f6c), TO_S15D16(0x00e1),
  38. TO_S15D16(0x00e1), TO_S15D16(0x1f45), TO_S15D16(0x1fdc)
  39. },
  40. { 0x00, 0x00, 0x00 },
  41. { 0x0040, 0x0200, 0x0200 },
  42. { 0x000, 0x3ff, 0x000, 0x3ff, 0x000, 0x3ff },
  43. { 0x040, 0x3ac, 0x040, 0x3c0, 0x040, 0x3c0 },
  44. };
  45. /**
  46. * sde_encoder_phys_wb_is_master - report wb always as master encoder
  47. */
  48. static bool sde_encoder_phys_wb_is_master(struct sde_encoder_phys *phys_enc)
  49. {
  50. return true;
  51. }
  52. /**
  53. * sde_encoder_phys_wb_get_intr_type - get interrupt type based on block mode
  54. * @hw_wb: Pointer to h/w writeback driver
  55. */
  56. static enum sde_intr_type sde_encoder_phys_wb_get_intr_type(
  57. struct sde_hw_wb *hw_wb)
  58. {
  59. return (hw_wb->caps->features & BIT(SDE_WB_BLOCK_MODE)) ?
  60. SDE_IRQ_TYPE_WB_ROT_COMP : SDE_IRQ_TYPE_WB_WFD_COMP;
  61. }
  62. /**
  63. * sde_encoder_phys_wb_set_ot_limit - set OT limit for writeback interface
  64. * @phys_enc: Pointer to physical encoder
  65. */
  66. static void sde_encoder_phys_wb_set_ot_limit(
  67. struct sde_encoder_phys *phys_enc)
  68. {
  69. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  70. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  71. struct sde_vbif_set_ot_params ot_params;
  72. memset(&ot_params, 0, sizeof(ot_params));
  73. ot_params.xin_id = hw_wb->caps->xin_id;
  74. ot_params.num = hw_wb->idx - WB_0;
  75. ot_params.width = wb_enc->wb_roi.w;
  76. ot_params.height = wb_enc->wb_roi.h;
  77. ot_params.is_wfd = true;
  78. ot_params.frame_rate = drm_mode_vrefresh(&phys_enc->cached_mode);
  79. ot_params.vbif_idx = hw_wb->caps->vbif_idx;
  80. ot_params.clk_ctrl = hw_wb->caps->clk_ctrl;
  81. ot_params.rd = false;
  82. sde_vbif_set_ot_limit(phys_enc->sde_kms, &ot_params);
  83. }
  84. /**
  85. * sde_encoder_phys_wb_set_qos_remap - set QoS remapper for writeback
  86. * @phys_enc: Pointer to physical encoder
  87. */
  88. static void sde_encoder_phys_wb_set_qos_remap(
  89. struct sde_encoder_phys *phys_enc)
  90. {
  91. struct sde_encoder_phys_wb *wb_enc;
  92. struct sde_hw_wb *hw_wb;
  93. struct drm_crtc *crtc;
  94. struct sde_vbif_set_qos_params qos_params;
  95. if (!phys_enc || !phys_enc->parent || !phys_enc->parent->crtc) {
  96. SDE_ERROR("invalid arguments\n");
  97. return;
  98. }
  99. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  100. if (!wb_enc->crtc) {
  101. SDE_ERROR("invalid crtc");
  102. return;
  103. }
  104. crtc = wb_enc->crtc;
  105. if (!wb_enc->hw_wb || !wb_enc->hw_wb->caps) {
  106. SDE_ERROR("invalid writeback hardware\n");
  107. return;
  108. }
  109. hw_wb = wb_enc->hw_wb;
  110. memset(&qos_params, 0, sizeof(qos_params));
  111. qos_params.vbif_idx = hw_wb->caps->vbif_idx;
  112. qos_params.xin_id = hw_wb->caps->xin_id;
  113. qos_params.clk_ctrl = hw_wb->caps->clk_ctrl;
  114. qos_params.num = hw_wb->idx - WB_0;
  115. qos_params.client_type = phys_enc->in_clone_mode ?
  116. VBIF_CWB_CLIENT : VBIF_NRT_CLIENT;
  117. SDE_DEBUG("[qos_remap] wb:%d vbif:%d xin:%d clone:%d\n",
  118. qos_params.num,
  119. qos_params.vbif_idx,
  120. qos_params.xin_id, qos_params.client_type);
  121. sde_vbif_set_qos_remap(phys_enc->sde_kms, &qos_params);
  122. }
  123. /**
  124. * sde_encoder_phys_wb_set_qos - set QoS/danger/safe LUTs for writeback
  125. * @phys_enc: Pointer to physical encoder
  126. */
  127. static void sde_encoder_phys_wb_set_qos(struct sde_encoder_phys *phys_enc)
  128. {
  129. struct sde_encoder_phys_wb *wb_enc;
  130. struct sde_hw_wb *hw_wb;
  131. struct sde_hw_wb_qos_cfg qos_cfg = {0};
  132. struct sde_perf_cfg *perf;
  133. u32 fps_index = 0, lut_index, index, frame_rate, qos_count;
  134. if (!phys_enc || !phys_enc->sde_kms || !phys_enc->sde_kms->catalog) {
  135. SDE_ERROR("invalid parameter(s)\n");
  136. return;
  137. }
  138. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  139. if (!wb_enc->hw_wb) {
  140. SDE_ERROR("invalid writeback hardware\n");
  141. return;
  142. }
  143. perf = &phys_enc->sde_kms->catalog->perf;
  144. frame_rate = drm_mode_vrefresh(&phys_enc->cached_mode);
  145. hw_wb = wb_enc->hw_wb;
  146. qos_count = perf->qos_refresh_count;
  147. while ((fps_index < qos_count) && perf->qos_refresh_rate) {
  148. if ((frame_rate <= perf->qos_refresh_rate[fps_index]) ||
  149. (fps_index == qos_count - 1))
  150. break;
  151. fps_index++;
  152. }
  153. qos_cfg.danger_safe_en = true;
  154. if (phys_enc->in_clone_mode && (SDE_FORMAT_IS_TILE(wb_enc->wb_fmt) ||
  155. SDE_FORMAT_IS_UBWC(wb_enc->wb_fmt)))
  156. lut_index = SDE_QOS_LUT_USAGE_CWB_TILE;
  157. else if (phys_enc->in_clone_mode)
  158. lut_index = SDE_QOS_LUT_USAGE_CWB;
  159. else
  160. lut_index = SDE_QOS_LUT_USAGE_NRT;
  161. index = (fps_index * SDE_QOS_LUT_USAGE_MAX) + lut_index;
  162. qos_cfg.danger_lut = perf->danger_lut[index];
  163. qos_cfg.safe_lut = (u32) perf->safe_lut[index];
  164. qos_cfg.creq_lut = perf->creq_lut[index * SDE_CREQ_LUT_TYPE_MAX];
  165. SDE_DEBUG("wb_enc:%d hw idx:%d fps:%d mode:%d luts[0x%x,0x%x 0x%llx]\n",
  166. DRMID(phys_enc->parent), hw_wb->idx - WB_0,
  167. frame_rate, phys_enc->in_clone_mode,
  168. qos_cfg.danger_lut, qos_cfg.safe_lut, qos_cfg.creq_lut);
  169. if (hw_wb->ops.setup_qos_lut)
  170. hw_wb->ops.setup_qos_lut(hw_wb, &qos_cfg);
  171. }
  172. /**
  173. * sde_encoder_phys_setup_cdm - setup chroma down block
  174. * @phys_enc: Pointer to physical encoder
  175. * @fb: Pointer to output framebuffer
  176. * @format: Output format
  177. */
  178. void sde_encoder_phys_setup_cdm(struct sde_encoder_phys *phys_enc,
  179. struct drm_framebuffer *fb, const struct sde_format *format,
  180. struct sde_rect *wb_roi)
  181. {
  182. struct sde_hw_cdm *hw_cdm;
  183. struct sde_hw_cdm_cfg *cdm_cfg;
  184. struct sde_hw_pingpong *hw_pp;
  185. int ret;
  186. if (!phys_enc || !format)
  187. return;
  188. cdm_cfg = &phys_enc->cdm_cfg;
  189. hw_pp = phys_enc->hw_pp;
  190. hw_cdm = phys_enc->hw_cdm;
  191. if (!hw_cdm)
  192. return;
  193. if (!SDE_FORMAT_IS_YUV(format)) {
  194. SDE_DEBUG("[cdm_disable fmt:%x]\n",
  195. format->base.pixel_format);
  196. if (hw_cdm && hw_cdm->ops.disable)
  197. hw_cdm->ops.disable(hw_cdm);
  198. return;
  199. }
  200. memset(cdm_cfg, 0, sizeof(struct sde_hw_cdm_cfg));
  201. if (!wb_roi)
  202. return;
  203. cdm_cfg->output_width = wb_roi->w;
  204. cdm_cfg->output_height = wb_roi->h;
  205. cdm_cfg->output_fmt = format;
  206. cdm_cfg->output_type = CDM_CDWN_OUTPUT_WB;
  207. cdm_cfg->output_bit_depth = SDE_FORMAT_IS_DX(format) ?
  208. CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT;
  209. /* enable 10 bit logic */
  210. switch (cdm_cfg->output_fmt->chroma_sample) {
  211. case SDE_CHROMA_RGB:
  212. cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
  213. cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
  214. break;
  215. case SDE_CHROMA_H2V1:
  216. cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
  217. cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
  218. break;
  219. case SDE_CHROMA_420:
  220. cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
  221. cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE;
  222. break;
  223. case SDE_CHROMA_H1V2:
  224. default:
  225. SDE_ERROR("unsupported chroma sampling type\n");
  226. cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
  227. cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
  228. break;
  229. }
  230. SDE_DEBUG("[cdm_enable:%d,%d,%X,%d,%d,%d,%d]\n",
  231. cdm_cfg->output_width,
  232. cdm_cfg->output_height,
  233. cdm_cfg->output_fmt->base.pixel_format,
  234. cdm_cfg->output_type,
  235. cdm_cfg->output_bit_depth,
  236. cdm_cfg->h_cdwn_type,
  237. cdm_cfg->v_cdwn_type);
  238. if (hw_cdm && hw_cdm->ops.setup_csc_data) {
  239. ret = hw_cdm->ops.setup_csc_data(hw_cdm,
  240. &sde_encoder_phys_wb_rgb2yuv_601l);
  241. if (ret < 0) {
  242. SDE_ERROR("failed to setup CSC %d\n", ret);
  243. return;
  244. }
  245. }
  246. if (hw_cdm && hw_cdm->ops.setup_cdwn) {
  247. ret = hw_cdm->ops.setup_cdwn(hw_cdm, cdm_cfg);
  248. if (ret < 0) {
  249. SDE_ERROR("failed to setup CDM %d\n", ret);
  250. return;
  251. }
  252. }
  253. if (hw_cdm && hw_pp && hw_cdm->ops.enable) {
  254. cdm_cfg->pp_id = hw_pp->idx;
  255. ret = hw_cdm->ops.enable(hw_cdm, cdm_cfg);
  256. if (ret < 0) {
  257. SDE_ERROR("failed to enable CDM %d\n", ret);
  258. return;
  259. }
  260. }
  261. }
  262. /**
  263. * sde_encoder_phys_wb_setup_fb - setup output framebuffer
  264. * @phys_enc: Pointer to physical encoder
  265. * @fb: Pointer to output framebuffer
  266. * @wb_roi: Pointer to output region of interest
  267. */
  268. static void sde_encoder_phys_wb_setup_fb(struct sde_encoder_phys *phys_enc,
  269. struct drm_framebuffer *fb, struct sde_rect *wb_roi)
  270. {
  271. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  272. struct sde_hw_wb *hw_wb;
  273. struct sde_hw_wb_cfg *wb_cfg;
  274. struct sde_hw_wb_cdp_cfg *cdp_cfg;
  275. const struct msm_format *format;
  276. struct sde_crtc_state *cstate;
  277. struct sde_rect pu_roi = {0,};
  278. int ret;
  279. struct msm_gem_address_space *aspace;
  280. u32 fb_mode;
  281. if (!phys_enc || !phys_enc->sde_kms || !phys_enc->sde_kms->catalog ||
  282. !phys_enc->connector) {
  283. SDE_ERROR("invalid encoder\n");
  284. return;
  285. }
  286. cstate = to_sde_crtc_state(wb_enc->crtc->state);
  287. hw_wb = wb_enc->hw_wb;
  288. wb_cfg = &wb_enc->wb_cfg;
  289. cdp_cfg = &wb_enc->cdp_cfg;
  290. memset(wb_cfg, 0, sizeof(struct sde_hw_wb_cfg));
  291. wb_cfg->intf_mode = phys_enc->intf_mode;
  292. fb_mode = sde_connector_get_property(phys_enc->connector->state,
  293. CONNECTOR_PROP_FB_TRANSLATION_MODE);
  294. if (phys_enc->enable_state == SDE_ENC_DISABLING)
  295. wb_cfg->is_secure = false;
  296. else if (fb_mode == SDE_DRM_FB_SEC)
  297. wb_cfg->is_secure = true;
  298. else
  299. wb_cfg->is_secure = false;
  300. aspace = (wb_cfg->is_secure) ?
  301. wb_enc->aspace[SDE_IOMMU_DOMAIN_SECURE] :
  302. wb_enc->aspace[SDE_IOMMU_DOMAIN_UNSECURE];
  303. SDE_DEBUG("[fb_secure:%d]\n", wb_cfg->is_secure);
  304. ret = msm_framebuffer_prepare(fb, aspace);
  305. if (ret) {
  306. SDE_ERROR("prep fb failed, %d\n", ret);
  307. return;
  308. }
  309. /* cache framebuffer for cleanup in writeback done */
  310. wb_enc->wb_fb = fb;
  311. wb_enc->wb_aspace = aspace;
  312. drm_framebuffer_get(fb);
  313. format = msm_framebuffer_format(fb);
  314. if (!format) {
  315. SDE_DEBUG("invalid format for fb\n");
  316. return;
  317. }
  318. wb_cfg->dest.format = sde_get_sde_format_ext(
  319. format->pixel_format,
  320. fb->modifier);
  321. if (!wb_cfg->dest.format) {
  322. /* this error should be detected during atomic_check */
  323. SDE_ERROR("failed to get format %x\n", format->pixel_format);
  324. return;
  325. }
  326. wb_cfg->roi = *wb_roi;
  327. ret = sde_format_populate_layout(aspace, fb, &wb_cfg->dest);
  328. if (ret) {
  329. SDE_DEBUG("failed to populate layout %d\n", ret);
  330. return;
  331. }
  332. wb_cfg->dest.width = fb->width;
  333. wb_cfg->dest.height = fb->height;
  334. wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes;
  335. if (hw_wb->ops.setup_crop && phys_enc->in_clone_mode) {
  336. wb_cfg->crop.x = wb_cfg->roi.x;
  337. wb_cfg->crop.y = wb_cfg->roi.y;
  338. if (cstate->user_roi_list.num_rects) {
  339. sde_kms_rect_merge_rectangles(&cstate->user_roi_list, &pu_roi);
  340. if ((wb_cfg->roi.w != pu_roi.w) || (wb_cfg->roi.h != pu_roi.h)) {
  341. /* offset cropping region to PU region */
  342. wb_cfg->crop.x = wb_cfg->crop.x - pu_roi.x;
  343. wb_cfg->crop.y = wb_cfg->crop.y - pu_roi.y;
  344. hw_wb->ops.setup_crop(hw_wb, wb_cfg, true);
  345. }
  346. } else if ((wb_cfg->roi.w != wb_cfg->dest.width) ||
  347. (wb_cfg->roi.h != wb_cfg->dest.height)) {
  348. hw_wb->ops.setup_crop(hw_wb, wb_cfg, true);
  349. } else {
  350. hw_wb->ops.setup_crop(hw_wb, wb_cfg, false);
  351. }
  352. }
  353. if ((wb_cfg->dest.format->fetch_planes == SDE_PLANE_PLANAR) &&
  354. (wb_cfg->dest.format->element[0] == C1_B_Cb))
  355. swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);
  356. SDE_DEBUG("[fb_offset:%8.8x,%8.8x,%8.8x,%8.8x]\n",
  357. wb_cfg->dest.plane_addr[0],
  358. wb_cfg->dest.plane_addr[1],
  359. wb_cfg->dest.plane_addr[2],
  360. wb_cfg->dest.plane_addr[3]);
  361. SDE_DEBUG("[fb_stride:%8.8x,%8.8x,%8.8x,%8.8x]\n",
  362. wb_cfg->dest.plane_pitch[0],
  363. wb_cfg->dest.plane_pitch[1],
  364. wb_cfg->dest.plane_pitch[2],
  365. wb_cfg->dest.plane_pitch[3]);
  366. if (hw_wb->ops.setup_roi)
  367. hw_wb->ops.setup_roi(hw_wb, wb_cfg);
  368. if (hw_wb->ops.setup_outformat)
  369. hw_wb->ops.setup_outformat(hw_wb, wb_cfg);
  370. if (hw_wb->ops.setup_cdp) {
  371. memset(cdp_cfg, 0, sizeof(struct sde_hw_wb_cdp_cfg));
  372. cdp_cfg->enable = phys_enc->sde_kms->catalog->perf.cdp_cfg
  373. [SDE_PERF_CDP_USAGE_NRT].wr_enable;
  374. cdp_cfg->ubwc_meta_enable =
  375. SDE_FORMAT_IS_UBWC(wb_cfg->dest.format);
  376. cdp_cfg->tile_amortize_enable =
  377. SDE_FORMAT_IS_UBWC(wb_cfg->dest.format) ||
  378. SDE_FORMAT_IS_TILE(wb_cfg->dest.format);
  379. cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;
  380. hw_wb->ops.setup_cdp(hw_wb, cdp_cfg);
  381. }
  382. if (hw_wb->ops.setup_outaddress) {
  383. SDE_EVT32(hw_wb->idx,
  384. wb_cfg->dest.width,
  385. wb_cfg->dest.height,
  386. wb_cfg->dest.plane_addr[0],
  387. wb_cfg->dest.plane_size[0],
  388. wb_cfg->dest.plane_addr[1],
  389. wb_cfg->dest.plane_size[1],
  390. wb_cfg->dest.plane_addr[2],
  391. wb_cfg->dest.plane_size[2],
  392. wb_cfg->dest.plane_addr[3],
  393. wb_cfg->dest.plane_size[3]);
  394. hw_wb->ops.setup_outaddress(hw_wb, wb_cfg);
  395. }
  396. }
  397. static void _sde_encoder_phys_wb_setup_cwb(struct sde_encoder_phys *phys_enc,
  398. bool enable)
  399. {
  400. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  401. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  402. struct sde_hw_ctl *hw_ctl = phys_enc->hw_ctl;
  403. struct sde_crtc *crtc = to_sde_crtc(wb_enc->crtc);
  404. struct sde_hw_pingpong *hw_pp = phys_enc->hw_pp;
  405. bool need_merge = (crtc->num_mixers > 1);
  406. int i = 0;
  407. if (!phys_enc->in_clone_mode) {
  408. SDE_DEBUG("not in CWB mode. early return\n");
  409. return;
  410. }
  411. if (!hw_pp || !hw_ctl || !hw_wb || hw_pp->idx >= PINGPONG_MAX) {
  412. SDE_ERROR("invalid hw resources - return\n");
  413. return;
  414. }
  415. hw_ctl = crtc->mixers[0].hw_ctl;
  416. if (hw_ctl && hw_ctl->ops.setup_intf_cfg_v1 &&
  417. (test_bit(SDE_WB_CWB_CTRL, &hw_wb->caps->features) ||
  418. test_bit(SDE_WB_DCWB_CTRL, &hw_wb->caps->features))) {
  419. struct sde_hw_intf_cfg_v1 intf_cfg = { 0, };
  420. for (i = 0; i < crtc->num_mixers; i++)
  421. intf_cfg.cwb[intf_cfg.cwb_count++] = (enum sde_cwb)
  422. (test_bit(SDE_WB_DCWB_CTRL, &hw_wb->caps->features) ?
  423. ((hw_pp->idx % 2) + i) : (hw_pp->idx + i));
  424. if (hw_pp->merge_3d && (intf_cfg.merge_3d_count <
  425. MAX_MERGE_3D_PER_CTL_V1) && need_merge)
  426. intf_cfg.merge_3d[intf_cfg.merge_3d_count++] =
  427. hw_pp->merge_3d->idx;
  428. if (hw_pp->ops.setup_3d_mode)
  429. hw_pp->ops.setup_3d_mode(hw_pp, (enable && need_merge) ?
  430. BLEND_3D_H_ROW_INT : 0);
  431. if ((hw_wb->ops.bind_pingpong_blk) &&
  432. test_bit(SDE_WB_CWB_CTRL, &hw_wb->caps->features))
  433. hw_wb->ops.bind_pingpong_blk(hw_wb, enable, hw_pp->idx);
  434. if ((hw_wb->ops.bind_dcwb_pp_blk) &&
  435. test_bit(SDE_WB_DCWB_CTRL, &hw_wb->caps->features))
  436. hw_wb->ops.bind_dcwb_pp_blk(hw_wb, enable, hw_pp->idx);
  437. if (hw_ctl->ops.update_intf_cfg) {
  438. hw_ctl->ops.update_intf_cfg(hw_ctl, &intf_cfg, enable);
  439. SDE_DEBUG("in CWB/DCWB mode on CTL_%d PP-%d merge3d:%d\n",
  440. hw_ctl->idx - CTL_0,
  441. hw_pp->idx - PINGPONG_0,
  442. hw_pp->merge_3d ?
  443. hw_pp->merge_3d->idx - MERGE_3D_0 : -1);
  444. }
  445. } else {
  446. struct sde_hw_intf_cfg *intf_cfg = &phys_enc->intf_cfg;
  447. memset(intf_cfg, 0, sizeof(struct sde_hw_intf_cfg));
  448. intf_cfg->intf = SDE_NONE;
  449. intf_cfg->wb = hw_wb->idx;
  450. if (hw_ctl && hw_ctl->ops.update_wb_cfg) {
  451. hw_ctl->ops.update_wb_cfg(hw_ctl, intf_cfg, enable);
  452. SDE_DEBUG("in CWB/DCWB mode adding WB for CTL_%d\n",
  453. hw_ctl->idx - CTL_0);
  454. }
  455. }
  456. }
  457. /**
  458. * sde_encoder_phys_wb_setup_cdp - setup chroma down prefetch block
  459. * @phys_enc: Pointer to physical encoder
  460. */
  461. static void sde_encoder_phys_wb_setup_cdp(struct sde_encoder_phys *phys_enc,
  462. const struct sde_format *format)
  463. {
  464. struct sde_encoder_phys_wb *wb_enc;
  465. struct sde_hw_wb *hw_wb;
  466. struct sde_hw_cdm *hw_cdm;
  467. struct sde_hw_ctl *ctl;
  468. const int num_wb = 1;
  469. if (!phys_enc) {
  470. SDE_ERROR("invalid encoder\n");
  471. return;
  472. }
  473. if (phys_enc->in_clone_mode) {
  474. SDE_DEBUG("in CWB mode. early return\n");
  475. return;
  476. }
  477. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  478. hw_wb = wb_enc->hw_wb;
  479. hw_cdm = phys_enc->hw_cdm;
  480. ctl = phys_enc->hw_ctl;
  481. if (test_bit(SDE_CTL_ACTIVE_CFG, &ctl->caps->features) &&
  482. (phys_enc->hw_ctl &&
  483. phys_enc->hw_ctl->ops.setup_intf_cfg_v1)) {
  484. struct sde_hw_intf_cfg_v1 *intf_cfg_v1 = &phys_enc->intf_cfg_v1;
  485. struct sde_hw_pingpong *hw_pp = phys_enc->hw_pp;
  486. enum sde_3d_blend_mode mode_3d;
  487. memset(intf_cfg_v1, 0, sizeof(struct sde_hw_intf_cfg_v1));
  488. mode_3d = sde_encoder_helper_get_3d_blend_mode(phys_enc);
  489. intf_cfg_v1->intf_count = SDE_NONE;
  490. intf_cfg_v1->wb_count = num_wb;
  491. intf_cfg_v1->wb[0] = hw_wb->idx;
  492. if (SDE_FORMAT_IS_YUV(format)) {
  493. intf_cfg_v1->cdm_count = num_wb;
  494. intf_cfg_v1->cdm[0] = hw_cdm->idx;
  495. }
  496. if (mode_3d && hw_pp && hw_pp->merge_3d &&
  497. intf_cfg_v1->merge_3d_count < MAX_MERGE_3D_PER_CTL_V1)
  498. intf_cfg_v1->merge_3d[intf_cfg_v1->merge_3d_count++] =
  499. hw_pp->merge_3d->idx;
  500. if (hw_pp && hw_pp->ops.setup_3d_mode)
  501. hw_pp->ops.setup_3d_mode(hw_pp, mode_3d);
  502. /* setup which pp blk will connect to this wb */
  503. if (hw_pp && hw_wb->ops.bind_pingpong_blk)
  504. hw_wb->ops.bind_pingpong_blk(hw_wb, true,
  505. hw_pp->idx);
  506. phys_enc->hw_ctl->ops.setup_intf_cfg_v1(phys_enc->hw_ctl,
  507. intf_cfg_v1);
  508. } else if (phys_enc->hw_ctl && phys_enc->hw_ctl->ops.setup_intf_cfg) {
  509. struct sde_hw_intf_cfg *intf_cfg = &phys_enc->intf_cfg;
  510. memset(intf_cfg, 0, sizeof(struct sde_hw_intf_cfg));
  511. intf_cfg->intf = SDE_NONE;
  512. intf_cfg->wb = hw_wb->idx;
  513. intf_cfg->mode_3d =
  514. sde_encoder_helper_get_3d_blend_mode(phys_enc);
  515. phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl,
  516. intf_cfg);
  517. }
  518. }
  519. static void _sde_enc_phys_wb_detect_cwb(struct sde_encoder_phys *phys_enc,
  520. struct drm_crtc_state *crtc_state)
  521. {
  522. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  523. const struct sde_wb_cfg *wb_cfg = wb_enc->hw_wb->caps;
  524. u32 encoder_mask = 0;
  525. /* Check if WB has CWB support */
  526. if ((wb_cfg->features & BIT(SDE_WB_HAS_CWB))
  527. || (wb_cfg->features & BIT(SDE_WB_HAS_DCWB))) {
  528. encoder_mask = crtc_state->encoder_mask;
  529. encoder_mask &= ~drm_encoder_mask(phys_enc->parent);
  530. }
  531. phys_enc->in_clone_mode = encoder_mask ? true : false;
  532. SDE_DEBUG("detect CWB(OR)DCWB - status:%d\n", phys_enc->in_clone_mode);
  533. }
  534. static int _sde_enc_phys_wb_validate_cwb(struct sde_encoder_phys *phys_enc,
  535. struct drm_crtc_state *crtc_state,
  536. struct drm_connector_state *conn_state)
  537. {
  538. struct drm_framebuffer *fb;
  539. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc_state);
  540. const struct drm_display_mode *mode = &crtc_state->mode;
  541. struct sde_rect wb_roi = {0,};
  542. struct sde_rect pu_roi = {0,};
  543. int out_width = 0, out_height = 0;
  544. int ds_srcw = 0, ds_srch = 0, ds_outw = 0, ds_outh = 0;
  545. const struct sde_format *fmt;
  546. int data_pt;
  547. int ds_in_use = false;
  548. int i = 0;
  549. int ret = 0;
  550. fb = sde_wb_connector_state_get_output_fb(conn_state);
  551. if (!fb) {
  552. SDE_DEBUG("no output framebuffer\n");
  553. return 0;
  554. }
  555. fmt = sde_get_sde_format_ext(fb->format->format, fb->modifier);
  556. if (!fmt) {
  557. SDE_ERROR("unsupported output pixel format:%x\n", fb->format->format);
  558. return -EINVAL;
  559. }
  560. ret = sde_wb_connector_state_get_output_roi(conn_state, &wb_roi);
  561. if (ret) {
  562. SDE_ERROR("failed to get roi %d\n", ret);
  563. return ret;
  564. }
  565. if (!wb_roi.w || !wb_roi.h) {
  566. SDE_ERROR("cwb roi is not set wxh:%dx%d\n", wb_roi.w, wb_roi.h);
  567. return -EINVAL;
  568. }
  569. data_pt = sde_crtc_get_property(cstate, CRTC_PROP_CAPTURE_OUTPUT);
  570. /* compute cumulative ds output dimensions if in use */
  571. for (i = 0; i < cstate->num_ds; i++) {
  572. if (cstate->ds_cfg[i].scl3_cfg.enable) {
  573. ds_in_use = true;
  574. ds_outw += cstate->ds_cfg[i].scl3_cfg.dst_width;
  575. ds_outh = cstate->ds_cfg[i].scl3_cfg.dst_height;
  576. ds_srcw += cstate->ds_cfg[i].lm_width;
  577. ds_srch = cstate->ds_cfg[i].lm_height;
  578. }
  579. }
  580. if ((ds_in_use && (!ds_outw || !ds_outh || !ds_srcw || !ds_srch))) {
  581. SDE_ERROR("invalid ds cfg src:%dx%d dst:%dx%d\n",
  582. ds_srcw, ds_srch, ds_outw, ds_outh);
  583. return -EINVAL;
  584. }
  585. /* 1) No DS case: same restrictions for LM & DSSPP tap point
  586. * a) wb-roi should be inside FB
  587. * b) mode resolution & wb-roi should be same
  588. * 2) With DS case: restrictions would change based on tap point
  589. * 2.1) LM Tap Point:
  590. * a) wb-roi should be inside FB
  591. * b) wb-roi should be same as crtc-LM bounds
  592. * 2.2) DSPP Tap point: same as No DS case
  593. * a) wb-roi should be inside FB
  594. * b) mode resolution & wb-roi should be same
  595. * 3) Partial Update case: additional stride check
  596. * a) cwb roi should be inside PU region or FB
  597. * b) cropping is only allowed for fully sampled data
  598. * c) add check for stride and QOS setting by 256B
  599. */
  600. if (ds_in_use && data_pt == CAPTURE_DSPP_OUT) {
  601. out_width = ds_outw;
  602. out_height = ds_outh;
  603. } else if (ds_in_use) { /* LM tap point */
  604. out_width = ds_srcw;
  605. out_height = ds_srch;
  606. } else {
  607. out_width = mode->hdisplay;
  608. out_height = mode->vdisplay;
  609. }
  610. if (SDE_FORMAT_IS_YUV(fmt) && ((wb_roi.w != out_width) || (wb_roi.h != out_height))) {
  611. SDE_ERROR("invalid wb roi[%dx%d] with ds_use:%d out[%dx%d] fmt:%x\n",
  612. wb_roi.w, wb_roi.h, ds_in_use, out_width, out_height,
  613. fmt->base.pixel_format);
  614. return -EINVAL;
  615. }
  616. if ((wb_roi.w > out_width) || (wb_roi.h > out_height)) {
  617. SDE_ERROR("invalid wb roi[%dx%d] with ds_use:%d out[%dx%d]\n",
  618. wb_roi.w, wb_roi.h, ds_in_use, out_width, out_height);
  619. return -EINVAL;
  620. }
  621. if (((wb_roi.w < out_width) || (wb_roi.h < out_height)) &&
  622. (wb_roi.w * wb_roi.h * fmt->bpp) % 256) {
  623. SDE_ERROR("invalid stride w = %d h = %d bpp =%d out_width = %d, out_height = %d\n",
  624. wb_roi.w, wb_roi.h, fmt->bpp, out_width, out_height);
  625. return -EINVAL;
  626. }
  627. if (((wb_roi.x + wb_roi.w) > fb->width) ||
  628. ((wb_roi.y + wb_roi.h) > fb->height)) {
  629. SDE_ERROR("invalid wb roi[%d,%d,%d,%d] fb[%dx%d]\n",
  630. wb_roi.x, wb_roi.y, wb_roi.w, wb_roi.h,
  631. fb->width, fb->height);
  632. return -EINVAL;
  633. }
  634. /* validate wb roi against pu rect */
  635. if (cstate->user_roi_list.num_rects) {
  636. sde_kms_rect_merge_rectangles(&cstate->user_roi_list, &pu_roi);
  637. if (wb_roi.w > pu_roi.w || wb_roi.h > pu_roi.h) {
  638. SDE_ERROR("invalid wb roi with pu [%dx%d vs %dx%d]\n",
  639. wb_roi.w, wb_roi.h, pu_roi.w, pu_roi.h);
  640. return -EINVAL;
  641. }
  642. }
  643. return ret;
  644. }
  645. /**
  646. * sde_encoder_phys_wb_atomic_check - verify and fixup given atomic states
  647. * @phys_enc: Pointer to physical encoder
  648. * @crtc_state: Pointer to CRTC atomic state
  649. * @conn_state: Pointer to connector atomic state
  650. */
  651. static int sde_encoder_phys_wb_atomic_check(
  652. struct sde_encoder_phys *phys_enc,
  653. struct drm_crtc_state *crtc_state,
  654. struct drm_connector_state *conn_state)
  655. {
  656. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  657. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  658. const struct sde_wb_cfg *wb_cfg = hw_wb->caps;
  659. struct drm_framebuffer *fb;
  660. const struct sde_format *fmt;
  661. struct sde_rect wb_roi;
  662. const struct drm_display_mode *mode = &crtc_state->mode;
  663. int rc;
  664. bool clone_mode_curr = false;
  665. SDE_DEBUG("[atomic_check:%d,\"%s\",%d,%d]\n",
  666. hw_wb->idx - WB_0, mode->name,
  667. mode->hdisplay, mode->vdisplay);
  668. if (!conn_state || !conn_state->connector) {
  669. SDE_ERROR("invalid connector state\n");
  670. return -EINVAL;
  671. } else if (conn_state->connector->status !=
  672. connector_status_connected) {
  673. SDE_ERROR("connector not connected %d\n",
  674. conn_state->connector->status);
  675. return -EINVAL;
  676. }
  677. clone_mode_curr = phys_enc->in_clone_mode;
  678. _sde_enc_phys_wb_detect_cwb(phys_enc, crtc_state);
  679. if (clone_mode_curr && !phys_enc->in_clone_mode) {
  680. SDE_ERROR("WB commit before CWB disable\n");
  681. return -EINVAL;
  682. }
  683. memset(&wb_roi, 0, sizeof(struct sde_rect));
  684. rc = sde_wb_connector_state_get_output_roi(conn_state, &wb_roi);
  685. if (rc) {
  686. SDE_ERROR("failed to get roi %d\n", rc);
  687. return rc;
  688. }
  689. SDE_DEBUG("[roi:%u,%u,%u,%u]\n", wb_roi.x, wb_roi.y,
  690. wb_roi.w, wb_roi.h);
  691. /* bypass check if commit with no framebuffer */
  692. fb = sde_wb_connector_state_get_output_fb(conn_state);
  693. if (!fb) {
  694. SDE_DEBUG("no output framebuffer\n");
  695. return 0;
  696. }
  697. SDE_DEBUG("[fb_id:%u][fb:%u,%u]\n", fb->base.id,
  698. fb->width, fb->height);
  699. fmt = sde_get_sde_format_ext(fb->format->format, fb->modifier);
  700. if (!fmt) {
  701. SDE_ERROR("unsupported output pixel format:%x\n",
  702. fb->format->format);
  703. return -EINVAL;
  704. }
  705. SDE_DEBUG("[fb_fmt:%x,%llx]\n", fb->format->format,
  706. fb->modifier);
  707. if (SDE_FORMAT_IS_YUV(fmt) &&
  708. !(wb_cfg->features & BIT(SDE_WB_YUV_CONFIG))) {
  709. SDE_ERROR("invalid output format %x\n", fmt->base.pixel_format);
  710. return -EINVAL;
  711. }
  712. if (SDE_FORMAT_IS_UBWC(fmt) &&
  713. !(wb_cfg->features & BIT(SDE_WB_UBWC))) {
  714. SDE_ERROR("invalid output format %x\n", fmt->base.pixel_format);
  715. return -EINVAL;
  716. }
  717. if (SDE_FORMAT_IS_YUV(fmt) != !!phys_enc->hw_cdm)
  718. crtc_state->mode_changed = true;
  719. /* if in clone mode, return after cwb validation */
  720. if (phys_enc->in_clone_mode) {
  721. rc = _sde_enc_phys_wb_validate_cwb(phys_enc, crtc_state,
  722. conn_state);
  723. if (rc)
  724. SDE_ERROR("failed in cwb validation %d\n", rc);
  725. return rc;
  726. }
  727. if (wb_roi.w && wb_roi.h) {
  728. if (wb_roi.w != mode->hdisplay) {
  729. SDE_ERROR("invalid roi w=%d, mode w=%d\n", wb_roi.w,
  730. mode->hdisplay);
  731. return -EINVAL;
  732. } else if (wb_roi.h != mode->vdisplay) {
  733. SDE_ERROR("invalid roi h=%d, mode h=%d\n", wb_roi.h,
  734. mode->vdisplay);
  735. return -EINVAL;
  736. } else if (wb_roi.x + wb_roi.w > fb->width) {
  737. SDE_ERROR("invalid roi x=%d, w=%d, fb w=%d\n",
  738. wb_roi.x, wb_roi.w, fb->width);
  739. return -EINVAL;
  740. } else if (wb_roi.y + wb_roi.h > fb->height) {
  741. SDE_ERROR("invalid roi y=%d, h=%d, fb h=%d\n",
  742. wb_roi.y, wb_roi.h, fb->height);
  743. return -EINVAL;
  744. } else if (wb_roi.w > SDE_WB_MAX_LINEWIDTH(fmt, wb_cfg)) {
  745. SDE_ERROR("invalid roi ubwc=%d w=%d, maxlinewidth=%u\n",
  746. SDE_FORMAT_IS_UBWC(fmt), wb_roi.w,
  747. SDE_WB_MAX_LINEWIDTH(fmt, wb_cfg));
  748. return -EINVAL;
  749. }
  750. } else {
  751. if (wb_roi.x || wb_roi.y) {
  752. SDE_ERROR("invalid roi x=%d, y=%d\n",
  753. wb_roi.x, wb_roi.y);
  754. return -EINVAL;
  755. } else if (fb->width != mode->hdisplay) {
  756. SDE_ERROR("invalid fb w=%d, mode w=%d\n", fb->width,
  757. mode->hdisplay);
  758. return -EINVAL;
  759. } else if (fb->height != mode->vdisplay) {
  760. SDE_ERROR("invalid fb h=%d, mode h=%d\n", fb->height,
  761. mode->vdisplay);
  762. return -EINVAL;
  763. } else if (fb->width > SDE_WB_MAX_LINEWIDTH(fmt, wb_cfg)) {
  764. SDE_ERROR("invalid fb ubwc=%d w=%d, maxlinewidth=%u\n",
  765. SDE_FORMAT_IS_UBWC(fmt), fb->width,
  766. SDE_WB_MAX_LINEWIDTH(fmt, wb_cfg));
  767. return -EINVAL;
  768. }
  769. }
  770. return rc;
  771. }
  772. static void _sde_encoder_phys_wb_update_cwb_flush(
  773. struct sde_encoder_phys *phys_enc, bool enable)
  774. {
  775. struct sde_encoder_phys_wb *wb_enc;
  776. struct sde_hw_wb *hw_wb;
  777. struct sde_hw_ctl *hw_ctl;
  778. struct sde_hw_cdm *hw_cdm;
  779. struct sde_hw_pingpong *hw_pp;
  780. struct sde_crtc *crtc;
  781. struct sde_crtc_state *crtc_state;
  782. int i = 0;
  783. int cwb_capture_mode = 0;
  784. enum sde_cwb cwb_idx = 0;
  785. enum sde_dcwb dcwb_idx = 0;
  786. enum sde_cwb src_pp_idx = 0;
  787. bool dspp_out = false;
  788. bool need_merge = false;
  789. if (!phys_enc->in_clone_mode) {
  790. SDE_DEBUG("not in CWB mode. early return\n");
  791. return;
  792. }
  793. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  794. crtc = to_sde_crtc(wb_enc->crtc);
  795. crtc_state = to_sde_crtc_state(wb_enc->crtc->state);
  796. cwb_capture_mode = sde_crtc_get_property(crtc_state,
  797. CRTC_PROP_CAPTURE_OUTPUT);
  798. hw_pp = phys_enc->hw_pp;
  799. hw_wb = wb_enc->hw_wb;
  800. hw_cdm = phys_enc->hw_cdm;
  801. /* In CWB mode, program actual source master sde_hw_ctl from crtc */
  802. hw_ctl = crtc->mixers[0].hw_ctl;
  803. if (!hw_ctl || !hw_wb || !hw_pp) {
  804. SDE_ERROR("[wb] HW resource not available for CWB\n");
  805. return;
  806. }
  807. /* treating LM idx of primary display ctl path as source ping-pong idx*/
  808. src_pp_idx = (enum sde_cwb)crtc->mixers[0].hw_lm->idx;
  809. cwb_idx = (enum sde_cwb)hw_pp->idx;
  810. dspp_out = (cwb_capture_mode == CAPTURE_DSPP_OUT);
  811. need_merge = (crtc->num_mixers > 1) ? true : false;
  812. if (test_bit(SDE_WB_DCWB_CTRL, &hw_wb->caps->features)) {
  813. dcwb_idx = (enum sde_dcwb) ((hw_pp->idx % 2) + i);
  814. if ((dcwb_idx + crtc->num_mixers) > DCWB_MAX) {
  815. SDE_ERROR("invalid hw config for DCWB. dcwb_idx=%d, num_mixers=%d\n",
  816. dcwb_idx, crtc->num_mixers);
  817. return;
  818. }
  819. } else {
  820. if (src_pp_idx > CWB_0 || ((cwb_idx + crtc->num_mixers) > CWB_MAX)) {
  821. SDE_ERROR("invalid hw config for CWB. pp_idx-%d, cwb_idx=%d, num_mixers=%d\n",
  822. src_pp_idx, dcwb_idx, crtc->num_mixers);
  823. return;
  824. }
  825. }
  826. if (hw_ctl->ops.update_bitmask)
  827. hw_ctl->ops.update_bitmask(hw_ctl, SDE_HW_FLUSH_WB,
  828. hw_wb->idx, 1);
  829. if (hw_ctl->ops.update_bitmask && hw_cdm)
  830. hw_ctl->ops.update_bitmask(hw_ctl, SDE_HW_FLUSH_CDM,
  831. hw_cdm->idx, 1);
  832. if (test_bit(SDE_WB_CWB_CTRL, &hw_wb->caps->features) ||
  833. test_bit(SDE_WB_DCWB_CTRL, &hw_wb->caps->features)) {
  834. for (i = 0; i < crtc->num_mixers; i++) {
  835. src_pp_idx = (enum sde_cwb) (src_pp_idx + i);
  836. if (test_bit(SDE_WB_DCWB_CTRL, &hw_wb->caps->features)) {
  837. dcwb_idx = (enum sde_dcwb) ((hw_pp->idx % 2) + i);
  838. if (hw_wb->ops.program_dcwb_ctrl)
  839. hw_wb->ops.program_dcwb_ctrl(hw_wb, dcwb_idx,
  840. src_pp_idx, cwb_capture_mode,
  841. enable);
  842. if (hw_ctl->ops.update_bitmask)
  843. hw_ctl->ops.update_bitmask(hw_ctl,
  844. SDE_HW_FLUSH_CWB, dcwb_idx, 1);
  845. } else if (test_bit(SDE_WB_CWB_CTRL, &hw_wb->caps->features)) {
  846. cwb_idx = (enum sde_cwb) (hw_pp->idx + i);
  847. if (hw_wb->ops.program_cwb_ctrl)
  848. hw_wb->ops.program_cwb_ctrl(hw_wb, cwb_idx,
  849. src_pp_idx, dspp_out, enable);
  850. if (hw_ctl->ops.update_bitmask)
  851. hw_ctl->ops.update_bitmask(hw_ctl,
  852. SDE_HW_FLUSH_CWB, cwb_idx, 1);
  853. }
  854. }
  855. if (need_merge && hw_ctl->ops.update_bitmask
  856. && hw_pp && hw_pp->merge_3d)
  857. hw_ctl->ops.update_bitmask(hw_ctl,
  858. SDE_HW_FLUSH_MERGE_3D,
  859. hw_pp->merge_3d->idx, 1);
  860. } else {
  861. phys_enc->hw_mdptop->ops.set_cwb_ppb_cntl(phys_enc->hw_mdptop,
  862. need_merge, dspp_out);
  863. }
  864. }
  865. /**
  866. * _sde_encoder_phys_wb_update_flush - flush hardware update
  867. * @phys_enc: Pointer to physical encoder
  868. */
  869. static void _sde_encoder_phys_wb_update_flush(struct sde_encoder_phys *phys_enc)
  870. {
  871. struct sde_encoder_phys_wb *wb_enc;
  872. struct sde_hw_wb *hw_wb;
  873. struct sde_hw_ctl *hw_ctl;
  874. struct sde_hw_cdm *hw_cdm;
  875. struct sde_hw_pingpong *hw_pp;
  876. struct sde_ctl_flush_cfg pending_flush = {0,};
  877. if (!phys_enc)
  878. return;
  879. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  880. hw_wb = wb_enc->hw_wb;
  881. hw_cdm = phys_enc->hw_cdm;
  882. hw_pp = phys_enc->hw_pp;
  883. hw_ctl = phys_enc->hw_ctl;
  884. SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
  885. if (phys_enc->in_clone_mode) {
  886. SDE_DEBUG("in CWB mode. early return\n");
  887. return;
  888. }
  889. if (!hw_ctl) {
  890. SDE_DEBUG("[wb:%d] no ctl assigned\n", hw_wb->idx - WB_0);
  891. return;
  892. }
  893. if (hw_ctl->ops.update_bitmask)
  894. hw_ctl->ops.update_bitmask(hw_ctl, SDE_HW_FLUSH_WB,
  895. hw_wb->idx, 1);
  896. if (hw_ctl->ops.update_bitmask && hw_cdm)
  897. hw_ctl->ops.update_bitmask(hw_ctl, SDE_HW_FLUSH_CDM,
  898. hw_cdm->idx, 1);
  899. if (hw_ctl->ops.update_bitmask && hw_pp && hw_pp->merge_3d)
  900. hw_ctl->ops.update_bitmask(hw_ctl, SDE_HW_FLUSH_MERGE_3D,
  901. hw_pp->merge_3d->idx, 1);
  902. if (hw_ctl->ops.get_pending_flush)
  903. hw_ctl->ops.get_pending_flush(hw_ctl,
  904. &pending_flush);
  905. SDE_DEBUG("Pending flush mask for CTL_%d is 0x%x, WB %d\n",
  906. hw_ctl->idx - CTL_0, pending_flush.pending_flush_mask,
  907. hw_wb->idx - WB_0);
  908. }
  909. /**
  910. * sde_encoder_phys_wb_setup - setup writeback encoder
  911. * @phys_enc: Pointer to physical encoder
  912. */
  913. static void sde_encoder_phys_wb_setup(
  914. struct sde_encoder_phys *phys_enc)
  915. {
  916. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  917. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  918. struct drm_display_mode mode = phys_enc->cached_mode;
  919. struct drm_framebuffer *fb;
  920. struct sde_rect *wb_roi = &wb_enc->wb_roi;
  921. SDE_DEBUG("[mode_set:%d,\"%s\",%d,%d]\n",
  922. hw_wb->idx - WB_0, mode.name,
  923. mode.hdisplay, mode.vdisplay);
  924. memset(wb_roi, 0, sizeof(struct sde_rect));
  925. /* clear writeback framebuffer - will be updated in setup_fb */
  926. wb_enc->wb_fb = NULL;
  927. wb_enc->wb_aspace = NULL;
  928. if (phys_enc->enable_state == SDE_ENC_DISABLING) {
  929. fb = wb_enc->fb_disable;
  930. wb_roi->w = 0;
  931. wb_roi->h = 0;
  932. } else {
  933. fb = sde_wb_get_output_fb(wb_enc->wb_dev);
  934. sde_wb_get_output_roi(wb_enc->wb_dev, wb_roi);
  935. }
  936. if (!fb) {
  937. SDE_DEBUG("no output framebuffer\n");
  938. return;
  939. }
  940. SDE_DEBUG("[fb_id:%u][fb:%u,%u]\n", fb->base.id,
  941. fb->width, fb->height);
  942. if (wb_roi->w == 0 || wb_roi->h == 0) {
  943. wb_roi->x = 0;
  944. wb_roi->y = 0;
  945. wb_roi->w = fb->width;
  946. wb_roi->h = fb->height;
  947. }
  948. SDE_DEBUG("[roi:%u,%u,%u,%u]\n", wb_roi->x, wb_roi->y,
  949. wb_roi->w, wb_roi->h);
  950. wb_enc->wb_fmt = sde_get_sde_format_ext(fb->format->format,
  951. fb->modifier);
  952. if (!wb_enc->wb_fmt) {
  953. SDE_ERROR("unsupported output pixel format: %d\n",
  954. fb->format->format);
  955. return;
  956. }
  957. SDE_DEBUG("[fb_fmt:%x,%llx]\n", fb->format->format,
  958. fb->modifier);
  959. sde_encoder_phys_wb_set_ot_limit(phys_enc);
  960. sde_encoder_phys_wb_set_qos_remap(phys_enc);
  961. sde_encoder_phys_wb_set_qos(phys_enc);
  962. sde_encoder_phys_setup_cdm(phys_enc, fb, wb_enc->wb_fmt, wb_roi);
  963. sde_encoder_phys_wb_setup_fb(phys_enc, fb, wb_roi);
  964. sde_encoder_phys_wb_setup_cdp(phys_enc, wb_enc->wb_fmt);
  965. _sde_encoder_phys_wb_setup_cwb(phys_enc, true);
  966. }
  967. static void _sde_encoder_phys_wb_frame_done_helper(void *arg, bool frame_error)
  968. {
  969. struct sde_encoder_phys_wb *wb_enc = arg;
  970. struct sde_encoder_phys *phys_enc = &wb_enc->base;
  971. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  972. u32 event = frame_error ? SDE_ENCODER_FRAME_EVENT_ERROR : 0;
  973. SDE_DEBUG("[wb:%d,%u]\n", hw_wb->idx - WB_0, wb_enc->frame_count);
  974. /* don't notify upper layer for internal commit */
  975. if (phys_enc->enable_state == SDE_ENC_DISABLING &&
  976. !phys_enc->in_clone_mode)
  977. goto complete;
  978. if (phys_enc->parent_ops.handle_frame_done &&
  979. atomic_add_unless(&phys_enc->pending_retire_fence_cnt, -1, 0)) {
  980. event |= SDE_ENCODER_FRAME_EVENT_DONE |
  981. SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE;
  982. if (phys_enc->in_clone_mode)
  983. event |= SDE_ENCODER_FRAME_EVENT_CWB_DONE;
  984. else
  985. event |= SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE;
  986. phys_enc->parent_ops.handle_frame_done(phys_enc->parent,
  987. phys_enc, event);
  988. }
  989. if (!phys_enc->in_clone_mode && phys_enc->parent_ops.handle_vblank_virt)
  990. phys_enc->parent_ops.handle_vblank_virt(phys_enc->parent,
  991. phys_enc);
  992. SDE_EVT32_IRQ(DRMID(phys_enc->parent), hw_wb->idx - WB_0, event,
  993. frame_error);
  994. complete:
  995. wake_up_all(&phys_enc->pending_kickoff_wq);
  996. }
  997. /**
  998. * sde_encoder_phys_wb_done_irq - Pingpong overflow interrupt handler for CWB
  999. * @arg: Pointer to writeback encoder
  1000. * @irq_idx: interrupt index
  1001. */
  1002. static void sde_encoder_phys_cwb_ovflow(void *arg, int irq_idx)
  1003. {
  1004. _sde_encoder_phys_wb_frame_done_helper(arg, true);
  1005. }
  1006. /**
  1007. * sde_encoder_phys_wb_done_irq - writeback interrupt handler
  1008. * @arg: Pointer to writeback encoder
  1009. * @irq_idx: interrupt index
  1010. */
  1011. static void sde_encoder_phys_wb_done_irq(void *arg, int irq_idx)
  1012. {
  1013. _sde_encoder_phys_wb_frame_done_helper(arg, false);
  1014. }
  1015. /**
  1016. * sde_encoder_phys_wb_irq_ctrl - irq control of WB
  1017. * @phys: Pointer to physical encoder
  1018. * @enable: indicates enable or disable interrupts
  1019. */
  1020. static void sde_encoder_phys_wb_irq_ctrl(
  1021. struct sde_encoder_phys *phys, bool enable)
  1022. {
  1023. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys);
  1024. const struct sde_wb_cfg *wb_cfg;
  1025. int index = 0, refcount;
  1026. int ret = 0, pp = 0;
  1027. u32 max_num_of_irqs = 0;
  1028. const u32 *irq_table = NULL;
  1029. if (!wb_enc)
  1030. return;
  1031. if (wb_enc->bypass_irqreg)
  1032. return;
  1033. pp = phys->hw_pp->idx - PINGPONG_0;
  1034. if ((pp + CRTC_DUAL_MIXERS_ONLY) >= PINGPONG_MAX) {
  1035. SDE_ERROR("invalid pingpong index for WB or CWB\n");
  1036. return;
  1037. }
  1038. refcount = atomic_read(&phys->wbirq_refcount);
  1039. /*
  1040. * For Dedicated CWB, only one overflow IRQ is used for
  1041. * both the PP_CWB blks. Make sure only one IRQ is registered
  1042. * when D-CWB is enabled.
  1043. */
  1044. wb_cfg = wb_enc->hw_wb->caps;
  1045. if (wb_cfg->features & BIT(SDE_WB_HAS_DCWB)) {
  1046. max_num_of_irqs = 1;
  1047. irq_table = dcwb_irq_tbl;
  1048. } else {
  1049. max_num_of_irqs = CRTC_DUAL_MIXERS_ONLY;
  1050. irq_table = cwb_irq_tbl;
  1051. }
  1052. if (enable && atomic_inc_return(&phys->wbirq_refcount) == 1) {
  1053. sde_encoder_helper_register_irq(phys, INTR_IDX_WB_DONE);
  1054. if (ret)
  1055. atomic_dec_return(&phys->wbirq_refcount);
  1056. for (index = 0; index < max_num_of_irqs; index++)
  1057. if (irq_table[index + pp] != SDE_NONE)
  1058. sde_encoder_helper_register_irq(phys,
  1059. irq_table[index + pp]);
  1060. } else if (!enable &&
  1061. atomic_dec_return(&phys->wbirq_refcount) == 0) {
  1062. sde_encoder_helper_unregister_irq(phys, INTR_IDX_WB_DONE);
  1063. if (ret)
  1064. atomic_inc_return(&phys->wbirq_refcount);
  1065. for (index = 0; index < max_num_of_irqs; index++)
  1066. if (irq_table[index + pp] != SDE_NONE)
  1067. sde_encoder_helper_unregister_irq(phys,
  1068. irq_table[index + pp]);
  1069. }
  1070. }
  1071. /**
  1072. * sde_encoder_phys_wb_mode_set - set display mode
  1073. * @phys_enc: Pointer to physical encoder
  1074. * @mode: Pointer to requested display mode
  1075. * @adj_mode: Pointer to adjusted display mode
  1076. */
  1077. static void sde_encoder_phys_wb_mode_set(
  1078. struct sde_encoder_phys *phys_enc,
  1079. struct drm_display_mode *mode,
  1080. struct drm_display_mode *adj_mode)
  1081. {
  1082. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1083. struct sde_rm *rm = &phys_enc->sde_kms->rm;
  1084. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  1085. struct sde_rm_hw_iter iter;
  1086. int i, instance;
  1087. phys_enc->cached_mode = *adj_mode;
  1088. instance = phys_enc->split_role == ENC_ROLE_SLAVE ? 1 : 0;
  1089. SDE_DEBUG("[mode_set_cache:%d,\"%s\",%d,%d]\n",
  1090. hw_wb->idx - WB_0, mode->name,
  1091. mode->hdisplay, mode->vdisplay);
  1092. phys_enc->hw_ctl = NULL;
  1093. phys_enc->hw_cdm = NULL;
  1094. /* Retrieve previously allocated HW Resources. CTL shouldn't fail */
  1095. sde_rm_init_hw_iter(&iter, phys_enc->parent->base.id, SDE_HW_BLK_CTL);
  1096. for (i = 0; i <= instance; i++) {
  1097. sde_rm_get_hw(rm, &iter);
  1098. if (i == instance)
  1099. phys_enc->hw_ctl = (struct sde_hw_ctl *) iter.hw;
  1100. }
  1101. if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) {
  1102. SDE_ERROR("failed init ctl: %ld\n",
  1103. (!phys_enc->hw_ctl) ?
  1104. -EINVAL : PTR_ERR(phys_enc->hw_ctl));
  1105. phys_enc->hw_ctl = NULL;
  1106. return;
  1107. }
  1108. /* CDM is optional */
  1109. sde_rm_init_hw_iter(&iter, phys_enc->parent->base.id, SDE_HW_BLK_CDM);
  1110. for (i = 0; i <= instance; i++) {
  1111. sde_rm_get_hw(rm, &iter);
  1112. if (i == instance)
  1113. phys_enc->hw_cdm = (struct sde_hw_cdm *) iter.hw;
  1114. }
  1115. if (IS_ERR(phys_enc->hw_cdm)) {
  1116. SDE_ERROR("CDM required but not allocated: %ld\n",
  1117. PTR_ERR(phys_enc->hw_cdm));
  1118. phys_enc->hw_cdm = NULL;
  1119. }
  1120. }
  1121. static int sde_encoder_phys_wb_frame_timeout(struct sde_encoder_phys *phys_enc)
  1122. {
  1123. u32 event = 0;
  1124. while (atomic_add_unless(&phys_enc->pending_retire_fence_cnt, -1, 0) &&
  1125. phys_enc->parent_ops.handle_frame_done) {
  1126. event = SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE
  1127. | SDE_ENCODER_FRAME_EVENT_ERROR;
  1128. if (phys_enc->in_clone_mode)
  1129. event |= SDE_ENCODER_FRAME_EVENT_CWB_DONE;
  1130. else
  1131. event |= SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE;
  1132. phys_enc->parent_ops.handle_frame_done(
  1133. phys_enc->parent, phys_enc, event);
  1134. SDE_EVT32(DRMID(phys_enc->parent), event,
  1135. atomic_read(&phys_enc->pending_retire_fence_cnt));
  1136. }
  1137. return event;
  1138. }
  1139. static bool _sde_encoder_phys_wb_is_idle(
  1140. struct sde_encoder_phys *phys_enc)
  1141. {
  1142. bool ret = false;
  1143. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1144. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  1145. struct sde_vbif_get_xin_status_params xin_status = {0};
  1146. xin_status.vbif_idx = hw_wb->caps->vbif_idx;
  1147. xin_status.xin_id = hw_wb->caps->xin_id;
  1148. xin_status.clk_ctrl = hw_wb->caps->clk_ctrl;
  1149. if (sde_vbif_get_xin_status(phys_enc->sde_kms, &xin_status)) {
  1150. _sde_encoder_phys_wb_frame_done_helper(wb_enc, false);
  1151. ret = true;
  1152. }
  1153. return ret;
  1154. }
  1155. static void _sde_encoder_phys_wb_reset_state(
  1156. struct sde_encoder_phys *phys_enc)
  1157. {
  1158. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1159. /*
  1160. * frame count and kickoff count are only used for debug purpose. Frame
  1161. * count can be more than kickoff count at the end of disable call due
  1162. * to extra frame_done wait. It does not cause any issue because
  1163. * frame_done wait is based on retire_fence count. Leaving these
  1164. * counters for debugging purpose.
  1165. */
  1166. if (wb_enc->frame_count != wb_enc->kickoff_count) {
  1167. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc),
  1168. wb_enc->kickoff_count, wb_enc->frame_count,
  1169. phys_enc->in_clone_mode);
  1170. wb_enc->frame_count = wb_enc->kickoff_count;
  1171. }
  1172. phys_enc->enable_state = SDE_ENC_DISABLED;
  1173. wb_enc->crtc = NULL;
  1174. phys_enc->hw_cdm = NULL;
  1175. phys_enc->hw_ctl = NULL;
  1176. phys_enc->in_clone_mode = false;
  1177. }
  1178. static int _sde_encoder_phys_wb_wait_for_commit_done(
  1179. struct sde_encoder_phys *phys_enc, bool is_disable)
  1180. {
  1181. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1182. u32 event = 0;
  1183. u64 wb_time = 0;
  1184. int rc = 0;
  1185. struct sde_encoder_wait_info wait_info = {0};
  1186. /* Return EWOULDBLOCK since we know the wait isn't necessary */
  1187. if (phys_enc->enable_state == SDE_ENC_DISABLED) {
  1188. SDE_ERROR("encoder already disabled\n");
  1189. return -EWOULDBLOCK;
  1190. }
  1191. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc), wb_enc->frame_count,
  1192. wb_enc->kickoff_count, !!wb_enc->wb_fb, is_disable,
  1193. phys_enc->in_clone_mode);
  1194. if (!is_disable && phys_enc->in_clone_mode &&
  1195. (atomic_read(&phys_enc->pending_retire_fence_cnt) <= 1))
  1196. goto skip_wait;
  1197. /* signal completion if commit with no framebuffer */
  1198. if (!wb_enc->wb_fb) {
  1199. SDE_DEBUG("no output framebuffer\n");
  1200. _sde_encoder_phys_wb_frame_done_helper(wb_enc, false);
  1201. }
  1202. if (atomic_read(&phys_enc->pending_retire_fence_cnt) > 1)
  1203. wait_info.count_check = 1;
  1204. wait_info.wq = &phys_enc->pending_kickoff_wq;
  1205. wait_info.atomic_cnt = &phys_enc->pending_retire_fence_cnt;
  1206. wait_info.timeout_ms = max_t(u32, wb_enc->wbdone_timeout,
  1207. KICKOFF_TIMEOUT_MS);
  1208. rc = sde_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_WB_DONE,
  1209. &wait_info);
  1210. if (rc == -ETIMEDOUT && _sde_encoder_phys_wb_is_idle(phys_enc)) {
  1211. rc = 0;
  1212. } else if (rc == -ETIMEDOUT) {
  1213. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc),
  1214. wb_enc->frame_count, SDE_EVTLOG_ERROR);
  1215. SDE_ERROR("wb:%d kickoff timed out\n", WBID(wb_enc));
  1216. event = sde_encoder_phys_wb_frame_timeout(phys_enc);
  1217. }
  1218. /* cleanup writeback framebuffer */
  1219. if (wb_enc->wb_fb && wb_enc->wb_aspace) {
  1220. msm_framebuffer_cleanup(wb_enc->wb_fb, wb_enc->wb_aspace);
  1221. drm_framebuffer_put(wb_enc->wb_fb);
  1222. wb_enc->wb_fb = NULL;
  1223. wb_enc->wb_aspace = NULL;
  1224. }
  1225. skip_wait:
  1226. /* remove vote for iommu/clk/bus */
  1227. wb_enc->frame_count++;
  1228. if (!rc) {
  1229. wb_enc->end_time = ktime_get();
  1230. wb_time = (u64)ktime_to_us(wb_enc->end_time) -
  1231. (u64)ktime_to_us(wb_enc->start_time);
  1232. SDE_DEBUG("wb:%d took %llu us\n", WBID(wb_enc), wb_time);
  1233. }
  1234. /* cleanup previous buffer if pending */
  1235. if (wb_enc->cwb_old_fb && wb_enc->cwb_old_aspace) {
  1236. msm_framebuffer_cleanup(wb_enc->cwb_old_fb, wb_enc->cwb_old_aspace);
  1237. drm_framebuffer_put(wb_enc->cwb_old_fb);
  1238. wb_enc->cwb_old_fb = NULL;
  1239. wb_enc->cwb_old_aspace = NULL;
  1240. }
  1241. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc), wb_enc->frame_count,
  1242. wb_time, event, rc);
  1243. return rc;
  1244. }
  1245. /**
  1246. * sde_encoder_phys_wb_wait_for_commit_done - wait until request is committed
  1247. * @phys_enc: Pointer to physical encoder
  1248. */
  1249. static int sde_encoder_phys_wb_wait_for_commit_done(
  1250. struct sde_encoder_phys *phys_enc)
  1251. {
  1252. int rc;
  1253. if (phys_enc->enable_state == SDE_ENC_DISABLING &&
  1254. phys_enc->in_clone_mode) {
  1255. rc = _sde_encoder_phys_wb_wait_for_commit_done(phys_enc, true);
  1256. _sde_encoder_phys_wb_reset_state(phys_enc);
  1257. sde_encoder_phys_wb_irq_ctrl(phys_enc, false);
  1258. } else {
  1259. rc = _sde_encoder_phys_wb_wait_for_commit_done(phys_enc, false);
  1260. }
  1261. return rc;
  1262. }
  1263. static int sde_encoder_phys_wb_wait_for_tx_complete(
  1264. struct sde_encoder_phys *phys_enc)
  1265. {
  1266. if (!atomic_read(&phys_enc->pending_retire_fence_cnt))
  1267. return 0;
  1268. return _sde_encoder_phys_wb_wait_for_commit_done(phys_enc, true);
  1269. }
  1270. /**
  1271. * sde_encoder_phys_wb_prepare_for_kickoff - pre-kickoff processing
  1272. * @phys_enc: Pointer to physical encoder
  1273. * @params: kickoff parameters
  1274. * Returns: Zero on success
  1275. */
  1276. static int sde_encoder_phys_wb_prepare_for_kickoff(
  1277. struct sde_encoder_phys *phys_enc,
  1278. struct sde_encoder_kickoff_params *params)
  1279. {
  1280. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1281. SDE_DEBUG("[wb:%d,%u]\n", wb_enc->hw_wb->idx - WB_0,
  1282. wb_enc->kickoff_count);
  1283. if (phys_enc->in_clone_mode) {
  1284. wb_enc->cwb_old_fb = wb_enc->wb_fb;
  1285. wb_enc->cwb_old_aspace = wb_enc->wb_aspace;
  1286. }
  1287. wb_enc->kickoff_count++;
  1288. /* set OT limit & enable traffic shaper */
  1289. sde_encoder_phys_wb_setup(phys_enc);
  1290. _sde_encoder_phys_wb_update_flush(phys_enc);
  1291. _sde_encoder_phys_wb_update_cwb_flush(phys_enc, true);
  1292. /* vote for iommu/clk/bus */
  1293. wb_enc->start_time = ktime_get();
  1294. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc),
  1295. wb_enc->kickoff_count, wb_enc->frame_count,
  1296. phys_enc->in_clone_mode);
  1297. return 0;
  1298. }
  1299. /**
  1300. * sde_encoder_phys_wb_trigger_flush - trigger flush processing
  1301. * @phys_enc: Pointer to physical encoder
  1302. */
  1303. static void sde_encoder_phys_wb_trigger_flush(struct sde_encoder_phys *phys_enc)
  1304. {
  1305. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1306. if (!phys_enc || !wb_enc->hw_wb) {
  1307. SDE_ERROR("invalid encoder\n");
  1308. return;
  1309. }
  1310. /*
  1311. * Bail out iff in CWB mode. In case of CWB, primary control-path
  1312. * which is actually driving would trigger the flush
  1313. */
  1314. if (phys_enc->in_clone_mode) {
  1315. SDE_DEBUG("in CWB mode. early return\n");
  1316. return;
  1317. }
  1318. SDE_DEBUG("[wb:%d]\n", wb_enc->hw_wb->idx - WB_0);
  1319. /* clear pending flush if commit with no framebuffer */
  1320. if (!wb_enc->wb_fb) {
  1321. SDE_DEBUG("no output framebuffer\n");
  1322. return;
  1323. }
  1324. sde_encoder_helper_trigger_flush(phys_enc);
  1325. }
  1326. /**
  1327. * sde_encoder_phys_wb_handle_post_kickoff - post-kickoff processing
  1328. * @phys_enc: Pointer to physical encoder
  1329. */
  1330. static void sde_encoder_phys_wb_handle_post_kickoff(
  1331. struct sde_encoder_phys *phys_enc)
  1332. {
  1333. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1334. SDE_DEBUG("[wb:%d]\n", wb_enc->hw_wb->idx - WB_0);
  1335. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc));
  1336. }
  1337. /**
  1338. * _sde_encoder_phys_wb_init_internal_fb - create fb for internal commit
  1339. * @wb_enc: Pointer to writeback encoder
  1340. * @pixel_format: DRM pixel format
  1341. * @width: Desired fb width
  1342. * @height: Desired fb height
  1343. * @pitch: Desired fb pitch
  1344. */
  1345. static int _sde_encoder_phys_wb_init_internal_fb(
  1346. struct sde_encoder_phys_wb *wb_enc,
  1347. uint32_t pixel_format, uint32_t width,
  1348. uint32_t height, uint32_t pitch)
  1349. {
  1350. struct drm_device *dev;
  1351. struct drm_framebuffer *fb;
  1352. struct drm_mode_fb_cmd2 mode_cmd;
  1353. uint32_t size;
  1354. int nplanes, i, ret;
  1355. struct msm_gem_address_space *aspace;
  1356. const struct drm_format_info *info;
  1357. if (!wb_enc || !wb_enc->base.parent || !wb_enc->base.sde_kms) {
  1358. SDE_ERROR("invalid params\n");
  1359. return -EINVAL;
  1360. }
  1361. aspace = wb_enc->base.sde_kms->aspace[SDE_IOMMU_DOMAIN_UNSECURE];
  1362. if (!aspace) {
  1363. SDE_ERROR("invalid address space\n");
  1364. return -EINVAL;
  1365. }
  1366. dev = wb_enc->base.sde_kms->dev;
  1367. if (!dev) {
  1368. SDE_ERROR("invalid dev\n");
  1369. return -EINVAL;
  1370. }
  1371. memset(&mode_cmd, 0, sizeof(mode_cmd));
  1372. mode_cmd.pixel_format = pixel_format;
  1373. mode_cmd.width = width;
  1374. mode_cmd.height = height;
  1375. mode_cmd.pitches[0] = pitch;
  1376. size = sde_format_get_framebuffer_size(pixel_format,
  1377. mode_cmd.width, mode_cmd.height,
  1378. mode_cmd.pitches, 0);
  1379. if (!size) {
  1380. SDE_DEBUG("not creating zero size buffer\n");
  1381. return -EINVAL;
  1382. }
  1383. /* allocate gem tracking object */
  1384. info = drm_get_format_info(dev, &mode_cmd);
  1385. nplanes = info->num_planes;
  1386. if (nplanes >= SDE_MAX_PLANES) {
  1387. SDE_ERROR("requested format has too many planes\n");
  1388. return -EINVAL;
  1389. }
  1390. wb_enc->bo_disable[0] = msm_gem_new(dev, size,
  1391. MSM_BO_SCANOUT | MSM_BO_WC);
  1392. if (IS_ERR_OR_NULL(wb_enc->bo_disable[0])) {
  1393. ret = PTR_ERR(wb_enc->bo_disable[0]);
  1394. wb_enc->bo_disable[0] = NULL;
  1395. SDE_ERROR("failed to create bo, %d\n", ret);
  1396. return ret;
  1397. }
  1398. for (i = 0; i < nplanes; ++i) {
  1399. wb_enc->bo_disable[i] = wb_enc->bo_disable[0];
  1400. mode_cmd.pitches[i] = width * info->cpp[i];
  1401. }
  1402. fb = msm_framebuffer_init(dev, &mode_cmd, wb_enc->bo_disable);
  1403. if (IS_ERR_OR_NULL(fb)) {
  1404. ret = PTR_ERR(fb);
  1405. drm_gem_object_put(wb_enc->bo_disable[0]);
  1406. wb_enc->bo_disable[0] = NULL;
  1407. SDE_ERROR("failed to init fb, %d\n", ret);
  1408. return ret;
  1409. }
  1410. /* prepare the backing buffer now so that it's available later */
  1411. ret = msm_framebuffer_prepare(fb, aspace);
  1412. if (!ret)
  1413. wb_enc->fb_disable = fb;
  1414. return ret;
  1415. }
  1416. /**
  1417. * _sde_encoder_phys_wb_destroy_internal_fb - deconstruct internal fb
  1418. * @wb_enc: Pointer to writeback encoder
  1419. */
  1420. static void _sde_encoder_phys_wb_destroy_internal_fb(
  1421. struct sde_encoder_phys_wb *wb_enc)
  1422. {
  1423. if (!wb_enc)
  1424. return;
  1425. if (wb_enc->fb_disable) {
  1426. drm_framebuffer_unregister_private(wb_enc->fb_disable);
  1427. drm_framebuffer_remove(wb_enc->fb_disable);
  1428. wb_enc->fb_disable = NULL;
  1429. }
  1430. if (wb_enc->bo_disable[0]) {
  1431. drm_gem_object_put(wb_enc->bo_disable[0]);
  1432. wb_enc->bo_disable[0] = NULL;
  1433. }
  1434. }
  1435. /**
  1436. * sde_encoder_phys_wb_enable - enable writeback encoder
  1437. * @phys_enc: Pointer to physical encoder
  1438. */
  1439. static void sde_encoder_phys_wb_enable(struct sde_encoder_phys *phys_enc)
  1440. {
  1441. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1442. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  1443. struct drm_device *dev;
  1444. struct drm_connector *connector;
  1445. SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
  1446. if (!wb_enc->base.parent || !wb_enc->base.parent->dev) {
  1447. SDE_ERROR("invalid drm device\n");
  1448. return;
  1449. }
  1450. dev = wb_enc->base.parent->dev;
  1451. /* find associated writeback connector */
  1452. connector = phys_enc->connector;
  1453. if (!connector || connector->encoder != phys_enc->parent) {
  1454. SDE_ERROR("failed to find writeback connector\n");
  1455. return;
  1456. }
  1457. wb_enc->wb_dev = sde_wb_connector_get_wb(connector);
  1458. phys_enc->enable_state = SDE_ENC_ENABLED;
  1459. /*
  1460. * cache the crtc in wb_enc on enable for duration of use case
  1461. * for correctly servicing asynchronous irq events and timers
  1462. */
  1463. wb_enc->crtc = phys_enc->parent->crtc;
  1464. }
  1465. /**
  1466. * sde_encoder_phys_wb_disable - disable writeback encoder
  1467. * @phys_enc: Pointer to physical encoder
  1468. */
  1469. static void sde_encoder_phys_wb_disable(struct sde_encoder_phys *phys_enc)
  1470. {
  1471. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1472. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  1473. SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
  1474. if (phys_enc->enable_state == SDE_ENC_DISABLED) {
  1475. SDE_ERROR("encoder is already disabled\n");
  1476. return;
  1477. }
  1478. SDE_DEBUG("[wait_for_done: wb:%d, frame:%u, kickoff:%u]\n",
  1479. hw_wb->idx - WB_0, wb_enc->frame_count,
  1480. wb_enc->kickoff_count);
  1481. if (!phys_enc->in_clone_mode || !wb_enc->crtc->state->active)
  1482. _sde_encoder_phys_wb_wait_for_commit_done(phys_enc, true);
  1483. if (!phys_enc->hw_ctl || !phys_enc->parent ||
  1484. !phys_enc->sde_kms || !wb_enc->fb_disable) {
  1485. SDE_DEBUG("invalid enc, skipping extra commit\n");
  1486. goto exit;
  1487. }
  1488. if (phys_enc->in_clone_mode) {
  1489. _sde_encoder_phys_wb_setup_cwb(phys_enc, false);
  1490. _sde_encoder_phys_wb_update_cwb_flush(phys_enc, false);
  1491. phys_enc->enable_state = SDE_ENC_DISABLING;
  1492. if (wb_enc->crtc->state->active) {
  1493. sde_encoder_phys_wb_irq_ctrl(phys_enc, true);
  1494. return;
  1495. }
  1496. goto exit;
  1497. }
  1498. /* reset h/w before final flush */
  1499. if (phys_enc->hw_ctl->ops.clear_pending_flush)
  1500. phys_enc->hw_ctl->ops.clear_pending_flush(phys_enc->hw_ctl);
  1501. /*
  1502. * New CTL reset sequence from 5.0 MDP onwards.
  1503. * If has_3d_merge_reset is not set, legacy reset
  1504. * sequence is executed.
  1505. */
  1506. if (hw_wb->catalog->has_3d_merge_reset) {
  1507. sde_encoder_helper_phys_disable(phys_enc, wb_enc);
  1508. goto exit;
  1509. }
  1510. if (sde_encoder_helper_reset_mixers(phys_enc, NULL))
  1511. goto exit;
  1512. phys_enc->enable_state = SDE_ENC_DISABLING;
  1513. sde_encoder_phys_wb_prepare_for_kickoff(phys_enc, NULL);
  1514. sde_encoder_phys_wb_irq_ctrl(phys_enc, true);
  1515. if (phys_enc->hw_ctl->ops.trigger_flush)
  1516. phys_enc->hw_ctl->ops.trigger_flush(phys_enc->hw_ctl);
  1517. sde_encoder_helper_trigger_start(phys_enc);
  1518. _sde_encoder_phys_wb_wait_for_commit_done(phys_enc, true);
  1519. sde_encoder_phys_wb_irq_ctrl(phys_enc, false);
  1520. exit:
  1521. _sde_encoder_phys_wb_reset_state(phys_enc);
  1522. }
  1523. /**
  1524. * sde_encoder_phys_wb_get_hw_resources - get hardware resources
  1525. * @phys_enc: Pointer to physical encoder
  1526. * @hw_res: Pointer to encoder resources
  1527. */
  1528. static void sde_encoder_phys_wb_get_hw_resources(
  1529. struct sde_encoder_phys *phys_enc,
  1530. struct sde_encoder_hw_resources *hw_res,
  1531. struct drm_connector_state *conn_state)
  1532. {
  1533. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1534. struct sde_hw_wb *hw_wb;
  1535. struct drm_framebuffer *fb;
  1536. const struct sde_format *fmt = NULL;
  1537. if (!phys_enc) {
  1538. SDE_ERROR("invalid encoder\n");
  1539. return;
  1540. }
  1541. fb = sde_wb_connector_state_get_output_fb(conn_state);
  1542. if (fb) {
  1543. fmt = sde_get_sde_format_ext(fb->format->format, fb->modifier);
  1544. if (!fmt) {
  1545. SDE_ERROR("unsupported output pixel format:%d\n",
  1546. fb->format->format);
  1547. return;
  1548. }
  1549. }
  1550. hw_wb = wb_enc->hw_wb;
  1551. hw_res->wbs[hw_wb->idx - WB_0] = phys_enc->intf_mode;
  1552. hw_res->needs_cdm = fmt ? SDE_FORMAT_IS_YUV(fmt) : false;
  1553. SDE_DEBUG("[wb:%d] intf_mode=%d needs_cdm=%d\n", hw_wb->idx - WB_0,
  1554. hw_res->wbs[hw_wb->idx - WB_0],
  1555. hw_res->needs_cdm);
  1556. }
  1557. #ifdef CONFIG_DEBUG_FS
  1558. /**
  1559. * sde_encoder_phys_wb_init_debugfs - initialize writeback encoder debugfs
  1560. * @phys_enc: Pointer to physical encoder
  1561. * @debugfs_root: Pointer to virtual encoder's debugfs_root dir
  1562. */
  1563. static int sde_encoder_phys_wb_init_debugfs(
  1564. struct sde_encoder_phys *phys_enc, struct dentry *debugfs_root)
  1565. {
  1566. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1567. if (!phys_enc || !wb_enc->hw_wb || !debugfs_root)
  1568. return -EINVAL;
  1569. debugfs_create_u32("wbdone_timeout", 0600, debugfs_root, &wb_enc->wbdone_timeout);
  1570. return 0;
  1571. }
  1572. #else
  1573. static int sde_encoder_phys_wb_init_debugfs(
  1574. struct sde_encoder_phys *phys_enc, struct dentry *debugfs_root)
  1575. {
  1576. return 0;
  1577. }
  1578. #endif
  1579. static int sde_encoder_phys_wb_late_register(struct sde_encoder_phys *phys_enc,
  1580. struct dentry *debugfs_root)
  1581. {
  1582. return sde_encoder_phys_wb_init_debugfs(phys_enc, debugfs_root);
  1583. }
  1584. /**
  1585. * sde_encoder_phys_wb_destroy - destroy writeback encoder
  1586. * @phys_enc: Pointer to physical encoder
  1587. */
  1588. static void sde_encoder_phys_wb_destroy(struct sde_encoder_phys *phys_enc)
  1589. {
  1590. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1591. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  1592. SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
  1593. if (!phys_enc)
  1594. return;
  1595. _sde_encoder_phys_wb_destroy_internal_fb(wb_enc);
  1596. kfree(wb_enc);
  1597. }
  1598. /**
  1599. * sde_encoder_phys_wb_init_ops - initialize writeback operations
  1600. * @ops: Pointer to encoder operation table
  1601. */
  1602. static void sde_encoder_phys_wb_init_ops(struct sde_encoder_phys_ops *ops)
  1603. {
  1604. ops->late_register = sde_encoder_phys_wb_late_register;
  1605. ops->is_master = sde_encoder_phys_wb_is_master;
  1606. ops->mode_set = sde_encoder_phys_wb_mode_set;
  1607. ops->enable = sde_encoder_phys_wb_enable;
  1608. ops->disable = sde_encoder_phys_wb_disable;
  1609. ops->destroy = sde_encoder_phys_wb_destroy;
  1610. ops->atomic_check = sde_encoder_phys_wb_atomic_check;
  1611. ops->get_hw_resources = sde_encoder_phys_wb_get_hw_resources;
  1612. ops->wait_for_commit_done = sde_encoder_phys_wb_wait_for_commit_done;
  1613. ops->wait_for_tx_complete = sde_encoder_phys_wb_wait_for_tx_complete;
  1614. ops->prepare_for_kickoff = sde_encoder_phys_wb_prepare_for_kickoff;
  1615. ops->handle_post_kickoff = sde_encoder_phys_wb_handle_post_kickoff;
  1616. ops->trigger_flush = sde_encoder_phys_wb_trigger_flush;
  1617. ops->trigger_start = sde_encoder_helper_trigger_start;
  1618. ops->hw_reset = sde_encoder_helper_hw_reset;
  1619. ops->irq_control = sde_encoder_phys_wb_irq_ctrl;
  1620. }
  1621. /**
  1622. * sde_encoder_phys_wb_init - initialize writeback encoder
  1623. * @init: Pointer to init info structure with initialization params
  1624. */
  1625. struct sde_encoder_phys *sde_encoder_phys_wb_init(
  1626. struct sde_enc_phys_init_params *p)
  1627. {
  1628. struct sde_encoder_phys *phys_enc;
  1629. struct sde_encoder_phys_wb *wb_enc;
  1630. const struct sde_wb_cfg *wb_cfg;
  1631. struct sde_hw_mdp *hw_mdp;
  1632. struct sde_encoder_irq *irq;
  1633. int ret = 0;
  1634. SDE_DEBUG("\n");
  1635. if (!p || !p->parent) {
  1636. SDE_ERROR("invalid params\n");
  1637. ret = -EINVAL;
  1638. goto fail_alloc;
  1639. }
  1640. wb_enc = kzalloc(sizeof(*wb_enc), GFP_KERNEL);
  1641. if (!wb_enc) {
  1642. SDE_ERROR("failed to allocate wb enc\n");
  1643. ret = -ENOMEM;
  1644. goto fail_alloc;
  1645. }
  1646. wb_enc->wbdone_timeout = KICKOFF_TIMEOUT_MS;
  1647. phys_enc = &wb_enc->base;
  1648. if (p->sde_kms->vbif[VBIF_NRT]) {
  1649. wb_enc->aspace[SDE_IOMMU_DOMAIN_UNSECURE] =
  1650. p->sde_kms->aspace[MSM_SMMU_DOMAIN_NRT_UNSECURE];
  1651. wb_enc->aspace[SDE_IOMMU_DOMAIN_SECURE] =
  1652. p->sde_kms->aspace[MSM_SMMU_DOMAIN_NRT_SECURE];
  1653. } else {
  1654. wb_enc->aspace[SDE_IOMMU_DOMAIN_UNSECURE] =
  1655. p->sde_kms->aspace[MSM_SMMU_DOMAIN_UNSECURE];
  1656. wb_enc->aspace[SDE_IOMMU_DOMAIN_SECURE] =
  1657. p->sde_kms->aspace[MSM_SMMU_DOMAIN_SECURE];
  1658. }
  1659. hw_mdp = sde_rm_get_mdp(&p->sde_kms->rm);
  1660. if (IS_ERR_OR_NULL(hw_mdp)) {
  1661. ret = PTR_ERR(hw_mdp);
  1662. SDE_ERROR("failed to init hw_top: %d\n", ret);
  1663. goto fail_mdp_init;
  1664. }
  1665. phys_enc->hw_mdptop = hw_mdp;
  1666. /**
  1667. * hw_wb resource permanently assigned to this encoder
  1668. * Other resources allocated at atomic commit time by use case
  1669. */
  1670. if (p->wb_idx != SDE_NONE) {
  1671. struct sde_rm_hw_iter iter;
  1672. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_WB);
  1673. while (sde_rm_get_hw(&p->sde_kms->rm, &iter)) {
  1674. struct sde_hw_wb *hw_wb = (struct sde_hw_wb *)iter.hw;
  1675. if (hw_wb->idx == p->wb_idx) {
  1676. wb_enc->hw_wb = hw_wb;
  1677. break;
  1678. }
  1679. }
  1680. if (!wb_enc->hw_wb) {
  1681. ret = -EINVAL;
  1682. SDE_ERROR("failed to init hw_wb%d\n", p->wb_idx - WB_0);
  1683. goto fail_wb_init;
  1684. }
  1685. } else {
  1686. ret = -EINVAL;
  1687. SDE_ERROR("invalid wb_idx\n");
  1688. goto fail_wb_check;
  1689. }
  1690. sde_encoder_phys_wb_init_ops(&phys_enc->ops);
  1691. phys_enc->parent = p->parent;
  1692. phys_enc->parent_ops = p->parent_ops;
  1693. phys_enc->sde_kms = p->sde_kms;
  1694. phys_enc->split_role = p->split_role;
  1695. phys_enc->intf_mode = INTF_MODE_WB_LINE;
  1696. phys_enc->intf_idx = p->intf_idx;
  1697. phys_enc->enc_spinlock = p->enc_spinlock;
  1698. phys_enc->vblank_ctl_lock = p->vblank_ctl_lock;
  1699. atomic_set(&phys_enc->pending_retire_fence_cnt, 0);
  1700. atomic_set(&phys_enc->wbirq_refcount, 0);
  1701. init_waitqueue_head(&phys_enc->pending_kickoff_wq);
  1702. wb_cfg = wb_enc->hw_wb->caps;
  1703. irq = &phys_enc->irq[INTR_IDX_WB_DONE];
  1704. INIT_LIST_HEAD(&irq->cb.list);
  1705. irq->name = "wb_done";
  1706. irq->hw_idx = wb_enc->hw_wb->idx;
  1707. irq->irq_idx = -1;
  1708. irq->intr_type = sde_encoder_phys_wb_get_intr_type(wb_enc->hw_wb);
  1709. irq->intr_idx = INTR_IDX_WB_DONE;
  1710. irq->cb.arg = wb_enc;
  1711. irq->cb.func = sde_encoder_phys_wb_done_irq;
  1712. if (wb_cfg && (wb_cfg->features & BIT(SDE_WB_HAS_DCWB))) {
  1713. irq = &phys_enc->irq[INTR_IDX_PP_CWB_OVFL];
  1714. INIT_LIST_HEAD(&irq->cb.list);
  1715. irq->name = "pp_cwb0_overflow";
  1716. irq->hw_idx = PINGPONG_CWB_0;
  1717. irq->irq_idx = -1;
  1718. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1719. irq->intr_idx = INTR_IDX_PP_CWB_OVFL;
  1720. irq->cb.arg = wb_enc;
  1721. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1722. } else {
  1723. irq = &phys_enc->irq[INTR_IDX_PP1_OVFL];
  1724. INIT_LIST_HEAD(&irq->cb.list);
  1725. irq->name = "pp1_overflow";
  1726. irq->hw_idx = CWB_1;
  1727. irq->irq_idx = -1;
  1728. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1729. irq->intr_idx = INTR_IDX_PP1_OVFL;
  1730. irq->cb.arg = wb_enc;
  1731. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1732. irq = &phys_enc->irq[INTR_IDX_PP2_OVFL];
  1733. INIT_LIST_HEAD(&irq->cb.list);
  1734. irq->name = "pp2_overflow";
  1735. irq->hw_idx = CWB_2;
  1736. irq->irq_idx = -1;
  1737. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1738. irq->intr_idx = INTR_IDX_PP2_OVFL;
  1739. irq->cb.arg = wb_enc;
  1740. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1741. irq = &phys_enc->irq[INTR_IDX_PP3_OVFL];
  1742. INIT_LIST_HEAD(&irq->cb.list);
  1743. irq->name = "pp3_overflow";
  1744. irq->hw_idx = CWB_3;
  1745. irq->irq_idx = -1;
  1746. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1747. irq->intr_idx = INTR_IDX_PP3_OVFL;
  1748. irq->cb.arg = wb_enc;
  1749. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1750. irq = &phys_enc->irq[INTR_IDX_PP4_OVFL];
  1751. INIT_LIST_HEAD(&irq->cb.list);
  1752. irq->name = "pp4_overflow";
  1753. irq->hw_idx = CWB_4;
  1754. irq->irq_idx = -1;
  1755. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1756. irq->intr_idx = INTR_IDX_PP4_OVFL;
  1757. irq->cb.arg = wb_enc;
  1758. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1759. irq = &phys_enc->irq[INTR_IDX_PP5_OVFL];
  1760. INIT_LIST_HEAD(&irq->cb.list);
  1761. irq->name = "pp5_overflow";
  1762. irq->hw_idx = CWB_5;
  1763. irq->irq_idx = -1;
  1764. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1765. irq->intr_idx = INTR_IDX_PP5_OVFL;
  1766. irq->cb.arg = wb_enc;
  1767. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1768. }
  1769. /* create internal buffer for disable logic */
  1770. if (_sde_encoder_phys_wb_init_internal_fb(wb_enc,
  1771. DRM_FORMAT_RGB888, 2, 1, 6)) {
  1772. SDE_ERROR("failed to init internal fb\n");
  1773. goto fail_wb_init;
  1774. }
  1775. SDE_DEBUG("Created sde_encoder_phys_wb for wb %d\n",
  1776. wb_enc->hw_wb->idx - WB_0);
  1777. return phys_enc;
  1778. fail_wb_init:
  1779. fail_wb_check:
  1780. fail_mdp_init:
  1781. kfree(wb_enc);
  1782. fail_alloc:
  1783. return ERR_PTR(ret);
  1784. }