qcs405.c 212 KB

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  1. /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/gpio.h>
  15. #include <linux/of_gpio.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/io.h>
  19. #include <linux/module.h>
  20. #include <linux/input.h>
  21. #include <linux/of_device.h>
  22. #include <linux/pm_qos.h>
  23. #include <sound/core.h>
  24. #include <sound/soc.h>
  25. #include <sound/soc-dapm.h>
  26. #include <sound/pcm.h>
  27. #include <sound/pcm_params.h>
  28. #include <sound/info.h>
  29. #include <dsp/audio_notifier.h>
  30. #include <dsp/q6afe-v2.h>
  31. #include <dsp/q6core.h>
  32. #include "device_event.h"
  33. #include "msm-pcm-routing-v2.h"
  34. #include "codecs/msm-cdc-pinctrl.h"
  35. #include "codecs/wcd9335.h"
  36. #include "codecs/wsa881x.h"
  37. #include "codecs/csra66x0/csra66x0.h"
  38. #include <dt-bindings/sound/audio-codec-port-types.h>
  39. #define DRV_NAME "qcs405-asoc-snd"
  40. #define __CHIPSET__ "QCS405 "
  41. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  42. #define DEV_NAME_STR_LEN 32
  43. #define SAMPLING_RATE_8KHZ 8000
  44. #define SAMPLING_RATE_11P025KHZ 11025
  45. #define SAMPLING_RATE_16KHZ 16000
  46. #define SAMPLING_RATE_22P05KHZ 22050
  47. #define SAMPLING_RATE_32KHZ 32000
  48. #define SAMPLING_RATE_44P1KHZ 44100
  49. #define SAMPLING_RATE_48KHZ 48000
  50. #define SAMPLING_RATE_88P2KHZ 88200
  51. #define SAMPLING_RATE_96KHZ 96000
  52. #define SAMPLING_RATE_176P4KHZ 176400
  53. #define SAMPLING_RATE_192KHZ 192000
  54. #define SAMPLING_RATE_352P8KHZ 352800
  55. #define SAMPLING_RATE_384KHZ 384000
  56. #define WSA8810_NAME_1 "wsa881x.20170211"
  57. #define WSA8810_NAME_2 "wsa881x.20170212"
  58. #define WCN_CDC_SLIM_RX_CH_MAX 2
  59. #define WCN_CDC_SLIM_TX_CH_MAX 3
  60. #define TDM_CHANNEL_MAX 8
  61. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  62. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  63. enum {
  64. SLIM_RX_0 = 0,
  65. SLIM_RX_1,
  66. SLIM_RX_2,
  67. SLIM_RX_3,
  68. SLIM_RX_4,
  69. SLIM_RX_5,
  70. SLIM_RX_6,
  71. SLIM_RX_7,
  72. SLIM_RX_MAX,
  73. };
  74. enum {
  75. SLIM_TX_0 = 0,
  76. SLIM_TX_1,
  77. SLIM_TX_2,
  78. SLIM_TX_3,
  79. SLIM_TX_4,
  80. SLIM_TX_5,
  81. SLIM_TX_6,
  82. SLIM_TX_7,
  83. SLIM_TX_8,
  84. SLIM_TX_MAX,
  85. };
  86. enum {
  87. PRIM_MI2S = 0,
  88. SEC_MI2S,
  89. TERT_MI2S,
  90. QUAT_MI2S,
  91. QUIN_MI2S,
  92. MI2S_MAX,
  93. };
  94. enum {
  95. PRIM_AUX_PCM = 0,
  96. SEC_AUX_PCM,
  97. TERT_AUX_PCM,
  98. QUAT_AUX_PCM,
  99. QUIN_AUX_PCM,
  100. AUX_PCM_MAX,
  101. };
  102. enum {
  103. WSA_CDC_DMA_RX_0 = 0,
  104. WSA_CDC_DMA_RX_1,
  105. CDC_DMA_RX_MAX,
  106. };
  107. enum {
  108. WSA_CDC_DMA_TX_0 = 0,
  109. WSA_CDC_DMA_TX_1,
  110. WSA_CDC_DMA_TX_2,
  111. VA_CDC_DMA_TX_0,
  112. VA_CDC_DMA_TX_1,
  113. CDC_DMA_TX_MAX,
  114. };
  115. struct mi2s_conf {
  116. struct mutex lock;
  117. u32 ref_cnt;
  118. u32 msm_is_mi2s_master;
  119. };
  120. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  121. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  122. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  123. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  124. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  125. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
  126. };
  127. struct dev_config {
  128. u32 sample_rate;
  129. u32 bit_format;
  130. u32 channels;
  131. };
  132. struct msm_wsa881x_dev_info {
  133. struct device_node *of_node;
  134. u32 index;
  135. };
  136. struct msm_csra66x0_dev_info {
  137. struct device_node *of_node;
  138. u32 index;
  139. };
  140. enum pinctrl_pin_state {
  141. STATE_DISABLE = 0, /* All pins are in sleep state */
  142. STATE_MI2S_ACTIVE, /* I2S = active, TDM = sleep */
  143. STATE_TDM_ACTIVE, /* I2S = sleep, TDM = active */
  144. };
  145. struct msm_pinctrl_info {
  146. struct pinctrl *pinctrl;
  147. struct pinctrl_state *mi2s_disable;
  148. struct pinctrl_state *tdm_disable;
  149. struct pinctrl_state *mi2s_active;
  150. struct pinctrl_state *tdm_active;
  151. enum pinctrl_pin_state curr_state;
  152. };
  153. struct msm_asoc_mach_data {
  154. struct snd_info_entry *codec_root;
  155. struct msm_pinctrl_info pinctrl_info;
  156. struct device_node *dmic_01_gpio_p; /* used by pinctrl API */
  157. struct device_node *dmic_23_gpio_p; /* used by pinctrl API */
  158. struct device_node *dmic_45_gpio_p; /* used by pinctrl API */
  159. struct device_node *dmic_67_gpio_p; /* used by pinctrl API */
  160. int dmic_01_gpio_cnt;
  161. int dmic_23_gpio_cnt;
  162. int dmic_45_gpio_cnt;
  163. int dmic_67_gpio_cnt;
  164. };
  165. struct msm_asoc_wcd93xx_codec {
  166. void* (*get_afe_config_fn)(struct snd_soc_codec *codec,
  167. enum afe_config_type config_type);
  168. };
  169. static const char *const pin_states[] = {"sleep", "i2s-active",
  170. "tdm-active"};
  171. enum {
  172. TDM_0 = 0,
  173. TDM_1,
  174. TDM_2,
  175. TDM_3,
  176. TDM_4,
  177. TDM_5,
  178. TDM_6,
  179. TDM_7,
  180. TDM_PORT_MAX,
  181. };
  182. enum {
  183. TDM_PRI = 0,
  184. TDM_SEC,
  185. TDM_TERT,
  186. TDM_QUAT,
  187. TDM_QUIN,
  188. TDM_INTERFACE_MAX,
  189. };
  190. struct tdm_port {
  191. u32 mode;
  192. u32 channel;
  193. };
  194. /* TDM default config */
  195. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  196. { /* PRI TDM */
  197. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  198. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  199. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  200. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  201. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  202. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  203. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  204. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  205. },
  206. { /* SEC TDM */
  207. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  208. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  209. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  210. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  211. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  212. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  213. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  214. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  215. },
  216. { /* TERT TDM */
  217. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  218. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  219. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  220. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  221. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  222. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  223. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  224. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  225. },
  226. { /* QUAT TDM */
  227. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  228. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  229. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  230. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  231. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  232. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  233. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  235. },
  236. { /* QUIN TDM */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  239. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  240. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  241. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  242. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  243. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  245. }
  246. };
  247. /* TDM default config */
  248. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  249. { /* PRI TDM */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  252. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  253. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  254. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  255. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  256. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  258. },
  259. { /* SEC TDM */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  261. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  262. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  263. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  264. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  265. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  266. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  268. },
  269. { /* TERT TDM */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  275. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  276. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  278. },
  279. { /* QUAT TDM */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  285. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  288. },
  289. { /* QUIN TDM */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  295. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  296. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  298. }
  299. };
  300. /* Default configuration of slimbus channels */
  301. static struct dev_config slim_rx_cfg[] = {
  302. [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  303. [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  304. [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  305. [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  306. [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  307. [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  308. [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  309. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  310. };
  311. static struct dev_config slim_tx_cfg[] = {
  312. [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  313. [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  314. [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  315. [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  316. [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  317. [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  318. [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  319. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  320. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  321. };
  322. /* Default configuration of Codec DMA Interface Tx */
  323. static struct dev_config cdc_dma_rx_cfg[] = {
  324. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  325. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  326. };
  327. /* Default configuration of Codec DMA Interface Rx */
  328. static struct dev_config cdc_dma_tx_cfg[] = {
  329. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  330. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  331. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  332. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  333. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  334. };
  335. static struct dev_config usb_rx_cfg = {
  336. .sample_rate = SAMPLING_RATE_48KHZ,
  337. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  338. .channels = 2,
  339. };
  340. static struct dev_config usb_tx_cfg = {
  341. .sample_rate = SAMPLING_RATE_48KHZ,
  342. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  343. .channels = 1,
  344. };
  345. static struct dev_config proxy_rx_cfg = {
  346. .sample_rate = SAMPLING_RATE_48KHZ,
  347. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  348. .channels = 2,
  349. };
  350. /* Default configuration of MI2S channels */
  351. static struct dev_config mi2s_rx_cfg[] = {
  352. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  353. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  354. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  355. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  356. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  357. };
  358. static struct dev_config mi2s_tx_cfg[] = {
  359. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  360. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  361. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  362. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  363. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  364. };
  365. static struct dev_config aux_pcm_rx_cfg[] = {
  366. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  367. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  368. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  369. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  370. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  371. };
  372. static struct dev_config aux_pcm_tx_cfg[] = {
  373. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  374. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  375. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  376. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  377. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  378. };
  379. static int msm_vi_feed_tx_ch = 2;
  380. static const char *const slim_rx_ch_text[] = {"One", "Two"};
  381. static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
  382. "Five", "Six", "Seven",
  383. "Eight"};
  384. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  385. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  386. "S32_LE"};
  387. static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  388. "KHZ_32", "KHZ_44P1", "KHZ_48",
  389. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  390. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  391. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  392. "KHZ_44P1", "KHZ_48",
  393. "KHZ_88P2", "KHZ_96"};
  394. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  395. "Five", "Six", "Seven",
  396. "Eight"};
  397. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  398. "Six", "Seven", "Eight"};
  399. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  400. "KHZ_16", "KHZ_22P05",
  401. "KHZ_32", "KHZ_44P1", "KHZ_48",
  402. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  403. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  404. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  405. "Five", "Six", "Seven", "Eight"};
  406. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  407. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  408. "KHZ_48", "KHZ_176P4",
  409. "KHZ_352P8"};
  410. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  411. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  412. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  413. "KHZ_48", "KHZ_96", "KHZ_192"};
  414. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  415. "Five", "Six", "Seven",
  416. "Eight"};
  417. static const char *const qos_text[] = {"Disable", "Enable"};
  418. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  419. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  420. "Five", "Six", "Seven",
  421. "Eight"};
  422. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  423. "KHZ_32", "KHZ_44P1", "KHZ_48",
  424. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  425. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  426. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
  427. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
  428. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
  429. static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
  430. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
  431. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
  432. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  433. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  434. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  435. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  436. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
  437. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
  438. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
  439. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
  440. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  441. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  442. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
  443. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
  444. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
  445. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
  446. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
  447. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  448. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  449. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  450. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  451. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  452. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  453. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  454. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  455. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  456. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  457. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  458. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  459. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  460. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  461. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  462. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  476. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  478. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  480. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  482. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  484. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  486. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  488. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  490. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  494. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  498. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  500. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  501. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  502. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  503. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  504. cdc_dma_sample_rate_text);
  505. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  506. cdc_dma_sample_rate_text);
  507. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  508. cdc_dma_sample_rate_text);
  509. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  510. cdc_dma_sample_rate_text);
  511. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  512. cdc_dma_sample_rate_text);
  513. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  514. cdc_dma_sample_rate_text);
  515. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  516. cdc_dma_sample_rate_text);
  517. static struct platform_device *spdev;
  518. static bool is_initial_boot;
  519. static bool codec_reg_done;
  520. static struct snd_soc_aux_dev *msm_aux_dev;
  521. static struct snd_soc_codec_conf *msm_codec_conf;
  522. static struct msm_asoc_wcd93xx_codec msm_codec_fn;
  523. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  524. int enable, bool dapm);
  525. static int msm_wsa881x_init(struct snd_soc_component *component);
  526. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  527. struct snd_ctl_elem_value *ucontrol);
  528. static struct snd_soc_dapm_route wcd_audio_paths[] = {
  529. {"MIC BIAS1", NULL, "MCLK TX"},
  530. {"MIC BIAS2", NULL, "MCLK TX"},
  531. {"MIC BIAS3", NULL, "MCLK TX"},
  532. {"MIC BIAS4", NULL, "MCLK TX"},
  533. };
  534. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  535. {
  536. AFE_API_VERSION_I2S_CONFIG,
  537. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  538. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  539. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  540. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  541. 0,
  542. },
  543. {
  544. AFE_API_VERSION_I2S_CONFIG,
  545. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  546. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  547. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  548. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  549. 0,
  550. },
  551. {
  552. AFE_API_VERSION_I2S_CONFIG,
  553. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  554. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  555. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  556. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  557. 0,
  558. },
  559. {
  560. AFE_API_VERSION_I2S_CONFIG,
  561. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  562. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  563. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  564. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  565. 0,
  566. },
  567. {
  568. AFE_API_VERSION_I2S_CONFIG,
  569. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  570. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  571. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  572. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  573. 0,
  574. }
  575. };
  576. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  577. static int slim_get_sample_rate_val(int sample_rate)
  578. {
  579. int sample_rate_val = 0;
  580. switch (sample_rate) {
  581. case SAMPLING_RATE_8KHZ:
  582. sample_rate_val = 0;
  583. break;
  584. case SAMPLING_RATE_16KHZ:
  585. sample_rate_val = 1;
  586. break;
  587. case SAMPLING_RATE_32KHZ:
  588. sample_rate_val = 2;
  589. break;
  590. case SAMPLING_RATE_44P1KHZ:
  591. sample_rate_val = 3;
  592. break;
  593. case SAMPLING_RATE_48KHZ:
  594. sample_rate_val = 4;
  595. break;
  596. case SAMPLING_RATE_88P2KHZ:
  597. sample_rate_val = 5;
  598. break;
  599. case SAMPLING_RATE_96KHZ:
  600. sample_rate_val = 6;
  601. break;
  602. case SAMPLING_RATE_176P4KHZ:
  603. sample_rate_val = 7;
  604. break;
  605. case SAMPLING_RATE_192KHZ:
  606. sample_rate_val = 8;
  607. break;
  608. case SAMPLING_RATE_352P8KHZ:
  609. sample_rate_val = 9;
  610. break;
  611. case SAMPLING_RATE_384KHZ:
  612. sample_rate_val = 10;
  613. break;
  614. default:
  615. sample_rate_val = 4;
  616. break;
  617. }
  618. return sample_rate_val;
  619. }
  620. static int slim_get_sample_rate(int value)
  621. {
  622. int sample_rate = 0;
  623. switch (value) {
  624. case 0:
  625. sample_rate = SAMPLING_RATE_8KHZ;
  626. break;
  627. case 1:
  628. sample_rate = SAMPLING_RATE_16KHZ;
  629. break;
  630. case 2:
  631. sample_rate = SAMPLING_RATE_32KHZ;
  632. break;
  633. case 3:
  634. sample_rate = SAMPLING_RATE_44P1KHZ;
  635. break;
  636. case 4:
  637. sample_rate = SAMPLING_RATE_48KHZ;
  638. break;
  639. case 5:
  640. sample_rate = SAMPLING_RATE_88P2KHZ;
  641. break;
  642. case 6:
  643. sample_rate = SAMPLING_RATE_96KHZ;
  644. break;
  645. case 7:
  646. sample_rate = SAMPLING_RATE_176P4KHZ;
  647. break;
  648. case 8:
  649. sample_rate = SAMPLING_RATE_192KHZ;
  650. break;
  651. case 9:
  652. sample_rate = SAMPLING_RATE_352P8KHZ;
  653. break;
  654. case 10:
  655. sample_rate = SAMPLING_RATE_384KHZ;
  656. break;
  657. default:
  658. sample_rate = SAMPLING_RATE_48KHZ;
  659. break;
  660. }
  661. return sample_rate;
  662. }
  663. static int slim_get_bit_format_val(int bit_format)
  664. {
  665. int val = 0;
  666. switch (bit_format) {
  667. case SNDRV_PCM_FORMAT_S32_LE:
  668. val = 3;
  669. break;
  670. case SNDRV_PCM_FORMAT_S24_3LE:
  671. val = 2;
  672. break;
  673. case SNDRV_PCM_FORMAT_S24_LE:
  674. val = 1;
  675. break;
  676. case SNDRV_PCM_FORMAT_S16_LE:
  677. default:
  678. val = 0;
  679. break;
  680. }
  681. return val;
  682. }
  683. static int slim_get_bit_format(int val)
  684. {
  685. int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  686. switch (val) {
  687. case 0:
  688. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  689. break;
  690. case 1:
  691. bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
  692. break;
  693. case 2:
  694. bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
  695. break;
  696. case 3:
  697. bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
  698. break;
  699. default:
  700. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  701. break;
  702. }
  703. return bit_fmt;
  704. }
  705. static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
  706. {
  707. int port_id = 0;
  708. if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
  709. port_id = SLIM_RX_0;
  710. } else if (strnstr(kcontrol->id.name,
  711. "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
  712. port_id = SLIM_RX_2;
  713. } else if (strnstr(kcontrol->id.name,
  714. "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
  715. port_id = SLIM_RX_5;
  716. } else if (strnstr(kcontrol->id.name,
  717. "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
  718. port_id = SLIM_RX_6;
  719. } else if (strnstr(kcontrol->id.name,
  720. "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
  721. port_id = SLIM_TX_0;
  722. } else if (strnstr(kcontrol->id.name,
  723. "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
  724. port_id = SLIM_TX_1;
  725. } else {
  726. pr_err("%s: unsupported channel: %s",
  727. __func__, kcontrol->id.name);
  728. return -EINVAL;
  729. }
  730. return port_id;
  731. }
  732. static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  733. struct snd_ctl_elem_value *ucontrol)
  734. {
  735. int ch_num = slim_get_port_idx(kcontrol);
  736. if (ch_num < 0)
  737. return ch_num;
  738. ucontrol->value.enumerated.item[0] =
  739. slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
  740. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  741. ch_num, slim_rx_cfg[ch_num].sample_rate,
  742. ucontrol->value.enumerated.item[0]);
  743. return 0;
  744. }
  745. static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  746. struct snd_ctl_elem_value *ucontrol)
  747. {
  748. int ch_num = slim_get_port_idx(kcontrol);
  749. if (ch_num < 0)
  750. return ch_num;
  751. slim_rx_cfg[ch_num].sample_rate =
  752. slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  753. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  754. ch_num, slim_rx_cfg[ch_num].sample_rate,
  755. ucontrol->value.enumerated.item[0]);
  756. return 0;
  757. }
  758. static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  759. struct snd_ctl_elem_value *ucontrol)
  760. {
  761. int ch_num = slim_get_port_idx(kcontrol);
  762. if (ch_num < 0)
  763. return ch_num;
  764. ucontrol->value.enumerated.item[0] =
  765. slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
  766. pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  767. ch_num, slim_tx_cfg[ch_num].sample_rate,
  768. ucontrol->value.enumerated.item[0]);
  769. return 0;
  770. }
  771. static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  772. struct snd_ctl_elem_value *ucontrol)
  773. {
  774. int sample_rate = 0;
  775. int ch_num = slim_get_port_idx(kcontrol);
  776. if (ch_num < 0)
  777. return ch_num;
  778. sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  779. if (sample_rate == SAMPLING_RATE_44P1KHZ) {
  780. pr_err("%s: Unsupported sample rate %d: for Tx path\n",
  781. __func__, sample_rate);
  782. return -EINVAL;
  783. }
  784. slim_tx_cfg[ch_num].sample_rate = sample_rate;
  785. pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
  786. ch_num, slim_tx_cfg[ch_num].sample_rate,
  787. ucontrol->value.enumerated.item[0]);
  788. return 0;
  789. }
  790. static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
  791. struct snd_ctl_elem_value *ucontrol)
  792. {
  793. int ch_num = slim_get_port_idx(kcontrol);
  794. if (ch_num < 0)
  795. return ch_num;
  796. ucontrol->value.enumerated.item[0] =
  797. slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
  798. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  799. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  800. ucontrol->value.enumerated.item[0]);
  801. return 0;
  802. }
  803. static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
  804. struct snd_ctl_elem_value *ucontrol)
  805. {
  806. int ch_num = slim_get_port_idx(kcontrol);
  807. if (ch_num < 0)
  808. return ch_num;
  809. slim_rx_cfg[ch_num].bit_format =
  810. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  811. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  812. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  813. ucontrol->value.enumerated.item[0]);
  814. return 0;
  815. }
  816. static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
  817. struct snd_ctl_elem_value *ucontrol)
  818. {
  819. int ch_num = slim_get_port_idx(kcontrol);
  820. if (ch_num < 0)
  821. return ch_num;
  822. ucontrol->value.enumerated.item[0] =
  823. slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
  824. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  825. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  826. ucontrol->value.enumerated.item[0]);
  827. return 0;
  828. }
  829. static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
  830. struct snd_ctl_elem_value *ucontrol)
  831. {
  832. int ch_num = slim_get_port_idx(kcontrol);
  833. if (ch_num < 0)
  834. return ch_num;
  835. slim_tx_cfg[ch_num].bit_format =
  836. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  837. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  838. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  839. ucontrol->value.enumerated.item[0]);
  840. return 0;
  841. }
  842. static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
  843. struct snd_ctl_elem_value *ucontrol)
  844. {
  845. int ch_num = slim_get_port_idx(kcontrol);
  846. if (ch_num < 0)
  847. return ch_num;
  848. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  849. ch_num, slim_rx_cfg[ch_num].channels);
  850. ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
  851. return 0;
  852. }
  853. static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
  854. struct snd_ctl_elem_value *ucontrol)
  855. {
  856. int ch_num = slim_get_port_idx(kcontrol);
  857. if (ch_num < 0)
  858. return ch_num;
  859. slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  860. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  861. ch_num, slim_rx_cfg[ch_num].channels);
  862. return 1;
  863. }
  864. static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
  865. struct snd_ctl_elem_value *ucontrol)
  866. {
  867. int ch_num = slim_get_port_idx(kcontrol);
  868. if (ch_num < 0)
  869. return ch_num;
  870. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  871. ch_num, slim_tx_cfg[ch_num].channels);
  872. ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
  873. return 0;
  874. }
  875. static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
  876. struct snd_ctl_elem_value *ucontrol)
  877. {
  878. int ch_num = slim_get_port_idx(kcontrol);
  879. if (ch_num < 0)
  880. return ch_num;
  881. slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  882. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  883. ch_num, slim_tx_cfg[ch_num].channels);
  884. return 1;
  885. }
  886. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  887. struct snd_ctl_elem_value *ucontrol)
  888. {
  889. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  890. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  891. ucontrol->value.integer.value[0]);
  892. return 0;
  893. }
  894. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  895. struct snd_ctl_elem_value *ucontrol)
  896. {
  897. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  898. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  899. return 1;
  900. }
  901. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  902. struct snd_ctl_elem_value *ucontrol)
  903. {
  904. /*
  905. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  906. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  907. * value.
  908. */
  909. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  910. case SAMPLING_RATE_96KHZ:
  911. ucontrol->value.integer.value[0] = 5;
  912. break;
  913. case SAMPLING_RATE_88P2KHZ:
  914. ucontrol->value.integer.value[0] = 4;
  915. break;
  916. case SAMPLING_RATE_48KHZ:
  917. ucontrol->value.integer.value[0] = 3;
  918. break;
  919. case SAMPLING_RATE_44P1KHZ:
  920. ucontrol->value.integer.value[0] = 2;
  921. break;
  922. case SAMPLING_RATE_16KHZ:
  923. ucontrol->value.integer.value[0] = 1;
  924. break;
  925. case SAMPLING_RATE_8KHZ:
  926. default:
  927. ucontrol->value.integer.value[0] = 0;
  928. break;
  929. }
  930. pr_debug("%s: sample rate = %d", __func__,
  931. slim_rx_cfg[SLIM_RX_7].sample_rate);
  932. return 0;
  933. }
  934. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  935. struct snd_ctl_elem_value *ucontrol)
  936. {
  937. switch (ucontrol->value.integer.value[0]) {
  938. case 1:
  939. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  940. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  941. break;
  942. case 2:
  943. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  944. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  945. break;
  946. case 3:
  947. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  948. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  949. break;
  950. case 4:
  951. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  952. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  953. break;
  954. case 5:
  955. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  956. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  957. break;
  958. case 0:
  959. default:
  960. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  961. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  962. break;
  963. }
  964. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  965. __func__,
  966. slim_rx_cfg[SLIM_RX_7].sample_rate,
  967. slim_tx_cfg[SLIM_TX_7].sample_rate,
  968. ucontrol->value.enumerated.item[0]);
  969. return 0;
  970. }
  971. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  972. {
  973. int idx = 0;
  974. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  975. sizeof("WSA_CDC_DMA_RX_0")))
  976. idx = WSA_CDC_DMA_RX_0;
  977. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  978. sizeof("WSA_CDC_DMA_RX_0")))
  979. idx = WSA_CDC_DMA_RX_1;
  980. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  981. sizeof("WSA_CDC_DMA_TX_0")))
  982. idx = WSA_CDC_DMA_TX_0;
  983. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  984. sizeof("WSA_CDC_DMA_TX_1")))
  985. idx = WSA_CDC_DMA_TX_1;
  986. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  987. sizeof("WSA_CDC_DMA_TX_2")))
  988. idx = WSA_CDC_DMA_TX_2;
  989. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  990. sizeof("VA_CDC_DMA_TX_0")))
  991. idx = VA_CDC_DMA_TX_0;
  992. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  993. sizeof("VA_CDC_DMA_TX_1")))
  994. idx = VA_CDC_DMA_TX_1;
  995. else {
  996. pr_err("%s: unsupported port: %s\n",
  997. __func__, kcontrol->id.name);
  998. return -EINVAL;
  999. }
  1000. return idx;
  1001. }
  1002. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  1003. struct snd_ctl_elem_value *ucontrol)
  1004. {
  1005. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1006. if (ch_num < 0)
  1007. return ch_num;
  1008. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1009. cdc_dma_rx_cfg[ch_num].channels - 1);
  1010. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1011. return 0;
  1012. }
  1013. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1014. struct snd_ctl_elem_value *ucontrol)
  1015. {
  1016. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1017. if (ch_num < 0)
  1018. return ch_num;
  1019. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1020. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1021. cdc_dma_rx_cfg[ch_num].channels);
  1022. return 1;
  1023. }
  1024. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1025. struct snd_ctl_elem_value *ucontrol)
  1026. {
  1027. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1028. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1029. case SNDRV_PCM_FORMAT_S32_LE:
  1030. ucontrol->value.integer.value[0] = 3;
  1031. break;
  1032. case SNDRV_PCM_FORMAT_S24_3LE:
  1033. ucontrol->value.integer.value[0] = 2;
  1034. break;
  1035. case SNDRV_PCM_FORMAT_S24_LE:
  1036. ucontrol->value.integer.value[0] = 1;
  1037. break;
  1038. case SNDRV_PCM_FORMAT_S16_LE:
  1039. default:
  1040. ucontrol->value.integer.value[0] = 0;
  1041. break;
  1042. }
  1043. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1044. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1045. ucontrol->value.integer.value[0]);
  1046. return 0;
  1047. }
  1048. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1049. struct snd_ctl_elem_value *ucontrol)
  1050. {
  1051. int rc = 0;
  1052. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1053. switch (ucontrol->value.integer.value[0]) {
  1054. case 3:
  1055. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1056. break;
  1057. case 2:
  1058. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1059. break;
  1060. case 1:
  1061. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1062. break;
  1063. case 0:
  1064. default:
  1065. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1066. break;
  1067. }
  1068. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1069. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1070. ucontrol->value.integer.value[0]);
  1071. return rc;
  1072. }
  1073. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1074. {
  1075. int sample_rate_val = 0;
  1076. switch (sample_rate) {
  1077. case SAMPLING_RATE_8KHZ:
  1078. sample_rate_val = 0;
  1079. break;
  1080. case SAMPLING_RATE_16KHZ:
  1081. sample_rate_val = 1;
  1082. break;
  1083. case SAMPLING_RATE_32KHZ:
  1084. sample_rate_val = 2;
  1085. break;
  1086. case SAMPLING_RATE_44P1KHZ:
  1087. sample_rate_val = 3;
  1088. break;
  1089. case SAMPLING_RATE_48KHZ:
  1090. sample_rate_val = 4;
  1091. break;
  1092. case SAMPLING_RATE_88P2KHZ:
  1093. sample_rate_val = 5;
  1094. break;
  1095. case SAMPLING_RATE_96KHZ:
  1096. sample_rate_val = 6;
  1097. break;
  1098. case SAMPLING_RATE_176P4KHZ:
  1099. sample_rate_val = 7;
  1100. break;
  1101. case SAMPLING_RATE_192KHZ:
  1102. sample_rate_val = 8;
  1103. break;
  1104. case SAMPLING_RATE_352P8KHZ:
  1105. sample_rate_val = 9;
  1106. break;
  1107. case SAMPLING_RATE_384KHZ:
  1108. sample_rate_val = 10;
  1109. break;
  1110. default:
  1111. sample_rate_val = 4;
  1112. break;
  1113. }
  1114. return sample_rate_val;
  1115. }
  1116. static int cdc_dma_get_sample_rate(int value)
  1117. {
  1118. int sample_rate = 0;
  1119. switch (value) {
  1120. case 0:
  1121. sample_rate = SAMPLING_RATE_8KHZ;
  1122. break;
  1123. case 1:
  1124. sample_rate = SAMPLING_RATE_16KHZ;
  1125. break;
  1126. case 2:
  1127. sample_rate = SAMPLING_RATE_32KHZ;
  1128. break;
  1129. case 3:
  1130. sample_rate = SAMPLING_RATE_44P1KHZ;
  1131. break;
  1132. case 4:
  1133. sample_rate = SAMPLING_RATE_48KHZ;
  1134. break;
  1135. case 5:
  1136. sample_rate = SAMPLING_RATE_88P2KHZ;
  1137. break;
  1138. case 6:
  1139. sample_rate = SAMPLING_RATE_96KHZ;
  1140. break;
  1141. case 7:
  1142. sample_rate = SAMPLING_RATE_176P4KHZ;
  1143. break;
  1144. case 8:
  1145. sample_rate = SAMPLING_RATE_192KHZ;
  1146. break;
  1147. case 9:
  1148. sample_rate = SAMPLING_RATE_352P8KHZ;
  1149. break;
  1150. case 10:
  1151. sample_rate = SAMPLING_RATE_384KHZ;
  1152. break;
  1153. default:
  1154. sample_rate = SAMPLING_RATE_48KHZ;
  1155. break;
  1156. }
  1157. return sample_rate;
  1158. }
  1159. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1160. struct snd_ctl_elem_value *ucontrol)
  1161. {
  1162. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1163. if (ch_num < 0)
  1164. return ch_num;
  1165. ucontrol->value.enumerated.item[0] =
  1166. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  1167. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  1168. cdc_dma_rx_cfg[ch_num].sample_rate);
  1169. return 0;
  1170. }
  1171. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1172. struct snd_ctl_elem_value *ucontrol)
  1173. {
  1174. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1175. if (ch_num < 0)
  1176. return ch_num;
  1177. cdc_dma_rx_cfg[ch_num].sample_rate =
  1178. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1179. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  1180. __func__, ucontrol->value.enumerated.item[0],
  1181. cdc_dma_rx_cfg[ch_num].sample_rate);
  1182. return 0;
  1183. }
  1184. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  1185. struct snd_ctl_elem_value *ucontrol)
  1186. {
  1187. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1188. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1189. cdc_dma_tx_cfg[ch_num].channels);
  1190. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  1191. return 0;
  1192. }
  1193. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  1194. struct snd_ctl_elem_value *ucontrol)
  1195. {
  1196. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1197. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1198. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1199. cdc_dma_tx_cfg[ch_num].channels);
  1200. return 1;
  1201. }
  1202. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1203. struct snd_ctl_elem_value *ucontrol)
  1204. {
  1205. int sample_rate_val;
  1206. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1207. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  1208. case SAMPLING_RATE_384KHZ:
  1209. sample_rate_val = 12;
  1210. break;
  1211. case SAMPLING_RATE_352P8KHZ:
  1212. sample_rate_val = 11;
  1213. break;
  1214. case SAMPLING_RATE_192KHZ:
  1215. sample_rate_val = 10;
  1216. break;
  1217. case SAMPLING_RATE_176P4KHZ:
  1218. sample_rate_val = 9;
  1219. break;
  1220. case SAMPLING_RATE_96KHZ:
  1221. sample_rate_val = 8;
  1222. break;
  1223. case SAMPLING_RATE_88P2KHZ:
  1224. sample_rate_val = 7;
  1225. break;
  1226. case SAMPLING_RATE_48KHZ:
  1227. sample_rate_val = 6;
  1228. break;
  1229. case SAMPLING_RATE_44P1KHZ:
  1230. sample_rate_val = 5;
  1231. break;
  1232. case SAMPLING_RATE_32KHZ:
  1233. sample_rate_val = 4;
  1234. break;
  1235. case SAMPLING_RATE_22P05KHZ:
  1236. sample_rate_val = 3;
  1237. break;
  1238. case SAMPLING_RATE_16KHZ:
  1239. sample_rate_val = 2;
  1240. break;
  1241. case SAMPLING_RATE_11P025KHZ:
  1242. sample_rate_val = 1;
  1243. break;
  1244. case SAMPLING_RATE_8KHZ:
  1245. sample_rate_val = 0;
  1246. break;
  1247. default:
  1248. sample_rate_val = 6;
  1249. break;
  1250. }
  1251. ucontrol->value.integer.value[0] = sample_rate_val;
  1252. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  1253. cdc_dma_tx_cfg[ch_num].sample_rate);
  1254. return 0;
  1255. }
  1256. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1257. struct snd_ctl_elem_value *ucontrol)
  1258. {
  1259. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1260. switch (ucontrol->value.integer.value[0]) {
  1261. case 12:
  1262. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  1263. break;
  1264. case 11:
  1265. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  1266. break;
  1267. case 10:
  1268. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  1269. break;
  1270. case 9:
  1271. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  1272. break;
  1273. case 8:
  1274. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  1275. break;
  1276. case 7:
  1277. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  1278. break;
  1279. case 6:
  1280. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1281. break;
  1282. case 5:
  1283. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  1284. break;
  1285. case 4:
  1286. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  1287. break;
  1288. case 3:
  1289. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  1290. break;
  1291. case 2:
  1292. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  1293. break;
  1294. case 1:
  1295. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  1296. break;
  1297. case 0:
  1298. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  1299. break;
  1300. default:
  1301. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1302. break;
  1303. }
  1304. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  1305. __func__, ucontrol->value.integer.value[0],
  1306. cdc_dma_tx_cfg[ch_num].sample_rate);
  1307. return 0;
  1308. }
  1309. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  1310. struct snd_ctl_elem_value *ucontrol)
  1311. {
  1312. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1313. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  1314. case SNDRV_PCM_FORMAT_S32_LE:
  1315. ucontrol->value.integer.value[0] = 3;
  1316. break;
  1317. case SNDRV_PCM_FORMAT_S24_3LE:
  1318. ucontrol->value.integer.value[0] = 2;
  1319. break;
  1320. case SNDRV_PCM_FORMAT_S24_LE:
  1321. ucontrol->value.integer.value[0] = 1;
  1322. break;
  1323. case SNDRV_PCM_FORMAT_S16_LE:
  1324. default:
  1325. ucontrol->value.integer.value[0] = 0;
  1326. break;
  1327. }
  1328. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1329. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1330. ucontrol->value.integer.value[0]);
  1331. return 0;
  1332. }
  1333. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  1334. struct snd_ctl_elem_value *ucontrol)
  1335. {
  1336. int rc = 0;
  1337. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1338. switch (ucontrol->value.integer.value[0]) {
  1339. case 3:
  1340. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1341. break;
  1342. case 2:
  1343. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1344. break;
  1345. case 1:
  1346. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1347. break;
  1348. case 0:
  1349. default:
  1350. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1351. break;
  1352. }
  1353. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1354. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1355. ucontrol->value.integer.value[0]);
  1356. return rc;
  1357. }
  1358. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1359. struct snd_ctl_elem_value *ucontrol)
  1360. {
  1361. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1362. usb_rx_cfg.channels);
  1363. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1364. return 0;
  1365. }
  1366. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1367. struct snd_ctl_elem_value *ucontrol)
  1368. {
  1369. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1370. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1371. return 1;
  1372. }
  1373. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1374. struct snd_ctl_elem_value *ucontrol)
  1375. {
  1376. int sample_rate_val;
  1377. switch (usb_rx_cfg.sample_rate) {
  1378. case SAMPLING_RATE_384KHZ:
  1379. sample_rate_val = 12;
  1380. break;
  1381. case SAMPLING_RATE_352P8KHZ:
  1382. sample_rate_val = 11;
  1383. break;
  1384. case SAMPLING_RATE_192KHZ:
  1385. sample_rate_val = 10;
  1386. break;
  1387. case SAMPLING_RATE_176P4KHZ:
  1388. sample_rate_val = 9;
  1389. break;
  1390. case SAMPLING_RATE_96KHZ:
  1391. sample_rate_val = 8;
  1392. break;
  1393. case SAMPLING_RATE_88P2KHZ:
  1394. sample_rate_val = 7;
  1395. break;
  1396. case SAMPLING_RATE_48KHZ:
  1397. sample_rate_val = 6;
  1398. break;
  1399. case SAMPLING_RATE_44P1KHZ:
  1400. sample_rate_val = 5;
  1401. break;
  1402. case SAMPLING_RATE_32KHZ:
  1403. sample_rate_val = 4;
  1404. break;
  1405. case SAMPLING_RATE_22P05KHZ:
  1406. sample_rate_val = 3;
  1407. break;
  1408. case SAMPLING_RATE_16KHZ:
  1409. sample_rate_val = 2;
  1410. break;
  1411. case SAMPLING_RATE_11P025KHZ:
  1412. sample_rate_val = 1;
  1413. break;
  1414. case SAMPLING_RATE_8KHZ:
  1415. default:
  1416. sample_rate_val = 0;
  1417. break;
  1418. }
  1419. ucontrol->value.integer.value[0] = sample_rate_val;
  1420. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1421. usb_rx_cfg.sample_rate);
  1422. return 0;
  1423. }
  1424. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1425. struct snd_ctl_elem_value *ucontrol)
  1426. {
  1427. switch (ucontrol->value.integer.value[0]) {
  1428. case 12:
  1429. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1430. break;
  1431. case 11:
  1432. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1433. break;
  1434. case 10:
  1435. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1436. break;
  1437. case 9:
  1438. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1439. break;
  1440. case 8:
  1441. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1442. break;
  1443. case 7:
  1444. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1445. break;
  1446. case 6:
  1447. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1448. break;
  1449. case 5:
  1450. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1451. break;
  1452. case 4:
  1453. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1454. break;
  1455. case 3:
  1456. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1457. break;
  1458. case 2:
  1459. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1460. break;
  1461. case 1:
  1462. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1463. break;
  1464. case 0:
  1465. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1466. break;
  1467. default:
  1468. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1469. break;
  1470. }
  1471. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1472. __func__, ucontrol->value.integer.value[0],
  1473. usb_rx_cfg.sample_rate);
  1474. return 0;
  1475. }
  1476. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1477. struct snd_ctl_elem_value *ucontrol)
  1478. {
  1479. switch (usb_rx_cfg.bit_format) {
  1480. case SNDRV_PCM_FORMAT_S32_LE:
  1481. ucontrol->value.integer.value[0] = 3;
  1482. break;
  1483. case SNDRV_PCM_FORMAT_S24_3LE:
  1484. ucontrol->value.integer.value[0] = 2;
  1485. break;
  1486. case SNDRV_PCM_FORMAT_S24_LE:
  1487. ucontrol->value.integer.value[0] = 1;
  1488. break;
  1489. case SNDRV_PCM_FORMAT_S16_LE:
  1490. default:
  1491. ucontrol->value.integer.value[0] = 0;
  1492. break;
  1493. }
  1494. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1495. __func__, usb_rx_cfg.bit_format,
  1496. ucontrol->value.integer.value[0]);
  1497. return 0;
  1498. }
  1499. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1500. struct snd_ctl_elem_value *ucontrol)
  1501. {
  1502. int rc = 0;
  1503. switch (ucontrol->value.integer.value[0]) {
  1504. case 3:
  1505. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1506. break;
  1507. case 2:
  1508. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1509. break;
  1510. case 1:
  1511. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1512. break;
  1513. case 0:
  1514. default:
  1515. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1516. break;
  1517. }
  1518. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1519. __func__, usb_rx_cfg.bit_format,
  1520. ucontrol->value.integer.value[0]);
  1521. return rc;
  1522. }
  1523. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1524. struct snd_ctl_elem_value *ucontrol)
  1525. {
  1526. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1527. usb_tx_cfg.channels);
  1528. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1529. return 0;
  1530. }
  1531. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1532. struct snd_ctl_elem_value *ucontrol)
  1533. {
  1534. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1535. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1536. return 1;
  1537. }
  1538. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1539. struct snd_ctl_elem_value *ucontrol)
  1540. {
  1541. int sample_rate_val;
  1542. switch (usb_tx_cfg.sample_rate) {
  1543. case SAMPLING_RATE_384KHZ:
  1544. sample_rate_val = 12;
  1545. break;
  1546. case SAMPLING_RATE_352P8KHZ:
  1547. sample_rate_val = 11;
  1548. break;
  1549. case SAMPLING_RATE_192KHZ:
  1550. sample_rate_val = 10;
  1551. break;
  1552. case SAMPLING_RATE_176P4KHZ:
  1553. sample_rate_val = 9;
  1554. break;
  1555. case SAMPLING_RATE_96KHZ:
  1556. sample_rate_val = 8;
  1557. break;
  1558. case SAMPLING_RATE_88P2KHZ:
  1559. sample_rate_val = 7;
  1560. break;
  1561. case SAMPLING_RATE_48KHZ:
  1562. sample_rate_val = 6;
  1563. break;
  1564. case SAMPLING_RATE_44P1KHZ:
  1565. sample_rate_val = 5;
  1566. break;
  1567. case SAMPLING_RATE_32KHZ:
  1568. sample_rate_val = 4;
  1569. break;
  1570. case SAMPLING_RATE_22P05KHZ:
  1571. sample_rate_val = 3;
  1572. break;
  1573. case SAMPLING_RATE_16KHZ:
  1574. sample_rate_val = 2;
  1575. break;
  1576. case SAMPLING_RATE_11P025KHZ:
  1577. sample_rate_val = 1;
  1578. break;
  1579. case SAMPLING_RATE_8KHZ:
  1580. sample_rate_val = 0;
  1581. break;
  1582. default:
  1583. sample_rate_val = 6;
  1584. break;
  1585. }
  1586. ucontrol->value.integer.value[0] = sample_rate_val;
  1587. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1588. usb_tx_cfg.sample_rate);
  1589. return 0;
  1590. }
  1591. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1592. struct snd_ctl_elem_value *ucontrol)
  1593. {
  1594. switch (ucontrol->value.integer.value[0]) {
  1595. case 12:
  1596. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1597. break;
  1598. case 11:
  1599. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1600. break;
  1601. case 10:
  1602. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1603. break;
  1604. case 9:
  1605. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1606. break;
  1607. case 8:
  1608. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1609. break;
  1610. case 7:
  1611. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1612. break;
  1613. case 6:
  1614. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1615. break;
  1616. case 5:
  1617. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1618. break;
  1619. case 4:
  1620. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1621. break;
  1622. case 3:
  1623. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1624. break;
  1625. case 2:
  1626. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1627. break;
  1628. case 1:
  1629. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1630. break;
  1631. case 0:
  1632. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1633. break;
  1634. default:
  1635. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1636. break;
  1637. }
  1638. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1639. __func__, ucontrol->value.integer.value[0],
  1640. usb_tx_cfg.sample_rate);
  1641. return 0;
  1642. }
  1643. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1644. struct snd_ctl_elem_value *ucontrol)
  1645. {
  1646. switch (usb_tx_cfg.bit_format) {
  1647. case SNDRV_PCM_FORMAT_S32_LE:
  1648. ucontrol->value.integer.value[0] = 3;
  1649. break;
  1650. case SNDRV_PCM_FORMAT_S24_3LE:
  1651. ucontrol->value.integer.value[0] = 2;
  1652. break;
  1653. case SNDRV_PCM_FORMAT_S24_LE:
  1654. ucontrol->value.integer.value[0] = 1;
  1655. break;
  1656. case SNDRV_PCM_FORMAT_S16_LE:
  1657. default:
  1658. ucontrol->value.integer.value[0] = 0;
  1659. break;
  1660. }
  1661. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1662. __func__, usb_tx_cfg.bit_format,
  1663. ucontrol->value.integer.value[0]);
  1664. return 0;
  1665. }
  1666. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1667. struct snd_ctl_elem_value *ucontrol)
  1668. {
  1669. int rc = 0;
  1670. switch (ucontrol->value.integer.value[0]) {
  1671. case 3:
  1672. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1673. break;
  1674. case 2:
  1675. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1676. break;
  1677. case 1:
  1678. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1679. break;
  1680. case 0:
  1681. default:
  1682. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1683. break;
  1684. }
  1685. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1686. __func__, usb_tx_cfg.bit_format,
  1687. ucontrol->value.integer.value[0]);
  1688. return rc;
  1689. }
  1690. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1691. struct snd_ctl_elem_value *ucontrol)
  1692. {
  1693. pr_debug("%s: proxy_rx channels = %d\n",
  1694. __func__, proxy_rx_cfg.channels);
  1695. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1696. return 0;
  1697. }
  1698. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1699. struct snd_ctl_elem_value *ucontrol)
  1700. {
  1701. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1702. pr_debug("%s: proxy_rx channels = %d\n",
  1703. __func__, proxy_rx_cfg.channels);
  1704. return 1;
  1705. }
  1706. static int tdm_get_sample_rate(int value)
  1707. {
  1708. int sample_rate = 0;
  1709. switch (value) {
  1710. case 0:
  1711. sample_rate = SAMPLING_RATE_8KHZ;
  1712. break;
  1713. case 1:
  1714. sample_rate = SAMPLING_RATE_16KHZ;
  1715. break;
  1716. case 2:
  1717. sample_rate = SAMPLING_RATE_32KHZ;
  1718. break;
  1719. case 3:
  1720. sample_rate = SAMPLING_RATE_48KHZ;
  1721. break;
  1722. case 4:
  1723. sample_rate = SAMPLING_RATE_176P4KHZ;
  1724. break;
  1725. case 5:
  1726. sample_rate = SAMPLING_RATE_352P8KHZ;
  1727. break;
  1728. default:
  1729. sample_rate = SAMPLING_RATE_48KHZ;
  1730. break;
  1731. }
  1732. return sample_rate;
  1733. }
  1734. static int aux_pcm_get_sample_rate(int value)
  1735. {
  1736. int sample_rate;
  1737. switch (value) {
  1738. case 1:
  1739. sample_rate = SAMPLING_RATE_16KHZ;
  1740. break;
  1741. case 0:
  1742. default:
  1743. sample_rate = SAMPLING_RATE_8KHZ;
  1744. break;
  1745. }
  1746. return sample_rate;
  1747. }
  1748. static int tdm_get_sample_rate_val(int sample_rate)
  1749. {
  1750. int sample_rate_val = 0;
  1751. switch (sample_rate) {
  1752. case SAMPLING_RATE_8KHZ:
  1753. sample_rate_val = 0;
  1754. break;
  1755. case SAMPLING_RATE_16KHZ:
  1756. sample_rate_val = 1;
  1757. break;
  1758. case SAMPLING_RATE_32KHZ:
  1759. sample_rate_val = 2;
  1760. break;
  1761. case SAMPLING_RATE_48KHZ:
  1762. sample_rate_val = 3;
  1763. break;
  1764. case SAMPLING_RATE_176P4KHZ:
  1765. sample_rate_val = 4;
  1766. break;
  1767. case SAMPLING_RATE_352P8KHZ:
  1768. sample_rate_val = 5;
  1769. break;
  1770. default:
  1771. sample_rate_val = 3;
  1772. break;
  1773. }
  1774. return sample_rate_val;
  1775. }
  1776. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1777. {
  1778. int sample_rate_val;
  1779. switch (sample_rate) {
  1780. case SAMPLING_RATE_16KHZ:
  1781. sample_rate_val = 1;
  1782. break;
  1783. case SAMPLING_RATE_8KHZ:
  1784. default:
  1785. sample_rate_val = 0;
  1786. break;
  1787. }
  1788. return sample_rate_val;
  1789. }
  1790. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1791. struct tdm_port *port)
  1792. {
  1793. if (port) {
  1794. if (strnstr(kcontrol->id.name, "PRI",
  1795. sizeof(kcontrol->id.name))) {
  1796. port->mode = TDM_PRI;
  1797. } else if (strnstr(kcontrol->id.name, "SEC",
  1798. sizeof(kcontrol->id.name))) {
  1799. port->mode = TDM_SEC;
  1800. } else if (strnstr(kcontrol->id.name, "TERT",
  1801. sizeof(kcontrol->id.name))) {
  1802. port->mode = TDM_TERT;
  1803. } else if (strnstr(kcontrol->id.name, "QUAT",
  1804. sizeof(kcontrol->id.name))) {
  1805. port->mode = TDM_QUAT;
  1806. } else if (strnstr(kcontrol->id.name, "QUIN",
  1807. sizeof(kcontrol->id.name))) {
  1808. port->mode = TDM_QUIN;
  1809. } else {
  1810. pr_err("%s: unsupported mode in: %s",
  1811. __func__, kcontrol->id.name);
  1812. return -EINVAL;
  1813. }
  1814. if (strnstr(kcontrol->id.name, "RX_0",
  1815. sizeof(kcontrol->id.name)) ||
  1816. strnstr(kcontrol->id.name, "TX_0",
  1817. sizeof(kcontrol->id.name))) {
  1818. port->channel = TDM_0;
  1819. } else if (strnstr(kcontrol->id.name, "RX_1",
  1820. sizeof(kcontrol->id.name)) ||
  1821. strnstr(kcontrol->id.name, "TX_1",
  1822. sizeof(kcontrol->id.name))) {
  1823. port->channel = TDM_1;
  1824. } else if (strnstr(kcontrol->id.name, "RX_2",
  1825. sizeof(kcontrol->id.name)) ||
  1826. strnstr(kcontrol->id.name, "TX_2",
  1827. sizeof(kcontrol->id.name))) {
  1828. port->channel = TDM_2;
  1829. } else if (strnstr(kcontrol->id.name, "RX_3",
  1830. sizeof(kcontrol->id.name)) ||
  1831. strnstr(kcontrol->id.name, "TX_3",
  1832. sizeof(kcontrol->id.name))) {
  1833. port->channel = TDM_3;
  1834. } else if (strnstr(kcontrol->id.name, "RX_4",
  1835. sizeof(kcontrol->id.name)) ||
  1836. strnstr(kcontrol->id.name, "TX_4",
  1837. sizeof(kcontrol->id.name))) {
  1838. port->channel = TDM_4;
  1839. } else if (strnstr(kcontrol->id.name, "RX_5",
  1840. sizeof(kcontrol->id.name)) ||
  1841. strnstr(kcontrol->id.name, "TX_5",
  1842. sizeof(kcontrol->id.name))) {
  1843. port->channel = TDM_5;
  1844. } else if (strnstr(kcontrol->id.name, "RX_6",
  1845. sizeof(kcontrol->id.name)) ||
  1846. strnstr(kcontrol->id.name, "TX_6",
  1847. sizeof(kcontrol->id.name))) {
  1848. port->channel = TDM_6;
  1849. } else if (strnstr(kcontrol->id.name, "RX_7",
  1850. sizeof(kcontrol->id.name)) ||
  1851. strnstr(kcontrol->id.name, "TX_7",
  1852. sizeof(kcontrol->id.name))) {
  1853. port->channel = TDM_7;
  1854. } else {
  1855. pr_err("%s: unsupported channel in: %s",
  1856. __func__, kcontrol->id.name);
  1857. return -EINVAL;
  1858. }
  1859. } else
  1860. return -EINVAL;
  1861. return 0;
  1862. }
  1863. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1864. struct snd_ctl_elem_value *ucontrol)
  1865. {
  1866. struct tdm_port port;
  1867. int ret = tdm_get_port_idx(kcontrol, &port);
  1868. if (ret) {
  1869. pr_err("%s: unsupported control: %s",
  1870. __func__, kcontrol->id.name);
  1871. } else {
  1872. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1873. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1874. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1875. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1876. ucontrol->value.enumerated.item[0]);
  1877. }
  1878. return ret;
  1879. }
  1880. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1881. struct snd_ctl_elem_value *ucontrol)
  1882. {
  1883. struct tdm_port port;
  1884. int ret = tdm_get_port_idx(kcontrol, &port);
  1885. if (ret) {
  1886. pr_err("%s: unsupported control: %s",
  1887. __func__, kcontrol->id.name);
  1888. } else {
  1889. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1890. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1891. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1892. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1893. ucontrol->value.enumerated.item[0]);
  1894. }
  1895. return ret;
  1896. }
  1897. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1898. struct snd_ctl_elem_value *ucontrol)
  1899. {
  1900. struct tdm_port port;
  1901. int ret = tdm_get_port_idx(kcontrol, &port);
  1902. if (ret) {
  1903. pr_err("%s: unsupported control: %s",
  1904. __func__, kcontrol->id.name);
  1905. } else {
  1906. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1907. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1908. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1909. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1910. ucontrol->value.enumerated.item[0]);
  1911. }
  1912. return ret;
  1913. }
  1914. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1915. struct snd_ctl_elem_value *ucontrol)
  1916. {
  1917. struct tdm_port port;
  1918. int ret = tdm_get_port_idx(kcontrol, &port);
  1919. if (ret) {
  1920. pr_err("%s: unsupported control: %s",
  1921. __func__, kcontrol->id.name);
  1922. } else {
  1923. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1924. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1925. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1926. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1927. ucontrol->value.enumerated.item[0]);
  1928. }
  1929. return ret;
  1930. }
  1931. static int tdm_get_format(int value)
  1932. {
  1933. int format = 0;
  1934. switch (value) {
  1935. case 0:
  1936. format = SNDRV_PCM_FORMAT_S16_LE;
  1937. break;
  1938. case 1:
  1939. format = SNDRV_PCM_FORMAT_S24_LE;
  1940. break;
  1941. case 2:
  1942. format = SNDRV_PCM_FORMAT_S32_LE;
  1943. break;
  1944. default:
  1945. format = SNDRV_PCM_FORMAT_S16_LE;
  1946. break;
  1947. }
  1948. return format;
  1949. }
  1950. static int tdm_get_format_val(int format)
  1951. {
  1952. int value = 0;
  1953. switch (format) {
  1954. case SNDRV_PCM_FORMAT_S16_LE:
  1955. value = 0;
  1956. break;
  1957. case SNDRV_PCM_FORMAT_S24_LE:
  1958. value = 1;
  1959. break;
  1960. case SNDRV_PCM_FORMAT_S32_LE:
  1961. value = 2;
  1962. break;
  1963. default:
  1964. value = 0;
  1965. break;
  1966. }
  1967. return value;
  1968. }
  1969. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  1970. struct snd_ctl_elem_value *ucontrol)
  1971. {
  1972. struct tdm_port port;
  1973. int ret = tdm_get_port_idx(kcontrol, &port);
  1974. if (ret) {
  1975. pr_err("%s: unsupported control: %s",
  1976. __func__, kcontrol->id.name);
  1977. } else {
  1978. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1979. tdm_rx_cfg[port.mode][port.channel].bit_format);
  1980. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1981. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1982. ucontrol->value.enumerated.item[0]);
  1983. }
  1984. return ret;
  1985. }
  1986. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  1987. struct snd_ctl_elem_value *ucontrol)
  1988. {
  1989. struct tdm_port port;
  1990. int ret = tdm_get_port_idx(kcontrol, &port);
  1991. if (ret) {
  1992. pr_err("%s: unsupported control: %s",
  1993. __func__, kcontrol->id.name);
  1994. } else {
  1995. tdm_rx_cfg[port.mode][port.channel].bit_format =
  1996. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1997. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1998. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1999. ucontrol->value.enumerated.item[0]);
  2000. }
  2001. return ret;
  2002. }
  2003. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  2004. struct snd_ctl_elem_value *ucontrol)
  2005. {
  2006. struct tdm_port port;
  2007. int ret = tdm_get_port_idx(kcontrol, &port);
  2008. if (ret) {
  2009. pr_err("%s: unsupported control: %s",
  2010. __func__, kcontrol->id.name);
  2011. } else {
  2012. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2013. tdm_tx_cfg[port.mode][port.channel].bit_format);
  2014. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2015. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2016. ucontrol->value.enumerated.item[0]);
  2017. }
  2018. return ret;
  2019. }
  2020. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  2021. struct snd_ctl_elem_value *ucontrol)
  2022. {
  2023. struct tdm_port port;
  2024. int ret = tdm_get_port_idx(kcontrol, &port);
  2025. if (ret) {
  2026. pr_err("%s: unsupported control: %s",
  2027. __func__, kcontrol->id.name);
  2028. } else {
  2029. tdm_tx_cfg[port.mode][port.channel].bit_format =
  2030. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2031. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2032. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2033. ucontrol->value.enumerated.item[0]);
  2034. }
  2035. return ret;
  2036. }
  2037. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  2038. struct snd_ctl_elem_value *ucontrol)
  2039. {
  2040. struct tdm_port port;
  2041. int ret = tdm_get_port_idx(kcontrol, &port);
  2042. if (ret) {
  2043. pr_err("%s: unsupported control: %s",
  2044. __func__, kcontrol->id.name);
  2045. } else {
  2046. ucontrol->value.enumerated.item[0] =
  2047. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  2048. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2049. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  2050. ucontrol->value.enumerated.item[0]);
  2051. }
  2052. return ret;
  2053. }
  2054. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  2055. struct snd_ctl_elem_value *ucontrol)
  2056. {
  2057. struct tdm_port port;
  2058. int ret = tdm_get_port_idx(kcontrol, &port);
  2059. if (ret) {
  2060. pr_err("%s: unsupported control: %s",
  2061. __func__, kcontrol->id.name);
  2062. } else {
  2063. tdm_rx_cfg[port.mode][port.channel].channels =
  2064. ucontrol->value.enumerated.item[0] + 1;
  2065. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2066. tdm_rx_cfg[port.mode][port.channel].channels,
  2067. ucontrol->value.enumerated.item[0] + 1);
  2068. }
  2069. return ret;
  2070. }
  2071. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  2072. struct snd_ctl_elem_value *ucontrol)
  2073. {
  2074. struct tdm_port port;
  2075. int ret = tdm_get_port_idx(kcontrol, &port);
  2076. if (ret) {
  2077. pr_err("%s: unsupported control: %s",
  2078. __func__, kcontrol->id.name);
  2079. } else {
  2080. ucontrol->value.enumerated.item[0] =
  2081. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  2082. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2083. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  2084. ucontrol->value.enumerated.item[0]);
  2085. }
  2086. return ret;
  2087. }
  2088. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  2089. struct snd_ctl_elem_value *ucontrol)
  2090. {
  2091. struct tdm_port port;
  2092. int ret = tdm_get_port_idx(kcontrol, &port);
  2093. if (ret) {
  2094. pr_err("%s: unsupported control: %s",
  2095. __func__, kcontrol->id.name);
  2096. } else {
  2097. tdm_tx_cfg[port.mode][port.channel].channels =
  2098. ucontrol->value.enumerated.item[0] + 1;
  2099. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2100. tdm_tx_cfg[port.mode][port.channel].channels,
  2101. ucontrol->value.enumerated.item[0] + 1);
  2102. }
  2103. return ret;
  2104. }
  2105. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  2106. {
  2107. int idx;
  2108. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  2109. sizeof("PRIM_AUX_PCM")))
  2110. idx = PRIM_AUX_PCM;
  2111. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  2112. sizeof("SEC_AUX_PCM")))
  2113. idx = SEC_AUX_PCM;
  2114. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  2115. sizeof("TERT_AUX_PCM")))
  2116. idx = TERT_AUX_PCM;
  2117. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  2118. sizeof("QUAT_AUX_PCM")))
  2119. idx = QUAT_AUX_PCM;
  2120. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  2121. sizeof("QUIN_AUX_PCM")))
  2122. idx = QUIN_AUX_PCM;
  2123. else {
  2124. pr_err("%s: unsupported port: %s",
  2125. __func__, kcontrol->id.name);
  2126. idx = -EINVAL;
  2127. }
  2128. return idx;
  2129. }
  2130. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2131. struct snd_ctl_elem_value *ucontrol)
  2132. {
  2133. int idx = aux_pcm_get_port_idx(kcontrol);
  2134. if (idx < 0)
  2135. return idx;
  2136. aux_pcm_rx_cfg[idx].sample_rate =
  2137. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2138. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2139. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2140. ucontrol->value.enumerated.item[0]);
  2141. return 0;
  2142. }
  2143. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2144. struct snd_ctl_elem_value *ucontrol)
  2145. {
  2146. int idx = aux_pcm_get_port_idx(kcontrol);
  2147. if (idx < 0)
  2148. return idx;
  2149. ucontrol->value.enumerated.item[0] =
  2150. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  2151. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2152. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2153. ucontrol->value.enumerated.item[0]);
  2154. return 0;
  2155. }
  2156. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2157. struct snd_ctl_elem_value *ucontrol)
  2158. {
  2159. int idx = aux_pcm_get_port_idx(kcontrol);
  2160. if (idx < 0)
  2161. return idx;
  2162. aux_pcm_tx_cfg[idx].sample_rate =
  2163. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2164. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2165. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2166. ucontrol->value.enumerated.item[0]);
  2167. return 0;
  2168. }
  2169. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2170. struct snd_ctl_elem_value *ucontrol)
  2171. {
  2172. int idx = aux_pcm_get_port_idx(kcontrol);
  2173. if (idx < 0)
  2174. return idx;
  2175. ucontrol->value.enumerated.item[0] =
  2176. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  2177. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2178. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2179. ucontrol->value.enumerated.item[0]);
  2180. return 0;
  2181. }
  2182. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2183. {
  2184. int idx;
  2185. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2186. sizeof("PRIM_MI2S_RX")))
  2187. idx = PRIM_MI2S;
  2188. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2189. sizeof("SEC_MI2S_RX")))
  2190. idx = SEC_MI2S;
  2191. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2192. sizeof("TERT_MI2S_RX")))
  2193. idx = TERT_MI2S;
  2194. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2195. sizeof("QUAT_MI2S_RX")))
  2196. idx = QUAT_MI2S;
  2197. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2198. sizeof("QUIN_MI2S_RX")))
  2199. idx = QUIN_MI2S;
  2200. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2201. sizeof("PRIM_MI2S_TX")))
  2202. idx = PRIM_MI2S;
  2203. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2204. sizeof("SEC_MI2S_TX")))
  2205. idx = SEC_MI2S;
  2206. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2207. sizeof("TERT_MI2S_TX")))
  2208. idx = TERT_MI2S;
  2209. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2210. sizeof("QUAT_MI2S_TX")))
  2211. idx = QUAT_MI2S;
  2212. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2213. sizeof("QUIN_MI2S_TX")))
  2214. idx = QUIN_MI2S;
  2215. else {
  2216. pr_err("%s: unsupported channel: %s",
  2217. __func__, kcontrol->id.name);
  2218. idx = -EINVAL;
  2219. }
  2220. return idx;
  2221. }
  2222. static int mi2s_get_sample_rate_val(int sample_rate)
  2223. {
  2224. int sample_rate_val;
  2225. switch (sample_rate) {
  2226. case SAMPLING_RATE_8KHZ:
  2227. sample_rate_val = 0;
  2228. break;
  2229. case SAMPLING_RATE_11P025KHZ:
  2230. sample_rate_val = 1;
  2231. break;
  2232. case SAMPLING_RATE_16KHZ:
  2233. sample_rate_val = 2;
  2234. break;
  2235. case SAMPLING_RATE_22P05KHZ:
  2236. sample_rate_val = 3;
  2237. break;
  2238. case SAMPLING_RATE_32KHZ:
  2239. sample_rate_val = 4;
  2240. break;
  2241. case SAMPLING_RATE_44P1KHZ:
  2242. sample_rate_val = 5;
  2243. break;
  2244. case SAMPLING_RATE_48KHZ:
  2245. sample_rate_val = 6;
  2246. break;
  2247. case SAMPLING_RATE_96KHZ:
  2248. sample_rate_val = 7;
  2249. break;
  2250. case SAMPLING_RATE_192KHZ:
  2251. sample_rate_val = 8;
  2252. break;
  2253. default:
  2254. sample_rate_val = 6;
  2255. break;
  2256. }
  2257. return sample_rate_val;
  2258. }
  2259. static int mi2s_get_sample_rate(int value)
  2260. {
  2261. int sample_rate;
  2262. switch (value) {
  2263. case 0:
  2264. sample_rate = SAMPLING_RATE_8KHZ;
  2265. break;
  2266. case 1:
  2267. sample_rate = SAMPLING_RATE_11P025KHZ;
  2268. break;
  2269. case 2:
  2270. sample_rate = SAMPLING_RATE_16KHZ;
  2271. break;
  2272. case 3:
  2273. sample_rate = SAMPLING_RATE_22P05KHZ;
  2274. break;
  2275. case 4:
  2276. sample_rate = SAMPLING_RATE_32KHZ;
  2277. break;
  2278. case 5:
  2279. sample_rate = SAMPLING_RATE_44P1KHZ;
  2280. break;
  2281. case 6:
  2282. sample_rate = SAMPLING_RATE_48KHZ;
  2283. break;
  2284. case 7:
  2285. sample_rate = SAMPLING_RATE_96KHZ;
  2286. break;
  2287. case 8:
  2288. sample_rate = SAMPLING_RATE_192KHZ;
  2289. break;
  2290. default:
  2291. sample_rate = SAMPLING_RATE_48KHZ;
  2292. break;
  2293. }
  2294. return sample_rate;
  2295. }
  2296. static int mi2s_auxpcm_get_format(int value)
  2297. {
  2298. int format;
  2299. switch (value) {
  2300. case 0:
  2301. format = SNDRV_PCM_FORMAT_S16_LE;
  2302. break;
  2303. case 1:
  2304. format = SNDRV_PCM_FORMAT_S24_LE;
  2305. break;
  2306. case 2:
  2307. format = SNDRV_PCM_FORMAT_S24_3LE;
  2308. break;
  2309. case 3:
  2310. format = SNDRV_PCM_FORMAT_S32_LE;
  2311. break;
  2312. default:
  2313. format = SNDRV_PCM_FORMAT_S16_LE;
  2314. break;
  2315. }
  2316. return format;
  2317. }
  2318. static int mi2s_auxpcm_get_format_value(int format)
  2319. {
  2320. int value;
  2321. switch (format) {
  2322. case SNDRV_PCM_FORMAT_S16_LE:
  2323. value = 0;
  2324. break;
  2325. case SNDRV_PCM_FORMAT_S24_LE:
  2326. value = 1;
  2327. break;
  2328. case SNDRV_PCM_FORMAT_S24_3LE:
  2329. value = 2;
  2330. break;
  2331. case SNDRV_PCM_FORMAT_S32_LE:
  2332. value = 3;
  2333. break;
  2334. default:
  2335. value = 0;
  2336. break;
  2337. }
  2338. return value;
  2339. }
  2340. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2341. struct snd_ctl_elem_value *ucontrol)
  2342. {
  2343. int idx = mi2s_get_port_idx(kcontrol);
  2344. if (idx < 0)
  2345. return idx;
  2346. mi2s_rx_cfg[idx].sample_rate =
  2347. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2348. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2349. idx, mi2s_rx_cfg[idx].sample_rate,
  2350. ucontrol->value.enumerated.item[0]);
  2351. return 0;
  2352. }
  2353. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2354. struct snd_ctl_elem_value *ucontrol)
  2355. {
  2356. int idx = mi2s_get_port_idx(kcontrol);
  2357. if (idx < 0)
  2358. return idx;
  2359. ucontrol->value.enumerated.item[0] =
  2360. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2361. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2362. idx, mi2s_rx_cfg[idx].sample_rate,
  2363. ucontrol->value.enumerated.item[0]);
  2364. return 0;
  2365. }
  2366. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2367. struct snd_ctl_elem_value *ucontrol)
  2368. {
  2369. int idx = mi2s_get_port_idx(kcontrol);
  2370. if (idx < 0)
  2371. return idx;
  2372. mi2s_tx_cfg[idx].sample_rate =
  2373. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2374. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2375. idx, mi2s_tx_cfg[idx].sample_rate,
  2376. ucontrol->value.enumerated.item[0]);
  2377. return 0;
  2378. }
  2379. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2380. struct snd_ctl_elem_value *ucontrol)
  2381. {
  2382. int idx = mi2s_get_port_idx(kcontrol);
  2383. if (idx < 0)
  2384. return idx;
  2385. ucontrol->value.enumerated.item[0] =
  2386. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2387. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2388. idx, mi2s_tx_cfg[idx].sample_rate,
  2389. ucontrol->value.enumerated.item[0]);
  2390. return 0;
  2391. }
  2392. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2393. struct snd_ctl_elem_value *ucontrol)
  2394. {
  2395. int idx = mi2s_get_port_idx(kcontrol);
  2396. if (idx < 0)
  2397. return idx;
  2398. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2399. idx, mi2s_rx_cfg[idx].channels);
  2400. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2401. return 0;
  2402. }
  2403. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2404. struct snd_ctl_elem_value *ucontrol)
  2405. {
  2406. int idx = mi2s_get_port_idx(kcontrol);
  2407. if (idx < 0)
  2408. return idx;
  2409. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2410. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2411. idx, mi2s_rx_cfg[idx].channels);
  2412. return 1;
  2413. }
  2414. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2415. struct snd_ctl_elem_value *ucontrol)
  2416. {
  2417. int idx = mi2s_get_port_idx(kcontrol);
  2418. if (idx < 0)
  2419. return idx;
  2420. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2421. idx, mi2s_tx_cfg[idx].channels);
  2422. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2423. return 0;
  2424. }
  2425. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2426. struct snd_ctl_elem_value *ucontrol)
  2427. {
  2428. int idx = mi2s_get_port_idx(kcontrol);
  2429. if (idx < 0)
  2430. return idx;
  2431. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2432. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2433. idx, mi2s_tx_cfg[idx].channels);
  2434. return 1;
  2435. }
  2436. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2437. struct snd_ctl_elem_value *ucontrol)
  2438. {
  2439. int idx = mi2s_get_port_idx(kcontrol);
  2440. if (idx < 0)
  2441. return idx;
  2442. ucontrol->value.enumerated.item[0] =
  2443. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2444. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2445. idx, mi2s_rx_cfg[idx].bit_format,
  2446. ucontrol->value.enumerated.item[0]);
  2447. return 0;
  2448. }
  2449. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2450. struct snd_ctl_elem_value *ucontrol)
  2451. {
  2452. int idx = mi2s_get_port_idx(kcontrol);
  2453. if (idx < 0)
  2454. return idx;
  2455. mi2s_rx_cfg[idx].bit_format =
  2456. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2457. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2458. idx, mi2s_rx_cfg[idx].bit_format,
  2459. ucontrol->value.enumerated.item[0]);
  2460. return 0;
  2461. }
  2462. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2463. struct snd_ctl_elem_value *ucontrol)
  2464. {
  2465. int idx = mi2s_get_port_idx(kcontrol);
  2466. if (idx < 0)
  2467. return idx;
  2468. ucontrol->value.enumerated.item[0] =
  2469. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2470. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2471. idx, mi2s_tx_cfg[idx].bit_format,
  2472. ucontrol->value.enumerated.item[0]);
  2473. return 0;
  2474. }
  2475. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2476. struct snd_ctl_elem_value *ucontrol)
  2477. {
  2478. int idx = mi2s_get_port_idx(kcontrol);
  2479. if (idx < 0)
  2480. return idx;
  2481. mi2s_tx_cfg[idx].bit_format =
  2482. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2483. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2484. idx, mi2s_tx_cfg[idx].bit_format,
  2485. ucontrol->value.enumerated.item[0]);
  2486. return 0;
  2487. }
  2488. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  2489. struct snd_ctl_elem_value *ucontrol)
  2490. {
  2491. int idx = aux_pcm_get_port_idx(kcontrol);
  2492. if (idx < 0)
  2493. return idx;
  2494. ucontrol->value.enumerated.item[0] =
  2495. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  2496. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2497. idx, aux_pcm_rx_cfg[idx].bit_format,
  2498. ucontrol->value.enumerated.item[0]);
  2499. return 0;
  2500. }
  2501. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  2502. struct snd_ctl_elem_value *ucontrol)
  2503. {
  2504. int idx = aux_pcm_get_port_idx(kcontrol);
  2505. if (idx < 0)
  2506. return idx;
  2507. aux_pcm_rx_cfg[idx].bit_format =
  2508. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2509. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2510. idx, aux_pcm_rx_cfg[idx].bit_format,
  2511. ucontrol->value.enumerated.item[0]);
  2512. return 0;
  2513. }
  2514. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  2515. struct snd_ctl_elem_value *ucontrol)
  2516. {
  2517. int idx = aux_pcm_get_port_idx(kcontrol);
  2518. if (idx < 0)
  2519. return idx;
  2520. ucontrol->value.enumerated.item[0] =
  2521. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  2522. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2523. idx, aux_pcm_tx_cfg[idx].bit_format,
  2524. ucontrol->value.enumerated.item[0]);
  2525. return 0;
  2526. }
  2527. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  2528. struct snd_ctl_elem_value *ucontrol)
  2529. {
  2530. int idx = aux_pcm_get_port_idx(kcontrol);
  2531. if (idx < 0)
  2532. return idx;
  2533. aux_pcm_tx_cfg[idx].bit_format =
  2534. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2535. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2536. idx, aux_pcm_tx_cfg[idx].bit_format,
  2537. ucontrol->value.enumerated.item[0]);
  2538. return 0;
  2539. }
  2540. static const struct snd_kcontrol_new msm_snd_sb_controls[] = {
  2541. SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
  2542. slim_rx_ch_get, slim_rx_ch_put),
  2543. SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
  2544. slim_rx_ch_get, slim_rx_ch_put),
  2545. SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
  2546. slim_tx_ch_get, slim_tx_ch_put),
  2547. SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
  2548. slim_tx_ch_get, slim_tx_ch_put),
  2549. SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
  2550. slim_rx_ch_get, slim_rx_ch_put),
  2551. SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
  2552. slim_rx_ch_get, slim_rx_ch_put),
  2553. SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
  2554. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2555. SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
  2556. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2557. SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
  2558. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2559. SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
  2560. slim_tx_bit_format_get, slim_tx_bit_format_put),
  2561. SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
  2562. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2563. SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
  2564. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2565. SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
  2566. slim_tx_sample_rate_get, slim_tx_sample_rate_put),
  2567. SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
  2568. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2569. SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
  2570. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2571. };
  2572. static const struct snd_kcontrol_new msm_snd_va_controls[] = {
  2573. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2574. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2575. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2576. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2577. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2578. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2579. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2580. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2581. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2582. va_cdc_dma_tx_0_sample_rate,
  2583. cdc_dma_tx_sample_rate_get,
  2584. cdc_dma_tx_sample_rate_put),
  2585. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  2586. va_cdc_dma_tx_1_sample_rate,
  2587. cdc_dma_tx_sample_rate_get,
  2588. cdc_dma_tx_sample_rate_put),
  2589. };
  2590. static const struct snd_kcontrol_new msm_snd_wsa_controls[] = {
  2591. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  2592. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  2593. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  2594. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2595. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  2596. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2597. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  2598. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2599. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  2600. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2601. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  2602. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2603. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  2604. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2605. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  2606. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2607. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  2608. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2609. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  2610. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2611. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  2612. wsa_cdc_dma_rx_0_sample_rate,
  2613. cdc_dma_rx_sample_rate_get,
  2614. cdc_dma_rx_sample_rate_put),
  2615. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  2616. wsa_cdc_dma_rx_1_sample_rate,
  2617. cdc_dma_rx_sample_rate_get,
  2618. cdc_dma_rx_sample_rate_put),
  2619. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  2620. wsa_cdc_dma_tx_0_sample_rate,
  2621. cdc_dma_tx_sample_rate_get,
  2622. cdc_dma_tx_sample_rate_put),
  2623. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  2624. wsa_cdc_dma_tx_1_sample_rate,
  2625. cdc_dma_tx_sample_rate_get,
  2626. cdc_dma_tx_sample_rate_put),
  2627. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  2628. wsa_cdc_dma_tx_2_sample_rate,
  2629. cdc_dma_tx_sample_rate_get,
  2630. cdc_dma_tx_sample_rate_put),
  2631. };
  2632. static const struct snd_kcontrol_new msm_snd_controls[] = {
  2633. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  2634. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  2635. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  2636. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  2637. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  2638. proxy_rx_ch_get, proxy_rx_ch_put),
  2639. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  2640. usb_audio_rx_format_get, usb_audio_rx_format_put),
  2641. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  2642. usb_audio_tx_format_get, usb_audio_tx_format_put),
  2643. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  2644. msm_bt_sample_rate_get,
  2645. msm_bt_sample_rate_put),
  2646. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  2647. usb_audio_rx_sample_rate_get,
  2648. usb_audio_rx_sample_rate_put),
  2649. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  2650. usb_audio_tx_sample_rate_get,
  2651. usb_audio_tx_sample_rate_put),
  2652. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2653. tdm_rx_sample_rate_get,
  2654. tdm_rx_sample_rate_put),
  2655. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2656. tdm_tx_sample_rate_get,
  2657. tdm_tx_sample_rate_put),
  2658. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  2659. tdm_rx_format_get,
  2660. tdm_rx_format_put),
  2661. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  2662. tdm_tx_format_get,
  2663. tdm_tx_format_put),
  2664. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  2665. tdm_rx_ch_get,
  2666. tdm_rx_ch_put),
  2667. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  2668. tdm_tx_ch_get,
  2669. tdm_tx_ch_put),
  2670. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2671. tdm_rx_sample_rate_get,
  2672. tdm_rx_sample_rate_put),
  2673. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2674. tdm_tx_sample_rate_get,
  2675. tdm_tx_sample_rate_put),
  2676. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  2677. tdm_rx_format_get,
  2678. tdm_rx_format_put),
  2679. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  2680. tdm_tx_format_get,
  2681. tdm_tx_format_put),
  2682. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  2683. tdm_rx_ch_get,
  2684. tdm_rx_ch_put),
  2685. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  2686. tdm_tx_ch_get,
  2687. tdm_tx_ch_put),
  2688. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2689. tdm_rx_sample_rate_get,
  2690. tdm_rx_sample_rate_put),
  2691. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2692. tdm_tx_sample_rate_get,
  2693. tdm_tx_sample_rate_put),
  2694. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  2695. tdm_rx_format_get,
  2696. tdm_rx_format_put),
  2697. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  2698. tdm_tx_format_get,
  2699. tdm_tx_format_put),
  2700. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  2701. tdm_rx_ch_get,
  2702. tdm_rx_ch_put),
  2703. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  2704. tdm_tx_ch_get,
  2705. tdm_tx_ch_put),
  2706. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2707. tdm_rx_sample_rate_get,
  2708. tdm_rx_sample_rate_put),
  2709. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2710. tdm_tx_sample_rate_get,
  2711. tdm_tx_sample_rate_put),
  2712. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  2713. tdm_rx_format_get,
  2714. tdm_rx_format_put),
  2715. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  2716. tdm_tx_format_get,
  2717. tdm_tx_format_put),
  2718. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  2719. tdm_rx_ch_get,
  2720. tdm_rx_ch_put),
  2721. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  2722. tdm_tx_ch_get,
  2723. tdm_tx_ch_put),
  2724. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2725. tdm_rx_sample_rate_get,
  2726. tdm_rx_sample_rate_put),
  2727. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2728. tdm_tx_sample_rate_get,
  2729. tdm_tx_sample_rate_put),
  2730. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  2731. tdm_rx_format_get,
  2732. tdm_rx_format_put),
  2733. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  2734. tdm_tx_format_get,
  2735. tdm_tx_format_put),
  2736. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  2737. tdm_rx_ch_get,
  2738. tdm_rx_ch_put),
  2739. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  2740. tdm_tx_ch_get,
  2741. tdm_tx_ch_put),
  2742. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  2743. aux_pcm_rx_sample_rate_get,
  2744. aux_pcm_rx_sample_rate_put),
  2745. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  2746. aux_pcm_rx_sample_rate_get,
  2747. aux_pcm_rx_sample_rate_put),
  2748. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  2749. aux_pcm_rx_sample_rate_get,
  2750. aux_pcm_rx_sample_rate_put),
  2751. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  2752. aux_pcm_rx_sample_rate_get,
  2753. aux_pcm_rx_sample_rate_put),
  2754. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  2755. aux_pcm_rx_sample_rate_get,
  2756. aux_pcm_rx_sample_rate_put),
  2757. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  2758. aux_pcm_tx_sample_rate_get,
  2759. aux_pcm_tx_sample_rate_put),
  2760. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  2761. aux_pcm_tx_sample_rate_get,
  2762. aux_pcm_tx_sample_rate_put),
  2763. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  2764. aux_pcm_tx_sample_rate_get,
  2765. aux_pcm_tx_sample_rate_put),
  2766. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  2767. aux_pcm_tx_sample_rate_get,
  2768. aux_pcm_tx_sample_rate_put),
  2769. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  2770. aux_pcm_tx_sample_rate_get,
  2771. aux_pcm_tx_sample_rate_put),
  2772. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  2773. mi2s_rx_sample_rate_get,
  2774. mi2s_rx_sample_rate_put),
  2775. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  2776. mi2s_rx_sample_rate_get,
  2777. mi2s_rx_sample_rate_put),
  2778. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  2779. mi2s_rx_sample_rate_get,
  2780. mi2s_rx_sample_rate_put),
  2781. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  2782. mi2s_rx_sample_rate_get,
  2783. mi2s_rx_sample_rate_put),
  2784. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  2785. mi2s_rx_sample_rate_get,
  2786. mi2s_rx_sample_rate_put),
  2787. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  2788. mi2s_tx_sample_rate_get,
  2789. mi2s_tx_sample_rate_put),
  2790. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  2791. mi2s_tx_sample_rate_get,
  2792. mi2s_tx_sample_rate_put),
  2793. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  2794. mi2s_tx_sample_rate_get,
  2795. mi2s_tx_sample_rate_put),
  2796. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  2797. mi2s_tx_sample_rate_get,
  2798. mi2s_tx_sample_rate_put),
  2799. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  2800. mi2s_tx_sample_rate_get,
  2801. mi2s_tx_sample_rate_put),
  2802. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  2803. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2804. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  2805. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2806. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  2807. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2808. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  2809. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2810. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  2811. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2812. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  2813. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2814. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  2815. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2816. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  2817. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2818. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  2819. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2820. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  2821. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2822. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  2823. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2824. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  2825. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2826. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  2827. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2828. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  2829. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2830. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  2831. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2832. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  2833. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2834. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  2835. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2836. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  2837. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2838. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  2839. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2840. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  2841. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2842. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  2843. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2844. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  2845. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2846. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  2847. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2848. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  2849. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2850. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  2851. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2852. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  2853. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2854. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  2855. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2856. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  2857. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2858. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  2859. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2860. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  2861. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2862. SOC_SINGLE_MULTI_EXT("VAD CFG", SND_SOC_NOPM, 0, 1000, 0, 3, NULL,
  2863. msm_snd_vad_cfg_put),
  2864. };
  2865. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  2866. int enable, bool dapm)
  2867. {
  2868. int ret = 0;
  2869. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  2870. ret = tasha_cdc_mclk_enable(codec, enable, dapm);
  2871. } else {
  2872. dev_err(codec->dev, "%s: unknown codec to enable ext clk\n",
  2873. __func__);
  2874. ret = -EINVAL;
  2875. }
  2876. return ret;
  2877. }
  2878. static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_codec *codec,
  2879. int enable, bool dapm)
  2880. {
  2881. int ret = 0;
  2882. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  2883. ret = tasha_cdc_mclk_tx_enable(codec, enable, dapm);
  2884. } else {
  2885. dev_err(codec->dev, "%s: unknown codec to enable TX ext clk\n",
  2886. __func__);
  2887. ret = -EINVAL;
  2888. }
  2889. return ret;
  2890. }
  2891. static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
  2892. struct snd_kcontrol *kcontrol, int event)
  2893. {
  2894. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2895. pr_debug("%s: event = %d\n", __func__, event);
  2896. switch (event) {
  2897. case SND_SOC_DAPM_PRE_PMU:
  2898. return msm_snd_enable_codec_ext_tx_clk(codec, 1, true);
  2899. case SND_SOC_DAPM_POST_PMD:
  2900. return msm_snd_enable_codec_ext_tx_clk(codec, 0, true);
  2901. }
  2902. return 0;
  2903. }
  2904. static int msm_mclk_event(struct snd_soc_dapm_widget *w,
  2905. struct snd_kcontrol *kcontrol, int event)
  2906. {
  2907. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2908. pr_debug("%s: event = %d\n", __func__, event);
  2909. switch (event) {
  2910. case SND_SOC_DAPM_PRE_PMU:
  2911. return msm_snd_enable_codec_ext_clk(codec, 1, true);
  2912. case SND_SOC_DAPM_POST_PMD:
  2913. return msm_snd_enable_codec_ext_clk(codec, 0, true);
  2914. }
  2915. return 0;
  2916. }
  2917. static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
  2918. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  2919. msm_mclk_event,
  2920. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2921. SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
  2922. msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2923. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  2924. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  2925. };
  2926. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  2927. struct snd_kcontrol *kcontrol, int event)
  2928. {
  2929. struct msm_asoc_mach_data *pdata = NULL;
  2930. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2931. int ret = 0;
  2932. uint32_t dmic_idx;
  2933. int *dmic_gpio_cnt;
  2934. struct device_node *dmic_gpio;
  2935. char *wname;
  2936. wname = strpbrk(w->name, "01234567");
  2937. if (!wname) {
  2938. dev_err(codec->dev, "%s: widget not found\n", __func__);
  2939. return -EINVAL;
  2940. }
  2941. ret = kstrtouint(wname, 10, &dmic_idx);
  2942. if (ret < 0) {
  2943. dev_err(codec->dev, "%s: Invalid DMIC line on the codec\n",
  2944. __func__);
  2945. return -EINVAL;
  2946. }
  2947. pdata = snd_soc_card_get_drvdata(codec->component.card);
  2948. switch (dmic_idx) {
  2949. case 0:
  2950. case 1:
  2951. dmic_gpio_cnt = &pdata->dmic_01_gpio_cnt;
  2952. dmic_gpio = pdata->dmic_01_gpio_p;
  2953. break;
  2954. case 2:
  2955. case 3:
  2956. dmic_gpio_cnt = &pdata->dmic_23_gpio_cnt;
  2957. dmic_gpio = pdata->dmic_23_gpio_p;
  2958. break;
  2959. case 4:
  2960. case 5:
  2961. dmic_gpio_cnt = &pdata->dmic_45_gpio_cnt;
  2962. dmic_gpio = pdata->dmic_45_gpio_p;
  2963. break;
  2964. case 6:
  2965. case 7:
  2966. dmic_gpio_cnt = &pdata->dmic_67_gpio_cnt;
  2967. dmic_gpio = pdata->dmic_67_gpio_p;
  2968. break;
  2969. default:
  2970. dev_err(codec->dev, "%s: Invalid DMIC Selection\n",
  2971. __func__);
  2972. return -EINVAL;
  2973. }
  2974. dev_dbg(codec->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  2975. __func__, event, dmic_idx, *dmic_gpio_cnt);
  2976. switch (event) {
  2977. case SND_SOC_DAPM_PRE_PMU:
  2978. (*dmic_gpio_cnt)++;
  2979. if (*dmic_gpio_cnt == 1) {
  2980. ret = msm_cdc_pinctrl_select_active_state(
  2981. dmic_gpio);
  2982. if (ret < 0) {
  2983. dev_err(codec->dev, "%s: gpio set cannot be activated %sd\n",
  2984. __func__, "dmic_gpio");
  2985. return ret;
  2986. }
  2987. }
  2988. break;
  2989. case SND_SOC_DAPM_POST_PMD:
  2990. (*dmic_gpio_cnt)--;
  2991. if (*dmic_gpio_cnt == 0) {
  2992. ret = msm_cdc_pinctrl_select_sleep_state(
  2993. dmic_gpio);
  2994. if (ret < 0) {
  2995. dev_err(codec->dev, "%s: gpio set cannot be de-activated %sd\n",
  2996. __func__, "dmic_gpio");
  2997. return ret;
  2998. }
  2999. }
  3000. break;
  3001. default:
  3002. dev_err(codec->dev, "%s: invalid DAPM event %d\n",
  3003. __func__, event);
  3004. return -EINVAL;
  3005. }
  3006. return 0;
  3007. }
  3008. static const struct snd_soc_dapm_widget msm_va_dapm_widgets[] = {
  3009. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3010. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3011. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3012. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3013. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3014. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3015. SND_SOC_DAPM_MIC("Digital Mic6", msm_dmic_event),
  3016. SND_SOC_DAPM_MIC("Digital Mic7", msm_dmic_event),
  3017. };
  3018. static const struct snd_soc_dapm_widget msm_wsa_dapm_widgets[] = {
  3019. };
  3020. static inline int param_is_mask(int p)
  3021. {
  3022. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  3023. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  3024. }
  3025. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  3026. int n)
  3027. {
  3028. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  3029. }
  3030. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  3031. unsigned int bit)
  3032. {
  3033. if (bit >= SNDRV_MASK_MAX)
  3034. return;
  3035. if (param_is_mask(n)) {
  3036. struct snd_mask *m = param_to_mask(p, n);
  3037. m->bits[0] = 0;
  3038. m->bits[1] = 0;
  3039. m->bits[bit >> 5] |= (1 << (bit & 31));
  3040. }
  3041. }
  3042. static int msm_slim_get_ch_from_beid(int32_t be_id)
  3043. {
  3044. int ch_id = 0;
  3045. switch (be_id) {
  3046. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3047. ch_id = SLIM_RX_0;
  3048. break;
  3049. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3050. ch_id = SLIM_RX_1;
  3051. break;
  3052. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3053. ch_id = SLIM_RX_2;
  3054. break;
  3055. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3056. ch_id = SLIM_RX_3;
  3057. break;
  3058. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3059. ch_id = SLIM_RX_4;
  3060. break;
  3061. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3062. ch_id = SLIM_RX_6;
  3063. break;
  3064. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3065. ch_id = SLIM_TX_0;
  3066. break;
  3067. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3068. ch_id = SLIM_TX_3;
  3069. break;
  3070. default:
  3071. ch_id = SLIM_RX_0;
  3072. break;
  3073. }
  3074. return ch_id;
  3075. }
  3076. static int msm_vad_get_portid_from_beid(int32_t be_id, int *port_id)
  3077. {
  3078. *port_id = 0xFFFF;
  3079. switch (be_id) {
  3080. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3081. *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  3082. break;
  3083. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3084. *port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  3085. break;
  3086. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3087. *port_id = AFE_PORT_ID_QUINARY_TDM_TX;
  3088. break;
  3089. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3090. *port_id = AFE_PORT_ID_QUINARY_PCM_TX;
  3091. break;
  3092. default:
  3093. return -EINVAL;
  3094. }
  3095. return 0;
  3096. }
  3097. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  3098. {
  3099. int idx = 0;
  3100. switch (be_id) {
  3101. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3102. idx = WSA_CDC_DMA_RX_0;
  3103. break;
  3104. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3105. idx = WSA_CDC_DMA_TX_0;
  3106. break;
  3107. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3108. idx = WSA_CDC_DMA_RX_1;
  3109. break;
  3110. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3111. idx = WSA_CDC_DMA_TX_1;
  3112. break;
  3113. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3114. idx = WSA_CDC_DMA_TX_2;
  3115. break;
  3116. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3117. idx = VA_CDC_DMA_TX_0;
  3118. break;
  3119. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3120. idx = VA_CDC_DMA_TX_1;
  3121. break;
  3122. default:
  3123. idx = VA_CDC_DMA_TX_0;
  3124. break;
  3125. }
  3126. return idx;
  3127. }
  3128. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3129. struct snd_pcm_hw_params *params)
  3130. {
  3131. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3132. struct snd_interval *rate = hw_param_interval(params,
  3133. SNDRV_PCM_HW_PARAM_RATE);
  3134. struct snd_interval *channels = hw_param_interval(params,
  3135. SNDRV_PCM_HW_PARAM_CHANNELS);
  3136. int rc = 0;
  3137. int idx;
  3138. void *config = NULL;
  3139. struct snd_soc_codec *codec = NULL;
  3140. pr_debug("%s: format = %d, rate = %d\n",
  3141. __func__, params_format(params), params_rate(params));
  3142. switch (dai_link->id) {
  3143. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3144. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3145. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3146. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3147. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3148. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3149. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3150. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3151. slim_rx_cfg[idx].bit_format);
  3152. rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
  3153. channels->min = channels->max = slim_rx_cfg[idx].channels;
  3154. break;
  3155. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3156. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3157. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3158. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3159. slim_tx_cfg[idx].bit_format);
  3160. rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
  3161. channels->min = channels->max = slim_tx_cfg[idx].channels;
  3162. break;
  3163. case MSM_BACKEND_DAI_SLIMBUS_1_TX:
  3164. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3165. slim_tx_cfg[1].bit_format);
  3166. rate->min = rate->max = slim_tx_cfg[1].sample_rate;
  3167. channels->min = channels->max = slim_tx_cfg[1].channels;
  3168. break;
  3169. case MSM_BACKEND_DAI_SLIMBUS_4_TX:
  3170. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3171. SNDRV_PCM_FORMAT_S32_LE);
  3172. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3173. channels->min = channels->max = msm_vi_feed_tx_ch;
  3174. break;
  3175. case MSM_BACKEND_DAI_SLIMBUS_5_RX:
  3176. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3177. slim_rx_cfg[5].bit_format);
  3178. rate->min = rate->max = slim_rx_cfg[5].sample_rate;
  3179. channels->min = channels->max = slim_rx_cfg[5].channels;
  3180. break;
  3181. case MSM_BACKEND_DAI_SLIMBUS_5_TX:
  3182. codec = rtd->codec;
  3183. rate->min = rate->max = SAMPLING_RATE_16KHZ;
  3184. channels->min = channels->max = 1;
  3185. config = msm_codec_fn.get_afe_config_fn(codec,
  3186. AFE_SLIMBUS_SLAVE_PORT_CONFIG);
  3187. if (config) {
  3188. rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
  3189. config, SLIMBUS_5_TX);
  3190. if (rc)
  3191. pr_err("%s: Failed to set slimbus slave port config %d\n",
  3192. __func__, rc);
  3193. }
  3194. break;
  3195. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3196. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3197. slim_rx_cfg[SLIM_RX_7].bit_format);
  3198. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3199. channels->min = channels->max =
  3200. slim_rx_cfg[SLIM_RX_7].channels;
  3201. break;
  3202. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3203. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3204. channels->min = channels->max =
  3205. slim_tx_cfg[SLIM_TX_7].channels;
  3206. break;
  3207. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3208. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3209. channels->min = channels->max =
  3210. slim_tx_cfg[SLIM_TX_8].channels;
  3211. break;
  3212. case MSM_BACKEND_DAI_USB_RX:
  3213. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3214. usb_rx_cfg.bit_format);
  3215. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3216. channels->min = channels->max = usb_rx_cfg.channels;
  3217. break;
  3218. case MSM_BACKEND_DAI_USB_TX:
  3219. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3220. usb_tx_cfg.bit_format);
  3221. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3222. channels->min = channels->max = usb_tx_cfg.channels;
  3223. break;
  3224. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3225. channels->min = channels->max = proxy_rx_cfg.channels;
  3226. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3227. break;
  3228. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3229. channels->min = channels->max =
  3230. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3231. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3232. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3233. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3234. break;
  3235. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3236. channels->min = channels->max =
  3237. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3238. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3239. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3240. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3241. break;
  3242. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3243. channels->min = channels->max =
  3244. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3245. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3246. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3247. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3248. break;
  3249. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3250. channels->min = channels->max =
  3251. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3252. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3253. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3254. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3255. break;
  3256. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3257. channels->min = channels->max =
  3258. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3259. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3260. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3261. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3262. break;
  3263. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3264. channels->min = channels->max =
  3265. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3266. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3267. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3268. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3269. break;
  3270. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3271. channels->min = channels->max =
  3272. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3273. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3274. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3275. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3276. break;
  3277. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3278. channels->min = channels->max =
  3279. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3280. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3281. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3282. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3283. break;
  3284. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3285. channels->min = channels->max =
  3286. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3287. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3288. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3289. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3290. break;
  3291. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3292. channels->min = channels->max =
  3293. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3294. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3295. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3296. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3297. break;
  3298. case MSM_BACKEND_DAI_AUXPCM_RX:
  3299. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3300. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3301. rate->min = rate->max =
  3302. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3303. channels->min = channels->max =
  3304. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3305. break;
  3306. case MSM_BACKEND_DAI_AUXPCM_TX:
  3307. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3308. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3309. rate->min = rate->max =
  3310. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3311. channels->min = channels->max =
  3312. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3313. break;
  3314. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3315. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3316. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3317. rate->min = rate->max =
  3318. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3319. channels->min = channels->max =
  3320. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3321. break;
  3322. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3323. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3324. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3325. rate->min = rate->max =
  3326. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3327. channels->min = channels->max =
  3328. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3329. break;
  3330. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3331. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3332. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3333. rate->min = rate->max =
  3334. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3335. channels->min = channels->max =
  3336. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3337. break;
  3338. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3339. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3340. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3341. rate->min = rate->max =
  3342. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3343. channels->min = channels->max =
  3344. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3345. break;
  3346. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3347. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3348. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3349. rate->min = rate->max =
  3350. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3351. channels->min = channels->max =
  3352. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3353. break;
  3354. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3355. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3356. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3357. rate->min = rate->max =
  3358. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3359. channels->min = channels->max =
  3360. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3361. break;
  3362. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3363. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3364. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3365. rate->min = rate->max =
  3366. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3367. channels->min = channels->max =
  3368. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3369. break;
  3370. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3371. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3372. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3373. rate->min = rate->max =
  3374. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3375. channels->min = channels->max =
  3376. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3377. break;
  3378. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3379. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3380. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3381. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3382. channels->min = channels->max =
  3383. mi2s_rx_cfg[PRIM_MI2S].channels;
  3384. break;
  3385. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3386. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3387. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3388. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3389. channels->min = channels->max =
  3390. mi2s_tx_cfg[PRIM_MI2S].channels;
  3391. break;
  3392. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3393. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3394. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3395. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3396. channels->min = channels->max =
  3397. mi2s_rx_cfg[SEC_MI2S].channels;
  3398. break;
  3399. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3400. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3401. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3402. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3403. channels->min = channels->max =
  3404. mi2s_tx_cfg[SEC_MI2S].channels;
  3405. break;
  3406. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3407. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3408. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3409. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3410. channels->min = channels->max =
  3411. mi2s_rx_cfg[TERT_MI2S].channels;
  3412. break;
  3413. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3414. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3415. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3416. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3417. channels->min = channels->max =
  3418. mi2s_tx_cfg[TERT_MI2S].channels;
  3419. break;
  3420. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3421. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3422. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3423. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3424. channels->min = channels->max =
  3425. mi2s_rx_cfg[QUAT_MI2S].channels;
  3426. break;
  3427. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3428. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3429. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3430. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3431. channels->min = channels->max =
  3432. mi2s_tx_cfg[QUAT_MI2S].channels;
  3433. break;
  3434. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3435. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3436. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3437. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3438. channels->min = channels->max =
  3439. mi2s_rx_cfg[QUIN_MI2S].channels;
  3440. break;
  3441. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3442. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3443. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3444. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3445. channels->min = channels->max =
  3446. mi2s_tx_cfg[QUIN_MI2S].channels;
  3447. break;
  3448. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3449. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3450. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3451. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3452. cdc_dma_rx_cfg[idx].bit_format);
  3453. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3454. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3455. break;
  3456. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3457. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3458. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3459. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3460. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3461. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3462. cdc_dma_tx_cfg[idx].bit_format);
  3463. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3464. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3465. break;
  3466. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3467. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3468. SNDRV_PCM_FORMAT_S32_LE);
  3469. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3470. channels->min = channels->max = msm_vi_feed_tx_ch;
  3471. break;
  3472. default:
  3473. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3474. break;
  3475. }
  3476. return rc;
  3477. }
  3478. static int msm_afe_set_config(struct snd_soc_codec *codec)
  3479. {
  3480. int ret = 0;
  3481. void *config_data = NULL;
  3482. if (!msm_codec_fn.get_afe_config_fn) {
  3483. dev_err(codec->dev, "%s: codec get afe config not init'ed\n",
  3484. __func__);
  3485. return -EINVAL;
  3486. }
  3487. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3488. AFE_CDC_REGISTERS_CONFIG);
  3489. if (config_data) {
  3490. ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
  3491. if (ret) {
  3492. dev_err(codec->dev,
  3493. "%s: Failed to set codec registers config %d\n",
  3494. __func__, ret);
  3495. return ret;
  3496. }
  3497. }
  3498. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3499. AFE_CDC_REGISTER_PAGE_CONFIG);
  3500. if (config_data) {
  3501. ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
  3502. 0);
  3503. if (ret)
  3504. dev_err(codec->dev,
  3505. "%s: Failed to set cdc register page config\n",
  3506. __func__);
  3507. }
  3508. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3509. AFE_SLIMBUS_SLAVE_CONFIG);
  3510. if (config_data) {
  3511. ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
  3512. if (ret) {
  3513. dev_err(codec->dev,
  3514. "%s: Failed to set slimbus slave config %d\n",
  3515. __func__, ret);
  3516. return ret;
  3517. }
  3518. }
  3519. return 0;
  3520. }
  3521. static void msm_afe_clear_config(void)
  3522. {
  3523. afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
  3524. afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
  3525. }
  3526. static int msm_adsp_power_up_config(struct snd_soc_codec *codec,
  3527. struct snd_card *card)
  3528. {
  3529. int ret = 0;
  3530. unsigned long timeout;
  3531. int adsp_ready = 0;
  3532. bool snd_card_online = 0;
  3533. timeout = jiffies +
  3534. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  3535. do {
  3536. if (!snd_card_online) {
  3537. snd_card_online = snd_card_is_online_state(card);
  3538. pr_debug("%s: Sound card is %s\n", __func__,
  3539. snd_card_online ? "Online" : "Offline");
  3540. }
  3541. if (!adsp_ready) {
  3542. adsp_ready = q6core_is_adsp_ready();
  3543. pr_debug("%s: ADSP Audio is %s\n", __func__,
  3544. adsp_ready ? "ready" : "not ready");
  3545. }
  3546. if (snd_card_online && adsp_ready)
  3547. break;
  3548. /*
  3549. * Sound card/ADSP will be coming up after subsystem restart and
  3550. * it might not be fully up when the control reaches
  3551. * here. So, wait for 50msec before checking ADSP state
  3552. */
  3553. msleep(50);
  3554. } while (time_after(timeout, jiffies));
  3555. if (!snd_card_online || !adsp_ready) {
  3556. pr_err("%s: Timeout. Sound card is %s, ADSP Audio is %s\n",
  3557. __func__,
  3558. snd_card_online ? "Online" : "Offline",
  3559. adsp_ready ? "ready" : "not ready");
  3560. ret = -ETIMEDOUT;
  3561. goto err;
  3562. }
  3563. ret = msm_afe_set_config(codec);
  3564. if (ret)
  3565. pr_err("%s: Failed to set AFE config. err %d\n",
  3566. __func__, ret);
  3567. return 0;
  3568. err:
  3569. return ret;
  3570. }
  3571. static int qcs405_notifier_service_cb(struct notifier_block *this,
  3572. unsigned long opcode, void *ptr)
  3573. {
  3574. int ret;
  3575. struct snd_soc_card *card = NULL;
  3576. const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
  3577. struct snd_soc_pcm_runtime *rtd;
  3578. struct snd_soc_codec *codec;
  3579. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  3580. switch (opcode) {
  3581. case AUDIO_NOTIFIER_SERVICE_DOWN:
  3582. /*
  3583. * Use flag to ignore initial boot notifications
  3584. * On initial boot msm_adsp_power_up_config is
  3585. * called on init. There is no need to clear
  3586. * and set the config again on initial boot.
  3587. */
  3588. if (is_initial_boot)
  3589. break;
  3590. msm_afe_clear_config();
  3591. break;
  3592. case AUDIO_NOTIFIER_SERVICE_UP:
  3593. if (is_initial_boot) {
  3594. is_initial_boot = false;
  3595. break;
  3596. }
  3597. if (!spdev)
  3598. return -EINVAL;
  3599. card = platform_get_drvdata(spdev);
  3600. rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
  3601. if (!rtd) {
  3602. dev_err(card->dev,
  3603. "%s: snd_soc_get_pcm_runtime for %s failed!\n",
  3604. __func__, be_dl_name);
  3605. ret = -EINVAL;
  3606. goto err;
  3607. }
  3608. codec = rtd->codec;
  3609. ret = msm_adsp_power_up_config(codec, card->snd_card);
  3610. if (ret < 0) {
  3611. dev_err(card->dev,
  3612. "%s: msm_adsp_power_up_config failed ret = %d!\n",
  3613. __func__, ret);
  3614. goto err;
  3615. }
  3616. break;
  3617. default:
  3618. break;
  3619. }
  3620. err:
  3621. return NOTIFY_OK;
  3622. }
  3623. static struct notifier_block service_nb = {
  3624. .notifier_call = qcs405_notifier_service_cb,
  3625. .priority = -INT_MAX,
  3626. };
  3627. static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
  3628. {
  3629. int ret = 0;
  3630. void *config_data;
  3631. struct snd_soc_codec *codec = rtd->codec;
  3632. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3633. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3634. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3635. struct snd_card *card;
  3636. struct snd_info_entry *entry;
  3637. struct msm_asoc_mach_data *pdata =
  3638. snd_soc_card_get_drvdata(rtd->card);
  3639. /*
  3640. * Codec SLIMBUS configuration
  3641. * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
  3642. * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
  3643. * TX14, TX15, TX16
  3644. */
  3645. unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150,
  3646. 151, 152, 153, 154, 155, 156};
  3647. unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133,
  3648. 134, 135, 136, 137, 138, 139,
  3649. 140, 141, 142, 143};
  3650. pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
  3651. rtd->pmdown_time = 0;
  3652. ret = snd_soc_add_codec_controls(codec, msm_snd_sb_controls,
  3653. ARRAY_SIZE(msm_snd_sb_controls));
  3654. if (ret < 0) {
  3655. pr_err("%s: add_codec_controls failed, err %d\n",
  3656. __func__, ret);
  3657. return ret;
  3658. }
  3659. snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
  3660. ARRAY_SIZE(msm_dapm_widgets));
  3661. snd_soc_dapm_add_routes(dapm, wcd_audio_paths,
  3662. ARRAY_SIZE(wcd_audio_paths));
  3663. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
  3664. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
  3665. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  3666. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  3667. snd_soc_dapm_sync(dapm);
  3668. snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  3669. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  3670. msm_codec_fn.get_afe_config_fn = tasha_get_afe_config;
  3671. ret = msm_adsp_power_up_config(codec, rtd->card->snd_card);
  3672. if (ret) {
  3673. dev_err(codec->dev, "%s: Failed to set AFE config %d\n",
  3674. __func__, ret);
  3675. goto err;
  3676. }
  3677. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3678. AFE_AANC_VERSION);
  3679. if (config_data) {
  3680. ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
  3681. if (ret) {
  3682. dev_err(codec->dev, "%s: Failed to set aanc version %d\n",
  3683. __func__, ret);
  3684. goto err;
  3685. }
  3686. }
  3687. card = rtd->card->snd_card;
  3688. entry = snd_info_create_subdir(card->module, "codecs",
  3689. card->proc_root);
  3690. if (!entry) {
  3691. pr_debug("%s: Cannot create codecs module entry\n",
  3692. __func__);
  3693. ret = 0;
  3694. goto err;
  3695. }
  3696. pdata->codec_root = entry;
  3697. tasha_codec_info_create_codec_entry(pdata->codec_root, codec);
  3698. codec_reg_done = true;
  3699. return 0;
  3700. err:
  3701. return ret;
  3702. }
  3703. static int msm_va_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  3704. {
  3705. int ret = 0;
  3706. struct snd_soc_codec *codec = rtd->codec;
  3707. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3708. ret = snd_soc_add_codec_controls(codec, msm_snd_va_controls,
  3709. ARRAY_SIZE(msm_snd_va_controls));
  3710. if (ret < 0) {
  3711. dev_err(codec->dev, "%s: add_codec_controls for va failed, err %d\n",
  3712. __func__, ret);
  3713. return ret;
  3714. }
  3715. snd_soc_dapm_new_controls(dapm, msm_va_dapm_widgets,
  3716. ARRAY_SIZE(msm_va_dapm_widgets));
  3717. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  3718. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  3719. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  3720. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  3721. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  3722. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  3723. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  3724. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  3725. snd_soc_dapm_sync(dapm);
  3726. return ret;
  3727. }
  3728. static int msm_wsa_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  3729. {
  3730. int ret = 0;
  3731. struct snd_soc_codec *codec = rtd->codec;
  3732. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3733. ret = snd_soc_add_codec_controls(codec, msm_snd_wsa_controls,
  3734. ARRAY_SIZE(msm_snd_wsa_controls));
  3735. if (ret < 0) {
  3736. dev_err(codec->dev, "%s: add_codec_controls for va failed, err %d\n",
  3737. __func__, ret);
  3738. return ret;
  3739. }
  3740. snd_soc_dapm_new_controls(dapm, msm_wsa_dapm_widgets,
  3741. ARRAY_SIZE(msm_wsa_dapm_widgets));
  3742. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  3743. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  3744. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  3745. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  3746. snd_soc_dapm_sync(dapm);
  3747. return ret;
  3748. }
  3749. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  3750. {
  3751. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  3752. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161};
  3753. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3754. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  3755. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  3756. }
  3757. static int msm_snd_hw_params(struct snd_pcm_substream *substream,
  3758. struct snd_pcm_hw_params *params)
  3759. {
  3760. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3761. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3762. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3763. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3764. int ret = 0;
  3765. u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  3766. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3767. u32 user_set_tx_ch = 0;
  3768. u32 rx_ch_count;
  3769. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3770. ret = snd_soc_dai_get_channel_map(codec_dai,
  3771. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3772. if (ret < 0) {
  3773. pr_err("%s: failed to get codec chan map, err:%d\n",
  3774. __func__, ret);
  3775. goto err;
  3776. }
  3777. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
  3778. pr_debug("%s: rx_5_ch=%d\n", __func__,
  3779. slim_rx_cfg[5].channels);
  3780. rx_ch_count = slim_rx_cfg[5].channels;
  3781. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
  3782. pr_debug("%s: rx_2_ch=%d\n", __func__,
  3783. slim_rx_cfg[2].channels);
  3784. rx_ch_count = slim_rx_cfg[2].channels;
  3785. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
  3786. pr_debug("%s: rx_6_ch=%d\n", __func__,
  3787. slim_rx_cfg[6].channels);
  3788. rx_ch_count = slim_rx_cfg[6].channels;
  3789. } else {
  3790. pr_debug("%s: rx_0_ch=%d\n", __func__,
  3791. slim_rx_cfg[0].channels);
  3792. rx_ch_count = slim_rx_cfg[0].channels;
  3793. }
  3794. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3795. rx_ch_count, rx_ch);
  3796. if (ret < 0) {
  3797. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3798. __func__, ret);
  3799. goto err;
  3800. }
  3801. } else {
  3802. pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
  3803. codec_dai->name, codec_dai->id, user_set_tx_ch);
  3804. ret = snd_soc_dai_get_channel_map(codec_dai,
  3805. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3806. if (ret < 0) {
  3807. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  3808. __func__, ret);
  3809. goto err;
  3810. }
  3811. /* For <codec>_tx1 case */
  3812. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
  3813. user_set_tx_ch = slim_tx_cfg[0].channels;
  3814. /* For <codec>_tx3 case */
  3815. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
  3816. user_set_tx_ch = slim_tx_cfg[1].channels;
  3817. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
  3818. user_set_tx_ch = msm_vi_feed_tx_ch;
  3819. else
  3820. user_set_tx_ch = tx_ch_cnt;
  3821. pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
  3822. __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
  3823. tx_ch_cnt, dai_link->id);
  3824. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3825. user_set_tx_ch, tx_ch, 0, 0);
  3826. if (ret < 0)
  3827. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  3828. __func__, ret);
  3829. }
  3830. err:
  3831. return ret;
  3832. }
  3833. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  3834. struct snd_pcm_hw_params *params)
  3835. {
  3836. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3837. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3838. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3839. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3840. int ret = 0;
  3841. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  3842. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3843. u32 user_set_tx_ch = 0;
  3844. u32 user_set_rx_ch = 0;
  3845. u32 ch_id;
  3846. ret = snd_soc_dai_get_channel_map(codec_dai,
  3847. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  3848. &rx_ch_cdc_dma);
  3849. if (ret < 0) {
  3850. pr_err("%s: failed to get codec chan map, err:%d\n",
  3851. __func__, ret);
  3852. goto err;
  3853. }
  3854. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3855. switch (dai_link->id) {
  3856. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3857. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3858. {
  3859. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3860. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  3861. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  3862. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  3863. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3864. user_set_rx_ch, &rx_ch_cdc_dma);
  3865. if (ret < 0) {
  3866. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3867. __func__, ret);
  3868. goto err;
  3869. }
  3870. }
  3871. break;
  3872. }
  3873. } else {
  3874. switch (dai_link->id) {
  3875. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3876. {
  3877. user_set_tx_ch = msm_vi_feed_tx_ch;
  3878. }
  3879. break;
  3880. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3881. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3882. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3883. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3884. {
  3885. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3886. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  3887. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  3888. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  3889. }
  3890. break;
  3891. }
  3892. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  3893. &tx_ch_cdc_dma, 0, 0);
  3894. if (ret < 0) {
  3895. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3896. __func__, ret);
  3897. goto err;
  3898. }
  3899. }
  3900. err:
  3901. return ret;
  3902. }
  3903. static int msm_slimbus_2_hw_params(struct snd_pcm_substream *substream,
  3904. struct snd_pcm_hw_params *params)
  3905. {
  3906. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3907. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3908. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3909. unsigned int rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  3910. unsigned int rx_ch_cnt = 0, tx_ch_cnt = 0;
  3911. unsigned int num_tx_ch = 0;
  3912. unsigned int num_rx_ch = 0;
  3913. int ret = 0;
  3914. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3915. num_rx_ch = params_channels(params);
  3916. pr_debug("%s: %s rx_dai_id = %d num_ch = %d\n", __func__,
  3917. codec_dai->name, codec_dai->id, num_rx_ch);
  3918. ret = snd_soc_dai_get_channel_map(codec_dai,
  3919. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3920. if (ret < 0) {
  3921. pr_err("%s: failed to get codec chan map, err:%d\n",
  3922. __func__, ret);
  3923. goto err;
  3924. }
  3925. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3926. num_rx_ch, rx_ch);
  3927. if (ret < 0) {
  3928. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3929. __func__, ret);
  3930. goto err;
  3931. }
  3932. } else {
  3933. num_tx_ch = params_channels(params);
  3934. pr_debug("%s: %s tx_dai_id = %d num_ch = %d\n", __func__,
  3935. codec_dai->name, codec_dai->id, num_tx_ch);
  3936. ret = snd_soc_dai_get_channel_map(codec_dai,
  3937. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3938. if (ret < 0) {
  3939. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  3940. __func__, ret);
  3941. goto err;
  3942. }
  3943. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3944. num_tx_ch, tx_ch, 0, 0);
  3945. if (ret < 0) {
  3946. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  3947. __func__, ret);
  3948. goto err;
  3949. }
  3950. }
  3951. err:
  3952. return ret;
  3953. }
  3954. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  3955. struct snd_pcm_hw_params *params)
  3956. {
  3957. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3958. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3959. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3960. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3961. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  3962. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3963. int ret;
  3964. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  3965. codec_dai->name, codec_dai->id);
  3966. ret = snd_soc_dai_get_channel_map(codec_dai,
  3967. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3968. if (ret) {
  3969. dev_err(rtd->dev,
  3970. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  3971. __func__, ret);
  3972. goto err;
  3973. }
  3974. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  3975. __func__, tx_ch_cnt, dai_link->id);
  3976. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3977. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  3978. if (ret)
  3979. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  3980. __func__, ret);
  3981. err:
  3982. return ret;
  3983. }
  3984. static int msm_get_port_id(int be_id)
  3985. {
  3986. int afe_port_id;
  3987. switch (be_id) {
  3988. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3989. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  3990. break;
  3991. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3992. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  3993. break;
  3994. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3995. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  3996. break;
  3997. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3998. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  3999. break;
  4000. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  4001. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  4002. break;
  4003. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  4004. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  4005. break;
  4006. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  4007. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  4008. break;
  4009. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  4010. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  4011. break;
  4012. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  4013. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  4014. break;
  4015. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  4016. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  4017. break;
  4018. default:
  4019. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  4020. afe_port_id = -EINVAL;
  4021. }
  4022. return afe_port_id;
  4023. }
  4024. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  4025. {
  4026. u32 bit_per_sample;
  4027. switch (bit_format) {
  4028. case SNDRV_PCM_FORMAT_S32_LE:
  4029. case SNDRV_PCM_FORMAT_S24_3LE:
  4030. case SNDRV_PCM_FORMAT_S24_LE:
  4031. bit_per_sample = 32;
  4032. break;
  4033. case SNDRV_PCM_FORMAT_S16_LE:
  4034. default:
  4035. bit_per_sample = 16;
  4036. break;
  4037. }
  4038. return bit_per_sample;
  4039. }
  4040. static void update_mi2s_clk_val(int dai_id, int stream)
  4041. {
  4042. u32 bit_per_sample;
  4043. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4044. bit_per_sample =
  4045. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  4046. mi2s_clk[dai_id].clk_freq_in_hz =
  4047. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4048. } else {
  4049. bit_per_sample =
  4050. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  4051. mi2s_clk[dai_id].clk_freq_in_hz =
  4052. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4053. }
  4054. }
  4055. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  4056. {
  4057. int ret = 0;
  4058. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4059. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4060. int port_id = 0;
  4061. int index = cpu_dai->id;
  4062. port_id = msm_get_port_id(rtd->dai_link->id);
  4063. if (port_id < 0) {
  4064. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  4065. ret = port_id;
  4066. goto err;
  4067. }
  4068. if (enable) {
  4069. update_mi2s_clk_val(index, substream->stream);
  4070. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4071. mi2s_clk[index].clk_freq_in_hz);
  4072. }
  4073. mi2s_clk[index].enable = enable;
  4074. ret = afe_set_lpass_clock_v2(port_id,
  4075. &mi2s_clk[index]);
  4076. if (ret < 0) {
  4077. dev_err(rtd->card->dev,
  4078. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4079. __func__, port_id, ret);
  4080. goto err;
  4081. }
  4082. err:
  4083. return ret;
  4084. }
  4085. static int msm_set_pinctrl(struct msm_pinctrl_info *pinctrl_info,
  4086. enum pinctrl_pin_state new_state)
  4087. {
  4088. int ret = 0;
  4089. int curr_state = 0;
  4090. if (pinctrl_info == NULL) {
  4091. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4092. ret = -EINVAL;
  4093. goto err;
  4094. }
  4095. if (pinctrl_info->pinctrl == NULL) {
  4096. pr_err("%s: pinctrl_info->pinctrl is NULL\n", __func__);
  4097. ret = -EINVAL;
  4098. goto err;
  4099. }
  4100. curr_state = pinctrl_info->curr_state;
  4101. pinctrl_info->curr_state = new_state;
  4102. pr_debug("%s: curr_state = %s new_state = %s\n", __func__,
  4103. pin_states[curr_state], pin_states[pinctrl_info->curr_state]);
  4104. if (curr_state == pinctrl_info->curr_state) {
  4105. pr_debug("%s: Already in same state\n", __func__);
  4106. goto err;
  4107. }
  4108. if (curr_state != STATE_DISABLE &&
  4109. pinctrl_info->curr_state != STATE_DISABLE) {
  4110. pr_debug("%s: state already active cannot switch\n", __func__);
  4111. ret = -EIO;
  4112. goto err;
  4113. }
  4114. switch (pinctrl_info->curr_state) {
  4115. case STATE_MI2S_ACTIVE:
  4116. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4117. pinctrl_info->mi2s_active);
  4118. if (ret) {
  4119. pr_err("%s: MI2S state select failed with %d\n",
  4120. __func__, ret);
  4121. ret = -EIO;
  4122. goto err;
  4123. }
  4124. break;
  4125. case STATE_TDM_ACTIVE:
  4126. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4127. pinctrl_info->tdm_active);
  4128. if (ret) {
  4129. pr_err("%s: TDM state select failed with %d\n",
  4130. __func__, ret);
  4131. ret = -EIO;
  4132. goto err;
  4133. }
  4134. break;
  4135. case STATE_DISABLE:
  4136. if (curr_state == STATE_MI2S_ACTIVE) {
  4137. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4138. pinctrl_info->mi2s_disable);
  4139. } else {
  4140. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4141. pinctrl_info->tdm_disable);
  4142. }
  4143. if (ret) {
  4144. pr_err("%s: state disable failed with %d\n",
  4145. __func__, ret);
  4146. ret = -EIO;
  4147. goto err;
  4148. }
  4149. break;
  4150. default:
  4151. pr_err("%s: TLMM pin state is invalid\n", __func__);
  4152. return -EINVAL;
  4153. }
  4154. err:
  4155. return ret;
  4156. }
  4157. static void msm_release_pinctrl(struct platform_device *pdev)
  4158. {
  4159. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4160. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4161. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4162. if (pinctrl_info->pinctrl) {
  4163. devm_pinctrl_put(pinctrl_info->pinctrl);
  4164. pinctrl_info->pinctrl = NULL;
  4165. }
  4166. }
  4167. static int msm_get_pinctrl(struct platform_device *pdev)
  4168. {
  4169. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4170. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4171. struct msm_pinctrl_info *pinctrl_info = NULL;
  4172. struct pinctrl *pinctrl;
  4173. int ret;
  4174. pinctrl_info = &pdata->pinctrl_info;
  4175. if (pinctrl_info == NULL) {
  4176. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4177. return -EINVAL;
  4178. }
  4179. pinctrl = devm_pinctrl_get(&pdev->dev);
  4180. if (IS_ERR_OR_NULL(pinctrl)) {
  4181. pr_err("%s: Unable to get pinctrl handle\n", __func__);
  4182. return -EINVAL;
  4183. }
  4184. pinctrl_info->pinctrl = pinctrl;
  4185. /* get all the states handles from Device Tree */
  4186. pinctrl_info->mi2s_disable = pinctrl_lookup_state(pinctrl,
  4187. "quat-mi2s-sleep");
  4188. if (IS_ERR(pinctrl_info->mi2s_disable)) {
  4189. pr_err("%s: could not get mi2s_disable pinstate\n", __func__);
  4190. goto err;
  4191. }
  4192. pinctrl_info->mi2s_active = pinctrl_lookup_state(pinctrl,
  4193. "quat-mi2s-active");
  4194. if (IS_ERR(pinctrl_info->mi2s_active)) {
  4195. pr_err("%s: could not get mi2s_active pinstate\n", __func__);
  4196. goto err;
  4197. }
  4198. pinctrl_info->tdm_disable = pinctrl_lookup_state(pinctrl,
  4199. "quat-tdm-sleep");
  4200. if (IS_ERR(pinctrl_info->tdm_disable)) {
  4201. pr_err("%s: could not get tdm_disable pinstate\n", __func__);
  4202. goto err;
  4203. }
  4204. pinctrl_info->tdm_active = pinctrl_lookup_state(pinctrl,
  4205. "quat-tdm-active");
  4206. if (IS_ERR(pinctrl_info->tdm_active)) {
  4207. pr_err("%s: could not get tdm_active pinstate\n",
  4208. __func__);
  4209. goto err;
  4210. }
  4211. /* Reset the TLMM pins to a default state */
  4212. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4213. pinctrl_info->mi2s_disable);
  4214. if (ret != 0) {
  4215. pr_err("%s: Disable TLMM pins failed with %d\n",
  4216. __func__, ret);
  4217. ret = -EIO;
  4218. goto err;
  4219. }
  4220. pinctrl_info->curr_state = STATE_DISABLE;
  4221. return 0;
  4222. err:
  4223. devm_pinctrl_put(pinctrl);
  4224. pinctrl_info->pinctrl = NULL;
  4225. return -EINVAL;
  4226. }
  4227. static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  4228. struct snd_pcm_hw_params *params)
  4229. {
  4230. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4231. struct snd_interval *rate = hw_param_interval(params,
  4232. SNDRV_PCM_HW_PARAM_RATE);
  4233. struct snd_interval *channels = hw_param_interval(params,
  4234. SNDRV_PCM_HW_PARAM_CHANNELS);
  4235. if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
  4236. channels->min = channels->max =
  4237. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4238. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4239. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4240. rate->min = rate->max =
  4241. tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4242. } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
  4243. channels->min = channels->max =
  4244. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4245. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4246. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  4247. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  4248. } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
  4249. channels->min = channels->max =
  4250. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4251. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4252. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4253. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4254. } else {
  4255. pr_err("%s: dai id 0x%x not supported\n",
  4256. __func__, cpu_dai->id);
  4257. return -EINVAL;
  4258. }
  4259. pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
  4260. __func__, cpu_dai->id, channels->max, rate->max,
  4261. params_format(params));
  4262. return 0;
  4263. }
  4264. static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4265. struct snd_pcm_hw_params *params)
  4266. {
  4267. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4268. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4269. int ret = 0;
  4270. int slot_width = 32;
  4271. int channels, slots;
  4272. unsigned int slot_mask, rate, clk_freq;
  4273. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  4274. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4275. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4276. switch (cpu_dai->id) {
  4277. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4278. slots = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  4279. break;
  4280. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4281. slots = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4282. break;
  4283. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4284. slots = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  4285. break;
  4286. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4287. slots = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4288. break;
  4289. case AFE_PORT_ID_QUINARY_TDM_RX:
  4290. slots = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4291. break;
  4292. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4293. slots = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  4294. break;
  4295. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4296. slots = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  4297. break;
  4298. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4299. slots = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  4300. break;
  4301. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4302. slots = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  4303. break;
  4304. case AFE_PORT_ID_QUINARY_TDM_TX:
  4305. slots = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4306. break;
  4307. default:
  4308. pr_err("%s: dai id 0x%x not supported\n",
  4309. __func__, cpu_dai->id);
  4310. return -EINVAL;
  4311. }
  4312. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4313. /*2 slot config - bits 0 and 1 set for the first two slots */
  4314. slot_mask = 0x0000FFFF >> (16-slots);
  4315. channels = slots;
  4316. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  4317. __func__, slot_width, slots);
  4318. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  4319. slots, slot_width);
  4320. if (ret < 0) {
  4321. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  4322. __func__, ret);
  4323. goto end;
  4324. }
  4325. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4326. 0, NULL, channels, slot_offset);
  4327. if (ret < 0) {
  4328. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  4329. __func__, ret);
  4330. goto end;
  4331. }
  4332. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4333. /*2 slot config - bits 0 and 1 set for the first two slots */
  4334. slot_mask = 0x0000FFFF >> (16-slots);
  4335. channels = slots;
  4336. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  4337. __func__, slot_width, slots);
  4338. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  4339. slots, slot_width);
  4340. if (ret < 0) {
  4341. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  4342. __func__, ret);
  4343. goto end;
  4344. }
  4345. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4346. channels, slot_offset, 0, NULL);
  4347. if (ret < 0) {
  4348. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  4349. __func__, ret);
  4350. goto end;
  4351. }
  4352. } else {
  4353. ret = -EINVAL;
  4354. pr_err("%s: invalid use case, err:%d\n",
  4355. __func__, ret);
  4356. goto end;
  4357. }
  4358. rate = params_rate(params);
  4359. clk_freq = rate * slot_width * slots;
  4360. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  4361. if (ret < 0)
  4362. pr_err("%s: failed to set tdm clk, err:%d\n",
  4363. __func__, ret);
  4364. end:
  4365. return ret;
  4366. }
  4367. static int qcs405_tdm_snd_startup(struct snd_pcm_substream *substream)
  4368. {
  4369. int ret = 0;
  4370. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4371. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4372. struct snd_soc_card *card = rtd->card;
  4373. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4374. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4375. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4376. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4377. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4378. ret = msm_set_pinctrl(pinctrl_info, STATE_TDM_ACTIVE);
  4379. if (ret)
  4380. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4381. __func__, ret);
  4382. }
  4383. return ret;
  4384. }
  4385. static void qcs405_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  4386. {
  4387. int ret = 0;
  4388. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4389. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4390. struct snd_soc_card *card = rtd->card;
  4391. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4392. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4393. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4394. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4395. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4396. ret = msm_set_pinctrl(pinctrl_info, STATE_DISABLE);
  4397. if (ret)
  4398. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4399. __func__, ret);
  4400. }
  4401. }
  4402. static struct snd_soc_ops qcs405_tdm_be_ops = {
  4403. .hw_params = qcs405_tdm_snd_hw_params,
  4404. .startup = qcs405_tdm_snd_startup,
  4405. .shutdown = qcs405_tdm_snd_shutdown
  4406. };
  4407. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4408. {
  4409. cpumask_t mask;
  4410. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4411. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4412. cpumask_clear(&mask);
  4413. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4414. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4415. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4416. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4417. pm_qos_add_request(&substream->latency_pm_qos_req,
  4418. PM_QOS_CPU_DMA_LATENCY,
  4419. MSM_LL_QOS_VALUE);
  4420. return 0;
  4421. }
  4422. static struct snd_soc_ops msm_fe_qos_ops = {
  4423. .prepare = msm_fe_qos_prepare,
  4424. };
  4425. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4426. {
  4427. int ret = 0;
  4428. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4429. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4430. int index = cpu_dai->id;
  4431. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4432. struct snd_soc_card *card = rtd->card;
  4433. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4434. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4435. int ret_pinctrl = 0;
  4436. dev_dbg(rtd->card->dev,
  4437. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4438. __func__, substream->name, substream->stream,
  4439. cpu_dai->name, cpu_dai->id);
  4440. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4441. ret = -EINVAL;
  4442. dev_err(rtd->card->dev,
  4443. "%s: CPU DAI id (%d) out of range\n",
  4444. __func__, cpu_dai->id);
  4445. goto err;
  4446. }
  4447. /*
  4448. * Mutex protection in case the same MI2S
  4449. * interface using for both TX and RX so
  4450. * that the same clock won't be enable twice.
  4451. */
  4452. mutex_lock(&mi2s_intf_conf[index].lock);
  4453. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4454. /* Check if msm needs to provide the clock to the interface */
  4455. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4456. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4457. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4458. }
  4459. ret = msm_mi2s_set_sclk(substream, true);
  4460. if (ret < 0) {
  4461. dev_err(rtd->card->dev,
  4462. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4463. __func__, ret);
  4464. goto clean_up;
  4465. }
  4466. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4467. if (ret < 0) {
  4468. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4469. __func__, index, ret);
  4470. goto clk_off;
  4471. }
  4472. if (index == QUAT_MI2S) {
  4473. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4474. STATE_MI2S_ACTIVE);
  4475. if (ret_pinctrl)
  4476. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4477. __func__, ret_pinctrl);
  4478. }
  4479. }
  4480. clk_off:
  4481. if (ret < 0)
  4482. msm_mi2s_set_sclk(substream, false);
  4483. clean_up:
  4484. if (ret < 0)
  4485. mi2s_intf_conf[index].ref_cnt--;
  4486. mutex_unlock(&mi2s_intf_conf[index].lock);
  4487. err:
  4488. return ret;
  4489. }
  4490. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4491. {
  4492. int ret;
  4493. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4494. int index = rtd->cpu_dai->id;
  4495. struct snd_soc_card *card = rtd->card;
  4496. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4497. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4498. int ret_pinctrl = 0;
  4499. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4500. substream->name, substream->stream);
  4501. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4502. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4503. return;
  4504. }
  4505. mutex_lock(&mi2s_intf_conf[index].lock);
  4506. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4507. ret = msm_mi2s_set_sclk(substream, false);
  4508. if (ret < 0)
  4509. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4510. __func__, index, ret);
  4511. if (index == QUAT_MI2S) {
  4512. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4513. STATE_DISABLE);
  4514. if (ret_pinctrl)
  4515. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4516. __func__, ret_pinctrl);
  4517. }
  4518. }
  4519. mutex_unlock(&mi2s_intf_conf[index].lock);
  4520. }
  4521. static struct snd_soc_ops msm_mi2s_be_ops = {
  4522. .startup = msm_mi2s_snd_startup,
  4523. .shutdown = msm_mi2s_snd_shutdown,
  4524. };
  4525. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  4526. .hw_params = msm_snd_cdc_dma_hw_params,
  4527. };
  4528. static struct snd_soc_ops msm_be_ops = {
  4529. .hw_params = msm_snd_hw_params,
  4530. };
  4531. static struct snd_soc_ops msm_slimbus_2_be_ops = {
  4532. .hw_params = msm_slimbus_2_hw_params,
  4533. };
  4534. static struct snd_soc_ops msm_wcn_ops = {
  4535. .hw_params = msm_wcn_hw_params,
  4536. };
  4537. /* Digital audio interface glue - connects codec <---> CPU */
  4538. static struct snd_soc_dai_link msm_common_dai_links[] = {
  4539. /* FrontEnd DAI Links */
  4540. {
  4541. .name = MSM_DAILINK_NAME(Media1),
  4542. .stream_name = "MultiMedia1",
  4543. .cpu_dai_name = "MultiMedia1",
  4544. .platform_name = "msm-pcm-dsp.0",
  4545. .dynamic = 1,
  4546. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4547. .dpcm_playback = 1,
  4548. .dpcm_capture = 1,
  4549. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4550. SND_SOC_DPCM_TRIGGER_POST},
  4551. .codec_dai_name = "snd-soc-dummy-dai",
  4552. .codec_name = "snd-soc-dummy",
  4553. .ignore_suspend = 1,
  4554. /* this dainlink has playback support */
  4555. .ignore_pmdown_time = 1,
  4556. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  4557. },
  4558. {
  4559. .name = MSM_DAILINK_NAME(Media2),
  4560. .stream_name = "MultiMedia2",
  4561. .cpu_dai_name = "MultiMedia2",
  4562. .platform_name = "msm-pcm-dsp.0",
  4563. .dynamic = 1,
  4564. .dpcm_playback = 1,
  4565. .dpcm_capture = 1,
  4566. .codec_dai_name = "snd-soc-dummy-dai",
  4567. .codec_name = "snd-soc-dummy",
  4568. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4569. SND_SOC_DPCM_TRIGGER_POST},
  4570. .ignore_suspend = 1,
  4571. /* this dainlink has playback support */
  4572. .ignore_pmdown_time = 1,
  4573. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  4574. },
  4575. {
  4576. .name = "VoiceMMode1",
  4577. .stream_name = "VoiceMMode1",
  4578. .cpu_dai_name = "VoiceMMode1",
  4579. .platform_name = "msm-pcm-voice",
  4580. .dynamic = 1,
  4581. .dpcm_playback = 1,
  4582. .dpcm_capture = 1,
  4583. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4584. SND_SOC_DPCM_TRIGGER_POST},
  4585. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4586. .ignore_suspend = 1,
  4587. .ignore_pmdown_time = 1,
  4588. .codec_dai_name = "snd-soc-dummy-dai",
  4589. .codec_name = "snd-soc-dummy",
  4590. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  4591. },
  4592. {
  4593. .name = "MSM VoIP",
  4594. .stream_name = "VoIP",
  4595. .cpu_dai_name = "VoIP",
  4596. .platform_name = "msm-voip-dsp",
  4597. .dynamic = 1,
  4598. .dpcm_playback = 1,
  4599. .dpcm_capture = 1,
  4600. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4601. SND_SOC_DPCM_TRIGGER_POST},
  4602. .codec_dai_name = "snd-soc-dummy-dai",
  4603. .codec_name = "snd-soc-dummy",
  4604. .ignore_suspend = 1,
  4605. /* this dainlink has playback support */
  4606. .ignore_pmdown_time = 1,
  4607. .id = MSM_FRONTEND_DAI_VOIP,
  4608. },
  4609. {
  4610. .name = MSM_DAILINK_NAME(ULL),
  4611. .stream_name = "MultiMedia3",
  4612. .cpu_dai_name = "MultiMedia3",
  4613. .platform_name = "msm-pcm-dsp.2",
  4614. .dynamic = 1,
  4615. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4616. .dpcm_playback = 1,
  4617. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4618. SND_SOC_DPCM_TRIGGER_POST},
  4619. .codec_dai_name = "snd-soc-dummy-dai",
  4620. .codec_name = "snd-soc-dummy",
  4621. .ignore_suspend = 1,
  4622. /* this dainlink has playback support */
  4623. .ignore_pmdown_time = 1,
  4624. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  4625. },
  4626. /* Hostless PCM purpose */
  4627. {
  4628. .name = "SLIMBUS_0 Hostless",
  4629. .stream_name = "SLIMBUS_0 Hostless",
  4630. .cpu_dai_name = "SLIMBUS0_HOSTLESS",
  4631. .platform_name = "msm-pcm-hostless",
  4632. .dynamic = 1,
  4633. .dpcm_playback = 1,
  4634. .dpcm_capture = 1,
  4635. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4636. SND_SOC_DPCM_TRIGGER_POST},
  4637. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4638. .ignore_suspend = 1,
  4639. /* this dailink has playback support */
  4640. .ignore_pmdown_time = 1,
  4641. .codec_dai_name = "snd-soc-dummy-dai",
  4642. .codec_name = "snd-soc-dummy",
  4643. },
  4644. {
  4645. .name = "MSM AFE-PCM RX",
  4646. .stream_name = "AFE-PROXY RX",
  4647. .cpu_dai_name = "msm-dai-q6-dev.241",
  4648. .codec_name = "msm-stub-codec.1",
  4649. .codec_dai_name = "msm-stub-rx",
  4650. .platform_name = "msm-pcm-afe",
  4651. .dpcm_playback = 1,
  4652. .ignore_suspend = 1,
  4653. /* this dainlink has playback support */
  4654. .ignore_pmdown_time = 1,
  4655. },
  4656. {
  4657. .name = "MSM AFE-PCM TX",
  4658. .stream_name = "AFE-PROXY TX",
  4659. .cpu_dai_name = "msm-dai-q6-dev.240",
  4660. .codec_name = "msm-stub-codec.1",
  4661. .codec_dai_name = "msm-stub-tx",
  4662. .platform_name = "msm-pcm-afe",
  4663. .dpcm_capture = 1,
  4664. .ignore_suspend = 1,
  4665. },
  4666. {
  4667. .name = MSM_DAILINK_NAME(Compress1),
  4668. .stream_name = "Compress1",
  4669. .cpu_dai_name = "MultiMedia4",
  4670. .platform_name = "msm-compress-dsp",
  4671. .dynamic = 1,
  4672. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  4673. .dpcm_playback = 1,
  4674. .dpcm_capture = 1,
  4675. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4676. SND_SOC_DPCM_TRIGGER_POST},
  4677. .codec_dai_name = "snd-soc-dummy-dai",
  4678. .codec_name = "snd-soc-dummy",
  4679. .ignore_suspend = 1,
  4680. .ignore_pmdown_time = 1,
  4681. /* this dainlink has playback support */
  4682. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  4683. },
  4684. {
  4685. .name = "AUXPCM Hostless",
  4686. .stream_name = "AUXPCM Hostless",
  4687. .cpu_dai_name = "AUXPCM_HOSTLESS",
  4688. .platform_name = "msm-pcm-hostless",
  4689. .dynamic = 1,
  4690. .dpcm_playback = 1,
  4691. .dpcm_capture = 1,
  4692. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4693. SND_SOC_DPCM_TRIGGER_POST},
  4694. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4695. .ignore_suspend = 1,
  4696. /* this dainlink has playback support */
  4697. .ignore_pmdown_time = 1,
  4698. .codec_dai_name = "snd-soc-dummy-dai",
  4699. .codec_name = "snd-soc-dummy",
  4700. },
  4701. {
  4702. .name = "SLIMBUS_1 Hostless",
  4703. .stream_name = "SLIMBUS_1 Hostless",
  4704. .cpu_dai_name = "SLIMBUS1_HOSTLESS",
  4705. .platform_name = "msm-pcm-hostless",
  4706. .dynamic = 1,
  4707. .dpcm_playback = 1,
  4708. .dpcm_capture = 1,
  4709. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4710. SND_SOC_DPCM_TRIGGER_POST},
  4711. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4712. .ignore_suspend = 1,
  4713. /* this dailink has playback support */
  4714. .ignore_pmdown_time = 1,
  4715. .codec_dai_name = "snd-soc-dummy-dai",
  4716. .codec_name = "snd-soc-dummy",
  4717. },
  4718. {
  4719. .name = "SLIMBUS_3 Hostless",
  4720. .stream_name = "SLIMBUS_3 Hostless",
  4721. .cpu_dai_name = "SLIMBUS3_HOSTLESS",
  4722. .platform_name = "msm-pcm-hostless",
  4723. .dynamic = 1,
  4724. .dpcm_playback = 1,
  4725. .dpcm_capture = 1,
  4726. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4727. SND_SOC_DPCM_TRIGGER_POST},
  4728. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4729. .ignore_suspend = 1,
  4730. /* this dailink has playback support */
  4731. .ignore_pmdown_time = 1,
  4732. .codec_dai_name = "snd-soc-dummy-dai",
  4733. .codec_name = "snd-soc-dummy",
  4734. },
  4735. {
  4736. .name = "SLIMBUS_4 Hostless",
  4737. .stream_name = "SLIMBUS_4 Hostless",
  4738. .cpu_dai_name = "SLIMBUS4_HOSTLESS",
  4739. .platform_name = "msm-pcm-hostless",
  4740. .dynamic = 1,
  4741. .dpcm_playback = 1,
  4742. .dpcm_capture = 1,
  4743. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4744. SND_SOC_DPCM_TRIGGER_POST},
  4745. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4746. .ignore_suspend = 1,
  4747. /* this dailink has playback support */
  4748. .ignore_pmdown_time = 1,
  4749. .codec_dai_name = "snd-soc-dummy-dai",
  4750. .codec_name = "snd-soc-dummy",
  4751. },
  4752. {
  4753. .name = MSM_DAILINK_NAME(LowLatency),
  4754. .stream_name = "MultiMedia5",
  4755. .cpu_dai_name = "MultiMedia5",
  4756. .platform_name = "msm-pcm-dsp.1",
  4757. .dynamic = 1,
  4758. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4759. .dpcm_playback = 1,
  4760. .dpcm_capture = 1,
  4761. .codec_dai_name = "snd-soc-dummy-dai",
  4762. .codec_name = "snd-soc-dummy",
  4763. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4764. SND_SOC_DPCM_TRIGGER_POST},
  4765. .ignore_suspend = 1,
  4766. /* this dainlink has playback support */
  4767. .ignore_pmdown_time = 1,
  4768. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  4769. .ops = &msm_fe_qos_ops,
  4770. },
  4771. {
  4772. .name = "Listen 1 Audio Service",
  4773. .stream_name = "Listen 1 Audio Service",
  4774. .cpu_dai_name = "LSM1",
  4775. .platform_name = "msm-lsm-client",
  4776. .dynamic = 1,
  4777. .dpcm_capture = 1,
  4778. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4779. SND_SOC_DPCM_TRIGGER_POST },
  4780. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4781. .ignore_suspend = 1,
  4782. .codec_dai_name = "snd-soc-dummy-dai",
  4783. .codec_name = "snd-soc-dummy",
  4784. .id = MSM_FRONTEND_DAI_LSM1,
  4785. },
  4786. /* Multiple Tunnel instances */
  4787. {
  4788. .name = MSM_DAILINK_NAME(Compress2),
  4789. .stream_name = "Compress2",
  4790. .cpu_dai_name = "MultiMedia7",
  4791. .platform_name = "msm-compress-dsp",
  4792. .dynamic = 1,
  4793. .dpcm_playback = 1,
  4794. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4795. SND_SOC_DPCM_TRIGGER_POST},
  4796. .codec_dai_name = "snd-soc-dummy-dai",
  4797. .codec_name = "snd-soc-dummy",
  4798. .ignore_suspend = 1,
  4799. .ignore_pmdown_time = 1,
  4800. /* this dainlink has playback support */
  4801. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  4802. },
  4803. {
  4804. .name = MSM_DAILINK_NAME(MultiMedia10),
  4805. .stream_name = "MultiMedia10",
  4806. .cpu_dai_name = "MultiMedia10",
  4807. .platform_name = "msm-pcm-dsp.1",
  4808. .dynamic = 1,
  4809. .dpcm_playback = 1,
  4810. .dpcm_capture = 1,
  4811. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4812. SND_SOC_DPCM_TRIGGER_POST},
  4813. .codec_dai_name = "snd-soc-dummy-dai",
  4814. .codec_name = "snd-soc-dummy",
  4815. .ignore_suspend = 1,
  4816. .ignore_pmdown_time = 1,
  4817. /* this dainlink has playback support */
  4818. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  4819. },
  4820. {
  4821. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  4822. .stream_name = "MM_NOIRQ",
  4823. .cpu_dai_name = "MultiMedia8",
  4824. .platform_name = "msm-pcm-dsp-noirq",
  4825. .dynamic = 1,
  4826. .dpcm_playback = 1,
  4827. .dpcm_capture = 1,
  4828. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4829. SND_SOC_DPCM_TRIGGER_POST},
  4830. .codec_dai_name = "snd-soc-dummy-dai",
  4831. .codec_name = "snd-soc-dummy",
  4832. .ignore_suspend = 1,
  4833. .ignore_pmdown_time = 1,
  4834. /* this dainlink has playback support */
  4835. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  4836. .ops = &msm_fe_qos_ops,
  4837. },
  4838. /* HDMI Hostless */
  4839. {
  4840. .name = "HDMI_RX_HOSTLESS",
  4841. .stream_name = "HDMI_RX_HOSTLESS",
  4842. .cpu_dai_name = "HDMI_HOSTLESS",
  4843. .platform_name = "msm-pcm-hostless",
  4844. .dynamic = 1,
  4845. .dpcm_playback = 1,
  4846. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4847. SND_SOC_DPCM_TRIGGER_POST},
  4848. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4849. .ignore_suspend = 1,
  4850. .ignore_pmdown_time = 1,
  4851. .codec_dai_name = "snd-soc-dummy-dai",
  4852. .codec_name = "snd-soc-dummy",
  4853. },
  4854. {
  4855. .name = "VoiceMMode2",
  4856. .stream_name = "VoiceMMode2",
  4857. .cpu_dai_name = "VoiceMMode2",
  4858. .platform_name = "msm-pcm-voice",
  4859. .dynamic = 1,
  4860. .dpcm_playback = 1,
  4861. .dpcm_capture = 1,
  4862. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4863. SND_SOC_DPCM_TRIGGER_POST},
  4864. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4865. .ignore_suspend = 1,
  4866. .ignore_pmdown_time = 1,
  4867. .codec_dai_name = "snd-soc-dummy-dai",
  4868. .codec_name = "snd-soc-dummy",
  4869. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  4870. },
  4871. /* LSM FE */
  4872. {
  4873. .name = "Listen 2 Audio Service",
  4874. .stream_name = "Listen 2 Audio Service",
  4875. .cpu_dai_name = "LSM2",
  4876. .platform_name = "msm-lsm-client",
  4877. .dynamic = 1,
  4878. .dpcm_capture = 1,
  4879. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4880. SND_SOC_DPCM_TRIGGER_POST },
  4881. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4882. .ignore_suspend = 1,
  4883. .codec_dai_name = "snd-soc-dummy-dai",
  4884. .codec_name = "snd-soc-dummy",
  4885. .id = MSM_FRONTEND_DAI_LSM2,
  4886. },
  4887. {
  4888. .name = "Listen 3 Audio Service",
  4889. .stream_name = "Listen 3 Audio Service",
  4890. .cpu_dai_name = "LSM3",
  4891. .platform_name = "msm-lsm-client",
  4892. .dynamic = 1,
  4893. .dpcm_capture = 1,
  4894. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4895. SND_SOC_DPCM_TRIGGER_POST },
  4896. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4897. .ignore_suspend = 1,
  4898. .codec_dai_name = "snd-soc-dummy-dai",
  4899. .codec_name = "snd-soc-dummy",
  4900. .id = MSM_FRONTEND_DAI_LSM3,
  4901. },
  4902. {
  4903. .name = "Listen 4 Audio Service",
  4904. .stream_name = "Listen 4 Audio Service",
  4905. .cpu_dai_name = "LSM4",
  4906. .platform_name = "msm-lsm-client",
  4907. .dynamic = 1,
  4908. .dpcm_capture = 1,
  4909. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4910. SND_SOC_DPCM_TRIGGER_POST },
  4911. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4912. .ignore_suspend = 1,
  4913. .codec_dai_name = "snd-soc-dummy-dai",
  4914. .codec_name = "snd-soc-dummy",
  4915. .id = MSM_FRONTEND_DAI_LSM4,
  4916. },
  4917. {
  4918. .name = "Listen 5 Audio Service",
  4919. .stream_name = "Listen 5 Audio Service",
  4920. .cpu_dai_name = "LSM5",
  4921. .platform_name = "msm-lsm-client",
  4922. .dynamic = 1,
  4923. .dpcm_capture = 1,
  4924. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4925. SND_SOC_DPCM_TRIGGER_POST },
  4926. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4927. .ignore_suspend = 1,
  4928. .codec_dai_name = "snd-soc-dummy-dai",
  4929. .codec_name = "snd-soc-dummy",
  4930. .id = MSM_FRONTEND_DAI_LSM5,
  4931. },
  4932. {
  4933. .name = "Listen 6 Audio Service",
  4934. .stream_name = "Listen 6 Audio Service",
  4935. .cpu_dai_name = "LSM6",
  4936. .platform_name = "msm-lsm-client",
  4937. .dynamic = 1,
  4938. .dpcm_capture = 1,
  4939. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4940. SND_SOC_DPCM_TRIGGER_POST },
  4941. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4942. .ignore_suspend = 1,
  4943. .codec_dai_name = "snd-soc-dummy-dai",
  4944. .codec_name = "snd-soc-dummy",
  4945. .id = MSM_FRONTEND_DAI_LSM6,
  4946. },
  4947. {
  4948. .name = "Listen 7 Audio Service",
  4949. .stream_name = "Listen 7 Audio Service",
  4950. .cpu_dai_name = "LSM7",
  4951. .platform_name = "msm-lsm-client",
  4952. .dynamic = 1,
  4953. .dpcm_capture = 1,
  4954. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4955. SND_SOC_DPCM_TRIGGER_POST },
  4956. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4957. .ignore_suspend = 1,
  4958. .codec_dai_name = "snd-soc-dummy-dai",
  4959. .codec_name = "snd-soc-dummy",
  4960. .id = MSM_FRONTEND_DAI_LSM7,
  4961. },
  4962. {
  4963. .name = "Listen 8 Audio Service",
  4964. .stream_name = "Listen 8 Audio Service",
  4965. .cpu_dai_name = "LSM8",
  4966. .platform_name = "msm-lsm-client",
  4967. .dynamic = 1,
  4968. .dpcm_capture = 1,
  4969. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4970. SND_SOC_DPCM_TRIGGER_POST },
  4971. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4972. .ignore_suspend = 1,
  4973. .codec_dai_name = "snd-soc-dummy-dai",
  4974. .codec_name = "snd-soc-dummy",
  4975. .id = MSM_FRONTEND_DAI_LSM8,
  4976. },
  4977. {
  4978. .name = MSM_DAILINK_NAME(Media9),
  4979. .stream_name = "MultiMedia9",
  4980. .cpu_dai_name = "MultiMedia9",
  4981. .platform_name = "msm-pcm-dsp.0",
  4982. .dynamic = 1,
  4983. .dpcm_playback = 1,
  4984. .dpcm_capture = 1,
  4985. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4986. SND_SOC_DPCM_TRIGGER_POST},
  4987. .codec_dai_name = "snd-soc-dummy-dai",
  4988. .codec_name = "snd-soc-dummy",
  4989. .ignore_suspend = 1,
  4990. /* this dainlink has playback support */
  4991. .ignore_pmdown_time = 1,
  4992. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  4993. },
  4994. {
  4995. .name = MSM_DAILINK_NAME(Compress4),
  4996. .stream_name = "Compress4",
  4997. .cpu_dai_name = "MultiMedia11",
  4998. .platform_name = "msm-compress-dsp",
  4999. .dynamic = 1,
  5000. .dpcm_playback = 1,
  5001. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5002. SND_SOC_DPCM_TRIGGER_POST},
  5003. .codec_dai_name = "snd-soc-dummy-dai",
  5004. .codec_name = "snd-soc-dummy",
  5005. .ignore_suspend = 1,
  5006. .ignore_pmdown_time = 1,
  5007. /* this dainlink has playback support */
  5008. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  5009. },
  5010. {
  5011. .name = MSM_DAILINK_NAME(Compress5),
  5012. .stream_name = "Compress5",
  5013. .cpu_dai_name = "MultiMedia12",
  5014. .platform_name = "msm-compress-dsp",
  5015. .dynamic = 1,
  5016. .dpcm_playback = 1,
  5017. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5018. SND_SOC_DPCM_TRIGGER_POST},
  5019. .codec_dai_name = "snd-soc-dummy-dai",
  5020. .codec_name = "snd-soc-dummy",
  5021. .ignore_suspend = 1,
  5022. .ignore_pmdown_time = 1,
  5023. /* this dainlink has playback support */
  5024. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  5025. },
  5026. {
  5027. .name = MSM_DAILINK_NAME(Compress6),
  5028. .stream_name = "Compress6",
  5029. .cpu_dai_name = "MultiMedia13",
  5030. .platform_name = "msm-compress-dsp",
  5031. .dynamic = 1,
  5032. .dpcm_playback = 1,
  5033. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5034. SND_SOC_DPCM_TRIGGER_POST},
  5035. .codec_dai_name = "snd-soc-dummy-dai",
  5036. .codec_name = "snd-soc-dummy",
  5037. .ignore_suspend = 1,
  5038. .ignore_pmdown_time = 1,
  5039. /* this dainlink has playback support */
  5040. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5041. },
  5042. {
  5043. .name = MSM_DAILINK_NAME(Compress7),
  5044. .stream_name = "Compress7",
  5045. .cpu_dai_name = "MultiMedia14",
  5046. .platform_name = "msm-compress-dsp",
  5047. .dynamic = 1,
  5048. .dpcm_playback = 1,
  5049. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5050. SND_SOC_DPCM_TRIGGER_POST},
  5051. .codec_dai_name = "snd-soc-dummy-dai",
  5052. .codec_name = "snd-soc-dummy",
  5053. .ignore_suspend = 1,
  5054. .ignore_pmdown_time = 1,
  5055. /* this dainlink has playback support */
  5056. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5057. },
  5058. {
  5059. .name = MSM_DAILINK_NAME(Compress8),
  5060. .stream_name = "Compress8",
  5061. .cpu_dai_name = "MultiMedia15",
  5062. .platform_name = "msm-compress-dsp",
  5063. .dynamic = 1,
  5064. .dpcm_playback = 1,
  5065. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5066. SND_SOC_DPCM_TRIGGER_POST},
  5067. .codec_dai_name = "snd-soc-dummy-dai",
  5068. .codec_name = "snd-soc-dummy",
  5069. .ignore_suspend = 1,
  5070. .ignore_pmdown_time = 1,
  5071. /* this dainlink has playback support */
  5072. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5073. },
  5074. {
  5075. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5076. .stream_name = "MM_NOIRQ_2",
  5077. .cpu_dai_name = "MultiMedia16",
  5078. .platform_name = "msm-pcm-dsp-noirq",
  5079. .dynamic = 1,
  5080. .dpcm_playback = 1,
  5081. .dpcm_capture = 1,
  5082. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5083. SND_SOC_DPCM_TRIGGER_POST},
  5084. .codec_dai_name = "snd-soc-dummy-dai",
  5085. .codec_name = "snd-soc-dummy",
  5086. .ignore_suspend = 1,
  5087. .ignore_pmdown_time = 1,
  5088. /* this dainlink has playback support */
  5089. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5090. },
  5091. {
  5092. .name = "SLIMBUS_8 Hostless",
  5093. .stream_name = "SLIMBUS8_HOSTLESS Capture",
  5094. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5095. .platform_name = "msm-pcm-hostless",
  5096. .dynamic = 1,
  5097. .dpcm_capture = 1,
  5098. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5099. SND_SOC_DPCM_TRIGGER_POST},
  5100. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5101. .ignore_suspend = 1,
  5102. .codec_dai_name = "snd-soc-dummy-dai",
  5103. .codec_name = "snd-soc-dummy",
  5104. },
  5105. };
  5106. static struct snd_soc_dai_link msm_tasha_fe_dai_links[] = {
  5107. /* Ultrasound RX DAI Link */
  5108. {
  5109. .name = "SLIMBUS_2 Hostless Playback",
  5110. .stream_name = "SLIMBUS_2 Hostless Playback",
  5111. .cpu_dai_name = "msm-dai-q6-dev.16388",
  5112. .platform_name = "msm-pcm-hostless",
  5113. .codec_name = "tasha_codec",
  5114. .codec_dai_name = "tasha_rx2",
  5115. .ignore_suspend = 1,
  5116. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5117. .ops = &msm_slimbus_2_be_ops,
  5118. },
  5119. /* Ultrasound TX DAI Link */
  5120. {
  5121. .name = "SLIMBUS_2 Hostless Capture",
  5122. .stream_name = "SLIMBUS_2 Hostless Capture",
  5123. .cpu_dai_name = "msm-dai-q6-dev.16389",
  5124. .platform_name = "msm-pcm-hostless",
  5125. .codec_name = "tasha_codec",
  5126. .codec_dai_name = "tasha_tx2",
  5127. .ignore_suspend = 1,
  5128. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5129. .ops = &msm_slimbus_2_be_ops,
  5130. },
  5131. {
  5132. .name = "SLIMBUS_6 Hostless Playback",
  5133. .stream_name = "SLIMBUS_6 Hostless",
  5134. .cpu_dai_name = "SLIMBUS6_HOSTLESS",
  5135. .platform_name = "msm-pcm-hostless",
  5136. .dynamic = 1,
  5137. .dpcm_playback = 1,
  5138. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5139. SND_SOC_DPCM_TRIGGER_POST},
  5140. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5141. .ignore_suspend = 1,
  5142. /* this dailink has playback support */
  5143. .ignore_pmdown_time = 1,
  5144. .codec_dai_name = "snd-soc-dummy-dai",
  5145. .codec_name = "snd-soc-dummy",
  5146. },
  5147. };
  5148. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5149. {
  5150. .name = MSM_DAILINK_NAME(ASM Loopback),
  5151. .stream_name = "MultiMedia6",
  5152. .cpu_dai_name = "MultiMedia6",
  5153. .platform_name = "msm-pcm-loopback",
  5154. .dynamic = 1,
  5155. .dpcm_playback = 1,
  5156. .dpcm_capture = 1,
  5157. .codec_dai_name = "snd-soc-dummy-dai",
  5158. .codec_name = "snd-soc-dummy",
  5159. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5160. SND_SOC_DPCM_TRIGGER_POST},
  5161. .ignore_suspend = 1,
  5162. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5163. .ignore_pmdown_time = 1,
  5164. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5165. },
  5166. {
  5167. .name = "USB Audio Hostless",
  5168. .stream_name = "USB Audio Hostless",
  5169. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5170. .platform_name = "msm-pcm-hostless",
  5171. .dynamic = 1,
  5172. .dpcm_playback = 1,
  5173. .dpcm_capture = 1,
  5174. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5175. SND_SOC_DPCM_TRIGGER_POST},
  5176. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5177. .ignore_suspend = 1,
  5178. .ignore_pmdown_time = 1,
  5179. .codec_dai_name = "snd-soc-dummy-dai",
  5180. .codec_name = "snd-soc-dummy",
  5181. },
  5182. {
  5183. .name = "SLIMBUS_7 Hostless",
  5184. .stream_name = "SLIMBUS_7 Hostless",
  5185. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5186. .platform_name = "msm-pcm-hostless",
  5187. .dynamic = 1,
  5188. .dpcm_capture = 1,
  5189. .dpcm_playback = 1,
  5190. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5191. SND_SOC_DPCM_TRIGGER_POST},
  5192. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5193. .ignore_suspend = 1,
  5194. .ignore_pmdown_time = 1,
  5195. .codec_dai_name = "snd-soc-dummy-dai",
  5196. .codec_name = "snd-soc-dummy",
  5197. },
  5198. };
  5199. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5200. /* Backend AFE DAI Links */
  5201. {
  5202. .name = LPASS_BE_AFE_PCM_RX,
  5203. .stream_name = "AFE Playback",
  5204. .cpu_dai_name = "msm-dai-q6-dev.224",
  5205. .platform_name = "msm-pcm-routing",
  5206. .codec_name = "msm-stub-codec.1",
  5207. .codec_dai_name = "msm-stub-rx",
  5208. .no_pcm = 1,
  5209. .dpcm_playback = 1,
  5210. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5211. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5212. /* this dainlink has playback support */
  5213. .ignore_pmdown_time = 1,
  5214. .ignore_suspend = 1,
  5215. },
  5216. {
  5217. .name = LPASS_BE_AFE_PCM_TX,
  5218. .stream_name = "AFE Capture",
  5219. .cpu_dai_name = "msm-dai-q6-dev.225",
  5220. .platform_name = "msm-pcm-routing",
  5221. .codec_name = "msm-stub-codec.1",
  5222. .codec_dai_name = "msm-stub-tx",
  5223. .no_pcm = 1,
  5224. .dpcm_capture = 1,
  5225. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5226. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5227. .ignore_suspend = 1,
  5228. },
  5229. /* Incall Record Uplink BACK END DAI Link */
  5230. {
  5231. .name = LPASS_BE_INCALL_RECORD_TX,
  5232. .stream_name = "Voice Uplink Capture",
  5233. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5234. .platform_name = "msm-pcm-routing",
  5235. .codec_name = "msm-stub-codec.1",
  5236. .codec_dai_name = "msm-stub-tx",
  5237. .no_pcm = 1,
  5238. .dpcm_capture = 1,
  5239. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5240. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5241. .ignore_suspend = 1,
  5242. },
  5243. /* Incall Record Downlink BACK END DAI Link */
  5244. {
  5245. .name = LPASS_BE_INCALL_RECORD_RX,
  5246. .stream_name = "Voice Downlink Capture",
  5247. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5248. .platform_name = "msm-pcm-routing",
  5249. .codec_name = "msm-stub-codec.1",
  5250. .codec_dai_name = "msm-stub-tx",
  5251. .no_pcm = 1,
  5252. .dpcm_capture = 1,
  5253. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5254. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5255. .ignore_suspend = 1,
  5256. },
  5257. /* Incall Music BACK END DAI Link */
  5258. {
  5259. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5260. .stream_name = "Voice Farend Playback",
  5261. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5262. .platform_name = "msm-pcm-routing",
  5263. .codec_name = "msm-stub-codec.1",
  5264. .codec_dai_name = "msm-stub-rx",
  5265. .no_pcm = 1,
  5266. .dpcm_playback = 1,
  5267. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5268. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5269. .ignore_suspend = 1,
  5270. .ignore_pmdown_time = 1,
  5271. },
  5272. /* Incall Music 2 BACK END DAI Link */
  5273. {
  5274. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5275. .stream_name = "Voice2 Farend Playback",
  5276. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5277. .platform_name = "msm-pcm-routing",
  5278. .codec_name = "msm-stub-codec.1",
  5279. .codec_dai_name = "msm-stub-rx",
  5280. .no_pcm = 1,
  5281. .dpcm_playback = 1,
  5282. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5283. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5284. .ignore_suspend = 1,
  5285. .ignore_pmdown_time = 1,
  5286. },
  5287. {
  5288. .name = LPASS_BE_USB_AUDIO_RX,
  5289. .stream_name = "USB Audio Playback",
  5290. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5291. .platform_name = "msm-pcm-routing",
  5292. .codec_name = "msm-stub-codec.1",
  5293. .codec_dai_name = "msm-stub-rx",
  5294. .no_pcm = 1,
  5295. .dpcm_playback = 1,
  5296. .id = MSM_BACKEND_DAI_USB_RX,
  5297. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5298. .ignore_pmdown_time = 1,
  5299. .ignore_suspend = 1,
  5300. },
  5301. {
  5302. .name = LPASS_BE_USB_AUDIO_TX,
  5303. .stream_name = "USB Audio Capture",
  5304. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5305. .platform_name = "msm-pcm-routing",
  5306. .codec_name = "msm-stub-codec.1",
  5307. .codec_dai_name = "msm-stub-tx",
  5308. .no_pcm = 1,
  5309. .dpcm_capture = 1,
  5310. .id = MSM_BACKEND_DAI_USB_TX,
  5311. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5312. .ignore_suspend = 1,
  5313. },
  5314. {
  5315. .name = LPASS_BE_PRI_TDM_RX_0,
  5316. .stream_name = "Primary TDM0 Playback",
  5317. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5318. .platform_name = "msm-pcm-routing",
  5319. .codec_name = "msm-stub-codec.1",
  5320. .codec_dai_name = "msm-stub-rx",
  5321. .no_pcm = 1,
  5322. .dpcm_playback = 1,
  5323. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5324. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5325. .ops = &qcs405_tdm_be_ops,
  5326. .ignore_suspend = 1,
  5327. .ignore_pmdown_time = 1,
  5328. },
  5329. {
  5330. .name = LPASS_BE_PRI_TDM_TX_0,
  5331. .stream_name = "Primary TDM0 Capture",
  5332. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5333. .platform_name = "msm-pcm-routing",
  5334. .codec_name = "msm-stub-codec.1",
  5335. .codec_dai_name = "msm-stub-tx",
  5336. .no_pcm = 1,
  5337. .dpcm_capture = 1,
  5338. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5339. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5340. .ops = &qcs405_tdm_be_ops,
  5341. .ignore_suspend = 1,
  5342. },
  5343. {
  5344. .name = LPASS_BE_SEC_TDM_RX_0,
  5345. .stream_name = "Secondary TDM0 Playback",
  5346. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5347. .platform_name = "msm-pcm-routing",
  5348. .codec_name = "msm-stub-codec.1",
  5349. .codec_dai_name = "msm-stub-rx",
  5350. .no_pcm = 1,
  5351. .dpcm_playback = 1,
  5352. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5353. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5354. .ops = &qcs405_tdm_be_ops,
  5355. .ignore_suspend = 1,
  5356. .ignore_pmdown_time = 1,
  5357. },
  5358. {
  5359. .name = LPASS_BE_SEC_TDM_TX_0,
  5360. .stream_name = "Secondary TDM0 Capture",
  5361. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5362. .platform_name = "msm-pcm-routing",
  5363. .codec_name = "msm-stub-codec.1",
  5364. .codec_dai_name = "msm-stub-tx",
  5365. .no_pcm = 1,
  5366. .dpcm_capture = 1,
  5367. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  5368. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5369. .ops = &qcs405_tdm_be_ops,
  5370. .ignore_suspend = 1,
  5371. },
  5372. {
  5373. .name = LPASS_BE_TERT_TDM_RX_0,
  5374. .stream_name = "Tertiary TDM0 Playback",
  5375. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  5376. .platform_name = "msm-pcm-routing",
  5377. .codec_name = "msm-stub-codec.1",
  5378. .codec_dai_name = "msm-stub-rx",
  5379. .no_pcm = 1,
  5380. .dpcm_playback = 1,
  5381. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  5382. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5383. .ops = &qcs405_tdm_be_ops,
  5384. .ignore_suspend = 1,
  5385. .ignore_pmdown_time = 1,
  5386. },
  5387. {
  5388. .name = LPASS_BE_TERT_TDM_TX_0,
  5389. .stream_name = "Tertiary TDM0 Capture",
  5390. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  5391. .platform_name = "msm-pcm-routing",
  5392. .codec_name = "msm-stub-codec.1",
  5393. .codec_dai_name = "msm-stub-tx",
  5394. .no_pcm = 1,
  5395. .dpcm_capture = 1,
  5396. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  5397. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5398. .ops = &qcs405_tdm_be_ops,
  5399. .ignore_suspend = 1,
  5400. },
  5401. {
  5402. .name = LPASS_BE_QUAT_TDM_RX_0,
  5403. .stream_name = "Quaternary TDM0 Playback",
  5404. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  5405. .platform_name = "msm-pcm-routing",
  5406. .codec_name = "msm-stub-codec.1",
  5407. .codec_dai_name = "msm-stub-rx",
  5408. .no_pcm = 1,
  5409. .dpcm_playback = 1,
  5410. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  5411. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5412. .ops = &qcs405_tdm_be_ops,
  5413. .ignore_suspend = 1,
  5414. .ignore_pmdown_time = 1,
  5415. },
  5416. {
  5417. .name = LPASS_BE_QUAT_TDM_TX_0,
  5418. .stream_name = "Quaternary TDM0 Capture",
  5419. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  5420. .platform_name = "msm-pcm-routing",
  5421. .codec_name = "msm-stub-codec.1",
  5422. .codec_dai_name = "msm-stub-tx",
  5423. .no_pcm = 1,
  5424. .dpcm_capture = 1,
  5425. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  5426. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5427. .ops = &qcs405_tdm_be_ops,
  5428. .ignore_suspend = 1,
  5429. },
  5430. };
  5431. static struct snd_soc_dai_link msm_tasha_be_dai_links[] = {
  5432. {
  5433. .name = LPASS_BE_SLIMBUS_0_RX,
  5434. .stream_name = "Slimbus Playback",
  5435. .cpu_dai_name = "msm-dai-q6-dev.16384",
  5436. .platform_name = "msm-pcm-routing",
  5437. .codec_name = "tasha_codec",
  5438. .codec_dai_name = "tasha_rx1",
  5439. .no_pcm = 1,
  5440. .dpcm_playback = 1,
  5441. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  5442. .init = &msm_audrx_init,
  5443. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5444. /* this dainlink has playback support */
  5445. .ignore_pmdown_time = 1,
  5446. .ignore_suspend = 1,
  5447. .ops = &msm_be_ops,
  5448. },
  5449. {
  5450. .name = LPASS_BE_SLIMBUS_0_TX,
  5451. .stream_name = "Slimbus Capture",
  5452. .cpu_dai_name = "msm-dai-q6-dev.16385",
  5453. .platform_name = "msm-pcm-routing",
  5454. .codec_name = "tasha_codec",
  5455. .codec_dai_name = "tasha_tx1",
  5456. .no_pcm = 1,
  5457. .dpcm_capture = 1,
  5458. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  5459. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5460. .ignore_suspend = 1,
  5461. .ops = &msm_be_ops,
  5462. },
  5463. {
  5464. .name = LPASS_BE_SLIMBUS_1_RX,
  5465. .stream_name = "Slimbus1 Playback",
  5466. .cpu_dai_name = "msm-dai-q6-dev.16386",
  5467. .platform_name = "msm-pcm-routing",
  5468. .codec_name = "tasha_codec",
  5469. .codec_dai_name = "tasha_rx1",
  5470. .no_pcm = 1,
  5471. .dpcm_playback = 1,
  5472. .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
  5473. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5474. .ops = &msm_be_ops,
  5475. /* dai link has playback support */
  5476. .ignore_pmdown_time = 1,
  5477. .ignore_suspend = 1,
  5478. },
  5479. {
  5480. .name = LPASS_BE_SLIMBUS_1_TX,
  5481. .stream_name = "Slimbus1 Capture",
  5482. .cpu_dai_name = "msm-dai-q6-dev.16387",
  5483. .platform_name = "msm-pcm-routing",
  5484. .codec_name = "tasha_codec",
  5485. .codec_dai_name = "tasha_tx3",
  5486. .no_pcm = 1,
  5487. .dpcm_capture = 1,
  5488. .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
  5489. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5490. .ops = &msm_be_ops,
  5491. .ignore_suspend = 1,
  5492. },
  5493. {
  5494. .name = LPASS_BE_SLIMBUS_2_RX,
  5495. .stream_name = "Slimbus2 Playback",
  5496. .cpu_dai_name = "msm-dai-q6-dev.16388",
  5497. .platform_name = "msm-pcm-routing",
  5498. .codec_name = "tasha_codec",
  5499. .codec_dai_name = "tasha_rx2",
  5500. .no_pcm = 1,
  5501. .dpcm_playback = 1,
  5502. .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
  5503. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5504. .ops = &msm_be_ops,
  5505. .ignore_pmdown_time = 1,
  5506. .ignore_suspend = 1,
  5507. },
  5508. {
  5509. .name = LPASS_BE_SLIMBUS_3_RX,
  5510. .stream_name = "Slimbus3 Playback",
  5511. .cpu_dai_name = "msm-dai-q6-dev.16390",
  5512. .platform_name = "msm-pcm-routing",
  5513. .codec_name = "tasha_codec",
  5514. .codec_dai_name = "tasha_rx1",
  5515. .no_pcm = 1,
  5516. .dpcm_playback = 1,
  5517. .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
  5518. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5519. .ops = &msm_be_ops,
  5520. /* dai link has playback support */
  5521. .ignore_pmdown_time = 1,
  5522. .ignore_suspend = 1,
  5523. },
  5524. {
  5525. .name = LPASS_BE_SLIMBUS_3_TX,
  5526. .stream_name = "Slimbus3 Capture",
  5527. .cpu_dai_name = "msm-dai-q6-dev.16391",
  5528. .platform_name = "msm-pcm-routing",
  5529. .codec_name = "tasha_codec",
  5530. .codec_dai_name = "tasha_tx1",
  5531. .no_pcm = 1,
  5532. .dpcm_capture = 1,
  5533. .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
  5534. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5535. .ops = &msm_be_ops,
  5536. .ignore_suspend = 1,
  5537. },
  5538. {
  5539. .name = LPASS_BE_SLIMBUS_4_RX,
  5540. .stream_name = "Slimbus4 Playback",
  5541. .cpu_dai_name = "msm-dai-q6-dev.16392",
  5542. .platform_name = "msm-pcm-routing",
  5543. .codec_name = "tasha_codec",
  5544. .codec_dai_name = "tasha_rx1",
  5545. .no_pcm = 1,
  5546. .dpcm_playback = 1,
  5547. .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
  5548. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5549. .ops = &msm_be_ops,
  5550. /* dai link has playback support */
  5551. .ignore_pmdown_time = 1,
  5552. .ignore_suspend = 1,
  5553. },
  5554. {
  5555. .name = LPASS_BE_SLIMBUS_5_RX,
  5556. .stream_name = "Slimbus5 Playback",
  5557. .cpu_dai_name = "msm-dai-q6-dev.16394",
  5558. .platform_name = "msm-pcm-routing",
  5559. .codec_name = "tasha_codec",
  5560. .codec_dai_name = "tasha_rx3",
  5561. .no_pcm = 1,
  5562. .dpcm_playback = 1,
  5563. .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
  5564. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5565. .ops = &msm_be_ops,
  5566. /* dai link has playback support */
  5567. .ignore_pmdown_time = 1,
  5568. .ignore_suspend = 1,
  5569. },
  5570. {
  5571. .name = LPASS_BE_SLIMBUS_6_RX,
  5572. .stream_name = "Slimbus6 Playback",
  5573. .cpu_dai_name = "msm-dai-q6-dev.16396",
  5574. .platform_name = "msm-pcm-routing",
  5575. .codec_name = "tasha_codec",
  5576. .codec_dai_name = "tasha_rx4",
  5577. .no_pcm = 1,
  5578. .dpcm_playback = 1,
  5579. .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
  5580. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5581. .ops = &msm_be_ops,
  5582. /* dai link has playback support */
  5583. .ignore_pmdown_time = 1,
  5584. .ignore_suspend = 1,
  5585. },
  5586. /* Slimbus VI Recording */
  5587. {
  5588. .name = LPASS_BE_SLIMBUS_TX_VI,
  5589. .stream_name = "Slimbus4 Capture",
  5590. .cpu_dai_name = "msm-dai-q6-dev.16393",
  5591. .platform_name = "msm-pcm-routing",
  5592. .codec_name = "tasha_codec",
  5593. .codec_dai_name = "tasha_vifeedback",
  5594. .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
  5595. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5596. .ops = &msm_be_ops,
  5597. .ignore_suspend = 1,
  5598. .no_pcm = 1,
  5599. .dpcm_capture = 1,
  5600. .ignore_pmdown_time = 1,
  5601. },
  5602. };
  5603. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  5604. {
  5605. .name = LPASS_BE_SLIMBUS_7_RX,
  5606. .stream_name = "Slimbus7 Playback",
  5607. .cpu_dai_name = "msm-dai-q6-dev.16398",
  5608. .platform_name = "msm-pcm-routing",
  5609. .codec_name = "btfmslim_slave",
  5610. /* BT codec driver determines capabilities based on
  5611. * dai name, bt codecdai name should always contains
  5612. * supported usecase information
  5613. */
  5614. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  5615. .no_pcm = 1,
  5616. .dpcm_playback = 1,
  5617. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5618. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5619. .ops = &msm_wcn_ops,
  5620. /* dai link has playback support */
  5621. .ignore_pmdown_time = 1,
  5622. .ignore_suspend = 1,
  5623. },
  5624. {
  5625. .name = LPASS_BE_SLIMBUS_7_TX,
  5626. .stream_name = "Slimbus7 Capture",
  5627. .cpu_dai_name = "msm-dai-q6-dev.16399",
  5628. .platform_name = "msm-pcm-routing",
  5629. .codec_name = "btfmslim_slave",
  5630. .codec_dai_name = "btfm_bt_sco_slim_tx",
  5631. .no_pcm = 1,
  5632. .dpcm_capture = 1,
  5633. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5634. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5635. .ops = &msm_wcn_ops,
  5636. .ignore_suspend = 1,
  5637. },
  5638. {
  5639. .name = LPASS_BE_SLIMBUS_8_TX,
  5640. .stream_name = "Slimbus8 Capture",
  5641. .cpu_dai_name = "msm-dai-q6-dev.16401",
  5642. .platform_name = "msm-pcm-routing",
  5643. .codec_name = "btfmslim_slave",
  5644. .codec_dai_name = "btfm_fm_slim_tx",
  5645. .no_pcm = 1,
  5646. .dpcm_capture = 1,
  5647. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  5648. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5649. .init = &msm_wcn_init,
  5650. .ops = &msm_wcn_ops,
  5651. .ignore_suspend = 1,
  5652. },
  5653. };
  5654. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  5655. {
  5656. .name = LPASS_BE_PRI_MI2S_RX,
  5657. .stream_name = "Primary MI2S Playback",
  5658. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5659. .platform_name = "msm-pcm-routing",
  5660. .codec_name = "msm-stub-codec.1",
  5661. .codec_dai_name = "msm-stub-rx",
  5662. .no_pcm = 1,
  5663. .dpcm_playback = 1,
  5664. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  5665. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5666. .ops = &msm_mi2s_be_ops,
  5667. .ignore_suspend = 1,
  5668. .ignore_pmdown_time = 1,
  5669. },
  5670. {
  5671. .name = LPASS_BE_PRI_MI2S_TX,
  5672. .stream_name = "Primary MI2S Capture",
  5673. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5674. .platform_name = "msm-pcm-routing",
  5675. .codec_name = "msm-stub-codec.1",
  5676. .codec_dai_name = "msm-stub-tx",
  5677. .no_pcm = 1,
  5678. .dpcm_capture = 1,
  5679. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  5680. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5681. .ops = &msm_mi2s_be_ops,
  5682. .ignore_suspend = 1,
  5683. },
  5684. {
  5685. .name = LPASS_BE_SEC_MI2S_RX,
  5686. .stream_name = "Secondary MI2S Playback",
  5687. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5688. .platform_name = "msm-pcm-routing",
  5689. .codec_name = "msm-stub-codec.1",
  5690. .codec_dai_name = "msm-stub-rx",
  5691. .no_pcm = 1,
  5692. .dpcm_playback = 1,
  5693. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  5694. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5695. .ops = &msm_mi2s_be_ops,
  5696. .ignore_suspend = 1,
  5697. .ignore_pmdown_time = 1,
  5698. },
  5699. {
  5700. .name = LPASS_BE_SEC_MI2S_TX,
  5701. .stream_name = "Secondary MI2S Capture",
  5702. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5703. .platform_name = "msm-pcm-routing",
  5704. .codec_name = "msm-stub-codec.1",
  5705. .codec_dai_name = "msm-stub-tx",
  5706. .no_pcm = 1,
  5707. .dpcm_capture = 1,
  5708. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  5709. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5710. .ops = &msm_mi2s_be_ops,
  5711. .ignore_suspend = 1,
  5712. },
  5713. {
  5714. .name = LPASS_BE_TERT_MI2S_RX,
  5715. .stream_name = "Tertiary MI2S Playback",
  5716. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5717. .platform_name = "msm-pcm-routing",
  5718. .codec_name = "msm-stub-codec.1",
  5719. .codec_dai_name = "msm-stub-rx",
  5720. .no_pcm = 1,
  5721. .dpcm_playback = 1,
  5722. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  5723. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5724. .ops = &msm_mi2s_be_ops,
  5725. .ignore_suspend = 1,
  5726. .ignore_pmdown_time = 1,
  5727. },
  5728. {
  5729. .name = LPASS_BE_TERT_MI2S_TX,
  5730. .stream_name = "Tertiary MI2S Capture",
  5731. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5732. .platform_name = "msm-pcm-routing",
  5733. .codec_name = "msm-stub-codec.1",
  5734. .codec_dai_name = "msm-stub-tx",
  5735. .no_pcm = 1,
  5736. .dpcm_capture = 1,
  5737. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  5738. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5739. .ops = &msm_mi2s_be_ops,
  5740. .ignore_suspend = 1,
  5741. },
  5742. {
  5743. .name = LPASS_BE_QUAT_MI2S_RX,
  5744. .stream_name = "Quaternary MI2S Playback",
  5745. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5746. .platform_name = "msm-pcm-routing",
  5747. .codec_name = "msm-stub-codec.1",
  5748. .codec_dai_name = "msm-stub-rx",
  5749. .no_pcm = 1,
  5750. .dpcm_playback = 1,
  5751. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  5752. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5753. .ops = &msm_mi2s_be_ops,
  5754. .ignore_suspend = 1,
  5755. .ignore_pmdown_time = 1,
  5756. },
  5757. {
  5758. .name = LPASS_BE_QUAT_MI2S_TX,
  5759. .stream_name = "Quaternary MI2S Capture",
  5760. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5761. .platform_name = "msm-pcm-routing",
  5762. .codec_name = "msm-stub-codec.1",
  5763. .codec_dai_name = "msm-stub-tx",
  5764. .no_pcm = 1,
  5765. .dpcm_capture = 1,
  5766. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  5767. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5768. .ops = &msm_mi2s_be_ops,
  5769. .ignore_suspend = 1,
  5770. },
  5771. {
  5772. .name = LPASS_BE_QUIN_MI2S_RX,
  5773. .stream_name = "Quinary MI2S Playback",
  5774. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5775. .platform_name = "msm-pcm-routing",
  5776. .codec_name = "msm-stub-codec.1",
  5777. .codec_dai_name = "msm-stub-rx",
  5778. .no_pcm = 1,
  5779. .dpcm_playback = 1,
  5780. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  5781. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5782. .ops = &msm_mi2s_be_ops,
  5783. .ignore_suspend = 1,
  5784. .ignore_pmdown_time = 1,
  5785. },
  5786. {
  5787. .name = LPASS_BE_QUIN_MI2S_TX,
  5788. .stream_name = "Quinary MI2S Capture",
  5789. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5790. .platform_name = "msm-pcm-routing",
  5791. .codec_name = "msm-stub-codec.1",
  5792. .codec_dai_name = "msm-stub-tx",
  5793. .no_pcm = 1,
  5794. .dpcm_capture = 1,
  5795. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  5796. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5797. .ops = &msm_mi2s_be_ops,
  5798. .ignore_suspend = 1,
  5799. },
  5800. };
  5801. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  5802. /* Primary AUX PCM Backend DAI Links */
  5803. {
  5804. .name = LPASS_BE_AUXPCM_RX,
  5805. .stream_name = "AUX PCM Playback",
  5806. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5807. .platform_name = "msm-pcm-routing",
  5808. .codec_name = "msm-stub-codec.1",
  5809. .codec_dai_name = "msm-stub-rx",
  5810. .no_pcm = 1,
  5811. .dpcm_playback = 1,
  5812. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  5813. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5814. .ignore_pmdown_time = 1,
  5815. .ignore_suspend = 1,
  5816. },
  5817. {
  5818. .name = LPASS_BE_AUXPCM_TX,
  5819. .stream_name = "AUX PCM Capture",
  5820. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5821. .platform_name = "msm-pcm-routing",
  5822. .codec_name = "msm-stub-codec.1",
  5823. .codec_dai_name = "msm-stub-tx",
  5824. .no_pcm = 1,
  5825. .dpcm_capture = 1,
  5826. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  5827. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5828. .ignore_suspend = 1,
  5829. },
  5830. /* Secondary AUX PCM Backend DAI Links */
  5831. {
  5832. .name = LPASS_BE_SEC_AUXPCM_RX,
  5833. .stream_name = "Sec AUX PCM Playback",
  5834. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5835. .platform_name = "msm-pcm-routing",
  5836. .codec_name = "msm-stub-codec.1",
  5837. .codec_dai_name = "msm-stub-rx",
  5838. .no_pcm = 1,
  5839. .dpcm_playback = 1,
  5840. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  5841. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5842. .ignore_pmdown_time = 1,
  5843. .ignore_suspend = 1,
  5844. },
  5845. {
  5846. .name = LPASS_BE_SEC_AUXPCM_TX,
  5847. .stream_name = "Sec AUX PCM Capture",
  5848. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5849. .platform_name = "msm-pcm-routing",
  5850. .codec_name = "msm-stub-codec.1",
  5851. .codec_dai_name = "msm-stub-tx",
  5852. .no_pcm = 1,
  5853. .dpcm_capture = 1,
  5854. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  5855. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5856. .ignore_suspend = 1,
  5857. },
  5858. /* Tertiary AUX PCM Backend DAI Links */
  5859. {
  5860. .name = LPASS_BE_TERT_AUXPCM_RX,
  5861. .stream_name = "Tert AUX PCM Playback",
  5862. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5863. .platform_name = "msm-pcm-routing",
  5864. .codec_name = "msm-stub-codec.1",
  5865. .codec_dai_name = "msm-stub-rx",
  5866. .no_pcm = 1,
  5867. .dpcm_playback = 1,
  5868. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  5869. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5870. .ignore_suspend = 1,
  5871. },
  5872. {
  5873. .name = LPASS_BE_TERT_AUXPCM_TX,
  5874. .stream_name = "Tert AUX PCM Capture",
  5875. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5876. .platform_name = "msm-pcm-routing",
  5877. .codec_name = "msm-stub-codec.1",
  5878. .codec_dai_name = "msm-stub-tx",
  5879. .no_pcm = 1,
  5880. .dpcm_capture = 1,
  5881. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  5882. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5883. .ignore_suspend = 1,
  5884. },
  5885. /* Quaternary AUX PCM Backend DAI Links */
  5886. {
  5887. .name = LPASS_BE_QUAT_AUXPCM_RX,
  5888. .stream_name = "Quat AUX PCM Playback",
  5889. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5890. .platform_name = "msm-pcm-routing",
  5891. .codec_name = "msm-stub-codec.1",
  5892. .codec_dai_name = "msm-stub-rx",
  5893. .no_pcm = 1,
  5894. .dpcm_playback = 1,
  5895. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  5896. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5897. .ignore_pmdown_time = 1,
  5898. .ignore_suspend = 1,
  5899. },
  5900. {
  5901. .name = LPASS_BE_QUAT_AUXPCM_TX,
  5902. .stream_name = "Quat AUX PCM Capture",
  5903. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5904. .platform_name = "msm-pcm-routing",
  5905. .codec_name = "msm-stub-codec.1",
  5906. .codec_dai_name = "msm-stub-tx",
  5907. .no_pcm = 1,
  5908. .dpcm_capture = 1,
  5909. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  5910. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5911. .ignore_suspend = 1,
  5912. },
  5913. /* Quinary AUX PCM Backend DAI Links */
  5914. {
  5915. .name = LPASS_BE_QUIN_AUXPCM_RX,
  5916. .stream_name = "Quin AUX PCM Playback",
  5917. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5918. .platform_name = "msm-pcm-routing",
  5919. .codec_name = "msm-stub-codec.1",
  5920. .codec_dai_name = "msm-stub-rx",
  5921. .no_pcm = 1,
  5922. .dpcm_playback = 1,
  5923. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  5924. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5925. .ignore_pmdown_time = 1,
  5926. .ignore_suspend = 1,
  5927. },
  5928. {
  5929. .name = LPASS_BE_QUIN_AUXPCM_TX,
  5930. .stream_name = "Quin AUX PCM Capture",
  5931. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5932. .platform_name = "msm-pcm-routing",
  5933. .codec_name = "msm-stub-codec.1",
  5934. .codec_dai_name = "msm-stub-tx",
  5935. .no_pcm = 1,
  5936. .dpcm_capture = 1,
  5937. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  5938. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5939. .ignore_suspend = 1,
  5940. },
  5941. };
  5942. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  5943. /* WSA CDC DMA Backend DAI Links */
  5944. {
  5945. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  5946. .stream_name = "WSA CDC DMA0 Playback",
  5947. .cpu_dai_name = "msm-dai-cdc-dma.45056",
  5948. .platform_name = "msm-pcm-routing",
  5949. .codec_name = "bolero_codec",
  5950. .codec_dai_name = "wsa_macro_rx1",
  5951. .no_pcm = 1,
  5952. .dpcm_playback = 1,
  5953. .init = &msm_wsa_cdc_dma_init,
  5954. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  5955. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5956. .ignore_pmdown_time = 1,
  5957. .ignore_suspend = 1,
  5958. .ops = &msm_cdc_dma_be_ops,
  5959. },
  5960. {
  5961. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5962. .stream_name = "WSA CDC DMA0 Capture",
  5963. .cpu_dai_name = "msm-dai-cdc-dma.45057",
  5964. .platform_name = "msm-pcm-hostless",
  5965. .codec_name = "bolero_codec",
  5966. .codec_dai_name = "wsa_macro_vifeedback",
  5967. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5968. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5969. .ignore_suspend = 1,
  5970. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5971. .ops = &msm_cdc_dma_be_ops,
  5972. },
  5973. {
  5974. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  5975. .stream_name = "WSA CDC DMA1 Playback",
  5976. .cpu_dai_name = "msm-dai-cdc-dma.45058",
  5977. .platform_name = "msm-pcm-routing",
  5978. .codec_name = "bolero_codec",
  5979. .codec_dai_name = "wsa_macro_rx_mix",
  5980. .no_pcm = 1,
  5981. .dpcm_playback = 1,
  5982. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  5983. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5984. .ignore_pmdown_time = 1,
  5985. .ignore_suspend = 1,
  5986. .ops = &msm_cdc_dma_be_ops,
  5987. },
  5988. {
  5989. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  5990. .stream_name = "WSA CDC DMA1 Capture",
  5991. .cpu_dai_name = "msm-dai-cdc-dma.45059",
  5992. .platform_name = "msm-pcm-routing",
  5993. .codec_name = "bolero_codec",
  5994. .codec_dai_name = "wsa_macro_echo",
  5995. .no_pcm = 1,
  5996. .dpcm_capture = 1,
  5997. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  5998. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5999. .ignore_suspend = 1,
  6000. .ops = &msm_cdc_dma_be_ops,
  6001. },
  6002. {
  6003. .name = LPASS_BE_WSA_CDC_DMA_TX_2,
  6004. .stream_name = "WSA CDC DMA2 Capture",
  6005. .cpu_dai_name = "msm-dai-cdc-dma.45061",
  6006. .platform_name = "msm-pcm-routing",
  6007. .codec_name = "bolero_codec",
  6008. .codec_dai_name = "msm-stub-tx",
  6009. .no_pcm = 1,
  6010. .dpcm_capture = 1,
  6011. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2,
  6012. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6013. .ignore_suspend = 1,
  6014. .ops = &msm_cdc_dma_be_ops,
  6015. },
  6016. };
  6017. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6018. {
  6019. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6020. .stream_name = "VA CDC DMA0 Capture",
  6021. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6022. .platform_name = "msm-pcm-routing",
  6023. .codec_name = "bolero_codec",
  6024. .codec_dai_name = "va_macro_tx1",
  6025. .no_pcm = 1,
  6026. .dpcm_capture = 1,
  6027. .init = &msm_va_cdc_dma_init,
  6028. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6029. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6030. .ignore_suspend = 1,
  6031. .ops = &msm_cdc_dma_be_ops,
  6032. },
  6033. {
  6034. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6035. .stream_name = "VA CDC DMA1 Capture",
  6036. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6037. .platform_name = "msm-pcm-routing",
  6038. .codec_name = "bolero_codec",
  6039. .codec_dai_name = "va_macro_tx2",
  6040. .no_pcm = 1,
  6041. .dpcm_capture = 1,
  6042. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6043. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6044. .ignore_suspend = 1,
  6045. .ops = &msm_cdc_dma_be_ops,
  6046. },
  6047. };
  6048. static struct snd_soc_dai_link msm_qcs405_dai_links[
  6049. ARRAY_SIZE(msm_common_dai_links) +
  6050. ARRAY_SIZE(msm_tasha_fe_dai_links) +
  6051. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6052. ARRAY_SIZE(msm_common_be_dai_links) +
  6053. ARRAY_SIZE(msm_tasha_be_dai_links) +
  6054. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6055. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6056. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6057. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6058. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links)];
  6059. static int msm_snd_card_tasha_late_probe(struct snd_soc_card *card)
  6060. {
  6061. int ret = 0;
  6062. ret = audio_notifier_register("qcs405", AUDIO_NOTIFIER_ADSP_DOMAIN,
  6063. &service_nb);
  6064. if (ret < 0)
  6065. pr_err("%s: Audio notifier register failed ret = %d\n",
  6066. __func__, ret);
  6067. return ret;
  6068. }
  6069. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  6070. struct snd_ctl_elem_value *ucontrol)
  6071. {
  6072. int ret = 0;
  6073. int port_id;
  6074. uint32_t vad_enable = ucontrol->value.integer.value[0];
  6075. uint32_t preroll_config = ucontrol->value.integer.value[1];
  6076. uint32_t vad_intf = ucontrol->value.integer.value[2];
  6077. if ((preroll_config < 0) || (preroll_config > 1000) ||
  6078. (vad_enable < 0) || (vad_enable > 1) ||
  6079. (vad_intf > MSM_BACKEND_DAI_MAX)) {
  6080. pr_err("%s: Invalid arguments\n", __func__);
  6081. ret = -EINVAL;
  6082. goto done;
  6083. }
  6084. pr_debug("%s: vad_enable=%d preroll_config=%d vad_intf=%d\n", __func__,
  6085. vad_enable, preroll_config, vad_intf);
  6086. ret = msm_vad_get_portid_from_beid(vad_intf, &port_id);
  6087. if (ret) {
  6088. pr_err("%s: Invalid vad interface\n", __func__);
  6089. goto done;
  6090. }
  6091. afe_set_vad_cfg(vad_enable, preroll_config, port_id);
  6092. done:
  6093. return ret;
  6094. }
  6095. static int msm_snd_card_codec_late_probe(struct snd_soc_card *card)
  6096. {
  6097. int ret = 0;
  6098. uint32_t tasha_codec = 0;
  6099. ret = afe_cal_init_hwdep(card);
  6100. if (ret) {
  6101. dev_err(card->dev, "afe cal hwdep init failed (%d)\n", ret);
  6102. ret = 0;
  6103. }
  6104. /* tasha late probe when it is present */
  6105. ret = of_property_read_u32(card->dev->of_node, "qcom,tasha-codec",
  6106. &tasha_codec);
  6107. if (ret) {
  6108. dev_err(card->dev, "%s: No DT match tasha codec\n", __func__);
  6109. ret = 0;
  6110. } else {
  6111. if (tasha_codec) {
  6112. ret = msm_snd_card_tasha_late_probe(card);
  6113. if (ret)
  6114. dev_err(card->dev, "%s: tasha late probe err\n",
  6115. __func__);
  6116. }
  6117. }
  6118. return ret;
  6119. }
  6120. struct snd_soc_card snd_soc_card_qcs405_msm = {
  6121. .name = "qcs405-snd-card",
  6122. .controls = msm_snd_controls,
  6123. .num_controls = ARRAY_SIZE(msm_snd_controls),
  6124. .late_probe = msm_snd_card_codec_late_probe,
  6125. };
  6126. static int msm_populate_dai_link_component_of_node(
  6127. struct snd_soc_card *card)
  6128. {
  6129. int i, index, ret = 0;
  6130. struct device *cdev = card->dev;
  6131. struct snd_soc_dai_link *dai_link = card->dai_link;
  6132. struct device_node *np;
  6133. if (!cdev) {
  6134. pr_err("%s: Sound card device memory NULL\n", __func__);
  6135. return -ENODEV;
  6136. }
  6137. for (i = 0; i < card->num_links; i++) {
  6138. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6139. continue;
  6140. /* populate platform_of_node for snd card dai links */
  6141. if (dai_link[i].platform_name &&
  6142. !dai_link[i].platform_of_node) {
  6143. index = of_property_match_string(cdev->of_node,
  6144. "asoc-platform-names",
  6145. dai_link[i].platform_name);
  6146. if (index < 0) {
  6147. pr_err("%s: No match found for platform name: %s\n",
  6148. __func__, dai_link[i].platform_name);
  6149. ret = index;
  6150. goto err;
  6151. }
  6152. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6153. index);
  6154. if (!np) {
  6155. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  6156. __func__, dai_link[i].platform_name,
  6157. index);
  6158. ret = -ENODEV;
  6159. goto err;
  6160. }
  6161. dai_link[i].platform_of_node = np;
  6162. dai_link[i].platform_name = NULL;
  6163. }
  6164. /* populate cpu_of_node for snd card dai links */
  6165. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6166. index = of_property_match_string(cdev->of_node,
  6167. "asoc-cpu-names",
  6168. dai_link[i].cpu_dai_name);
  6169. if (index >= 0) {
  6170. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6171. index);
  6172. if (!np) {
  6173. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  6174. __func__,
  6175. dai_link[i].cpu_dai_name);
  6176. ret = -ENODEV;
  6177. goto err;
  6178. }
  6179. dai_link[i].cpu_of_node = np;
  6180. dai_link[i].cpu_dai_name = NULL;
  6181. }
  6182. }
  6183. /* populate codec_of_node for snd card dai links */
  6184. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6185. index = of_property_match_string(cdev->of_node,
  6186. "asoc-codec-names",
  6187. dai_link[i].codec_name);
  6188. if (index < 0)
  6189. continue;
  6190. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6191. index);
  6192. if (!np) {
  6193. pr_err("%s: retrieving phandle for codec %s failed\n",
  6194. __func__, dai_link[i].codec_name);
  6195. ret = -ENODEV;
  6196. goto err;
  6197. }
  6198. dai_link[i].codec_of_node = np;
  6199. dai_link[i].codec_name = NULL;
  6200. }
  6201. }
  6202. err:
  6203. return ret;
  6204. }
  6205. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6206. /* FrontEnd DAI Links */
  6207. {
  6208. .name = "MSMSTUB Media1",
  6209. .stream_name = "MultiMedia1",
  6210. .cpu_dai_name = "MultiMedia1",
  6211. .platform_name = "msm-pcm-dsp.0",
  6212. .dynamic = 1,
  6213. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6214. .dpcm_playback = 1,
  6215. .dpcm_capture = 1,
  6216. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6217. SND_SOC_DPCM_TRIGGER_POST},
  6218. .codec_dai_name = "snd-soc-dummy-dai",
  6219. .codec_name = "snd-soc-dummy",
  6220. .ignore_suspend = 1,
  6221. /* this dainlink has playback support */
  6222. .ignore_pmdown_time = 1,
  6223. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6224. },
  6225. };
  6226. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6227. /* Backend DAI Links */
  6228. {
  6229. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6230. .stream_name = "VA CDC DMA0 Capture",
  6231. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6232. .platform_name = "msm-pcm-routing",
  6233. .codec_name = "bolero_codec",
  6234. .codec_dai_name = "va_macro_tx1",
  6235. .no_pcm = 1,
  6236. .dpcm_capture = 1,
  6237. .init = &msm_va_cdc_dma_init,
  6238. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6239. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6240. .ignore_suspend = 1,
  6241. .ops = &msm_cdc_dma_be_ops,
  6242. },
  6243. {
  6244. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6245. .stream_name = "VA CDC DMA1 Capture",
  6246. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6247. .platform_name = "msm-pcm-routing",
  6248. .codec_name = "bolero_codec",
  6249. .codec_dai_name = "va_macro_tx2",
  6250. .no_pcm = 1,
  6251. .dpcm_capture = 1,
  6252. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6253. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6254. .ignore_suspend = 1,
  6255. .ops = &msm_cdc_dma_be_ops,
  6256. },
  6257. };
  6258. static struct snd_soc_dai_link msm_stub_dai_links[
  6259. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6260. ARRAY_SIZE(msm_stub_be_dai_links)];
  6261. struct snd_soc_card snd_soc_card_stub_msm = {
  6262. .name = "qcs405-stub-snd-card",
  6263. };
  6264. static const struct of_device_id qcs405_asoc_machine_of_match[] = {
  6265. { .compatible = "qcom,qcs405-asoc-snd",
  6266. .data = "codec"},
  6267. { .compatible = "qcom,qcs405-asoc-snd-stub",
  6268. .data = "stub_codec"},
  6269. {},
  6270. };
  6271. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6272. {
  6273. struct snd_soc_card *card = NULL;
  6274. struct snd_soc_dai_link *dailink;
  6275. int total_links = 0;
  6276. uint32_t tasha_codec = 0, auxpcm_audio_intf = 0;
  6277. uint32_t va_bolero_codec = 0, wsa_bolero_codec = 0, mi2s_audio_intf = 0;
  6278. const struct of_device_id *match;
  6279. int rc = 0;
  6280. match = of_match_node(qcs405_asoc_machine_of_match, dev->of_node);
  6281. if (!match) {
  6282. dev_err(dev, "%s: No DT match found for sound card\n",
  6283. __func__);
  6284. return NULL;
  6285. }
  6286. if (!strcmp(match->data, "codec")) {
  6287. card = &snd_soc_card_qcs405_msm;
  6288. memcpy(msm_qcs405_dai_links + total_links,
  6289. msm_common_dai_links,
  6290. sizeof(msm_common_dai_links));
  6291. total_links += ARRAY_SIZE(msm_common_dai_links);
  6292. rc = of_property_read_u32(dev->of_node, "qcom,tasha-codec",
  6293. &tasha_codec);
  6294. if (rc) {
  6295. dev_dbg(dev, "%s: No DT match tasha codec\n",
  6296. __func__);
  6297. } else {
  6298. if (tasha_codec) {
  6299. dev_dbg(dev, "%s(): Tasha codec is present\n",
  6300. __func__);
  6301. memcpy(msm_qcs405_dai_links + total_links,
  6302. msm_tasha_fe_dai_links,
  6303. sizeof(msm_tasha_fe_dai_links));
  6304. total_links +=
  6305. ARRAY_SIZE(msm_tasha_fe_dai_links);
  6306. }
  6307. }
  6308. memcpy(msm_qcs405_dai_links + total_links,
  6309. msm_common_misc_fe_dai_links,
  6310. sizeof(msm_common_misc_fe_dai_links));
  6311. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  6312. memcpy(msm_qcs405_dai_links + total_links,
  6313. msm_common_be_dai_links,
  6314. sizeof(msm_common_be_dai_links));
  6315. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  6316. if (tasha_codec) {
  6317. memcpy(msm_qcs405_dai_links + total_links,
  6318. msm_tasha_be_dai_links,
  6319. sizeof(msm_tasha_be_dai_links));
  6320. total_links += ARRAY_SIZE(msm_tasha_be_dai_links);
  6321. }
  6322. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  6323. &va_bolero_codec);
  6324. if (rc) {
  6325. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  6326. __func__);
  6327. } else {
  6328. if (va_bolero_codec) {
  6329. dev_dbg(dev, "%s(): VA macro in bolero codec present\n",
  6330. __func__);
  6331. memcpy(msm_qcs405_dai_links + total_links,
  6332. msm_va_cdc_dma_be_dai_links,
  6333. sizeof(msm_va_cdc_dma_be_dai_links));
  6334. total_links +=
  6335. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  6336. }
  6337. }
  6338. rc = of_property_read_u32(dev->of_node, "qcom,wsa-bolero-codec",
  6339. &wsa_bolero_codec);
  6340. if (rc) {
  6341. dev_dbg(dev, "%s: No DT match WSA Macro codec\n",
  6342. __func__);
  6343. } else {
  6344. if (wsa_bolero_codec) {
  6345. dev_dbg(dev, "%s(): WSAmacro in bolero codec present\n",
  6346. __func__);
  6347. memcpy(msm_qcs405_dai_links + total_links,
  6348. msm_wsa_cdc_dma_be_dai_links,
  6349. sizeof(msm_wsa_cdc_dma_be_dai_links));
  6350. total_links +=
  6351. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  6352. }
  6353. }
  6354. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  6355. &mi2s_audio_intf);
  6356. if (rc) {
  6357. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  6358. __func__);
  6359. } else {
  6360. if (mi2s_audio_intf) {
  6361. memcpy(msm_qcs405_dai_links + total_links,
  6362. msm_mi2s_be_dai_links,
  6363. sizeof(msm_mi2s_be_dai_links));
  6364. total_links +=
  6365. ARRAY_SIZE(msm_mi2s_be_dai_links);
  6366. }
  6367. }
  6368. rc = of_property_read_u32(dev->of_node,
  6369. "qcom,auxpcm-audio-intf",
  6370. &auxpcm_audio_intf);
  6371. if (rc) {
  6372. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  6373. __func__);
  6374. } else {
  6375. if (auxpcm_audio_intf) {
  6376. memcpy(msm_qcs405_dai_links + total_links,
  6377. msm_auxpcm_be_dai_links,
  6378. sizeof(msm_auxpcm_be_dai_links));
  6379. total_links +=
  6380. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  6381. }
  6382. }
  6383. dailink = msm_qcs405_dai_links;
  6384. } else if (!strcmp(match->data, "stub_codec")) {
  6385. card = &snd_soc_card_stub_msm;
  6386. memcpy(msm_stub_dai_links + total_links,
  6387. msm_stub_fe_dai_links,
  6388. sizeof(msm_stub_fe_dai_links));
  6389. total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
  6390. memcpy(msm_stub_dai_links + total_links,
  6391. msm_stub_be_dai_links,
  6392. sizeof(msm_stub_be_dai_links));
  6393. total_links += ARRAY_SIZE(msm_stub_be_dai_links);
  6394. dailink = msm_stub_dai_links;
  6395. }
  6396. if (card) {
  6397. card->dai_link = dailink;
  6398. card->num_links = total_links;
  6399. }
  6400. return card;
  6401. }
  6402. static int msm_wsa881x_init(struct snd_soc_component *component)
  6403. {
  6404. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6405. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6406. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  6407. SPKR_L_BOOST, SPKR_L_VI};
  6408. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  6409. SPKR_R_BOOST, SPKR_R_VI};
  6410. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  6411. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  6412. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  6413. struct msm_asoc_mach_data *pdata;
  6414. struct snd_soc_dapm_context *dapm;
  6415. int ret = 0;
  6416. if (!codec) {
  6417. pr_err("%s codec is NULL\n", __func__);
  6418. return -EINVAL;
  6419. }
  6420. dapm = snd_soc_codec_get_dapm(codec);
  6421. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  6422. dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n",
  6423. __func__, codec->component.name);
  6424. wsa881x_set_channel_map(codec, &spkleft_ports[0],
  6425. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6426. &ch_rate[0], &spkleft_port_types[0]);
  6427. if (dapm->component) {
  6428. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  6429. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  6430. }
  6431. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  6432. dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n",
  6433. __func__, codec->component.name);
  6434. wsa881x_set_channel_map(codec, &spkright_ports[0],
  6435. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6436. &ch_rate[0], &spkright_port_types[0]);
  6437. if (dapm->component) {
  6438. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  6439. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  6440. }
  6441. } else {
  6442. dev_err(codec->dev, "%s: wrong codec name %s\n", __func__,
  6443. codec->component.name);
  6444. ret = -EINVAL;
  6445. goto err;
  6446. }
  6447. pdata = snd_soc_card_get_drvdata(component->card);
  6448. if (pdata && pdata->codec_root)
  6449. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  6450. codec);
  6451. err:
  6452. return ret;
  6453. }
  6454. static int msm_init_wsa_dev(struct platform_device *pdev,
  6455. struct snd_soc_card *card)
  6456. {
  6457. struct device_node *wsa_of_node;
  6458. u32 wsa_max_devs;
  6459. u32 wsa_dev_cnt;
  6460. int i;
  6461. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  6462. const char *wsa_auxdev_name_prefix[1];
  6463. char *dev_name_str = NULL;
  6464. int found = 0;
  6465. int ret = 0;
  6466. /* Get maximum WSA device count for this platform */
  6467. ret = of_property_read_u32(pdev->dev.of_node,
  6468. "qcom,wsa-max-devs", &wsa_max_devs);
  6469. if (ret) {
  6470. dev_info(&pdev->dev,
  6471. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  6472. __func__, pdev->dev.of_node->full_name, ret);
  6473. card->num_aux_devs = 0;
  6474. return 0;
  6475. }
  6476. if (wsa_max_devs == 0) {
  6477. dev_warn(&pdev->dev,
  6478. "%s: Max WSA devices is 0 for this target?\n",
  6479. __func__);
  6480. card->num_aux_devs = 0;
  6481. return 0;
  6482. }
  6483. /* Get count of WSA device phandles for this platform */
  6484. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  6485. "qcom,wsa-devs", NULL);
  6486. if (wsa_dev_cnt == -ENOENT) {
  6487. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  6488. __func__);
  6489. goto err;
  6490. } else if (wsa_dev_cnt <= 0) {
  6491. dev_err(&pdev->dev,
  6492. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  6493. __func__, wsa_dev_cnt);
  6494. ret = -EINVAL;
  6495. goto err;
  6496. }
  6497. /*
  6498. * Expect total phandles count to be NOT less than maximum possible
  6499. * WSA count. However, if it is less, then assign same value to
  6500. * max count as well.
  6501. */
  6502. if (wsa_dev_cnt < wsa_max_devs) {
  6503. dev_dbg(&pdev->dev,
  6504. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  6505. __func__, wsa_max_devs, wsa_dev_cnt);
  6506. wsa_max_devs = wsa_dev_cnt;
  6507. }
  6508. /* Make sure prefix string passed for each WSA device */
  6509. ret = of_property_count_strings(pdev->dev.of_node,
  6510. "qcom,wsa-aux-dev-prefix");
  6511. if (ret != wsa_dev_cnt) {
  6512. dev_err(&pdev->dev,
  6513. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  6514. __func__, wsa_dev_cnt, ret);
  6515. ret = -EINVAL;
  6516. goto err;
  6517. }
  6518. /*
  6519. * Alloc mem to store phandle and index info of WSA device, if already
  6520. * registered with ALSA core
  6521. */
  6522. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  6523. sizeof(struct msm_wsa881x_dev_info),
  6524. GFP_KERNEL);
  6525. if (!wsa881x_dev_info) {
  6526. ret = -ENOMEM;
  6527. goto err;
  6528. }
  6529. /*
  6530. * search and check whether all WSA devices are already
  6531. * registered with ALSA core or not. If found a node, store
  6532. * the node and the index in a local array of struct for later
  6533. * use.
  6534. */
  6535. for (i = 0; i < wsa_dev_cnt; i++) {
  6536. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  6537. "qcom,wsa-devs", i);
  6538. if (unlikely(!wsa_of_node)) {
  6539. /* we should not be here */
  6540. dev_err(&pdev->dev,
  6541. "%s: wsa dev node is not present\n",
  6542. __func__);
  6543. ret = -EINVAL;
  6544. goto err_free_dev_info;
  6545. }
  6546. if (soc_find_component(wsa_of_node, NULL)) {
  6547. /* WSA device registered with ALSA core */
  6548. wsa881x_dev_info[found].of_node = wsa_of_node;
  6549. wsa881x_dev_info[found].index = i;
  6550. found++;
  6551. if (found == wsa_max_devs)
  6552. break;
  6553. }
  6554. }
  6555. if (found < wsa_max_devs) {
  6556. dev_dbg(&pdev->dev,
  6557. "%s: failed to find %d components. Found only %d\n",
  6558. __func__, wsa_max_devs, found);
  6559. return -EPROBE_DEFER;
  6560. }
  6561. dev_info(&pdev->dev,
  6562. "%s: found %d wsa881x devices registered with ALSA core\n",
  6563. __func__, found);
  6564. card->num_aux_devs = wsa_max_devs;
  6565. card->num_configs = wsa_max_devs;
  6566. /* Alloc array of AUX devs struct */
  6567. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6568. sizeof(struct snd_soc_aux_dev),
  6569. GFP_KERNEL);
  6570. if (!msm_aux_dev) {
  6571. ret = -ENOMEM;
  6572. goto err_free_dev_info;
  6573. }
  6574. /* Alloc array of codec conf struct */
  6575. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6576. sizeof(struct snd_soc_codec_conf),
  6577. GFP_KERNEL);
  6578. if (!msm_codec_conf) {
  6579. ret = -ENOMEM;
  6580. goto err_free_aux_dev;
  6581. }
  6582. for (i = 0; i < card->num_aux_devs; i++) {
  6583. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  6584. GFP_KERNEL);
  6585. if (!dev_name_str) {
  6586. ret = -ENOMEM;
  6587. goto err_free_cdc_conf;
  6588. }
  6589. ret = of_property_read_string_index(pdev->dev.of_node,
  6590. "qcom,wsa-aux-dev-prefix",
  6591. wsa881x_dev_info[i].index,
  6592. wsa_auxdev_name_prefix);
  6593. if (ret) {
  6594. dev_err(&pdev->dev,
  6595. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  6596. __func__, ret);
  6597. ret = -EINVAL;
  6598. goto err_free_dev_name_str;
  6599. }
  6600. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  6601. msm_aux_dev[i].name = dev_name_str;
  6602. msm_aux_dev[i].codec_name = NULL;
  6603. msm_aux_dev[i].codec_of_node =
  6604. wsa881x_dev_info[i].of_node;
  6605. msm_aux_dev[i].init = msm_wsa881x_init;
  6606. msm_codec_conf[i].dev_name = NULL;
  6607. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  6608. msm_codec_conf[i].of_node =
  6609. wsa881x_dev_info[i].of_node;
  6610. }
  6611. card->codec_conf = msm_codec_conf;
  6612. card->aux_dev = msm_aux_dev;
  6613. return 0;
  6614. err_free_dev_name_str:
  6615. devm_kfree(&pdev->dev, dev_name_str);
  6616. err_free_cdc_conf:
  6617. devm_kfree(&pdev->dev, msm_codec_conf);
  6618. err_free_aux_dev:
  6619. devm_kfree(&pdev->dev, msm_aux_dev);
  6620. err_free_dev_info:
  6621. devm_kfree(&pdev->dev, wsa881x_dev_info);
  6622. err:
  6623. return ret;
  6624. }
  6625. static int msm_csra66x0_init(struct snd_soc_component *component)
  6626. {
  6627. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  6628. if (!codec) {
  6629. pr_err("%s codec is NULL\n", __func__);
  6630. return -EINVAL;
  6631. }
  6632. return 0;
  6633. }
  6634. static int msm_init_csra_dev(struct platform_device *pdev,
  6635. struct snd_soc_card *card)
  6636. {
  6637. struct device_node *csra_of_node;
  6638. u32 csra_max_devs;
  6639. u32 csra_dev_cnt;
  6640. char *dev_name_str = NULL;
  6641. struct msm_csra66x0_dev_info *csra66x0_dev_info;
  6642. const char *csra_auxdev_name_prefix[1];
  6643. int i;
  6644. int found = 0;
  6645. int ret = 0;
  6646. /* Get maximum CSRA device count for this platform */
  6647. ret = of_property_read_u32(pdev->dev.of_node,
  6648. "qcom,csra-max-devs", &csra_max_devs);
  6649. if (ret) {
  6650. dev_info(&pdev->dev,
  6651. "%s: csra-max-devs property missing in DT %s, ret = %d\n",
  6652. __func__, pdev->dev.of_node->full_name, ret);
  6653. card->num_aux_devs = 0;
  6654. return 0;
  6655. }
  6656. if (csra_max_devs == 0) {
  6657. dev_warn(&pdev->dev,
  6658. "%s: Max CSRA devices is 0 for this target?\n",
  6659. __func__);
  6660. return 0;
  6661. }
  6662. /* Get count of CSRA device phandles for this platform */
  6663. csra_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  6664. "qcom,csra-devs", NULL);
  6665. if (csra_dev_cnt == -ENOENT) {
  6666. dev_warn(&pdev->dev, "%s: No csra device defined in DT.\n",
  6667. __func__);
  6668. goto err;
  6669. } else if (csra_dev_cnt <= 0) {
  6670. dev_err(&pdev->dev,
  6671. "%s: Error reading csra device from DT. csra_dev_cnt = %d\n",
  6672. __func__, csra_dev_cnt);
  6673. ret = -EINVAL;
  6674. goto err;
  6675. }
  6676. /*
  6677. * Expect total phandles count to be NOT less than maximum possible
  6678. * CSRA count. However, if it is less, then assign same value to
  6679. * max count as well.
  6680. */
  6681. if (csra_dev_cnt < csra_max_devs) {
  6682. dev_dbg(&pdev->dev,
  6683. "%s: csra_max_devs = %d cannot exceed csra_dev_cnt = %d\n",
  6684. __func__, csra_max_devs, csra_dev_cnt);
  6685. csra_max_devs = csra_dev_cnt;
  6686. }
  6687. /* Make sure prefix string passed for each CSRA device */
  6688. ret = of_property_count_strings(pdev->dev.of_node,
  6689. "qcom,csra-aux-dev-prefix");
  6690. if (ret != csra_dev_cnt) {
  6691. dev_err(&pdev->dev,
  6692. "%s: expecting %d csra prefix. Defined only %d in DT\n",
  6693. __func__, csra_dev_cnt, ret);
  6694. ret = -EINVAL;
  6695. goto err;
  6696. }
  6697. /*
  6698. * Alloc mem to store phandle and index info of CSRA device, if already
  6699. * registered with ALSA core
  6700. */
  6701. csra66x0_dev_info = devm_kcalloc(&pdev->dev, csra_max_devs,
  6702. sizeof(struct msm_csra66x0_dev_info),
  6703. GFP_KERNEL);
  6704. if (!csra66x0_dev_info) {
  6705. ret = -ENOMEM;
  6706. goto err;
  6707. }
  6708. /*
  6709. * search and check whether all CSRA devices are already
  6710. * registered with ALSA core or not. If found a node, store
  6711. * the node and the index in a local array of struct for later
  6712. * use.
  6713. */
  6714. for (i = 0; i < csra_dev_cnt; i++) {
  6715. csra_of_node = of_parse_phandle(pdev->dev.of_node,
  6716. "qcom,csra-devs", i);
  6717. if (unlikely(!csra_of_node)) {
  6718. /* we should not be here */
  6719. dev_err(&pdev->dev,
  6720. "%s: csra dev node is not present\n",
  6721. __func__);
  6722. ret = -EINVAL;
  6723. goto err_free_dev_info;
  6724. }
  6725. if (soc_find_component(csra_of_node, NULL)) {
  6726. /* CSRA device registered with ALSA core */
  6727. csra66x0_dev_info[found].of_node = csra_of_node;
  6728. csra66x0_dev_info[found].index = i;
  6729. found++;
  6730. if (found == csra_max_devs)
  6731. break;
  6732. }
  6733. }
  6734. if (found < csra_max_devs) {
  6735. dev_dbg(&pdev->dev,
  6736. "%s: failed to find %d components. Found only %d\n",
  6737. __func__, csra_max_devs, found);
  6738. return -EPROBE_DEFER;
  6739. }
  6740. dev_info(&pdev->dev,
  6741. "%s: found %d csra66x0 devices registered with ALSA core\n",
  6742. __func__, found);
  6743. card->num_aux_devs = csra_max_devs;
  6744. card->num_configs = csra_max_devs;
  6745. /* Alloc array of AUX devs struct */
  6746. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6747. sizeof(struct snd_soc_aux_dev), GFP_KERNEL);
  6748. if (!msm_aux_dev) {
  6749. ret = -ENOMEM;
  6750. goto err_free_dev_info;
  6751. }
  6752. /* Alloc array of codec conf struct */
  6753. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6754. sizeof(struct snd_soc_codec_conf), GFP_KERNEL);
  6755. if (!msm_codec_conf) {
  6756. ret = -ENOMEM;
  6757. goto err_free_aux_dev;
  6758. }
  6759. for (i = 0; i < card->num_aux_devs; i++) {
  6760. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  6761. GFP_KERNEL);
  6762. if (!dev_name_str) {
  6763. ret = -ENOMEM;
  6764. goto err_free_cdc_conf;
  6765. }
  6766. ret = of_property_read_string_index(pdev->dev.of_node,
  6767. "qcom,csra-aux-dev-prefix",
  6768. csra66x0_dev_info[i].index,
  6769. csra_auxdev_name_prefix);
  6770. if (ret) {
  6771. dev_err(&pdev->dev,
  6772. "%s: failed to read csra aux dev prefix, ret = %d\n",
  6773. __func__, ret);
  6774. ret = -EINVAL;
  6775. goto err_free_dev_name_str;
  6776. }
  6777. snprintf(dev_name_str, strlen("csra66x0.%d"), "csra66x0.%d", i);
  6778. msm_aux_dev[i].name = dev_name_str;
  6779. msm_aux_dev[i].codec_name = NULL;
  6780. msm_aux_dev[i].codec_of_node =
  6781. csra66x0_dev_info[i].of_node;
  6782. msm_aux_dev[i].init = msm_csra66x0_init; /* codec specific init */
  6783. msm_codec_conf[i].dev_name = NULL;
  6784. msm_codec_conf[i].name_prefix = csra_auxdev_name_prefix[0];
  6785. msm_codec_conf[i].of_node = csra66x0_dev_info[i].of_node;
  6786. }
  6787. card->codec_conf = msm_codec_conf;
  6788. card->aux_dev = msm_aux_dev;
  6789. return 0;
  6790. err_free_dev_name_str:
  6791. devm_kfree(&pdev->dev, dev_name_str);
  6792. err_free_cdc_conf:
  6793. devm_kfree(&pdev->dev, msm_codec_conf);
  6794. err_free_aux_dev:
  6795. devm_kfree(&pdev->dev, msm_aux_dev);
  6796. err_free_dev_info:
  6797. devm_kfree(&pdev->dev, csra66x0_dev_info);
  6798. err:
  6799. return ret;
  6800. }
  6801. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  6802. {
  6803. int count;
  6804. u32 mi2s_master_slave[MI2S_MAX];
  6805. int ret;
  6806. for (count = 0; count < MI2S_MAX; count++) {
  6807. mutex_init(&mi2s_intf_conf[count].lock);
  6808. mi2s_intf_conf[count].ref_cnt = 0;
  6809. }
  6810. ret = of_property_read_u32_array(pdev->dev.of_node,
  6811. "qcom,msm-mi2s-master",
  6812. mi2s_master_slave, MI2S_MAX);
  6813. if (ret) {
  6814. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  6815. __func__);
  6816. } else {
  6817. for (count = 0; count < MI2S_MAX; count++) {
  6818. mi2s_intf_conf[count].msm_is_mi2s_master =
  6819. mi2s_master_slave[count];
  6820. }
  6821. }
  6822. }
  6823. static void msm_i2s_auxpcm_deinit(void)
  6824. {
  6825. int count;
  6826. for (count = 0; count < MI2S_MAX; count++) {
  6827. mutex_destroy(&mi2s_intf_conf[count].lock);
  6828. mi2s_intf_conf[count].ref_cnt = 0;
  6829. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  6830. }
  6831. }
  6832. static int msm_asoc_machine_probe(struct platform_device *pdev)
  6833. {
  6834. struct snd_soc_card *card;
  6835. struct msm_asoc_mach_data *pdata;
  6836. int ret;
  6837. u32 val;
  6838. if (!pdev->dev.of_node) {
  6839. dev_err(&pdev->dev, "No platform supplied from device tree\n");
  6840. return -EINVAL;
  6841. }
  6842. pdata = devm_kzalloc(&pdev->dev,
  6843. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  6844. if (!pdata)
  6845. return -ENOMEM;
  6846. card = populate_snd_card_dailinks(&pdev->dev);
  6847. if (!card) {
  6848. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  6849. ret = -EINVAL;
  6850. goto err;
  6851. }
  6852. card->dev = &pdev->dev;
  6853. platform_set_drvdata(pdev, card);
  6854. snd_soc_card_set_drvdata(card, pdata);
  6855. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  6856. if (ret) {
  6857. dev_err(&pdev->dev, "parse card name failed, err:%d\n",
  6858. ret);
  6859. goto err;
  6860. }
  6861. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  6862. if (ret) {
  6863. dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
  6864. ret);
  6865. goto err;
  6866. }
  6867. ret = msm_populate_dai_link_component_of_node(card);
  6868. if (ret) {
  6869. ret = -EPROBE_DEFER;
  6870. goto err;
  6871. }
  6872. ret = of_property_read_u32(pdev->dev.of_node, "qcom,csra-codec", &val);
  6873. if (ret) {
  6874. dev_info(&pdev->dev, "no 'qcom,csra-codec' in DT\n");
  6875. val = 0;
  6876. }
  6877. if (val) {
  6878. ret = msm_init_csra_dev(pdev, card);
  6879. if (ret)
  6880. goto err;
  6881. } else {
  6882. ret = msm_init_wsa_dev(pdev, card);
  6883. if (ret)
  6884. goto err;
  6885. }
  6886. pdata->dmic_01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6887. "qcom,cdc-dmic01-gpios",
  6888. 0);
  6889. pdata->dmic_23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6890. "qcom,cdc-dmic23-gpios",
  6891. 0);
  6892. pdata->dmic_45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6893. "qcom,cdc-dmic45-gpios",
  6894. 0);
  6895. pdata->dmic_67_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6896. "qcom,cdc-dmic67-gpios",
  6897. 0);
  6898. ret = devm_snd_soc_register_card(&pdev->dev, card);
  6899. if (ret == -EPROBE_DEFER) {
  6900. if (codec_reg_done)
  6901. ret = -EINVAL;
  6902. goto err;
  6903. } else if (ret) {
  6904. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  6905. ret);
  6906. goto err;
  6907. }
  6908. dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
  6909. spdev = pdev;
  6910. /* Parse pinctrl info from devicetree */
  6911. ret = msm_get_pinctrl(pdev);
  6912. if (!ret) {
  6913. pr_debug("%s: pinctrl parsing successful\n", __func__);
  6914. } else {
  6915. dev_dbg(&pdev->dev,
  6916. "%s: Parsing pinctrl failed with %d. Cannot use Ports\n",
  6917. __func__, ret);
  6918. ret = 0;
  6919. }
  6920. msm_i2s_auxpcm_init(pdev);
  6921. is_initial_boot = true;
  6922. return 0;
  6923. err:
  6924. msm_release_pinctrl(pdev);
  6925. return ret;
  6926. }
  6927. static int msm_asoc_machine_remove(struct platform_device *pdev)
  6928. {
  6929. audio_notifier_deregister("qcs405");
  6930. msm_i2s_auxpcm_deinit();
  6931. msm_release_pinctrl(pdev);
  6932. return 0;
  6933. }
  6934. static struct platform_driver qcs405_asoc_machine_driver = {
  6935. .driver = {
  6936. .name = DRV_NAME,
  6937. .owner = THIS_MODULE,
  6938. .pm = &snd_soc_pm_ops,
  6939. .of_match_table = qcs405_asoc_machine_of_match,
  6940. },
  6941. .probe = msm_asoc_machine_probe,
  6942. .remove = msm_asoc_machine_remove,
  6943. };
  6944. module_platform_driver(qcs405_asoc_machine_driver);
  6945. MODULE_DESCRIPTION("ALSA SoC QCS405 Machine driver");
  6946. MODULE_LICENSE("GPL v2");
  6947. MODULE_ALIAS("platform:" DRV_NAME);
  6948. MODULE_DEVICE_TABLE(of, qcs405_asoc_machine_of_match);