sde_plane.c 135 KB

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  1. /*
  2. * Copyright (C) 2014-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/debugfs.h>
  20. #include <linux/dma-buf.h>
  21. #include <drm/sde_drm.h>
  22. #include <drm/msm_drm_pp.h>
  23. #include "msm_prop.h"
  24. #include "msm_drv.h"
  25. #include "sde_kms.h"
  26. #include "sde_fence.h"
  27. #include "sde_formats.h"
  28. #include "sde_hw_sspp.h"
  29. #include "sde_hw_catalog_format.h"
  30. #include "sde_trace.h"
  31. #include "sde_crtc.h"
  32. #include "sde_vbif.h"
  33. #include "sde_plane.h"
  34. #include "sde_color_processing.h"
  35. #define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
  36. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  37. #define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
  38. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  39. #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
  40. #define PHASE_STEP_SHIFT 21
  41. #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
  42. #define PHASE_RESIDUAL 15
  43. #define SHARP_STRENGTH_DEFAULT 32
  44. #define SHARP_EDGE_THR_DEFAULT 112
  45. #define SHARP_SMOOTH_THR_DEFAULT 8
  46. #define SHARP_NOISE_THR_DEFAULT 2
  47. #define SDE_NAME_SIZE 12
  48. #define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
  49. #define TIME_MULTIPLEX_RECT(r0, r1, buffer_lines) \
  50. ((r0).y >= ((r1).y + (r1).h + buffer_lines))
  51. #define SDE_QSEED_DEFAULT_DYN_EXP 0x0
  52. /**
  53. * enum sde_plane_qos - Different qos configurations for each pipe
  54. *
  55. * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
  56. * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
  57. * this configuration is mutually exclusive from VBLANK_CTRL.
  58. * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
  59. */
  60. enum sde_plane_qos {
  61. SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
  62. SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
  63. SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
  64. };
  65. /*
  66. * struct sde_plane - local sde plane structure
  67. * @aspace: address space pointer
  68. * @csc_cfg: Decoded user configuration for csc
  69. * @csc_usr_ptr: Points to csc_cfg if valid user config available
  70. * @csc_ptr: Points to sde_csc_cfg structure to use for current
  71. * @mplane_list: List of multirect planes of the same pipe
  72. * @catalog: Points to sde catalog structure
  73. * @revalidate: force revalidation of all the plane properties
  74. * @xin_halt_forced_clk: whether or not clocks were forced on for xin halt
  75. * @blob_rot_caps: Pointer to rotator capability blob
  76. */
  77. struct sde_plane {
  78. struct drm_plane base;
  79. struct mutex lock;
  80. enum sde_sspp pipe;
  81. uint64_t features; /* capabilities from catalog */
  82. uint32_t perf_features; /* perf capabilities from catalog */
  83. uint32_t nformats;
  84. uint32_t formats[64];
  85. struct sde_hw_pipe *pipe_hw;
  86. struct sde_hw_pipe_cfg pipe_cfg;
  87. struct sde_hw_sharp_cfg sharp_cfg;
  88. struct sde_hw_pipe_qos_cfg pipe_qos_cfg;
  89. uint32_t color_fill;
  90. bool is_error;
  91. bool is_rt_pipe;
  92. bool is_virtual;
  93. struct list_head mplane_list;
  94. struct sde_mdss_cfg *catalog;
  95. bool revalidate;
  96. bool xin_halt_forced_clk;
  97. struct sde_csc_cfg csc_cfg;
  98. struct sde_csc_cfg *csc_usr_ptr;
  99. struct sde_csc_cfg *csc_ptr;
  100. const struct sde_sspp_sub_blks *pipe_sblk;
  101. char pipe_name[SDE_NAME_SIZE];
  102. struct msm_property_info property_info;
  103. struct msm_property_data property_data[PLANE_PROP_COUNT];
  104. struct drm_property_blob *blob_info;
  105. struct drm_property_blob *blob_rot_caps;
  106. /* debugfs related stuff */
  107. struct dentry *debugfs_root;
  108. bool debugfs_default_scale;
  109. };
  110. #define to_sde_plane(x) container_of(x, struct sde_plane, base)
  111. static int plane_prop_array[PLANE_PROP_COUNT] = {SDE_PLANE_DIRTY_ALL};
  112. static struct sde_kms *_sde_plane_get_kms(struct drm_plane *plane)
  113. {
  114. struct msm_drm_private *priv;
  115. if (!plane || !plane->dev)
  116. return NULL;
  117. priv = plane->dev->dev_private;
  118. if (!priv)
  119. return NULL;
  120. return to_sde_kms(priv->kms);
  121. }
  122. static struct sde_hw_ctl *_sde_plane_get_hw_ctl(const struct drm_plane *plane)
  123. {
  124. struct drm_plane_state *pstate = NULL;
  125. struct drm_crtc *drm_crtc = NULL;
  126. struct sde_crtc *sde_crtc = NULL;
  127. struct sde_crtc_mixer *mixer = NULL;
  128. struct sde_hw_ctl *ctl = NULL;
  129. if (!plane) {
  130. DRM_ERROR("Invalid plane %pK\n", plane);
  131. return NULL;
  132. }
  133. pstate = plane->state;
  134. if (!pstate) {
  135. DRM_ERROR("Invalid plane state %pK\n", pstate);
  136. return NULL;
  137. }
  138. drm_crtc = pstate->crtc;
  139. if (!drm_crtc) {
  140. DRM_ERROR("Invalid drm_crtc %pK\n", drm_crtc);
  141. return NULL;
  142. }
  143. sde_crtc = to_sde_crtc(drm_crtc);
  144. if (!sde_crtc) {
  145. DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
  146. return NULL;
  147. }
  148. /* it will always return the first mixer and single CTL */
  149. mixer = sde_crtc->mixers;
  150. if (!mixer) {
  151. DRM_ERROR("invalid mixer %pK\n", mixer);
  152. return NULL;
  153. }
  154. ctl = mixer->hw_ctl;
  155. if (!mixer) {
  156. DRM_ERROR("invalid ctl %pK\n", ctl);
  157. return NULL;
  158. }
  159. return ctl;
  160. }
  161. static bool sde_plane_enabled(const struct drm_plane_state *state)
  162. {
  163. return state && state->fb && state->crtc;
  164. }
  165. bool sde_plane_is_sec_ui_allowed(struct drm_plane *plane)
  166. {
  167. struct sde_plane *psde;
  168. if (!plane)
  169. return false;
  170. psde = to_sde_plane(plane);
  171. return !(psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI));
  172. }
  173. void sde_plane_setup_src_split_order(struct drm_plane *plane,
  174. enum sde_sspp_multirect_index rect_mode, bool enable)
  175. {
  176. struct sde_plane *psde;
  177. if (!plane)
  178. return;
  179. psde = to_sde_plane(plane);
  180. if (psde->pipe_hw->ops.set_src_split_order)
  181. psde->pipe_hw->ops.set_src_split_order(psde->pipe_hw,
  182. rect_mode, enable);
  183. }
  184. void sde_plane_set_sid(struct drm_plane *plane, u32 vm)
  185. {
  186. struct sde_plane *psde;
  187. struct sde_kms *sde_kms;
  188. struct msm_drm_private *priv;
  189. if (!plane || !plane->dev) {
  190. SDE_ERROR("invalid plane %d\n");
  191. return;
  192. }
  193. priv = plane->dev->dev_private;
  194. if (!priv || !priv->kms) {
  195. SDE_ERROR("invalid KMS reference\n");
  196. return;
  197. }
  198. sde_kms = to_sde_kms(priv->kms);
  199. psde = to_sde_plane(plane);
  200. sde_hw_set_sspp_sid(sde_kms->hw_sid, psde->pipe, vm);
  201. }
  202. void _sde_plane_set_qos_lut(struct drm_plane *plane,
  203. struct drm_crtc *crtc,
  204. struct drm_framebuffer *fb)
  205. {
  206. struct sde_plane *psde;
  207. const struct sde_format *fmt = NULL;
  208. u32 frame_rate, qos_count, fps_index = 0, lut_index, index;
  209. struct sde_perf_cfg *perf;
  210. struct sde_plane_state *pstate;
  211. if (!plane || !fb) {
  212. SDE_ERROR("invalid arguments\n");
  213. return;
  214. }
  215. psde = to_sde_plane(plane);
  216. pstate = to_sde_plane_state(plane->state);
  217. if (!psde->pipe_hw || !psde->pipe_sblk || !psde->catalog) {
  218. SDE_ERROR("invalid arguments\n");
  219. return;
  220. } else if (!psde->pipe_hw->ops.setup_qos_lut) {
  221. return;
  222. }
  223. frame_rate = drm_mode_vrefresh(&crtc->mode);
  224. perf = &psde->catalog->perf;
  225. qos_count = perf->qos_refresh_count;
  226. while ((fps_index < qos_count) && perf->qos_refresh_rate) {
  227. if ((frame_rate <= perf->qos_refresh_rate[fps_index]) ||
  228. (fps_index == qos_count - 1))
  229. break;
  230. fps_index++;
  231. }
  232. if (!psde->is_rt_pipe) {
  233. lut_index = SDE_QOS_LUT_USAGE_NRT;
  234. } else {
  235. fmt = sde_get_sde_format_ext(
  236. fb->format->format,
  237. fb->modifier);
  238. if (fmt && SDE_FORMAT_IS_LINEAR(fmt) &&
  239. pstate->scaler3_cfg.enable)
  240. lut_index = SDE_QOS_LUT_USAGE_LINEAR_QSEED;
  241. else if (fmt && SDE_FORMAT_IS_LINEAR(fmt))
  242. lut_index = SDE_QOS_LUT_USAGE_LINEAR;
  243. else if (pstate->scaler3_cfg.enable)
  244. lut_index = SDE_QOS_LUT_USAGE_MACROTILE_QSEED;
  245. else
  246. lut_index = SDE_QOS_LUT_USAGE_MACROTILE;
  247. }
  248. index = (fps_index * SDE_QOS_LUT_USAGE_MAX) + lut_index;
  249. psde->pipe_qos_cfg.danger_lut = perf->danger_lut[index];
  250. psde->pipe_qos_cfg.safe_lut = perf->safe_lut[index];
  251. psde->pipe_qos_cfg.creq_lut = perf->creq_lut[index];
  252. trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0,
  253. (fmt) ? fmt->base.pixel_format : 0,
  254. (fmt) ? fmt->fetch_mode : 0,
  255. psde->pipe_qos_cfg.danger_lut,
  256. psde->pipe_qos_cfg.safe_lut,
  257. psde->pipe_qos_cfg.creq_lut);
  258. SDE_DEBUG(
  259. "plane%u: pnum:%d fmt:%4.4s fps:%d mode:%d luts[0x%x,0x%x 0x%llx]\n",
  260. plane->base.id,
  261. psde->pipe - SSPP_VIG0,
  262. fmt ? (char *)&fmt->base.pixel_format : NULL, frame_rate,
  263. fmt ? fmt->fetch_mode : -1,
  264. psde->pipe_qos_cfg.danger_lut,
  265. psde->pipe_qos_cfg.safe_lut,
  266. psde->pipe_qos_cfg.creq_lut);
  267. psde->pipe_hw->ops.setup_qos_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
  268. }
  269. /**
  270. * _sde_plane_set_qos_ctrl - set QoS control of the given plane
  271. * @plane: Pointer to drm plane
  272. * @enable: true to enable QoS control
  273. * @flags: QoS control mode (enum sde_plane_qos)
  274. */
  275. static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
  276. bool enable, u32 flags)
  277. {
  278. struct sde_plane *psde;
  279. if (!plane) {
  280. SDE_ERROR("invalid arguments\n");
  281. return;
  282. }
  283. psde = to_sde_plane(plane);
  284. if (!psde->pipe_hw || !psde->pipe_sblk) {
  285. SDE_ERROR("invalid arguments\n");
  286. return;
  287. } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
  288. return;
  289. }
  290. if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
  291. psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
  292. psde->pipe_qos_cfg.danger_vblank =
  293. psde->pipe_sblk->danger_vblank;
  294. psde->pipe_qos_cfg.vblank_en = enable;
  295. }
  296. if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
  297. /* this feature overrules previous VBLANK_CTRL */
  298. psde->pipe_qos_cfg.vblank_en = false;
  299. psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
  300. }
  301. if (flags & SDE_PLANE_QOS_PANIC_CTRL)
  302. psde->pipe_qos_cfg.danger_safe_en = enable;
  303. if (!psde->is_rt_pipe) {
  304. psde->pipe_qos_cfg.vblank_en = false;
  305. psde->pipe_qos_cfg.danger_safe_en = false;
  306. }
  307. SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
  308. plane->base.id,
  309. psde->pipe - SSPP_VIG0,
  310. psde->pipe_qos_cfg.danger_safe_en,
  311. psde->pipe_qos_cfg.vblank_en,
  312. psde->pipe_qos_cfg.creq_vblank,
  313. psde->pipe_qos_cfg.danger_vblank,
  314. psde->is_rt_pipe);
  315. psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
  316. &psde->pipe_qos_cfg);
  317. }
  318. void sde_plane_set_revalidate(struct drm_plane *plane, bool enable)
  319. {
  320. struct sde_plane *psde;
  321. if (!plane)
  322. return;
  323. psde = to_sde_plane(plane);
  324. psde->revalidate = enable;
  325. }
  326. int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
  327. {
  328. struct sde_plane *psde;
  329. int rc;
  330. if (!plane) {
  331. SDE_ERROR("invalid arguments\n");
  332. return -EINVAL;
  333. }
  334. psde = to_sde_plane(plane);
  335. if (!psde->is_rt_pipe)
  336. goto end;
  337. rc = pm_runtime_get_sync(plane->dev->dev);
  338. if (rc < 0) {
  339. SDE_ERROR("failed to enable power resource %d\n", rc);
  340. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  341. return rc;
  342. }
  343. _sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL);
  344. pm_runtime_put_sync(plane->dev->dev);
  345. end:
  346. return 0;
  347. }
  348. /**
  349. * _sde_plane_set_ot_limit - set OT limit for the given plane
  350. * @plane: Pointer to drm plane
  351. * @crtc: Pointer to drm crtc
  352. */
  353. static void _sde_plane_set_ot_limit(struct drm_plane *plane,
  354. struct drm_crtc *crtc)
  355. {
  356. struct sde_plane *psde;
  357. struct sde_vbif_set_ot_params ot_params;
  358. struct msm_drm_private *priv;
  359. struct sde_kms *sde_kms;
  360. if (!plane || !plane->dev || !crtc) {
  361. SDE_ERROR("invalid arguments plane %d crtc %d\n",
  362. !plane, !crtc);
  363. return;
  364. }
  365. priv = plane->dev->dev_private;
  366. if (!priv || !priv->kms) {
  367. SDE_ERROR("invalid KMS reference\n");
  368. return;
  369. }
  370. sde_kms = to_sde_kms(priv->kms);
  371. psde = to_sde_plane(plane);
  372. if (!psde->pipe_hw) {
  373. SDE_ERROR("invalid pipe reference\n");
  374. return;
  375. }
  376. memset(&ot_params, 0, sizeof(ot_params));
  377. ot_params.xin_id = psde->pipe_hw->cap->xin_id;
  378. ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
  379. ot_params.width = psde->pipe_cfg.src_rect.w;
  380. ot_params.height = psde->pipe_cfg.src_rect.h;
  381. ot_params.is_wfd = !psde->is_rt_pipe;
  382. ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
  383. ot_params.vbif_idx = VBIF_RT;
  384. ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  385. ot_params.rd = true;
  386. sde_vbif_set_ot_limit(sde_kms, &ot_params);
  387. }
  388. /**
  389. * _sde_plane_set_vbif_qos - set vbif QoS for the given plane
  390. * @plane: Pointer to drm plane
  391. */
  392. static void _sde_plane_set_qos_remap(struct drm_plane *plane)
  393. {
  394. struct sde_plane *psde;
  395. struct sde_vbif_set_qos_params qos_params;
  396. struct msm_drm_private *priv;
  397. struct sde_kms *sde_kms;
  398. if (!plane || !plane->dev) {
  399. SDE_ERROR("invalid arguments\n");
  400. return;
  401. }
  402. priv = plane->dev->dev_private;
  403. if (!priv || !priv->kms) {
  404. SDE_ERROR("invalid KMS reference\n");
  405. return;
  406. }
  407. sde_kms = to_sde_kms(priv->kms);
  408. psde = to_sde_plane(plane);
  409. if (!psde->pipe_hw) {
  410. SDE_ERROR("invalid pipe reference\n");
  411. return;
  412. }
  413. memset(&qos_params, 0, sizeof(qos_params));
  414. qos_params.vbif_idx = VBIF_RT;
  415. qos_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  416. qos_params.xin_id = psde->pipe_hw->cap->xin_id;
  417. qos_params.num = psde->pipe_hw->idx - SSPP_VIG0;
  418. qos_params.client_type = psde->is_rt_pipe ?
  419. VBIF_RT_CLIENT : VBIF_NRT_CLIENT;
  420. SDE_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
  421. plane->base.id, qos_params.num,
  422. qos_params.vbif_idx,
  423. qos_params.xin_id, qos_params.client_type,
  424. qos_params.clk_ctrl);
  425. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  426. }
  427. /**
  428. * _sde_plane_set_ts_prefill - set prefill with traffic shaper
  429. * @plane: Pointer to drm plane
  430. * @pstate: Pointer to sde plane state
  431. */
  432. static void _sde_plane_set_ts_prefill(struct drm_plane *plane,
  433. struct sde_plane_state *pstate)
  434. {
  435. struct sde_plane *psde;
  436. struct sde_hw_pipe_ts_cfg cfg;
  437. struct msm_drm_private *priv;
  438. struct sde_kms *sde_kms;
  439. if (!plane || !plane->dev) {
  440. SDE_ERROR("invalid arguments");
  441. return;
  442. }
  443. priv = plane->dev->dev_private;
  444. if (!priv || !priv->kms) {
  445. SDE_ERROR("invalid KMS reference\n");
  446. return;
  447. }
  448. sde_kms = to_sde_kms(priv->kms);
  449. psde = to_sde_plane(plane);
  450. if (!psde->pipe_hw) {
  451. SDE_ERROR("invalid pipe reference\n");
  452. return;
  453. }
  454. if (!psde->pipe_hw || !psde->pipe_hw->ops.setup_ts_prefill)
  455. return;
  456. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_VBLANK_AMORTIZE);
  457. memset(&cfg, 0, sizeof(cfg));
  458. cfg.size = sde_plane_get_property(pstate,
  459. PLANE_PROP_PREFILL_SIZE);
  460. cfg.time = sde_plane_get_property(pstate,
  461. PLANE_PROP_PREFILL_TIME);
  462. SDE_DEBUG("plane%d size:%llu time:%llu\n",
  463. plane->base.id, cfg.size, cfg.time);
  464. SDE_EVT32_VERBOSE(DRMID(plane), cfg.size, cfg.time);
  465. psde->pipe_hw->ops.setup_ts_prefill(psde->pipe_hw, &cfg,
  466. pstate->multirect_index);
  467. }
  468. /* helper to update a state's input fence pointer from the property */
  469. static void _sde_plane_set_input_fence(struct sde_plane *psde,
  470. struct sde_plane_state *pstate, uint64_t fd)
  471. {
  472. if (!psde || !pstate) {
  473. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  474. !psde, !pstate);
  475. return;
  476. }
  477. /* clear previous reference */
  478. if (pstate->input_fence)
  479. sde_sync_put(pstate->input_fence);
  480. /* get fence pointer for later */
  481. if (fd == 0)
  482. pstate->input_fence = NULL;
  483. else
  484. pstate->input_fence = sde_sync_get(fd);
  485. SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
  486. }
  487. int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
  488. {
  489. struct sde_plane *psde;
  490. struct sde_plane_state *pstate;
  491. uint32_t prefix;
  492. void *input_fence;
  493. int ret = -EINVAL;
  494. signed long rc;
  495. if (!plane) {
  496. SDE_ERROR("invalid plane\n");
  497. } else if (!plane->state) {
  498. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  499. } else {
  500. psde = to_sde_plane(plane);
  501. pstate = to_sde_plane_state(plane->state);
  502. input_fence = pstate->input_fence;
  503. if (input_fence) {
  504. prefix = sde_sync_get_name_prefix(input_fence);
  505. rc = sde_sync_wait(input_fence, wait_ms);
  506. switch (rc) {
  507. case 0:
  508. SDE_ERROR_PLANE(psde, "%ums timeout on %08X fd %d\n",
  509. wait_ms, prefix, sde_plane_get_property(pstate,
  510. PLANE_PROP_INPUT_FENCE));
  511. psde->is_error = true;
  512. sde_kms_timeline_status(plane->dev);
  513. ret = -ETIMEDOUT;
  514. break;
  515. case -ERESTARTSYS:
  516. SDE_ERROR_PLANE(psde,
  517. "%ums wait interrupted on %08X\n",
  518. wait_ms, prefix);
  519. psde->is_error = true;
  520. ret = -ERESTARTSYS;
  521. break;
  522. case -EINVAL:
  523. SDE_ERROR_PLANE(psde,
  524. "invalid fence param for %08X\n",
  525. prefix);
  526. psde->is_error = true;
  527. ret = -EINVAL;
  528. break;
  529. default:
  530. SDE_DEBUG_PLANE(psde, "signaled\n");
  531. ret = 0;
  532. break;
  533. }
  534. SDE_EVT32_VERBOSE(DRMID(plane), -ret, prefix);
  535. } else {
  536. ret = 0;
  537. }
  538. }
  539. return ret;
  540. }
  541. /**
  542. * _sde_plane_get_aspace: gets the address space based on the
  543. * fb_translation mode property
  544. */
  545. static int _sde_plane_get_aspace(
  546. struct sde_plane *psde,
  547. struct sde_plane_state *pstate,
  548. struct msm_gem_address_space **aspace)
  549. {
  550. struct sde_kms *kms;
  551. int mode;
  552. if (!psde || !pstate || !aspace) {
  553. SDE_ERROR("invalid parameters\n");
  554. return -EINVAL;
  555. }
  556. kms = _sde_plane_get_kms(&psde->base);
  557. if (!kms) {
  558. SDE_ERROR("invalid kms\n");
  559. return -EINVAL;
  560. }
  561. mode = sde_plane_get_property(pstate,
  562. PLANE_PROP_FB_TRANSLATION_MODE);
  563. switch (mode) {
  564. case SDE_DRM_FB_NON_SEC:
  565. *aspace = kms->aspace[MSM_SMMU_DOMAIN_UNSECURE];
  566. if (!aspace)
  567. return -EINVAL;
  568. break;
  569. case SDE_DRM_FB_SEC:
  570. *aspace = kms->aspace[MSM_SMMU_DOMAIN_SECURE];
  571. if (!aspace)
  572. return -EINVAL;
  573. break;
  574. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  575. case SDE_DRM_FB_SEC_DIR_TRANS:
  576. *aspace = NULL;
  577. break;
  578. default:
  579. SDE_ERROR("invalid fb_translation mode:%d\n", mode);
  580. return -EFAULT;
  581. }
  582. return 0;
  583. }
  584. static inline void _sde_plane_set_scanout(struct drm_plane *plane,
  585. struct sde_plane_state *pstate,
  586. struct sde_hw_pipe_cfg *pipe_cfg,
  587. struct drm_framebuffer *fb)
  588. {
  589. struct sde_plane *psde;
  590. struct msm_gem_address_space *aspace = NULL;
  591. int ret, mode;
  592. bool secure = false;
  593. if (!plane || !pstate || !pipe_cfg || !fb) {
  594. SDE_ERROR(
  595. "invalid arg(s), plane %d state %d cfg %d fb %d\n",
  596. !plane, !pstate, !pipe_cfg, !fb);
  597. return;
  598. }
  599. psde = to_sde_plane(plane);
  600. if (!psde->pipe_hw) {
  601. SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
  602. return;
  603. }
  604. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  605. if (ret) {
  606. SDE_ERROR_PLANE(psde, "Failed to get aspace %d\n", ret);
  607. return;
  608. }
  609. /*
  610. * framebuffer prepare is deferred for prepare_fb calls that
  611. * happen during the transition from secure to non-secure.
  612. * Handle the prepare at this point for such cases. This can be
  613. * expected for one or two frames during the transition.
  614. */
  615. if (aspace && pstate->defer_prepare_fb) {
  616. SDE_EVT32(DRMID(plane), psde->pipe, aspace->domain_attached);
  617. ret = msm_framebuffer_prepare(fb, pstate->aspace);
  618. if (ret) {
  619. SDE_ERROR_PLANE(psde,
  620. "failed to prepare framebuffer %d\n", ret);
  621. return;
  622. }
  623. pstate->defer_prepare_fb = false;
  624. }
  625. mode = sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE);
  626. if ((mode == SDE_DRM_FB_SEC) || (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  627. secure = true;
  628. ret = sde_format_populate_layout(aspace, fb, &pipe_cfg->layout);
  629. if (ret == -EAGAIN)
  630. SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
  631. else if (ret) {
  632. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  633. /*
  634. * Force solid fill color on error. This is to prevent
  635. * smmu faults during secure session transition.
  636. */
  637. psde->is_error = true;
  638. } else if (psde->pipe_hw->ops.setup_sourceaddress) {
  639. SDE_EVT32_VERBOSE(psde->pipe_hw->idx,
  640. pipe_cfg->layout.width,
  641. pipe_cfg->layout.height,
  642. pipe_cfg->layout.plane_addr[0],
  643. pipe_cfg->layout.plane_size[0],
  644. pipe_cfg->layout.plane_addr[1],
  645. pipe_cfg->layout.plane_size[1],
  646. pipe_cfg->layout.plane_addr[2],
  647. pipe_cfg->layout.plane_size[2],
  648. pipe_cfg->layout.plane_addr[3],
  649. pipe_cfg->layout.plane_size[3],
  650. pstate->multirect_index,
  651. secure);
  652. psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg,
  653. pstate->multirect_index);
  654. }
  655. }
  656. static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
  657. struct sde_plane_state *pstate)
  658. {
  659. struct sde_hw_scaler3_cfg *cfg;
  660. int ret = 0;
  661. if (!psde || !pstate) {
  662. SDE_ERROR("invalid args\n");
  663. return -EINVAL;
  664. }
  665. cfg = &pstate->scaler3_cfg;
  666. cfg->dir_lut = msm_property_get_blob(
  667. &psde->property_info,
  668. &pstate->property_state, &cfg->dir_len,
  669. PLANE_PROP_SCALER_LUT_ED);
  670. cfg->cir_lut = msm_property_get_blob(
  671. &psde->property_info,
  672. &pstate->property_state, &cfg->cir_len,
  673. PLANE_PROP_SCALER_LUT_CIR);
  674. cfg->sep_lut = msm_property_get_blob(
  675. &psde->property_info,
  676. &pstate->property_state, &cfg->sep_len,
  677. PLANE_PROP_SCALER_LUT_SEP);
  678. if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
  679. ret = -ENODATA;
  680. return ret;
  681. }
  682. static int _sde_plane_setup_scaler3lite_lut(struct sde_plane *psde,
  683. struct sde_plane_state *pstate)
  684. {
  685. struct sde_hw_scaler3_cfg *cfg;
  686. cfg = &pstate->scaler3_cfg;
  687. cfg->sep_lut = msm_property_get_blob(
  688. &psde->property_info,
  689. &pstate->property_state, &cfg->sep_len,
  690. PLANE_PROP_SCALER_LUT_SEP);
  691. return cfg->sep_lut ? 0 : -ENODATA;
  692. }
  693. static void _sde_plane_setup_scaler3(struct sde_plane *psde,
  694. struct sde_plane_state *pstate, const struct sde_format *fmt,
  695. uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
  696. {
  697. uint32_t decimated, i, src_w, src_h, dst_w, dst_h, src_h_pre_down;
  698. struct sde_hw_scaler3_cfg *scale_cfg;
  699. bool pre_down_supported = (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  700. bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90);
  701. if (!fmt || !chroma_subsmpl_h || !chroma_subsmpl_v) {
  702. SDE_ERROR("fmt %d smp_h %d smp_v %d\n", !fmt,
  703. chroma_subsmpl_h, chroma_subsmpl_v);
  704. return;
  705. }
  706. scale_cfg = &pstate->scaler3_cfg;
  707. src_w = psde->pipe_cfg.src_rect.w;
  708. src_h = psde->pipe_cfg.src_rect.h;
  709. dst_w = psde->pipe_cfg.dst_rect.w;
  710. dst_h = psde->pipe_cfg.dst_rect.h;
  711. memset(scale_cfg, 0, sizeof(*scale_cfg));
  712. memset(&pstate->pixel_ext, 0, sizeof(struct sde_hw_pixel_ext));
  713. /*
  714. * For inline rotation cases, scaler config is post-rotation,
  715. * so swap the dimensions here. However, pixel extension will
  716. * need pre-rotation settings, this will be corrected below
  717. * when calculating pixel extension settings.
  718. */
  719. if (inline_rotation)
  720. swap(src_w, src_h);
  721. decimated = DECIMATED_DIMENSION(src_w,
  722. psde->pipe_cfg.horz_decimation);
  723. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] =
  724. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);
  725. decimated = DECIMATED_DIMENSION(src_h,
  726. psde->pipe_cfg.vert_decimation);
  727. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] =
  728. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);
  729. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2] =
  730. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] / chroma_subsmpl_v;
  731. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2] =
  732. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] / chroma_subsmpl_h;
  733. scale_cfg->phase_step_x[SDE_SSPP_COMP_2] =
  734. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2];
  735. scale_cfg->phase_step_y[SDE_SSPP_COMP_2] =
  736. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2];
  737. scale_cfg->phase_step_x[SDE_SSPP_COMP_3] =
  738. scale_cfg->phase_step_x[SDE_SSPP_COMP_0];
  739. scale_cfg->phase_step_y[SDE_SSPP_COMP_3] =
  740. scale_cfg->phase_step_y[SDE_SSPP_COMP_0];
  741. for (i = 0; i < SDE_MAX_PLANES; i++) {
  742. /*
  743. * For inline rotation cases with pre-downscaling enabled
  744. * set x pre-downscale value if required. Only x direction
  745. * is currently supported. Use src_h as values have been swapped
  746. * and x direction corresponds to height value.
  747. */
  748. src_h_pre_down = src_h;
  749. if (pre_down_supported && inline_rotation) {
  750. if (i == 0 && (src_h > mult_frac(dst_h, 11, 5)))
  751. src_h_pre_down = src_h / 2;
  752. }
  753. scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,
  754. psde->pipe_cfg.horz_decimation);
  755. scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h_pre_down,
  756. psde->pipe_cfg.vert_decimation);
  757. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) {
  758. scale_cfg->src_width[i] /= chroma_subsmpl_h;
  759. scale_cfg->src_height[i] /= chroma_subsmpl_v;
  760. }
  761. scale_cfg->preload_x[i] = psde->pipe_sblk->scaler_blk.h_preload;
  762. scale_cfg->preload_y[i] = psde->pipe_sblk->scaler_blk.v_preload;
  763. /* For pixel extension we need the pre-rotated orientation */
  764. if (inline_rotation) {
  765. pstate->pixel_ext.num_ext_pxls_top[i] =
  766. scale_cfg->src_width[i];
  767. pstate->pixel_ext.num_ext_pxls_left[i] =
  768. scale_cfg->src_height[i];
  769. } else {
  770. pstate->pixel_ext.num_ext_pxls_top[i] =
  771. scale_cfg->src_height[i];
  772. pstate->pixel_ext.num_ext_pxls_left[i] =
  773. scale_cfg->src_width[i];
  774. }
  775. }
  776. if ((!(SDE_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
  777. && (src_w == dst_w) && !inline_rotation) ||
  778. pstate->multirect_mode)
  779. return;
  780. SDE_DEBUG_PLANE(psde,
  781. "setting bilinear: src:%dx%d dst:%dx%d chroma:%dx%d fmt:%x\n",
  782. src_w, src_h, dst_w, dst_h,
  783. chroma_subsmpl_v, chroma_subsmpl_h,
  784. fmt->base.pixel_format);
  785. scale_cfg->dst_width = dst_w;
  786. scale_cfg->dst_height = dst_h;
  787. scale_cfg->y_rgb_filter_cfg = SDE_SCALE_BIL;
  788. scale_cfg->uv_filter_cfg = SDE_SCALE_BIL;
  789. scale_cfg->alpha_filter_cfg = SDE_SCALE_ALPHA_BIL;
  790. scale_cfg->lut_flag = 0;
  791. scale_cfg->blend_cfg = 1;
  792. scale_cfg->enable = 1;
  793. scale_cfg->dyn_exp_disabled = SDE_QSEED_DEFAULT_DYN_EXP;
  794. }
  795. /**
  796. * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
  797. * @psde: Pointer to SDE plane object
  798. * @src: Source size
  799. * @dst: Destination size
  800. * @phase_steps: Pointer to output array for phase steps
  801. * @filter: Pointer to output array for filter type
  802. * @fmt: Pointer to format definition
  803. * @chroma_subsampling: Subsampling amount for chroma channel
  804. *
  805. * Returns: 0 on success
  806. */
  807. static int _sde_plane_setup_scaler2(struct sde_plane *psde,
  808. uint32_t src, uint32_t dst, uint32_t *phase_steps,
  809. enum sde_hw_filter *filter, const struct sde_format *fmt,
  810. uint32_t chroma_subsampling)
  811. {
  812. if (!psde || !phase_steps || !filter || !fmt) {
  813. SDE_ERROR(
  814. "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
  815. !psde, !phase_steps, !filter, !fmt);
  816. return -EINVAL;
  817. }
  818. /* calculate phase steps, leave init phase as zero */
  819. phase_steps[SDE_SSPP_COMP_0] =
  820. mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
  821. phase_steps[SDE_SSPP_COMP_1_2] =
  822. phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
  823. phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
  824. phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
  825. /* calculate scaler config, if necessary */
  826. if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
  827. filter[SDE_SSPP_COMP_3] =
  828. (src <= dst) ? SDE_SCALE_FILTER_BIL :
  829. SDE_SCALE_FILTER_PCMN;
  830. if (SDE_FORMAT_IS_YUV(fmt)) {
  831. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
  832. filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
  833. } else {
  834. filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
  835. filter[SDE_SSPP_COMP_1_2] =
  836. SDE_SCALE_FILTER_NEAREST;
  837. }
  838. } else {
  839. /* disable scaler */
  840. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
  841. filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
  842. filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
  843. }
  844. return 0;
  845. }
  846. /**
  847. * _sde_plane_setup_pixel_ext - determine default pixel extension values
  848. * @psde: Pointer to SDE plane object
  849. * @src: Source size
  850. * @dst: Destination size
  851. * @decimated_src: Source size after decimation, if any
  852. * @phase_steps: Pointer to output array for phase steps
  853. * @out_src: Output array for pixel extension values
  854. * @out_edge1: Output array for pixel extension first edge
  855. * @out_edge2: Output array for pixel extension second edge
  856. * @filter: Pointer to array for filter type
  857. * @fmt: Pointer to format definition
  858. * @chroma_subsampling: Subsampling amount for chroma channel
  859. * @post_compare: Whether to chroma subsampled source size for comparisions
  860. */
  861. static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
  862. uint32_t src, uint32_t dst, uint32_t decimated_src,
  863. uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
  864. int *out_edge2, enum sde_hw_filter *filter,
  865. const struct sde_format *fmt, uint32_t chroma_subsampling,
  866. bool post_compare)
  867. {
  868. int64_t edge1, edge2, caf;
  869. uint32_t src_work;
  870. int i, tmp;
  871. if (psde && phase_steps && out_src && out_edge1 &&
  872. out_edge2 && filter && fmt) {
  873. /* handle CAF for YUV formats */
  874. if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
  875. caf = PHASE_STEP_UNIT_SCALE;
  876. else
  877. caf = 0;
  878. for (i = 0; i < SDE_MAX_PLANES; i++) {
  879. src_work = decimated_src;
  880. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
  881. src_work /= chroma_subsampling;
  882. if (post_compare)
  883. src = src_work;
  884. if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
  885. /* unity */
  886. edge1 = 0;
  887. edge2 = 0;
  888. } else if (dst >= src) {
  889. /* upscale */
  890. edge1 = (1 << PHASE_RESIDUAL);
  891. edge1 -= caf;
  892. edge2 = (1 << PHASE_RESIDUAL);
  893. edge2 += (dst - 1) * *(phase_steps + i);
  894. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  895. edge2 += caf;
  896. edge2 = -(edge2);
  897. } else {
  898. /* downscale */
  899. edge1 = 0;
  900. edge2 = (dst - 1) * *(phase_steps + i);
  901. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  902. edge2 += *(phase_steps + i);
  903. edge2 = -(edge2);
  904. }
  905. /* only enable CAF for luma plane */
  906. caf = 0;
  907. /* populate output arrays */
  908. *(out_src + i) = src_work;
  909. /* edge updates taken from __pxl_extn_helper */
  910. if (edge1 >= 0) {
  911. tmp = (uint32_t)edge1;
  912. tmp >>= PHASE_STEP_SHIFT;
  913. *(out_edge1 + i) = -tmp;
  914. } else {
  915. tmp = (uint32_t)(-edge1);
  916. *(out_edge1 + i) =
  917. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  918. PHASE_STEP_SHIFT;
  919. }
  920. if (edge2 >= 0) {
  921. tmp = (uint32_t)edge2;
  922. tmp >>= PHASE_STEP_SHIFT;
  923. *(out_edge2 + i) = -tmp;
  924. } else {
  925. tmp = (uint32_t)(-edge2);
  926. *(out_edge2 + i) =
  927. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  928. PHASE_STEP_SHIFT;
  929. }
  930. }
  931. }
  932. }
  933. static inline void _sde_plane_setup_csc(struct sde_plane *psde)
  934. {
  935. static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
  936. {
  937. /* S15.16 format */
  938. 0x00012A00, 0x00000000, 0x00019880,
  939. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  940. 0x00012A00, 0x00020480, 0x00000000,
  941. },
  942. /* signed bias */
  943. { 0xfff0, 0xff80, 0xff80,},
  944. { 0x0, 0x0, 0x0,},
  945. /* unsigned clamp */
  946. { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
  947. { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
  948. };
  949. static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = {
  950. {
  951. /* S15.16 format */
  952. 0x00012A00, 0x00000000, 0x00019880,
  953. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  954. 0x00012A00, 0x00020480, 0x00000000,
  955. },
  956. /* signed bias */
  957. { 0xffc0, 0xfe00, 0xfe00,},
  958. { 0x0, 0x0, 0x0,},
  959. /* unsigned clamp */
  960. { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
  961. { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
  962. };
  963. if (!psde) {
  964. SDE_ERROR("invalid plane\n");
  965. return;
  966. }
  967. /* revert to kernel default if override not available */
  968. if (psde->csc_usr_ptr)
  969. psde->csc_ptr = psde->csc_usr_ptr;
  970. else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features)
  971. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L;
  972. else
  973. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
  974. SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
  975. psde->csc_ptr->csc_mv[0],
  976. psde->csc_ptr->csc_mv[1],
  977. psde->csc_ptr->csc_mv[2]);
  978. }
  979. static void sde_color_process_plane_setup(struct drm_plane *plane)
  980. {
  981. struct sde_plane *psde;
  982. struct sde_plane_state *pstate;
  983. uint32_t hue, saturation, value, contrast;
  984. struct drm_msm_memcol *memcol = NULL;
  985. struct drm_msm_3d_gamut *vig_gamut = NULL;
  986. struct drm_msm_igc_lut *igc = NULL;
  987. struct drm_msm_pgc_lut *gc = NULL;
  988. size_t memcol_sz = 0, size = 0;
  989. struct sde_hw_cp_cfg hw_cfg = {};
  990. struct sde_hw_ctl *ctl = _sde_plane_get_hw_ctl(plane);
  991. bool fp16_igc, fp16_unmult;
  992. struct drm_msm_fp16_gc *fp16_gc = NULL;
  993. struct drm_msm_fp16_csc *fp16_csc = NULL;
  994. psde = to_sde_plane(plane);
  995. pstate = to_sde_plane_state(plane->state);
  996. hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
  997. if (psde->pipe_hw->ops.setup_pa_hue)
  998. psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue);
  999. saturation = (uint32_t) sde_plane_get_property(pstate,
  1000. PLANE_PROP_SATURATION_ADJUST);
  1001. if (psde->pipe_hw->ops.setup_pa_sat)
  1002. psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation);
  1003. value = (uint32_t) sde_plane_get_property(pstate,
  1004. PLANE_PROP_VALUE_ADJUST);
  1005. if (psde->pipe_hw->ops.setup_pa_val)
  1006. psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value);
  1007. contrast = (uint32_t) sde_plane_get_property(pstate,
  1008. PLANE_PROP_CONTRAST_ADJUST);
  1009. if (psde->pipe_hw->ops.setup_pa_cont)
  1010. psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast);
  1011. if (psde->pipe_hw->ops.setup_pa_memcolor) {
  1012. /* Skin memory color setup */
  1013. memcol = msm_property_get_blob(&psde->property_info,
  1014. &pstate->property_state,
  1015. &memcol_sz,
  1016. PLANE_PROP_SKIN_COLOR);
  1017. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1018. MEMCOLOR_SKIN, memcol);
  1019. /* Sky memory color setup */
  1020. memcol = msm_property_get_blob(&psde->property_info,
  1021. &pstate->property_state,
  1022. &memcol_sz,
  1023. PLANE_PROP_SKY_COLOR);
  1024. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1025. MEMCOLOR_SKY, memcol);
  1026. /* Foliage memory color setup */
  1027. memcol = msm_property_get_blob(&psde->property_info,
  1028. &pstate->property_state,
  1029. &memcol_sz,
  1030. PLANE_PROP_FOLIAGE_COLOR);
  1031. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1032. MEMCOLOR_FOLIAGE, memcol);
  1033. }
  1034. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_GAMUT &&
  1035. psde->pipe_hw->ops.setup_vig_gamut) {
  1036. vig_gamut = msm_property_get_blob(&psde->property_info,
  1037. &pstate->property_state,
  1038. &size,
  1039. PLANE_PROP_VIG_GAMUT);
  1040. hw_cfg.last_feature = 0;
  1041. hw_cfg.ctl = ctl;
  1042. hw_cfg.len = sizeof(struct drm_msm_3d_gamut);
  1043. hw_cfg.payload = vig_gamut;
  1044. psde->pipe_hw->ops.setup_vig_gamut(psde->pipe_hw, &hw_cfg);
  1045. }
  1046. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_IGC &&
  1047. psde->pipe_hw->ops.setup_vig_igc) {
  1048. igc = msm_property_get_blob(&psde->property_info,
  1049. &pstate->property_state,
  1050. &size,
  1051. PLANE_PROP_VIG_IGC);
  1052. hw_cfg.last_feature = 0;
  1053. hw_cfg.ctl = ctl;
  1054. hw_cfg.len = sizeof(struct drm_msm_igc_lut);
  1055. hw_cfg.payload = igc;
  1056. psde->pipe_hw->ops.setup_vig_igc(psde->pipe_hw, &hw_cfg);
  1057. }
  1058. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_IGC &&
  1059. psde->pipe_hw->ops.setup_dma_igc) {
  1060. igc = msm_property_get_blob(&psde->property_info,
  1061. &pstate->property_state,
  1062. &size,
  1063. PLANE_PROP_DMA_IGC);
  1064. hw_cfg.last_feature = 0;
  1065. hw_cfg.ctl = ctl;
  1066. hw_cfg.len = sizeof(struct drm_msm_igc_lut);
  1067. hw_cfg.payload = igc;
  1068. psde->pipe_hw->ops.setup_dma_igc(psde->pipe_hw, &hw_cfg,
  1069. pstate->multirect_index);
  1070. }
  1071. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_GC &&
  1072. psde->pipe_hw->ops.setup_dma_gc) {
  1073. gc = msm_property_get_blob(&psde->property_info,
  1074. &pstate->property_state,
  1075. &size,
  1076. PLANE_PROP_DMA_GC);
  1077. hw_cfg.last_feature = 0;
  1078. hw_cfg.ctl = ctl;
  1079. hw_cfg.len = sizeof(struct drm_msm_pgc_lut);
  1080. hw_cfg.payload = gc;
  1081. psde->pipe_hw->ops.setup_dma_gc(psde->pipe_hw, &hw_cfg,
  1082. pstate->multirect_index);
  1083. }
  1084. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_IGC &&
  1085. psde->pipe_hw->ops.setup_fp16_igc) {
  1086. fp16_igc = !!sde_plane_get_property(pstate,
  1087. PLANE_PROP_FP16_IGC);
  1088. hw_cfg.last_feature = 0;
  1089. hw_cfg.ctl = ctl;
  1090. hw_cfg.len = sizeof(bool);
  1091. hw_cfg.payload = &fp16_igc;
  1092. psde->pipe_hw->ops.setup_fp16_igc(psde->pipe_hw,
  1093. pstate->multirect_index, &hw_cfg);
  1094. }
  1095. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_GC &&
  1096. psde->pipe_hw->ops.setup_fp16_gc) {
  1097. fp16_gc = msm_property_get_blob(&psde->property_info,
  1098. &pstate->property_state,
  1099. &size,
  1100. PLANE_PROP_FP16_GC);
  1101. hw_cfg.last_feature = 0;
  1102. hw_cfg.ctl = ctl;
  1103. hw_cfg.len = size;
  1104. hw_cfg.payload = fp16_gc;
  1105. psde->pipe_hw->ops.setup_fp16_gc(psde->pipe_hw,
  1106. pstate->multirect_index, &hw_cfg);
  1107. }
  1108. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_CSC &&
  1109. psde->pipe_hw->ops.setup_fp16_csc) {
  1110. fp16_csc = msm_property_get_blob(&psde->property_info,
  1111. &pstate->property_state,
  1112. &size,
  1113. PLANE_PROP_FP16_CSC);
  1114. hw_cfg.last_feature = 0;
  1115. hw_cfg.ctl = ctl;
  1116. hw_cfg.len = size;
  1117. hw_cfg.payload = fp16_csc;
  1118. psde->pipe_hw->ops.setup_fp16_csc(psde->pipe_hw,
  1119. pstate->multirect_index, &hw_cfg);
  1120. }
  1121. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_UNMULT &&
  1122. psde->pipe_hw->ops.setup_fp16_unmult) {
  1123. fp16_unmult = !!sde_plane_get_property(pstate,
  1124. PLANE_PROP_FP16_UNMULT);
  1125. hw_cfg.last_feature = 0;
  1126. hw_cfg.ctl = ctl;
  1127. hw_cfg.len = sizeof(bool);
  1128. hw_cfg.payload = &fp16_unmult;
  1129. psde->pipe_hw->ops.setup_fp16_unmult(psde->pipe_hw,
  1130. pstate->multirect_index, &hw_cfg);
  1131. }
  1132. }
  1133. static void _sde_plane_setup_scaler(struct sde_plane *psde,
  1134. struct sde_plane_state *pstate,
  1135. const struct sde_format *fmt, bool color_fill)
  1136. {
  1137. struct sde_hw_pixel_ext *pe;
  1138. uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
  1139. const struct drm_format_info *info = NULL;
  1140. if (!psde || !fmt || !pstate) {
  1141. SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
  1142. !psde, !fmt, !pstate);
  1143. return;
  1144. }
  1145. info = drm_format_info(fmt->base.pixel_format);
  1146. pe = &pstate->pixel_ext;
  1147. psde->pipe_cfg.horz_decimation =
  1148. sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  1149. psde->pipe_cfg.vert_decimation =
  1150. sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  1151. /* don't chroma subsample if decimating */
  1152. chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : info->hsub;
  1153. chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : info->vsub;
  1154. /* update scaler */
  1155. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  1156. (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE))) {
  1157. int rc = -EINVAL;
  1158. if (!color_fill && !psde->debugfs_default_scale)
  1159. rc = is_qseed3_rev_qseed3lite(psde->pipe_hw->catalog) ?
  1160. _sde_plane_setup_scaler3lite_lut(psde, pstate) :
  1161. _sde_plane_setup_scaler3_lut(psde, pstate);
  1162. if (rc || pstate->scaler_check_state !=
  1163. SDE_PLANE_SCLCHECK_SCALER_V2) {
  1164. SDE_EVT32_VERBOSE(DRMID(&psde->base), color_fill,
  1165. pstate->scaler_check_state,
  1166. psde->debugfs_default_scale, rc,
  1167. psde->pipe_cfg.src_rect.w,
  1168. psde->pipe_cfg.src_rect.h,
  1169. psde->pipe_cfg.dst_rect.w,
  1170. psde->pipe_cfg.dst_rect.h,
  1171. pstate->multirect_mode);
  1172. /* calculate default config for QSEED3 */
  1173. _sde_plane_setup_scaler3(psde, pstate, fmt,
  1174. chroma_subsmpl_h, chroma_subsmpl_v);
  1175. }
  1176. } else if (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V1 ||
  1177. color_fill || psde->debugfs_default_scale) {
  1178. uint32_t deci_dim, i;
  1179. /* calculate default configuration for QSEED2 */
  1180. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  1181. SDE_DEBUG_PLANE(psde, "default config\n");
  1182. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
  1183. psde->pipe_cfg.horz_decimation);
  1184. _sde_plane_setup_scaler2(psde,
  1185. deci_dim,
  1186. psde->pipe_cfg.dst_rect.w,
  1187. pe->phase_step_x,
  1188. pe->horz_filter, fmt, chroma_subsmpl_h);
  1189. if (SDE_FORMAT_IS_YUV(fmt))
  1190. deci_dim &= ~0x1;
  1191. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
  1192. psde->pipe_cfg.dst_rect.w, deci_dim,
  1193. pe->phase_step_x,
  1194. pe->roi_w,
  1195. pe->num_ext_pxls_left,
  1196. pe->num_ext_pxls_right, pe->horz_filter, fmt,
  1197. chroma_subsmpl_h, 0);
  1198. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
  1199. psde->pipe_cfg.vert_decimation);
  1200. _sde_plane_setup_scaler2(psde,
  1201. deci_dim,
  1202. psde->pipe_cfg.dst_rect.h,
  1203. pe->phase_step_y,
  1204. pe->vert_filter, fmt, chroma_subsmpl_v);
  1205. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
  1206. psde->pipe_cfg.dst_rect.h, deci_dim,
  1207. pe->phase_step_y,
  1208. pe->roi_h,
  1209. pe->num_ext_pxls_top,
  1210. pe->num_ext_pxls_btm, pe->vert_filter, fmt,
  1211. chroma_subsmpl_v, 1);
  1212. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1213. if (pe->num_ext_pxls_left[i] >= 0)
  1214. pe->left_rpt[i] = pe->num_ext_pxls_left[i];
  1215. else
  1216. pe->left_ftch[i] = pe->num_ext_pxls_left[i];
  1217. if (pe->num_ext_pxls_right[i] >= 0)
  1218. pe->right_rpt[i] = pe->num_ext_pxls_right[i];
  1219. else
  1220. pe->right_ftch[i] = pe->num_ext_pxls_right[i];
  1221. if (pe->num_ext_pxls_top[i] >= 0)
  1222. pe->top_rpt[i] = pe->num_ext_pxls_top[i];
  1223. else
  1224. pe->top_ftch[i] = pe->num_ext_pxls_top[i];
  1225. if (pe->num_ext_pxls_btm[i] >= 0)
  1226. pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
  1227. else
  1228. pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
  1229. }
  1230. }
  1231. if (psde->pipe_hw->ops.setup_pre_downscale)
  1232. psde->pipe_hw->ops.setup_pre_downscale(psde->pipe_hw,
  1233. &pstate->pre_down);
  1234. }
  1235. /**
  1236. * _sde_plane_color_fill - enables color fill on plane
  1237. * @psde: Pointer to SDE plane object
  1238. * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
  1239. * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
  1240. * Returns: 0 on success
  1241. */
  1242. static int _sde_plane_color_fill(struct sde_plane *psde,
  1243. uint32_t color, uint32_t alpha)
  1244. {
  1245. const struct sde_format *fmt;
  1246. const struct drm_plane *plane;
  1247. struct sde_plane_state *pstate;
  1248. bool blend_enable = true;
  1249. if (!psde || !psde->base.state) {
  1250. SDE_ERROR("invalid plane\n");
  1251. return -EINVAL;
  1252. }
  1253. if (!psde->pipe_hw) {
  1254. SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
  1255. return -EINVAL;
  1256. }
  1257. plane = &psde->base;
  1258. pstate = to_sde_plane_state(plane->state);
  1259. SDE_DEBUG_PLANE(psde, "\n");
  1260. /*
  1261. * select fill format to match user property expectation,
  1262. * h/w only supports RGB variants
  1263. */
  1264. fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
  1265. blend_enable = (SDE_DRM_BLEND_OP_OPAQUE !=
  1266. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP));
  1267. /* update sspp */
  1268. if (fmt && psde->pipe_hw->ops.setup_solidfill) {
  1269. psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
  1270. (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
  1271. pstate->multirect_index);
  1272. /* override scaler/decimation if solid fill */
  1273. psde->pipe_cfg.src_rect.x = 0;
  1274. psde->pipe_cfg.src_rect.y = 0;
  1275. psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
  1276. psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
  1277. _sde_plane_setup_scaler(psde, pstate, fmt, true);
  1278. if (psde->pipe_hw->ops.setup_format)
  1279. psde->pipe_hw->ops.setup_format(psde->pipe_hw,
  1280. fmt, blend_enable,
  1281. SDE_SSPP_SOLID_FILL,
  1282. pstate->multirect_index);
  1283. if (psde->pipe_hw->ops.setup_rects)
  1284. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  1285. &psde->pipe_cfg,
  1286. pstate->multirect_index);
  1287. if (psde->pipe_hw->ops.setup_pe)
  1288. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  1289. &pstate->pixel_ext);
  1290. if (psde->pipe_hw->ops.setup_scaler &&
  1291. pstate->multirect_index != SDE_SSPP_RECT_1) {
  1292. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  1293. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  1294. &psde->pipe_cfg, &pstate->pixel_ext,
  1295. &pstate->scaler3_cfg);
  1296. }
  1297. }
  1298. return 0;
  1299. }
  1300. /**
  1301. * sde_plane_rot_atomic_check - verify rotator update of the given state
  1302. * @plane: Pointer to drm plane
  1303. * @state: Pointer to drm plane state to be validated
  1304. * return: 0 if success; error code otherwise
  1305. */
  1306. static int sde_plane_rot_atomic_check(struct drm_plane *plane,
  1307. struct drm_plane_state *state)
  1308. {
  1309. struct sde_plane *psde;
  1310. struct sde_plane_state *pstate, *old_pstate;
  1311. int ret = 0;
  1312. u32 rotation;
  1313. if (!plane || !state) {
  1314. SDE_ERROR("invalid plane/state\n");
  1315. return -EINVAL;
  1316. }
  1317. psde = to_sde_plane(plane);
  1318. pstate = to_sde_plane_state(state);
  1319. old_pstate = to_sde_plane_state(plane->state);
  1320. /* check inline rotation and simplify the transform */
  1321. rotation = drm_rotation_simplify(
  1322. state->rotation,
  1323. DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
  1324. DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1325. if ((rotation & DRM_MODE_ROTATE_180) ||
  1326. (rotation & DRM_MODE_ROTATE_270)) {
  1327. SDE_ERROR_PLANE(psde,
  1328. "invalid rotation transform must be simplified 0x%x\n",
  1329. rotation);
  1330. ret = -EINVAL;
  1331. goto exit;
  1332. }
  1333. if (rotation & DRM_MODE_ROTATE_90) {
  1334. struct msm_drm_private *priv = plane->dev->dev_private;
  1335. struct sde_kms *sde_kms;
  1336. const struct msm_format *msm_fmt;
  1337. const struct sde_format *fmt;
  1338. struct sde_rect src;
  1339. bool q16_data = true;
  1340. POPULATE_RECT(&src, state->src_x, state->src_y,
  1341. state->src_w, state->src_h, q16_data);
  1342. /*
  1343. * DRM framework expects rotation flag in counter-clockwise
  1344. * direction and the HW expects in clockwise direction.
  1345. * Flip the flags to match with HW.
  1346. */
  1347. rotation ^= (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1348. if (!psde->pipe_sblk->in_rot_maxdwnscale_rt_num ||
  1349. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom ||
  1350. !psde->pipe_sblk->in_rot_maxdwnscale_nrt ||
  1351. !psde->pipe_sblk->in_rot_maxheight ||
  1352. !psde->pipe_sblk->in_rot_format_list ||
  1353. !(psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))) {
  1354. SDE_ERROR_PLANE(psde,
  1355. "wrong config rt:%d/%d nrt:%d fmt:%d h:%d 0x%x\n",
  1356. !psde->pipe_sblk->in_rot_maxdwnscale_rt_num,
  1357. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom,
  1358. !psde->pipe_sblk->in_rot_maxdwnscale_nrt,
  1359. !psde->pipe_sblk->in_rot_format_list,
  1360. !psde->pipe_sblk->in_rot_maxheight,
  1361. psde->features);
  1362. ret = -EINVAL;
  1363. goto exit;
  1364. }
  1365. /* check for valid height */
  1366. if (src.h > psde->pipe_sblk->in_rot_maxheight) {
  1367. SDE_ERROR_PLANE(psde,
  1368. "invalid height for inline rot:%d max:%d\n",
  1369. src.h, psde->pipe_sblk->in_rot_maxheight);
  1370. ret = -EINVAL;
  1371. goto exit;
  1372. }
  1373. if (!sde_plane_enabled(state))
  1374. goto exit;
  1375. /* check for valid formats supported by inline rot */
  1376. sde_kms = to_sde_kms(priv->kms);
  1377. msm_fmt = msm_framebuffer_format(state->fb);
  1378. fmt = to_sde_format(msm_fmt);
  1379. ret = sde_format_validate_fmt(&sde_kms->base, fmt,
  1380. psde->pipe_sblk->in_rot_format_list);
  1381. }
  1382. exit:
  1383. pstate->rotation = rotation;
  1384. return ret;
  1385. }
  1386. static bool _sde_plane_halt_requests(struct drm_plane *plane,
  1387. uint32_t xin_id, bool halt_forced_clk, bool enable)
  1388. {
  1389. struct sde_plane *psde;
  1390. struct msm_drm_private *priv;
  1391. struct sde_vbif_set_xin_halt_params halt_params;
  1392. if (!plane || !plane->dev) {
  1393. SDE_ERROR("invalid arguments\n");
  1394. return false;
  1395. }
  1396. psde = to_sde_plane(plane);
  1397. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1398. SDE_ERROR("invalid pipe reference\n");
  1399. return false;
  1400. }
  1401. priv = plane->dev->dev_private;
  1402. if (!priv || !priv->kms) {
  1403. SDE_ERROR("invalid KMS reference\n");
  1404. return false;
  1405. }
  1406. memset(&halt_params, 0, sizeof(halt_params));
  1407. halt_params.vbif_idx = VBIF_RT;
  1408. halt_params.xin_id = xin_id;
  1409. halt_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  1410. halt_params.forced_on = halt_forced_clk;
  1411. halt_params.enable = enable;
  1412. return sde_vbif_set_xin_halt(to_sde_kms(priv->kms), &halt_params);
  1413. }
  1414. void sde_plane_halt_requests(struct drm_plane *plane, bool enable)
  1415. {
  1416. struct sde_plane *psde;
  1417. if (!plane) {
  1418. SDE_ERROR("invalid plane\n");
  1419. return;
  1420. }
  1421. psde = to_sde_plane(plane);
  1422. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1423. SDE_ERROR("invalid pipe reference\n");
  1424. return;
  1425. }
  1426. SDE_EVT32(DRMID(plane), psde->xin_halt_forced_clk, enable);
  1427. psde->xin_halt_forced_clk =
  1428. _sde_plane_halt_requests(plane, psde->pipe_hw->cap->xin_id,
  1429. psde->xin_halt_forced_clk, enable);
  1430. }
  1431. void sde_plane_secure_ctrl_xin_client(struct drm_plane *plane,
  1432. struct drm_crtc *crtc)
  1433. {
  1434. struct sde_plane *psde;
  1435. if (!plane || !crtc) {
  1436. SDE_ERROR("invalid plane/crtc\n");
  1437. return;
  1438. }
  1439. psde = to_sde_plane(plane);
  1440. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  1441. return;
  1442. /* do all VBIF programming for the sec-ui allowed SSPP */
  1443. _sde_plane_set_qos_remap(plane);
  1444. _sde_plane_set_ot_limit(plane, crtc);
  1445. }
  1446. /**
  1447. * sde_plane_rot_install_properties - install plane rotator properties
  1448. * @plane: Pointer to drm plane
  1449. * @catalog: Pointer to mdss configuration
  1450. * return: none
  1451. */
  1452. static void sde_plane_rot_install_properties(struct drm_plane *plane,
  1453. struct sde_mdss_cfg *catalog)
  1454. {
  1455. struct sde_plane *psde = to_sde_plane(plane);
  1456. unsigned int supported_rotations = DRM_MODE_ROTATE_0 |
  1457. DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
  1458. int ret = 0;
  1459. if (!plane || !psde) {
  1460. SDE_ERROR("invalid plane\n");
  1461. return;
  1462. } else if (!catalog) {
  1463. SDE_ERROR("invalid catalog\n");
  1464. return;
  1465. }
  1466. if (!psde->is_virtual && psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))
  1467. supported_rotations |= DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270;
  1468. ret = drm_plane_create_rotation_property(plane,
  1469. DRM_MODE_ROTATE_0, supported_rotations);
  1470. if (ret) {
  1471. DRM_ERROR("create rotation property failed: %d\n", ret);
  1472. return;
  1473. }
  1474. }
  1475. void sde_plane_clear_multirect(const struct drm_plane_state *drm_state)
  1476. {
  1477. struct sde_plane_state *pstate;
  1478. if (!drm_state)
  1479. return;
  1480. pstate = to_sde_plane_state(drm_state);
  1481. pstate->multirect_index = SDE_SSPP_RECT_SOLO;
  1482. pstate->multirect_mode = SDE_SSPP_MULTIRECT_NONE;
  1483. }
  1484. /**
  1485. * multi_rect validate API allows to validate only R0 and R1 RECT
  1486. * passing for each plane. Client of this API must not pass multiple
  1487. * plane which are not sharing same XIN client. Such calls will fail
  1488. * even though kernel client is passing valid multirect configuration.
  1489. */
  1490. int sde_plane_validate_multirect_v2(struct sde_multirect_plane_states *plane)
  1491. {
  1492. struct sde_plane_state *pstate[R_MAX];
  1493. const struct drm_plane_state *drm_state[R_MAX];
  1494. struct sde_rect src[R_MAX], dst[R_MAX];
  1495. struct sde_plane *sde_plane[R_MAX];
  1496. const struct sde_format *fmt[R_MAX];
  1497. int xin_id[R_MAX];
  1498. bool q16_data = true;
  1499. int i, j, buffer_lines, width_threshold[R_MAX];
  1500. unsigned int max_tile_height = 1;
  1501. bool parallel_fetch_qualified = true;
  1502. enum sde_sspp_multirect_mode mode = SDE_SSPP_MULTIRECT_NONE;
  1503. const struct msm_format *msm_fmt;
  1504. bool const_alpha_enable = true;
  1505. for (i = 0; i < R_MAX; i++) {
  1506. drm_state[i] = i ? plane->r1 : plane->r0;
  1507. if (!drm_state[i]) {
  1508. SDE_ERROR("drm plane state is NULL\n");
  1509. return -EINVAL;
  1510. }
  1511. pstate[i] = to_sde_plane_state(drm_state[i]);
  1512. sde_plane[i] = to_sde_plane(drm_state[i]->plane);
  1513. xin_id[i] = sde_plane[i]->pipe_hw->cap->xin_id;
  1514. for (j = 0; j < i; j++) {
  1515. if (xin_id[i] != xin_id[j]) {
  1516. SDE_ERROR_PLANE(sde_plane[i],
  1517. "invalid multirect validate call base:%d xin_id:%d curr:%d xin:%d\n",
  1518. j, xin_id[j], i, xin_id[i]);
  1519. return -EINVAL;
  1520. }
  1521. }
  1522. msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
  1523. if (!msm_fmt) {
  1524. SDE_ERROR_PLANE(sde_plane[i], "null fb\n");
  1525. return -EINVAL;
  1526. }
  1527. fmt[i] = to_sde_format(msm_fmt);
  1528. if (SDE_FORMAT_IS_UBWC(fmt[i]) &&
  1529. (fmt[i]->tile_height > max_tile_height))
  1530. max_tile_height = fmt[i]->tile_height;
  1531. POPULATE_RECT(&src[i], drm_state[i]->src_x, drm_state[i]->src_y,
  1532. drm_state[i]->src_w, drm_state[i]->src_h, q16_data);
  1533. POPULATE_RECT(&dst[i], drm_state[i]->crtc_x,
  1534. drm_state[i]->crtc_y, drm_state[i]->crtc_w,
  1535. drm_state[i]->crtc_h, !q16_data);
  1536. if (src[i].w != dst[i].w || src[i].h != dst[i].h) {
  1537. SDE_ERROR_PLANE(sde_plane[i],
  1538. "scaling is not supported in multirect mode\n");
  1539. return -EINVAL;
  1540. }
  1541. if (pstate[i]->rotation & DRM_MODE_ROTATE_90) {
  1542. SDE_ERROR_PLANE(sde_plane[i],
  1543. "inline rotation is not supported in mulirect mode\n");
  1544. return -EINVAL;
  1545. }
  1546. if (SDE_FORMAT_IS_YUV(fmt[i])) {
  1547. SDE_ERROR_PLANE(sde_plane[i],
  1548. "Unsupported format for multirect mode\n");
  1549. return -EINVAL;
  1550. }
  1551. /**
  1552. * SSPP PD_MEM is split half - one for each RECT.
  1553. * Tiled formats need 5 lines of buffering while fetching
  1554. * whereas linear formats need only 2 lines.
  1555. * So we cannot support more than half of the supported SSPP
  1556. * width for tiled formats.
  1557. */
  1558. width_threshold[i] = sde_plane[i]->pipe_sblk->maxlinewidth;
  1559. if (SDE_FORMAT_IS_UBWC(fmt[i]))
  1560. width_threshold[i] /= 2;
  1561. if (parallel_fetch_qualified && src[i].w > width_threshold[i])
  1562. parallel_fetch_qualified = false;
  1563. if (sde_plane[i]->is_virtual)
  1564. mode = sde_plane_get_property(pstate[i],
  1565. PLANE_PROP_MULTIRECT_MODE);
  1566. if (pstate[i]->const_alpha_en != const_alpha_enable)
  1567. const_alpha_enable = false;
  1568. }
  1569. buffer_lines = 2 * max_tile_height;
  1570. /**
  1571. * fallback to driver mode selection logic if client is using
  1572. * multirect plane without setting property.
  1573. *
  1574. * validate multirect mode configuration based on rectangle
  1575. */
  1576. switch (mode) {
  1577. case SDE_SSPP_MULTIRECT_NONE:
  1578. if (parallel_fetch_qualified)
  1579. mode = SDE_SSPP_MULTIRECT_PARALLEL;
  1580. else if (TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) ||
  1581. TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines))
  1582. mode = SDE_SSPP_MULTIRECT_TIME_MX;
  1583. else
  1584. SDE_ERROR(
  1585. "planes(%d - %d) multirect mode selection fail\n",
  1586. drm_state[R0]->plane->base.id,
  1587. drm_state[R1]->plane->base.id);
  1588. break;
  1589. case SDE_SSPP_MULTIRECT_PARALLEL:
  1590. if (!parallel_fetch_qualified) {
  1591. SDE_ERROR("R0 plane:%d width_threshold:%d src_w:%d\n",
  1592. drm_state[R0]->plane->base.id,
  1593. width_threshold[R0], src[R0].w);
  1594. SDE_ERROR("R1 plane:%d width_threshold:%d src_w:%d\n",
  1595. drm_state[R1]->plane->base.id,
  1596. width_threshold[R1], src[R1].w);
  1597. SDE_ERROR("parallel fetch not qualified\n");
  1598. mode = SDE_SSPP_MULTIRECT_NONE;
  1599. }
  1600. break;
  1601. case SDE_SSPP_MULTIRECT_TIME_MX:
  1602. if (!TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) &&
  1603. !TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines)) {
  1604. SDE_ERROR(
  1605. "buffer_lines:%d R0 plane:%d dst_y:%d dst_h:%d\n",
  1606. buffer_lines, drm_state[R0]->plane->base.id,
  1607. dst[R0].y, dst[R0].h);
  1608. SDE_ERROR(
  1609. "buffer_lines:%d R1 plane:%d dst_y:%d dst_h:%d\n",
  1610. buffer_lines, drm_state[R1]->plane->base.id,
  1611. dst[R1].y, dst[R1].h);
  1612. SDE_ERROR("time multiplexed fetch not qualified\n");
  1613. mode = SDE_SSPP_MULTIRECT_NONE;
  1614. }
  1615. break;
  1616. default:
  1617. SDE_ERROR("bad mode:%d selection\n", mode);
  1618. mode = SDE_SSPP_MULTIRECT_NONE;
  1619. break;
  1620. }
  1621. for (i = 0; i < R_MAX; i++) {
  1622. pstate[i]->multirect_mode = mode;
  1623. pstate[i]->const_alpha_en = const_alpha_enable;
  1624. }
  1625. if (mode == SDE_SSPP_MULTIRECT_NONE)
  1626. return -EINVAL;
  1627. if (sde_plane[R0]->is_virtual) {
  1628. pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
  1629. pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
  1630. } else {
  1631. pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
  1632. pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
  1633. }
  1634. SDE_DEBUG_PLANE(sde_plane[R0], "R0: %d - %d\n",
  1635. pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
  1636. SDE_DEBUG_PLANE(sde_plane[R1], "R1: %d - %d\n",
  1637. pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
  1638. return 0;
  1639. }
  1640. /**
  1641. * sde_plane_ctl_flush - set/clear control flush bitmask for the given plane
  1642. * @plane: Pointer to drm plane structure
  1643. * @ctl: Pointer to hardware control driver
  1644. * @set: set if true else clear
  1645. */
  1646. void sde_plane_ctl_flush(struct drm_plane *plane, struct sde_hw_ctl *ctl,
  1647. bool set)
  1648. {
  1649. if (!plane || !ctl) {
  1650. SDE_ERROR("invalid parameters\n");
  1651. return;
  1652. }
  1653. if (!ctl->ops.update_bitmask_sspp) {
  1654. SDE_ERROR("invalid ops\n");
  1655. return;
  1656. }
  1657. ctl->ops.update_bitmask_sspp(ctl, sde_plane_pipe(plane), set);
  1658. }
  1659. static int sde_plane_prepare_fb(struct drm_plane *plane,
  1660. struct drm_plane_state *new_state)
  1661. {
  1662. struct drm_framebuffer *fb = new_state->fb;
  1663. struct sde_plane *psde = to_sde_plane(plane);
  1664. struct sde_plane_state *pstate = to_sde_plane_state(new_state);
  1665. struct sde_hw_fmt_layout layout;
  1666. struct msm_gem_address_space *aspace;
  1667. int ret;
  1668. if (!fb)
  1669. return 0;
  1670. SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
  1671. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  1672. if (ret) {
  1673. SDE_ERROR_PLANE(psde, "Failed to get aspace\n");
  1674. return ret;
  1675. }
  1676. /* cache aspace */
  1677. pstate->aspace = aspace;
  1678. /*
  1679. * when transitioning from secure to non-secure,
  1680. * plane->prepare_fb happens before the commit. In such case,
  1681. * defer the prepare_fb and handled it late, during the commit
  1682. * after attaching the domains as part of the transition
  1683. */
  1684. pstate->defer_prepare_fb = (aspace && !aspace->domain_attached) ?
  1685. true : false;
  1686. if (pstate->defer_prepare_fb) {
  1687. SDE_EVT32(DRMID(plane), psde->pipe);
  1688. SDE_DEBUG_PLANE(psde,
  1689. "domain not attached, prepare_fb handled later\n");
  1690. return 0;
  1691. }
  1692. if (pstate->aspace && fb) {
  1693. ret = msm_framebuffer_prepare(fb,
  1694. pstate->aspace);
  1695. if (ret) {
  1696. SDE_ERROR("failed to prepare framebuffer\n");
  1697. return ret;
  1698. }
  1699. }
  1700. /* validate framebuffer layout before commit */
  1701. ret = sde_format_populate_layout(pstate->aspace,
  1702. fb, &layout);
  1703. if (ret) {
  1704. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  1705. return ret;
  1706. }
  1707. return 0;
  1708. }
  1709. static void sde_plane_cleanup_fb(struct drm_plane *plane,
  1710. struct drm_plane_state *old_state)
  1711. {
  1712. struct sde_plane *psde = to_sde_plane(plane);
  1713. struct sde_plane_state *old_pstate;
  1714. if (!old_state || !old_state->fb || !plane)
  1715. return;
  1716. old_pstate = to_sde_plane_state(old_state);
  1717. SDE_DEBUG_PLANE(psde, "FB[%u]\n", old_state->fb->base.id);
  1718. msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
  1719. }
  1720. static void _sde_plane_sspp_atomic_check_mode_changed(struct sde_plane *psde,
  1721. struct drm_plane_state *state,
  1722. struct drm_plane_state *old_state)
  1723. {
  1724. struct sde_plane_state *pstate = to_sde_plane_state(state);
  1725. struct sde_plane_state *old_pstate = to_sde_plane_state(old_state);
  1726. struct drm_framebuffer *fb, *old_fb;
  1727. /* no need to check it again */
  1728. if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
  1729. return;
  1730. if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
  1731. || psde->is_error) {
  1732. SDE_DEBUG_PLANE(psde,
  1733. "enabling/disabling full modeset required\n");
  1734. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1735. } else if (to_sde_plane_state(old_state)->pending) {
  1736. SDE_DEBUG_PLANE(psde, "still pending\n");
  1737. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1738. } else if (pstate->multirect_index != old_pstate->multirect_index ||
  1739. pstate->multirect_mode != old_pstate->multirect_mode) {
  1740. SDE_DEBUG_PLANE(psde, "multirect config updated\n");
  1741. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1742. } else if (state->src_w != old_state->src_w ||
  1743. state->src_h != old_state->src_h ||
  1744. state->src_x != old_state->src_x ||
  1745. state->src_y != old_state->src_y) {
  1746. SDE_DEBUG_PLANE(psde, "src rect updated\n");
  1747. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1748. } else if (state->crtc_w != old_state->crtc_w ||
  1749. state->crtc_h != old_state->crtc_h ||
  1750. state->crtc_x != old_state->crtc_x ||
  1751. state->crtc_y != old_state->crtc_y) {
  1752. SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
  1753. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1754. } else if (pstate->excl_rect.w != old_pstate->excl_rect.w ||
  1755. pstate->excl_rect.h != old_pstate->excl_rect.h ||
  1756. pstate->excl_rect.x != old_pstate->excl_rect.x ||
  1757. pstate->excl_rect.y != old_pstate->excl_rect.y) {
  1758. SDE_DEBUG_PLANE(psde, "excl_rect updated\n");
  1759. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1760. } else if (pstate->rotation != old_pstate->rotation) {
  1761. SDE_DEBUG_PLANE(psde, "rotation updated 0x%x->0x%x\n",
  1762. pstate->rotation, old_pstate->rotation);
  1763. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
  1764. }
  1765. fb = state->fb;
  1766. old_fb = old_state->fb;
  1767. if (!fb || !old_fb) {
  1768. SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
  1769. } else if ((fb->format->format != old_fb->format->format) ||
  1770. pstate->const_alpha_en != old_pstate->const_alpha_en) {
  1771. SDE_DEBUG_PLANE(psde, "format change\n");
  1772. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
  1773. } else {
  1774. uint64_t new_mod = fb->modifier;
  1775. uint64_t old_mod = old_fb->modifier;
  1776. uint32_t *new_pitches = fb->pitches;
  1777. uint32_t *old_pitches = old_fb->pitches;
  1778. uint32_t *new_offset = fb->offsets;
  1779. uint32_t *old_offset = old_fb->offsets;
  1780. int i;
  1781. if (new_mod != old_mod) {
  1782. SDE_DEBUG_PLANE(psde,
  1783. "format modifiers change new_mode:%llu old_mode:%llu\n",
  1784. new_mod, old_mod);
  1785. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1786. SDE_PLANE_DIRTY_RECTS;
  1787. }
  1788. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) {
  1789. if (new_pitches[i] != old_pitches[i]) {
  1790. SDE_DEBUG_PLANE(psde,
  1791. "pitches change plane:%d old_pitches:%u new_pitches:%u\n",
  1792. i, old_pitches[i], new_pitches[i]);
  1793. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1794. break;
  1795. }
  1796. }
  1797. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) {
  1798. if (new_offset[i] != old_offset[i]) {
  1799. SDE_DEBUG_PLANE(psde,
  1800. "offset change plane:%d old_offset:%u new_offset:%u\n",
  1801. i, old_offset[i], new_offset[i]);
  1802. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1803. SDE_PLANE_DIRTY_RECTS;
  1804. break;
  1805. }
  1806. }
  1807. }
  1808. }
  1809. int sde_plane_validate_src_addr(struct drm_plane *plane,
  1810. unsigned long base_addr, u32 size)
  1811. {
  1812. int ret = -EINVAL;
  1813. u32 addr;
  1814. struct sde_plane *psde = to_sde_plane(plane);
  1815. if (!psde || !base_addr || !size) {
  1816. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1817. return ret;
  1818. }
  1819. if (psde->pipe_hw && psde->pipe_hw->ops.get_sourceaddress) {
  1820. addr = psde->pipe_hw->ops.get_sourceaddress(psde->pipe_hw,
  1821. is_sde_plane_virtual(plane));
  1822. if ((addr >= base_addr) && (addr < (base_addr + size)))
  1823. ret = 0;
  1824. }
  1825. return ret;
  1826. }
  1827. static inline bool _sde_plane_is_pre_downscale_enabled(
  1828. struct sde_hw_inline_pre_downscale_cfg *pre_down)
  1829. {
  1830. return pre_down->pre_downscale_x_0 || pre_down->pre_downscale_y_0;
  1831. }
  1832. static int _sde_plane_validate_scaler_v2(struct sde_plane *psde,
  1833. struct sde_plane_state *pstate,
  1834. const struct sde_format *fmt,
  1835. uint32_t img_w, uint32_t img_h,
  1836. uint32_t src_w, uint32_t src_h,
  1837. uint32_t deci_w, uint32_t deci_h)
  1838. {
  1839. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  1840. bool pre_down_en;
  1841. int i;
  1842. if (!psde || !pstate || !fmt) {
  1843. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1844. return -EINVAL;
  1845. }
  1846. if (psde->debugfs_default_scale ||
  1847. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  1848. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK))
  1849. return 0;
  1850. pd_cfg = &pstate->pre_down;
  1851. pre_down_en = _sde_plane_is_pre_downscale_enabled(pd_cfg);
  1852. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_INVALID;
  1853. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1854. uint32_t hor_req_pixels, hor_fetch_pixels;
  1855. uint32_t vert_req_pixels, vert_fetch_pixels;
  1856. uint32_t src_w_tmp, src_h_tmp;
  1857. uint32_t scaler_w, scaler_h;
  1858. uint32_t pre_down_ratio_x = 1, pre_down_ratio_y = 1;
  1859. bool rot;
  1860. /* re-use color plane 1's config for plane 2 */
  1861. if (i == 2)
  1862. continue;
  1863. if (pre_down_en) {
  1864. if (i == 0 && pd_cfg->pre_downscale_x_0)
  1865. pre_down_ratio_x = pd_cfg->pre_downscale_x_0;
  1866. if (i == 0 && pd_cfg->pre_downscale_y_0)
  1867. pre_down_ratio_y = pd_cfg->pre_downscale_y_0;
  1868. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_x_1)
  1869. pre_down_ratio_x = pd_cfg->pre_downscale_x_1;
  1870. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_y_1)
  1871. pre_down_ratio_y = pd_cfg->pre_downscale_y_1;
  1872. SDE_DEBUG_PLANE(psde, "pre_down[%d]: x:%d, y:%d\n",
  1873. i, pre_down_ratio_x, pre_down_ratio_y);
  1874. }
  1875. src_w_tmp = src_w;
  1876. src_h_tmp = src_h;
  1877. /*
  1878. * For chroma plane, width is half for the following sub sampled
  1879. * formats. Except in case of decimation, where hardware avoids
  1880. * 1 line of decimation instead of downsampling.
  1881. */
  1882. if (i == 1) {
  1883. if (!deci_w &&
  1884. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1885. fmt->chroma_sample == SDE_CHROMA_H2V1))
  1886. src_w_tmp >>= 1;
  1887. if (!deci_h &&
  1888. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1889. fmt->chroma_sample == SDE_CHROMA_H1V2))
  1890. src_h_tmp >>= 1;
  1891. }
  1892. hor_req_pixels = pstate->pixel_ext.roi_w[i];
  1893. vert_req_pixels = pstate->pixel_ext.roi_h[i];
  1894. hor_fetch_pixels = DECIMATED_DIMENSION(src_w_tmp +
  1895. (int8_t)(pstate->pixel_ext.left_ftch[i] & 0xFF) +
  1896. (int8_t)(pstate->pixel_ext.right_ftch[i] & 0xFF),
  1897. deci_w);
  1898. vert_fetch_pixels = DECIMATED_DIMENSION(src_h_tmp +
  1899. (int8_t)(pstate->pixel_ext.top_ftch[i] & 0xFF) +
  1900. (int8_t)(pstate->pixel_ext.btm_ftch[i] & 0xFF),
  1901. deci_h);
  1902. if ((hor_req_pixels != hor_fetch_pixels) ||
  1903. (hor_fetch_pixels > img_w) ||
  1904. (vert_req_pixels != vert_fetch_pixels) ||
  1905. (vert_fetch_pixels > img_h)) {
  1906. SDE_ERROR_PLANE(psde,
  1907. "req %d/%d, fetch %d/%d, src %dx%d\n",
  1908. hor_req_pixels, vert_req_pixels,
  1909. hor_fetch_pixels, vert_fetch_pixels,
  1910. img_w, img_h);
  1911. return -EINVAL;
  1912. }
  1913. /*
  1914. * swap the scaler src width & height for inline-rotation 90
  1915. * comparison with Pixel-Extension, as PE is based on
  1916. * pre-rotation and QSEED is based on post-rotation
  1917. */
  1918. rot = pstate->rotation & DRM_MODE_ROTATE_90;
  1919. scaler_w = rot ? pstate->scaler3_cfg.src_height[i]
  1920. : pstate->scaler3_cfg.src_width[i];
  1921. scaler_h = rot ? pstate->scaler3_cfg.src_width[i]
  1922. : pstate->scaler3_cfg.src_height[i];
  1923. /*
  1924. * Alpha plane can only be scaled using bilinear or pixel
  1925. * repeat/drop, src_width and src_height are only specified
  1926. * for Y and UV plane
  1927. */
  1928. if (i != 3 && (hor_req_pixels / pre_down_ratio_x != scaler_w ||
  1929. vert_req_pixels / pre_down_ratio_y !=
  1930. scaler_h)) {
  1931. SDE_ERROR_PLANE(psde,
  1932. "roi[%d] roi:%dx%d scaler:%dx%d src:%dx%d rot:%d pd:%d/%d\n",
  1933. i, pstate->pixel_ext.roi_w[i],
  1934. pstate->pixel_ext.roi_h[i], scaler_w, scaler_h,
  1935. src_w, src_h, rot, pre_down_ratio_x, pre_down_ratio_y);
  1936. return -EINVAL;
  1937. }
  1938. /*
  1939. * SSPP fetch , unpack output and QSEED3 input lines need
  1940. * to match for Y plane
  1941. */
  1942. if (i == 0 &&
  1943. (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  1944. BIT(SDE_DRM_DEINTERLACE)) &&
  1945. ((pstate->scaler3_cfg.src_height[i] != (src_h/2)) ||
  1946. (pstate->pixel_ext.roi_h[i] != (src_h/2)))) {
  1947. SDE_ERROR_PLANE(psde,
  1948. "de-interlace fail roi[%d] %d/%d, src %dx%d, src %dx%d\n",
  1949. i, pstate->pixel_ext.roi_w[i],
  1950. pstate->pixel_ext.roi_h[i],
  1951. pstate->scaler3_cfg.src_width[i],
  1952. pstate->scaler3_cfg.src_height[i],
  1953. src_w, src_h);
  1954. return -EINVAL;
  1955. }
  1956. }
  1957. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2;
  1958. return 0;
  1959. }
  1960. static inline bool _sde_plane_has_pre_downscale(struct sde_plane *psde)
  1961. {
  1962. return (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  1963. }
  1964. static int _sde_atomic_check_pre_downscale(struct sde_plane *psde,
  1965. struct sde_plane_state *pstate, struct sde_rect *dst,
  1966. u32 src_w, u32 src_h)
  1967. {
  1968. int ret = 0;
  1969. u32 min_ratio_numer, min_ratio_denom;
  1970. struct sde_hw_inline_pre_downscale_cfg *pd_cfg = &pstate->pre_down;
  1971. bool pd_x;
  1972. bool pd_y;
  1973. if (!_sde_plane_is_pre_downscale_enabled(pd_cfg))
  1974. return ret;
  1975. pd_x = pd_cfg->pre_downscale_x_0 > 1;
  1976. pd_y = pd_cfg->pre_downscale_y_0 > 1;
  1977. min_ratio_numer = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_num;
  1978. min_ratio_denom = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_denom;
  1979. if (pd_x && !_sde_plane_has_pre_downscale(psde)) {
  1980. SDE_ERROR_PLANE(psde,
  1981. "hw does not support pre-downscale X: 0x%x\n",
  1982. psde->features);
  1983. ret = -EINVAL;
  1984. } else if (pd_y && !(psde->features & BIT(SDE_SSPP_PREDOWNSCALE_Y))) {
  1985. SDE_ERROR_PLANE(psde,
  1986. "hw does not support pre-downscale Y: 0x%x\n",
  1987. psde->features);
  1988. ret = -EINVAL;
  1989. } else if (!min_ratio_numer || !min_ratio_denom) {
  1990. SDE_ERROR_PLANE(psde,
  1991. "min downscale ratio not set! %u / %u\n",
  1992. min_ratio_numer, min_ratio_denom);
  1993. ret = -EINVAL;
  1994. /* compare pre-rotated src w/h with post-rotated dst h/w resp. */
  1995. } else if (pd_x && (src_w < mult_frac(dst->h, min_ratio_numer,
  1996. min_ratio_denom))) {
  1997. SDE_ERROR_PLANE(psde,
  1998. "failed min downscale-x check %u->%u, %u/%u\n",
  1999. src_w, dst->h, min_ratio_numer, min_ratio_denom);
  2000. ret = -EINVAL;
  2001. } else if (pd_y && (src_h < mult_frac(dst->w, min_ratio_numer,
  2002. min_ratio_denom))) {
  2003. SDE_ERROR_PLANE(psde,
  2004. "failed min downscale-y check %u->%u, %u/%u\n",
  2005. src_h, dst->w, min_ratio_numer, min_ratio_denom);
  2006. ret = -EINVAL;
  2007. }
  2008. return ret;
  2009. }
  2010. static void _sde_plane_get_max_downscale_limits(struct sde_plane *psde,
  2011. struct sde_plane_state *pstate, bool rt_client, u32 dst_h,
  2012. u32 src_h, u32 *max_numer_w, u32 *max_denom_w,
  2013. u32 *max_numer_h, u32 *max_denom_h)
  2014. {
  2015. bool rotated, has_predown, default_scale;
  2016. const struct sde_sspp_sub_blks *sblk;
  2017. struct sde_hw_inline_pre_downscale_cfg *pd;
  2018. rotated = pstate->rotation & DRM_MODE_ROTATE_90;
  2019. sblk = psde->pipe_sblk;
  2020. *max_numer_w = sblk->maxdwnscale;
  2021. *max_denom_w = 1;
  2022. *max_numer_h = sblk->maxdwnscale;
  2023. *max_denom_h = 1;
  2024. has_predown = _sde_plane_has_pre_downscale(psde);
  2025. if (has_predown)
  2026. pd = &pstate->pre_down;
  2027. default_scale = psde->debugfs_default_scale ||
  2028. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  2029. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK);
  2030. /**
  2031. * Inline rotation has different max vertical downscaling limits since
  2032. * the source-width becomes the scaler's pre-downscaled source-height.
  2033. **/
  2034. if (rotated) {
  2035. if (rt_client && has_predown) {
  2036. if (default_scale)
  2037. pd->pre_downscale_x_0 = (src_h >
  2038. mult_frac(dst_h, 11, 5)) ? 2 : 0;
  2039. *max_numer_h = pd->pre_downscale_x_0 ?
  2040. sblk->in_rot_maxdwnscale_rt_num :
  2041. sblk->in_rot_maxdwnscale_rt_nopd_num;
  2042. *max_denom_h = pd->pre_downscale_x_0 ?
  2043. sblk->in_rot_maxdwnscale_rt_denom :
  2044. sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2045. } else if (rt_client) {
  2046. *max_numer_h = sblk->in_rot_maxdwnscale_rt_num;
  2047. *max_denom_h = sblk->in_rot_maxdwnscale_rt_denom;
  2048. } else {
  2049. *max_numer_h = sblk->in_rot_maxdwnscale_nrt;
  2050. }
  2051. }
  2052. }
  2053. static int _sde_atomic_check_decimation_scaler(struct drm_plane_state *state,
  2054. struct sde_plane *psde, const struct sde_format *fmt,
  2055. struct sde_plane_state *pstate, struct sde_rect *src,
  2056. struct sde_rect *dst, u32 width, u32 height)
  2057. {
  2058. int ret = 0;
  2059. uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
  2060. uint32_t scaler_src_w, scaler_src_h;
  2061. uint32_t max_downscale_num_w, max_downscale_denom_w;
  2062. uint32_t max_downscale_num_h, max_downscale_denom_h;
  2063. uint32_t max_upscale, max_linewidth;
  2064. bool inline_rotation, rt_client;
  2065. struct drm_crtc *crtc;
  2066. struct drm_crtc_state *new_cstate;
  2067. const struct sde_sspp_sub_blks *sblk;
  2068. if (!state || !state->state || !state->crtc) {
  2069. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  2070. return -EINVAL;
  2071. }
  2072. deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  2073. deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  2074. src_deci_w = DECIMATED_DIMENSION(src->w, deci_w);
  2075. src_deci_h = DECIMATED_DIMENSION(src->h, deci_h);
  2076. /* with inline rotator, the source of the scaler is post-rotated */
  2077. inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90 ? true : false;
  2078. if (inline_rotation) {
  2079. scaler_src_w = src_deci_h;
  2080. scaler_src_h = src_deci_w;
  2081. } else {
  2082. scaler_src_w = src_deci_w;
  2083. scaler_src_h = src_deci_h;
  2084. }
  2085. sblk = psde->pipe_sblk;
  2086. max_upscale = sblk->maxupscale;
  2087. if (inline_rotation)
  2088. max_linewidth = sblk->in_rot_maxheight;
  2089. else if (scaler_src_w != state->crtc_w || scaler_src_h != state->crtc_h)
  2090. max_linewidth = sblk->scaling_linewidth;
  2091. else
  2092. max_linewidth = sblk->maxlinewidth;
  2093. crtc = state->crtc;
  2094. new_cstate = drm_atomic_get_new_crtc_state(state->state, crtc);
  2095. rt_client = sde_crtc_is_rt_client(crtc, new_cstate);
  2096. _sde_plane_get_max_downscale_limits(psde, pstate, rt_client, dst->h,
  2097. scaler_src_h, &max_downscale_num_w, &max_downscale_denom_w,
  2098. &max_downscale_num_h, &max_downscale_denom_h);
  2099. /* decimation validation */
  2100. if ((deci_w || deci_h)
  2101. && ((deci_w > sblk->maxhdeciexp)
  2102. || (deci_h > sblk->maxvdeciexp))) {
  2103. SDE_ERROR_PLANE(psde, "too much decimation requested\n");
  2104. ret = -EINVAL;
  2105. } else if ((deci_w || deci_h)
  2106. && (fmt->fetch_mode != SDE_FETCH_LINEAR)) {
  2107. SDE_ERROR_PLANE(psde, "decimation requires linear fetch\n");
  2108. ret = -EINVAL;
  2109. } else if (!(psde->features & SDE_SSPP_SCALER) &&
  2110. ((src->w != dst->w) || (src->h != dst->h))) {
  2111. SDE_ERROR_PLANE(psde,
  2112. "pipe doesn't support scaling %ux%u->%ux%u\n",
  2113. src->w, src->h, dst->w, dst->h);
  2114. ret = -EINVAL;
  2115. /* check scaler source width */
  2116. } else if (scaler_src_w > max_linewidth) {
  2117. SDE_ERROR_PLANE(psde,
  2118. "invalid src w:%u, scaler w:%u, line w:%u, rot: %d\n",
  2119. src->w, scaler_src_w, max_linewidth, inline_rotation);
  2120. ret = -E2BIG;
  2121. /* check max scaler capability */
  2122. } else if (((scaler_src_w * max_upscale) < dst->w) ||
  2123. ((scaler_src_h * max_upscale) < dst->h) ||
  2124. (mult_frac(dst->w, max_downscale_num_w, max_downscale_denom_w)
  2125. < scaler_src_w) ||
  2126. (mult_frac(dst->h, max_downscale_num_h, max_downscale_denom_h)
  2127. < scaler_src_h)) {
  2128. SDE_ERROR_PLANE(psde,
  2129. "too much scaling %ux%u->%ux%u rot:%d dwn:%d/%d %d/%d\n",
  2130. scaler_src_w, scaler_src_h, dst->w, dst->h,
  2131. inline_rotation, max_downscale_num_w,
  2132. max_downscale_denom_w, max_downscale_num_h,
  2133. max_downscale_denom_h);
  2134. ret = -E2BIG;
  2135. /* check inline pre-downscale support */
  2136. } else if (inline_rotation && _sde_atomic_check_pre_downscale(psde,
  2137. pstate, dst, src_deci_w, src_deci_h)) {
  2138. ret = -EINVAL;
  2139. /* QSEED validation */
  2140. } else if (_sde_plane_validate_scaler_v2(psde, pstate, fmt,
  2141. width, height, src->w, src->h,
  2142. deci_w, deci_h)) {
  2143. ret = -EINVAL;
  2144. }
  2145. return ret;
  2146. }
  2147. static int _sde_atomic_check_excl_rect(struct sde_plane *psde,
  2148. struct sde_plane_state *pstate, struct sde_rect *src,
  2149. const struct sde_format *fmt, int ret)
  2150. {
  2151. /* check excl rect configs */
  2152. if (!ret && pstate->excl_rect.w && pstate->excl_rect.h) {
  2153. struct sde_rect intersect;
  2154. /*
  2155. * Check exclusion rect against src rect.
  2156. * it must intersect with source rect.
  2157. */
  2158. sde_kms_rect_intersect(src, &pstate->excl_rect, &intersect);
  2159. if (intersect.w != pstate->excl_rect.w ||
  2160. intersect.h != pstate->excl_rect.h ||
  2161. SDE_FORMAT_IS_YUV(fmt)) {
  2162. SDE_ERROR_PLANE(psde,
  2163. "invalid excl_rect:{%d,%d,%d,%d} src:{%d,%d,%d,%d}, fmt: %4.4s\n",
  2164. pstate->excl_rect.x, pstate->excl_rect.y,
  2165. pstate->excl_rect.w, pstate->excl_rect.h,
  2166. src->x, src->y, src->w, src->h,
  2167. (char *)&fmt->base.pixel_format);
  2168. ret = -EINVAL;
  2169. }
  2170. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  2171. pstate->excl_rect.x, pstate->excl_rect.y,
  2172. pstate->excl_rect.w, pstate->excl_rect.h);
  2173. }
  2174. return ret;
  2175. }
  2176. static int _sde_plane_validate_shared_crtc(struct sde_plane *psde,
  2177. struct drm_plane_state *state)
  2178. {
  2179. struct sde_kms *sde_kms;
  2180. struct sde_splash_display *splash_display;
  2181. int i, j;
  2182. sde_kms = _sde_plane_get_kms(&psde->base);
  2183. if (!sde_kms || !state->crtc)
  2184. return 0;
  2185. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2186. splash_display = &sde_kms->splash_data.splash_display[i];
  2187. if (splash_display && splash_display->cont_splash_enabled &&
  2188. splash_display->encoder &&
  2189. state->crtc != splash_display->encoder->crtc) {
  2190. for (j = 0; j < MAX_DATA_PATH_PER_DSIPLAY; j++) {
  2191. if (splash_display->pipes[j].sspp ==
  2192. psde->pipe) {
  2193. SDE_ERROR_PLANE(psde,
  2194. "pipe:%d used in cont-splash on crtc:%d\n",
  2195. psde->pipe,
  2196. splash_display->encoder->crtc->base.id);
  2197. return -EINVAL;
  2198. }
  2199. }
  2200. }
  2201. }
  2202. return 0;
  2203. }
  2204. static int _sde_plane_sspp_atomic_check_helper(struct sde_plane *psde,
  2205. const struct sde_format *fmt,
  2206. struct sde_rect src, struct sde_rect dst,
  2207. u32 width, u32 height)
  2208. {
  2209. int ret = 0;
  2210. u32 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
  2211. if (SDE_FORMAT_IS_YUV(fmt) &&
  2212. (!(psde->features & SDE_SSPP_SCALER) ||
  2213. !(psde->features & (BIT(SDE_SSPP_CSC)
  2214. | BIT(SDE_SSPP_CSC_10BIT))))) {
  2215. SDE_ERROR_PLANE(psde,
  2216. "plane doesn't have scaler/csc for yuv\n");
  2217. ret = -EINVAL;
  2218. /* check src bounds */
  2219. } else if (width > MAX_IMG_WIDTH || height > MAX_IMG_HEIGHT ||
  2220. src.w < min_src_size || src.h < min_src_size ||
  2221. CHECK_LAYER_BOUNDS(src.x, src.w, width) ||
  2222. CHECK_LAYER_BOUNDS(src.y, src.h, height)) {
  2223. SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
  2224. src.x, src.y, src.w, src.h);
  2225. ret = -E2BIG;
  2226. /* valid yuv image */
  2227. } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
  2228. (src.w & 0x1) || (src.h & 0x1))) {
  2229. SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
  2230. src.x, src.y, src.w, src.h);
  2231. ret = -EINVAL;
  2232. /* min dst support */
  2233. } else if (dst.w < 0x1 || dst.h < 0x1) {
  2234. SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
  2235. dst.x, dst.y, dst.w, dst.h);
  2236. ret = -EINVAL;
  2237. } else if (SDE_FORMAT_IS_UBWC(fmt) &&
  2238. !psde->catalog->ubwc_version) {
  2239. SDE_ERROR_PLANE(psde, "ubwc not supported\n");
  2240. ret = -EINVAL;
  2241. }
  2242. return ret;
  2243. }
  2244. static int sde_plane_sspp_atomic_check(struct drm_plane *plane,
  2245. struct drm_plane_state *state)
  2246. {
  2247. int ret = 0;
  2248. struct sde_plane *psde;
  2249. struct sde_plane_state *pstate;
  2250. const struct msm_format *msm_fmt;
  2251. const struct sde_format *fmt;
  2252. struct sde_rect src, dst;
  2253. bool q16_data = true;
  2254. struct drm_framebuffer *fb;
  2255. u32 width;
  2256. u32 height;
  2257. psde = to_sde_plane(plane);
  2258. pstate = to_sde_plane_state(state);
  2259. if (!psde->pipe_sblk) {
  2260. SDE_ERROR_PLANE(psde, "invalid catalog\n");
  2261. return -EINVAL;
  2262. }
  2263. /* src values are in Q16 fixed point, convert to integer */
  2264. POPULATE_RECT(&src, state->src_x, state->src_y,
  2265. state->src_w, state->src_h, q16_data);
  2266. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
  2267. state->crtc_h, !q16_data);
  2268. SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
  2269. sde_plane_enabled(plane->state), sde_plane_enabled(state));
  2270. if (!sde_plane_enabled(state))
  2271. goto modeset_update;
  2272. fb = state->fb;
  2273. width = fb ? state->fb->width : 0x0;
  2274. height = fb ? state->fb->height : 0x0;
  2275. SDE_DEBUG("plane%d sspp:%x/%dx%d/%4.4s/%llx\n",
  2276. plane->base.id,
  2277. pstate->rotation,
  2278. width, height,
  2279. fb ? (char *) &state->fb->format->format : 0x0,
  2280. fb ? state->fb->modifier : 0x0);
  2281. SDE_DEBUG("src:%dx%d %d,%d crtc:%dx%d+%d+%d\n",
  2282. state->src_w >> 16, state->src_h >> 16,
  2283. state->src_x >> 16, state->src_y >> 16,
  2284. state->crtc_w, state->crtc_h,
  2285. state->crtc_x, state->crtc_y);
  2286. msm_fmt = msm_framebuffer_format(fb);
  2287. fmt = to_sde_format(msm_fmt);
  2288. ret = _sde_plane_sspp_atomic_check_helper(psde, fmt, src, dst, width,
  2289. height);
  2290. if (ret)
  2291. return ret;
  2292. ret = _sde_atomic_check_decimation_scaler(state, psde, fmt, pstate,
  2293. &src, &dst, width, height);
  2294. if (ret)
  2295. return ret;
  2296. ret = _sde_atomic_check_excl_rect(psde, pstate,
  2297. &src, fmt, ret);
  2298. if (ret)
  2299. return ret;
  2300. ret = _sde_plane_validate_shared_crtc(psde, state);
  2301. if (ret)
  2302. return ret;
  2303. pstate->const_alpha_en = fmt->alpha_enable &&
  2304. (SDE_DRM_BLEND_OP_OPAQUE !=
  2305. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP)) &&
  2306. (pstate->stage != SDE_STAGE_0);
  2307. modeset_update:
  2308. if (!ret)
  2309. _sde_plane_sspp_atomic_check_mode_changed(psde,
  2310. state, plane->state);
  2311. return ret;
  2312. }
  2313. static int sde_plane_atomic_check(struct drm_plane *plane,
  2314. struct drm_plane_state *state)
  2315. {
  2316. int ret = 0;
  2317. struct sde_plane *psde;
  2318. struct sde_plane_state *pstate;
  2319. if (!plane || !state) {
  2320. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  2321. !plane, !state);
  2322. ret = -EINVAL;
  2323. goto exit;
  2324. }
  2325. psde = to_sde_plane(plane);
  2326. pstate = to_sde_plane_state(state);
  2327. SDE_DEBUG_PLANE(psde, "\n");
  2328. ret = sde_plane_rot_atomic_check(plane, state);
  2329. if (ret)
  2330. goto exit;
  2331. ret = sde_plane_sspp_atomic_check(plane, state);
  2332. exit:
  2333. return ret;
  2334. }
  2335. void sde_plane_flush(struct drm_plane *plane)
  2336. {
  2337. struct sde_plane *psde;
  2338. struct sde_plane_state *pstate;
  2339. if (!plane || !plane->state) {
  2340. SDE_ERROR("invalid plane\n");
  2341. return;
  2342. }
  2343. psde = to_sde_plane(plane);
  2344. pstate = to_sde_plane_state(plane->state);
  2345. /*
  2346. * These updates have to be done immediately before the plane flush
  2347. * timing, and may not be moved to the atomic_update/mode_set functions.
  2348. */
  2349. if (psde->is_error)
  2350. /* force white frame with 100% alpha pipe output on error */
  2351. _sde_plane_color_fill(psde, 0xFFFFFF, 0xFF);
  2352. else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
  2353. /* force 100% alpha */
  2354. _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
  2355. else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
  2356. psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
  2357. /* flag h/w flush complete */
  2358. if (plane->state)
  2359. pstate->pending = false;
  2360. }
  2361. /**
  2362. * sde_plane_set_error: enable/disable error condition
  2363. * @plane: pointer to drm_plane structure
  2364. */
  2365. void sde_plane_set_error(struct drm_plane *plane, bool error)
  2366. {
  2367. struct sde_plane *psde;
  2368. if (!plane)
  2369. return;
  2370. psde = to_sde_plane(plane);
  2371. psde->is_error = error;
  2372. }
  2373. static void _sde_plane_sspp_setup_sys_cache(struct sde_plane *psde,
  2374. struct sde_plane_state *pstate, bool is_tp10)
  2375. {
  2376. struct sde_sc_cfg *sc_cfg = psde->catalog->sc_cfg;
  2377. bool prev_rd_en;
  2378. if (!psde->pipe_hw->ops.setup_sys_cache ||
  2379. !(psde->perf_features & BIT(SDE_PERF_SSPP_SYS_CACHE)))
  2380. return;
  2381. prev_rd_en = pstate->sc_cfg.rd_en;
  2382. SDE_DEBUG("features:0x%x rotation:0x%x\n",
  2383. psde->features, pstate->rotation);
  2384. pstate->sc_cfg.rd_en = false;
  2385. pstate->sc_cfg.rd_scid = 0x0;
  2386. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2387. SSPP_SYS_CACHE_SCID;
  2388. pstate->sc_cfg.type = SDE_SYS_CACHE_NONE;
  2389. if (pstate->rotation & DRM_MODE_ROTATE_90) {
  2390. if (is_tp10 && sc_cfg[SDE_SYS_CACHE_ROT].has_sys_cache) {
  2391. pstate->sc_cfg.rd_en = true;
  2392. pstate->sc_cfg.rd_scid =
  2393. sc_cfg[SDE_SYS_CACHE_ROT].llcc_scid;
  2394. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2395. SSPP_SYS_CACHE_SCID;
  2396. pstate->sc_cfg.type = SDE_SYS_CACHE_ROT;
  2397. }
  2398. } else if (pstate->static_cache_state == CACHE_STATE_FRAME_WRITE &&
  2399. sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache) {
  2400. pstate->sc_cfg.rd_en = true;
  2401. pstate->sc_cfg.rd_scid =
  2402. sc_cfg[SDE_SYS_CACHE_DISP].llcc_scid;
  2403. pstate->sc_cfg.rd_noallocate = false;
  2404. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2405. SSPP_SYS_CACHE_SCID | SSPP_SYS_CACHE_NO_ALLOC;
  2406. pstate->sc_cfg.type = SDE_SYS_CACHE_DISP;
  2407. } else if (pstate->static_cache_state == CACHE_STATE_FRAME_READ &&
  2408. sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache) {
  2409. pstate->sc_cfg.rd_en = true;
  2410. pstate->sc_cfg.rd_scid =
  2411. sc_cfg[SDE_SYS_CACHE_DISP].llcc_scid;
  2412. pstate->sc_cfg.rd_noallocate = true;
  2413. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2414. SSPP_SYS_CACHE_SCID | SSPP_SYS_CACHE_NO_ALLOC;
  2415. pstate->sc_cfg.type = SDE_SYS_CACHE_DISP;
  2416. }
  2417. if (!pstate->sc_cfg.rd_en && !prev_rd_en)
  2418. return;
  2419. SDE_EVT32(DRMID(&psde->base), pstate->sc_cfg.rd_scid,
  2420. pstate->sc_cfg.rd_en, pstate->sc_cfg.rd_noallocate);
  2421. psde->pipe_hw->ops.setup_sys_cache(
  2422. psde->pipe_hw, &pstate->sc_cfg);
  2423. }
  2424. void sde_plane_static_img_control(struct drm_plane *plane,
  2425. enum sde_crtc_cache_state state)
  2426. {
  2427. struct sde_plane *psde;
  2428. struct sde_plane_state *pstate;
  2429. if (!plane || !plane->state) {
  2430. SDE_ERROR("invalid plane\n");
  2431. return;
  2432. }
  2433. psde = to_sde_plane(plane);
  2434. pstate = to_sde_plane_state(plane->state);
  2435. pstate->static_cache_state = state;
  2436. if (state == CACHE_STATE_FRAME_WRITE || state == CACHE_STATE_FRAME_READ)
  2437. _sde_plane_sspp_setup_sys_cache(psde, pstate, false);
  2438. }
  2439. static void _sde_plane_map_prop_to_dirty_bits(void)
  2440. {
  2441. plane_prop_array[PLANE_PROP_SCALER_V1] =
  2442. plane_prop_array[PLANE_PROP_SCALER_V2] =
  2443. plane_prop_array[PLANE_PROP_SCALER_LUT_ED] =
  2444. plane_prop_array[PLANE_PROP_SCALER_LUT_CIR] =
  2445. plane_prop_array[PLANE_PROP_SCALER_LUT_SEP] =
  2446. plane_prop_array[PLANE_PROP_H_DECIMATE] =
  2447. plane_prop_array[PLANE_PROP_V_DECIMATE] =
  2448. plane_prop_array[PLANE_PROP_SRC_CONFIG] =
  2449. plane_prop_array[PLANE_PROP_ZPOS] =
  2450. plane_prop_array[PLANE_PROP_EXCL_RECT_V1] =
  2451. SDE_PLANE_DIRTY_RECTS;
  2452. plane_prop_array[PLANE_PROP_CSC_V1] =
  2453. plane_prop_array[PLANE_PROP_CSC_DMA_V1] =
  2454. plane_prop_array[PLANE_PROP_INVERSE_PMA] =
  2455. SDE_PLANE_DIRTY_FORMAT;
  2456. plane_prop_array[PLANE_PROP_MULTIRECT_MODE] =
  2457. plane_prop_array[PLANE_PROP_COLOR_FILL] =
  2458. SDE_PLANE_DIRTY_ALL;
  2459. /* no special action required */
  2460. plane_prop_array[PLANE_PROP_INFO] =
  2461. plane_prop_array[PLANE_PROP_ALPHA] =
  2462. plane_prop_array[PLANE_PROP_INPUT_FENCE] =
  2463. plane_prop_array[PLANE_PROP_BLEND_OP] = 0;
  2464. plane_prop_array[PLANE_PROP_FB_TRANSLATION_MODE] =
  2465. SDE_PLANE_DIRTY_FB_TRANSLATION_MODE;
  2466. plane_prop_array[PLANE_PROP_PREFILL_SIZE] =
  2467. plane_prop_array[PLANE_PROP_PREFILL_TIME] =
  2468. SDE_PLANE_DIRTY_PERF;
  2469. plane_prop_array[PLANE_PROP_VIG_GAMUT] = SDE_PLANE_DIRTY_VIG_GAMUT;
  2470. plane_prop_array[PLANE_PROP_VIG_IGC] = SDE_PLANE_DIRTY_VIG_IGC;
  2471. plane_prop_array[PLANE_PROP_DMA_IGC] = SDE_PLANE_DIRTY_DMA_IGC;
  2472. plane_prop_array[PLANE_PROP_DMA_GC] = SDE_PLANE_DIRTY_DMA_GC;
  2473. plane_prop_array[PLANE_PROP_SKIN_COLOR] =
  2474. plane_prop_array[PLANE_PROP_SKY_COLOR] =
  2475. plane_prop_array[PLANE_PROP_FOLIAGE_COLOR] =
  2476. plane_prop_array[PLANE_PROP_HUE_ADJUST] =
  2477. plane_prop_array[PLANE_PROP_SATURATION_ADJUST] =
  2478. plane_prop_array[PLANE_PROP_VALUE_ADJUST] =
  2479. plane_prop_array[PLANE_PROP_CONTRAST_ADJUST] =
  2480. SDE_PLANE_DIRTY_ALL;
  2481. plane_prop_array[PLANE_PROP_FP16_IGC] = SDE_PLANE_DIRTY_FP16_IGC;
  2482. plane_prop_array[PLANE_PROP_FP16_GC] = SDE_PLANE_DIRTY_FP16_GC;
  2483. plane_prop_array[PLANE_PROP_FP16_CSC] = SDE_PLANE_DIRTY_FP16_CSC;
  2484. plane_prop_array[PLANE_PROP_FP16_UNMULT] = SDE_PLANE_DIRTY_FP16_UNMULT;
  2485. }
  2486. static inline bool _sde_plane_allow_uidle(struct sde_plane *psde,
  2487. struct sde_rect *src, struct sde_rect *dst)
  2488. {
  2489. u32 max_downscale = psde->catalog->uidle_cfg.max_dwnscale;
  2490. u32 downscale = (src->h * 1000)/dst->h;
  2491. return (downscale > max_downscale) ? false : true;
  2492. }
  2493. static void _sde_plane_setup_uidle(struct drm_crtc *crtc,
  2494. struct sde_plane *psde, struct sde_plane_state *pstate,
  2495. struct sde_rect *src, struct sde_rect *dst)
  2496. {
  2497. struct sde_hw_pipe_uidle_cfg cfg;
  2498. u32 fal1_threshold_max = 15;
  2499. u32 line_time = sde_crtc_get_line_time(crtc);
  2500. u32 fal1_target_idle_time_ns =
  2501. psde->catalog->uidle_cfg.fal1_target_idle_time * 1000; /* nS */
  2502. u32 fal10_target_idle_time_ns =
  2503. psde->catalog->uidle_cfg.fal10_target_idle_time * 1000; /* nS */
  2504. u32 fal10_threshold =
  2505. psde->catalog->uidle_cfg.fal10_threshold; /* uS */
  2506. if (line_time && fal10_threshold && fal10_target_idle_time_ns &&
  2507. fal1_target_idle_time_ns) {
  2508. cfg.enable = _sde_plane_allow_uidle(psde, src, dst);
  2509. cfg.fal10_threshold = fal10_threshold;
  2510. cfg.fal10_exit_threshold = fal10_threshold + 2;
  2511. cfg.fal1_threshold = min(1 +
  2512. (fal1_target_idle_time_ns*1000/line_time*2)/1000,
  2513. fal1_threshold_max);
  2514. cfg.fal_allowed_threshold = fal10_threshold +
  2515. (fal10_target_idle_time_ns*1000/line_time*2)/1000;
  2516. } else {
  2517. SDE_ERROR("invalid settings, will disable UIDLE %d %d %d %d\n",
  2518. line_time, fal10_threshold, fal10_target_idle_time_ns,
  2519. fal1_target_idle_time_ns);
  2520. memset(&cfg, 0, sizeof(struct sde_hw_pipe_uidle_cfg));
  2521. }
  2522. SDE_DEBUG_PLANE(psde,
  2523. "tholds: fal10=%d fal10_exit=%d fal1=%d fal_allowed=%d\n",
  2524. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2525. cfg.fal1_threshold, cfg.fal_allowed_threshold);
  2526. SDE_DEBUG_PLANE(psde,
  2527. "times: line:%d fal1_idle:%d fal10_idle:%d dwnscale:%d\n",
  2528. line_time, fal1_target_idle_time_ns,
  2529. fal10_target_idle_time_ns,
  2530. psde->catalog->uidle_cfg.max_dwnscale);
  2531. SDE_EVT32_VERBOSE(cfg.enable,
  2532. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2533. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2534. psde->catalog->uidle_cfg.max_dwnscale);
  2535. psde->pipe_hw->ops.setup_uidle(
  2536. psde->pipe_hw, &cfg,
  2537. pstate->multirect_index);
  2538. }
  2539. static void _sde_plane_update_secure_session(struct sde_plane *psde,
  2540. struct sde_plane_state *pstate)
  2541. {
  2542. bool enable = false;
  2543. int mode = sde_plane_get_property(pstate,
  2544. PLANE_PROP_FB_TRANSLATION_MODE);
  2545. if ((mode == SDE_DRM_FB_SEC) ||
  2546. (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  2547. enable = true;
  2548. /* update secure session flag */
  2549. psde->pipe_hw->ops.setup_secure_address(psde->pipe_hw,
  2550. pstate->multirect_index,
  2551. enable);
  2552. }
  2553. static void _sde_plane_update_roi_config(struct drm_plane *plane,
  2554. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2555. {
  2556. const struct sde_format *fmt;
  2557. const struct msm_format *msm_fmt;
  2558. struct sde_plane *psde;
  2559. struct drm_plane_state *state;
  2560. struct sde_plane_state *pstate;
  2561. struct sde_rect src, dst;
  2562. const struct sde_rect *crtc_roi;
  2563. bool q16_data = true;
  2564. int idx;
  2565. psde = to_sde_plane(plane);
  2566. state = plane->state;
  2567. pstate = to_sde_plane_state(state);
  2568. msm_fmt = msm_framebuffer_format(fb);
  2569. if (!msm_fmt) {
  2570. SDE_ERROR("crtc%d plane%d: null format\n",
  2571. DRMID(crtc), DRMID(plane));
  2572. return;
  2573. }
  2574. fmt = to_sde_format(msm_fmt);
  2575. POPULATE_RECT(&src, state->src_x, state->src_y,
  2576. state->src_w, state->src_h, q16_data);
  2577. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
  2578. state->crtc_w, state->crtc_h, !q16_data);
  2579. SDE_DEBUG_PLANE(psde,
  2580. "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %4.4s ubwc %d\n",
  2581. fb->base.id, src.x, src.y, src.w, src.h,
  2582. crtc->base.id, dst.x, dst.y, dst.w, dst.h,
  2583. (char *)&fmt->base.pixel_format,
  2584. SDE_FORMAT_IS_UBWC(fmt));
  2585. if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  2586. BIT(SDE_DRM_DEINTERLACE)) {
  2587. SDE_DEBUG_PLANE(psde, "deinterlace\n");
  2588. for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
  2589. psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
  2590. src.h /= 2;
  2591. src.y = DIV_ROUND_UP(src.y, 2);
  2592. src.y &= ~0x1;
  2593. }
  2594. /*
  2595. * adjust layer mixer position of the sspp in the presence
  2596. * of a partial update to the active lm origin
  2597. */
  2598. sde_crtc_get_crtc_roi(crtc->state, &crtc_roi);
  2599. dst.x -= crtc_roi->x;
  2600. dst.y -= crtc_roi->y;
  2601. /* check for UIDLE */
  2602. if (psde->pipe_hw->ops.setup_uidle)
  2603. _sde_plane_setup_uidle(crtc, psde, pstate, &src, &dst);
  2604. psde->pipe_cfg.src_rect = src;
  2605. psde->pipe_cfg.dst_rect = dst;
  2606. _sde_plane_setup_scaler(psde, pstate, fmt, false);
  2607. /* check for color fill */
  2608. psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
  2609. PLANE_PROP_COLOR_FILL);
  2610. if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
  2611. /* skip remaining processing on color fill */
  2612. pstate->dirty = 0x0;
  2613. } else if (psde->pipe_hw->ops.setup_rects) {
  2614. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  2615. &psde->pipe_cfg,
  2616. pstate->multirect_index);
  2617. }
  2618. if (psde->pipe_hw->ops.setup_pe &&
  2619. (pstate->multirect_index != SDE_SSPP_RECT_1))
  2620. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  2621. &pstate->pixel_ext);
  2622. /**
  2623. * when programmed in multirect mode, scalar block will be
  2624. * bypassed. Still we need to update alpha and bitwidth
  2625. * ONLY for RECT0
  2626. */
  2627. if (psde->pipe_hw->ops.setup_scaler &&
  2628. pstate->multirect_index != SDE_SSPP_RECT_1) {
  2629. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  2630. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  2631. &psde->pipe_cfg, &pstate->pixel_ext,
  2632. &pstate->scaler3_cfg);
  2633. }
  2634. /* update excl rect */
  2635. if (psde->pipe_hw->ops.setup_excl_rect)
  2636. psde->pipe_hw->ops.setup_excl_rect(psde->pipe_hw,
  2637. &pstate->excl_rect,
  2638. pstate->multirect_index);
  2639. /* enable multirect config of corresponding rect */
  2640. if (psde->pipe_hw->ops.update_multirect)
  2641. psde->pipe_hw->ops.update_multirect(
  2642. psde->pipe_hw,
  2643. true,
  2644. pstate->multirect_index,
  2645. pstate->multirect_mode);
  2646. }
  2647. static void _sde_plane_update_format_and_rects(struct sde_plane *psde,
  2648. struct sde_plane_state *pstate, const struct sde_format *fmt)
  2649. {
  2650. uint32_t src_flags = 0;
  2651. SDE_DEBUG_PLANE(psde, "rotation 0x%X\n", pstate->rotation);
  2652. if (pstate->rotation & DRM_MODE_REFLECT_X)
  2653. src_flags |= SDE_SSPP_FLIP_LR;
  2654. if (pstate->rotation & DRM_MODE_REFLECT_Y)
  2655. src_flags |= SDE_SSPP_FLIP_UD;
  2656. if (pstate->rotation & DRM_MODE_ROTATE_90)
  2657. src_flags |= SDE_SSPP_ROT_90;
  2658. /* update format */
  2659. psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt,
  2660. pstate->const_alpha_en, src_flags,
  2661. pstate->multirect_index);
  2662. if (psde->pipe_hw->ops.setup_cdp) {
  2663. struct sde_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
  2664. memset(cdp_cfg, 0, sizeof(struct sde_hw_pipe_cdp_cfg));
  2665. cdp_cfg->enable = psde->catalog->perf.cdp_cfg
  2666. [SDE_PERF_CDP_USAGE_RT].rd_enable;
  2667. cdp_cfg->ubwc_meta_enable =
  2668. SDE_FORMAT_IS_UBWC(fmt);
  2669. cdp_cfg->tile_amortize_enable =
  2670. SDE_FORMAT_IS_UBWC(fmt) ||
  2671. SDE_FORMAT_IS_TILE(fmt);
  2672. cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;
  2673. psde->pipe_hw->ops.setup_cdp(psde->pipe_hw, cdp_cfg,
  2674. pstate->multirect_index);
  2675. }
  2676. _sde_plane_sspp_setup_sys_cache(psde, pstate,
  2677. sde_format_is_tp10_ubwc(fmt));
  2678. /* update csc */
  2679. if (SDE_FORMAT_IS_YUV(fmt))
  2680. _sde_plane_setup_csc(psde);
  2681. else
  2682. psde->csc_ptr = 0;
  2683. if (psde->pipe_hw->ops.setup_inverse_pma) {
  2684. uint32_t pma_mode = 0;
  2685. if (fmt->alpha_enable)
  2686. pma_mode = (uint32_t) sde_plane_get_property(
  2687. pstate, PLANE_PROP_INVERSE_PMA);
  2688. psde->pipe_hw->ops.setup_inverse_pma(psde->pipe_hw,
  2689. pstate->multirect_index, pma_mode);
  2690. }
  2691. if (psde->pipe_hw->ops.setup_dgm_csc)
  2692. psde->pipe_hw->ops.setup_dgm_csc(psde->pipe_hw,
  2693. pstate->multirect_index, psde->csc_usr_ptr);
  2694. }
  2695. static void _sde_plane_update_sharpening(struct sde_plane *psde)
  2696. {
  2697. psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
  2698. psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
  2699. psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
  2700. psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
  2701. psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
  2702. &psde->sharp_cfg);
  2703. }
  2704. static void _sde_plane_update_properties(struct drm_plane *plane,
  2705. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2706. {
  2707. uint32_t nplanes;
  2708. const struct msm_format *msm_fmt;
  2709. const struct sde_format *fmt;
  2710. struct sde_plane *psde;
  2711. struct drm_plane_state *state;
  2712. struct sde_plane_state *pstate;
  2713. psde = to_sde_plane(plane);
  2714. state = plane->state;
  2715. pstate = to_sde_plane_state(state);
  2716. if (!pstate) {
  2717. SDE_ERROR("invalid plane state for plane%d\n", DRMID(plane));
  2718. return;
  2719. }
  2720. msm_fmt = msm_framebuffer_format(fb);
  2721. if (!msm_fmt) {
  2722. SDE_ERROR("crtc%d plane%d: null format\n",
  2723. DRMID(crtc), DRMID(plane));
  2724. return;
  2725. }
  2726. fmt = to_sde_format(msm_fmt);
  2727. nplanes = fmt->num_planes;
  2728. /* update secure session flag */
  2729. if (pstate->dirty & SDE_PLANE_DIRTY_FB_TRANSLATION_MODE)
  2730. _sde_plane_update_secure_session(psde, pstate);
  2731. /* update roi config */
  2732. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2733. _sde_plane_update_roi_config(plane, crtc, fb);
  2734. if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT ||
  2735. pstate->dirty & SDE_PLANE_DIRTY_RECTS) &&
  2736. psde->pipe_hw->ops.setup_format)
  2737. _sde_plane_update_format_and_rects(psde, pstate, fmt);
  2738. sde_color_process_plane_setup(plane);
  2739. /* update sharpening */
  2740. if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
  2741. psde->pipe_hw->ops.setup_sharpening)
  2742. _sde_plane_update_sharpening(psde);
  2743. if (pstate->dirty & (SDE_PLANE_DIRTY_QOS | SDE_PLANE_DIRTY_RECTS |
  2744. SDE_PLANE_DIRTY_FORMAT))
  2745. _sde_plane_set_qos_lut(plane, crtc, fb);
  2746. if (plane->type != DRM_PLANE_TYPE_CURSOR) {
  2747. _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
  2748. _sde_plane_set_ot_limit(plane, crtc);
  2749. if (pstate->dirty & SDE_PLANE_DIRTY_PERF)
  2750. _sde_plane_set_ts_prefill(plane, pstate);
  2751. }
  2752. if (pstate->dirty & SDE_PLANE_DIRTY_QOS)
  2753. _sde_plane_set_qos_remap(plane);
  2754. /* clear dirty */
  2755. pstate->dirty = 0x0;
  2756. }
  2757. static int sde_plane_sspp_atomic_update(struct drm_plane *plane,
  2758. struct drm_plane_state *old_state)
  2759. {
  2760. struct sde_plane *psde;
  2761. struct drm_plane_state *state;
  2762. struct sde_plane_state *pstate;
  2763. struct sde_plane_state *old_pstate;
  2764. struct drm_crtc *crtc;
  2765. struct drm_framebuffer *fb;
  2766. int idx;
  2767. int dirty_prop_flag;
  2768. bool is_rt;
  2769. if (!plane) {
  2770. SDE_ERROR("invalid plane\n");
  2771. return -EINVAL;
  2772. } else if (!plane->state) {
  2773. SDE_ERROR("invalid plane state\n");
  2774. return -EINVAL;
  2775. } else if (!old_state) {
  2776. SDE_ERROR("invalid old state\n");
  2777. return -EINVAL;
  2778. }
  2779. psde = to_sde_plane(plane);
  2780. state = plane->state;
  2781. pstate = to_sde_plane_state(state);
  2782. old_pstate = to_sde_plane_state(old_state);
  2783. crtc = state->crtc;
  2784. fb = state->fb;
  2785. if (!crtc || !fb) {
  2786. SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
  2787. !crtc, !fb);
  2788. return -EINVAL;
  2789. }
  2790. SDE_DEBUG(
  2791. "plane%d sspp:%dx%d/%4.4s/%llx/%dx%d+%d+%d/%x crtc:%dx%d+%d+%d\n",
  2792. plane->base.id,
  2793. state->fb->width, state->fb->height,
  2794. (char *) &state->fb->format->format,
  2795. state->fb->modifier,
  2796. state->src_w >> 16, state->src_h >> 16,
  2797. state->src_x >> 16, state->src_y >> 16,
  2798. pstate->rotation,
  2799. state->crtc_w, state->crtc_h,
  2800. state->crtc_x, state->crtc_y);
  2801. /* force reprogramming of all the parameters, if the flag is set */
  2802. if (psde->revalidate) {
  2803. SDE_DEBUG("plane:%d - reconfigure all the parameters\n",
  2804. plane->base.id);
  2805. pstate->dirty = SDE_PLANE_DIRTY_ALL | SDE_PLANE_DIRTY_CP;
  2806. psde->revalidate = false;
  2807. }
  2808. /* determine what needs to be refreshed */
  2809. mutex_lock(&psde->property_info.property_lock);
  2810. while ((idx = msm_property_pop_dirty(&psde->property_info,
  2811. &pstate->property_state)) >= 0) {
  2812. dirty_prop_flag = plane_prop_array[idx];
  2813. pstate->dirty |= dirty_prop_flag;
  2814. }
  2815. mutex_unlock(&psde->property_info.property_lock);
  2816. /**
  2817. * since plane_atomic_check is invoked before crtc_atomic_check
  2818. * in the commit sequence, all the parameters for updating the
  2819. * plane dirty flag will not be available during
  2820. * plane_atomic_check as some features params are updated
  2821. * in crtc_atomic_check (eg.:sDMA). So check for mode_change
  2822. * before sspp update.
  2823. */
  2824. _sde_plane_sspp_atomic_check_mode_changed(psde, state,
  2825. old_state);
  2826. /* re-program the output rects always if partial update roi changed */
  2827. if (sde_crtc_is_crtc_roi_dirty(crtc->state))
  2828. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  2829. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2830. memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
  2831. _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
  2832. is_rt = sde_crtc_is_rt_client(crtc, crtc->state);
  2833. if (is_rt != psde->is_rt_pipe) {
  2834. psde->is_rt_pipe = is_rt;
  2835. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  2836. }
  2837. /* early out if nothing dirty */
  2838. if (!pstate->dirty)
  2839. return 0;
  2840. pstate->pending = true;
  2841. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  2842. _sde_plane_update_properties(plane, crtc, fb);
  2843. return 0;
  2844. }
  2845. static void _sde_plane_atomic_disable(struct drm_plane *plane,
  2846. struct drm_plane_state *old_state)
  2847. {
  2848. struct sde_plane *psde;
  2849. struct drm_plane_state *state;
  2850. struct sde_plane_state *pstate;
  2851. u32 multirect_index = SDE_SSPP_RECT_0;
  2852. struct sde_cp_crtc_skip_blend_plane skip_blend_plane;
  2853. u32 blend_type;
  2854. if (!plane) {
  2855. SDE_ERROR("invalid plane\n");
  2856. return;
  2857. } else if (!plane->state) {
  2858. SDE_ERROR("invalid plane state\n");
  2859. return;
  2860. } else if (!old_state) {
  2861. SDE_ERROR("invalid old state\n");
  2862. return;
  2863. }
  2864. psde = to_sde_plane(plane);
  2865. state = plane->state;
  2866. pstate = to_sde_plane_state(state);
  2867. blend_type = sde_plane_get_property(pstate,
  2868. PLANE_PROP_BLEND_OP);
  2869. /* some of the color features are dependent on plane with skip blend.
  2870. * if skip blend plane is being disabled, we need to disable color properties.
  2871. */
  2872. if (blend_type == SDE_DRM_BLEND_OP_SKIP && old_state->crtc) {
  2873. skip_blend_plane.valid_plane = false;
  2874. skip_blend_plane.plane = SSPP_NONE;
  2875. sde_cp_set_skip_blend_plane_info(old_state->crtc, &skip_blend_plane);
  2876. sde_crtc_disable_cp_features(old_state->crtc);
  2877. }
  2878. SDE_EVT32(DRMID(plane), is_sde_plane_virtual(plane),
  2879. pstate->multirect_mode);
  2880. pstate->pending = true;
  2881. if (is_sde_plane_virtual(plane))
  2882. multirect_index = SDE_SSPP_RECT_1;
  2883. /* disable multirect config of corresponding rect */
  2884. if (psde->pipe_hw && psde->pipe_hw->ops.update_multirect)
  2885. psde->pipe_hw->ops.update_multirect(psde->pipe_hw, false,
  2886. multirect_index, SDE_SSPP_MULTIRECT_TIME_MX);
  2887. }
  2888. static void sde_plane_atomic_update(struct drm_plane *plane,
  2889. struct drm_plane_state *old_state)
  2890. {
  2891. struct sde_plane *psde;
  2892. struct drm_plane_state *state;
  2893. if (!plane) {
  2894. SDE_ERROR("invalid plane\n");
  2895. return;
  2896. } else if (!plane->state) {
  2897. SDE_ERROR("invalid plane state\n");
  2898. return;
  2899. }
  2900. psde = to_sde_plane(plane);
  2901. psde->is_error = false;
  2902. state = plane->state;
  2903. SDE_DEBUG_PLANE(psde, "\n");
  2904. if (!sde_plane_enabled(state)) {
  2905. _sde_plane_atomic_disable(plane, old_state);
  2906. } else {
  2907. int ret;
  2908. ret = sde_plane_sspp_atomic_update(plane, old_state);
  2909. /* atomic_check should have ensured that this doesn't fail */
  2910. WARN_ON(ret < 0);
  2911. }
  2912. }
  2913. void sde_plane_restore(struct drm_plane *plane)
  2914. {
  2915. struct sde_plane *psde;
  2916. if (!plane || !plane->state) {
  2917. SDE_ERROR("invalid plane\n");
  2918. return;
  2919. }
  2920. psde = to_sde_plane(plane);
  2921. /*
  2922. * Revalidate is only true here if idle PC occurred and
  2923. * there is no plane state update in current commit cycle.
  2924. */
  2925. if (!psde->revalidate)
  2926. return;
  2927. SDE_DEBUG_PLANE(psde, "\n");
  2928. /* last plane state is same as current state */
  2929. sde_plane_atomic_update(plane, plane->state);
  2930. }
  2931. bool sde_plane_is_cache_required(struct drm_plane *plane,
  2932. enum sde_sys_cache_type type)
  2933. {
  2934. struct sde_plane_state *pstate;
  2935. if (!plane || !plane->state) {
  2936. SDE_ERROR("invalid plane\n");
  2937. return false;
  2938. }
  2939. pstate = to_sde_plane_state(plane->state);
  2940. /* check if llcc is required for the plane */
  2941. if (pstate->sc_cfg.rd_en && (pstate->sc_cfg.type == type))
  2942. return true;
  2943. else
  2944. return false;
  2945. }
  2946. static void _sde_plane_install_master_only_properties(struct sde_plane *psde)
  2947. {
  2948. char feature_name[256];
  2949. if (psde->pipe_sblk->maxhdeciexp) {
  2950. msm_property_install_range(&psde->property_info,
  2951. "h_decimate", 0x0, 0,
  2952. psde->pipe_sblk->maxhdeciexp, 0,
  2953. PLANE_PROP_H_DECIMATE);
  2954. }
  2955. if (psde->pipe_sblk->maxvdeciexp) {
  2956. msm_property_install_range(&psde->property_info,
  2957. "v_decimate", 0x0, 0,
  2958. psde->pipe_sblk->maxvdeciexp, 0,
  2959. PLANE_PROP_V_DECIMATE);
  2960. }
  2961. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  2962. msm_property_install_range(
  2963. &psde->property_info, "scaler_v2",
  2964. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  2965. msm_property_install_blob(&psde->property_info,
  2966. "lut_ed", 0, PLANE_PROP_SCALER_LUT_ED);
  2967. msm_property_install_blob(&psde->property_info,
  2968. "lut_cir", 0,
  2969. PLANE_PROP_SCALER_LUT_CIR);
  2970. msm_property_install_blob(&psde->property_info,
  2971. "lut_sep", 0,
  2972. PLANE_PROP_SCALER_LUT_SEP);
  2973. } else if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  2974. msm_property_install_range(
  2975. &psde->property_info, "scaler_v2",
  2976. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  2977. msm_property_install_blob(&psde->property_info,
  2978. "lut_sep", 0,
  2979. PLANE_PROP_SCALER_LUT_SEP);
  2980. } else if (psde->features & SDE_SSPP_SCALER) {
  2981. msm_property_install_range(
  2982. &psde->property_info, "scaler_v1", 0x0,
  2983. 0, ~0, 0, PLANE_PROP_SCALER_V1);
  2984. }
  2985. if (psde->features & BIT(SDE_SSPP_CSC) ||
  2986. psde->features & BIT(SDE_SSPP_CSC_10BIT))
  2987. msm_property_install_volatile_range(
  2988. &psde->property_info, "csc_v1", 0x0,
  2989. 0, ~0, 0, PLANE_PROP_CSC_V1);
  2990. if (psde->features & BIT(SDE_SSPP_HSIC)) {
  2991. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2992. "SDE_SSPP_HUE_V",
  2993. psde->pipe_sblk->hsic_blk.version >> 16);
  2994. msm_property_install_range(&psde->property_info,
  2995. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2996. PLANE_PROP_HUE_ADJUST);
  2997. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2998. "SDE_SSPP_SATURATION_V",
  2999. psde->pipe_sblk->hsic_blk.version >> 16);
  3000. msm_property_install_range(&psde->property_info,
  3001. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3002. PLANE_PROP_SATURATION_ADJUST);
  3003. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3004. "SDE_SSPP_VALUE_V",
  3005. psde->pipe_sblk->hsic_blk.version >> 16);
  3006. msm_property_install_range(&psde->property_info,
  3007. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3008. PLANE_PROP_VALUE_ADJUST);
  3009. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3010. "SDE_SSPP_CONTRAST_V",
  3011. psde->pipe_sblk->hsic_blk.version >> 16);
  3012. msm_property_install_range(&psde->property_info,
  3013. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3014. PLANE_PROP_CONTRAST_ADJUST);
  3015. }
  3016. }
  3017. static void _sde_plane_install_colorproc_properties(struct sde_plane *psde,
  3018. struct sde_kms_info *info)
  3019. {
  3020. char feature_name[256];
  3021. bool is_master = !psde->is_virtual;
  3022. if ((is_master &&
  3023. (psde->features & BIT(SDE_SSPP_INVERSE_PMA))) ||
  3024. (psde->features & BIT(SDE_SSPP_DGM_INVERSE_PMA))) {
  3025. msm_property_install_range(&psde->property_info,
  3026. "inverse_pma", 0x0, 0, 1, 0, PLANE_PROP_INVERSE_PMA);
  3027. sde_kms_info_add_keyint(info, "inverse_pma", 1);
  3028. }
  3029. if (psde->features & BIT(SDE_SSPP_DGM_CSC)) {
  3030. msm_property_install_volatile_range(
  3031. &psde->property_info, "csc_dma_v1", 0x0,
  3032. 0, ~0, 0, PLANE_PROP_CSC_DMA_V1);
  3033. sde_kms_info_add_keyint(info, "csc_dma_v1", 1);
  3034. }
  3035. if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
  3036. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3037. "SDE_SSPP_SKIN_COLOR_V",
  3038. psde->pipe_sblk->memcolor_blk.version >> 16);
  3039. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3040. PLANE_PROP_SKIN_COLOR);
  3041. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3042. "SDE_SSPP_SKY_COLOR_V",
  3043. psde->pipe_sblk->memcolor_blk.version >> 16);
  3044. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3045. PLANE_PROP_SKY_COLOR);
  3046. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3047. "SDE_SSPP_FOLIAGE_COLOR_V",
  3048. psde->pipe_sblk->memcolor_blk.version >> 16);
  3049. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3050. PLANE_PROP_FOLIAGE_COLOR);
  3051. }
  3052. if (psde->features & BIT(SDE_SSPP_VIG_GAMUT)) {
  3053. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3054. "SDE_VIG_3D_LUT_GAMUT_V",
  3055. psde->pipe_sblk->gamut_blk.version >> 16);
  3056. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3057. PLANE_PROP_VIG_GAMUT);
  3058. }
  3059. if (psde->features & BIT(SDE_SSPP_VIG_IGC)) {
  3060. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3061. "SDE_VIG_1D_LUT_IGC_V",
  3062. psde->pipe_sblk->igc_blk[0].version >> 16);
  3063. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3064. PLANE_PROP_VIG_IGC);
  3065. }
  3066. if (psde->features & BIT(SDE_SSPP_DMA_IGC)) {
  3067. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3068. "SDE_DGM_1D_LUT_IGC_V",
  3069. psde->pipe_sblk->igc_blk[0].version >> 16);
  3070. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3071. PLANE_PROP_DMA_IGC);
  3072. }
  3073. if (psde->features & BIT(SDE_SSPP_DMA_GC)) {
  3074. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3075. "SDE_DGM_1D_LUT_GC_V",
  3076. psde->pipe_sblk->gc_blk[0].version >> 16);
  3077. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3078. PLANE_PROP_DMA_GC);
  3079. }
  3080. if (psde->features & BIT(SDE_SSPP_FP16_IGC)) {
  3081. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3082. "SDE_SSPP_FP16_IGC_V",
  3083. psde->pipe_sblk->fp16_igc_blk[0].version >> 16);
  3084. msm_property_install_range(&psde->property_info, feature_name,
  3085. 0x0, 0, 1, 0, PLANE_PROP_FP16_IGC);
  3086. }
  3087. if (psde->features & BIT(SDE_SSPP_FP16_GC)) {
  3088. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3089. "SDE_SSPP_FP16_GC_V",
  3090. psde->pipe_sblk->fp16_gc_blk[0].version >> 16);
  3091. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3092. PLANE_PROP_FP16_GC);
  3093. }
  3094. if (psde->features & BIT(SDE_SSPP_FP16_CSC)) {
  3095. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3096. "SDE_SSPP_FP16_CSC_V",
  3097. psde->pipe_sblk->fp16_csc_blk[0].version >> 16);
  3098. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3099. PLANE_PROP_FP16_CSC);
  3100. }
  3101. if (psde->features & BIT(SDE_SSPP_FP16_UNMULT)) {
  3102. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3103. "SDE_SSPP_FP16_UNMULT_V",
  3104. psde->pipe_sblk->fp16_unmult_blk[0].version >> 16);
  3105. msm_property_install_range(&psde->property_info, feature_name,
  3106. 0x0, 0, 1, 0, PLANE_PROP_FP16_UNMULT);
  3107. }
  3108. }
  3109. static void _sde_plane_setup_capabilities_blob(struct sde_plane *psde,
  3110. u32 master_plane_id, struct sde_kms_info *info,
  3111. struct sde_mdss_cfg *catalog)
  3112. {
  3113. bool is_master = !psde->is_virtual;
  3114. const struct sde_format_extended *format_list;
  3115. u32 index;
  3116. int pipe_id;
  3117. if (is_master) {
  3118. format_list = psde->pipe_sblk->format_list;
  3119. } else {
  3120. format_list = psde->pipe_sblk->virt_format_list;
  3121. sde_kms_info_add_keyint(info, "primary_smart_plane_id",
  3122. master_plane_id);
  3123. }
  3124. if (format_list) {
  3125. sde_kms_info_start(info, "pixel_formats");
  3126. while (format_list->fourcc_format) {
  3127. sde_kms_info_append_format(info,
  3128. format_list->fourcc_format,
  3129. format_list->modifier);
  3130. ++format_list;
  3131. }
  3132. sde_kms_info_stop(info);
  3133. }
  3134. if (psde->pipe_hw && catalog->qseed_hw_version)
  3135. sde_kms_info_add_keyint(info, "scaler_step_ver",
  3136. catalog->qseed_hw_version);
  3137. sde_kms_info_add_keyint(info, "max_linewidth",
  3138. psde->pipe_sblk->maxlinewidth);
  3139. sde_kms_info_add_keyint(info, "max_upscale",
  3140. psde->pipe_sblk->maxupscale);
  3141. sde_kms_info_add_keyint(info, "max_downscale",
  3142. psde->pipe_sblk->maxdwnscale);
  3143. sde_kms_info_add_keyint(info, "max_horizontal_deci",
  3144. psde->pipe_sblk->maxhdeciexp);
  3145. sde_kms_info_add_keyint(info, "max_vertical_deci",
  3146. psde->pipe_sblk->maxvdeciexp);
  3147. sde_kms_info_add_keyint(info, "max_per_pipe_bw",
  3148. psde->pipe_sblk->max_per_pipe_bw * 1000LL);
  3149. sde_kms_info_add_keyint(info, "max_per_pipe_bw_high",
  3150. psde->pipe_sblk->max_per_pipe_bw_high * 1000LL);
  3151. if (psde->pipe <= SSPP_VIG3 && psde->pipe >= SSPP_VIG0)
  3152. pipe_id = psde->pipe - SSPP_VIG0;
  3153. else if (psde->pipe <= SSPP_RGB3 && psde->pipe >= SSPP_RGB0)
  3154. pipe_id = psde->pipe - SSPP_RGB0;
  3155. else if (psde->pipe <= SSPP_DMA3 && psde->pipe >= SSPP_DMA0)
  3156. pipe_id = psde->pipe - SSPP_DMA0;
  3157. else
  3158. pipe_id = -1;
  3159. sde_kms_info_add_keyint(info, "pipe_idx", pipe_id);
  3160. index = (master_plane_id == 0) ? 0 : 1;
  3161. if (catalog->has_demura &&
  3162. catalog->demura_supported[psde->pipe][index] != ~0x0)
  3163. sde_kms_info_add_keyint(info, "demura_block", index);
  3164. if (psde->features & BIT(SDE_SSPP_SEC_UI_ALLOWED))
  3165. sde_kms_info_add_keyint(info, "sec_ui_allowed", 1);
  3166. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  3167. sde_kms_info_add_keyint(info, "block_sec_ui", 1);
  3168. if (psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3169. const struct sde_format_extended *inline_rot_fmt_list;
  3170. sde_kms_info_add_keyint(info, "true_inline_rot_rev",
  3171. catalog->true_inline_rot_rev);
  3172. sde_kms_info_add_keyint(info,
  3173. "true_inline_dwnscale_rt",
  3174. (int) (psde->pipe_sblk->in_rot_maxdwnscale_rt_num /
  3175. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom));
  3176. sde_kms_info_add_keyint(info,
  3177. "true_inline_dwnscale_rt_numerator",
  3178. psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3179. sde_kms_info_add_keyint(info,
  3180. "true_inline_dwnscale_rt_denominator",
  3181. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3182. sde_kms_info_add_keyint(info, "true_inline_dwnscale_nrt",
  3183. psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3184. sde_kms_info_add_keyint(info, "true_inline_max_height",
  3185. psde->pipe_sblk->in_rot_maxheight);
  3186. inline_rot_fmt_list = psde->pipe_sblk->in_rot_format_list;
  3187. if (inline_rot_fmt_list) {
  3188. sde_kms_info_start(info, "inline_rot_pixel_formats");
  3189. while (inline_rot_fmt_list->fourcc_format) {
  3190. sde_kms_info_append_format(info,
  3191. inline_rot_fmt_list->fourcc_format,
  3192. inline_rot_fmt_list->modifier);
  3193. ++inline_rot_fmt_list;
  3194. }
  3195. sde_kms_info_stop(info);
  3196. }
  3197. }
  3198. }
  3199. /* helper to install properties which are common to planes and crtcs */
  3200. static void _sde_plane_install_properties(struct drm_plane *plane,
  3201. struct sde_mdss_cfg *catalog, u32 master_plane_id)
  3202. {
  3203. static const struct drm_prop_enum_list e_blend_op[] = {
  3204. {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
  3205. {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
  3206. {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
  3207. {SDE_DRM_BLEND_OP_COVERAGE, "coverage"},
  3208. {SDE_DRM_BLEND_OP_SKIP, "skip_blending"},
  3209. };
  3210. static const struct drm_prop_enum_list e_src_config[] = {
  3211. {SDE_DRM_DEINTERLACE, "deinterlace"}
  3212. };
  3213. static const struct drm_prop_enum_list e_fb_translation_mode[] = {
  3214. {SDE_DRM_FB_NON_SEC, "non_sec"},
  3215. {SDE_DRM_FB_SEC, "sec"},
  3216. {SDE_DRM_FB_NON_SEC_DIR_TRANS, "non_sec_direct_translation"},
  3217. {SDE_DRM_FB_SEC_DIR_TRANS, "sec_direct_translation"},
  3218. };
  3219. static const struct drm_prop_enum_list e_multirect_mode[] = {
  3220. {SDE_SSPP_MULTIRECT_NONE, "none"},
  3221. {SDE_SSPP_MULTIRECT_PARALLEL, "parallel"},
  3222. {SDE_SSPP_MULTIRECT_TIME_MX, "serial"},
  3223. };
  3224. struct sde_kms_info *info;
  3225. struct sde_plane *psde = to_sde_plane(plane);
  3226. bool is_master;
  3227. int zpos_max = 255;
  3228. int zpos_def = 0;
  3229. if (!plane || !psde) {
  3230. SDE_ERROR("invalid plane\n");
  3231. return;
  3232. } else if (!psde->pipe_hw || !psde->pipe_sblk) {
  3233. SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
  3234. !psde->pipe_hw, !psde->pipe_sblk);
  3235. return;
  3236. } else if (!catalog) {
  3237. SDE_ERROR("invalid catalog\n");
  3238. return;
  3239. }
  3240. psde->catalog = catalog;
  3241. is_master = !psde->is_virtual;
  3242. info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
  3243. if (!info) {
  3244. SDE_ERROR("failed to allocate info memory\n");
  3245. return;
  3246. }
  3247. if (sde_is_custom_client()) {
  3248. if (catalog->mixer_count &&
  3249. catalog->mixer[0].sblk->maxblendstages) {
  3250. zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
  3251. if (catalog->has_base_layer &&
  3252. (zpos_max > SDE_STAGE_MAX - 1))
  3253. zpos_max = SDE_STAGE_MAX - 1;
  3254. else if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)
  3255. zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1;
  3256. }
  3257. } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
  3258. /* reserve zpos == 0 for primary planes */
  3259. zpos_def = drm_plane_index(plane) + 1;
  3260. }
  3261. msm_property_install_range(&psde->property_info, "zpos",
  3262. 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
  3263. msm_property_install_range(&psde->property_info, "alpha",
  3264. 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
  3265. /* linux default file descriptor range on each process */
  3266. msm_property_install_range(&psde->property_info, "input_fence",
  3267. 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
  3268. if (is_master)
  3269. _sde_plane_install_master_only_properties(psde);
  3270. else
  3271. msm_property_install_enum(&psde->property_info,
  3272. "multirect_mode", 0x0, 0, e_multirect_mode,
  3273. ARRAY_SIZE(e_multirect_mode), 0,
  3274. PLANE_PROP_MULTIRECT_MODE);
  3275. if (psde->features & BIT(SDE_SSPP_EXCL_RECT))
  3276. msm_property_install_volatile_range(&psde->property_info,
  3277. "excl_rect_v1", 0x0, 0, ~0, 0, PLANE_PROP_EXCL_RECT_V1);
  3278. sde_plane_rot_install_properties(plane, catalog);
  3279. msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
  3280. e_blend_op, ARRAY_SIZE(e_blend_op), 0, PLANE_PROP_BLEND_OP);
  3281. msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
  3282. e_src_config, ARRAY_SIZE(e_src_config), 0,
  3283. PLANE_PROP_SRC_CONFIG);
  3284. if (psde->pipe_hw->ops.setup_solidfill)
  3285. msm_property_install_range(&psde->property_info, "color_fill",
  3286. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
  3287. msm_property_install_range(&psde->property_info, "prefill_size", 0x0,
  3288. 0, ~0, 0, PLANE_PROP_PREFILL_SIZE);
  3289. msm_property_install_range(&psde->property_info, "prefill_time", 0x0,
  3290. 0, ~0, 0, PLANE_PROP_PREFILL_TIME);
  3291. msm_property_install_blob(&psde->property_info, "capabilities",
  3292. DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
  3293. sde_kms_info_reset(info);
  3294. _sde_plane_setup_capabilities_blob(psde, master_plane_id, info,
  3295. catalog);
  3296. _sde_plane_install_colorproc_properties(psde, info);
  3297. msm_property_set_blob(&psde->property_info, &psde->blob_info,
  3298. info->data, SDE_KMS_INFO_DATALEN(info),
  3299. PLANE_PROP_INFO);
  3300. msm_property_install_enum(&psde->property_info, "fb_translation_mode",
  3301. 0x0, 0, e_fb_translation_mode,
  3302. ARRAY_SIZE(e_fb_translation_mode), 0,
  3303. PLANE_PROP_FB_TRANSLATION_MODE);
  3304. kfree(info);
  3305. }
  3306. static inline void _sde_plane_set_csc_v1(struct sde_plane *psde,
  3307. void __user *usr_ptr)
  3308. {
  3309. struct sde_drm_csc_v1 csc_v1;
  3310. int i;
  3311. if (!psde) {
  3312. SDE_ERROR("invalid plane\n");
  3313. return;
  3314. }
  3315. psde->csc_usr_ptr = NULL;
  3316. if (!usr_ptr) {
  3317. SDE_DEBUG_PLANE(psde, "csc data removed\n");
  3318. return;
  3319. }
  3320. if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
  3321. SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
  3322. return;
  3323. }
  3324. /* populate from user space */
  3325. for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
  3326. psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
  3327. for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
  3328. psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
  3329. psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
  3330. }
  3331. for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
  3332. psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
  3333. psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
  3334. }
  3335. psde->csc_usr_ptr = &psde->csc_cfg;
  3336. }
  3337. static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde,
  3338. struct sde_plane_state *pstate, void __user *usr)
  3339. {
  3340. struct sde_drm_scaler_v1 scale_v1;
  3341. struct sde_hw_pixel_ext *pe;
  3342. int i;
  3343. if (!psde || !pstate) {
  3344. SDE_ERROR("invalid argument(s)\n");
  3345. return;
  3346. }
  3347. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3348. if (!usr) {
  3349. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3350. return;
  3351. }
  3352. if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
  3353. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3354. return;
  3355. }
  3356. /* force property to be dirty, even if the pointer didn't change */
  3357. msm_property_set_dirty(&psde->property_info,
  3358. &pstate->property_state, PLANE_PROP_SCALER_V1);
  3359. /* populate from user space */
  3360. pe = &pstate->pixel_ext;
  3361. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3362. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3363. pe->init_phase_x[i] = scale_v1.init_phase_x[i];
  3364. pe->phase_step_x[i] = scale_v1.phase_step_x[i];
  3365. pe->init_phase_y[i] = scale_v1.init_phase_y[i];
  3366. pe->phase_step_y[i] = scale_v1.phase_step_y[i];
  3367. pe->horz_filter[i] = scale_v1.horz_filter[i];
  3368. pe->vert_filter[i] = scale_v1.vert_filter[i];
  3369. }
  3370. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3371. pe->left_ftch[i] = scale_v1.pe.left_ftch[i];
  3372. pe->right_ftch[i] = scale_v1.pe.right_ftch[i];
  3373. pe->left_rpt[i] = scale_v1.pe.left_rpt[i];
  3374. pe->right_rpt[i] = scale_v1.pe.right_rpt[i];
  3375. pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i];
  3376. pe->top_ftch[i] = scale_v1.pe.top_ftch[i];
  3377. pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i];
  3378. pe->top_rpt[i] = scale_v1.pe.top_rpt[i];
  3379. pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i];
  3380. pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i];
  3381. }
  3382. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V1;
  3383. SDE_EVT32_VERBOSE(DRMID(&psde->base));
  3384. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3385. }
  3386. static void _sde_plane_clear_predownscale_settings(
  3387. struct sde_plane_state *pstate)
  3388. {
  3389. pstate->pre_down.pre_downscale_x_0 = 0;
  3390. pstate->pre_down.pre_downscale_x_1 = 0;
  3391. pstate->pre_down.pre_downscale_y_0 = 0;
  3392. pstate->pre_down.pre_downscale_y_1 = 0;
  3393. }
  3394. static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
  3395. struct sde_plane_state *pstate, void __user *usr)
  3396. {
  3397. struct sde_drm_scaler_v2 scale_v2;
  3398. struct sde_hw_pixel_ext *pe;
  3399. int i;
  3400. struct sde_hw_scaler3_cfg *cfg;
  3401. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  3402. if (!psde || !pstate) {
  3403. SDE_ERROR("invalid argument(s)\n");
  3404. return;
  3405. }
  3406. cfg = &pstate->scaler3_cfg;
  3407. pd_cfg = &pstate->pre_down;
  3408. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3409. if (!usr) {
  3410. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3411. cfg->enable = 0;
  3412. _sde_plane_clear_predownscale_settings(pstate);
  3413. goto end;
  3414. }
  3415. if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
  3416. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3417. return;
  3418. }
  3419. /* detach/ignore user data if 'disabled' */
  3420. if (!scale_v2.enable) {
  3421. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3422. cfg->enable = 0;
  3423. _sde_plane_clear_predownscale_settings(pstate);
  3424. goto end;
  3425. }
  3426. /* populate from user space */
  3427. sde_set_scaler_v2(cfg, &scale_v2);
  3428. if (_sde_plane_has_pre_downscale(psde)) {
  3429. pd_cfg->pre_downscale_x_0 = scale_v2.pre_downscale_x_0;
  3430. pd_cfg->pre_downscale_x_1 = scale_v2.pre_downscale_x_1;
  3431. pd_cfg->pre_downscale_y_0 = scale_v2.pre_downscale_y_0;
  3432. pd_cfg->pre_downscale_y_1 = scale_v2.pre_downscale_y_1;
  3433. }
  3434. pe = &pstate->pixel_ext;
  3435. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3436. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3437. pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
  3438. pe->right_ftch[i] = scale_v2.pe.right_ftch[i];
  3439. pe->left_rpt[i] = scale_v2.pe.left_rpt[i];
  3440. pe->right_rpt[i] = scale_v2.pe.right_rpt[i];
  3441. pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i];
  3442. pe->top_ftch[i] = scale_v2.pe.top_ftch[i];
  3443. pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i];
  3444. pe->top_rpt[i] = scale_v2.pe.top_rpt[i];
  3445. pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i];
  3446. pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i];
  3447. }
  3448. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2_CHECK;
  3449. end:
  3450. /* force property to be dirty, even if the pointer didn't change */
  3451. msm_property_set_dirty(&psde->property_info,
  3452. &pstate->property_state, PLANE_PROP_SCALER_V2);
  3453. SDE_EVT32_VERBOSE(DRMID(&psde->base), cfg->enable, cfg->de.enable,
  3454. cfg->src_width[0], cfg->src_height[0],
  3455. cfg->dst_width, cfg->dst_height);
  3456. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3457. }
  3458. static void _sde_plane_set_excl_rect_v1(struct sde_plane *psde,
  3459. struct sde_plane_state *pstate, void __user *usr_ptr)
  3460. {
  3461. struct drm_clip_rect excl_rect_v1;
  3462. if (!psde || !pstate) {
  3463. SDE_ERROR("invalid argument(s)\n");
  3464. return;
  3465. }
  3466. if (!usr_ptr) {
  3467. memset(&pstate->excl_rect, 0, sizeof(pstate->excl_rect));
  3468. SDE_DEBUG_PLANE(psde, "excl_rect data cleared\n");
  3469. return;
  3470. }
  3471. if (copy_from_user(&excl_rect_v1, usr_ptr, sizeof(excl_rect_v1))) {
  3472. SDE_ERROR_PLANE(psde, "failed to copy excl_rect data\n");
  3473. return;
  3474. }
  3475. /* populate from user space */
  3476. pstate->excl_rect.x = excl_rect_v1.x1;
  3477. pstate->excl_rect.y = excl_rect_v1.y1;
  3478. pstate->excl_rect.w = excl_rect_v1.x2 - excl_rect_v1.x1;
  3479. pstate->excl_rect.h = excl_rect_v1.y2 - excl_rect_v1.y1;
  3480. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  3481. pstate->excl_rect.x, pstate->excl_rect.y,
  3482. pstate->excl_rect.w, pstate->excl_rect.h);
  3483. }
  3484. static int sde_plane_atomic_set_property(struct drm_plane *plane,
  3485. struct drm_plane_state *state, struct drm_property *property,
  3486. uint64_t val)
  3487. {
  3488. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3489. struct sde_plane_state *pstate;
  3490. int idx, ret = -EINVAL;
  3491. SDE_DEBUG_PLANE(psde, "\n");
  3492. if (!plane) {
  3493. SDE_ERROR("invalid plane\n");
  3494. } else if (!state) {
  3495. SDE_ERROR_PLANE(psde, "invalid state\n");
  3496. } else {
  3497. pstate = to_sde_plane_state(state);
  3498. ret = msm_property_atomic_set(&psde->property_info,
  3499. &pstate->property_state, property, val);
  3500. if (!ret) {
  3501. idx = msm_property_index(&psde->property_info,
  3502. property);
  3503. switch (idx) {
  3504. case PLANE_PROP_INPUT_FENCE:
  3505. _sde_plane_set_input_fence(psde, pstate, val);
  3506. break;
  3507. case PLANE_PROP_CSC_V1:
  3508. case PLANE_PROP_CSC_DMA_V1:
  3509. _sde_plane_set_csc_v1(psde, (void __user *)val);
  3510. break;
  3511. case PLANE_PROP_SCALER_V1:
  3512. _sde_plane_set_scaler_v1(psde, pstate,
  3513. (void *)(uintptr_t)val);
  3514. break;
  3515. case PLANE_PROP_SCALER_V2:
  3516. _sde_plane_set_scaler_v2(psde, pstate,
  3517. (void *)(uintptr_t)val);
  3518. break;
  3519. case PLANE_PROP_EXCL_RECT_V1:
  3520. _sde_plane_set_excl_rect_v1(psde, pstate,
  3521. (void *)(uintptr_t)val);
  3522. break;
  3523. default:
  3524. /* nothing to do */
  3525. break;
  3526. }
  3527. }
  3528. }
  3529. SDE_DEBUG_PLANE(psde, "%s[%d] <= 0x%llx ret=%d\n",
  3530. property->name, property->base.id, val, ret);
  3531. return ret;
  3532. }
  3533. static int sde_plane_atomic_get_property(struct drm_plane *plane,
  3534. const struct drm_plane_state *state,
  3535. struct drm_property *property, uint64_t *val)
  3536. {
  3537. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3538. struct sde_plane_state *pstate;
  3539. int ret = -EINVAL;
  3540. if (!plane) {
  3541. SDE_ERROR("invalid plane\n");
  3542. } else if (!state) {
  3543. SDE_ERROR("invalid state\n");
  3544. } else {
  3545. SDE_DEBUG_PLANE(psde, "\n");
  3546. pstate = to_sde_plane_state(state);
  3547. ret = msm_property_atomic_get(&psde->property_info,
  3548. &pstate->property_state, property, val);
  3549. }
  3550. return ret;
  3551. }
  3552. int sde_plane_helper_reset_custom_properties(struct drm_plane *plane,
  3553. struct drm_plane_state *plane_state)
  3554. {
  3555. struct sde_plane *psde;
  3556. struct sde_plane_state *pstate;
  3557. struct drm_property *drm_prop;
  3558. enum msm_mdp_plane_property prop_idx;
  3559. if (!plane || !plane_state) {
  3560. SDE_ERROR("invalid params\n");
  3561. return -EINVAL;
  3562. }
  3563. psde = to_sde_plane(plane);
  3564. pstate = to_sde_plane_state(plane_state);
  3565. for (prop_idx = 0; prop_idx < PLANE_PROP_COUNT; prop_idx++) {
  3566. uint64_t val = pstate->property_values[prop_idx].value;
  3567. uint64_t def;
  3568. int ret;
  3569. drm_prop = msm_property_index_to_drm_property(
  3570. &psde->property_info, prop_idx);
  3571. if (!drm_prop) {
  3572. /* not all props will be installed, based on caps */
  3573. SDE_DEBUG_PLANE(psde, "invalid property index %d\n",
  3574. prop_idx);
  3575. continue;
  3576. }
  3577. def = msm_property_get_default(&psde->property_info, prop_idx);
  3578. if (val == def)
  3579. continue;
  3580. SDE_DEBUG_PLANE(psde, "set prop %s idx %d from %llu to %llu\n",
  3581. drm_prop->name, prop_idx, val, def);
  3582. ret = sde_plane_atomic_set_property(plane, plane_state,
  3583. drm_prop, def);
  3584. if (ret) {
  3585. SDE_ERROR_PLANE(psde,
  3586. "set property failed, idx %d ret %d\n",
  3587. prop_idx, ret);
  3588. continue;
  3589. }
  3590. }
  3591. return 0;
  3592. }
  3593. static void sde_plane_destroy(struct drm_plane *plane)
  3594. {
  3595. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3596. SDE_DEBUG_PLANE(psde, "\n");
  3597. if (psde) {
  3598. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  3599. if (psde->blob_info)
  3600. drm_property_blob_put(psde->blob_info);
  3601. msm_property_destroy(&psde->property_info);
  3602. mutex_destroy(&psde->lock);
  3603. /* this will destroy the states as well */
  3604. drm_plane_cleanup(plane);
  3605. if (psde->pipe_hw)
  3606. sde_hw_sspp_destroy(psde->pipe_hw);
  3607. kfree(psde);
  3608. }
  3609. }
  3610. void sde_plane_destroy_fb(struct drm_plane_state *state)
  3611. {
  3612. struct sde_plane_state *pstate;
  3613. if (!state) {
  3614. SDE_ERROR("invalid arg state %d\n", !state);
  3615. return;
  3616. }
  3617. pstate = to_sde_plane_state(state);
  3618. if (sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE) ==
  3619. SDE_DRM_FB_SEC) {
  3620. /* remove ref count for frame buffers */
  3621. if (state->fb) {
  3622. drm_framebuffer_put(state->fb);
  3623. state->fb = NULL;
  3624. }
  3625. }
  3626. }
  3627. static void sde_plane_destroy_state(struct drm_plane *plane,
  3628. struct drm_plane_state *state)
  3629. {
  3630. struct sde_plane *psde;
  3631. struct sde_plane_state *pstate;
  3632. if (!plane || !state) {
  3633. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  3634. !plane, !state);
  3635. return;
  3636. }
  3637. psde = to_sde_plane(plane);
  3638. pstate = to_sde_plane_state(state);
  3639. SDE_DEBUG_PLANE(psde, "\n");
  3640. /* remove ref count for frame buffers */
  3641. if (state->fb)
  3642. drm_framebuffer_put(state->fb);
  3643. /* remove ref count for fence */
  3644. if (pstate->input_fence)
  3645. sde_sync_put(pstate->input_fence);
  3646. pstate->input_fence = 0;
  3647. /* destroy value helper */
  3648. msm_property_destroy_state(&psde->property_info, pstate,
  3649. &pstate->property_state);
  3650. }
  3651. static struct drm_plane_state *
  3652. sde_plane_duplicate_state(struct drm_plane *plane)
  3653. {
  3654. struct sde_plane *psde;
  3655. struct sde_plane_state *pstate;
  3656. struct sde_plane_state *old_state;
  3657. struct drm_property *drm_prop;
  3658. uint64_t input_fence_default;
  3659. if (!plane) {
  3660. SDE_ERROR("invalid plane\n");
  3661. return NULL;
  3662. } else if (!plane->state) {
  3663. SDE_ERROR("invalid plane state\n");
  3664. return NULL;
  3665. }
  3666. old_state = to_sde_plane_state(plane->state);
  3667. psde = to_sde_plane(plane);
  3668. if (old_state->cont_splash_populated) {
  3669. plane->state->crtc = NULL;
  3670. old_state->cont_splash_populated = false;
  3671. }
  3672. pstate = msm_property_alloc_state(&psde->property_info);
  3673. if (!pstate) {
  3674. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3675. return NULL;
  3676. }
  3677. SDE_DEBUG_PLANE(psde, "\n");
  3678. /* duplicate value helper */
  3679. msm_property_duplicate_state(&psde->property_info, old_state, pstate,
  3680. &pstate->property_state, pstate->property_values);
  3681. /* clear out any input fence */
  3682. pstate->input_fence = 0;
  3683. input_fence_default = msm_property_get_default(
  3684. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3685. drm_prop = msm_property_index_to_drm_property(
  3686. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3687. if (msm_property_atomic_set(&psde->property_info,
  3688. &pstate->property_state, drm_prop,
  3689. input_fence_default))
  3690. SDE_DEBUG_PLANE(psde,
  3691. "error clearing duplicated input fence\n");
  3692. pstate->dirty = 0x0;
  3693. pstate->pending = false;
  3694. __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
  3695. /* reset layout offset */
  3696. if (pstate->layout_offset) {
  3697. if (pstate->layout_offset > 0)
  3698. pstate->base.crtc_x += pstate->layout_offset;
  3699. pstate->layout = SDE_LAYOUT_NONE;
  3700. pstate->layout_offset = 0;
  3701. }
  3702. return &pstate->base;
  3703. }
  3704. static void sde_plane_reset(struct drm_plane *plane)
  3705. {
  3706. struct sde_plane *psde;
  3707. struct sde_plane_state *pstate;
  3708. if (!plane) {
  3709. SDE_ERROR("invalid plane\n");
  3710. return;
  3711. }
  3712. psde = to_sde_plane(plane);
  3713. SDE_DEBUG_PLANE(psde, "\n");
  3714. if (plane->state && !sde_crtc_is_reset_required(plane->state->crtc)) {
  3715. SDE_DEBUG_PLANE(psde, "avoid reset for plane\n");
  3716. return;
  3717. }
  3718. /* remove previous state, if present */
  3719. if (plane->state) {
  3720. sde_plane_destroy_state(plane, plane->state);
  3721. plane->state = 0;
  3722. }
  3723. pstate = msm_property_alloc_state(&psde->property_info);
  3724. if (!pstate) {
  3725. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3726. return;
  3727. }
  3728. /* reset value helper */
  3729. msm_property_reset_state(&psde->property_info, pstate,
  3730. &pstate->property_state,
  3731. pstate->property_values);
  3732. pstate->base.plane = plane;
  3733. plane->state = &pstate->base;
  3734. }
  3735. u32 sde_plane_get_ubwc_error(struct drm_plane *plane)
  3736. {
  3737. u32 ubwc_error = 0;
  3738. struct sde_plane *psde;
  3739. struct sde_plane_state *pstate;
  3740. if (!plane) {
  3741. SDE_ERROR("invalid plane\n");
  3742. return 0;
  3743. }
  3744. psde = to_sde_plane(plane);
  3745. pstate = to_sde_plane_state(plane->state);
  3746. if (!psde->is_virtual && psde->pipe_hw->ops.get_ubwc_error)
  3747. ubwc_error = psde->pipe_hw->ops.get_ubwc_error(psde->pipe_hw,
  3748. pstate->multirect_index);
  3749. return ubwc_error;
  3750. }
  3751. void sde_plane_clear_ubwc_error(struct drm_plane *plane)
  3752. {
  3753. struct sde_plane *psde;
  3754. struct sde_plane_state *pstate;
  3755. if (!plane) {
  3756. SDE_ERROR("invalid plane\n");
  3757. return;
  3758. }
  3759. psde = to_sde_plane(plane);
  3760. pstate = to_sde_plane_state(plane->state);
  3761. if (psde->pipe_hw->ops.clear_ubwc_error)
  3762. psde->pipe_hw->ops.clear_ubwc_error(psde->pipe_hw, pstate->multirect_index);
  3763. }
  3764. u32 sde_plane_get_meta_error(struct drm_plane *plane)
  3765. {
  3766. u32 meta_error = 0;
  3767. struct sde_plane *psde;
  3768. struct sde_plane_state *pstate;
  3769. if (!plane) {
  3770. SDE_ERROR("invalid plane\n");
  3771. return 0;
  3772. }
  3773. psde = to_sde_plane(plane);
  3774. pstate = to_sde_plane_state(plane->state);
  3775. if (psde->pipe_hw->ops.get_meta_error)
  3776. meta_error = psde->pipe_hw->ops.get_meta_error(psde->pipe_hw,
  3777. pstate->multirect_index);
  3778. return meta_error;
  3779. }
  3780. void sde_plane_clear_meta_error(struct drm_plane *plane)
  3781. {
  3782. struct sde_plane *psde;
  3783. struct sde_plane_state *pstate;
  3784. if (!plane) {
  3785. SDE_ERROR("invalid plane\n");
  3786. return;
  3787. }
  3788. psde = to_sde_plane(plane);
  3789. pstate = to_sde_plane_state(plane->state);
  3790. if (psde->pipe_hw->ops.clear_meta_error)
  3791. psde->pipe_hw->ops.clear_meta_error(psde->pipe_hw, pstate->multirect_index);
  3792. }
  3793. #ifdef CONFIG_DEBUG_FS
  3794. static ssize_t _sde_plane_danger_read(struct file *file,
  3795. char __user *buff, size_t count, loff_t *ppos)
  3796. {
  3797. struct sde_kms *kms = file->private_data;
  3798. struct sde_mdss_cfg *cfg = kms->catalog;
  3799. int len = 0;
  3800. char buf[40] = {'\0'};
  3801. if (!cfg)
  3802. return -ENODEV;
  3803. if (*ppos)
  3804. return 0; /* the end */
  3805. len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
  3806. if (len < 0 || len >= sizeof(buf))
  3807. return 0;
  3808. if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
  3809. return -EFAULT;
  3810. *ppos += len; /* increase offset */
  3811. return len;
  3812. }
  3813. static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable)
  3814. {
  3815. struct drm_plane *plane;
  3816. drm_for_each_plane(plane, kms->dev) {
  3817. if (plane->fb && plane->state) {
  3818. sde_plane_danger_signal_ctrl(plane, enable);
  3819. SDE_DEBUG("plane:%d img:%dx%d ",
  3820. plane->base.id, plane->fb->width,
  3821. plane->fb->height);
  3822. SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
  3823. plane->state->src_x >> 16,
  3824. plane->state->src_y >> 16,
  3825. plane->state->src_w >> 16,
  3826. plane->state->src_h >> 16,
  3827. plane->state->crtc_x, plane->state->crtc_y,
  3828. plane->state->crtc_w, plane->state->crtc_h);
  3829. } else {
  3830. SDE_DEBUG("Inactive plane:%d\n", plane->base.id);
  3831. }
  3832. }
  3833. }
  3834. static ssize_t _sde_plane_danger_write(struct file *file,
  3835. const char __user *user_buf, size_t count, loff_t *ppos)
  3836. {
  3837. struct sde_kms *kms = file->private_data;
  3838. struct sde_mdss_cfg *cfg = kms->catalog;
  3839. int disable_panic;
  3840. char buf[10];
  3841. if (!cfg)
  3842. return -EFAULT;
  3843. if (count >= sizeof(buf))
  3844. return -EFAULT;
  3845. if (copy_from_user(buf, user_buf, count))
  3846. return -EFAULT;
  3847. buf[count] = 0; /* end of string */
  3848. if (kstrtoint(buf, 0, &disable_panic))
  3849. return -EFAULT;
  3850. if (disable_panic) {
  3851. /* Disable panic signal for all active pipes */
  3852. SDE_DEBUG("Disabling danger:\n");
  3853. _sde_plane_set_danger_state(kms, false);
  3854. kms->has_danger_ctrl = false;
  3855. } else {
  3856. /* Enable panic signal for all active pipes */
  3857. SDE_DEBUG("Enabling danger:\n");
  3858. kms->has_danger_ctrl = true;
  3859. _sde_plane_set_danger_state(kms, true);
  3860. }
  3861. return count;
  3862. }
  3863. static const struct file_operations sde_plane_danger_enable = {
  3864. .open = simple_open,
  3865. .read = _sde_plane_danger_read,
  3866. .write = _sde_plane_danger_write,
  3867. };
  3868. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3869. {
  3870. struct sde_plane *psde;
  3871. struct sde_kms *kms;
  3872. struct msm_drm_private *priv;
  3873. const struct sde_sspp_sub_blks *sblk = 0;
  3874. const struct sde_sspp_cfg *cfg = 0;
  3875. if (!plane || !plane->dev) {
  3876. SDE_ERROR("invalid arguments\n");
  3877. return -EINVAL;
  3878. }
  3879. priv = plane->dev->dev_private;
  3880. if (!priv || !priv->kms) {
  3881. SDE_ERROR("invalid KMS reference\n");
  3882. return -EINVAL;
  3883. }
  3884. kms = to_sde_kms(priv->kms);
  3885. psde = to_sde_plane(plane);
  3886. if (psde && psde->pipe_hw)
  3887. cfg = psde->pipe_hw->cap;
  3888. if (cfg)
  3889. sblk = cfg->sblk;
  3890. if (!sblk)
  3891. return 0;
  3892. /* create overall sub-directory for the pipe */
  3893. psde->debugfs_root =
  3894. debugfs_create_dir(psde->pipe_name,
  3895. plane->dev->primary->debugfs_root);
  3896. if (!psde->debugfs_root)
  3897. return -ENOMEM;
  3898. /* don't error check these */
  3899. debugfs_create_x64("features", 0400,
  3900. psde->debugfs_root, &psde->features);
  3901. if (cfg->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  3902. cfg->features & BIT(SDE_SSPP_SCALER_QSEED3LITE) ||
  3903. cfg->features & BIT(SDE_SSPP_SCALER_QSEED2))
  3904. debugfs_create_bool("default_scaling",
  3905. 0600,
  3906. psde->debugfs_root,
  3907. &psde->debugfs_default_scale);
  3908. if (cfg->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3909. debugfs_create_u32("in_rot_max_downscale_rt_num",
  3910. 0600,
  3911. psde->debugfs_root,
  3912. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3913. debugfs_create_u32("in_rot_max_downscale_rt_denom",
  3914. 0600,
  3915. psde->debugfs_root,
  3916. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3917. debugfs_create_u32("in_rot_max_downscale_nrt",
  3918. 0600,
  3919. psde->debugfs_root,
  3920. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3921. debugfs_create_u32("in_rot_max_height",
  3922. 0600,
  3923. psde->debugfs_root,
  3924. (u32 *) &psde->pipe_sblk->in_rot_maxheight);
  3925. }
  3926. debugfs_create_u32("xin_id",
  3927. 0400,
  3928. psde->debugfs_root,
  3929. (u32 *) &cfg->xin_id);
  3930. debugfs_create_x32("creq_vblank",
  3931. 0600,
  3932. psde->debugfs_root,
  3933. (u32 *) &sblk->creq_vblank);
  3934. debugfs_create_x32("danger_vblank",
  3935. 0600,
  3936. psde->debugfs_root,
  3937. (u32 *) &sblk->danger_vblank);
  3938. debugfs_create_file("disable_danger",
  3939. 0600,
  3940. psde->debugfs_root,
  3941. kms, &sde_plane_danger_enable);
  3942. return 0;
  3943. }
  3944. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  3945. {
  3946. struct sde_plane *psde;
  3947. if (!plane)
  3948. return;
  3949. psde = to_sde_plane(plane);
  3950. debugfs_remove_recursive(psde->debugfs_root);
  3951. }
  3952. #else
  3953. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3954. {
  3955. return 0;
  3956. }
  3957. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  3958. {
  3959. }
  3960. #endif
  3961. static int sde_plane_late_register(struct drm_plane *plane)
  3962. {
  3963. return _sde_plane_init_debugfs(plane);
  3964. }
  3965. static void sde_plane_early_unregister(struct drm_plane *plane)
  3966. {
  3967. _sde_plane_destroy_debugfs(plane);
  3968. }
  3969. static const struct drm_plane_funcs sde_plane_funcs = {
  3970. .update_plane = drm_atomic_helper_update_plane,
  3971. .disable_plane = drm_atomic_helper_disable_plane,
  3972. .destroy = sde_plane_destroy,
  3973. .atomic_set_property = sde_plane_atomic_set_property,
  3974. .atomic_get_property = sde_plane_atomic_get_property,
  3975. .reset = sde_plane_reset,
  3976. .atomic_duplicate_state = sde_plane_duplicate_state,
  3977. .atomic_destroy_state = sde_plane_destroy_state,
  3978. .late_register = sde_plane_late_register,
  3979. .early_unregister = sde_plane_early_unregister,
  3980. };
  3981. static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
  3982. .prepare_fb = sde_plane_prepare_fb,
  3983. .cleanup_fb = sde_plane_cleanup_fb,
  3984. .atomic_check = sde_plane_atomic_check,
  3985. .atomic_update = sde_plane_atomic_update,
  3986. };
  3987. enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
  3988. {
  3989. return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
  3990. }
  3991. bool is_sde_plane_virtual(struct drm_plane *plane)
  3992. {
  3993. return plane ? to_sde_plane(plane)->is_virtual : false;
  3994. }
  3995. /* initialize plane */
  3996. struct drm_plane *sde_plane_init(struct drm_device *dev,
  3997. uint32_t pipe, bool primary_plane,
  3998. unsigned long possible_crtcs, u32 master_plane_id)
  3999. {
  4000. struct drm_plane *plane = NULL, *master_plane = NULL;
  4001. const struct sde_format_extended *format_list;
  4002. struct sde_plane *psde;
  4003. struct msm_drm_private *priv;
  4004. struct sde_kms *kms;
  4005. enum drm_plane_type type;
  4006. int ret = -EINVAL;
  4007. if (!dev) {
  4008. SDE_ERROR("[%u]device is NULL\n", pipe);
  4009. goto exit;
  4010. }
  4011. priv = dev->dev_private;
  4012. if (!priv) {
  4013. SDE_ERROR("[%u]private data is NULL\n", pipe);
  4014. goto exit;
  4015. }
  4016. if (!priv->kms) {
  4017. SDE_ERROR("[%u]invalid KMS reference\n", pipe);
  4018. goto exit;
  4019. }
  4020. kms = to_sde_kms(priv->kms);
  4021. if (!kms->catalog) {
  4022. SDE_ERROR("[%u]invalid catalog reference\n", pipe);
  4023. goto exit;
  4024. }
  4025. /* create and zero local structure */
  4026. psde = kzalloc(sizeof(*psde), GFP_KERNEL);
  4027. if (!psde) {
  4028. SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
  4029. ret = -ENOMEM;
  4030. goto exit;
  4031. }
  4032. /* cache local stuff for later */
  4033. plane = &psde->base;
  4034. psde->pipe = pipe;
  4035. psde->is_virtual = (master_plane_id != 0);
  4036. INIT_LIST_HEAD(&psde->mplane_list);
  4037. master_plane = drm_plane_find(dev, NULL, master_plane_id);
  4038. if (master_plane) {
  4039. struct sde_plane *mpsde = to_sde_plane(master_plane);
  4040. list_add_tail(&psde->mplane_list, &mpsde->mplane_list);
  4041. }
  4042. /* initialize underlying h/w driver */
  4043. psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog,
  4044. psde->is_virtual);
  4045. if (IS_ERR(psde->pipe_hw)) {
  4046. SDE_ERROR("[%u]SSPP init failed\n", pipe);
  4047. ret = PTR_ERR(psde->pipe_hw);
  4048. goto clean_plane;
  4049. } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
  4050. SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
  4051. goto clean_sspp;
  4052. }
  4053. /* cache features mask for later */
  4054. psde->features = psde->pipe_hw->cap->features_ext;
  4055. psde->perf_features = psde->pipe_hw->cap->perf_features;
  4056. psde->pipe_sblk = psde->pipe_hw->cap->sblk;
  4057. if (!psde->pipe_sblk) {
  4058. SDE_ERROR("[%u]invalid sblk\n", pipe);
  4059. goto clean_sspp;
  4060. }
  4061. if (psde->is_virtual)
  4062. format_list = psde->pipe_sblk->virt_format_list;
  4063. else
  4064. format_list = psde->pipe_sblk->format_list;
  4065. psde->nformats = sde_populate_formats(format_list,
  4066. psde->formats,
  4067. 0,
  4068. ARRAY_SIZE(psde->formats));
  4069. if (!psde->nformats) {
  4070. SDE_ERROR("[%u]no valid formats for plane\n", pipe);
  4071. goto clean_sspp;
  4072. }
  4073. if (psde->features & BIT(SDE_SSPP_CURSOR))
  4074. type = DRM_PLANE_TYPE_CURSOR;
  4075. else if (primary_plane)
  4076. type = DRM_PLANE_TYPE_PRIMARY;
  4077. else
  4078. type = DRM_PLANE_TYPE_OVERLAY;
  4079. ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
  4080. psde->formats, psde->nformats,
  4081. NULL, type, NULL);
  4082. if (ret)
  4083. goto clean_sspp;
  4084. /* Populate static array of plane property flags */
  4085. _sde_plane_map_prop_to_dirty_bits();
  4086. /* success! finalize initialization */
  4087. drm_plane_helper_add(plane, &sde_plane_helper_funcs);
  4088. msm_property_init(&psde->property_info, &plane->base, dev,
  4089. priv->plane_property, psde->property_data,
  4090. PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
  4091. sizeof(struct sde_plane_state));
  4092. _sde_plane_install_properties(plane, kms->catalog, master_plane_id);
  4093. /* save user friendly pipe name for later */
  4094. snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
  4095. mutex_init(&psde->lock);
  4096. SDE_DEBUG("%s created for pipe:%u id:%u master:%u\n", psde->pipe_name,
  4097. pipe, plane->base.id, master_plane_id);
  4098. return plane;
  4099. clean_sspp:
  4100. if (psde && psde->pipe_hw)
  4101. sde_hw_sspp_destroy(psde->pipe_hw);
  4102. clean_plane:
  4103. kfree(psde);
  4104. exit:
  4105. return ERR_PTR(ret);
  4106. }