msm_vidc_internal.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2020, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _MSM_VIDC_INTERNAL_H_
  6. #define _MSM_VIDC_INTERNAL_H_
  7. #include <linux/bits.h>
  8. #include <linux/workqueue.h>
  9. #include <media/v4l2-dev.h>
  10. #include <media/v4l2-device.h>
  11. #include <media/v4l2-ioctl.h>
  12. #include <media/v4l2-event.h>
  13. #include <media/v4l2-ctrls.h>
  14. #include <media/videobuf2-core.h>
  15. #include <media/videobuf2-v4l2.h>
  16. #define MAX_NAME_LENGTH 128
  17. #define MAX_MATRIX_COEFFS 9
  18. #define MAX_BIAS_COEFFS 3
  19. #define MAX_LIMIT_COEFFS 6
  20. #define MAX_DEBUGFS_NAME 50
  21. #define DEFAULT_TIMEOUT 3
  22. #define DEFAULT_HEIGHT 240
  23. #define DEFAULT_WIDTH 320
  24. #define MIN_SUPPORTED_WIDTH 32
  25. #define MIN_SUPPORTED_HEIGHT 32
  26. #define DEFAULT_FPS 30
  27. #define MINIMUM_FPS 1
  28. #define MAXIMUM_FPS 960
  29. #define SINGLE_INPUT_BUFFER 1
  30. #define SINGLE_OUTPUT_BUFFER 1
  31. #define MAX_NUM_INPUT_BUFFERS VIDEO_MAX_FRAME // same as VB2_MAX_FRAME
  32. #define MAX_NUM_OUTPUT_BUFFERS VIDEO_MAX_FRAME // same as VB2_MAX_FRAME
  33. #define MAX_SUPPORTED_INSTANCES 16
  34. #define MAX_BSE_VPP_DELAY 6
  35. #define DEFAULT_BSE_VPP_DELAY 2
  36. #define MAX_CAP_PARENTS 16
  37. #define MAX_CAP_CHILDREN 16
  38. /* Maintains the number of FTB's between each FBD over a window */
  39. #define DCVS_FTB_WINDOW 16
  40. /* Superframe can have maximum of 32 frames */
  41. #define VIDC_SUPERFRAME_MAX 32
  42. #define COLOR_RANGE_UNSPECIFIED (-1)
  43. #define V4L2_EVENT_VIDC_BASE 10
  44. #define INPUT_PLANE V4L2_BUF_TYPE_VIDEO_OUTPUT
  45. #define OUTPUT_PLANE V4L2_BUF_TYPE_VIDEO_CAPTURE
  46. #define INPUT_META_PLANE V4L2_BUF_TYPE_META_OUTPUT
  47. #define OUTPUT_META_PLANE V4L2_BUF_TYPE_META_CAPTURE
  48. #define VIDC_IFACEQ_MAX_PKT_SIZE 1024
  49. #define VIDC_IFACEQ_MED_PKT_SIZE 768
  50. #define VIDC_IFACEQ_MIN_PKT_SIZE 8
  51. #define VIDC_IFACEQ_VAR_SMALL_PKT_SIZE 100
  52. #define VIDC_IFACEQ_VAR_LARGE_PKT_SIZE 512
  53. #define VIDC_IFACEQ_VAR_HUGE_PKT_SIZE (1024*12)
  54. #define NUM_MBS_PER_SEC(__height, __width, __fps) \
  55. (NUM_MBS_PER_FRAME(__height, __width) * __fps)
  56. #define NUM_MBS_PER_FRAME(__height, __width) \
  57. ((ALIGN(__height, 16) / 16) * (ALIGN(__width, 16) / 16))
  58. #define IS_PRIV_CTRL(idx) ( \
  59. (V4L2_CTRL_ID2WHICH(idx) == V4L2_CTRL_CLASS_MPEG) && \
  60. V4L2_CTRL_DRIVER_PRIV(idx))
  61. /*
  62. * Convert Q16 number into Integer and Fractional part upto 2 places.
  63. * Ex : 105752 / 65536 = 1.61; 1.61 in Q16 = 105752;
  64. * Integer part = 105752 / 65536 = 1;
  65. * Reminder = 105752 * 0xFFFF = 40216; Last 16 bits.
  66. * Fractional part = 40216 * 100 / 65536 = 61;
  67. * Now convert to FP(1, 61, 100).
  68. */
  69. #define Q16_INT(q) ((q) >> 16)
  70. #define Q16_FRAC(q) ((((q) & 0xFFFF) * 100) >> 16)
  71. enum msm_vidc_domain_type {
  72. MSM_VIDC_ENCODER = BIT(0),
  73. MSM_VIDC_DECODER = BIT(1),
  74. };
  75. enum msm_vidc_codec_type {
  76. MSM_VIDC_H264 = BIT(0),
  77. MSM_VIDC_HEVC = BIT(1),
  78. MSM_VIDC_VP9 = BIT(2),
  79. MSM_VIDC_MPEG2 = BIT(3),
  80. };
  81. enum msm_vidc_colorformat_type {
  82. MSM_VIDC_FMT_NV12 = BIT(0),
  83. MSM_VIDC_FMT_NV21 = BIT(1),
  84. MSM_VIDC_FMT_NV12_UBWC = BIT(2),
  85. MSM_VIDC_FMT_NV12_P010_UBWC = BIT(3),
  86. MSM_VIDC_FMT_NV12_TP10_UBWC = BIT(4),
  87. MSM_VIDC_FMT_RGBA8888_UBWC = BIT(5),
  88. MSM_VIDC_FMT_SDE_Y_CBCR_H2V2_P010_VENUS = BIT(6),
  89. };
  90. enum msm_vidc_buffer_type {
  91. MSM_VIDC_BUF_QUEUE = BIT(0),
  92. MSM_VIDC_BUF_INPUT = BIT(1),
  93. MSM_VIDC_BUF_OUTPUT = BIT(2),
  94. MSM_VIDC_BUF_INPUT_META = BIT(3),
  95. MSM_VIDC_BUF_OUTPUT_META = BIT(4),
  96. MSM_VIDC_BUF_SCRATCH = BIT(5),
  97. MSM_VIDC_BUF_SCRATCH_1 = BIT(6),
  98. MSM_VIDC_BUF_SCRATCH_2 = BIT(7),
  99. MSM_VIDC_BUF_PERSIST = BIT(8),
  100. MSM_VIDC_BUF_PERSIST_1 = BIT(9),
  101. };
  102. enum msm_vidc_buffer_attributes {
  103. MSM_VIDC_ATTR_DEFERRED_SUBMISSION = BIT(0),
  104. MSM_VIDC_ATTR_READ_ONLY = BIT(1),
  105. MSM_VIDC_ATTR_PENDING_RELEASE = BIT(2),
  106. MSM_VIDC_ATTR_QUEUED = BIT(3),
  107. };
  108. enum msm_vidc_buffer_region {
  109. MSM_VIDC_NON_SECURE = BIT(0),
  110. MSM_VIDC_SECURE_PIXEL = BIT(1),
  111. MSM_VIDC_SECURE_NONPIXEL = BIT(2),
  112. MSM_VIDC_SECURE_BITSTREAM = BIT(3),
  113. };
  114. enum msm_vidc_port_type {
  115. INPUT_PORT,
  116. OUTPUT_PORT,
  117. INPUT_META_PORT,
  118. OUTPUT_META_PORT,
  119. MAX_PORT,
  120. };
  121. enum msm_vidc_core_capability_type {
  122. CORE_CAP_NONE = 0,
  123. ENC_CODECS,
  124. DEC_CODECS,
  125. MAX_SESSION_COUNT,
  126. MAX_SECURE_SESSION_COUNT,
  127. MAX_LOAD,
  128. MAX_MBPF,
  129. MAX_MBPS,
  130. MAX_MBPF_HQ,
  131. MAX_MBPS_HQ,
  132. MAX_MBPF_B_FRAME,
  133. MAX_MBPS_B_FRAME,
  134. SW_PC,
  135. SW_PC_DELAY,
  136. FW_UNLOAD,
  137. FW_UNLOAD_DELAY,
  138. HW_RESPONSE_TIMEOUT,
  139. DEBUG_TIMEOUT,
  140. PREFIX_BUF_COUNT_PIX,
  141. PREFIX_BUF_SIZE_PIX,
  142. PREFIX_BUF_COUNT_NON_PIX,
  143. PREFIX_BUF_SIZE_NON_PIX,
  144. PAGEFAULT_NON_FATAL,
  145. PAGETABLE_CACHING,
  146. DCVS,
  147. DECODE_BATCH,
  148. DECODE_BATCH_TIMEOUT,
  149. AV_SYNC_WINDOW_SIZE,
  150. CLK_FREQ_THRESHOLD,
  151. CORE_CAP_MAX,
  152. };
  153. enum msm_vidc_inst_capability_type {
  154. INST_CAP_NONE = 0,
  155. FRAME_WIDTH,
  156. FRAME_HEIGHT,
  157. PIX_FMTS,
  158. MIN_BUFFERS_INPUT,
  159. MIN_BUFFERS_OUTPUT,
  160. DECODE_ORDER,
  161. THUMBNAIL_MODE,
  162. SECURE_MODE,
  163. LOWLATENCY_MODE,
  164. LOWLATENCY_HINT,
  165. BUF_SIZE_LIMIT,
  166. MBPF,
  167. MBPS,
  168. FRAME_RATE,
  169. BIT_RATE,
  170. BITRATE_MODE,
  171. LAYER_BITRATE,
  172. ENTROPY_MODE,
  173. CABAC_BITRATE,
  174. LTR_COUNT,
  175. LCU_SIZE,
  176. POWER_SAVE_MBPS,
  177. SCALE_X,
  178. SCALE_Y,
  179. PROFILE,
  180. LEVEL,
  181. I_FRAME_QP,
  182. P_FRAME_QP,
  183. B_FRAME_QP,
  184. B_FRAME,
  185. HIER_P_LAYERS,
  186. BLUR_WIDTH,
  187. BLUR_HEIGHT,
  188. SLICE_BYTE,
  189. SLICE_MB,
  190. SECURE,
  191. SECURE_FRAME_WIDTH,
  192. SECURE_FRAME_HEIGHT,
  193. SECURE_MBPF,
  194. SECURE_BIT_RATE,
  195. BATCH_MBPF,
  196. BATCH_FRAME_RATE,
  197. LOSSLESS_FRAME_WIDTH,
  198. LOSSLESS_FRAME_HEIGHT,
  199. LOSSLESS_MBPF,
  200. ALL_INTRA_FRAME_RATE,
  201. HEVC_IMAGE_FRAME_WIDTH,
  202. HEVC_IMAGE_FRAME_HEIGHT,
  203. HEIC_IMAGE_FRAME_WIDTH,
  204. HEIC_IMAGE_FRAME_HEIGHT,
  205. MB_CYCLES_VSP,
  206. MB_CYCLES_VPP,
  207. MB_CYCLES_LP,
  208. MB_CYCLES_FW,
  209. MB_CYCLES_FW_VPP,
  210. INST_CAP_MAX,
  211. };
  212. enum msm_vidc_inst_capability_flags {
  213. CAP_FLAG_NONE = 0,
  214. CAP_FLAG_ROOT = BIT(0),
  215. CAP_FLAG_DYNAMIC_ALLOWED = BIT(1),
  216. CAP_FLAG_MENU = BIT(2),
  217. };
  218. struct msm_vidc_inst_cap {
  219. enum msm_vidc_inst_capability_type cap;
  220. s32 min;
  221. s32 max;
  222. u32 step_or_mask;
  223. s32 value;
  224. u32 v4l2_id;
  225. u32 hfi_id;
  226. enum msm_vidc_inst_capability_flags flags;
  227. enum msm_vidc_inst_capability_type parents[MAX_CAP_PARENTS];
  228. enum msm_vidc_inst_capability_type children[MAX_CAP_CHILDREN];
  229. int (*adjust)(void *inst,
  230. enum msm_vidc_inst_capability_type cap_id,
  231. struct v4l2_ctrl *ctrl);
  232. int (*set)(void *inst,
  233. enum msm_vidc_inst_capability_type cap_id);
  234. };
  235. struct msm_vidc_inst_capability {
  236. enum msm_vidc_domain_type domain;
  237. enum msm_vidc_codec_type codec;
  238. struct msm_vidc_inst_cap cap[INST_CAP_MAX];
  239. };
  240. struct msm_vidc_core_capability {
  241. enum msm_vidc_core_capability_type type;
  242. u32 value;
  243. };
  244. struct msm_vidc_inst_cap_entry {
  245. struct list_head list;
  246. enum msm_vidc_inst_capability_type cap_id;
  247. };
  248. enum efuse_purpose {
  249. SKU_VERSION = 0,
  250. };
  251. enum sku_version {
  252. SKU_VERSION_0 = 0,
  253. SKU_VERSION_1,
  254. SKU_VERSION_2,
  255. };
  256. enum msm_vidc_ssr_trigger_type {
  257. SSR_ERR_FATAL = 1,
  258. SSR_SW_DIV_BY_ZERO,
  259. SSR_HW_WDOG_IRQ,
  260. };
  261. enum msm_vidc_cache_op {
  262. MSM_VIDC_CACHE_CLEAN,
  263. MSM_VIDC_CACHE_INVALIDATE,
  264. MSM_VIDC_CACHE_CLEAN_INVALIDATE,
  265. };
  266. enum msm_vidc_dcvs_flags {
  267. MSM_VIDC_DCVS_INCR = BIT(0),
  268. MSM_VIDC_DCVS_DECR = BIT(1),
  269. };
  270. enum msm_vidc_clock_properties {
  271. CLOCK_PROP_HAS_SCALING = BIT(0),
  272. CLOCK_PROP_HAS_MEM_RETENTION = BIT(1),
  273. };
  274. enum profiling_points {
  275. FRAME_PROCESSING = 0,
  276. MAX_PROFILING_POINTS,
  277. };
  278. enum signal_session_response {
  279. SIGNAL_CMD_STOP = 0,
  280. SIGNAL_CMD_CLOSE,
  281. MAX_SIGNAL,
  282. };
  283. #define HFI_MASK_QHDR_TX_TYPE 0xFF000000
  284. #define HFI_MASK_QHDR_RX_TYPE 0x00FF0000
  285. #define HFI_MASK_QHDR_PRI_TYPE 0x0000FF00
  286. #define HFI_MASK_QHDR_Q_ID_TYPE 0x000000FF
  287. #define HFI_Q_ID_HOST_TO_CTRL_CMD_Q 0x00
  288. #define HFI_Q_ID_CTRL_TO_HOST_MSG_Q 0x01
  289. #define HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q 0x02
  290. #define HFI_MASK_QHDR_STATUS 0x000000FF
  291. #define VIDC_IFACEQ_NUMQ 3
  292. #define VIDC_IFACEQ_CMDQ_IDX 0
  293. #define VIDC_IFACEQ_MSGQ_IDX 1
  294. #define VIDC_IFACEQ_DBGQ_IDX 2
  295. #define VIDC_IFACEQ_MAX_BUF_COUNT 50
  296. #define VIDC_IFACE_MAX_PARALLEL_CLNTS 16
  297. #define VIDC_IFACEQ_DFLT_QHDR 0x01010000
  298. struct hfi_queue_table_header {
  299. u32 qtbl_version;
  300. u32 qtbl_size;
  301. u32 qtbl_qhdr0_offset;
  302. u32 qtbl_qhdr_size;
  303. u32 qtbl_num_q;
  304. u32 qtbl_num_active_q;
  305. void *device_addr;
  306. char name[256];
  307. };
  308. struct hfi_queue_header {
  309. u32 qhdr_status;
  310. u32 qhdr_start_addr;
  311. u32 qhdr_type;
  312. u32 qhdr_q_size;
  313. u32 qhdr_pkt_size;
  314. u32 qhdr_pkt_drop_cnt;
  315. u32 qhdr_rx_wm;
  316. u32 qhdr_tx_wm;
  317. u32 qhdr_rx_req;
  318. u32 qhdr_tx_req;
  319. u32 qhdr_rx_irq_status;
  320. u32 qhdr_tx_irq_status;
  321. u32 qhdr_read_idx;
  322. u32 qhdr_write_idx;
  323. };
  324. #define VIDC_IFACEQ_TABLE_SIZE (sizeof(struct hfi_queue_table_header) \
  325. + sizeof(struct hfi_queue_header) * VIDC_IFACEQ_NUMQ)
  326. #define VIDC_IFACEQ_QUEUE_SIZE (VIDC_IFACEQ_MAX_PKT_SIZE * \
  327. VIDC_IFACEQ_MAX_BUF_COUNT * VIDC_IFACE_MAX_PARALLEL_CLNTS)
  328. #define VIDC_IFACEQ_GET_QHDR_START_ADDR(ptr, i) \
  329. (void *)((ptr + sizeof(struct hfi_queue_table_header)) + \
  330. (i * sizeof(struct hfi_queue_header)))
  331. #define QDSS_SIZE 4096
  332. #define SFR_SIZE 4096
  333. #define QUEUE_SIZE (VIDC_IFACEQ_TABLE_SIZE + \
  334. (VIDC_IFACEQ_QUEUE_SIZE * VIDC_IFACEQ_NUMQ))
  335. #define ALIGNED_QDSS_SIZE ALIGN(QDSS_SIZE, SZ_4K)
  336. #define ALIGNED_SFR_SIZE ALIGN(SFR_SIZE, SZ_4K)
  337. #define ALIGNED_QUEUE_SIZE ALIGN(QUEUE_SIZE, SZ_4K)
  338. #define SHARED_QSIZE ALIGN(ALIGNED_SFR_SIZE + ALIGNED_QUEUE_SIZE + \
  339. ALIGNED_QDSS_SIZE, SZ_1M)
  340. struct buf_count {
  341. u32 etb;
  342. u32 ftb;
  343. u32 fbd;
  344. u32 ebd;
  345. };
  346. struct profile_data {
  347. u32 start;
  348. u32 stop;
  349. u32 cumulative;
  350. char name[64];
  351. u32 sampling;
  352. u32 average;
  353. };
  354. struct msm_vidc_debug {
  355. struct profile_data pdata[MAX_PROFILING_POINTS];
  356. u32 profile;
  357. u32 samples;
  358. struct buf_count count;
  359. };
  360. struct msm_vidc_input_cr_data {
  361. struct list_head list;
  362. u32 index;
  363. u32 input_cr;
  364. };
  365. struct msm_vidc_timestamps {
  366. struct list_head list;
  367. u64 timestamp_us;
  368. u32 framerate;
  369. bool is_valid;
  370. };
  371. struct msm_vidc_session_idle {
  372. bool idle;
  373. u64 last_activity_time_ns;
  374. };
  375. struct msm_vidc_color_info {
  376. u32 colorspace;
  377. u32 ycbcr_enc;
  378. u32 xfer_func;
  379. u32 quantization;
  380. };
  381. struct msm_vidc_crop {
  382. u32 x;
  383. u32 y;
  384. u32 width;
  385. u32 height;
  386. };
  387. struct msm_vidc_properties {
  388. u32 frame_rate;
  389. u32 operating_rate;
  390. u32 bit_rate;
  391. u32 profile;
  392. u32 level;
  393. u32 entropy_mode;
  394. u32 rc_type;
  395. };
  396. struct msm_vidc_subscription_params {
  397. u32 align_width;
  398. u32 align_height;
  399. struct msm_vidc_crop crop;
  400. struct msm_vidc_color_info color_info;
  401. u32 bit_depth;
  402. u32 cabac;
  403. u32 interlace;
  404. u32 min_count;
  405. u32 pic_order_cnt;
  406. u32 profile;
  407. };
  408. struct msm_vidc_decode_vpp_delay {
  409. bool enable;
  410. u32 size;
  411. };
  412. struct msm_vidc_decode_batch {
  413. bool enable;
  414. u32 size;
  415. struct delayed_work work;
  416. };
  417. struct msm_vidc_power {
  418. u32 buffer_counter;
  419. u32 min_threshold;
  420. u32 nom_threshold;
  421. u32 max_threshold;
  422. bool dcvs_mode;
  423. u32 dcvs_window;
  424. u64 min_freq;
  425. u64 curr_freq;
  426. u32 ddr_bw;
  427. u32 sys_cache_bw;
  428. u32 dcvs_flags;
  429. };
  430. struct msm_vidc_alloc {
  431. struct list_head list;
  432. enum msm_vidc_buffer_type buffer_type;
  433. enum msm_vidc_buffer_region region;
  434. u32 size;
  435. u8 cached:1;
  436. u8 secure:1;
  437. u8 map_kernel:1;
  438. struct dma_buf *dmabuf;
  439. void *kvaddr;
  440. };
  441. struct msm_vidc_alloc_info {
  442. struct list_head list; // list of "struct msm_vidc_alloc"
  443. };
  444. struct msm_vidc_map {
  445. struct list_head list;
  446. bool valid;
  447. enum msm_vidc_buffer_type buffer_type;
  448. enum msm_vidc_buffer_region region;
  449. struct dma_buf *dmabuf;
  450. u32 refcount;
  451. u64 device_addr;
  452. struct sg_table *table;
  453. struct dma_buf_attachment *attach;
  454. };
  455. struct msm_vidc_map_info {
  456. struct list_head list; // list of "struct msm_vidc_map"
  457. };
  458. struct msm_vidc_buffer {
  459. struct list_head list;
  460. bool valid;
  461. enum msm_vidc_buffer_type type;
  462. u32 index;
  463. int fd;
  464. u32 buffer_size;
  465. u32 data_offset;
  466. u32 data_size;
  467. u64 device_addr;
  468. void *dmabuf;
  469. u32 flags;
  470. u64 timestamp;
  471. enum msm_vidc_buffer_attributes attr;
  472. };
  473. struct msm_vidc_buffer_info {
  474. struct list_head list; // list of "struct msm_vidc_buffer"
  475. u32 min_count;
  476. u32 extra_count;
  477. u32 actual_count;
  478. u32 size;
  479. };
  480. struct msm_vidc_ssr {
  481. bool trigger;
  482. enum msm_vidc_ssr_trigger_type ssr_type;
  483. };
  484. #define call_mem_op(c, op, ...) \
  485. (((c) && (c)->mem_ops && (c)->mem_ops->op) ? \
  486. ((c)->mem_ops->op(__VA_ARGS__)) : 0)
  487. struct msm_vidc_memory_ops {
  488. int (*allocate)(void *inst, struct msm_vidc_buffer *mbuf);
  489. int (*dma_map)(void *inst, struct msm_vidc_buffer *mbuf);
  490. int (*dma_unmap)(void *inst, struct msm_vidc_buffer *mbuf);
  491. int (*free)(void *inst, struct msm_vidc_buffer *mbuf);
  492. int (*cache_op)(void *inst, struct msm_vidc_buffer *mbuf,
  493. enum msm_vidc_cache_op cache_op);
  494. };
  495. #endif // _MSM_VIDC_INTERNAL_H_