3e42fefa2f
AQT1000 codec is a hifi headset that supports audio playback and recording on headset. It also supports playback of fractional sampling rates. Audio playback and recording is transferred through I2S interface. Add driver for AQT1000 codec Change-Id: Iba163e9203d67216cdbf87727b06801356a001e3 Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
882 строки
60 KiB
C
882 строки
60 KiB
C
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _AQT1000_REGISTERS_H
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#define _AQT1000_REGISTERS_H
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#define AQT1000_PAGE0_BASE (0x00000000)
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#define AQT1000_PAGE0_PAGE_REGISTER (0x00000000)
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#define AQT1000_CHIP_CFG0_BASE (0x00000001)
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#define AQT1000_CHIP_CFG0_CHIP_ID_BYTE0 (0x00000001)
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#define AQT1000_CHIP_CFG0_CHIP_ID_BYTE1 (0x00000002)
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#define AQT1000_CHIP_CFG0_CHIP_ID_BYTE2 (0x00000003)
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#define AQT1000_CHIP_CFG0_CHIP_ID_BYTE3 (0x00000004)
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#define AQT1000_CHIP_CFG0_EFUSE_CTL (0x00000005)
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#define AQT1000_CHIP_CFG0_EFUSE_TEST0 (0x00000006)
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#define AQT1000_CHIP_CFG0_EFUSE_TEST1 (0x00000007)
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#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT0 (0x00000009)
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#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT1 (0x0000000A)
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#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT2 (0x0000000B)
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#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT3 (0x0000000C)
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#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT4 (0x0000000D)
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#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT5 (0x0000000E)
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#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT6 (0x0000000F)
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#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT7 (0x00000010)
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#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT8 (0x00000011)
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#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT9 (0x00000012)
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#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT10 (0x00000013)
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#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT11 (0x00000014)
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#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT12 (0x00000015)
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#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT13 (0x00000016)
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#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT14 (0x00000017)
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#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT15 (0x00000018)
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#define AQT1000_CHIP_CFG0_EFUSE_STATUS (0x00000019)
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#define AQT1000_CHIP_CFG0_I2C_SLAVE_ID_NONNEGO (0x0000001A)
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#define AQT1000_CHIP_CFG0_I2C_SLAVE_ID_1 (0x0000001B)
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#define AQT1000_CHIP_CFG0_I2C_SLAVE_ID_2 (0x0000001C)
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#define AQT1000_CHIP_CFG0_I2C_SLAVE_ID_3 (0x0000001D)
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#define AQT1000_CHIP_CFG0_I2C_ACTIVE (0x00000020)
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#define AQT1000_CHIP_CFG0_CLK_CFG_MCLK (0x00000021)
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#define AQT1000_CHIP_CFG0_CLK_CFG_MCLK2 (0x00000022)
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#define AQT1000_CHIP_CFG0_CLK_CTL_CDC_DIG (0x00000023)
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#define AQT1000_CHIP_CFG0_RST_CTL (0x00000032)
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#define AQT1000_CHIP_CFG0_EFUSE2_CTL (0x0000003D)
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#define AQT1000_CHIP_CFG0_EFUSE2_TEST0 (0x0000003E)
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#define AQT1000_CHIP_CFG0_EFUSE2_TEST1 (0x0000003F)
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#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT0 (0x00000040)
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#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT1 (0x00000041)
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#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT2 (0x00000042)
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#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT3 (0x00000043)
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#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT4 (0x00000044)
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#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT5 (0x00000045)
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#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT6 (0x00000046)
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#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT7 (0x00000047)
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#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT8 (0x00000048)
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#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT9 (0x00000049)
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#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT10 (0x0000004A)
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#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT11 (0x0000004B)
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#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT12 (0x0000004C)
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#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT13 (0x0000004D)
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#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT14 (0x0000004E)
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#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT15 (0x0000004F)
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#define AQT1000_CHIP_CFG0_EFUSE2_STATUS (0x00000050)
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#define AQT1000_CHIP_CFG1_BASE (0x00000051)
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#define AQT1000_CHIP_CFG1_PWR_CTL (0x00000051)
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#define AQT1000_CHIP_CFG1_BUS_MTRX_CFG (0x00000052)
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#define AQT1000_CHIP_CFG1_DMA_BUS_VOTE (0x00000053)
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#define AQT1000_CHIP_CFG1_USB_BUS_VOTE (0x00000054)
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#define AQT1000_CHIP_CFG1_BLSP_BUS_VOTE (0x00000055)
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#define AQT1000_CHIP_CFG1_PWR_MEM_SD (0x00000059)
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#define AQT1000_CHIP_CFG1_PWR_SYS_MEM_SD_RAM (0x0000005C)
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#define AQT1000_CHIP_CFG1_PWR_SYS_MEM_SD_ROM (0x0000005D)
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#define AQT1000_CHIP_CFG1_PWR_SYS_MEM_FORCE_DS_RAM (0x0000005E)
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#define AQT1000_CHIP_CFG1_PWR_SYS_MEM_FORCE_DS_ROM (0x0000005F)
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#define AQT1000_CHIP_CFG1_CLK_CFG_FLL (0x00000061)
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#define AQT1000_CHIP_CFG1_CLK_CFG_SPI_M (0x00000062)
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#define AQT1000_CHIP_CFG1_CLK_CFG_I2C_M (0x00000063)
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#define AQT1000_CHIP_CFG1_CLK_CFG_UART (0x00000064)
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#define AQT1000_CHIP_CFG1_RST_USB_SS (0x00000071)
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#define AQT1000_CHIP_CFG1_RST_BLSP (0x00000072)
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#define AQT1000_CHIP_CFG1_RST_BUS_MTRX (0x00000073)
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#define AQT1000_CHIP_CFG1_RST_MISC (0x00000074)
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#define AQT1000_CHIP_CFG1_ANA_WAIT_STATE_CTL (0x00000081)
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#define AQT1000_PAGE1_BASE (0x00000100)
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#define AQT1000_PAGE1_PAGE_REGISTER (0x00000100)
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#define AQT1000_FLL_BASE (0x00000101)
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#define AQT1000_FLL_USER_CTL_0 (0x00000101)
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#define AQT1000_FLL_USER_CTL_1 (0x00000102)
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#define AQT1000_FLL_USER_CTL_2 (0x00000103)
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#define AQT1000_FLL_USER_CTL_3 (0x00000104)
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#define AQT1000_FLL_USER_CTL_4 (0x00000105)
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#define AQT1000_FLL_USER_CTL_5 (0x00000106)
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#define AQT1000_FLL_USER_CTL_6 (0x00000107)
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#define AQT1000_FLL_USER_CTL_7 (0x00000108)
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#define AQT1000_FLL_USER_CTL_8 (0x00000109)
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#define AQT1000_FLL_USER_CTL_9 (0x0000010A)
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#define AQT1000_FLL_L_VAL_CTL_0 (0x0000010B)
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#define AQT1000_FLL_L_VAL_CTL_1 (0x0000010C)
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#define AQT1000_FLL_DSM_FRAC_CTL_0 (0x0000010D)
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#define AQT1000_FLL_DSM_FRAC_CTL_1 (0x0000010E)
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#define AQT1000_FLL_CONFIG_CTL_0 (0x0000010F)
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#define AQT1000_FLL_CONFIG_CTL_1 (0x00000110)
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#define AQT1000_FLL_CONFIG_CTL_2 (0x00000111)
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#define AQT1000_FLL_CONFIG_CTL_3 (0x00000112)
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#define AQT1000_FLL_CONFIG_CTL_4 (0x00000113)
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#define AQT1000_FLL_TEST_CTL_0 (0x00000114)
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#define AQT1000_FLL_TEST_CTL_1 (0x00000115)
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#define AQT1000_FLL_TEST_CTL_2 (0x00000116)
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#define AQT1000_FLL_TEST_CTL_3 (0x00000117)
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#define AQT1000_FLL_TEST_CTL_4 (0x00000118)
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#define AQT1000_FLL_TEST_CTL_5 (0x00000119)
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#define AQT1000_FLL_TEST_CTL_6 (0x0000011A)
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#define AQT1000_FLL_TEST_CTL_7 (0x0000011B)
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#define AQT1000_FLL_FREQ_CTL_0 (0x0000011C)
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#define AQT1000_FLL_FREQ_CTL_1 (0x0000011D)
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#define AQT1000_FLL_FREQ_CTL_2 (0x0000011E)
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#define AQT1000_FLL_FREQ_CTL_3 (0x0000011F)
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#define AQT1000_FLL_SSC_CTL_0 (0x00000120)
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#define AQT1000_FLL_SSC_CTL_1 (0x00000121)
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#define AQT1000_FLL_SSC_CTL_2 (0x00000122)
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#define AQT1000_FLL_SSC_CTL_3 (0x00000123)
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#define AQT1000_FLL_FLL_MODE (0x00000124)
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#define AQT1000_FLL_STATUS_0 (0x00000125)
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#define AQT1000_FLL_STATUS_1 (0x00000126)
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#define AQT1000_FLL_STATUS_2 (0x00000127)
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#define AQT1000_FLL_STATUS_3 (0x00000128)
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#define AQT1000_PAGE2_BASE (0x00000200)
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#define AQT1000_PAGE2_PAGE_REGISTER (0x00000200)
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#define AQT1000_I2S_BASE (0x00000201)
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#define AQT1000_I2S_I2S_0_TX_CFG (0x00000201)
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#define AQT1000_I2S_I2S_0_RX_CFG (0x00000202)
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#define AQT1000_I2S_I2S_0_CTL (0x00000203)
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#define AQT1000_I2S_I2S_CLKSRC_CTL (0x00000204)
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#define AQT1000_I2S_I2S_HS_CLK_CTL (0x00000205)
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#define AQT1000_I2S_I2S_0_RST (0x00000206)
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#define AQT1000_I2S_SHADOW_I2S_0_CTL (0x00000207)
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#define AQT1000_I2S_SHADOW_I2S_0_RX_CFG (0x00000208)
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#define AQT1000_PAGE5_BASE (0x00000500)
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#define AQT1000_PAGE5_PAGE_REGISTER (0x00000500)
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#define AQT1000_INTR_CTRL_INTR_CTRL_BASE (0x00000501)
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#define AQT1000_INTR_CTRL_MCU_INT_POLARITY (0x00000501)
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#define AQT1000_INTR_CTRL_INT_MASK_0 (0x00000502)
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#define AQT1000_INTR_CTRL_INT_MASK_1 (0x00000503)
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#define AQT1000_INTR_CTRL_INT_MASK_2 (0x00000504)
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#define AQT1000_INTR_CTRL_INT_MASK_3 (0x00000505)
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#define AQT1000_INTR_CTRL_INT_MASK_4 (0x00000506)
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#define AQT1000_INTR_CTRL_INT_MASK_5 (0x00000507)
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#define AQT1000_INTR_CTRL_INT_MASK_6 (0x00000508)
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#define AQT1000_INTR_CTRL_INT_STATUS_0 (0x00000509)
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#define AQT1000_INTR_CTRL_INT_STATUS_1 (0x0000050A)
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#define AQT1000_INTR_CTRL_INT_STATUS_2 (0x0000050B)
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#define AQT1000_INTR_CTRL_INT_STATUS_3 (0x0000050C)
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#define AQT1000_INTR_CTRL_INT_STATUS_4 (0x0000050D)
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#define AQT1000_INTR_CTRL_INT_STATUS_5 (0x0000050E)
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#define AQT1000_INTR_CTRL_INT_STATUS_6 (0x0000050F)
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#define AQT1000_INTR_CTRL_INT_CLEAR_0 (0x00000510)
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#define AQT1000_INTR_CTRL_INT_CLEAR_1 (0x00000511)
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#define AQT1000_INTR_CTRL_INT_CLEAR_2 (0x00000512)
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#define AQT1000_INTR_CTRL_INT_CLEAR_3 (0x00000513)
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#define AQT1000_INTR_CTRL_INT_CLEAR_4 (0x00000514)
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#define AQT1000_INTR_CTRL_INT_CLEAR_5 (0x00000515)
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#define AQT1000_INTR_CTRL_INT_CLEAR_6 (0x00000516)
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#define AQT1000_INTR_CTRL_INT_TYPE_0 (0x00000517)
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#define AQT1000_INTR_CTRL_INT_TYPE_1 (0x00000518)
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#define AQT1000_INTR_CTRL_INT_TYPE_2 (0x00000519)
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#define AQT1000_INTR_CTRL_INT_TYPE_3 (0x0000051A)
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#define AQT1000_INTR_CTRL_INT_TYPE_4 (0x0000051B)
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#define AQT1000_INTR_CTRL_INT_TYPE_5 (0x0000051C)
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#define AQT1000_INTR_CTRL_INT_TYPE_6 (0x0000051D)
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#define AQT1000_INTR_CTRL_INT_TEST_EN_0 (0x0000051E)
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#define AQT1000_INTR_CTRL_INT_TEST_EN_1 (0x0000051F)
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#define AQT1000_INTR_CTRL_INT_TEST_EN_2 (0x00000520)
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#define AQT1000_INTR_CTRL_INT_TEST_EN_3 (0x00000521)
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#define AQT1000_INTR_CTRL_INT_TEST_EN_4 (0x00000522)
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#define AQT1000_INTR_CTRL_INT_TEST_EN_5 (0x00000523)
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#define AQT1000_INTR_CTRL_INT_TEST_EN_6 (0x00000524)
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#define AQT1000_INTR_CTRL_INT_TEST_VAL_0 (0x00000525)
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#define AQT1000_INTR_CTRL_INT_TEST_VAL_1 (0x00000526)
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#define AQT1000_INTR_CTRL_INT_TEST_VAL_2 (0x00000527)
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#define AQT1000_INTR_CTRL_INT_TEST_VAL_3 (0x00000528)
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#define AQT1000_INTR_CTRL_INT_TEST_VAL_4 (0x00000529)
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#define AQT1000_INTR_CTRL_INT_TEST_VAL_5 (0x0000052A)
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#define AQT1000_INTR_CTRL_INT_TEST_VAL_6 (0x0000052B)
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#define AQT1000_INTR_CTRL_INT_DEST_0 (0x0000052C)
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#define AQT1000_INTR_CTRL_INT_DEST_1 (0x0000052D)
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#define AQT1000_INTR_CTRL_INT_DEST_2 (0x0000052E)
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#define AQT1000_INTR_CTRL_INT_DEST_3 (0x0000052F)
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#define AQT1000_INTR_CTRL_INT_DEST_4 (0x00000530)
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#define AQT1000_INTR_CTRL_INT_DEST_5 (0x00000531)
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#define AQT1000_INTR_CTRL_INT_DEST_6 (0x00000532)
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#define AQT1000_INTR_CTRL_INT_DEST_7 (0x00000533)
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#define AQT1000_INTR_CTRL_INT_DEST_8 (0x00000534)
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#define AQT1000_INTR_CTRL_INT_DEST_9 (0x00000535)
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#define AQT1000_INTR_CTRL_INT_DEST_10 (0x00000536)
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#define AQT1000_INTR_CTRL_INT_DEST_11 (0x00000537)
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#define AQT1000_INTR_CTRL_INT_DEST_12 (0x00000538)
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#define AQT1000_INTR_CTRL_INT_DEST_13 (0x00000539)
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#define AQT1000_INTR_CTRL_CLR_COMMIT (0x000005E1)
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#define AQT1000_ANA_BASE (0x00000600)
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#define AQT1000_ANA_PAGE_REGISTER (0x00000600)
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#define AQT1000_ANA_BIAS (0x00000601)
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#define AQT1000_ANA_RX_SUPPLIES (0x00000608)
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#define AQT1000_ANA_HPH (0x00000609)
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#define AQT1000_ANA_AMIC1 (0x0000060E)
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#define AQT1000_ANA_AMIC2 (0x0000060F)
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#define AQT1000_ANA_AMIC3 (0x00000610)
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#define AQT1000_ANA_AMIC3_HPF (0x00000611)
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#define AQT1000_ANA_MBHC_MECH (0x00000614)
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#define AQT1000_ANA_MBHC_ELECT (0x00000615)
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#define AQT1000_ANA_MBHC_ZDET (0x00000616)
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#define AQT1000_ANA_MBHC_RESULT_1 (0x00000617)
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#define AQT1000_ANA_MBHC_RESULT_2 (0x00000618)
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#define AQT1000_ANA_MBHC_RESULT_3 (0x00000619)
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#define AQT1000_ANA_MBHC_BTN0 (0x0000061A)
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#define AQT1000_ANA_MBHC_BTN1 (0x0000061B)
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#define AQT1000_ANA_MBHC_BTN2 (0x0000061C)
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#define AQT1000_ANA_MBHC_BTN3 (0x0000061D)
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#define AQT1000_ANA_MBHC_BTN4 (0x0000061E)
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#define AQT1000_ANA_MBHC_BTN5 (0x0000061F)
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#define AQT1000_ANA_MBHC_BTN6 (0x00000620)
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#define AQT1000_ANA_MBHC_BTN7 (0x00000621)
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#define AQT1000_ANA_MICB1 (0x00000622)
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#define AQT1000_ANA_MICB1_RAMP (0x00000624)
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#define AQT1000_BIAS_BASE (0x00000628)
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#define AQT1000_BIAS_CTL (0x00000628)
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#define AQT1000_BIAS_CCOMP_FINE_ADJ (0x00000629)
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#define AQT1000_LED_BASE (0x0000062E)
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#define AQT1000_LED_LED_MODE_SEL_R (0x0000062E)
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#define AQT1000_LED_LED_MISC_R (0x0000062F)
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#define AQT1000_LED_LED_MODE_SEL_G (0x00000630)
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#define AQT1000_LED_LED_MISC_G (0x00000631)
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#define AQT1000_LED_LED_MODE_SEL_B (0x00000632)
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#define AQT1000_LED_LED_MISC_B (0x00000633)
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#define AQT1000_LDOH_BASE (0x0000063A)
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#define AQT1000_LDOH_MODE (0x0000063A)
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#define AQT1000_LDOH_BIAS (0x0000063B)
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#define AQT1000_LDOH_STB_LOADS (0x0000063C)
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#define AQT1000_LDOH_MISC1 (0x0000063D)
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#define AQT1000_LDOL_BASE (0x00000640)
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#define AQT1000_LDOL_VDDCX_ADJUST (0x00000640)
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#define AQT1000_LDOL_DISABLE_LDOL (0x00000641)
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#define AQT1000_BUCK_5V_BASE (0x00000644)
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#define AQT1000_BUCK_5V_EN_CTL (0x00000644)
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#define AQT1000_BUCK_5V_VOUT_SEL (0x00000645)
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#define AQT1000_BUCK_5V_CTRL_VCL_1 (0x00000646)
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#define AQT1000_BUCK_5V_CTRL_VCL_2 (0x00000647)
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#define AQT1000_BUCK_5V_CTRL_CCL_2 (0x00000648)
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#define AQT1000_BUCK_5V_CTRL_CCL_1 (0x00000649)
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#define AQT1000_BUCK_5V_CTRL_CCL_3 (0x0000064A)
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#define AQT1000_BUCK_5V_CTRL_CCL_4 (0x0000064B)
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#define AQT1000_BUCK_5V_CTRL_CCL_5 (0x0000064C)
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#define AQT1000_BUCK_5V_IBIAS_CTL_1 (0x0000064D)
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#define AQT1000_BUCK_5V_IBIAS_CTL_2 (0x0000064E)
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#define AQT1000_BUCK_5V_IBIAS_CTL_3 (0x0000064F)
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#define AQT1000_BUCK_5V_IBIAS_CTL_4 (0x00000650)
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#define AQT1000_BUCK_5V_IBIAS_CTL_5 (0x00000651)
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#define AQT1000_BUCK_5V_ATEST_DTEST_CTL (0x00000652)
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#define AQT1000_PON_BASE (0x00000653)
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#define AQT1000_PON_BG_CTRL (0x00000653)
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#define AQT1000_PON_TEST_CTRL (0x00000654)
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#define AQT1000_MBHC_BASE (0x00000656)
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#define AQT1000_MBHC_CTL_CLK (0x00000656)
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#define AQT1000_MBHC_CTL_ANA (0x00000657)
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#define AQT1000_MBHC_CTL_SPARE_1 (0x00000658)
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#define AQT1000_MBHC_CTL_SPARE_2 (0x00000659)
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#define AQT1000_MBHC_CTL_BCS (0x0000065A)
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#define AQT1000_MBHC_MOISTURE_DET_FSM_STATUS (0x0000065B)
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#define AQT1000_MBHC_TEST_CTL (0x0000065C)
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#define AQT1000_MICB1_BASE (0x0000066B)
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#define AQT1000_MICB1_TEST_CTL_1 (0x0000066B)
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#define AQT1000_MICB1_TEST_CTL_2 (0x0000066C)
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#define AQT1000_MICB1_TEST_CTL_3 (0x0000066D)
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#define AQT1000_MICB1_MISC_BASE (0x0000066E)
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#define AQT1000_MICB1_MISC_MICB1_INM_RES_BIAS (0x0000066E)
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#define AQT1000_MICB1_MISC_MICB_MISC1 (0x0000066F)
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#define AQT1000_MICB1_MISC_MICB_MISC2 (0x00000670)
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#define AQT1000_TX_COM_BASE (0x00000677)
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#define AQT1000_TX_COM_ADC_VCM (0x00000677)
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#define AQT1000_TX_COM_BIAS_ATEST (0x00000678)
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#define AQT1000_TX_COM_ADC_INT1_IB (0x00000679)
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#define AQT1000_TX_COM_ADC_INT2_IB (0x0000067A)
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#define AQT1000_TX_COM_TXFE_DIV_CTL (0x0000067B)
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#define AQT1000_TX_COM_TXFE_DIV_START (0x0000067C)
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#define AQT1000_TX_COM_TXFE_DIV_STOP_9P6M (0x0000067D)
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#define AQT1000_TX_COM_TXFE_DIV_STOP_12P288M (0x0000067E)
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#define AQT1000_TX_1_2_BASE (0x0000067F)
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#define AQT1000_TX_1_2_TEST_EN (0x0000067F)
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#define AQT1000_TX_1_2_ADC_IB (0x00000680)
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#define AQT1000_TX_1_2_ATEST_REFCTL (0x00000681)
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#define AQT1000_TX_1_2_TEST_CTL (0x00000682)
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#define AQT1000_TX_1_2_TEST_BLK_EN (0x00000683)
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#define AQT1000_TX_1_2_TXFE_CLKDIV (0x00000684)
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#define AQT1000_TX_1_2_SAR1_ERR (0x00000685)
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#define AQT1000_TX_1_2_SAR2_ERR (0x00000686)
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#define AQT1000_TX_3_BASE (0x00000687)
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#define AQT1000_TX_3_TEST_EN (0x00000687)
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#define AQT1000_TX_3_ADC_IB (0x00000688)
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#define AQT1000_TX_3_ATEST_REFCTL (0x00000689)
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#define AQT1000_TX_3_TEST_CTL (0x0000068A)
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#define AQT1000_TX_3_TEST_BLK_EN (0x0000068B)
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#define AQT1000_TX_3_TXFE_CLKDIV (0x0000068C)
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#define AQT1000_TX_3_SAR1_ERR (0x0000068D)
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#define AQT1000_TX_3_SAR2_ERR (0x0000068E)
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#define AQT1000_TX_BASE (0x0000068F)
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#define AQT1000_TX_ATEST1_2_SEL (0x0000068F)
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#define AQT1000_CLASSH_BASE (0x00000697)
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#define AQT1000_CLASSH_MODE_1 (0x00000697)
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#define AQT1000_CLASSH_MODE_2 (0x00000698)
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#define AQT1000_CLASSH_MODE_3 (0x00000699)
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#define AQT1000_CLASSH_CTRL_VCL_1 (0x0000069A)
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#define AQT1000_CLASSH_CTRL_VCL_2 (0x0000069B)
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#define AQT1000_CLASSH_CTRL_CCL_1 (0x0000069C)
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#define AQT1000_CLASSH_CTRL_CCL_2 (0x0000069D)
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#define AQT1000_CLASSH_CTRL_CCL_3 (0x0000069E)
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#define AQT1000_CLASSH_CTRL_CCL_4 (0x0000069F)
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#define AQT1000_CLASSH_CTRL_CCL_5 (0x000006A0)
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#define AQT1000_CLASSH_BUCK_TMUX_A_D (0x000006A1)
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#define AQT1000_CLASSH_BUCK_SW_DRV_CNTL (0x000006A2)
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#define AQT1000_CLASSH_SPARE (0x000006A3)
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#define AQT1000_FLYBACK_BASE (0x000006A4)
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#define AQT1000_FLYBACK_EN (0x000006A4)
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#define AQT1000_FLYBACK_VNEG_CTRL_1 (0x000006A5)
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#define AQT1000_FLYBACK_VNEG_CTRL_2 (0x000006A6)
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#define AQT1000_FLYBACK_VNEG_CTRL_3 (0x000006A7)
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#define AQT1000_FLYBACK_VNEG_CTRL_4 (0x000006A8)
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#define AQT1000_FLYBACK_VNEG_CTRL_5 (0x000006A9)
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#define AQT1000_FLYBACK_VNEG_CTRL_6 (0x000006AA)
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#define AQT1000_FLYBACK_VNEG_CTRL_7 (0x000006AB)
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#define AQT1000_FLYBACK_VNEG_CTRL_8 (0x000006AC)
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#define AQT1000_FLYBACK_VNEG_CTRL_9 (0x000006AD)
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#define AQT1000_FLYBACK_VNEGDAC_CTRL_1 (0x000006AE)
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#define AQT1000_FLYBACK_VNEGDAC_CTRL_2 (0x000006AF)
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#define AQT1000_FLYBACK_VNEGDAC_CTRL_3 (0x000006B0)
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#define AQT1000_FLYBACK_CTRL_1 (0x000006B1)
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#define AQT1000_FLYBACK_TEST_CTL (0x000006B2)
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#define AQT1000_RX_BASE (0x000006B3)
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#define AQT1000_RX_AUX_SW_CTL (0x000006B3)
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#define AQT1000_RX_PA_AUX_IN_CONN (0x000006B4)
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#define AQT1000_RX_TIMER_DIV (0x000006B5)
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#define AQT1000_RX_OCP_CTL (0x000006B6)
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#define AQT1000_RX_OCP_COUNT (0x000006B7)
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#define AQT1000_RX_BIAS_ATEST (0x000006B8)
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#define AQT1000_RX_BIAS_MISC1 (0x000006B9)
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#define AQT1000_RX_BIAS_HPH_LDO (0x000006BA)
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#define AQT1000_RX_BIAS_HPH_PA (0x000006BB)
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#define AQT1000_RX_BIAS_HPH_RDACBUFF_CNP2 (0x000006BC)
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#define AQT1000_RX_BIAS_HPH_RDAC_LDO (0x000006BD)
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#define AQT1000_RX_BIAS_HPH_CNP1 (0x000006BE)
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#define AQT1000_RX_BIAS_HPH_LOWPOWER (0x000006BF)
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#define AQT1000_RX_BIAS_MISC2 (0x000006C0)
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#define AQT1000_RX_BIAS_MISC3 (0x000006C1)
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#define AQT1000_RX_BIAS_MISC4 (0x000006C2)
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#define AQT1000_RX_BIAS_MISC5 (0x000006C3)
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#define AQT1000_RX_BIAS_BUCK_RST (0x000006C4)
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#define AQT1000_RX_BIAS_BUCK_VREF_ERRAMP (0x000006C5)
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#define AQT1000_RX_BIAS_FLYB_ERRAMP (0x000006C6)
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#define AQT1000_RX_BIAS_FLYB_BUFF (0x000006C7)
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#define AQT1000_RX_BIAS_FLYB_MID_RST (0x000006C8)
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#define AQT1000_HPH_BASE (0x000006C9)
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#define AQT1000_HPH_L_STATUS (0x000006C9)
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#define AQT1000_HPH_R_STATUS (0x000006CA)
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#define AQT1000_HPH_CNP_EN (0x000006CB)
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#define AQT1000_HPH_CNP_WG_CTL (0x000006CC)
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#define AQT1000_HPH_CNP_WG_TIME (0x000006CD)
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#define AQT1000_HPH_OCP_CTL (0x000006CE)
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#define AQT1000_HPH_AUTO_CHOP (0x000006CF)
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#define AQT1000_HPH_CHOP_CTL (0x000006D0)
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#define AQT1000_HPH_PA_CTL1 (0x000006D1)
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#define AQT1000_HPH_PA_CTL2 (0x000006D2)
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#define AQT1000_HPH_L_EN (0x000006D3)
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#define AQT1000_HPH_L_TEST (0x000006D4)
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#define AQT1000_HPH_L_ATEST (0x000006D5)
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#define AQT1000_HPH_R_EN (0x000006D6)
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#define AQT1000_HPH_R_TEST (0x000006D7)
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#define AQT1000_HPH_R_ATEST (0x000006D8)
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#define AQT1000_HPH_RDAC_CLK_CTL1 (0x000006D9)
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#define AQT1000_HPH_RDAC_CLK_CTL2 (0x000006DA)
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#define AQT1000_HPH_RDAC_LDO_CTL (0x000006DB)
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#define AQT1000_HPH_RDAC_CHOP_CLK_LP_CTL (0x000006DC)
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#define AQT1000_HPH_REFBUFF_UHQA_CTL (0x000006DD)
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#define AQT1000_HPH_REFBUFF_LP_CTL (0x000006DE)
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#define AQT1000_HPH_L_DAC_CTL (0x000006DF)
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#define AQT1000_HPH_R_DAC_CTL (0x000006E0)
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#define AQT1000_HPHLR_BASE (0x000006E1)
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#define AQT1000_HPHLR_SURGE_COMP_SEL (0x000006E1)
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#define AQT1000_HPHLR_SURGE_EN (0x000006E2)
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#define AQT1000_HPHLR_SURGE_MISC1 (0x000006E3)
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#define AQT1000_HPHLR_SURGE_STATUS (0x000006E4)
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#define AQT1000_ANA_NEW_BASE (0x00000700)
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#define AQT1000_ANA_NEW_PAGE_REGISTER (0x00000700)
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#define AQT1000_HPH_NEW_BASE (0x00000701)
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#define AQT1000_HPH_NEW_ANA_HPH2 (0x00000701)
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#define AQT1000_HPH_NEW_ANA_HPH3 (0x00000702)
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#define AQT1000_CLK_SYS_BASE (0x0000070E)
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#define AQT1000_CLK_SYS_MCLK1_PRG (0x0000070E)
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#define AQT1000_CLK_SYS_MCLK2_I2S_HS_CLK_PRG (0x0000070F)
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#define AQT1000_CLK_SYS_XO_CAP_XTP (0x00000710)
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#define AQT1000_CLK_SYS_XO_CAP_XTM (0x00000711)
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#define AQT1000_CLK_SYS_PLL_ENABLES (0x00000712)
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#define AQT1000_CLK_SYS_PLL_PRESET (0x00000713)
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#define AQT1000_CLK_SYS_PLL_STATUS (0x00000714)
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#define AQT1000_MBHC_NEW_BASE (0x0000071F)
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#define AQT1000_MBHC_NEW_ELECT_REM_CLAMP_CTL (0x0000071F)
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#define AQT1000_MBHC_NEW_CTL_1 (0x00000720)
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#define AQT1000_MBHC_NEW_CTL_2 (0x00000721)
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#define AQT1000_MBHC_NEW_PLUG_DETECT_CTL (0x00000722)
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#define AQT1000_MBHC_NEW_ZDET_ANA_CTL (0x00000723)
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#define AQT1000_MBHC_NEW_ZDET_RAMP_CTL (0x00000724)
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#define AQT1000_MBHC_NEW_FSM_STATUS (0x00000725)
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#define AQT1000_MBHC_NEW_ADC_RESULT (0x00000726)
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#define AQT1000_HPH_NEW_INT_BASE (0x00000732)
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#define AQT1000_HPH_NEW_INT_RDAC_GAIN_CTL (0x00000732)
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#define AQT1000_HPH_NEW_INT_RDAC_HD2_CTL_L (0x00000733)
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#define AQT1000_HPH_NEW_INT_RDAC_VREF_CTL (0x00000734)
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#define AQT1000_HPH_NEW_INT_RDAC_OVERRIDE_CTL (0x00000735)
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#define AQT1000_HPH_NEW_INT_RDAC_HD2_CTL_R (0x00000736)
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#define AQT1000_HPH_NEW_INT_PA_MISC1 (0x00000737)
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#define AQT1000_HPH_NEW_INT_PA_MISC2 (0x00000738)
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#define AQT1000_HPH_NEW_INT_PA_RDAC_MISC (0x00000739)
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#define AQT1000_HPH_NEW_INT_HPH_TIMER1 (0x0000073A)
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#define AQT1000_HPH_NEW_INT_HPH_TIMER2 (0x0000073B)
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#define AQT1000_HPH_NEW_INT_HPH_TIMER3 (0x0000073C)
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#define AQT1000_HPH_NEW_INT_HPH_TIMER4 (0x0000073D)
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#define AQT1000_HPH_NEW_INT_PA_RDAC_MISC2 (0x0000073E)
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#define AQT1000_HPH_NEW_INT_PA_RDAC_MISC3 (0x0000073F)
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#define AQT1000_RX_NEW_INT_BASE (0x00000745)
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#define AQT1000_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI (0x00000745)
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#define AQT1000_RX_NEW_INT_HPH_RDAC_BIAS_ULP (0x00000746)
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#define AQT1000_RX_NEW_INT_HPH_RDAC_LDO_LP (0x00000747)
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#define AQT1000_CLK_SYS_INT_BASE (0x0000076C)
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#define AQT1000_CLK_SYS_INT_CLK_TEST1 (0x0000076C)
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#define AQT1000_CLK_SYS_INT_XO_TEST1 (0x0000076D)
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#define AQT1000_CLK_SYS_INT_XO_TEST2 (0x0000076E)
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#define AQT1000_CLK_SYS_INT_POST_DIV_REG0 (0x0000076F)
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#define AQT1000_CLK_SYS_INT_POST_DIV_REG1 (0x00000770)
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#define AQT1000_CLK_SYS_INT_REF_DIV_REG0 (0x00000771)
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#define AQT1000_CLK_SYS_INT_REF_DIV_REG1 (0x00000772)
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#define AQT1000_CLK_SYS_INT_FILTER_REG0 (0x00000773)
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#define AQT1000_CLK_SYS_INT_FILTER_REG1 (0x00000774)
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#define AQT1000_CLK_SYS_INT_PLL_L_VAL (0x00000775)
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#define AQT1000_CLK_SYS_INT_PLL_M_VAL (0x00000776)
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#define AQT1000_CLK_SYS_INT_PLL_N_VAL (0x00000777)
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#define AQT1000_CLK_SYS_INT_TEST_REG0 (0x00000778)
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#define AQT1000_CLK_SYS_INT_PFD_CP_DSM_PROG (0x00000779)
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#define AQT1000_CLK_SYS_INT_VCO_PROG (0x0000077A)
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#define AQT1000_CLK_SYS_INT_TEST_REG1 (0x0000077B)
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#define AQT1000_CLK_SYS_INT_LDO_LOCK_CFG (0x0000077C)
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#define AQT1000_CLK_SYS_INT_DIG_LOCK_DET_CFG (0x0000077D)
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#define AQT1000_MBHC_NEW_INT_BASE (0x000007AF)
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#define AQT1000_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL (0x000007AF)
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#define AQT1000_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL (0x000007B0)
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#define AQT1000_MBHC_NEW_INT_MECH_DET_CURRENT (0x000007B1)
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#define AQT1000_MBHC_NEW_INT_SPARE_2 (0x000007B2)
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#define AQT1000_PAGE10_BASE (0x00000A00)
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#define AQT1000_PAGE10_PAGE_REGISTER (0x00000A00)
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#define AQT1000_CDC_ANC0_BASE (0x00000A01)
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#define AQT1000_CDC_ANC0_CLK_RESET_CTL (0x00000A01)
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#define AQT1000_CDC_ANC0_MODE_1_CTL (0x00000A02)
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#define AQT1000_CDC_ANC0_MODE_2_CTL (0x00000A03)
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#define AQT1000_CDC_ANC0_FF_SHIFT (0x00000A04)
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#define AQT1000_CDC_ANC0_FB_SHIFT (0x00000A05)
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#define AQT1000_CDC_ANC0_LPF_FF_A_CTL (0x00000A06)
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#define AQT1000_CDC_ANC0_LPF_FF_B_CTL (0x00000A07)
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#define AQT1000_CDC_ANC0_LPF_FB_CTL (0x00000A08)
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#define AQT1000_CDC_ANC0_SMLPF_CTL (0x00000A09)
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#define AQT1000_CDC_ANC0_DCFLT_SHIFT_CTL (0x00000A0A)
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#define AQT1000_CDC_ANC0_IIR_ADAPT_CTL (0x00000A0B)
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#define AQT1000_CDC_ANC0_IIR_COEFF_1_CTL (0x00000A0C)
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#define AQT1000_CDC_ANC0_IIR_COEFF_2_CTL (0x00000A0D)
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#define AQT1000_CDC_ANC0_FF_A_GAIN_CTL (0x00000A0E)
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#define AQT1000_CDC_ANC0_FF_B_GAIN_CTL (0x00000A0F)
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#define AQT1000_CDC_ANC0_FB_GAIN_CTL (0x00000A10)
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#define AQT1000_CDC_ANC0_RC_COMMON_CTL (0x00000A11)
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#define AQT1000_CDC_ANC0_FIFO_COMMON_CTL (0x00000A13)
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#define AQT1000_CDC_ANC0_RC0_STATUS_FMIN_CNTR (0x00000A14)
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#define AQT1000_CDC_ANC0_RC1_STATUS_FMIN_CNTR (0x00000A15)
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#define AQT1000_CDC_ANC0_RC0_STATUS_FMAX_CNTR (0x00000A16)
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#define AQT1000_CDC_ANC0_RC1_STATUS_FMAX_CNTR (0x00000A17)
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#define AQT1000_CDC_ANC0_STATUS_FIFO (0x00000A18)
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#define AQT1000_CDC_ANC1_BASE (0x00000A19)
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#define AQT1000_CDC_ANC1_CLK_RESET_CTL (0x00000A19)
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#define AQT1000_CDC_ANC1_MODE_1_CTL (0x00000A1A)
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#define AQT1000_CDC_ANC1_MODE_2_CTL (0x00000A1B)
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#define AQT1000_CDC_ANC1_FF_SHIFT (0x00000A1C)
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#define AQT1000_CDC_ANC1_FB_SHIFT (0x00000A1D)
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#define AQT1000_CDC_ANC1_LPF_FF_A_CTL (0x00000A1E)
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#define AQT1000_CDC_ANC1_LPF_FF_B_CTL (0x00000A1F)
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#define AQT1000_CDC_ANC1_LPF_FB_CTL (0x00000A20)
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#define AQT1000_CDC_ANC1_SMLPF_CTL (0x00000A21)
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#define AQT1000_CDC_ANC1_DCFLT_SHIFT_CTL (0x00000A22)
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#define AQT1000_CDC_ANC1_IIR_ADAPT_CTL (0x00000A23)
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#define AQT1000_CDC_ANC1_IIR_COEFF_1_CTL (0x00000A24)
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#define AQT1000_CDC_ANC1_IIR_COEFF_2_CTL (0x00000A25)
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#define AQT1000_CDC_ANC1_FF_A_GAIN_CTL (0x00000A26)
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#define AQT1000_CDC_ANC1_FF_B_GAIN_CTL (0x00000A27)
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#define AQT1000_CDC_ANC1_FB_GAIN_CTL (0x00000A28)
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#define AQT1000_CDC_ANC1_RC_COMMON_CTL (0x00000A29)
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#define AQT1000_CDC_ANC1_FIFO_COMMON_CTL (0x00000A2B)
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#define AQT1000_CDC_ANC1_RC0_STATUS_FMIN_CNTR (0x00000A2C)
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#define AQT1000_CDC_ANC1_RC1_STATUS_FMIN_CNTR (0x00000A2D)
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#define AQT1000_CDC_ANC1_RC0_STATUS_FMAX_CNTR (0x00000A2E)
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#define AQT1000_CDC_ANC1_RC1_STATUS_FMAX_CNTR (0x00000A2F)
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#define AQT1000_CDC_ANC1_STATUS_FIFO (0x00000A30)
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#define AQT1000_CDC_TX0_BASE (0x00000A31)
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#define AQT1000_CDC_TX0_TX_PATH_CTL (0x00000A31)
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#define AQT1000_CDC_TX0_TX_PATH_CFG0 (0x00000A32)
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#define AQT1000_CDC_TX0_TX_PATH_CFG1 (0x00000A33)
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#define AQT1000_CDC_TX0_TX_VOL_CTL (0x00000A34)
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#define AQT1000_CDC_TX0_TX_PATH_SEC0 (0x00000A37)
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#define AQT1000_CDC_TX0_TX_PATH_SEC1 (0x00000A38)
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#define AQT1000_CDC_TX0_TX_PATH_SEC2 (0x00000A39)
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#define AQT1000_CDC_TX0_TX_PATH_SEC3 (0x00000A3A)
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#define AQT1000_CDC_TX0_TX_PATH_SEC4 (0x00000A3B)
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#define AQT1000_CDC_TX0_TX_PATH_SEC5 (0x00000A3C)
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#define AQT1000_CDC_TX0_TX_PATH_SEC6 (0x00000A3D)
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#define AQT1000_CDC_TX1_BASE (0x00000A41)
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#define AQT1000_CDC_TX1_TX_PATH_CTL (0x00000A41)
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#define AQT1000_CDC_TX1_TX_PATH_CFG0 (0x00000A42)
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#define AQT1000_CDC_TX1_TX_PATH_CFG1 (0x00000A43)
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#define AQT1000_CDC_TX1_TX_VOL_CTL (0x00000A44)
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#define AQT1000_CDC_TX1_TX_PATH_SEC0 (0x00000A47)
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|
#define AQT1000_CDC_TX1_TX_PATH_SEC1 (0x00000A48)
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|
#define AQT1000_CDC_TX1_TX_PATH_SEC2 (0x00000A49)
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|
#define AQT1000_CDC_TX1_TX_PATH_SEC3 (0x00000A4A)
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#define AQT1000_CDC_TX1_TX_PATH_SEC4 (0x00000A4B)
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#define AQT1000_CDC_TX1_TX_PATH_SEC5 (0x00000A4C)
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#define AQT1000_CDC_TX1_TX_PATH_SEC6 (0x00000A4D)
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#define AQT1000_CDC_TX2_BASE (0x00000A51)
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#define AQT1000_CDC_TX2_TX_PATH_CTL (0x00000A51)
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#define AQT1000_CDC_TX2_TX_PATH_CFG0 (0x00000A52)
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#define AQT1000_CDC_TX2_TX_PATH_CFG1 (0x00000A53)
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#define AQT1000_CDC_TX2_TX_VOL_CTL (0x00000A54)
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#define AQT1000_CDC_TX2_TX_PATH_SEC0 (0x00000A57)
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#define AQT1000_CDC_TX2_TX_PATH_SEC1 (0x00000A58)
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#define AQT1000_CDC_TX2_TX_PATH_SEC2 (0x00000A59)
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#define AQT1000_CDC_TX2_TX_PATH_SEC3 (0x00000A5A)
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#define AQT1000_CDC_TX2_TX_PATH_SEC4 (0x00000A5B)
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#define AQT1000_CDC_TX2_TX_PATH_SEC5 (0x00000A5C)
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#define AQT1000_CDC_TX2_TX_PATH_SEC6 (0x00000A5D)
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#define AQT1000_CDC_TX2_TX_PATH_SEC7 (0x00000A5E)
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#define AQT1000_PAGE11_BASE (0x00000B00)
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#define AQT1000_PAGE11_PAGE_REGISTER (0x00000B00)
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#define AQT1000_CDC_COMPANDER1_BASE (0x00000B01)
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#define AQT1000_CDC_COMPANDER1_CTL0 (0x00000B01)
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#define AQT1000_CDC_COMPANDER1_CTL1 (0x00000B02)
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#define AQT1000_CDC_COMPANDER1_CTL2 (0x00000B03)
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#define AQT1000_CDC_COMPANDER1_CTL3 (0x00000B04)
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#define AQT1000_CDC_COMPANDER1_CTL4 (0x00000B05)
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#define AQT1000_CDC_COMPANDER1_CTL5 (0x00000B06)
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#define AQT1000_CDC_COMPANDER1_CTL6 (0x00000B07)
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#define AQT1000_CDC_COMPANDER1_CTL7 (0x00000B08)
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#define AQT1000_CDC_COMPANDER2_BASE (0x00000B09)
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#define AQT1000_CDC_COMPANDER2_CTL0 (0x00000B09)
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#define AQT1000_CDC_COMPANDER2_CTL1 (0x00000B0A)
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#define AQT1000_CDC_COMPANDER2_CTL2 (0x00000B0B)
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#define AQT1000_CDC_COMPANDER2_CTL3 (0x00000B0C)
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#define AQT1000_CDC_COMPANDER2_CTL4 (0x00000B0D)
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#define AQT1000_CDC_COMPANDER2_CTL5 (0x00000B0E)
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#define AQT1000_CDC_COMPANDER2_CTL6 (0x00000B0F)
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#define AQT1000_CDC_COMPANDER2_CTL7 (0x00000B10)
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#define AQT1000_CDC_RX1_BASE (0x00000B55)
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#define AQT1000_CDC_RX1_RX_PATH_CTL (0x00000B55)
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#define AQT1000_CDC_RX1_RX_PATH_CFG0 (0x00000B56)
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#define AQT1000_CDC_RX1_RX_PATH_CFG1 (0x00000B57)
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#define AQT1000_CDC_RX1_RX_PATH_CFG2 (0x00000B58)
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#define AQT1000_CDC_RX1_RX_VOL_CTL (0x00000B59)
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#define AQT1000_CDC_RX1_RX_PATH_MIX_CTL (0x00000B5A)
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#define AQT1000_CDC_RX1_RX_PATH_MIX_CFG (0x00000B5B)
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#define AQT1000_CDC_RX1_RX_VOL_MIX_CTL (0x00000B5C)
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#define AQT1000_CDC_RX1_RX_PATH_SEC0 (0x00000B5D)
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#define AQT1000_CDC_RX1_RX_PATH_SEC1 (0x00000B5E)
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#define AQT1000_CDC_RX1_RX_PATH_SEC2 (0x00000B5F)
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#define AQT1000_CDC_RX1_RX_PATH_SEC3 (0x00000B60)
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#define AQT1000_CDC_RX1_RX_PATH_SEC4 (0x00000B61)
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#define AQT1000_CDC_RX1_RX_PATH_SEC5 (0x00000B62)
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#define AQT1000_CDC_RX1_RX_PATH_SEC6 (0x00000B63)
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#define AQT1000_CDC_RX1_RX_PATH_SEC7 (0x00000B64)
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#define AQT1000_CDC_RX1_RX_PATH_MIX_SEC0 (0x00000B65)
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#define AQT1000_CDC_RX1_RX_PATH_MIX_SEC1 (0x00000B66)
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#define AQT1000_CDC_RX1_RX_PATH_DSMDEM_CTL (0x00000B67)
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#define AQT1000_CDC_RX2_BASE (0x00000B69)
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#define AQT1000_CDC_RX2_RX_PATH_CTL (0x00000B69)
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#define AQT1000_CDC_RX2_RX_PATH_CFG0 (0x00000B6A)
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#define AQT1000_CDC_RX2_RX_PATH_CFG1 (0x00000B6B)
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#define AQT1000_CDC_RX2_RX_PATH_CFG2 (0x00000B6C)
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#define AQT1000_CDC_RX2_RX_VOL_CTL (0x00000B6D)
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#define AQT1000_CDC_RX2_RX_PATH_MIX_CTL (0x00000B6E)
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#define AQT1000_CDC_RX2_RX_PATH_MIX_CFG (0x00000B6F)
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#define AQT1000_CDC_RX2_RX_VOL_MIX_CTL (0x00000B70)
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#define AQT1000_CDC_RX2_RX_PATH_SEC0 (0x00000B71)
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#define AQT1000_CDC_RX2_RX_PATH_SEC1 (0x00000B72)
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#define AQT1000_CDC_RX2_RX_PATH_SEC2 (0x00000B73)
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#define AQT1000_CDC_RX2_RX_PATH_SEC3 (0x00000B74)
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#define AQT1000_CDC_RX2_RX_PATH_SEC4 (0x00000B75)
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#define AQT1000_CDC_RX2_RX_PATH_SEC5 (0x00000B76)
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#define AQT1000_CDC_RX2_RX_PATH_SEC6 (0x00000B77)
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#define AQT1000_CDC_RX2_RX_PATH_SEC7 (0x00000B78)
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#define AQT1000_CDC_RX2_RX_PATH_MIX_SEC0 (0x00000B79)
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#define AQT1000_CDC_RX2_RX_PATH_MIX_SEC1 (0x00000B7A)
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#define AQT1000_CDC_RX2_RX_PATH_DSMDEM_CTL (0x00000B7B)
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#define AQT1000_CDC_EQ_IIR0_BASE (0x00000BD1)
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#define AQT1000_CDC_EQ_IIR0_PATH_CTL (0x00000BD1)
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#define AQT1000_CDC_EQ_IIR0_PATH_CFG0 (0x00000BD2)
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#define AQT1000_CDC_EQ_IIR0_PATH_CFG1 (0x00000BD3)
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#define AQT1000_CDC_EQ_IIR0_PATH_CFG2 (0x00000BD4)
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#define AQT1000_CDC_EQ_IIR0_PATH_CFG3 (0x00000BD5)
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#define AQT1000_CDC_EQ_IIR0_COEF_CFG0 (0x00000BD6)
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#define AQT1000_CDC_EQ_IIR0_COEF_CFG1 (0x00000BD7)
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#define AQT1000_CDC_EQ_IIR1_BASE (0x00000BE1)
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#define AQT1000_CDC_EQ_IIR1_PATH_CTL (0x00000BE1)
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#define AQT1000_CDC_EQ_IIR1_PATH_CFG0 (0x00000BE2)
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#define AQT1000_CDC_EQ_IIR1_PATH_CFG1 (0x00000BE3)
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#define AQT1000_CDC_EQ_IIR1_PATH_CFG2 (0x00000BE4)
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#define AQT1000_CDC_EQ_IIR1_PATH_CFG3 (0x00000BE5)
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#define AQT1000_CDC_EQ_IIR1_COEF_CFG0 (0x00000BE6)
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#define AQT1000_CDC_EQ_IIR1_COEF_CFG1 (0x00000BE7)
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#define AQT1000_PAGE12_BASE (0x00000C00)
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#define AQT1000_PAGE12_PAGE_REGISTER (0x00000C00)
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#define AQT1000_CDC_CLSH_CDC_CLSH_BASE (0x00000C01)
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#define AQT1000_CDC_CLSH_CRC (0x00000C01)
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#define AQT1000_CDC_CLSH_DLY_CTRL (0x00000C02)
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#define AQT1000_CDC_CLSH_DECAY_CTRL (0x00000C03)
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#define AQT1000_CDC_CLSH_HPH_V_PA (0x00000C04)
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#define AQT1000_CDC_CLSH_EAR_V_PA (0x00000C05)
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#define AQT1000_CDC_CLSH_HPH_V_HD (0x00000C06)
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#define AQT1000_CDC_CLSH_EAR_V_HD (0x00000C07)
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#define AQT1000_CDC_CLSH_K1_MSB (0x00000C08)
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#define AQT1000_CDC_CLSH_K1_LSB (0x00000C09)
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#define AQT1000_CDC_CLSH_K2_MSB (0x00000C0A)
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#define AQT1000_CDC_CLSH_K2_LSB (0x00000C0B)
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#define AQT1000_CDC_CLSH_IDLE_CTRL (0x00000C0C)
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#define AQT1000_CDC_CLSH_IDLE_HPH (0x00000C0D)
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#define AQT1000_CDC_CLSH_IDLE_EAR (0x00000C0E)
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#define AQT1000_CDC_CLSH_TEST0 (0x00000C0F)
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#define AQT1000_CDC_CLSH_TEST1 (0x00000C10)
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#define AQT1000_CDC_CLSH_OVR_VREF (0x00000C11)
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#define AQT1000_MIXING_ASRC0_BASE (0x00000C55)
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#define AQT1000_MIXING_ASRC0_CLK_RST_CTL (0x00000C55)
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#define AQT1000_MIXING_ASRC0_CTL0 (0x00000C56)
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#define AQT1000_MIXING_ASRC0_CTL1 (0x00000C57)
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#define AQT1000_MIXING_ASRC0_FIFO_CTL (0x00000C58)
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#define AQT1000_MIXING_ASRC0_STATUS_FMIN_CNTR_LSB (0x00000C59)
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#define AQT1000_MIXING_ASRC0_STATUS_FMIN_CNTR_MSB (0x00000C5A)
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#define AQT1000_MIXING_ASRC0_STATUS_FMAX_CNTR_LSB (0x00000C5B)
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#define AQT1000_MIXING_ASRC0_STATUS_FMAX_CNTR_MSB (0x00000C5C)
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#define AQT1000_MIXING_ASRC0_STATUS_FIFO (0x00000C5D)
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#define AQT1000_MIXING_ASRC1_BASE (0x00000C61)
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#define AQT1000_MIXING_ASRC1_CLK_RST_CTL (0x00000C61)
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#define AQT1000_MIXING_ASRC1_CTL0 (0x00000C62)
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#define AQT1000_MIXING_ASRC1_CTL1 (0x00000C63)
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#define AQT1000_MIXING_ASRC1_FIFO_CTL (0x00000C64)
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#define AQT1000_MIXING_ASRC1_STATUS_FMIN_CNTR_LSB (0x00000C65)
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#define AQT1000_MIXING_ASRC1_STATUS_FMIN_CNTR_MSB (0x00000C66)
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#define AQT1000_MIXING_ASRC1_STATUS_FMAX_CNTR_LSB (0x00000C67)
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#define AQT1000_MIXING_ASRC1_STATUS_FMAX_CNTR_MSB (0x00000C68)
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#define AQT1000_MIXING_ASRC1_STATUS_FIFO (0x00000C69)
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#define AQT1000_CDC_SIDETONE_SRC0_BASE (0x00000CB5)
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#define AQT1000_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL (0x00000CB5)
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#define AQT1000_CDC_SIDETONE_SRC0_ST_SRC_PATH_CFG1 (0x00000CB6)
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#define AQT1000_SIDETONE_ASRC0_BASE (0x00000CBD)
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#define AQT1000_SIDETONE_ASRC0_CLK_RST_CTL (0x00000CBD)
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#define AQT1000_SIDETONE_ASRC0_CTL0 (0x00000CBE)
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#define AQT1000_SIDETONE_ASRC0_CTL1 (0x00000CBF)
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#define AQT1000_SIDETONE_ASRC0_FIFO_CTL (0x00000CC0)
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#define AQT1000_SIDETONE_ASRC0_STATUS_FMIN_CNTR_LSB (0x00000CC1)
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#define AQT1000_SIDETONE_ASRC0_STATUS_FMIN_CNTR_MSB (0x00000CC2)
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#define AQT1000_SIDETONE_ASRC0_STATUS_FMAX_CNTR_LSB (0x00000CC3)
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#define AQT1000_SIDETONE_ASRC0_STATUS_FMAX_CNTR_MSB (0x00000CC4)
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#define AQT1000_SIDETONE_ASRC0_STATUS_FIFO (0x00000CC5)
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#define AQT1000_EC_REF_HQ0_BASE (0x00000CD5)
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#define AQT1000_EC_REF_HQ0_EC_REF_HQ_PATH_CTL (0x00000CD5)
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#define AQT1000_EC_REF_HQ0_EC_REF_HQ_CFG0 (0x00000CD6)
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#define AQT1000_EC_REF_HQ1_BASE (0x00000CDD)
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#define AQT1000_EC_REF_HQ1_EC_REF_HQ_PATH_CTL (0x00000CDD)
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#define AQT1000_EC_REF_HQ1_EC_REF_HQ_CFG0 (0x00000CDE)
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#define AQT1000_EC_ASRC0_BASE (0x00000CE5)
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#define AQT1000_EC_ASRC0_CLK_RST_CTL (0x00000CE5)
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#define AQT1000_EC_ASRC0_CTL0 (0x00000CE6)
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#define AQT1000_EC_ASRC0_CTL1 (0x00000CE7)
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#define AQT1000_EC_ASRC0_FIFO_CTL (0x00000CE8)
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#define AQT1000_EC_ASRC0_STATUS_FMIN_CNTR_LSB (0x00000CE9)
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#define AQT1000_EC_ASRC0_STATUS_FMIN_CNTR_MSB (0x00000CEA)
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#define AQT1000_EC_ASRC0_STATUS_FMAX_CNTR_LSB (0x00000CEB)
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#define AQT1000_EC_ASRC0_STATUS_FMAX_CNTR_MSB (0x00000CEC)
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#define AQT1000_EC_ASRC0_STATUS_FIFO (0x00000CED)
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#define AQT1000_EC_ASRC1_BASE (0x00000CF1)
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#define AQT1000_EC_ASRC1_CLK_RST_CTL (0x00000CF1)
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#define AQT1000_EC_ASRC1_CTL0 (0x00000CF2)
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#define AQT1000_EC_ASRC1_CTL1 (0x00000CF3)
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#define AQT1000_EC_ASRC1_FIFO_CTL (0x00000CF4)
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#define AQT1000_EC_ASRC1_STATUS_FMIN_CNTR_LSB (0x00000CF5)
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#define AQT1000_EC_ASRC1_STATUS_FMIN_CNTR_MSB (0x00000CF6)
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#define AQT1000_EC_ASRC1_STATUS_FMAX_CNTR_LSB (0x00000CF7)
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#define AQT1000_EC_ASRC1_STATUS_FMAX_CNTR_MSB (0x00000CF8)
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#define AQT1000_EC_ASRC1_STATUS_FIFO (0x00000CF9)
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#define AQT1000_PAGE13_BASE (0x00000D00)
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#define AQT1000_PAGE13_PAGE_REGISTER (0x00000D00)
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#define AQT1000_CDC_RX_INP_MUX_CDC_RX_INP_MUX_BASE (0x00000D01)
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#define AQT1000_CDC_RX_INP_MUX_RX_INT1_CFG0 (0x00000D03)
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#define AQT1000_CDC_RX_INP_MUX_RX_INT1_CFG1 (0x00000D04)
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#define AQT1000_CDC_RX_INP_MUX_RX_INT2_CFG0 (0x00000D05)
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#define AQT1000_CDC_RX_INP_MUX_RX_INT2_CFG1 (0x00000D06)
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#define AQT1000_CDC_RX_INP_MUX_EQ_IIR_CFG0 (0x00000D11)
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#define AQT1000_CDC_RX_INP_MUX_DSD_CFG0 (0x00000D12)
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#define AQT1000_CDC_RX_INP_MUX_RX_MIX_CFG0 (0x00000D13)
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#define AQT1000_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0 (0x00000D18)
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#define AQT1000_CDC_RX_INP_MUX_ANC_CFG0 (0x00000D1A)
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#define AQT1000_CDC_RX_INP_MUX_SPLINE_ASRC_CFG0 (0x00000D1B)
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#define AQT1000_CDC_RX_INP_MUX_EC_REF_HQ_CFG0 (0x00000D1C)
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#define AQT1000_CDC_TX_INP_MUX_CDC_TX_INP_MUX_BASE (0x00000D1D)
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#define AQT1000_CDC_TX_INP_MUX_ADC_MUX0_CFG0 (0x00000D1D)
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#define AQT1000_CDC_TX_INP_MUX_ADC_MUX0_CFG1 (0x00000D1E)
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#define AQT1000_CDC_TX_INP_MUX_ADC_MUX1_CFG0 (0x00000D1F)
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#define AQT1000_CDC_TX_INP_MUX_ADC_MUX1_CFG1 (0x00000D20)
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#define AQT1000_CDC_TX_INP_MUX_ADC_MUX2_CFG0 (0x00000D21)
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#define AQT1000_CDC_TX_INP_MUX_ADC_MUX2_CFG1 (0x00000D22)
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#define AQT1000_CDC_TX_INP_MUX_ADC_MUX10_CFG0 (0x00000D29)
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#define AQT1000_CDC_TX_INP_MUX_ADC_MUX10_CFG1 (0x00000D2A)
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#define AQT1000_CDC_TX_INP_MUX_ADC_MUX11_CFG0 (0x00000D2B)
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#define AQT1000_CDC_TX_INP_MUX_ADC_MUX11_CFG1 (0x00000D2C)
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#define AQT1000_CDC_TX_INP_MUX_ADC_MUX12_CFG0 (0x00000D2D)
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#define AQT1000_CDC_TX_INP_MUX_ADC_MUX12_CFG1 (0x00000D2E)
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#define AQT1000_CDC_TX_INP_MUX_ADC_MUX13_CFG0 (0x00000D2F)
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#define AQT1000_CDC_TX_INP_MUX_ADC_MUX13_CFG1 (0x00000D30)
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#define AQT1000_CDC_SIDETONE_IIR_INP_MUX_CDC_SIDETONE_IIR_INP_MUX_BASE (0xD31)
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#define AQT1000_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0 (0x00000D31)
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#define AQT1000_CDC_IF_ROUTER_CDC_IF_ROUTER_BASE (0x00000D3D)
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#define AQT1000_CDC_IF_ROUTER_TX_MUX_CFG0 (0x00000D3D)
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#define AQT1000_CDC_CLK_RST_CTRL_CDC_CLK_RST_CTRL_BASE (0x00000D41)
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#define AQT1000_CDC_CLK_RST_CTRL_MCLK_CONTROL (0x00000D41)
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#define AQT1000_CDC_CLK_RST_CTRL_FS_CNT_CONTROL (0x00000D42)
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#define AQT1000_CDC_CLK_RST_CTRL_DSD_CONTROL (0x00000D44)
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#define AQT1000_CDC_CLK_RST_CTRL_ASRC_SHARE_CONTROL (0x00000D45)
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#define AQT1000_CDC_CLK_RST_CTRL_GFM_CONTROL (0x00000D46)
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#define AQT1000_CDC_CLK_RST_CTRL_I2S_CONTROL (0x00000D47)
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#define AQT1000_CDC_SIDETONE_IIR0_BASE (0x00000D55)
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#define AQT1000_CDC_SIDETONE_IIR0_IIR_PATH_CTL (0x00000D55)
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#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL (0x00000D56)
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#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL (0x00000D57)
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#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL (0x00000D58)
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#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL (0x00000D59)
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#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B5_CTL (0x00000D5A)
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#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B6_CTL (0x00000D5B)
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#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B7_CTL (0x00000D5C)
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#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B8_CTL (0x00000D5D)
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#define AQT1000_CDC_SIDETONE_IIR0_IIR_CTL (0x00000D5E)
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#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL (0x00000D5F)
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#define AQT1000_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL (0x00000D60)
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#define AQT1000_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL (0x00000D61)
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#define AQT1000_CDC_TOP_CDC_TOP_BASE (0x00000D81)
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#define AQT1000_CDC_TOP_TOP_CFG0 (0x00000D81)
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#define AQT1000_CDC_TOP_HPHL_COMP_WR_LSB (0x00000D89)
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#define AQT1000_CDC_TOP_HPHL_COMP_WR_MSB (0x00000D8A)
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#define AQT1000_CDC_TOP_HPHL_COMP_LUT (0x00000D8B)
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#define AQT1000_CDC_TOP_HPHL_COMP_RD_LSB (0x00000D8C)
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#define AQT1000_CDC_TOP_HPHL_COMP_RD_MSB (0x00000D8D)
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#define AQT1000_CDC_TOP_HPHR_COMP_WR_LSB (0x00000D8E)
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#define AQT1000_CDC_TOP_HPHR_COMP_WR_MSB (0x00000D8F)
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#define AQT1000_CDC_TOP_HPHR_COMP_LUT (0x00000D90)
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#define AQT1000_CDC_TOP_HPHR_COMP_RD_LSB (0x00000D91)
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#define AQT1000_CDC_TOP_HPHR_COMP_RD_MSB (0x00000D92)
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#define AQT1000_CDC_DSD0_BASE (0x00000DB1)
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#define AQT1000_CDC_DSD0_PATH_CTL (0x00000DB1)
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#define AQT1000_CDC_DSD0_CFG0 (0x00000DB2)
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#define AQT1000_CDC_DSD0_CFG1 (0x00000DB3)
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#define AQT1000_CDC_DSD0_CFG2 (0x00000DB4)
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#define AQT1000_CDC_DSD0_CFG3 (0x00000DB5)
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#define AQT1000_CDC_DSD0_CFG4 (0x00000DB6)
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#define AQT1000_CDC_DSD0_CFG5 (0x00000DB7)
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#define AQT1000_CDC_DSD1_BASE (0x00000DC1)
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#define AQT1000_CDC_DSD1_PATH_CTL (0x00000DC1)
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#define AQT1000_CDC_DSD1_CFG0 (0x00000DC2)
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#define AQT1000_CDC_DSD1_CFG1 (0x00000DC3)
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#define AQT1000_CDC_DSD1_CFG2 (0x00000DC4)
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#define AQT1000_CDC_DSD1_CFG3 (0x00000DC5)
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#define AQT1000_CDC_DSD1_CFG4 (0x00000DC6)
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#define AQT1000_CDC_DSD1_CFG5 (0x00000DC7)
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#define AQT1000_CDC_RX_IDLE_DET_CDC_RX_IDLE_DET_BASE (0x00000DD1)
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#define AQT1000_CDC_RX_IDLE_DET_PATH_CTL (0x00000DD1)
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#define AQT1000_CDC_RX_IDLE_DET_CFG0 (0x00000DD2)
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#define AQT1000_CDC_RX_IDLE_DET_CFG1 (0x00000DD3)
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#define AQT1000_CDC_RX_IDLE_DET_CFG2 (0x00000DD4)
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#define AQT1000_CDC_RX_IDLE_DET_CFG3 (0x00000DD5)
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#define AQT1000_CDC_DOP_DET_CDC_DOP_DET_BASE (0x00000DD9)
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#define AQT1000_CDC_DOP_DET_CTL (0x00000DD9)
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#define AQT1000_CDC_DOP_DET_CFG0 (0x00000DDA)
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#define AQT1000_CDC_DOP_DET_CFG1 (0x00000DDB)
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#define AQT1000_CDC_DOP_DET_CFG2 (0x00000DDC)
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#define AQT1000_CDC_DOP_DET_CFG3 (0x00000DDD)
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#define AQT1000_CDC_DOP_DET_CFG4 (0x00000DDE)
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#define AQT1000_CDC_DOP_DET_STATUS0 (0x00000DE1)
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#define AQT1000_PAGE15_BASE (0x00000F00)
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#define AQT1000_PAGE15_PAGE_REGISTER (0x00000F00)
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#define AQT1000_CDC_DEBUG_CDC_DEBUG_BASE (0x00000FA1)
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#define AQT1000_CDC_DEBUG_DSD0_DEBUG_CFG0 (0x00000FA1)
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#define AQT1000_CDC_DEBUG_DSD0_DEBUG_CFG1 (0x00000FA2)
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#define AQT1000_CDC_DEBUG_DSD0_DEBUG_CFG2 (0x00000FA3)
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#define AQT1000_CDC_DEBUG_DSD0_DEBUG_CFG3 (0x00000FA4)
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#define AQT1000_CDC_DEBUG_DSD1_DEBUG_CFG0 (0x00000FA5)
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#define AQT1000_CDC_DEBUG_DSD1_DEBUG_CFG1 (0x00000FA6)
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#define AQT1000_CDC_DEBUG_DSD1_DEBUG_CFG2 (0x00000FA7)
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#define AQT1000_CDC_DEBUG_DSD1_DEBUG_CFG3 (0x00000FA8)
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#define AQT1000_CDC_DEBUG_RC_RE_ASRC_DEBUG_CFG0 (0x00000FAB)
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#define AQT1000_CDC_DEBUG_ANC0_RC0_FIFO_CTL (0x00000FAC)
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#define AQT1000_CDC_DEBUG_ANC0_RC1_FIFO_CTL (0x00000FAD)
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#define AQT1000_CDC_DEBUG_ANC1_RC0_FIFO_CTL (0x00000FAE)
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#define AQT1000_CDC_DEBUG_ANC1_RC1_FIFO_CTL (0x00000FAF)
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#define AQT1000_CDC_DEBUG_ANC_RC_RST_DBG_CNTR (0x00000FB0)
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#define AQT1000_PAGE128_BASE (0x00008000)
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#define AQT1000_PAGE128_PAGE_REGISTER (0x00008000)
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#define AQT1000_TLMM_TLMM_BASE (0x00008001)
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#define AQT1000_TLMM_SPI_CLK_PINCFG (0x00008001)
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#define AQT1000_TLMM_SPI_MOSI_PINCFG (0x00008002)
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#define AQT1000_TLMM_SPI_MISO_PINCFG (0x00008003)
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#define AQT1000_TLMM_SPI_CS_N_PINCFG (0x00008004)
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#define AQT1000_TLMM_GPIO1_PINCFG (0x00008005)
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#define AQT1000_TLMM_GPIO2_PINCFG (0x00008006)
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#define AQT1000_TLMM_GPIO3_PINCFG (0x00008007)
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#define AQT1000_TLMM_GPIO4_PINCFG (0x00008008)
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#define AQT1000_TLMM_GPIO5_PINCFG (0x00008009)
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#define AQT1000_TLMM_GPIO6_PINCFG (0x0000800A)
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#define AQT1000_TLMM_GPIO7_PINCFG (0x0000800B)
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#define AQT1000_TLMM_GPIO8_PINCFG (0x0000800C)
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#define AQT1000_TLMM_GPIO9_PINCFG (0x0000800D)
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#define AQT1000_TLMM_GPIO10_PINCFG (0x0000800E)
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#define AQT1000_PAD_CTRL_PAD_CTRL_BASE (0x00008031)
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#define AQT1000_PAD_CTRL_PAD_PDN_CTRL_0 (0x00008031)
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#define AQT1000_PAD_CTRL_PAD_PDN_CTRL_1 (0x00008032)
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#define AQT1000_PAD_CTRL_PAD_PU_CTRL_0 (0x00008033)
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#define AQT1000_PAD_CTRL_PAD_PU_CTRL_1 (0x00008034)
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#define AQT1000_PAD_CTRL_GPIO_CTL_0_OE (0x00008036)
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#define AQT1000_PAD_CTRL_GPIO_CTL_1_OE (0x00008037)
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#define AQT1000_PAD_CTRL_GPIO_CTL_0_DATA (0x00008038)
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#define AQT1000_PAD_CTRL_GPIO_CTL_1_DATA (0x00008039)
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#define AQT1000_PAD_CTRL_PAD_DRVCTL (0x0000803A)
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#define AQT1000_PAD_CTRL_PIN_STATUS (0x0000803B)
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#define AQT1000_PAD_CTRL_MEM_CTRL (0x0000803C)
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#define AQT1000_PAD_CTRL_PAD_INP_DISABLE_0 (0x0000803E)
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#define AQT1000_PAD_CTRL_PAD_INP_DISABLE_1 (0x0000803F)
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#define AQT1000_PAD_CTRL_PIN_CTL_OE_0 (0x00008040)
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#define AQT1000_PAD_CTRL_PIN_CTL_OE_1 (0x00008041)
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#define AQT1000_PAD_CTRL_PIN_CTL_DATA_0 (0x00008042)
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#define AQT1000_PAD_CTRL_PIN_CTL_DATA_1 (0x00008043)
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#define AQT1000_PAD_CTRL_USB_PHY_CLK_DIV (0x00008044)
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#define AQT1000_PAD_CTRL_DEBUG_BUS_CDC (0x00008045)
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#define AQT1000_PAD_CTRL_DEBUG_BUS_SEL (0x00008046)
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#define AQT1000_PAD_CTRL_DEBUG_EN_1 (0x00008047)
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#define AQT1000_PAD_CTRL_DEBUG_EN_2 (0x00008048)
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#define AQT1000_PAD_CTRL_DEBUG_EN_3 (0x00008049)
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#define AQT1000_PAD_CTRL_DEBUG_EN_4 (0x0000804A)
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#define AQT1000_PAD_CTRL_DEBUG_EN_5 (0x0000804B)
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#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_0 (0x0000804C)
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#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_1 (0x0000804D)
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#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_2 (0x0000804E)
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#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_3 (0x0000804F)
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#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_4 (0x00008050)
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#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_5 (0x00008051)
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#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_6 (0x00008052)
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#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_7 (0x00008053)
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#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_8 (0x00008054)
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#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_9 (0x00008055)
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#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_10 (0x00008056)
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#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_11 (0x00008057)
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#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_12 (0x00008058)
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#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_13 (0x00008059)
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#define AQT1000_PAD_CTRL_DEBUG_READ_0 (0x0000805A)
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#define AQT1000_PAD_CTRL_DEBUG_READ_1 (0x0000805B)
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#define AQT1000_PAD_CTRL_DEBUG_READ_2 (0x0000805C)
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#define AQT1000_PAD_CTRL_DEBUG_READ_3 (0x0000805D)
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#define AQT1000_PAD_CTRL_FPGA_CTL (0x00008061)
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#define AQT1000_MAX_REGISTER (0x000080FF)
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#endif /*_AQT_REGISTERS_H*/
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