dp_tx.c 140 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065406640674068406940704071407240734074407540764077407840794080408140824083408440854086408740884089409040914092409340944095409640974098409941004101410241034104410541064107410841094110411141124113411441154116411741184119412041214122412341244125412641274128412941304131413241334134413541364137413841394140414141424143414441454146414741484149415041514152415341544155415641574158415941604161416241634164416541664167416841694170417141724173417441754176417741784179418041814182418341844185418641874188418941904191419241934194419541964197419841994200420142024203420442054206420742084209421042114212421342144215421642174218421942204221422242234224422542264227422842294230423142324233423442354236423742384239424042414242424342444245424642474248424942504251425242534254425542564257425842594260426142624263426442654266426742684269427042714272427342744275427642774278427942804281428242834284428542864287428842894290429142924293429442954296429742984299430043014302430343044305430643074308430943104311431243134314431543164317431843194320432143224323432443254326432743284329433043314332433343344335433643374338433943404341434243434344434543464347434843494350435143524353435443554356435743584359436043614362436343644365436643674368436943704371437243734374437543764377437843794380438143824383438443854386438743884389439043914392439343944395439643974398439944004401440244034404440544064407440844094410441144124413441444154416441744184419442044214422442344244425442644274428442944304431443244334434443544364437443844394440444144424443444444454446444744484449445044514452445344544455445644574458445944604461446244634464446544664467446844694470447144724473447444754476447744784479448044814482448344844485448644874488448944904491449244934494449544964497449844994500450145024503450445054506450745084509451045114512451345144515451645174518451945204521452245234524452545264527452845294530453145324533453445354536453745384539454045414542454345444545454645474548454945504551455245534554455545564557455845594560456145624563456445654566456745684569457045714572457345744575457645774578457945804581458245834584458545864587458845894590459145924593459445954596459745984599460046014602460346044605460646074608460946104611461246134614461546164617461846194620462146224623462446254626462746284629463046314632463346344635463646374638463946404641464246434644464546464647464846494650465146524653465446554656465746584659466046614662466346644665466646674668466946704671467246734674467546764677467846794680468146824683468446854686468746884689469046914692469346944695469646974698469947004701470247034704470547064707470847094710471147124713471447154716471747184719472047214722472347244725472647274728472947304731473247334734473547364737473847394740474147424743474447454746474747484749475047514752475347544755475647574758475947604761476247634764476547664767476847694770477147724773477447754776477747784779478047814782478347844785478647874788478947904791479247934794479547964797479847994800480148024803480448054806480748084809481048114812481348144815481648174818481948204821482248234824482548264827482848294830483148324833483448354836483748384839484048414842484348444845484648474848484948504851485248534854485548564857485848594860486148624863486448654866486748684869487048714872487348744875487648774878487948804881488248834884488548864887488848894890489148924893489448954896489748984899490049014902490349044905490649074908490949104911491249134914491549164917491849194920492149224923492449254926492749284929493049314932493349344935493649374938493949404941494249434944494549464947494849494950495149524953495449554956495749584959496049614962496349644965496649674968496949704971497249734974497549764977497849794980498149824983498449854986498749884989499049914992499349944995499649974998499950005001500250035004500550065007500850095010501150125013501450155016501750185019502050215022502350245025502650275028502950305031503250335034503550365037503850395040504150425043504450455046504750485049505050515052505350545055505650575058505950605061506250635064506550665067506850695070507150725073507450755076507750785079508050815082508350845085508650875088508950905091509250935094509550965097509850995100510151025103510451055106510751085109511051115112511351145115511651175118511951205121512251235124512551265127512851295130513151325133513451355136513751385139514051415142514351445145514651475148514951505151515251535154515551565157515851595160516151625163516451655166516751685169517051715172517351745175517651775178517951805181518251835184518551865187518851895190519151925193519451955196519751985199520052015202520352045205520652075208520952105211521252135214521552165217521852195220522152225223522452255226522752285229523052315232523352345235523652375238523952405241524252435244524552465247524852495250525152525253525452555256525752585259526052615262526352645265526652675268526952705271527252735274527552765277527852795280528152825283528452855286
  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #include "dp_ipa.h"
  31. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  32. #include "if_meta_hdr.h"
  33. #endif
  34. #include "enet.h"
  35. #include "dp_internal.h"
  36. #ifdef FEATURE_WDS
  37. #include "dp_txrx_wds.h"
  38. #endif
  39. #ifdef ATH_SUPPORT_IQUE
  40. #include "dp_txrx_me.h"
  41. #endif
  42. #include "dp_hist.h"
  43. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  44. #include <dp_swlm.h>
  45. #endif
  46. /* Flag to skip CCE classify when mesh or tid override enabled */
  47. #define DP_TX_SKIP_CCE_CLASSIFY \
  48. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  49. /* TODO Add support in TSO */
  50. #define DP_DESC_NUM_FRAG(x) 0
  51. /* disable TQM_BYPASS */
  52. #define TQM_BYPASS_WAR 0
  53. /* invalid peer id for reinject*/
  54. #define DP_INVALID_PEER 0XFFFE
  55. /*mapping between hal encrypt type and cdp_sec_type*/
  56. #define MAX_CDP_SEC_TYPE 12
  57. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  58. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  59. HAL_TX_ENCRYPT_TYPE_WEP_128,
  60. HAL_TX_ENCRYPT_TYPE_WEP_104,
  61. HAL_TX_ENCRYPT_TYPE_WEP_40,
  62. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  63. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  64. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  65. HAL_TX_ENCRYPT_TYPE_WAPI,
  66. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  67. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  68. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  69. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  70. #ifdef CONFIG_WLAN_SYSFS_MEM_STATS
  71. /**
  72. * dp_update_tx_desc_stats - Update the increase or decrease in
  73. * outstanding tx desc count
  74. * values on pdev and soc
  75. * @vdev: DP pdev handle
  76. *
  77. * Return: void
  78. */
  79. static inline void
  80. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  81. {
  82. int32_t tx_descs_cnt =
  83. qdf_atomic_read(&pdev->num_tx_outstanding);
  84. if (pdev->tx_descs_max < tx_descs_cnt)
  85. pdev->tx_descs_max = tx_descs_cnt;
  86. qdf_mem_tx_desc_cnt_update(pdev->num_tx_outstanding,
  87. pdev->tx_descs_max);
  88. }
  89. #else /* CONFIG_WLAN_SYSFS_MEM_STATS */
  90. static inline void
  91. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  92. {
  93. }
  94. #endif /* CONFIG_WLAN_SYSFS_MEM_STATS */
  95. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  96. static inline
  97. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  98. {
  99. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  100. QDF_DMA_TO_DEVICE,
  101. desc->nbuf->len);
  102. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  103. }
  104. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  105. {
  106. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  107. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  108. QDF_DMA_TO_DEVICE,
  109. desc->nbuf->len);
  110. }
  111. #else
  112. static inline
  113. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  114. {
  115. }
  116. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  117. {
  118. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  119. QDF_DMA_TO_DEVICE, desc->nbuf->len);
  120. }
  121. #endif
  122. #ifdef QCA_TX_LIMIT_CHECK
  123. /**
  124. * dp_tx_limit_check - Check if allocated tx descriptors reached
  125. * soc max limit and pdev max limit
  126. * @vdev: DP vdev handle
  127. *
  128. * Return: true if allocated tx descriptors reached max configured value, else
  129. * false
  130. */
  131. static inline bool
  132. dp_tx_limit_check(struct dp_vdev *vdev)
  133. {
  134. struct dp_pdev *pdev = vdev->pdev;
  135. struct dp_soc *soc = pdev->soc;
  136. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  137. soc->num_tx_allowed) {
  138. dp_tx_info("queued packets are more than max tx, drop the frame");
  139. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  140. return true;
  141. }
  142. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  143. pdev->num_tx_allowed) {
  144. dp_tx_info("queued packets are more than max tx, drop the frame");
  145. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  146. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_outstand.num, 1);
  147. return true;
  148. }
  149. return false;
  150. }
  151. /**
  152. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  153. * reached soc max limit
  154. * @vdev: DP vdev handle
  155. *
  156. * Return: true if allocated tx descriptors reached max configured value, else
  157. * false
  158. */
  159. static inline bool
  160. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  161. {
  162. struct dp_pdev *pdev = vdev->pdev;
  163. struct dp_soc *soc = pdev->soc;
  164. if (qdf_atomic_read(&soc->num_tx_exception) >=
  165. soc->num_msdu_exception_desc) {
  166. dp_info("exc packets are more than max drop the exc pkt");
  167. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  168. return true;
  169. }
  170. return false;
  171. }
  172. /**
  173. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  174. * @vdev: DP pdev handle
  175. *
  176. * Return: void
  177. */
  178. static inline void
  179. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  180. {
  181. struct dp_soc *soc = pdev->soc;
  182. qdf_atomic_inc(&pdev->num_tx_outstanding);
  183. qdf_atomic_inc(&soc->num_tx_outstanding);
  184. dp_update_tx_desc_stats(pdev);
  185. }
  186. /**
  187. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  188. * @vdev: DP pdev handle
  189. *
  190. * Return: void
  191. */
  192. static inline void
  193. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  194. {
  195. struct dp_soc *soc = pdev->soc;
  196. qdf_atomic_dec(&pdev->num_tx_outstanding);
  197. qdf_atomic_dec(&soc->num_tx_outstanding);
  198. dp_update_tx_desc_stats(pdev);
  199. }
  200. #else //QCA_TX_LIMIT_CHECK
  201. static inline bool
  202. dp_tx_limit_check(struct dp_vdev *vdev)
  203. {
  204. return false;
  205. }
  206. static inline bool
  207. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  208. {
  209. return false;
  210. }
  211. static inline void
  212. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  213. {
  214. qdf_atomic_inc(&pdev->num_tx_outstanding);
  215. dp_update_tx_desc_stats(pdev);
  216. }
  217. static inline void
  218. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  219. {
  220. qdf_atomic_dec(&pdev->num_tx_outstanding);
  221. dp_update_tx_desc_stats(pdev);
  222. }
  223. #endif //QCA_TX_LIMIT_CHECK
  224. #if defined(FEATURE_TSO)
  225. /**
  226. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  227. *
  228. * @soc - core txrx main context
  229. * @seg_desc - tso segment descriptor
  230. * @num_seg_desc - tso number segment descriptor
  231. */
  232. static void dp_tx_tso_unmap_segment(
  233. struct dp_soc *soc,
  234. struct qdf_tso_seg_elem_t *seg_desc,
  235. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  236. {
  237. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  238. if (qdf_unlikely(!seg_desc)) {
  239. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  240. __func__, __LINE__);
  241. qdf_assert(0);
  242. } else if (qdf_unlikely(!num_seg_desc)) {
  243. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  244. __func__, __LINE__);
  245. qdf_assert(0);
  246. } else {
  247. bool is_last_seg;
  248. /* no tso segment left to do dma unmap */
  249. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  250. return;
  251. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  252. true : false;
  253. qdf_nbuf_unmap_tso_segment(soc->osdev,
  254. seg_desc, is_last_seg);
  255. num_seg_desc->num_seg.tso_cmn_num_seg--;
  256. }
  257. }
  258. /**
  259. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  260. * back to the freelist
  261. *
  262. * @soc - soc device handle
  263. * @tx_desc - Tx software descriptor
  264. */
  265. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  266. struct dp_tx_desc_s *tx_desc)
  267. {
  268. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  269. if (qdf_unlikely(!tx_desc->tso_desc)) {
  270. dp_tx_err("SO desc is NULL!");
  271. qdf_assert(0);
  272. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  273. dp_tx_err("TSO num desc is NULL!");
  274. qdf_assert(0);
  275. } else {
  276. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  277. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  278. /* Add the tso num segment into the free list */
  279. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  280. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  281. tx_desc->tso_num_desc);
  282. tx_desc->tso_num_desc = NULL;
  283. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  284. }
  285. /* Add the tso segment into the free list*/
  286. dp_tx_tso_desc_free(soc,
  287. tx_desc->pool_id, tx_desc->tso_desc);
  288. tx_desc->tso_desc = NULL;
  289. }
  290. }
  291. #else
  292. static void dp_tx_tso_unmap_segment(
  293. struct dp_soc *soc,
  294. struct qdf_tso_seg_elem_t *seg_desc,
  295. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  296. {
  297. }
  298. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  299. struct dp_tx_desc_s *tx_desc)
  300. {
  301. }
  302. #endif
  303. /**
  304. * dp_tx_desc_release() - Release Tx Descriptor
  305. * @tx_desc : Tx Descriptor
  306. * @desc_pool_id: Descriptor Pool ID
  307. *
  308. * Deallocate all resources attached to Tx descriptor and free the Tx
  309. * descriptor.
  310. *
  311. * Return:
  312. */
  313. static void
  314. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  315. {
  316. struct dp_pdev *pdev = tx_desc->pdev;
  317. struct dp_soc *soc;
  318. uint8_t comp_status = 0;
  319. qdf_assert(pdev);
  320. soc = pdev->soc;
  321. dp_tx_outstanding_dec(pdev);
  322. if (tx_desc->frm_type == dp_tx_frm_tso)
  323. dp_tx_tso_desc_release(soc, tx_desc);
  324. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  325. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  326. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  327. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  328. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  329. qdf_atomic_dec(&soc->num_tx_exception);
  330. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  331. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  332. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  333. soc->hal_soc);
  334. else
  335. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  336. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  337. tx_desc->id, comp_status,
  338. qdf_atomic_read(&pdev->num_tx_outstanding));
  339. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  340. return;
  341. }
  342. /**
  343. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  344. * @vdev: DP vdev Handle
  345. * @nbuf: skb
  346. * @msdu_info: msdu_info required to create HTT metadata
  347. *
  348. * Prepares and fills HTT metadata in the frame pre-header for special frames
  349. * that should be transmitted using varying transmit parameters.
  350. * There are 2 VDEV modes that currently needs this special metadata -
  351. * 1) Mesh Mode
  352. * 2) DSRC Mode
  353. *
  354. * Return: HTT metadata size
  355. *
  356. */
  357. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  358. struct dp_tx_msdu_info_s *msdu_info)
  359. {
  360. uint32_t *meta_data = msdu_info->meta_data;
  361. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  362. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  363. uint8_t htt_desc_size;
  364. /* Size rounded of multiple of 8 bytes */
  365. uint8_t htt_desc_size_aligned;
  366. uint8_t *hdr = NULL;
  367. /*
  368. * Metadata - HTT MSDU Extension header
  369. */
  370. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  371. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  372. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  373. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  374. meta_data[0])) {
  375. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  376. htt_desc_size_aligned)) {
  377. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  378. htt_desc_size_aligned);
  379. if (!nbuf) {
  380. /*
  381. * qdf_nbuf_realloc_headroom won't do skb_clone
  382. * as skb_realloc_headroom does. so, no free is
  383. * needed here.
  384. */
  385. DP_STATS_INC(vdev,
  386. tx_i.dropped.headroom_insufficient,
  387. 1);
  388. qdf_print(" %s[%d] skb_realloc_headroom failed",
  389. __func__, __LINE__);
  390. return 0;
  391. }
  392. }
  393. /* Fill and add HTT metaheader */
  394. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  395. if (!hdr) {
  396. dp_tx_err("Error in filling HTT metadata");
  397. return 0;
  398. }
  399. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  400. } else if (vdev->opmode == wlan_op_mode_ocb) {
  401. /* Todo - Add support for DSRC */
  402. }
  403. return htt_desc_size_aligned;
  404. }
  405. /**
  406. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  407. * @tso_seg: TSO segment to process
  408. * @ext_desc: Pointer to MSDU extension descriptor
  409. *
  410. * Return: void
  411. */
  412. #if defined(FEATURE_TSO)
  413. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  414. void *ext_desc)
  415. {
  416. uint8_t num_frag;
  417. uint32_t tso_flags;
  418. /*
  419. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  420. * tcp_flag_mask
  421. *
  422. * Checksum enable flags are set in TCL descriptor and not in Extension
  423. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  424. */
  425. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  426. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  427. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  428. tso_seg->tso_flags.ip_len);
  429. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  430. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  431. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  432. uint32_t lo = 0;
  433. uint32_t hi = 0;
  434. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  435. (tso_seg->tso_frags[num_frag].length));
  436. qdf_dmaaddr_to_32s(
  437. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  438. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  439. tso_seg->tso_frags[num_frag].length);
  440. }
  441. return;
  442. }
  443. #else
  444. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  445. void *ext_desc)
  446. {
  447. return;
  448. }
  449. #endif
  450. #if defined(FEATURE_TSO)
  451. /**
  452. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  453. * allocated and free them
  454. *
  455. * @soc: soc handle
  456. * @free_seg: list of tso segments
  457. * @msdu_info: msdu descriptor
  458. *
  459. * Return - void
  460. */
  461. static void dp_tx_free_tso_seg_list(
  462. struct dp_soc *soc,
  463. struct qdf_tso_seg_elem_t *free_seg,
  464. struct dp_tx_msdu_info_s *msdu_info)
  465. {
  466. struct qdf_tso_seg_elem_t *next_seg;
  467. while (free_seg) {
  468. next_seg = free_seg->next;
  469. dp_tx_tso_desc_free(soc,
  470. msdu_info->tx_queue.desc_pool_id,
  471. free_seg);
  472. free_seg = next_seg;
  473. }
  474. }
  475. /**
  476. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  477. * allocated and free them
  478. *
  479. * @soc: soc handle
  480. * @free_num_seg: list of tso number segments
  481. * @msdu_info: msdu descriptor
  482. * Return - void
  483. */
  484. static void dp_tx_free_tso_num_seg_list(
  485. struct dp_soc *soc,
  486. struct qdf_tso_num_seg_elem_t *free_num_seg,
  487. struct dp_tx_msdu_info_s *msdu_info)
  488. {
  489. struct qdf_tso_num_seg_elem_t *next_num_seg;
  490. while (free_num_seg) {
  491. next_num_seg = free_num_seg->next;
  492. dp_tso_num_seg_free(soc,
  493. msdu_info->tx_queue.desc_pool_id,
  494. free_num_seg);
  495. free_num_seg = next_num_seg;
  496. }
  497. }
  498. /**
  499. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  500. * do dma unmap for each segment
  501. *
  502. * @soc: soc handle
  503. * @free_seg: list of tso segments
  504. * @num_seg_desc: tso number segment descriptor
  505. *
  506. * Return - void
  507. */
  508. static void dp_tx_unmap_tso_seg_list(
  509. struct dp_soc *soc,
  510. struct qdf_tso_seg_elem_t *free_seg,
  511. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  512. {
  513. struct qdf_tso_seg_elem_t *next_seg;
  514. if (qdf_unlikely(!num_seg_desc)) {
  515. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  516. return;
  517. }
  518. while (free_seg) {
  519. next_seg = free_seg->next;
  520. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  521. free_seg = next_seg;
  522. }
  523. }
  524. #ifdef FEATURE_TSO_STATS
  525. /**
  526. * dp_tso_get_stats_idx: Retrieve the tso packet id
  527. * @pdev - pdev handle
  528. *
  529. * Return: id
  530. */
  531. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  532. {
  533. uint32_t stats_idx;
  534. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  535. % CDP_MAX_TSO_PACKETS);
  536. return stats_idx;
  537. }
  538. #else
  539. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  540. {
  541. return 0;
  542. }
  543. #endif /* FEATURE_TSO_STATS */
  544. /**
  545. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  546. * free the tso segments descriptor and
  547. * tso num segments descriptor
  548. *
  549. * @soc: soc handle
  550. * @msdu_info: msdu descriptor
  551. * @tso_seg_unmap: flag to show if dma unmap is necessary
  552. *
  553. * Return - void
  554. */
  555. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  556. struct dp_tx_msdu_info_s *msdu_info,
  557. bool tso_seg_unmap)
  558. {
  559. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  560. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  561. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  562. tso_info->tso_num_seg_list;
  563. /* do dma unmap for each segment */
  564. if (tso_seg_unmap)
  565. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  566. /* free all tso number segment descriptor though looks only have 1 */
  567. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  568. /* free all tso segment descriptor */
  569. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  570. }
  571. /**
  572. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  573. * @vdev: virtual device handle
  574. * @msdu: network buffer
  575. * @msdu_info: meta data associated with the msdu
  576. *
  577. * Return: QDF_STATUS_SUCCESS success
  578. */
  579. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  580. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  581. {
  582. struct qdf_tso_seg_elem_t *tso_seg;
  583. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  584. struct dp_soc *soc = vdev->pdev->soc;
  585. struct dp_pdev *pdev = vdev->pdev;
  586. struct qdf_tso_info_t *tso_info;
  587. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  588. tso_info = &msdu_info->u.tso_info;
  589. tso_info->curr_seg = NULL;
  590. tso_info->tso_seg_list = NULL;
  591. tso_info->num_segs = num_seg;
  592. msdu_info->frm_type = dp_tx_frm_tso;
  593. tso_info->tso_num_seg_list = NULL;
  594. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  595. while (num_seg) {
  596. tso_seg = dp_tx_tso_desc_alloc(
  597. soc, msdu_info->tx_queue.desc_pool_id);
  598. if (tso_seg) {
  599. tso_seg->next = tso_info->tso_seg_list;
  600. tso_info->tso_seg_list = tso_seg;
  601. num_seg--;
  602. } else {
  603. dp_err_rl("Failed to alloc tso seg desc");
  604. DP_STATS_INC_PKT(vdev->pdev,
  605. tso_stats.tso_no_mem_dropped, 1,
  606. qdf_nbuf_len(msdu));
  607. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  608. return QDF_STATUS_E_NOMEM;
  609. }
  610. }
  611. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  612. tso_num_seg = dp_tso_num_seg_alloc(soc,
  613. msdu_info->tx_queue.desc_pool_id);
  614. if (tso_num_seg) {
  615. tso_num_seg->next = tso_info->tso_num_seg_list;
  616. tso_info->tso_num_seg_list = tso_num_seg;
  617. } else {
  618. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  619. __func__);
  620. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  621. return QDF_STATUS_E_NOMEM;
  622. }
  623. msdu_info->num_seg =
  624. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  625. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  626. msdu_info->num_seg);
  627. if (!(msdu_info->num_seg)) {
  628. /*
  629. * Free allocated TSO seg desc and number seg desc,
  630. * do unmap for segments if dma map has done.
  631. */
  632. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  633. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  634. return QDF_STATUS_E_INVAL;
  635. }
  636. tso_info->curr_seg = tso_info->tso_seg_list;
  637. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  638. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  639. msdu, msdu_info->num_seg);
  640. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  641. tso_info->msdu_stats_idx);
  642. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  643. return QDF_STATUS_SUCCESS;
  644. }
  645. #else
  646. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  647. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  648. {
  649. return QDF_STATUS_E_NOMEM;
  650. }
  651. #endif
  652. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  653. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  654. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  655. /**
  656. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  657. * @vdev: DP Vdev handle
  658. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  659. * @desc_pool_id: Descriptor Pool ID
  660. *
  661. * Return:
  662. */
  663. static
  664. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  665. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  666. {
  667. uint8_t i;
  668. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  669. struct dp_tx_seg_info_s *seg_info;
  670. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  671. struct dp_soc *soc = vdev->pdev->soc;
  672. /* Allocate an extension descriptor */
  673. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  674. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  675. if (!msdu_ext_desc) {
  676. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  677. return NULL;
  678. }
  679. if (msdu_info->exception_fw &&
  680. qdf_unlikely(vdev->mesh_vdev)) {
  681. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  682. &msdu_info->meta_data[0],
  683. sizeof(struct htt_tx_msdu_desc_ext2_t));
  684. qdf_atomic_inc(&soc->num_tx_exception);
  685. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  686. }
  687. switch (msdu_info->frm_type) {
  688. case dp_tx_frm_sg:
  689. case dp_tx_frm_me:
  690. case dp_tx_frm_raw:
  691. seg_info = msdu_info->u.sg_info.curr_seg;
  692. /* Update the buffer pointers in MSDU Extension Descriptor */
  693. for (i = 0; i < seg_info->frag_cnt; i++) {
  694. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  695. seg_info->frags[i].paddr_lo,
  696. seg_info->frags[i].paddr_hi,
  697. seg_info->frags[i].len);
  698. }
  699. break;
  700. case dp_tx_frm_tso:
  701. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  702. &cached_ext_desc[0]);
  703. break;
  704. default:
  705. break;
  706. }
  707. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  708. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  709. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  710. msdu_ext_desc->vaddr);
  711. return msdu_ext_desc;
  712. }
  713. /**
  714. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  715. *
  716. * @skb: skb to be traced
  717. * @msdu_id: msdu_id of the packet
  718. * @vdev_id: vdev_id of the packet
  719. *
  720. * Return: None
  721. */
  722. #ifdef DP_DISABLE_TX_PKT_TRACE
  723. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  724. uint8_t vdev_id)
  725. {
  726. }
  727. #else
  728. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  729. uint8_t vdev_id)
  730. {
  731. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  732. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  733. DPTRACE(qdf_dp_trace_ptr(skb,
  734. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  735. QDF_TRACE_DEFAULT_PDEV_ID,
  736. qdf_nbuf_data_addr(skb),
  737. sizeof(qdf_nbuf_data(skb)),
  738. msdu_id, vdev_id, 0));
  739. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  740. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  741. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  742. msdu_id, QDF_TX));
  743. }
  744. #endif
  745. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  746. /**
  747. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  748. * exception by the upper layer (OS_IF)
  749. * @soc: DP soc handle
  750. * @nbuf: packet to be transmitted
  751. *
  752. * Returns: 1 if the packet is marked as exception,
  753. * 0, if the packet is not marked as exception.
  754. */
  755. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  756. qdf_nbuf_t nbuf)
  757. {
  758. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  759. }
  760. #else
  761. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  762. qdf_nbuf_t nbuf)
  763. {
  764. return 0;
  765. }
  766. #endif
  767. /**
  768. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  769. * @vdev: DP vdev handle
  770. * @nbuf: skb
  771. * @desc_pool_id: Descriptor pool ID
  772. * @meta_data: Metadata to the fw
  773. * @tx_exc_metadata: Handle that holds exception path metadata
  774. * Allocate and prepare Tx descriptor with msdu information.
  775. *
  776. * Return: Pointer to Tx Descriptor on success,
  777. * NULL on failure
  778. */
  779. static
  780. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  781. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  782. struct dp_tx_msdu_info_s *msdu_info,
  783. struct cdp_tx_exception_metadata *tx_exc_metadata)
  784. {
  785. uint8_t align_pad;
  786. uint8_t is_exception = 0;
  787. uint8_t htt_hdr_size;
  788. struct dp_tx_desc_s *tx_desc;
  789. struct dp_pdev *pdev = vdev->pdev;
  790. struct dp_soc *soc = pdev->soc;
  791. if (dp_tx_limit_check(vdev))
  792. return NULL;
  793. /* Allocate software Tx descriptor */
  794. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  795. if (qdf_unlikely(!tx_desc)) {
  796. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  797. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  798. return NULL;
  799. }
  800. dp_tx_outstanding_inc(pdev);
  801. /* Initialize the SW tx descriptor */
  802. tx_desc->nbuf = nbuf;
  803. tx_desc->frm_type = dp_tx_frm_std;
  804. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  805. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  806. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  807. tx_desc->vdev_id = vdev->vdev_id;
  808. tx_desc->pdev = pdev;
  809. tx_desc->msdu_ext_desc = NULL;
  810. tx_desc->pkt_offset = 0;
  811. tx_desc->length = qdf_nbuf_headlen(nbuf);
  812. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  813. if (qdf_unlikely(vdev->multipass_en)) {
  814. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  815. goto failure;
  816. }
  817. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  818. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  819. is_exception = 1;
  820. /*
  821. * For special modes (vdev_type == ocb or mesh), data frames should be
  822. * transmitted using varying transmit parameters (tx spec) which include
  823. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  824. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  825. * These frames are sent as exception packets to firmware.
  826. *
  827. * HW requirement is that metadata should always point to a
  828. * 8-byte aligned address. So we add alignment pad to start of buffer.
  829. * HTT Metadata should be ensured to be multiple of 8-bytes,
  830. * to get 8-byte aligned start address along with align_pad added
  831. *
  832. * |-----------------------------|
  833. * | |
  834. * |-----------------------------| <-----Buffer Pointer Address given
  835. * | | ^ in HW descriptor (aligned)
  836. * | HTT Metadata | |
  837. * | | |
  838. * | | | Packet Offset given in descriptor
  839. * | | |
  840. * |-----------------------------| |
  841. * | Alignment Pad | v
  842. * |-----------------------------| <----- Actual buffer start address
  843. * | SKB Data | (Unaligned)
  844. * | |
  845. * | |
  846. * | |
  847. * | |
  848. * | |
  849. * |-----------------------------|
  850. */
  851. if (qdf_unlikely((msdu_info->exception_fw)) ||
  852. (vdev->opmode == wlan_op_mode_ocb) ||
  853. (tx_exc_metadata &&
  854. tx_exc_metadata->is_tx_sniffer)) {
  855. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  856. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  857. DP_STATS_INC(vdev,
  858. tx_i.dropped.headroom_insufficient, 1);
  859. goto failure;
  860. }
  861. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  862. dp_tx_err("qdf_nbuf_push_head failed");
  863. goto failure;
  864. }
  865. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  866. msdu_info);
  867. if (htt_hdr_size == 0)
  868. goto failure;
  869. tx_desc->length = qdf_nbuf_headlen(nbuf);
  870. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  871. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  872. is_exception = 1;
  873. tx_desc->length -= tx_desc->pkt_offset;
  874. }
  875. #if !TQM_BYPASS_WAR
  876. if (is_exception || tx_exc_metadata)
  877. #endif
  878. {
  879. /* Temporary WAR due to TQM VP issues */
  880. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  881. qdf_atomic_inc(&soc->num_tx_exception);
  882. }
  883. return tx_desc;
  884. failure:
  885. dp_tx_desc_release(tx_desc, desc_pool_id);
  886. return NULL;
  887. }
  888. /**
  889. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  890. * @vdev: DP vdev handle
  891. * @nbuf: skb
  892. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  893. * @desc_pool_id : Descriptor Pool ID
  894. *
  895. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  896. * information. For frames wth fragments, allocate and prepare
  897. * an MSDU extension descriptor
  898. *
  899. * Return: Pointer to Tx Descriptor on success,
  900. * NULL on failure
  901. */
  902. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  903. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  904. uint8_t desc_pool_id)
  905. {
  906. struct dp_tx_desc_s *tx_desc;
  907. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  908. struct dp_pdev *pdev = vdev->pdev;
  909. struct dp_soc *soc = pdev->soc;
  910. if (dp_tx_limit_check(vdev))
  911. return NULL;
  912. /* Allocate software Tx descriptor */
  913. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  914. if (!tx_desc) {
  915. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  916. return NULL;
  917. }
  918. dp_tx_outstanding_inc(pdev);
  919. /* Initialize the SW tx descriptor */
  920. tx_desc->nbuf = nbuf;
  921. tx_desc->frm_type = msdu_info->frm_type;
  922. tx_desc->tx_encap_type = vdev->tx_encap_type;
  923. tx_desc->vdev_id = vdev->vdev_id;
  924. tx_desc->pdev = pdev;
  925. tx_desc->pkt_offset = 0;
  926. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  927. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  928. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  929. /* Handle scattered frames - TSO/SG/ME */
  930. /* Allocate and prepare an extension descriptor for scattered frames */
  931. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  932. if (!msdu_ext_desc) {
  933. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  934. goto failure;
  935. }
  936. #if TQM_BYPASS_WAR
  937. /* Temporary WAR due to TQM VP issues */
  938. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  939. qdf_atomic_inc(&soc->num_tx_exception);
  940. #endif
  941. if (qdf_unlikely(msdu_info->exception_fw))
  942. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  943. tx_desc->msdu_ext_desc = msdu_ext_desc;
  944. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  945. tx_desc->dma_addr = msdu_ext_desc->paddr;
  946. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  947. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  948. else
  949. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  950. return tx_desc;
  951. failure:
  952. dp_tx_desc_release(tx_desc, desc_pool_id);
  953. return NULL;
  954. }
  955. /**
  956. * dp_tx_prepare_raw() - Prepare RAW packet TX
  957. * @vdev: DP vdev handle
  958. * @nbuf: buffer pointer
  959. * @seg_info: Pointer to Segment info Descriptor to be prepared
  960. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  961. * descriptor
  962. *
  963. * Return:
  964. */
  965. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  966. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  967. {
  968. qdf_nbuf_t curr_nbuf = NULL;
  969. uint16_t total_len = 0;
  970. qdf_dma_addr_t paddr;
  971. int32_t i;
  972. int32_t mapped_buf_num = 0;
  973. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  974. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  975. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  976. /* Continue only if frames are of DATA type */
  977. if (!DP_FRAME_IS_DATA(qos_wh)) {
  978. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  979. dp_tx_debug("Pkt. recd is of not data type");
  980. goto error;
  981. }
  982. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  983. if (vdev->raw_mode_war &&
  984. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  985. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  986. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  987. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  988. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  989. /*
  990. * Number of nbuf's must not exceed the size of the frags
  991. * array in seg_info.
  992. */
  993. if (i >= DP_TX_MAX_NUM_FRAGS) {
  994. dp_err_rl("nbuf cnt exceeds the max number of segs");
  995. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  996. goto error;
  997. }
  998. if (QDF_STATUS_SUCCESS !=
  999. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1000. curr_nbuf,
  1001. QDF_DMA_TO_DEVICE,
  1002. curr_nbuf->len)) {
  1003. dp_tx_err("%s dma map error ", __func__);
  1004. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1005. goto error;
  1006. }
  1007. /* Update the count of mapped nbuf's */
  1008. mapped_buf_num++;
  1009. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1010. seg_info->frags[i].paddr_lo = paddr;
  1011. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1012. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1013. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1014. total_len += qdf_nbuf_len(curr_nbuf);
  1015. }
  1016. seg_info->frag_cnt = i;
  1017. seg_info->total_len = total_len;
  1018. seg_info->next = NULL;
  1019. sg_info->curr_seg = seg_info;
  1020. msdu_info->frm_type = dp_tx_frm_raw;
  1021. msdu_info->num_seg = 1;
  1022. return nbuf;
  1023. error:
  1024. i = 0;
  1025. while (nbuf) {
  1026. curr_nbuf = nbuf;
  1027. if (i < mapped_buf_num) {
  1028. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1029. QDF_DMA_TO_DEVICE,
  1030. curr_nbuf->len);
  1031. i++;
  1032. }
  1033. nbuf = qdf_nbuf_next(nbuf);
  1034. qdf_nbuf_free(curr_nbuf);
  1035. }
  1036. return NULL;
  1037. }
  1038. /**
  1039. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1040. * @soc: DP soc handle
  1041. * @nbuf: Buffer pointer
  1042. *
  1043. * unmap the chain of nbufs that belong to this RAW frame.
  1044. *
  1045. * Return: None
  1046. */
  1047. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1048. qdf_nbuf_t nbuf)
  1049. {
  1050. qdf_nbuf_t cur_nbuf = nbuf;
  1051. do {
  1052. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1053. QDF_DMA_TO_DEVICE,
  1054. cur_nbuf->len);
  1055. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1056. } while (cur_nbuf);
  1057. }
  1058. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1059. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, nbuf) \
  1060. { \
  1061. qdf_nbuf_t nbuf_local; \
  1062. struct dp_vdev *vdev_local = vdev_hdl; \
  1063. do { \
  1064. if (qdf_likely(!((vdev_local)->peer_protocol_count_track))) \
  1065. break; \
  1066. nbuf_local = nbuf; \
  1067. if (qdf_unlikely(((vdev_local)->tx_encap_type) == \
  1068. htt_cmn_pkt_type_raw)) \
  1069. break; \
  1070. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local)))) \
  1071. break; \
  1072. else if (qdf_nbuf_is_tso((nbuf_local))) \
  1073. break; \
  1074. dp_vdev_peer_stats_update_protocol_cnt((vdev_local), \
  1075. (nbuf_local), \
  1076. NULL, 1, 0); \
  1077. } while (0); \
  1078. }
  1079. #else
  1080. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, skb)
  1081. #endif
  1082. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1083. /**
  1084. * dp_tx_update_stats() - Update soc level tx stats
  1085. * @soc: DP soc handle
  1086. * @nbuf: packet being transmitted
  1087. *
  1088. * Returns: none
  1089. */
  1090. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1091. qdf_nbuf_t nbuf)
  1092. {
  1093. DP_STATS_INC_PKT(soc, tx.egress, 1, qdf_nbuf_len(nbuf));
  1094. }
  1095. /**
  1096. * dp_tx_attempt_coalescing() - Check and attempt TCL register write coalescing
  1097. * @soc: Datapath soc handle
  1098. * @tx_desc: tx packet descriptor
  1099. * @tid: TID for pkt transmission
  1100. *
  1101. * Returns: 1, if coalescing is to be done
  1102. * 0, if coalescing is not to be done
  1103. */
  1104. static inline int
  1105. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1106. struct dp_tx_desc_s *tx_desc,
  1107. uint8_t tid)
  1108. {
  1109. struct dp_swlm *swlm = &soc->swlm;
  1110. union swlm_data swlm_query_data;
  1111. struct dp_swlm_tcl_data tcl_data;
  1112. QDF_STATUS status;
  1113. int ret;
  1114. if (qdf_unlikely(!swlm->is_enabled))
  1115. return 0;
  1116. tcl_data.nbuf = tx_desc->nbuf;
  1117. tcl_data.tid = tid;
  1118. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1119. swlm_query_data.tcl_data = &tcl_data;
  1120. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1121. if (QDF_IS_STATUS_ERROR(status)) {
  1122. dp_swlm_tcl_reset_session_data(soc);
  1123. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1124. return 0;
  1125. }
  1126. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1127. if (ret) {
  1128. DP_STATS_INC(swlm, tcl.coalesce_success, 1);
  1129. } else {
  1130. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1131. }
  1132. return ret;
  1133. }
  1134. /**
  1135. * dp_tx_ring_access_end() - HAL ring access end for data transmission
  1136. * @soc: Datapath soc handle
  1137. * @hal_ring_hdl: HAL ring handle
  1138. * @coalesce: Coalesce the current write or not
  1139. *
  1140. * Returns: none
  1141. */
  1142. static inline void
  1143. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1144. int coalesce)
  1145. {
  1146. if (coalesce)
  1147. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1148. else
  1149. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1150. }
  1151. #else
  1152. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1153. qdf_nbuf_t nbuf)
  1154. {
  1155. }
  1156. static inline int
  1157. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1158. struct dp_tx_desc_s *tx_desc,
  1159. uint8_t tid)
  1160. {
  1161. return 0;
  1162. }
  1163. static inline void
  1164. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1165. int coalesce)
  1166. {
  1167. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1168. }
  1169. #endif
  1170. #ifdef FEATURE_RUNTIME_PM
  1171. /**
  1172. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1173. * @soc: Datapath soc handle
  1174. * @hal_ring_hdl: HAL ring handle
  1175. * @coalesce: Coalesce the current write or not
  1176. *
  1177. * Wrapper for HAL ring access end for data transmission for
  1178. * FEATURE_RUNTIME_PM
  1179. *
  1180. * Returns: none
  1181. */
  1182. static inline void
  1183. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1184. hal_ring_handle_t hal_ring_hdl,
  1185. int coalesce)
  1186. {
  1187. int ret;
  1188. ret = hif_pm_runtime_get(soc->hif_handle,
  1189. RTPM_ID_DW_TX_HW_ENQUEUE, true);
  1190. switch (ret) {
  1191. case 0:
  1192. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1193. hif_pm_runtime_put(soc->hif_handle,
  1194. RTPM_ID_DW_TX_HW_ENQUEUE);
  1195. break;
  1196. /*
  1197. * If hif_pm_runtime_get returns -EBUSY or -EINPROGRESS,
  1198. * take the dp runtime refcount using dp_runtime_get,
  1199. * check link state,if up, write TX ring HP, else just set flush event.
  1200. * In dp_runtime_resume, wait until dp runtime refcount becomes
  1201. * zero or time out, then flush pending tx.
  1202. */
  1203. case -EBUSY:
  1204. case -EINPROGRESS:
  1205. dp_runtime_get(soc);
  1206. if (hif_pm_get_link_state(soc->hif_handle) ==
  1207. HIF_PM_LINK_STATE_UP) {
  1208. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1209. } else {
  1210. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1211. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1212. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1213. }
  1214. dp_runtime_put(soc);
  1215. break;
  1216. default:
  1217. dp_runtime_get(soc);
  1218. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1219. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1220. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1221. dp_runtime_put(soc);
  1222. }
  1223. }
  1224. #else
  1225. static inline void
  1226. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1227. hal_ring_handle_t hal_ring_hdl,
  1228. int coalesce)
  1229. {
  1230. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1231. }
  1232. #endif
  1233. /**
  1234. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  1235. * @soc: DP Soc Handle
  1236. * @vdev: DP vdev handle
  1237. * @tx_desc: Tx Descriptor Handle
  1238. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1239. * @fw_metadata: Metadata to send to Target Firmware along with frame
  1240. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  1241. * @tx_exc_metadata: Handle that holds exception path meta data
  1242. *
  1243. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  1244. * from software Tx descriptor
  1245. *
  1246. * Return: QDF_STATUS_SUCCESS: success
  1247. * QDF_STATUS_E_RESOURCES: Error return
  1248. */
  1249. static QDF_STATUS
  1250. dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  1251. struct dp_tx_desc_s *tx_desc, uint16_t fw_metadata,
  1252. struct cdp_tx_exception_metadata *tx_exc_metadata,
  1253. struct dp_tx_msdu_info_s *msdu_info)
  1254. {
  1255. void *hal_tx_desc;
  1256. uint32_t *hal_tx_desc_cached;
  1257. int coalesce = 0;
  1258. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1259. uint8_t ring_id = tx_q->ring_id & DP_TX_QUEUE_MASK;
  1260. uint8_t tid = msdu_info->tid;
  1261. /*
  1262. * Setting it initialization statically here to avoid
  1263. * a memset call jump with qdf_mem_set call
  1264. */
  1265. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1266. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  1267. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  1268. tx_exc_metadata->sec_type : vdev->sec_type);
  1269. /* Return Buffer Manager ID */
  1270. uint8_t bm_id = dp_tx_get_rbm_id(soc, ring_id);
  1271. hal_ring_handle_t hal_ring_hdl = NULL;
  1272. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1273. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  1274. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1275. return QDF_STATUS_E_RESOURCES;
  1276. }
  1277. hal_tx_desc_cached = (void *) cached_desc;
  1278. hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
  1279. tx_desc->dma_addr, bm_id, tx_desc->id,
  1280. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG));
  1281. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  1282. vdev->lmac_id);
  1283. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  1284. vdev->search_type);
  1285. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  1286. vdev->bss_ast_idx);
  1287. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  1288. vdev->dscp_tid_map_id);
  1289. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  1290. sec_type_map[sec_type]);
  1291. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1292. (vdev->bss_ast_hash & 0xF));
  1293. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1294. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  1295. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1296. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  1297. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  1298. vdev->hal_desc_addr_search_flags);
  1299. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1300. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1301. /* verify checksum offload configuration*/
  1302. if (vdev->csum_enabled &&
  1303. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  1304. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  1305. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1306. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1307. }
  1308. if (tid != HTT_TX_EXT_TID_INVALID)
  1309. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1310. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  1311. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  1312. if (qdf_unlikely(vdev->pdev->delay_stats_flag) ||
  1313. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  1314. soc->wlan_cfg_ctx)))
  1315. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  1316. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  1317. tx_desc->length,
  1318. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG),
  1319. (uint64_t)tx_desc->dma_addr, tx_desc->pkt_offset,
  1320. tx_desc->id);
  1321. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  1322. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1323. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1324. "%s %d : HAL RING Access Failed -- %pK",
  1325. __func__, __LINE__, hal_ring_hdl);
  1326. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1327. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1328. return status;
  1329. }
  1330. /* Sync cached descriptor with HW */
  1331. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1332. if (qdf_unlikely(!hal_tx_desc)) {
  1333. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1334. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1335. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1336. goto ring_access_fail;
  1337. }
  1338. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1339. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1340. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  1341. coalesce = dp_tx_attempt_coalescing(soc, vdev, tx_desc, tid);
  1342. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
  1343. dp_tx_update_stats(soc, tx_desc->nbuf);
  1344. status = QDF_STATUS_SUCCESS;
  1345. ring_access_fail:
  1346. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, coalesce);
  1347. return status;
  1348. }
  1349. /**
  1350. * dp_cce_classify() - Classify the frame based on CCE rules
  1351. * @vdev: DP vdev handle
  1352. * @nbuf: skb
  1353. *
  1354. * Classify frames based on CCE rules
  1355. * Return: bool( true if classified,
  1356. * else false)
  1357. */
  1358. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1359. {
  1360. qdf_ether_header_t *eh = NULL;
  1361. uint16_t ether_type;
  1362. qdf_llc_t *llcHdr;
  1363. qdf_nbuf_t nbuf_clone = NULL;
  1364. qdf_dot3_qosframe_t *qos_wh = NULL;
  1365. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1366. /*
  1367. * In case of mesh packets or hlos tid override enabled,
  1368. * don't do any classification
  1369. */
  1370. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1371. & DP_TX_SKIP_CCE_CLASSIFY))
  1372. return false;
  1373. }
  1374. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1375. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1376. ether_type = eh->ether_type;
  1377. llcHdr = (qdf_llc_t *)(nbuf->data +
  1378. sizeof(qdf_ether_header_t));
  1379. } else {
  1380. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1381. /* For encrypted packets don't do any classification */
  1382. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1383. return false;
  1384. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1385. if (qdf_unlikely(
  1386. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1387. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1388. ether_type = *(uint16_t *)(nbuf->data
  1389. + QDF_IEEE80211_4ADDR_HDR_LEN
  1390. + sizeof(qdf_llc_t)
  1391. - sizeof(ether_type));
  1392. llcHdr = (qdf_llc_t *)(nbuf->data +
  1393. QDF_IEEE80211_4ADDR_HDR_LEN);
  1394. } else {
  1395. ether_type = *(uint16_t *)(nbuf->data
  1396. + QDF_IEEE80211_3ADDR_HDR_LEN
  1397. + sizeof(qdf_llc_t)
  1398. - sizeof(ether_type));
  1399. llcHdr = (qdf_llc_t *)(nbuf->data +
  1400. QDF_IEEE80211_3ADDR_HDR_LEN);
  1401. }
  1402. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1403. && (ether_type ==
  1404. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1405. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1406. return true;
  1407. }
  1408. }
  1409. return false;
  1410. }
  1411. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1412. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1413. sizeof(*llcHdr));
  1414. nbuf_clone = qdf_nbuf_clone(nbuf);
  1415. if (qdf_unlikely(nbuf_clone)) {
  1416. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1417. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1418. qdf_nbuf_pull_head(nbuf_clone,
  1419. sizeof(qdf_net_vlanhdr_t));
  1420. }
  1421. }
  1422. } else {
  1423. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1424. nbuf_clone = qdf_nbuf_clone(nbuf);
  1425. if (qdf_unlikely(nbuf_clone)) {
  1426. qdf_nbuf_pull_head(nbuf_clone,
  1427. sizeof(qdf_net_vlanhdr_t));
  1428. }
  1429. }
  1430. }
  1431. if (qdf_unlikely(nbuf_clone))
  1432. nbuf = nbuf_clone;
  1433. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1434. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1435. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1436. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1437. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1438. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1439. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1440. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1441. if (qdf_unlikely(nbuf_clone))
  1442. qdf_nbuf_free(nbuf_clone);
  1443. return true;
  1444. }
  1445. if (qdf_unlikely(nbuf_clone))
  1446. qdf_nbuf_free(nbuf_clone);
  1447. return false;
  1448. }
  1449. /**
  1450. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1451. * @vdev: DP vdev handle
  1452. * @nbuf: skb
  1453. *
  1454. * Extract the DSCP or PCP information from frame and map into TID value.
  1455. *
  1456. * Return: void
  1457. */
  1458. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1459. struct dp_tx_msdu_info_s *msdu_info)
  1460. {
  1461. uint8_t tos = 0, dscp_tid_override = 0;
  1462. uint8_t *hdr_ptr, *L3datap;
  1463. uint8_t is_mcast = 0;
  1464. qdf_ether_header_t *eh = NULL;
  1465. qdf_ethervlan_header_t *evh = NULL;
  1466. uint16_t ether_type;
  1467. qdf_llc_t *llcHdr;
  1468. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1469. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1470. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1471. eh = (qdf_ether_header_t *)nbuf->data;
  1472. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1473. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1474. } else {
  1475. qdf_dot3_qosframe_t *qos_wh =
  1476. (qdf_dot3_qosframe_t *) nbuf->data;
  1477. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1478. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1479. return;
  1480. }
  1481. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1482. ether_type = eh->ether_type;
  1483. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1484. /*
  1485. * Check if packet is dot3 or eth2 type.
  1486. */
  1487. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1488. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1489. sizeof(*llcHdr));
  1490. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1491. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1492. sizeof(*llcHdr);
  1493. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1494. + sizeof(*llcHdr) +
  1495. sizeof(qdf_net_vlanhdr_t));
  1496. } else {
  1497. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1498. sizeof(*llcHdr);
  1499. }
  1500. } else {
  1501. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1502. evh = (qdf_ethervlan_header_t *) eh;
  1503. ether_type = evh->ether_type;
  1504. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1505. }
  1506. }
  1507. /*
  1508. * Find priority from IP TOS DSCP field
  1509. */
  1510. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1511. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1512. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1513. /* Only for unicast frames */
  1514. if (!is_mcast) {
  1515. /* send it on VO queue */
  1516. msdu_info->tid = DP_VO_TID;
  1517. }
  1518. } else {
  1519. /*
  1520. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1521. * from TOS byte.
  1522. */
  1523. tos = ip->ip_tos;
  1524. dscp_tid_override = 1;
  1525. }
  1526. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1527. /* TODO
  1528. * use flowlabel
  1529. *igmpmld cases to be handled in phase 2
  1530. */
  1531. unsigned long ver_pri_flowlabel;
  1532. unsigned long pri;
  1533. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1534. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1535. DP_IPV6_PRIORITY_SHIFT;
  1536. tos = pri;
  1537. dscp_tid_override = 1;
  1538. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1539. msdu_info->tid = DP_VO_TID;
  1540. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1541. /* Only for unicast frames */
  1542. if (!is_mcast) {
  1543. /* send ucast arp on VO queue */
  1544. msdu_info->tid = DP_VO_TID;
  1545. }
  1546. }
  1547. /*
  1548. * Assign all MCAST packets to BE
  1549. */
  1550. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1551. if (is_mcast) {
  1552. tos = 0;
  1553. dscp_tid_override = 1;
  1554. }
  1555. }
  1556. if (dscp_tid_override == 1) {
  1557. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1558. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1559. }
  1560. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1561. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1562. return;
  1563. }
  1564. /**
  1565. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1566. * @vdev: DP vdev handle
  1567. * @nbuf: skb
  1568. *
  1569. * Software based TID classification is required when more than 2 DSCP-TID
  1570. * mapping tables are needed.
  1571. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1572. *
  1573. * Return: void
  1574. */
  1575. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1576. struct dp_tx_msdu_info_s *msdu_info)
  1577. {
  1578. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1579. /*
  1580. * skip_sw_tid_classification flag will set in below cases-
  1581. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1582. * 2. hlos_tid_override enabled for vdev
  1583. * 3. mesh mode enabled for vdev
  1584. */
  1585. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1586. /* Update tid in msdu_info from skb priority */
  1587. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1588. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1589. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1590. return;
  1591. }
  1592. return;
  1593. }
  1594. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1595. }
  1596. #ifdef FEATURE_WLAN_TDLS
  1597. /**
  1598. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1599. * @soc: datapath SOC
  1600. * @vdev: datapath vdev
  1601. * @tx_desc: TX descriptor
  1602. *
  1603. * Return: None
  1604. */
  1605. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1606. struct dp_vdev *vdev,
  1607. struct dp_tx_desc_s *tx_desc)
  1608. {
  1609. if (vdev) {
  1610. if (vdev->is_tdls_frame) {
  1611. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1612. vdev->is_tdls_frame = false;
  1613. }
  1614. }
  1615. }
  1616. /**
  1617. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1618. * @soc: dp_soc handle
  1619. * @tx_desc: TX descriptor
  1620. * @vdev: datapath vdev handle
  1621. *
  1622. * Return: None
  1623. */
  1624. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1625. struct dp_tx_desc_s *tx_desc)
  1626. {
  1627. struct hal_tx_completion_status ts = {0};
  1628. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1629. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1630. DP_MOD_ID_TDLS);
  1631. if (qdf_unlikely(!vdev)) {
  1632. dp_err_rl("vdev is null!");
  1633. goto error;
  1634. }
  1635. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1636. if (vdev->tx_non_std_data_callback.func) {
  1637. qdf_nbuf_set_next(nbuf, NULL);
  1638. vdev->tx_non_std_data_callback.func(
  1639. vdev->tx_non_std_data_callback.ctxt,
  1640. nbuf, ts.status);
  1641. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1642. return;
  1643. } else {
  1644. dp_err_rl("callback func is null");
  1645. }
  1646. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1647. error:
  1648. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1649. qdf_nbuf_free(nbuf);
  1650. }
  1651. /**
  1652. * dp_tx_msdu_single_map() - do nbuf map
  1653. * @vdev: DP vdev handle
  1654. * @tx_desc: DP TX descriptor pointer
  1655. * @nbuf: skb pointer
  1656. *
  1657. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1658. * operation done in other component.
  1659. *
  1660. * Return: QDF_STATUS
  1661. */
  1662. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1663. struct dp_tx_desc_s *tx_desc,
  1664. qdf_nbuf_t nbuf)
  1665. {
  1666. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1667. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1668. nbuf,
  1669. QDF_DMA_TO_DEVICE,
  1670. nbuf->len);
  1671. else
  1672. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1673. QDF_DMA_TO_DEVICE);
  1674. }
  1675. #else
  1676. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1677. struct dp_vdev *vdev,
  1678. struct dp_tx_desc_s *tx_desc)
  1679. {
  1680. }
  1681. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1682. struct dp_tx_desc_s *tx_desc)
  1683. {
  1684. }
  1685. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1686. struct dp_tx_desc_s *tx_desc,
  1687. qdf_nbuf_t nbuf)
  1688. {
  1689. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1690. nbuf,
  1691. QDF_DMA_TO_DEVICE,
  1692. nbuf->len);
  1693. }
  1694. #endif
  1695. #ifdef MESH_MODE_SUPPORT
  1696. /**
  1697. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1698. * @soc: datapath SOC
  1699. * @vdev: datapath vdev
  1700. * @tx_desc: TX descriptor
  1701. *
  1702. * Return: None
  1703. */
  1704. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1705. struct dp_vdev *vdev,
  1706. struct dp_tx_desc_s *tx_desc)
  1707. {
  1708. if (qdf_unlikely(vdev->mesh_vdev))
  1709. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1710. }
  1711. /**
  1712. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1713. * @soc: dp_soc handle
  1714. * @tx_desc: TX descriptor
  1715. * @vdev: datapath vdev handle
  1716. *
  1717. * Return: None
  1718. */
  1719. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1720. struct dp_tx_desc_s *tx_desc)
  1721. {
  1722. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1723. struct dp_vdev *vdev = NULL;
  1724. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1725. qdf_nbuf_free(nbuf);
  1726. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1727. } else {
  1728. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1729. DP_MOD_ID_MESH);
  1730. if (vdev && vdev->osif_tx_free_ext)
  1731. vdev->osif_tx_free_ext((nbuf));
  1732. else
  1733. qdf_nbuf_free(nbuf);
  1734. if (vdev)
  1735. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1736. }
  1737. }
  1738. #else
  1739. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1740. struct dp_vdev *vdev,
  1741. struct dp_tx_desc_s *tx_desc)
  1742. {
  1743. }
  1744. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1745. struct dp_tx_desc_s *tx_desc)
  1746. {
  1747. }
  1748. #endif
  1749. /**
  1750. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1751. * @vdev: DP vdev handle
  1752. * @nbuf: skb
  1753. *
  1754. * Return: 1 if frame needs to be dropped else 0
  1755. */
  1756. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1757. {
  1758. struct dp_pdev *pdev = NULL;
  1759. struct dp_ast_entry *src_ast_entry = NULL;
  1760. struct dp_ast_entry *dst_ast_entry = NULL;
  1761. struct dp_soc *soc = NULL;
  1762. qdf_assert(vdev);
  1763. pdev = vdev->pdev;
  1764. qdf_assert(pdev);
  1765. soc = pdev->soc;
  1766. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1767. (soc, dstmac, vdev->pdev->pdev_id);
  1768. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1769. (soc, srcmac, vdev->pdev->pdev_id);
  1770. if (dst_ast_entry && src_ast_entry) {
  1771. if (dst_ast_entry->peer_id ==
  1772. src_ast_entry->peer_id)
  1773. return 1;
  1774. }
  1775. return 0;
  1776. }
  1777. /**
  1778. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1779. * @vdev: DP vdev handle
  1780. * @nbuf: skb
  1781. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1782. * @meta_data: Metadata to the fw
  1783. * @tx_q: Tx queue to be used for this Tx frame
  1784. * @peer_id: peer_id of the peer in case of NAWDS frames
  1785. * @tx_exc_metadata: Handle that holds exception path metadata
  1786. *
  1787. * Return: NULL on success,
  1788. * nbuf when it fails to send
  1789. */
  1790. qdf_nbuf_t
  1791. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1792. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1793. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1794. {
  1795. struct dp_pdev *pdev = vdev->pdev;
  1796. struct dp_soc *soc = pdev->soc;
  1797. struct dp_tx_desc_s *tx_desc;
  1798. QDF_STATUS status;
  1799. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1800. uint16_t htt_tcl_metadata = 0;
  1801. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1802. uint8_t tid = msdu_info->tid;
  1803. struct cdp_tid_tx_stats *tid_stats = NULL;
  1804. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1805. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1806. msdu_info, tx_exc_metadata);
  1807. if (!tx_desc) {
  1808. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1809. vdev, tx_q->desc_pool_id);
  1810. drop_code = TX_DESC_ERR;
  1811. goto fail_return;
  1812. }
  1813. if (qdf_unlikely(soc->cce_disable)) {
  1814. if (dp_cce_classify(vdev, nbuf) == true) {
  1815. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1816. tid = DP_VO_TID;
  1817. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1818. }
  1819. }
  1820. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1821. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1822. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1823. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1824. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1825. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1826. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1827. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1828. peer_id);
  1829. } else
  1830. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1831. if (msdu_info->exception_fw)
  1832. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1833. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1834. !pdev->enhanced_stats_en);
  1835. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1836. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1837. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1838. /* Handle failure */
  1839. dp_err("qdf_nbuf_map failed");
  1840. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1841. drop_code = TX_DMA_MAP_ERR;
  1842. goto release_desc;
  1843. }
  1844. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1845. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1846. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, htt_tcl_metadata,
  1847. tx_exc_metadata, msdu_info);
  1848. if (status != QDF_STATUS_SUCCESS) {
  1849. dp_tx_err("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1850. tx_desc, tx_q->ring_id);
  1851. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1852. QDF_DMA_TO_DEVICE,
  1853. nbuf->len);
  1854. drop_code = TX_HW_ENQUEUE;
  1855. goto release_desc;
  1856. }
  1857. return NULL;
  1858. release_desc:
  1859. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1860. fail_return:
  1861. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1862. tid_stats = &pdev->stats.tid_stats.
  1863. tid_tx_stats[tx_q->ring_id][tid];
  1864. tid_stats->swdrop_cnt[drop_code]++;
  1865. return nbuf;
  1866. }
  1867. /**
  1868. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1869. * @soc: Soc handle
  1870. * @desc: software Tx descriptor to be processed
  1871. *
  1872. * Return: none
  1873. */
  1874. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1875. struct dp_tx_desc_s *desc)
  1876. {
  1877. qdf_nbuf_t nbuf = desc->nbuf;
  1878. /* nbuf already freed in vdev detach path */
  1879. if (!nbuf)
  1880. return;
  1881. /* If it is TDLS mgmt, don't unmap or free the frame */
  1882. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1883. return dp_non_std_tx_comp_free_buff(soc, desc);
  1884. /* 0 : MSDU buffer, 1 : MLE */
  1885. if (desc->msdu_ext_desc) {
  1886. /* TSO free */
  1887. if (hal_tx_ext_desc_get_tso_enable(
  1888. desc->msdu_ext_desc->vaddr)) {
  1889. /* unmap eash TSO seg before free the nbuf */
  1890. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  1891. desc->tso_num_desc);
  1892. qdf_nbuf_free(nbuf);
  1893. return;
  1894. }
  1895. }
  1896. /* If it's ME frame, dont unmap the cloned nbuf's */
  1897. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  1898. goto nbuf_free;
  1899. dp_tx_unmap(soc, desc);
  1900. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  1901. return dp_mesh_tx_comp_free_buff(soc, desc);
  1902. nbuf_free:
  1903. qdf_nbuf_free(nbuf);
  1904. }
  1905. /**
  1906. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1907. * @vdev: DP vdev handle
  1908. * @nbuf: skb
  1909. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1910. *
  1911. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1912. *
  1913. * Return: NULL on success,
  1914. * nbuf when it fails to send
  1915. */
  1916. #if QDF_LOCK_STATS
  1917. noinline
  1918. #else
  1919. #endif
  1920. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1921. struct dp_tx_msdu_info_s *msdu_info)
  1922. {
  1923. uint32_t i;
  1924. struct dp_pdev *pdev = vdev->pdev;
  1925. struct dp_soc *soc = pdev->soc;
  1926. struct dp_tx_desc_s *tx_desc;
  1927. bool is_cce_classified = false;
  1928. QDF_STATUS status;
  1929. uint16_t htt_tcl_metadata = 0;
  1930. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1931. struct cdp_tid_tx_stats *tid_stats = NULL;
  1932. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  1933. if (qdf_unlikely(soc->cce_disable)) {
  1934. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1935. if (is_cce_classified) {
  1936. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1937. msdu_info->tid = DP_VO_TID;
  1938. }
  1939. }
  1940. if (msdu_info->frm_type == dp_tx_frm_me)
  1941. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1942. i = 0;
  1943. /* Print statement to track i and num_seg */
  1944. /*
  1945. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1946. * descriptors using information in msdu_info
  1947. */
  1948. while (i < msdu_info->num_seg) {
  1949. /*
  1950. * Setup Tx descriptor for an MSDU, and MSDU extension
  1951. * descriptor
  1952. */
  1953. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1954. tx_q->desc_pool_id);
  1955. if (!tx_desc) {
  1956. if (msdu_info->frm_type == dp_tx_frm_me) {
  1957. prep_desc_fail++;
  1958. dp_tx_me_free_buf(pdev,
  1959. (void *)(msdu_info->u.sg_info
  1960. .curr_seg->frags[0].vaddr));
  1961. if (prep_desc_fail == msdu_info->num_seg) {
  1962. /*
  1963. * Unmap is needed only if descriptor
  1964. * preparation failed for all segments.
  1965. */
  1966. qdf_nbuf_unmap(soc->osdev,
  1967. msdu_info->u.sg_info.
  1968. curr_seg->nbuf,
  1969. QDF_DMA_TO_DEVICE);
  1970. }
  1971. /*
  1972. * Free the nbuf for the current segment
  1973. * and make it point to the next in the list.
  1974. * For me, there are as many segments as there
  1975. * are no of clients.
  1976. */
  1977. qdf_nbuf_free(msdu_info->u.sg_info
  1978. .curr_seg->nbuf);
  1979. if (msdu_info->u.sg_info.curr_seg->next) {
  1980. msdu_info->u.sg_info.curr_seg =
  1981. msdu_info->u.sg_info
  1982. .curr_seg->next;
  1983. nbuf = msdu_info->u.sg_info
  1984. .curr_seg->nbuf;
  1985. }
  1986. i++;
  1987. continue;
  1988. }
  1989. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1990. dp_tx_tso_unmap_segment(soc,
  1991. msdu_info->u.tso_info.
  1992. curr_seg,
  1993. msdu_info->u.tso_info.
  1994. tso_num_seg_list);
  1995. if (msdu_info->u.tso_info.curr_seg->next) {
  1996. msdu_info->u.tso_info.curr_seg =
  1997. msdu_info->u.tso_info.curr_seg->next;
  1998. i++;
  1999. continue;
  2000. }
  2001. }
  2002. goto done;
  2003. }
  2004. if (msdu_info->frm_type == dp_tx_frm_me) {
  2005. tx_desc->me_buffer =
  2006. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  2007. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2008. }
  2009. if (is_cce_classified)
  2010. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2011. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2012. if (msdu_info->exception_fw) {
  2013. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2014. }
  2015. /*
  2016. * For frames with multiple segments (TSO, ME), jump to next
  2017. * segment.
  2018. */
  2019. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2020. if (msdu_info->u.tso_info.curr_seg->next) {
  2021. msdu_info->u.tso_info.curr_seg =
  2022. msdu_info->u.tso_info.curr_seg->next;
  2023. /*
  2024. * If this is a jumbo nbuf, then increment the
  2025. * number of nbuf users for each additional
  2026. * segment of the msdu. This will ensure that
  2027. * the skb is freed only after receiving tx
  2028. * completion for all segments of an nbuf
  2029. */
  2030. qdf_nbuf_inc_users(nbuf);
  2031. /* Check with MCL if this is needed */
  2032. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2033. */
  2034. }
  2035. }
  2036. /*
  2037. * Enqueue the Tx MSDU descriptor to HW for transmit
  2038. */
  2039. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, htt_tcl_metadata,
  2040. NULL, msdu_info);
  2041. if (status != QDF_STATUS_SUCCESS) {
  2042. dp_info("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2043. tx_desc, tx_q->ring_id);
  2044. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2045. tid_stats = &pdev->stats.tid_stats.
  2046. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2047. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2048. if (msdu_info->frm_type == dp_tx_frm_me) {
  2049. hw_enq_fail++;
  2050. if (hw_enq_fail == msdu_info->num_seg) {
  2051. /*
  2052. * Unmap is needed only if enqueue
  2053. * failed for all segments.
  2054. */
  2055. qdf_nbuf_unmap(soc->osdev,
  2056. msdu_info->u.sg_info.
  2057. curr_seg->nbuf,
  2058. QDF_DMA_TO_DEVICE);
  2059. }
  2060. /*
  2061. * Free the nbuf for the current segment
  2062. * and make it point to the next in the list.
  2063. * For me, there are as many segments as there
  2064. * are no of clients.
  2065. */
  2066. qdf_nbuf_free(msdu_info->u.sg_info
  2067. .curr_seg->nbuf);
  2068. if (msdu_info->u.sg_info.curr_seg->next) {
  2069. msdu_info->u.sg_info.curr_seg =
  2070. msdu_info->u.sg_info
  2071. .curr_seg->next;
  2072. nbuf = msdu_info->u.sg_info
  2073. .curr_seg->nbuf;
  2074. } else
  2075. break;
  2076. i++;
  2077. continue;
  2078. }
  2079. /*
  2080. * For TSO frames, the nbuf users increment done for
  2081. * the current segment has to be reverted, since the
  2082. * hw enqueue for this segment failed
  2083. */
  2084. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2085. msdu_info->u.tso_info.curr_seg) {
  2086. /*
  2087. * unmap and free current,
  2088. * retransmit remaining segments
  2089. */
  2090. dp_tx_comp_free_buf(soc, tx_desc);
  2091. i++;
  2092. continue;
  2093. }
  2094. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2095. goto done;
  2096. }
  2097. /*
  2098. * TODO
  2099. * if tso_info structure can be modified to have curr_seg
  2100. * as first element, following 2 blocks of code (for TSO and SG)
  2101. * can be combined into 1
  2102. */
  2103. /*
  2104. * For Multicast-Unicast converted packets,
  2105. * each converted frame (for a client) is represented as
  2106. * 1 segment
  2107. */
  2108. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2109. (msdu_info->frm_type == dp_tx_frm_me)) {
  2110. if (msdu_info->u.sg_info.curr_seg->next) {
  2111. msdu_info->u.sg_info.curr_seg =
  2112. msdu_info->u.sg_info.curr_seg->next;
  2113. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2114. } else
  2115. break;
  2116. }
  2117. i++;
  2118. }
  2119. nbuf = NULL;
  2120. done:
  2121. return nbuf;
  2122. }
  2123. /**
  2124. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2125. * for SG frames
  2126. * @vdev: DP vdev handle
  2127. * @nbuf: skb
  2128. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2129. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2130. *
  2131. * Return: NULL on success,
  2132. * nbuf when it fails to send
  2133. */
  2134. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2135. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2136. {
  2137. uint32_t cur_frag, nr_frags, i;
  2138. qdf_dma_addr_t paddr;
  2139. struct dp_tx_sg_info_s *sg_info;
  2140. sg_info = &msdu_info->u.sg_info;
  2141. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2142. if (QDF_STATUS_SUCCESS !=
  2143. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2144. QDF_DMA_TO_DEVICE,
  2145. qdf_nbuf_headlen(nbuf))) {
  2146. dp_tx_err("dma map error");
  2147. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2148. qdf_nbuf_free(nbuf);
  2149. return NULL;
  2150. }
  2151. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2152. seg_info->frags[0].paddr_lo = paddr;
  2153. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2154. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2155. seg_info->frags[0].vaddr = (void *) nbuf;
  2156. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2157. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  2158. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  2159. dp_tx_err("frag dma map error");
  2160. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2161. goto map_err;
  2162. }
  2163. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2164. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2165. seg_info->frags[cur_frag + 1].paddr_hi =
  2166. ((uint64_t) paddr) >> 32;
  2167. seg_info->frags[cur_frag + 1].len =
  2168. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2169. }
  2170. seg_info->frag_cnt = (cur_frag + 1);
  2171. seg_info->total_len = qdf_nbuf_len(nbuf);
  2172. seg_info->next = NULL;
  2173. sg_info->curr_seg = seg_info;
  2174. msdu_info->frm_type = dp_tx_frm_sg;
  2175. msdu_info->num_seg = 1;
  2176. return nbuf;
  2177. map_err:
  2178. /* restore paddr into nbuf before calling unmap */
  2179. qdf_nbuf_mapped_paddr_set(nbuf,
  2180. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2181. ((uint64_t)
  2182. seg_info->frags[0].paddr_hi) << 32));
  2183. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2184. QDF_DMA_TO_DEVICE,
  2185. seg_info->frags[0].len);
  2186. for (i = 1; i <= cur_frag; i++) {
  2187. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2188. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2189. seg_info->frags[i].paddr_hi) << 32),
  2190. seg_info->frags[i].len,
  2191. QDF_DMA_TO_DEVICE);
  2192. }
  2193. qdf_nbuf_free(nbuf);
  2194. return NULL;
  2195. }
  2196. /**
  2197. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2198. * @vdev: DP vdev handle
  2199. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2200. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2201. *
  2202. * Return: NULL on failure,
  2203. * nbuf when extracted successfully
  2204. */
  2205. static
  2206. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2207. struct dp_tx_msdu_info_s *msdu_info,
  2208. uint16_t ppdu_cookie)
  2209. {
  2210. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2211. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2212. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2213. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2214. (msdu_info->meta_data[5], 1);
  2215. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2216. (msdu_info->meta_data[5], 1);
  2217. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2218. (msdu_info->meta_data[6], ppdu_cookie);
  2219. msdu_info->exception_fw = 1;
  2220. msdu_info->is_tx_sniffer = 1;
  2221. }
  2222. #ifdef MESH_MODE_SUPPORT
  2223. /**
  2224. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2225. and prepare msdu_info for mesh frames.
  2226. * @vdev: DP vdev handle
  2227. * @nbuf: skb
  2228. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2229. *
  2230. * Return: NULL on failure,
  2231. * nbuf when extracted successfully
  2232. */
  2233. static
  2234. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2235. struct dp_tx_msdu_info_s *msdu_info)
  2236. {
  2237. struct meta_hdr_s *mhdr;
  2238. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2239. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2240. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2241. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2242. msdu_info->exception_fw = 0;
  2243. goto remove_meta_hdr;
  2244. }
  2245. msdu_info->exception_fw = 1;
  2246. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2247. meta_data->host_tx_desc_pool = 1;
  2248. meta_data->update_peer_cache = 1;
  2249. meta_data->learning_frame = 1;
  2250. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2251. meta_data->power = mhdr->power;
  2252. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2253. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2254. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2255. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2256. meta_data->dyn_bw = 1;
  2257. meta_data->valid_pwr = 1;
  2258. meta_data->valid_mcs_mask = 1;
  2259. meta_data->valid_nss_mask = 1;
  2260. meta_data->valid_preamble_type = 1;
  2261. meta_data->valid_retries = 1;
  2262. meta_data->valid_bw_info = 1;
  2263. }
  2264. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2265. meta_data->encrypt_type = 0;
  2266. meta_data->valid_encrypt_type = 1;
  2267. meta_data->learning_frame = 0;
  2268. }
  2269. meta_data->valid_key_flags = 1;
  2270. meta_data->key_flags = (mhdr->keyix & 0x3);
  2271. remove_meta_hdr:
  2272. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2273. dp_tx_err("qdf_nbuf_pull_head failed");
  2274. qdf_nbuf_free(nbuf);
  2275. return NULL;
  2276. }
  2277. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2278. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2279. " tid %d to_fw %d",
  2280. msdu_info->meta_data[0],
  2281. msdu_info->meta_data[1],
  2282. msdu_info->meta_data[2],
  2283. msdu_info->meta_data[3],
  2284. msdu_info->meta_data[4],
  2285. msdu_info->meta_data[5],
  2286. msdu_info->tid, msdu_info->exception_fw);
  2287. return nbuf;
  2288. }
  2289. #else
  2290. static
  2291. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2292. struct dp_tx_msdu_info_s *msdu_info)
  2293. {
  2294. return nbuf;
  2295. }
  2296. #endif
  2297. /**
  2298. * dp_check_exc_metadata() - Checks if parameters are valid
  2299. * @tx_exc - holds all exception path parameters
  2300. *
  2301. * Returns true when all the parameters are valid else false
  2302. *
  2303. */
  2304. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2305. {
  2306. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  2307. HTT_INVALID_TID);
  2308. bool invalid_encap_type =
  2309. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2310. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2311. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2312. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2313. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2314. tx_exc->ppdu_cookie == 0);
  2315. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2316. invalid_cookie) {
  2317. return false;
  2318. }
  2319. return true;
  2320. }
  2321. #ifdef ATH_SUPPORT_IQUE
  2322. /**
  2323. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2324. * @vdev: vdev handle
  2325. * @nbuf: skb
  2326. *
  2327. * Return: true on success,
  2328. * false on failure
  2329. */
  2330. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2331. {
  2332. qdf_ether_header_t *eh;
  2333. /* Mcast to Ucast Conversion*/
  2334. if (qdf_likely(!vdev->mcast_enhancement_en))
  2335. return true;
  2336. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2337. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2338. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2339. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2340. qdf_nbuf_set_next(nbuf, NULL);
  2341. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2342. qdf_nbuf_len(nbuf));
  2343. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2344. QDF_STATUS_SUCCESS) {
  2345. return false;
  2346. }
  2347. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2348. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2349. QDF_STATUS_SUCCESS) {
  2350. return false;
  2351. }
  2352. }
  2353. }
  2354. return true;
  2355. }
  2356. #else
  2357. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2358. {
  2359. return true;
  2360. }
  2361. #endif
  2362. /**
  2363. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2364. * @nbuf: qdf_nbuf_t
  2365. * @vdev: struct dp_vdev *
  2366. *
  2367. * Allow packet for processing only if it is for peer client which is
  2368. * connected with same vap. Drop packet if client is connected to
  2369. * different vap.
  2370. *
  2371. * Return: QDF_STATUS
  2372. */
  2373. static inline QDF_STATUS
  2374. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2375. {
  2376. struct dp_ast_entry *dst_ast_entry = NULL;
  2377. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2378. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2379. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2380. return QDF_STATUS_SUCCESS;
  2381. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2382. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2383. eh->ether_dhost,
  2384. vdev->vdev_id);
  2385. /* If there is no ast entry, return failure */
  2386. if (qdf_unlikely(!dst_ast_entry)) {
  2387. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2388. return QDF_STATUS_E_FAILURE;
  2389. }
  2390. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2391. return QDF_STATUS_SUCCESS;
  2392. }
  2393. /**
  2394. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2395. * @soc: DP soc handle
  2396. * @vdev_id: id of DP vdev handle
  2397. * @nbuf: skb
  2398. * @tx_exc_metadata: Handle that holds exception path meta data
  2399. *
  2400. * Entry point for Core Tx layer (DP_TX) invoked from
  2401. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2402. *
  2403. * Return: NULL on success,
  2404. * nbuf when it fails to send
  2405. */
  2406. qdf_nbuf_t
  2407. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2408. qdf_nbuf_t nbuf,
  2409. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2410. {
  2411. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2412. qdf_ether_header_t *eh = NULL;
  2413. struct dp_tx_msdu_info_s msdu_info;
  2414. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2415. DP_MOD_ID_TX_EXCEPTION);
  2416. if (qdf_unlikely(!vdev))
  2417. goto fail;
  2418. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2419. if (!tx_exc_metadata)
  2420. goto fail;
  2421. msdu_info.tid = tx_exc_metadata->tid;
  2422. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2423. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2424. QDF_MAC_ADDR_REF(nbuf->data));
  2425. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2426. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2427. dp_tx_err("Invalid parameters in exception path");
  2428. goto fail;
  2429. }
  2430. /* Basic sanity checks for unsupported packets */
  2431. /* MESH mode */
  2432. if (qdf_unlikely(vdev->mesh_vdev)) {
  2433. dp_tx_err("Mesh mode is not supported in exception path");
  2434. goto fail;
  2435. }
  2436. /*
  2437. * Classify the frame and call corresponding
  2438. * "prepare" function which extracts the segment (TSO)
  2439. * and fragmentation information (for TSO , SG, ME, or Raw)
  2440. * into MSDU_INFO structure which is later used to fill
  2441. * SW and HW descriptors.
  2442. */
  2443. if (qdf_nbuf_is_tso(nbuf)) {
  2444. dp_verbose_debug("TSO frame %pK", vdev);
  2445. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2446. qdf_nbuf_len(nbuf));
  2447. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2448. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2449. qdf_nbuf_len(nbuf));
  2450. goto fail;
  2451. }
  2452. goto send_multiple;
  2453. }
  2454. /* SG */
  2455. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2456. struct dp_tx_seg_info_s seg_info = {0};
  2457. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2458. if (!nbuf)
  2459. goto fail;
  2460. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2461. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2462. qdf_nbuf_len(nbuf));
  2463. goto send_multiple;
  2464. }
  2465. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2466. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2467. qdf_nbuf_len(nbuf));
  2468. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2469. tx_exc_metadata->ppdu_cookie);
  2470. }
  2471. /*
  2472. * Get HW Queue to use for this frame.
  2473. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2474. * dedicated for data and 1 for command.
  2475. * "queue_id" maps to one hardware ring.
  2476. * With each ring, we also associate a unique Tx descriptor pool
  2477. * to minimize lock contention for these resources.
  2478. */
  2479. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2480. /*
  2481. * Check exception descriptors
  2482. */
  2483. if (dp_tx_exception_limit_check(vdev))
  2484. goto fail;
  2485. /* Single linear frame */
  2486. /*
  2487. * If nbuf is a simple linear frame, use send_single function to
  2488. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2489. * SRNG. There is no need to setup a MSDU extension descriptor.
  2490. */
  2491. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2492. tx_exc_metadata->peer_id, tx_exc_metadata);
  2493. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2494. return nbuf;
  2495. send_multiple:
  2496. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2497. fail:
  2498. if (vdev)
  2499. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2500. dp_verbose_debug("pkt send failed");
  2501. return nbuf;
  2502. }
  2503. /**
  2504. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2505. * in exception path in special case to avoid regular exception path chk.
  2506. * @soc: DP soc handle
  2507. * @vdev_id: id of DP vdev handle
  2508. * @nbuf: skb
  2509. * @tx_exc_metadata: Handle that holds exception path meta data
  2510. *
  2511. * Entry point for Core Tx layer (DP_TX) invoked from
  2512. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2513. *
  2514. * Return: NULL on success,
  2515. * nbuf when it fails to send
  2516. */
  2517. qdf_nbuf_t
  2518. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2519. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2520. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2521. {
  2522. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2523. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2524. DP_MOD_ID_TX_EXCEPTION);
  2525. if (qdf_unlikely(!vdev))
  2526. goto fail;
  2527. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2528. == QDF_STATUS_E_FAILURE)) {
  2529. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2530. goto fail;
  2531. }
  2532. /* Unref count as it will agin be taken inside dp_tx_exception */
  2533. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2534. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2535. fail:
  2536. if (vdev)
  2537. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2538. dp_verbose_debug("pkt send failed");
  2539. return nbuf;
  2540. }
  2541. /**
  2542. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2543. * @soc: DP soc handle
  2544. * @vdev_id: DP vdev handle
  2545. * @nbuf: skb
  2546. *
  2547. * Entry point for Core Tx layer (DP_TX) invoked from
  2548. * hard_start_xmit in OSIF/HDD
  2549. *
  2550. * Return: NULL on success,
  2551. * nbuf when it fails to send
  2552. */
  2553. #ifdef MESH_MODE_SUPPORT
  2554. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2555. qdf_nbuf_t nbuf)
  2556. {
  2557. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2558. struct meta_hdr_s *mhdr;
  2559. qdf_nbuf_t nbuf_mesh = NULL;
  2560. qdf_nbuf_t nbuf_clone = NULL;
  2561. struct dp_vdev *vdev;
  2562. uint8_t no_enc_frame = 0;
  2563. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2564. if (!nbuf_mesh) {
  2565. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2566. "qdf_nbuf_unshare failed");
  2567. return nbuf;
  2568. }
  2569. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2570. if (!vdev) {
  2571. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2572. "vdev is NULL for vdev_id %d", vdev_id);
  2573. return nbuf;
  2574. }
  2575. nbuf = nbuf_mesh;
  2576. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2577. if ((vdev->sec_type != cdp_sec_type_none) &&
  2578. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2579. no_enc_frame = 1;
  2580. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2581. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2582. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2583. !no_enc_frame) {
  2584. nbuf_clone = qdf_nbuf_clone(nbuf);
  2585. if (!nbuf_clone) {
  2586. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2587. "qdf_nbuf_clone failed");
  2588. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2589. return nbuf;
  2590. }
  2591. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2592. }
  2593. if (nbuf_clone) {
  2594. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2595. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2596. } else {
  2597. qdf_nbuf_free(nbuf_clone);
  2598. }
  2599. }
  2600. if (no_enc_frame)
  2601. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2602. else
  2603. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2604. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2605. if ((!nbuf) && no_enc_frame) {
  2606. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2607. }
  2608. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2609. return nbuf;
  2610. }
  2611. #else
  2612. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2613. qdf_nbuf_t nbuf)
  2614. {
  2615. return dp_tx_send(soc, vdev_id, nbuf);
  2616. }
  2617. #endif
  2618. /**
  2619. * dp_tx_nawds_handler() - NAWDS handler
  2620. *
  2621. * @soc: DP soc handle
  2622. * @vdev_id: id of DP vdev handle
  2623. * @msdu_info: msdu_info required to create HTT metadata
  2624. * @nbuf: skb
  2625. *
  2626. * This API transfers the multicast frames with the peer id
  2627. * on NAWDS enabled peer.
  2628. * Return: none
  2629. */
  2630. static inline
  2631. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2632. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2633. {
  2634. struct dp_peer *peer = NULL;
  2635. qdf_nbuf_t nbuf_clone = NULL;
  2636. uint16_t peer_id = DP_INVALID_PEER;
  2637. uint16_t sa_peer_id = DP_INVALID_PEER;
  2638. struct dp_ast_entry *ast_entry = NULL;
  2639. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2640. qdf_spin_lock_bh(&soc->ast_lock);
  2641. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2642. (soc,
  2643. (uint8_t *)(eh->ether_shost),
  2644. vdev->pdev->pdev_id);
  2645. if (ast_entry)
  2646. sa_peer_id = ast_entry->peer_id;
  2647. qdf_spin_unlock_bh(&soc->ast_lock);
  2648. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2649. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2650. if (!peer->bss_peer && peer->nawds_enabled) {
  2651. peer_id = peer->peer_id;
  2652. /* Multicast packets needs to be
  2653. * dropped in case of intra bss forwarding
  2654. */
  2655. if (sa_peer_id == peer->peer_id) {
  2656. dp_tx_debug("multicast packet");
  2657. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  2658. continue;
  2659. }
  2660. nbuf_clone = qdf_nbuf_clone(nbuf);
  2661. if (!nbuf_clone) {
  2662. QDF_TRACE(QDF_MODULE_ID_DP,
  2663. QDF_TRACE_LEVEL_ERROR,
  2664. FL("nbuf clone failed"));
  2665. break;
  2666. }
  2667. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2668. msdu_info, peer_id,
  2669. NULL);
  2670. if (nbuf_clone) {
  2671. dp_tx_debug("pkt send failed");
  2672. qdf_nbuf_free(nbuf_clone);
  2673. } else {
  2674. if (peer_id != DP_INVALID_PEER)
  2675. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2676. 1, qdf_nbuf_len(nbuf));
  2677. }
  2678. }
  2679. }
  2680. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2681. }
  2682. /**
  2683. * dp_tx_send() - Transmit a frame on a given VAP
  2684. * @soc: DP soc handle
  2685. * @vdev_id: id of DP vdev handle
  2686. * @nbuf: skb
  2687. *
  2688. * Entry point for Core Tx layer (DP_TX) invoked from
  2689. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2690. * cases
  2691. *
  2692. * Return: NULL on success,
  2693. * nbuf when it fails to send
  2694. */
  2695. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2696. qdf_nbuf_t nbuf)
  2697. {
  2698. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2699. uint16_t peer_id = HTT_INVALID_PEER;
  2700. /*
  2701. * doing a memzero is causing additional function call overhead
  2702. * so doing static stack clearing
  2703. */
  2704. struct dp_tx_msdu_info_s msdu_info = {0};
  2705. struct dp_vdev *vdev = NULL;
  2706. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2707. return nbuf;
  2708. /*
  2709. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2710. * this in per packet path.
  2711. *
  2712. * As in this path vdev memory is already protected with netdev
  2713. * tx lock
  2714. */
  2715. vdev = soc->vdev_id_map[vdev_id];
  2716. if (qdf_unlikely(!vdev))
  2717. return nbuf;
  2718. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2719. QDF_MAC_ADDR_REF(nbuf->data));
  2720. /*
  2721. * Set Default Host TID value to invalid TID
  2722. * (TID override disabled)
  2723. */
  2724. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2725. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2726. if (qdf_unlikely(vdev->mesh_vdev)) {
  2727. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2728. &msdu_info);
  2729. if (!nbuf_mesh) {
  2730. dp_verbose_debug("Extracting mesh metadata failed");
  2731. return nbuf;
  2732. }
  2733. nbuf = nbuf_mesh;
  2734. }
  2735. /*
  2736. * Get HW Queue to use for this frame.
  2737. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2738. * dedicated for data and 1 for command.
  2739. * "queue_id" maps to one hardware ring.
  2740. * With each ring, we also associate a unique Tx descriptor pool
  2741. * to minimize lock contention for these resources.
  2742. */
  2743. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2744. /*
  2745. * TCL H/W supports 2 DSCP-TID mapping tables.
  2746. * Table 1 - Default DSCP-TID mapping table
  2747. * Table 2 - 1 DSCP-TID override table
  2748. *
  2749. * If we need a different DSCP-TID mapping for this vap,
  2750. * call tid_classify to extract DSCP/ToS from frame and
  2751. * map to a TID and store in msdu_info. This is later used
  2752. * to fill in TCL Input descriptor (per-packet TID override).
  2753. */
  2754. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2755. /*
  2756. * Classify the frame and call corresponding
  2757. * "prepare" function which extracts the segment (TSO)
  2758. * and fragmentation information (for TSO , SG, ME, or Raw)
  2759. * into MSDU_INFO structure which is later used to fill
  2760. * SW and HW descriptors.
  2761. */
  2762. if (qdf_nbuf_is_tso(nbuf)) {
  2763. dp_verbose_debug("TSO frame %pK", vdev);
  2764. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2765. qdf_nbuf_len(nbuf));
  2766. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2767. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2768. qdf_nbuf_len(nbuf));
  2769. return nbuf;
  2770. }
  2771. goto send_multiple;
  2772. }
  2773. /* SG */
  2774. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2775. struct dp_tx_seg_info_s seg_info = {0};
  2776. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2777. if (!nbuf)
  2778. return NULL;
  2779. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2780. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2781. qdf_nbuf_len(nbuf));
  2782. goto send_multiple;
  2783. }
  2784. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  2785. return NULL;
  2786. /* RAW */
  2787. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2788. struct dp_tx_seg_info_s seg_info = {0};
  2789. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2790. if (!nbuf)
  2791. return NULL;
  2792. dp_verbose_debug("Raw frame %pK", vdev);
  2793. goto send_multiple;
  2794. }
  2795. if (qdf_unlikely(vdev->nawds_enabled)) {
  2796. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2797. qdf_nbuf_data(nbuf);
  2798. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2799. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2800. peer_id = DP_INVALID_PEER;
  2801. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2802. 1, qdf_nbuf_len(nbuf));
  2803. }
  2804. /* Single linear frame */
  2805. /*
  2806. * If nbuf is a simple linear frame, use send_single function to
  2807. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2808. * SRNG. There is no need to setup a MSDU extension descriptor.
  2809. */
  2810. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2811. return nbuf;
  2812. send_multiple:
  2813. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2814. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2815. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2816. return nbuf;
  2817. }
  2818. /**
  2819. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  2820. * case to vaoid check in perpkt path.
  2821. * @soc: DP soc handle
  2822. * @vdev_id: id of DP vdev handle
  2823. * @nbuf: skb
  2824. *
  2825. * Entry point for Core Tx layer (DP_TX) invoked from
  2826. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  2827. * with special condition to avoid per pkt check in dp_tx_send
  2828. *
  2829. * Return: NULL on success,
  2830. * nbuf when it fails to send
  2831. */
  2832. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2833. uint8_t vdev_id, qdf_nbuf_t nbuf)
  2834. {
  2835. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2836. struct dp_vdev *vdev = NULL;
  2837. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2838. return nbuf;
  2839. /*
  2840. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2841. * this in per packet path.
  2842. *
  2843. * As in this path vdev memory is already protected with netdev
  2844. * tx lock
  2845. */
  2846. vdev = soc->vdev_id_map[vdev_id];
  2847. if (qdf_unlikely(!vdev))
  2848. return nbuf;
  2849. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2850. == QDF_STATUS_E_FAILURE)) {
  2851. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2852. return nbuf;
  2853. }
  2854. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  2855. }
  2856. /**
  2857. * dp_tx_reinject_handler() - Tx Reinject Handler
  2858. * @soc: datapath soc handle
  2859. * @vdev: datapath vdev handle
  2860. * @tx_desc: software descriptor head pointer
  2861. * @status : Tx completion status from HTT descriptor
  2862. *
  2863. * This function reinjects frames back to Target.
  2864. * Todo - Host queue needs to be added
  2865. *
  2866. * Return: none
  2867. */
  2868. static
  2869. void dp_tx_reinject_handler(struct dp_soc *soc,
  2870. struct dp_vdev *vdev,
  2871. struct dp_tx_desc_s *tx_desc,
  2872. uint8_t *status)
  2873. {
  2874. struct dp_peer *peer = NULL;
  2875. uint32_t peer_id = HTT_INVALID_PEER;
  2876. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2877. qdf_nbuf_t nbuf_copy = NULL;
  2878. struct dp_tx_msdu_info_s msdu_info;
  2879. #ifdef WDS_VENDOR_EXTENSION
  2880. int is_mcast = 0, is_ucast = 0;
  2881. int num_peers_3addr = 0;
  2882. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2883. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2884. #endif
  2885. qdf_assert(vdev);
  2886. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2887. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2888. dp_tx_debug("Tx reinject path");
  2889. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2890. qdf_nbuf_len(tx_desc->nbuf));
  2891. #ifdef WDS_VENDOR_EXTENSION
  2892. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2893. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2894. } else {
  2895. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2896. }
  2897. is_ucast = !is_mcast;
  2898. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2899. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2900. if (peer->bss_peer)
  2901. continue;
  2902. /* Detect wds peers that use 3-addr framing for mcast.
  2903. * if there are any, the bss_peer is used to send the
  2904. * the mcast frame using 3-addr format. all wds enabled
  2905. * peers that use 4-addr framing for mcast frames will
  2906. * be duplicated and sent as 4-addr frames below.
  2907. */
  2908. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2909. num_peers_3addr = 1;
  2910. break;
  2911. }
  2912. }
  2913. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2914. #endif
  2915. if (qdf_unlikely(vdev->mesh_vdev)) {
  2916. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2917. } else {
  2918. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2919. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2920. if ((peer->peer_id != HTT_INVALID_PEER) &&
  2921. #ifdef WDS_VENDOR_EXTENSION
  2922. /*
  2923. * . if 3-addr STA, then send on BSS Peer
  2924. * . if Peer WDS enabled and accept 4-addr mcast,
  2925. * send mcast on that peer only
  2926. * . if Peer WDS enabled and accept 4-addr ucast,
  2927. * send ucast on that peer only
  2928. */
  2929. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2930. (peer->wds_enabled &&
  2931. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2932. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2933. #else
  2934. ((peer->bss_peer &&
  2935. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))))) {
  2936. #endif
  2937. peer_id = DP_INVALID_PEER;
  2938. nbuf_copy = qdf_nbuf_copy(nbuf);
  2939. if (!nbuf_copy) {
  2940. dp_tx_debug("nbuf copy failed");
  2941. break;
  2942. }
  2943. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2944. nbuf_copy,
  2945. &msdu_info,
  2946. peer_id,
  2947. NULL);
  2948. if (nbuf_copy) {
  2949. dp_tx_debug("pkt send failed");
  2950. qdf_nbuf_free(nbuf_copy);
  2951. }
  2952. }
  2953. }
  2954. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2955. }
  2956. qdf_nbuf_free(nbuf);
  2957. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2958. }
  2959. /**
  2960. * dp_tx_inspect_handler() - Tx Inspect Handler
  2961. * @soc: datapath soc handle
  2962. * @vdev: datapath vdev handle
  2963. * @tx_desc: software descriptor head pointer
  2964. * @status : Tx completion status from HTT descriptor
  2965. *
  2966. * Handles Tx frames sent back to Host for inspection
  2967. * (ProxyARP)
  2968. *
  2969. * Return: none
  2970. */
  2971. static void dp_tx_inspect_handler(struct dp_soc *soc,
  2972. struct dp_vdev *vdev,
  2973. struct dp_tx_desc_s *tx_desc,
  2974. uint8_t *status)
  2975. {
  2976. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2977. "%s Tx inspect path",
  2978. __func__);
  2979. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  2980. qdf_nbuf_len(tx_desc->nbuf));
  2981. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2982. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2983. }
  2984. #ifdef MESH_MODE_SUPPORT
  2985. /**
  2986. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2987. * in mesh meta header
  2988. * @tx_desc: software descriptor head pointer
  2989. * @ts: pointer to tx completion stats
  2990. * Return: none
  2991. */
  2992. static
  2993. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2994. struct hal_tx_completion_status *ts)
  2995. {
  2996. struct meta_hdr_s *mhdr;
  2997. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2998. if (!tx_desc->msdu_ext_desc) {
  2999. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3000. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3001. "netbuf %pK offset %d",
  3002. netbuf, tx_desc->pkt_offset);
  3003. return;
  3004. }
  3005. }
  3006. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  3007. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3008. "netbuf %pK offset %zu", netbuf,
  3009. sizeof(struct meta_hdr_s));
  3010. return;
  3011. }
  3012. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  3013. mhdr->rssi = ts->ack_frame_rssi;
  3014. mhdr->band = tx_desc->pdev->operating_channel.band;
  3015. mhdr->channel = tx_desc->pdev->operating_channel.num;
  3016. }
  3017. #else
  3018. static
  3019. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3020. struct hal_tx_completion_status *ts)
  3021. {
  3022. }
  3023. #endif
  3024. #ifdef QCA_PEER_EXT_STATS
  3025. /*
  3026. * dp_tx_compute_tid_delay() - Compute per TID delay
  3027. * @stats: Per TID delay stats
  3028. * @tx_desc: Software Tx descriptor
  3029. *
  3030. * Compute the software enqueue and hw enqueue delays and
  3031. * update the respective histograms
  3032. *
  3033. * Return: void
  3034. */
  3035. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3036. struct dp_tx_desc_s *tx_desc)
  3037. {
  3038. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3039. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3040. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3041. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3042. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3043. timestamp_hw_enqueue = tx_desc->timestamp;
  3044. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3045. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3046. timestamp_hw_enqueue);
  3047. /*
  3048. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3049. */
  3050. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3051. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3052. }
  3053. /*
  3054. * dp_tx_update_peer_ext_stats() - Update the peer extended stats
  3055. * @peer: DP peer context
  3056. * @tx_desc: Tx software descriptor
  3057. * @tid: Transmission ID
  3058. * @ring_id: Rx CPU context ID/CPU_ID
  3059. *
  3060. * Update the peer extended stats. These are enhanced other
  3061. * delay stats per msdu level.
  3062. *
  3063. * Return: void
  3064. */
  3065. static void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3066. struct dp_tx_desc_s *tx_desc,
  3067. uint8_t tid, uint8_t ring_id)
  3068. {
  3069. struct dp_pdev *pdev = peer->vdev->pdev;
  3070. struct dp_soc *soc = NULL;
  3071. struct cdp_peer_ext_stats *pext_stats = NULL;
  3072. soc = pdev->soc;
  3073. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3074. return;
  3075. pext_stats = peer->pext_stats;
  3076. qdf_assert(pext_stats);
  3077. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3078. /*
  3079. * For non-TID packets use the TID 9
  3080. */
  3081. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3082. tid = CDP_MAX_DATA_TIDS - 1;
  3083. dp_tx_compute_tid_delay(&pext_stats->delay_stats[tid][ring_id],
  3084. tx_desc);
  3085. }
  3086. #else
  3087. static inline void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3088. struct dp_tx_desc_s *tx_desc,
  3089. uint8_t tid, uint8_t ring_id)
  3090. {
  3091. }
  3092. #endif
  3093. /**
  3094. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3095. * to pass in correct fields
  3096. *
  3097. * @vdev: pdev handle
  3098. * @tx_desc: tx descriptor
  3099. * @tid: tid value
  3100. * @ring_id: TCL or WBM ring number for transmit path
  3101. * Return: none
  3102. */
  3103. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  3104. struct dp_tx_desc_s *tx_desc,
  3105. uint8_t tid, uint8_t ring_id)
  3106. {
  3107. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3108. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3109. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  3110. return;
  3111. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3112. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3113. timestamp_hw_enqueue = tx_desc->timestamp;
  3114. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3115. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3116. timestamp_hw_enqueue);
  3117. interframe_delay = (uint32_t)(timestamp_ingress -
  3118. vdev->prev_tx_enq_tstamp);
  3119. /*
  3120. * Delay in software enqueue
  3121. */
  3122. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  3123. CDP_DELAY_STATS_SW_ENQ, ring_id);
  3124. /*
  3125. * Delay between packet enqueued to HW and Tx completion
  3126. */
  3127. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  3128. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  3129. /*
  3130. * Update interframe delay stats calculated at hardstart receive point.
  3131. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3132. * interframe delay will not be calculate correctly for 1st frame.
  3133. * On the other side, this will help in avoiding extra per packet check
  3134. * of !vdev->prev_tx_enq_tstamp.
  3135. */
  3136. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  3137. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  3138. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3139. }
  3140. #ifdef DISABLE_DP_STATS
  3141. static
  3142. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3143. {
  3144. }
  3145. #else
  3146. static
  3147. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3148. {
  3149. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3150. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3151. if (subtype != QDF_PROTO_INVALID)
  3152. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  3153. }
  3154. #endif
  3155. /**
  3156. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3157. * per wbm ring
  3158. *
  3159. * @tx_desc: software descriptor head pointer
  3160. * @ts: Tx completion status
  3161. * @peer: peer handle
  3162. * @ring_id: ring number
  3163. *
  3164. * Return: None
  3165. */
  3166. static inline void
  3167. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3168. struct hal_tx_completion_status *ts,
  3169. struct dp_peer *peer, uint8_t ring_id)
  3170. {
  3171. struct dp_pdev *pdev = peer->vdev->pdev;
  3172. struct dp_soc *soc = NULL;
  3173. uint8_t mcs, pkt_type;
  3174. uint8_t tid = ts->tid;
  3175. uint32_t length;
  3176. struct cdp_tid_tx_stats *tid_stats;
  3177. if (!pdev)
  3178. return;
  3179. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3180. tid = CDP_MAX_DATA_TIDS - 1;
  3181. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3182. soc = pdev->soc;
  3183. mcs = ts->mcs;
  3184. pkt_type = ts->pkt_type;
  3185. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3186. dp_err("Release source is not from TQM");
  3187. return;
  3188. }
  3189. length = qdf_nbuf_len(tx_desc->nbuf);
  3190. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  3191. if (qdf_unlikely(pdev->delay_stats_flag))
  3192. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  3193. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  3194. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  3195. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  3196. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3197. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  3198. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  3199. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  3200. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  3201. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  3202. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  3203. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  3204. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  3205. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  3206. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  3207. /*
  3208. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  3209. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  3210. * are no completions for failed cases. Hence updating tx_failed from
  3211. * data path. Please note that if tx_failed is fixed to be from ppdu,
  3212. * then this has to be removed
  3213. */
  3214. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  3215. peer->stats.tx.dropped.fw_rem_notx +
  3216. peer->stats.tx.dropped.fw_rem_tx +
  3217. peer->stats.tx.dropped.age_out +
  3218. peer->stats.tx.dropped.fw_reason1 +
  3219. peer->stats.tx.dropped.fw_reason2 +
  3220. peer->stats.tx.dropped.fw_reason3;
  3221. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3222. tid_stats->tqm_status_cnt[ts->status]++;
  3223. }
  3224. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3225. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  3226. return;
  3227. }
  3228. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  3229. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  3230. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  3231. /*
  3232. * Following Rate Statistics are updated from HTT PPDU events from FW.
  3233. * Return from here if HTT PPDU events are enabled.
  3234. */
  3235. if (!(soc->process_tx_status))
  3236. return;
  3237. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3238. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  3239. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3240. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  3241. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3242. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3243. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3244. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3245. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3246. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3247. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3248. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3249. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3250. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3251. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3252. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3253. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3254. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3255. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3256. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3257. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  3258. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  3259. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3260. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3261. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  3262. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  3263. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  3264. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  3265. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  3266. &peer->stats, ts->peer_id,
  3267. UPDATE_PEER_STATS, pdev->pdev_id);
  3268. #endif
  3269. }
  3270. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3271. /**
  3272. * dp_tx_flow_pool_lock() - take flow pool lock
  3273. * @soc: core txrx main context
  3274. * @tx_desc: tx desc
  3275. *
  3276. * Return: None
  3277. */
  3278. static inline
  3279. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3280. struct dp_tx_desc_s *tx_desc)
  3281. {
  3282. struct dp_tx_desc_pool_s *pool;
  3283. uint8_t desc_pool_id;
  3284. desc_pool_id = tx_desc->pool_id;
  3285. pool = &soc->tx_desc[desc_pool_id];
  3286. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3287. }
  3288. /**
  3289. * dp_tx_flow_pool_unlock() - release flow pool lock
  3290. * @soc: core txrx main context
  3291. * @tx_desc: tx desc
  3292. *
  3293. * Return: None
  3294. */
  3295. static inline
  3296. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3297. struct dp_tx_desc_s *tx_desc)
  3298. {
  3299. struct dp_tx_desc_pool_s *pool;
  3300. uint8_t desc_pool_id;
  3301. desc_pool_id = tx_desc->pool_id;
  3302. pool = &soc->tx_desc[desc_pool_id];
  3303. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3304. }
  3305. #else
  3306. static inline
  3307. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3308. {
  3309. }
  3310. static inline
  3311. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3312. {
  3313. }
  3314. #endif
  3315. /**
  3316. * dp_tx_notify_completion() - Notify tx completion for this desc
  3317. * @soc: core txrx main context
  3318. * @vdev: datapath vdev handle
  3319. * @tx_desc: tx desc
  3320. * @netbuf: buffer
  3321. * @status: tx status
  3322. *
  3323. * Return: none
  3324. */
  3325. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3326. struct dp_vdev *vdev,
  3327. struct dp_tx_desc_s *tx_desc,
  3328. qdf_nbuf_t netbuf,
  3329. uint8_t status)
  3330. {
  3331. void *osif_dev;
  3332. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3333. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3334. qdf_assert(tx_desc);
  3335. dp_tx_flow_pool_lock(soc, tx_desc);
  3336. if (!vdev ||
  3337. !vdev->osif_vdev) {
  3338. dp_tx_flow_pool_unlock(soc, tx_desc);
  3339. return;
  3340. }
  3341. osif_dev = vdev->osif_vdev;
  3342. tx_compl_cbk = vdev->tx_comp;
  3343. dp_tx_flow_pool_unlock(soc, tx_desc);
  3344. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3345. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3346. if (tx_compl_cbk)
  3347. tx_compl_cbk(netbuf, osif_dev, flag);
  3348. }
  3349. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3350. * @pdev: pdev handle
  3351. * @tid: tid value
  3352. * @txdesc_ts: timestamp from txdesc
  3353. * @ppdu_id: ppdu id
  3354. *
  3355. * Return: none
  3356. */
  3357. #ifdef FEATURE_PERPKT_INFO
  3358. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3359. struct dp_peer *peer,
  3360. uint8_t tid,
  3361. uint64_t txdesc_ts,
  3362. uint32_t ppdu_id)
  3363. {
  3364. uint64_t delta_ms;
  3365. struct cdp_tx_sojourn_stats *sojourn_stats;
  3366. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  3367. return;
  3368. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3369. tid >= CDP_DATA_TID_MAX))
  3370. return;
  3371. if (qdf_unlikely(!pdev->sojourn_buf))
  3372. return;
  3373. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3374. qdf_nbuf_data(pdev->sojourn_buf);
  3375. sojourn_stats->cookie = (void *)peer->rdkstats_ctx;
  3376. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  3377. txdesc_ts;
  3378. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  3379. delta_ms);
  3380. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3381. sojourn_stats->num_msdus[tid] = 1;
  3382. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3383. peer->avg_sojourn_msdu[tid].internal;
  3384. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3385. pdev->sojourn_buf, HTT_INVALID_PEER,
  3386. WDI_NO_VAL, pdev->pdev_id);
  3387. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3388. sojourn_stats->num_msdus[tid] = 0;
  3389. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3390. }
  3391. #else
  3392. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3393. struct dp_peer *peer,
  3394. uint8_t tid,
  3395. uint64_t txdesc_ts,
  3396. uint32_t ppdu_id)
  3397. {
  3398. }
  3399. #endif
  3400. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  3401. /**
  3402. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  3403. * @soc: dp_soc handle
  3404. * @desc: Tx Descriptor
  3405. * @ts: HAL Tx completion descriptor contents
  3406. *
  3407. * This function is used to send tx completion to packet capture
  3408. */
  3409. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  3410. struct dp_tx_desc_s *desc,
  3411. struct hal_tx_completion_status *ts)
  3412. {
  3413. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  3414. desc, ts->peer_id,
  3415. WDI_NO_VAL, desc->pdev->pdev_id);
  3416. }
  3417. #endif
  3418. /**
  3419. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3420. * @soc: DP Soc handle
  3421. * @tx_desc: software Tx descriptor
  3422. * @ts : Tx completion status from HAL/HTT descriptor
  3423. *
  3424. * Return: none
  3425. */
  3426. static inline void
  3427. dp_tx_comp_process_desc(struct dp_soc *soc,
  3428. struct dp_tx_desc_s *desc,
  3429. struct hal_tx_completion_status *ts,
  3430. struct dp_peer *peer)
  3431. {
  3432. uint64_t time_latency = 0;
  3433. /*
  3434. * m_copy/tx_capture modes are not supported for
  3435. * scatter gather packets
  3436. */
  3437. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3438. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3439. desc->timestamp);
  3440. }
  3441. dp_send_completion_to_pkt_capture(soc, desc, ts);
  3442. if (!(desc->msdu_ext_desc)) {
  3443. dp_tx_enh_unmap(soc, desc);
  3444. if (QDF_STATUS_SUCCESS ==
  3445. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  3446. return;
  3447. }
  3448. if (QDF_STATUS_SUCCESS ==
  3449. dp_get_completion_indication_for_stack(soc,
  3450. desc->pdev,
  3451. peer, ts,
  3452. desc->nbuf,
  3453. time_latency)) {
  3454. dp_send_completion_to_stack(soc,
  3455. desc->pdev,
  3456. ts->peer_id,
  3457. ts->ppdu_id,
  3458. desc->nbuf);
  3459. return;
  3460. }
  3461. }
  3462. dp_tx_comp_free_buf(soc, desc);
  3463. }
  3464. #ifdef DISABLE_DP_STATS
  3465. /**
  3466. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3467. * @soc: core txrx main context
  3468. * @tx_desc: tx desc
  3469. * @status: tx status
  3470. *
  3471. * Return: none
  3472. */
  3473. static inline
  3474. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3475. struct dp_vdev *vdev,
  3476. struct dp_tx_desc_s *tx_desc,
  3477. uint8_t status)
  3478. {
  3479. }
  3480. #else
  3481. static inline
  3482. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3483. struct dp_vdev *vdev,
  3484. struct dp_tx_desc_s *tx_desc,
  3485. uint8_t status)
  3486. {
  3487. void *osif_dev;
  3488. ol_txrx_stats_rx_fp stats_cbk;
  3489. uint8_t pkt_type;
  3490. qdf_assert(tx_desc);
  3491. if (!vdev ||
  3492. !vdev->osif_vdev ||
  3493. !vdev->stats_cb)
  3494. return;
  3495. osif_dev = vdev->osif_vdev;
  3496. stats_cbk = vdev->stats_cb;
  3497. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3498. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3499. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3500. &pkt_type);
  3501. }
  3502. #endif
  3503. /**
  3504. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3505. * @soc: DP soc handle
  3506. * @tx_desc: software descriptor head pointer
  3507. * @ts: Tx completion status
  3508. * @peer: peer handle
  3509. * @ring_id: ring number
  3510. *
  3511. * Return: none
  3512. */
  3513. static inline
  3514. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3515. struct dp_tx_desc_s *tx_desc,
  3516. struct hal_tx_completion_status *ts,
  3517. struct dp_peer *peer, uint8_t ring_id)
  3518. {
  3519. uint32_t length;
  3520. qdf_ether_header_t *eh;
  3521. struct dp_vdev *vdev = NULL;
  3522. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3523. enum qdf_dp_tx_rx_status dp_status;
  3524. if (!nbuf) {
  3525. dp_info_rl("invalid tx descriptor. nbuf NULL");
  3526. goto out;
  3527. }
  3528. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3529. length = qdf_nbuf_len(nbuf);
  3530. dp_status = dp_tx_hw_to_qdf(ts->status);
  3531. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3532. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3533. QDF_TRACE_DEFAULT_PDEV_ID,
  3534. qdf_nbuf_data_addr(nbuf),
  3535. sizeof(qdf_nbuf_data(nbuf)),
  3536. tx_desc->id, ts->status, dp_status));
  3537. dp_tx_comp_debug("-------------------- \n"
  3538. "Tx Completion Stats: \n"
  3539. "-------------------- \n"
  3540. "ack_frame_rssi = %d \n"
  3541. "first_msdu = %d \n"
  3542. "last_msdu = %d \n"
  3543. "msdu_part_of_amsdu = %d \n"
  3544. "rate_stats valid = %d \n"
  3545. "bw = %d \n"
  3546. "pkt_type = %d \n"
  3547. "stbc = %d \n"
  3548. "ldpc = %d \n"
  3549. "sgi = %d \n"
  3550. "mcs = %d \n"
  3551. "ofdma = %d \n"
  3552. "tones_in_ru = %d \n"
  3553. "tsf = %d \n"
  3554. "ppdu_id = %d \n"
  3555. "transmit_cnt = %d \n"
  3556. "tid = %d \n"
  3557. "peer_id = %d\n",
  3558. ts->ack_frame_rssi, ts->first_msdu,
  3559. ts->last_msdu, ts->msdu_part_of_amsdu,
  3560. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3561. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3562. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3563. ts->transmit_cnt, ts->tid, ts->peer_id);
  3564. /* Update SoC level stats */
  3565. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3566. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3567. if (!peer) {
  3568. dp_info_rl("peer is null or deletion in progress");
  3569. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3570. goto out;
  3571. }
  3572. vdev = peer->vdev;
  3573. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  3574. /* Update per-packet stats for mesh mode */
  3575. if (qdf_unlikely(vdev->mesh_vdev) &&
  3576. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3577. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3578. /* Update peer level stats */
  3579. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  3580. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3581. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  3582. if ((peer->vdev->tx_encap_type ==
  3583. htt_cmn_pkt_type_ethernet) &&
  3584. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3585. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  3586. }
  3587. }
  3588. } else {
  3589. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3590. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3591. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3592. if (qdf_unlikely(peer->in_twt)) {
  3593. DP_STATS_INC_PKT(peer,
  3594. tx.tx_success_twt,
  3595. 1, length);
  3596. }
  3597. }
  3598. }
  3599. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3600. dp_tx_update_peer_ext_stats(peer, tx_desc, ts->tid, ring_id);
  3601. #ifdef QCA_SUPPORT_RDK_STATS
  3602. if (soc->rdkstats_enabled)
  3603. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3604. tx_desc->timestamp,
  3605. ts->ppdu_id);
  3606. #endif
  3607. out:
  3608. return;
  3609. }
  3610. /**
  3611. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3612. * @soc: core txrx main context
  3613. * @comp_head: software descriptor head pointer
  3614. * @ring_id: ring number
  3615. *
  3616. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3617. * and release the software descriptors after processing is complete
  3618. *
  3619. * Return: none
  3620. */
  3621. static void
  3622. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3623. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3624. {
  3625. struct dp_tx_desc_s *desc;
  3626. struct dp_tx_desc_s *next;
  3627. struct hal_tx_completion_status ts;
  3628. struct dp_peer *peer = NULL;
  3629. uint16_t peer_id = DP_INVALID_PEER;
  3630. qdf_nbuf_t netbuf;
  3631. desc = comp_head;
  3632. while (desc) {
  3633. if (peer_id != desc->peer_id) {
  3634. if (peer)
  3635. dp_peer_unref_delete(peer,
  3636. DP_MOD_ID_TX_COMP);
  3637. peer_id = desc->peer_id;
  3638. peer = dp_peer_get_ref_by_id(soc, peer_id,
  3639. DP_MOD_ID_TX_COMP);
  3640. }
  3641. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3642. struct dp_pdev *pdev = desc->pdev;
  3643. if (qdf_likely(peer)) {
  3644. /*
  3645. * Increment peer statistics
  3646. * Minimal statistics update done here
  3647. */
  3648. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1,
  3649. desc->length);
  3650. if (desc->tx_status !=
  3651. HAL_TX_TQM_RR_FRAME_ACKED)
  3652. DP_STATS_INC(peer, tx.tx_failed, 1);
  3653. }
  3654. qdf_assert(pdev);
  3655. dp_tx_outstanding_dec(pdev);
  3656. /*
  3657. * Calling a QDF WRAPPER here is creating signifcant
  3658. * performance impact so avoided the wrapper call here
  3659. */
  3660. next = desc->next;
  3661. qdf_mem_unmap_nbytes_single(soc->osdev,
  3662. desc->dma_addr,
  3663. QDF_DMA_TO_DEVICE,
  3664. desc->length);
  3665. qdf_nbuf_free(desc->nbuf);
  3666. dp_tx_desc_free(soc, desc, desc->pool_id);
  3667. desc = next;
  3668. continue;
  3669. }
  3670. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3671. dp_tx_comp_process_tx_status(soc, desc, &ts, peer, ring_id);
  3672. netbuf = desc->nbuf;
  3673. /* check tx complete notification */
  3674. if (peer && qdf_nbuf_tx_notify_comp_get(netbuf))
  3675. dp_tx_notify_completion(soc, peer->vdev, desc,
  3676. netbuf, ts.status);
  3677. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3678. next = desc->next;
  3679. dp_tx_desc_release(desc, desc->pool_id);
  3680. desc = next;
  3681. }
  3682. if (peer)
  3683. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3684. }
  3685. /**
  3686. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  3687. * @soc: Handle to DP soc structure
  3688. * @tx_desc: software descriptor head pointer
  3689. * @status : Tx completion status from HTT descriptor
  3690. * @ring_id: ring number
  3691. *
  3692. * This function will process HTT Tx indication messages from Target
  3693. *
  3694. * Return: none
  3695. */
  3696. static
  3697. void dp_tx_process_htt_completion(struct dp_soc *soc,
  3698. struct dp_tx_desc_s *tx_desc, uint8_t *status,
  3699. uint8_t ring_id)
  3700. {
  3701. uint8_t tx_status;
  3702. struct dp_pdev *pdev;
  3703. struct dp_vdev *vdev;
  3704. struct hal_tx_completion_status ts = {0};
  3705. uint32_t *htt_desc = (uint32_t *)status;
  3706. struct dp_peer *peer;
  3707. struct cdp_tid_tx_stats *tid_stats = NULL;
  3708. struct htt_soc *htt_handle;
  3709. uint8_t vdev_id;
  3710. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3711. htt_handle = (struct htt_soc *)soc->htt_handle;
  3712. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3713. /*
  3714. * There can be scenario where WBM consuming descriptor enqueued
  3715. * from TQM2WBM first and TQM completion can happen before MEC
  3716. * notification comes from FW2WBM. Avoid access any field of tx
  3717. * descriptor in case of MEC notify.
  3718. */
  3719. if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY) {
  3720. /*
  3721. * Get vdev id from HTT status word in case of MEC
  3722. * notification
  3723. */
  3724. vdev_id = HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(htt_desc[3]);
  3725. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3726. return;
  3727. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3728. DP_MOD_ID_HTT_COMP);
  3729. if (!vdev)
  3730. return;
  3731. dp_tx_mec_handler(vdev, status);
  3732. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3733. return;
  3734. }
  3735. /*
  3736. * If the descriptor is already freed in vdev_detach,
  3737. * continue to next descriptor
  3738. */
  3739. if ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) && !tx_desc->flags) {
  3740. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d", tx_desc->id);
  3741. return;
  3742. }
  3743. pdev = tx_desc->pdev;
  3744. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3745. dp_tx_comp_info_rl("pdev in down state %d", tx_desc->id);
  3746. dp_tx_comp_free_buf(soc, tx_desc);
  3747. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3748. return;
  3749. }
  3750. qdf_assert(tx_desc->pdev);
  3751. vdev_id = tx_desc->vdev_id;
  3752. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3753. DP_MOD_ID_HTT_COMP);
  3754. if (!vdev)
  3755. return;
  3756. switch (tx_status) {
  3757. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3758. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3759. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3760. {
  3761. uint8_t tid;
  3762. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3763. ts.peer_id =
  3764. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3765. htt_desc[2]);
  3766. ts.tid =
  3767. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3768. htt_desc[2]);
  3769. } else {
  3770. ts.peer_id = HTT_INVALID_PEER;
  3771. ts.tid = HTT_INVALID_TID;
  3772. }
  3773. ts.ppdu_id =
  3774. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3775. htt_desc[1]);
  3776. ts.ack_frame_rssi =
  3777. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3778. htt_desc[1]);
  3779. ts.tsf = htt_desc[3];
  3780. ts.first_msdu = 1;
  3781. ts.last_msdu = 1;
  3782. tid = ts.tid;
  3783. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3784. tid = CDP_MAX_DATA_TIDS - 1;
  3785. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3786. if (qdf_unlikely(pdev->delay_stats_flag))
  3787. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3788. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3789. tid_stats->htt_status_cnt[tx_status]++;
  3790. }
  3791. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3792. DP_MOD_ID_HTT_COMP);
  3793. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, peer, ring_id);
  3794. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3795. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3796. if (qdf_likely(peer))
  3797. dp_peer_unref_delete(peer, DP_MOD_ID_HTT_COMP);
  3798. break;
  3799. }
  3800. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3801. {
  3802. dp_tx_reinject_handler(soc, vdev, tx_desc, status);
  3803. break;
  3804. }
  3805. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3806. {
  3807. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  3808. break;
  3809. }
  3810. default:
  3811. dp_tx_comp_debug("Invalid HTT tx_status %d\n",
  3812. tx_status);
  3813. break;
  3814. }
  3815. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3816. }
  3817. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3818. static inline
  3819. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3820. {
  3821. bool limit_hit = false;
  3822. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3823. limit_hit =
  3824. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  3825. if (limit_hit)
  3826. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3827. return limit_hit;
  3828. }
  3829. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3830. {
  3831. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3832. }
  3833. #else
  3834. static inline
  3835. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3836. {
  3837. return false;
  3838. }
  3839. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3840. {
  3841. return false;
  3842. }
  3843. #endif
  3844. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3845. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3846. uint32_t quota)
  3847. {
  3848. void *tx_comp_hal_desc;
  3849. uint8_t buffer_src;
  3850. uint8_t pool_id;
  3851. uint32_t tx_desc_id;
  3852. struct dp_tx_desc_s *tx_desc = NULL;
  3853. struct dp_tx_desc_s *head_desc = NULL;
  3854. struct dp_tx_desc_s *tail_desc = NULL;
  3855. uint32_t num_processed = 0;
  3856. uint32_t count;
  3857. uint32_t num_avail_for_reap = 0;
  3858. bool force_break = false;
  3859. DP_HIST_INIT();
  3860. more_data:
  3861. /* Re-initialize local variables to be re-used */
  3862. head_desc = NULL;
  3863. tail_desc = NULL;
  3864. count = 0;
  3865. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  3866. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  3867. return 0;
  3868. }
  3869. num_avail_for_reap = hal_srng_dst_num_valid(soc->hal_soc, hal_ring_hdl, 0);
  3870. if (num_avail_for_reap >= quota)
  3871. num_avail_for_reap = quota;
  3872. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  3873. /* Find head descriptor from completion ring */
  3874. while (qdf_likely(num_avail_for_reap)) {
  3875. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  3876. if (qdf_unlikely(!tx_comp_hal_desc))
  3877. break;
  3878. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  3879. /* If this buffer was not released by TQM or FW, then it is not
  3880. * Tx completion indication, assert */
  3881. if (qdf_unlikely(buffer_src !=
  3882. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  3883. (qdf_unlikely(buffer_src !=
  3884. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  3885. uint8_t wbm_internal_error;
  3886. dp_err_rl(
  3887. "Tx comp release_src != TQM | FW but from %d",
  3888. buffer_src);
  3889. hal_dump_comp_desc(tx_comp_hal_desc);
  3890. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  3891. /* When WBM sees NULL buffer_addr_info in any of
  3892. * ingress rings it sends an error indication,
  3893. * with wbm_internal_error=1, to a specific ring.
  3894. * The WBM2SW ring used to indicate these errors is
  3895. * fixed in HW, and that ring is being used as Tx
  3896. * completion ring. These errors are not related to
  3897. * Tx completions, and should just be ignored
  3898. */
  3899. wbm_internal_error = hal_get_wbm_internal_error(
  3900. soc->hal_soc,
  3901. tx_comp_hal_desc);
  3902. if (wbm_internal_error) {
  3903. dp_err_rl("Tx comp wbm_internal_error!!");
  3904. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  3905. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  3906. buffer_src)
  3907. dp_handle_wbm_internal_error(
  3908. soc,
  3909. tx_comp_hal_desc,
  3910. hal_tx_comp_get_buffer_type(
  3911. tx_comp_hal_desc));
  3912. } else {
  3913. dp_err_rl("Tx comp wbm_internal_error false");
  3914. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  3915. }
  3916. continue;
  3917. }
  3918. /* Get descriptor id */
  3919. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  3920. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3921. DP_TX_DESC_ID_POOL_OS;
  3922. /* Find Tx descriptor */
  3923. tx_desc = dp_tx_desc_find(soc, pool_id,
  3924. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3925. DP_TX_DESC_ID_PAGE_OS,
  3926. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3927. DP_TX_DESC_ID_OFFSET_OS);
  3928. /*
  3929. * If the release source is FW, process the HTT status
  3930. */
  3931. if (qdf_unlikely(buffer_src ==
  3932. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3933. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  3934. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  3935. htt_tx_status);
  3936. dp_tx_process_htt_completion(soc, tx_desc,
  3937. htt_tx_status, ring_id);
  3938. } else {
  3939. tx_desc->peer_id =
  3940. hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  3941. tx_desc->tx_status =
  3942. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  3943. /*
  3944. * If the fast completion mode is enabled extended
  3945. * metadata from descriptor is not copied
  3946. */
  3947. if (qdf_likely(tx_desc->flags &
  3948. DP_TX_DESC_FLAG_SIMPLE))
  3949. goto add_to_pool;
  3950. /*
  3951. * If the descriptor is already freed in vdev_detach,
  3952. * continue to next descriptor
  3953. */
  3954. if (qdf_unlikely
  3955. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  3956. !tx_desc->flags)) {
  3957. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  3958. tx_desc_id);
  3959. continue;
  3960. }
  3961. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3962. dp_tx_comp_info_rl("pdev in down state %d",
  3963. tx_desc_id);
  3964. dp_tx_comp_free_buf(soc, tx_desc);
  3965. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3966. goto next_desc;
  3967. }
  3968. /* Pool id is not matching. Error */
  3969. if (tx_desc->pool_id != pool_id) {
  3970. dp_tx_comp_alert("Tx Comp pool id %d not matched %d",
  3971. pool_id, tx_desc->pool_id);
  3972. qdf_assert_always(0);
  3973. }
  3974. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  3975. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  3976. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  3977. tx_desc->flags, tx_desc_id);
  3978. qdf_assert_always(0);
  3979. }
  3980. /* Collect hw completion contents */
  3981. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  3982. &tx_desc->comp, 1);
  3983. add_to_pool:
  3984. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  3985. /* First ring descriptor on the cycle */
  3986. if (!head_desc) {
  3987. head_desc = tx_desc;
  3988. tail_desc = tx_desc;
  3989. }
  3990. tail_desc->next = tx_desc;
  3991. tx_desc->next = NULL;
  3992. tail_desc = tx_desc;
  3993. }
  3994. next_desc:
  3995. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3996. /*
  3997. * Processed packet count is more than given quota
  3998. * stop to processing
  3999. */
  4000. count++;
  4001. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  4002. break;
  4003. }
  4004. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  4005. /* Process the reaped descriptors */
  4006. if (head_desc)
  4007. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  4008. if (dp_tx_comp_enable_eol_data_check(soc)) {
  4009. if (num_processed >= quota)
  4010. force_break = true;
  4011. if (!force_break &&
  4012. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  4013. hal_ring_hdl)) {
  4014. DP_STATS_INC(soc, tx.hp_oos2, 1);
  4015. if (!hif_exec_should_yield(soc->hif_handle,
  4016. int_ctx->dp_intr_id))
  4017. goto more_data;
  4018. }
  4019. }
  4020. DP_TX_HIST_STATS_PER_PDEV();
  4021. return num_processed;
  4022. }
  4023. #ifdef FEATURE_WLAN_TDLS
  4024. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4025. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  4026. {
  4027. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4028. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4029. DP_MOD_ID_TDLS);
  4030. if (!vdev) {
  4031. dp_err("vdev handle for id %d is NULL", vdev_id);
  4032. return NULL;
  4033. }
  4034. if (tx_spec & OL_TX_SPEC_NO_FREE)
  4035. vdev->is_tdls_frame = true;
  4036. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  4037. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  4038. }
  4039. #endif
  4040. static void dp_tx_vdev_update_feature_flags(struct dp_vdev *vdev)
  4041. {
  4042. struct wlan_cfg_dp_soc_ctxt *cfg;
  4043. struct dp_soc *soc;
  4044. soc = vdev->pdev->soc;
  4045. if (!soc)
  4046. return;
  4047. cfg = soc->wlan_cfg_ctx;
  4048. if (!cfg)
  4049. return;
  4050. if (vdev->opmode == wlan_op_mode_ndi)
  4051. vdev->csum_enabled = wlan_cfg_get_nan_checksum_offload(cfg);
  4052. else if ((vdev->subtype == wlan_op_subtype_p2p_device) ||
  4053. (vdev->subtype == wlan_op_subtype_p2p_cli) ||
  4054. (vdev->subtype == wlan_op_subtype_p2p_go))
  4055. vdev->csum_enabled = wlan_cfg_get_p2p_checksum_offload(cfg);
  4056. else
  4057. vdev->csum_enabled = wlan_cfg_get_checksum_offload(cfg);
  4058. }
  4059. /**
  4060. * dp_tx_vdev_attach() - attach vdev to dp tx
  4061. * @vdev: virtual device instance
  4062. *
  4063. * Return: QDF_STATUS_SUCCESS: success
  4064. * QDF_STATUS_E_RESOURCES: Error return
  4065. */
  4066. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4067. {
  4068. int pdev_id;
  4069. /*
  4070. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4071. */
  4072. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4073. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  4074. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4075. vdev->vdev_id);
  4076. pdev_id =
  4077. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4078. vdev->pdev->pdev_id);
  4079. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4080. /*
  4081. * Set HTT Extension Valid bit to 0 by default
  4082. */
  4083. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4084. dp_tx_vdev_update_search_flags(vdev);
  4085. dp_tx_vdev_update_feature_flags(vdev);
  4086. return QDF_STATUS_SUCCESS;
  4087. }
  4088. #ifndef FEATURE_WDS
  4089. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4090. {
  4091. return false;
  4092. }
  4093. #endif
  4094. /**
  4095. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4096. * @vdev: virtual device instance
  4097. *
  4098. * Return: void
  4099. *
  4100. */
  4101. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4102. {
  4103. struct dp_soc *soc = vdev->pdev->soc;
  4104. /*
  4105. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4106. * for TDLS link
  4107. *
  4108. * Enable AddrY (SA based search) only for non-WDS STA and
  4109. * ProxySTA VAP (in HKv1) modes.
  4110. *
  4111. * In all other VAP modes, only DA based search should be
  4112. * enabled
  4113. */
  4114. if (vdev->opmode == wlan_op_mode_sta &&
  4115. vdev->tdls_link_connected)
  4116. vdev->hal_desc_addr_search_flags =
  4117. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4118. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4119. !dp_tx_da_search_override(vdev))
  4120. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4121. else
  4122. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4123. /* Set search type only when peer map v2 messaging is enabled
  4124. * as we will have the search index (AST hash) only when v2 is
  4125. * enabled
  4126. */
  4127. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  4128. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  4129. else
  4130. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4131. }
  4132. static inline bool
  4133. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4134. struct dp_vdev *vdev,
  4135. struct dp_tx_desc_s *tx_desc)
  4136. {
  4137. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4138. return false;
  4139. /*
  4140. * if vdev is given, then only check whether desc
  4141. * vdev match. if vdev is NULL, then check whether
  4142. * desc pdev match.
  4143. */
  4144. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4145. (tx_desc->pdev == pdev);
  4146. }
  4147. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4148. /**
  4149. * dp_tx_desc_flush() - release resources associated
  4150. * to TX Desc
  4151. *
  4152. * @dp_pdev: Handle to DP pdev structure
  4153. * @vdev: virtual device instance
  4154. * NULL: no specific Vdev is required and check all allcated TX desc
  4155. * on this pdev.
  4156. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4157. *
  4158. * @force_free:
  4159. * true: flush the TX desc.
  4160. * false: only reset the Vdev in each allocated TX desc
  4161. * that associated to current Vdev.
  4162. *
  4163. * This function will go through the TX desc pool to flush
  4164. * the outstanding TX data or reset Vdev to NULL in associated TX
  4165. * Desc.
  4166. */
  4167. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4168. bool force_free)
  4169. {
  4170. uint8_t i;
  4171. uint32_t j;
  4172. uint32_t num_desc, page_id, offset;
  4173. uint16_t num_desc_per_page;
  4174. struct dp_soc *soc = pdev->soc;
  4175. struct dp_tx_desc_s *tx_desc = NULL;
  4176. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4177. if (!vdev && !force_free) {
  4178. dp_err("Reset TX desc vdev, Vdev param is required!");
  4179. return;
  4180. }
  4181. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4182. tx_desc_pool = &soc->tx_desc[i];
  4183. if (!(tx_desc_pool->pool_size) ||
  4184. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4185. !(tx_desc_pool->desc_pages.cacheable_pages))
  4186. continue;
  4187. /*
  4188. * Add flow pool lock protection in case pool is freed
  4189. * due to all tx_desc is recycled when handle TX completion.
  4190. * this is not necessary when do force flush as:
  4191. * a. double lock will happen if dp_tx_desc_release is
  4192. * also trying to acquire it.
  4193. * b. dp interrupt has been disabled before do force TX desc
  4194. * flush in dp_pdev_deinit().
  4195. */
  4196. if (!force_free)
  4197. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4198. num_desc = tx_desc_pool->pool_size;
  4199. num_desc_per_page =
  4200. tx_desc_pool->desc_pages.num_element_per_page;
  4201. for (j = 0; j < num_desc; j++) {
  4202. page_id = j / num_desc_per_page;
  4203. offset = j % num_desc_per_page;
  4204. if (qdf_unlikely(!(tx_desc_pool->
  4205. desc_pages.cacheable_pages)))
  4206. break;
  4207. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4208. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4209. /*
  4210. * Free TX desc if force free is
  4211. * required, otherwise only reset vdev
  4212. * in this TX desc.
  4213. */
  4214. if (force_free) {
  4215. dp_tx_comp_free_buf(soc, tx_desc);
  4216. dp_tx_desc_release(tx_desc, i);
  4217. } else {
  4218. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4219. }
  4220. }
  4221. }
  4222. if (!force_free)
  4223. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4224. }
  4225. }
  4226. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4227. /**
  4228. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4229. *
  4230. * @soc: Handle to DP soc structure
  4231. * @tx_desc: pointer of one TX desc
  4232. * @desc_pool_id: TX Desc pool id
  4233. */
  4234. static inline void
  4235. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4236. uint8_t desc_pool_id)
  4237. {
  4238. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4239. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4240. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4241. }
  4242. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4243. bool force_free)
  4244. {
  4245. uint8_t i, num_pool;
  4246. uint32_t j;
  4247. uint32_t num_desc, page_id, offset;
  4248. uint16_t num_desc_per_page;
  4249. struct dp_soc *soc = pdev->soc;
  4250. struct dp_tx_desc_s *tx_desc = NULL;
  4251. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4252. if (!vdev && !force_free) {
  4253. dp_err("Reset TX desc vdev, Vdev param is required!");
  4254. return;
  4255. }
  4256. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4257. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4258. for (i = 0; i < num_pool; i++) {
  4259. tx_desc_pool = &soc->tx_desc[i];
  4260. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4261. continue;
  4262. num_desc_per_page =
  4263. tx_desc_pool->desc_pages.num_element_per_page;
  4264. for (j = 0; j < num_desc; j++) {
  4265. page_id = j / num_desc_per_page;
  4266. offset = j % num_desc_per_page;
  4267. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4268. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4269. if (force_free) {
  4270. dp_tx_comp_free_buf(soc, tx_desc);
  4271. dp_tx_desc_release(tx_desc, i);
  4272. } else {
  4273. dp_tx_desc_reset_vdev(soc, tx_desc,
  4274. i);
  4275. }
  4276. }
  4277. }
  4278. }
  4279. }
  4280. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4281. /**
  4282. * dp_tx_vdev_detach() - detach vdev from dp tx
  4283. * @vdev: virtual device instance
  4284. *
  4285. * Return: QDF_STATUS_SUCCESS: success
  4286. * QDF_STATUS_E_RESOURCES: Error return
  4287. */
  4288. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4289. {
  4290. struct dp_pdev *pdev = vdev->pdev;
  4291. /* Reset TX desc associated to this Vdev as NULL */
  4292. dp_tx_desc_flush(pdev, vdev, false);
  4293. return QDF_STATUS_SUCCESS;
  4294. }
  4295. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4296. /* Pools will be allocated dynamically */
  4297. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4298. int num_desc)
  4299. {
  4300. uint8_t i;
  4301. for (i = 0; i < num_pool; i++) {
  4302. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4303. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4304. }
  4305. return QDF_STATUS_SUCCESS;
  4306. }
  4307. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4308. int num_desc)
  4309. {
  4310. return QDF_STATUS_SUCCESS;
  4311. }
  4312. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4313. {
  4314. }
  4315. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4316. {
  4317. uint8_t i;
  4318. for (i = 0; i < num_pool; i++)
  4319. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4320. }
  4321. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4322. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4323. int num_desc)
  4324. {
  4325. uint8_t i, count;
  4326. /* Allocate software Tx descriptor pools */
  4327. for (i = 0; i < num_pool; i++) {
  4328. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4329. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4330. FL("Tx Desc Pool alloc %d failed %pK"),
  4331. i, soc);
  4332. goto fail;
  4333. }
  4334. }
  4335. return QDF_STATUS_SUCCESS;
  4336. fail:
  4337. for (count = 0; count < i; count++)
  4338. dp_tx_desc_pool_free(soc, count);
  4339. return QDF_STATUS_E_NOMEM;
  4340. }
  4341. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4342. int num_desc)
  4343. {
  4344. uint8_t i;
  4345. for (i = 0; i < num_pool; i++) {
  4346. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4347. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4348. FL("Tx Desc Pool init %d failed %pK"),
  4349. i, soc);
  4350. return QDF_STATUS_E_NOMEM;
  4351. }
  4352. }
  4353. return QDF_STATUS_SUCCESS;
  4354. }
  4355. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4356. {
  4357. uint8_t i;
  4358. for (i = 0; i < num_pool; i++)
  4359. dp_tx_desc_pool_deinit(soc, i);
  4360. }
  4361. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4362. {
  4363. uint8_t i;
  4364. for (i = 0; i < num_pool; i++)
  4365. dp_tx_desc_pool_free(soc, i);
  4366. }
  4367. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4368. /**
  4369. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4370. * @soc: core txrx main context
  4371. * @num_pool: number of pools
  4372. *
  4373. */
  4374. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4375. {
  4376. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4377. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4378. }
  4379. /**
  4380. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4381. * @soc: core txrx main context
  4382. * @num_pool: number of pools
  4383. *
  4384. */
  4385. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4386. {
  4387. dp_tx_tso_desc_pool_free(soc, num_pool);
  4388. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4389. }
  4390. /**
  4391. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4392. * @soc: core txrx main context
  4393. *
  4394. * This function frees all tx related descriptors as below
  4395. * 1. Regular TX descriptors (static pools)
  4396. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4397. * 3. TSO descriptors
  4398. *
  4399. */
  4400. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4401. {
  4402. uint8_t num_pool;
  4403. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4404. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4405. dp_tx_ext_desc_pool_free(soc, num_pool);
  4406. dp_tx_delete_static_pools(soc, num_pool);
  4407. }
  4408. /**
  4409. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4410. * @soc: core txrx main context
  4411. *
  4412. * This function de-initializes all tx related descriptors as below
  4413. * 1. Regular TX descriptors (static pools)
  4414. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4415. * 3. TSO descriptors
  4416. *
  4417. */
  4418. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4419. {
  4420. uint8_t num_pool;
  4421. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4422. dp_tx_flow_control_deinit(soc);
  4423. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4424. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4425. dp_tx_deinit_static_pools(soc, num_pool);
  4426. }
  4427. /**
  4428. * dp_tso_attach() - TSO attach handler
  4429. * @txrx_soc: Opaque Dp handle
  4430. *
  4431. * Reserve TSO descriptor buffers
  4432. *
  4433. * Return: QDF_STATUS_E_FAILURE on failure or
  4434. * QDF_STATUS_SUCCESS on success
  4435. */
  4436. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4437. uint8_t num_pool,
  4438. uint16_t num_desc)
  4439. {
  4440. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4441. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4442. return QDF_STATUS_E_FAILURE;
  4443. }
  4444. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4445. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4446. num_pool, soc);
  4447. return QDF_STATUS_E_FAILURE;
  4448. }
  4449. return QDF_STATUS_SUCCESS;
  4450. }
  4451. /**
  4452. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4453. * @soc: DP soc handle
  4454. * @num_pool: Number of pools
  4455. * @num_desc: Number of descriptors
  4456. *
  4457. * Initialize TSO descriptor pools
  4458. *
  4459. * Return: QDF_STATUS_E_FAILURE on failure or
  4460. * QDF_STATUS_SUCCESS on success
  4461. */
  4462. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4463. uint8_t num_pool,
  4464. uint16_t num_desc)
  4465. {
  4466. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4467. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4468. return QDF_STATUS_E_FAILURE;
  4469. }
  4470. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4471. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4472. num_pool, soc);
  4473. return QDF_STATUS_E_FAILURE;
  4474. }
  4475. return QDF_STATUS_SUCCESS;
  4476. }
  4477. /**
  4478. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4479. * @soc: core txrx main context
  4480. *
  4481. * This function allocates memory for following descriptor pools
  4482. * 1. regular sw tx descriptor pools (static pools)
  4483. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4484. * 3. TSO descriptor pools
  4485. *
  4486. * Return: QDF_STATUS_SUCCESS: success
  4487. * QDF_STATUS_E_RESOURCES: Error return
  4488. */
  4489. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4490. {
  4491. uint8_t num_pool;
  4492. uint32_t num_desc;
  4493. uint32_t num_ext_desc;
  4494. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4495. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4496. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4497. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4498. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4499. __func__, num_pool, num_desc);
  4500. if ((num_pool > MAX_TXDESC_POOLS) ||
  4501. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4502. goto fail1;
  4503. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4504. goto fail1;
  4505. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4506. goto fail2;
  4507. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4508. return QDF_STATUS_SUCCESS;
  4509. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4510. goto fail3;
  4511. return QDF_STATUS_SUCCESS;
  4512. fail3:
  4513. dp_tx_ext_desc_pool_free(soc, num_pool);
  4514. fail2:
  4515. dp_tx_delete_static_pools(soc, num_pool);
  4516. fail1:
  4517. return QDF_STATUS_E_RESOURCES;
  4518. }
  4519. /**
  4520. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4521. * @soc: core txrx main context
  4522. *
  4523. * This function initializes the following TX descriptor pools
  4524. * 1. regular sw tx descriptor pools (static pools)
  4525. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4526. * 3. TSO descriptor pools
  4527. *
  4528. * Return: QDF_STATUS_SUCCESS: success
  4529. * QDF_STATUS_E_RESOURCES: Error return
  4530. */
  4531. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4532. {
  4533. uint8_t num_pool;
  4534. uint32_t num_desc;
  4535. uint32_t num_ext_desc;
  4536. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4537. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4538. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4539. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4540. goto fail1;
  4541. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4542. goto fail2;
  4543. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4544. return QDF_STATUS_SUCCESS;
  4545. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4546. goto fail3;
  4547. dp_tx_flow_control_init(soc);
  4548. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4549. return QDF_STATUS_SUCCESS;
  4550. fail3:
  4551. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4552. fail2:
  4553. dp_tx_deinit_static_pools(soc, num_pool);
  4554. fail1:
  4555. return QDF_STATUS_E_RESOURCES;
  4556. }
  4557. /**
  4558. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4559. * @txrx_soc: dp soc handle
  4560. *
  4561. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4562. * QDF_STATUS_E_FAILURE
  4563. */
  4564. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4565. {
  4566. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4567. uint8_t num_pool;
  4568. uint32_t num_desc;
  4569. uint32_t num_ext_desc;
  4570. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4571. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4572. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4573. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4574. return QDF_STATUS_E_FAILURE;
  4575. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4576. return QDF_STATUS_E_FAILURE;
  4577. return QDF_STATUS_SUCCESS;
  4578. }
  4579. /**
  4580. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4581. * @txrx_soc: dp soc handle
  4582. *
  4583. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4584. */
  4585. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4586. {
  4587. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4588. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4589. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4590. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4591. return QDF_STATUS_SUCCESS;
  4592. }