dp_ipa.c 64 KB

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  1. /*
  2. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifdef IPA_OFFLOAD
  17. #include <qdf_ipa_wdi3.h>
  18. #include <qdf_types.h>
  19. #include <qdf_lock.h>
  20. #include <hal_hw_headers.h>
  21. #include <hal_api.h>
  22. #include <hif.h>
  23. #include <htt.h>
  24. #include <wdi_event.h>
  25. #include <queue.h>
  26. #include "dp_types.h"
  27. #include "dp_htt.h"
  28. #include "dp_tx.h"
  29. #include "dp_rx.h"
  30. #include "dp_ipa.h"
  31. /* Ring index for WBM2SW2 release ring */
  32. #define IPA_TX_COMP_RING_IDX HAL_IPA_TX_COMP_RING_IDX
  33. /* Hard coded config parameters until dp_ops_cfg.cfg_attach implemented */
  34. #define CFG_IPA_UC_TX_BUF_SIZE_DEFAULT (2048)
  35. /* WAR for IPA_OFFLOAD case. In some cases, its observed that WBM tries to
  36. * release a buffer into WBM2SW RELEASE ring for IPA, and the ring is full.
  37. * This causes back pressure, resulting in a FW crash.
  38. * By leaving some entries with no buffer attached, WBM will be able to write
  39. * to the ring, and from dumps we can figure out the buffer which is causing
  40. * this issue.
  41. */
  42. #define DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES 16
  43. /**
  44. *struct dp_ipa_reo_remap_record - history for dp ipa reo remaps
  45. * @ix0_reg: reo destination ring IX0 value
  46. * @ix2_reg: reo destination ring IX2 value
  47. * @ix3_reg: reo destination ring IX3 value
  48. */
  49. struct dp_ipa_reo_remap_record {
  50. uint64_t timestamp;
  51. uint32_t ix0_reg;
  52. uint32_t ix2_reg;
  53. uint32_t ix3_reg;
  54. };
  55. #define REO_REMAP_HISTORY_SIZE 32
  56. struct dp_ipa_reo_remap_record dp_ipa_reo_remap_history[REO_REMAP_HISTORY_SIZE];
  57. static qdf_atomic_t dp_ipa_reo_remap_history_index;
  58. static int dp_ipa_reo_remap_record_index_next(qdf_atomic_t *index)
  59. {
  60. int next = qdf_atomic_inc_return(index);
  61. if (next == REO_REMAP_HISTORY_SIZE)
  62. qdf_atomic_sub(REO_REMAP_HISTORY_SIZE, index);
  63. return next % REO_REMAP_HISTORY_SIZE;
  64. }
  65. /**
  66. * dp_ipa_reo_remap_history_add() - Record dp ipa reo remap values
  67. * @ix0_val: reo destination ring IX0 value
  68. * @ix2_val: reo destination ring IX2 value
  69. * @ix3_val: reo destination ring IX3 value
  70. *
  71. * Return: None
  72. */
  73. static void dp_ipa_reo_remap_history_add(uint32_t ix0_val, uint32_t ix2_val,
  74. uint32_t ix3_val)
  75. {
  76. int idx = dp_ipa_reo_remap_record_index_next(
  77. &dp_ipa_reo_remap_history_index);
  78. struct dp_ipa_reo_remap_record *record = &dp_ipa_reo_remap_history[idx];
  79. record->timestamp = qdf_get_log_timestamp();
  80. record->ix0_reg = ix0_val;
  81. record->ix2_reg = ix2_val;
  82. record->ix3_reg = ix3_val;
  83. }
  84. static QDF_STATUS __dp_ipa_handle_buf_smmu_mapping(struct dp_soc *soc,
  85. qdf_nbuf_t nbuf,
  86. uint32_t size,
  87. bool create)
  88. {
  89. qdf_mem_info_t mem_map_table = {0};
  90. qdf_update_mem_map_table(soc->osdev, &mem_map_table,
  91. qdf_nbuf_get_frag_paddr(nbuf, 0),
  92. size);
  93. if (create)
  94. return qdf_ipa_wdi_create_smmu_mapping(1, &mem_map_table);
  95. else
  96. return qdf_ipa_wdi_release_smmu_mapping(1, &mem_map_table);
  97. }
  98. QDF_STATUS dp_ipa_handle_rx_buf_smmu_mapping(struct dp_soc *soc,
  99. qdf_nbuf_t nbuf,
  100. uint32_t size,
  101. bool create)
  102. {
  103. struct dp_pdev *pdev;
  104. int i;
  105. for (i = 0; i < soc->pdev_count; i++) {
  106. pdev = soc->pdev_list[i];
  107. if (pdev && pdev->monitor_configured)
  108. return QDF_STATUS_SUCCESS;
  109. }
  110. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx) ||
  111. !qdf_mem_smmu_s1_enabled(soc->osdev))
  112. return QDF_STATUS_SUCCESS;
  113. /**
  114. * Even if ipa pipes is disabled, but if it's unmap
  115. * operation and nbuf has done ipa smmu map before,
  116. * do ipa smmu unmap as well.
  117. */
  118. if (!qdf_atomic_read(&soc->ipa_pipes_enabled)) {
  119. if (!create && qdf_nbuf_is_rx_ipa_smmu_map(nbuf)) {
  120. DP_STATS_INC(soc, rx.err.ipa_unmap_no_pipe, 1);
  121. } else {
  122. return QDF_STATUS_SUCCESS;
  123. }
  124. }
  125. if (qdf_unlikely(create == qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  126. if (create) {
  127. DP_STATS_INC(soc, rx.err.ipa_smmu_map_dup, 1);
  128. } else {
  129. DP_STATS_INC(soc, rx.err.ipa_smmu_unmap_dup, 1);
  130. }
  131. return QDF_STATUS_E_INVAL;
  132. }
  133. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  134. return __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, size, create);
  135. }
  136. static QDF_STATUS __dp_ipa_tx_buf_smmu_mapping(
  137. struct dp_soc *soc,
  138. struct dp_pdev *pdev,
  139. bool create)
  140. {
  141. uint32_t index;
  142. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  143. uint32_t tx_buffer_cnt = soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt;
  144. qdf_nbuf_t nbuf;
  145. uint32_t buf_len;
  146. if (!ipa_is_ready()) {
  147. dp_info("IPA is not READY");
  148. return 0;
  149. }
  150. for (index = 0; index < tx_buffer_cnt; index++) {
  151. nbuf = (qdf_nbuf_t)
  152. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[index];
  153. if (!nbuf)
  154. continue;
  155. buf_len = qdf_nbuf_get_data_len(nbuf);
  156. ret = __dp_ipa_handle_buf_smmu_mapping(
  157. soc, nbuf, buf_len, create);
  158. qdf_assert_always(!ret);
  159. }
  160. return ret;
  161. }
  162. #ifdef RX_DESC_MULTI_PAGE_ALLOC
  163. static QDF_STATUS dp_ipa_handle_rx_buf_pool_smmu_mapping(struct dp_soc *soc,
  164. struct dp_pdev *pdev,
  165. bool create)
  166. {
  167. struct rx_desc_pool *rx_pool;
  168. uint8_t pdev_id;
  169. uint32_t num_desc, page_id, offset, i;
  170. uint16_t num_desc_per_page;
  171. union dp_rx_desc_list_elem_t *rx_desc_elem;
  172. struct dp_rx_desc *rx_desc;
  173. qdf_nbuf_t nbuf;
  174. if (!qdf_ipa_is_ready())
  175. return QDF_STATUS_SUCCESS;
  176. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  177. return QDF_STATUS_SUCCESS;
  178. pdev_id = pdev->pdev_id;
  179. rx_pool = &soc->rx_desc_buf[pdev_id];
  180. qdf_spin_lock_bh(&rx_pool->lock);
  181. num_desc = rx_pool->pool_size;
  182. num_desc_per_page = rx_pool->desc_pages.num_element_per_page;
  183. for (i = 0; i < num_desc; i++) {
  184. page_id = i / num_desc_per_page;
  185. offset = i % num_desc_per_page;
  186. if (qdf_unlikely(!(rx_pool->desc_pages.cacheable_pages)))
  187. break;
  188. rx_desc_elem = dp_rx_desc_find(page_id, offset, rx_pool);
  189. rx_desc = &rx_desc_elem->rx_desc;
  190. if ((!(rx_desc->in_use)) || rx_desc->unmapped)
  191. continue;
  192. nbuf = rx_desc->nbuf;
  193. if (qdf_unlikely(create ==
  194. qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  195. if (create) {
  196. DP_STATS_INC(soc,
  197. rx.err.ipa_smmu_map_dup, 1);
  198. } else {
  199. DP_STATS_INC(soc,
  200. rx.err.ipa_smmu_unmap_dup, 1);
  201. }
  202. continue;
  203. }
  204. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  205. __dp_ipa_handle_buf_smmu_mapping(soc, nbuf,
  206. rx_pool->buf_size, create);
  207. }
  208. qdf_spin_unlock_bh(&rx_pool->lock);
  209. return QDF_STATUS_SUCCESS;
  210. }
  211. #else
  212. static QDF_STATUS dp_ipa_handle_rx_buf_pool_smmu_mapping(struct dp_soc *soc,
  213. struct dp_pdev *pdev,
  214. bool create)
  215. {
  216. struct rx_desc_pool *rx_pool;
  217. uint8_t pdev_id;
  218. qdf_nbuf_t nbuf;
  219. int i;
  220. if (!qdf_ipa_is_ready())
  221. return QDF_STATUS_SUCCESS;
  222. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  223. return QDF_STATUS_SUCCESS;
  224. pdev_id = pdev->pdev_id;
  225. rx_pool = &soc->rx_desc_buf[pdev_id];
  226. qdf_spin_lock_bh(&rx_pool->lock);
  227. for (i = 0; i < rx_pool->pool_size; i++) {
  228. if ((!(rx_pool->array[i].rx_desc.in_use)) ||
  229. rx_pool->array[i].rx_desc.unmapped)
  230. continue;
  231. nbuf = rx_pool->array[i].rx_desc.nbuf;
  232. if (qdf_unlikely(create ==
  233. qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  234. if (create) {
  235. DP_STATS_INC(soc,
  236. rx.err.ipa_smmu_map_dup, 1);
  237. } else {
  238. DP_STATS_INC(soc,
  239. rx.err.ipa_smmu_unmap_dup, 1);
  240. }
  241. continue;
  242. }
  243. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  244. __dp_ipa_handle_buf_smmu_mapping(soc, nbuf,
  245. rx_pool->buf_size, create);
  246. }
  247. qdf_spin_unlock_bh(&rx_pool->lock);
  248. return QDF_STATUS_SUCCESS;
  249. }
  250. #endif /* RX_DESC_MULTI_PAGE_ALLOC */
  251. /**
  252. * dp_tx_ipa_uc_detach - Free autonomy TX resources
  253. * @soc: data path instance
  254. * @pdev: core txrx pdev context
  255. *
  256. * Free allocated TX buffers with WBM SRNG
  257. *
  258. * Return: none
  259. */
  260. static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  261. {
  262. int idx;
  263. qdf_nbuf_t nbuf;
  264. struct dp_ipa_resources *ipa_res;
  265. for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
  266. nbuf = (qdf_nbuf_t)
  267. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx];
  268. if (!nbuf)
  269. continue;
  270. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_BIDIRECTIONAL);
  271. qdf_mem_dp_tx_skb_cnt_dec();
  272. qdf_mem_dp_tx_skb_dec(qdf_nbuf_get_end_offset(nbuf));
  273. qdf_nbuf_free(nbuf);
  274. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx] =
  275. (void *)NULL;
  276. }
  277. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
  278. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
  279. ipa_res = &pdev->ipa_resource;
  280. if (!ipa_res->is_db_ddr_mapped)
  281. iounmap(ipa_res->tx_comp_doorbell_vaddr);
  282. qdf_mem_free_sgtable(&ipa_res->tx_ring.sgtable);
  283. qdf_mem_free_sgtable(&ipa_res->tx_comp_ring.sgtable);
  284. }
  285. /**
  286. * dp_rx_ipa_uc_detach - free autonomy RX resources
  287. * @soc: data path instance
  288. * @pdev: core txrx pdev context
  289. *
  290. * This function will detach DP RX into main device context
  291. * will free DP Rx resources.
  292. *
  293. * Return: none
  294. */
  295. static void dp_rx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  296. {
  297. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  298. qdf_mem_free_sgtable(&ipa_res->rx_rdy_ring.sgtable);
  299. qdf_mem_free_sgtable(&ipa_res->rx_refill_ring.sgtable);
  300. }
  301. int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  302. {
  303. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  304. return QDF_STATUS_SUCCESS;
  305. /* TX resource detach */
  306. dp_tx_ipa_uc_detach(soc, pdev);
  307. /* RX resource detach */
  308. dp_rx_ipa_uc_detach(soc, pdev);
  309. return QDF_STATUS_SUCCESS; /* success */
  310. }
  311. /**
  312. * dp_tx_ipa_uc_attach - Allocate autonomy TX resources
  313. * @soc: data path instance
  314. * @pdev: Physical device handle
  315. *
  316. * Allocate TX buffer from non-cacheable memory
  317. * Attache allocated TX buffers with WBM SRNG
  318. *
  319. * Return: int
  320. */
  321. static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  322. {
  323. uint32_t tx_buffer_count;
  324. uint32_t ring_base_align = 8;
  325. qdf_dma_addr_t buffer_paddr;
  326. struct hal_srng *wbm_srng = (struct hal_srng *)
  327. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  328. struct hal_srng_params srng_params;
  329. uint32_t paddr_lo;
  330. uint32_t paddr_hi;
  331. void *ring_entry;
  332. int num_entries;
  333. qdf_nbuf_t nbuf;
  334. int retval = QDF_STATUS_SUCCESS;
  335. int max_alloc_count = 0;
  336. /*
  337. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  338. * unsigned int uc_tx_buf_sz =
  339. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  340. */
  341. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  342. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  343. hal_get_srng_params(soc->hal_soc, hal_srng_to_hal_ring_handle(wbm_srng),
  344. &srng_params);
  345. num_entries = srng_params.num_entries;
  346. max_alloc_count =
  347. num_entries - DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES;
  348. if (max_alloc_count <= 0) {
  349. dp_err("incorrect value for buffer count %u", max_alloc_count);
  350. return -EINVAL;
  351. }
  352. dp_info("requested %d buffers to be posted to wbm ring",
  353. max_alloc_count);
  354. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned =
  355. qdf_mem_malloc(num_entries *
  356. sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned));
  357. if (!soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned) {
  358. dp_err("IPA WBM Ring Tx buf pool vaddr alloc fail");
  359. return -ENOMEM;
  360. }
  361. hal_srng_access_start_unlocked(soc->hal_soc,
  362. hal_srng_to_hal_ring_handle(wbm_srng));
  363. /*
  364. * Allocate Tx buffers as many as possible.
  365. * Leave DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES empty
  366. * Populate Tx buffers into WBM2IPA ring
  367. * This initial buffer population will simulate H/W as source ring,
  368. * and update HP
  369. */
  370. for (tx_buffer_count = 0;
  371. tx_buffer_count < max_alloc_count - 1; tx_buffer_count++) {
  372. nbuf = qdf_nbuf_alloc(soc->osdev, alloc_size, 0, 256, FALSE);
  373. if (!nbuf)
  374. break;
  375. ring_entry = hal_srng_dst_get_next_hp(soc->hal_soc,
  376. hal_srng_to_hal_ring_handle(wbm_srng));
  377. if (!ring_entry) {
  378. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  379. "%s: Failed to get WBM ring entry",
  380. __func__);
  381. qdf_nbuf_free(nbuf);
  382. break;
  383. }
  384. qdf_nbuf_map_single(soc->osdev, nbuf,
  385. QDF_DMA_BIDIRECTIONAL);
  386. buffer_paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  387. qdf_mem_dp_tx_skb_cnt_inc();
  388. qdf_mem_dp_tx_skb_inc(qdf_nbuf_get_end_offset(nbuf));
  389. paddr_lo = ((uint64_t)buffer_paddr & 0x00000000ffffffff);
  390. paddr_hi = ((uint64_t)buffer_paddr & 0x0000001f00000000) >> 32;
  391. HAL_RXDMA_PADDR_LO_SET(ring_entry, paddr_lo);
  392. HAL_RXDMA_PADDR_HI_SET(ring_entry, paddr_hi);
  393. HAL_RXDMA_MANAGER_SET(ring_entry, (IPA_TCL_DATA_RING_IDX +
  394. HAL_WBM_SW0_BM_ID));
  395. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[tx_buffer_count]
  396. = (void *)nbuf;
  397. }
  398. hal_srng_access_end_unlocked(soc->hal_soc,
  399. hal_srng_to_hal_ring_handle(wbm_srng));
  400. soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt = tx_buffer_count;
  401. if (tx_buffer_count) {
  402. dp_info("IPA WDI TX buffer: %d allocated", tx_buffer_count);
  403. } else {
  404. dp_err("No IPA WDI TX buffer allocated!");
  405. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
  406. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
  407. retval = -ENOMEM;
  408. }
  409. return retval;
  410. }
  411. /**
  412. * dp_rx_ipa_uc_attach - Allocate autonomy RX resources
  413. * @soc: data path instance
  414. * @pdev: core txrx pdev context
  415. *
  416. * This function will attach a DP RX instance into the main
  417. * device (SOC) context.
  418. *
  419. * Return: QDF_STATUS_SUCCESS: success
  420. * QDF_STATUS_E_RESOURCES: Error return
  421. */
  422. static int dp_rx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  423. {
  424. return QDF_STATUS_SUCCESS;
  425. }
  426. int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  427. {
  428. int error;
  429. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  430. return QDF_STATUS_SUCCESS;
  431. /* TX resource attach */
  432. error = dp_tx_ipa_uc_attach(soc, pdev);
  433. if (error) {
  434. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  435. "%s: DP IPA UC TX attach fail code %d",
  436. __func__, error);
  437. return error;
  438. }
  439. /* RX resource attach */
  440. error = dp_rx_ipa_uc_attach(soc, pdev);
  441. if (error) {
  442. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  443. "%s: DP IPA UC RX attach fail code %d",
  444. __func__, error);
  445. dp_tx_ipa_uc_detach(soc, pdev);
  446. return error;
  447. }
  448. return QDF_STATUS_SUCCESS; /* success */
  449. }
  450. /*
  451. * dp_ipa_ring_resource_setup() - setup IPA ring resources
  452. * @soc: data path SoC handle
  453. *
  454. * Return: none
  455. */
  456. int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  457. struct dp_pdev *pdev)
  458. {
  459. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  460. struct hal_srng *hal_srng;
  461. struct hal_srng_params srng_params;
  462. qdf_dma_addr_t hp_addr;
  463. unsigned long addr_offset, dev_base_paddr;
  464. uint32_t ix0;
  465. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  466. return QDF_STATUS_SUCCESS;
  467. /* IPA TCL_DATA Ring - HAL_SRNG_SW2TCL3 */
  468. hal_srng = (struct hal_srng *)
  469. soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng;
  470. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  471. hal_srng_to_hal_ring_handle(hal_srng),
  472. &srng_params);
  473. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr =
  474. srng_params.ring_base_paddr;
  475. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr =
  476. srng_params.ring_base_vaddr;
  477. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size =
  478. (srng_params.num_entries * srng_params.entry_size) << 2;
  479. /*
  480. * For the register backed memory addresses, use the scn->mem_pa to
  481. * calculate the physical address of the shadow registers
  482. */
  483. dev_base_paddr =
  484. (unsigned long)
  485. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  486. addr_offset = (unsigned long)(hal_srng->u.src_ring.hp_addr) -
  487. (unsigned long)(hal_soc->dev_base_addr);
  488. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr =
  489. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  490. dp_info("IPA TCL_DATA Ring addr_offset=%x, dev_base_paddr=%x, hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  491. (unsigned int)addr_offset,
  492. (unsigned int)dev_base_paddr,
  493. (unsigned int)(soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr),
  494. (void *)soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr,
  495. (void *)soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr,
  496. srng_params.num_entries,
  497. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size);
  498. /* IPA TX COMP Ring - HAL_SRNG_WBM2SW2_RELEASE */
  499. hal_srng = (struct hal_srng *)
  500. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  501. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  502. hal_srng_to_hal_ring_handle(hal_srng),
  503. &srng_params);
  504. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr =
  505. srng_params.ring_base_paddr;
  506. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr =
  507. srng_params.ring_base_vaddr;
  508. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size =
  509. (srng_params.num_entries * srng_params.entry_size) << 2;
  510. soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr =
  511. hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  512. hal_srng_to_hal_ring_handle(hal_srng));
  513. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  514. (unsigned long)(hal_soc->dev_base_addr);
  515. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr =
  516. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  517. dp_info("IPA TX COMP Ring addr_offset=%x, dev_base_paddr=%x, ipa_wbm_tp_paddr=%x paddr=%pK vaddr=0%pK size= %u(%u bytes)",
  518. (unsigned int)addr_offset,
  519. (unsigned int)dev_base_paddr,
  520. (unsigned int)(soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr),
  521. (void *)soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr,
  522. (void *)soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr,
  523. srng_params.num_entries,
  524. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size);
  525. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW4 */
  526. hal_srng = (struct hal_srng *)
  527. soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  528. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  529. hal_srng_to_hal_ring_handle(hal_srng),
  530. &srng_params);
  531. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr =
  532. srng_params.ring_base_paddr;
  533. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr =
  534. srng_params.ring_base_vaddr;
  535. soc->ipa_uc_rx_rsc.ipa_reo_ring_size =
  536. (srng_params.num_entries * srng_params.entry_size) << 2;
  537. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  538. (unsigned long)(hal_soc->dev_base_addr);
  539. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr =
  540. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  541. dp_info("IPA REO_DEST Ring addr_offset=%x, dev_base_paddr=%x, tp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  542. (unsigned int)addr_offset,
  543. (unsigned int)dev_base_paddr,
  544. (unsigned int)(soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr),
  545. (void *)soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr,
  546. (void *)soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr,
  547. srng_params.num_entries,
  548. soc->ipa_uc_rx_rsc.ipa_reo_ring_size);
  549. hal_srng = (struct hal_srng *)
  550. pdev->rx_refill_buf_ring2.hal_srng;
  551. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  552. hal_srng_to_hal_ring_handle(hal_srng),
  553. &srng_params);
  554. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr =
  555. srng_params.ring_base_paddr;
  556. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr =
  557. srng_params.ring_base_vaddr;
  558. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size =
  559. (srng_params.num_entries * srng_params.entry_size) << 2;
  560. hp_addr = hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  561. hal_srng_to_hal_ring_handle(hal_srng));
  562. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr =
  563. qdf_mem_paddr_from_dmaaddr(soc->osdev, hp_addr);
  564. dp_info("IPA REFILL_BUF Ring hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  565. (unsigned int)(soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr),
  566. (void *)soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr,
  567. (void *)soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr,
  568. srng_params.num_entries,
  569. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size);
  570. /*
  571. * Set DEST_RING_MAPPING_4 to SW2 as default value for
  572. * DESTINATION_RING_CTRL_IX_0.
  573. */
  574. ix0 = HAL_REO_REMAP_IX0(REO_REMAP_TCL, 0) |
  575. HAL_REO_REMAP_IX0(REO_REMAP_SW1, 1) |
  576. HAL_REO_REMAP_IX0(REO_REMAP_SW2, 2) |
  577. HAL_REO_REMAP_IX0(REO_REMAP_SW3, 3) |
  578. HAL_REO_REMAP_IX0(REO_REMAP_SW2, 4) |
  579. HAL_REO_REMAP_IX0(REO_REMAP_RELEASE, 5) |
  580. HAL_REO_REMAP_IX0(REO_REMAP_FW, 6) |
  581. HAL_REO_REMAP_IX0(REO_REMAP_FW, 7);
  582. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL, NULL, NULL);
  583. return 0;
  584. }
  585. static QDF_STATUS dp_ipa_get_shared_mem_info(qdf_device_t osdev,
  586. qdf_shared_mem_t *shared_mem,
  587. void *cpu_addr,
  588. qdf_dma_addr_t dma_addr,
  589. uint32_t size)
  590. {
  591. qdf_dma_addr_t paddr;
  592. int ret;
  593. shared_mem->vaddr = cpu_addr;
  594. qdf_mem_set_dma_size(osdev, &shared_mem->mem_info, size);
  595. *qdf_mem_get_dma_addr_ptr(osdev, &shared_mem->mem_info) = dma_addr;
  596. paddr = qdf_mem_paddr_from_dmaaddr(osdev, dma_addr);
  597. qdf_mem_set_dma_pa(osdev, &shared_mem->mem_info, paddr);
  598. ret = qdf_mem_dma_get_sgtable(osdev->dev, &shared_mem->sgtable,
  599. shared_mem->vaddr, dma_addr, size);
  600. if (ret) {
  601. dp_err("Unable to get DMA sgtable");
  602. return QDF_STATUS_E_NOMEM;
  603. }
  604. qdf_dma_get_sgtable_dma_addr(&shared_mem->sgtable);
  605. return QDF_STATUS_SUCCESS;
  606. }
  607. QDF_STATUS dp_ipa_get_resource(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  608. {
  609. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  610. struct dp_pdev *pdev =
  611. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  612. struct dp_ipa_resources *ipa_res;
  613. if (!pdev) {
  614. dp_err("Invalid instance");
  615. return QDF_STATUS_E_FAILURE;
  616. }
  617. ipa_res = &pdev->ipa_resource;
  618. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  619. return QDF_STATUS_SUCCESS;
  620. ipa_res->tx_num_alloc_buffer =
  621. (uint32_t)soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt;
  622. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->tx_ring,
  623. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr,
  624. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr,
  625. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size);
  626. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->tx_comp_ring,
  627. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr,
  628. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr,
  629. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size);
  630. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->rx_rdy_ring,
  631. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr,
  632. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr,
  633. soc->ipa_uc_rx_rsc.ipa_reo_ring_size);
  634. dp_ipa_get_shared_mem_info(
  635. soc->osdev, &ipa_res->rx_refill_ring,
  636. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr,
  637. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr,
  638. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size);
  639. if (!qdf_mem_get_dma_addr(soc->osdev, &ipa_res->tx_ring.mem_info) ||
  640. !qdf_mem_get_dma_addr(soc->osdev,
  641. &ipa_res->tx_comp_ring.mem_info) ||
  642. !qdf_mem_get_dma_addr(soc->osdev, &ipa_res->rx_rdy_ring.mem_info) ||
  643. !qdf_mem_get_dma_addr(soc->osdev,
  644. &ipa_res->rx_refill_ring.mem_info))
  645. return QDF_STATUS_E_FAILURE;
  646. return QDF_STATUS_SUCCESS;
  647. }
  648. static void dp_ipa_set_tx_doorbell_paddr(struct dp_soc *soc,
  649. struct dp_ipa_resources *ipa_res)
  650. {
  651. struct hal_srng *wbm_srng = (struct hal_srng *)
  652. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  653. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  654. ipa_res->tx_comp_doorbell_paddr);
  655. dp_info("paddr %pK vaddr %pK",
  656. (void *)ipa_res->tx_comp_doorbell_paddr,
  657. (void *)ipa_res->tx_comp_doorbell_vaddr);
  658. }
  659. #ifdef IPA_SET_RESET_TX_DB_PA
  660. #define DP_IPA_SET_TX_DB_PADDR(soc, ipa_res)
  661. #else
  662. #define DP_IPA_SET_TX_DB_PADDR(soc, ipa_res) \
  663. dp_ipa_set_tx_doorbell_paddr(soc, ipa_res)
  664. #endif
  665. QDF_STATUS dp_ipa_set_doorbell_paddr(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  666. {
  667. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  668. struct dp_pdev *pdev =
  669. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  670. struct dp_ipa_resources *ipa_res;
  671. struct hal_srng *reo_srng = (struct hal_srng *)
  672. soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  673. uint32_t tx_comp_doorbell_dmaaddr;
  674. uint32_t rx_ready_doorbell_dmaaddr;
  675. int ret = 0;
  676. if (!pdev) {
  677. dp_err("Invalid instance");
  678. return QDF_STATUS_E_FAILURE;
  679. }
  680. ipa_res = &pdev->ipa_resource;
  681. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  682. return QDF_STATUS_SUCCESS;
  683. if (ipa_res->is_db_ddr_mapped)
  684. ipa_res->tx_comp_doorbell_vaddr =
  685. phys_to_virt(ipa_res->tx_comp_doorbell_paddr);
  686. else
  687. ipa_res->tx_comp_doorbell_vaddr =
  688. ioremap(ipa_res->tx_comp_doorbell_paddr, 4);
  689. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  690. ret = pld_smmu_map(soc->osdev->dev,
  691. ipa_res->tx_comp_doorbell_paddr,
  692. &tx_comp_doorbell_dmaaddr,
  693. sizeof(uint32_t));
  694. ipa_res->tx_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  695. qdf_assert_always(!ret);
  696. ret = pld_smmu_map(soc->osdev->dev,
  697. ipa_res->rx_ready_doorbell_paddr,
  698. &rx_ready_doorbell_dmaaddr,
  699. sizeof(uint32_t));
  700. ipa_res->rx_ready_doorbell_paddr = rx_ready_doorbell_dmaaddr;
  701. qdf_assert_always(!ret);
  702. }
  703. DP_IPA_SET_TX_DB_PADDR(soc, ipa_res);
  704. /*
  705. * For RX, REO module on Napier/Hastings does reordering on incoming
  706. * Ethernet packets and writes one or more descriptors to REO2IPA Rx
  707. * ring.It then updates the ring’s Write/Head ptr and rings a doorbell
  708. * to IPA.
  709. * Set the doorbell addr for the REO ring.
  710. */
  711. hal_srng_dst_set_hp_paddr_confirm(reo_srng,
  712. ipa_res->rx_ready_doorbell_paddr);
  713. return QDF_STATUS_SUCCESS;
  714. }
  715. QDF_STATUS dp_ipa_op_response(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  716. uint8_t *op_msg)
  717. {
  718. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  719. struct dp_pdev *pdev =
  720. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  721. if (!pdev) {
  722. dp_err("Invalid instance");
  723. return QDF_STATUS_E_FAILURE;
  724. }
  725. if (!wlan_cfg_is_ipa_enabled(pdev->soc->wlan_cfg_ctx))
  726. return QDF_STATUS_SUCCESS;
  727. if (pdev->ipa_uc_op_cb) {
  728. pdev->ipa_uc_op_cb(op_msg, pdev->usr_ctxt);
  729. } else {
  730. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  731. "%s: IPA callback function is not registered", __func__);
  732. qdf_mem_free(op_msg);
  733. return QDF_STATUS_E_FAILURE;
  734. }
  735. return QDF_STATUS_SUCCESS;
  736. }
  737. QDF_STATUS dp_ipa_register_op_cb(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  738. ipa_uc_op_cb_type op_cb,
  739. void *usr_ctxt)
  740. {
  741. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  742. struct dp_pdev *pdev =
  743. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  744. if (!pdev) {
  745. dp_err("Invalid instance");
  746. return QDF_STATUS_E_FAILURE;
  747. }
  748. if (!wlan_cfg_is_ipa_enabled(pdev->soc->wlan_cfg_ctx))
  749. return QDF_STATUS_SUCCESS;
  750. pdev->ipa_uc_op_cb = op_cb;
  751. pdev->usr_ctxt = usr_ctxt;
  752. return QDF_STATUS_SUCCESS;
  753. }
  754. void dp_ipa_deregister_op_cb(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  755. {
  756. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  757. struct dp_pdev *pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  758. if (!pdev) {
  759. dp_err("Invalid instance");
  760. return;
  761. }
  762. dp_debug("Deregister OP handler callback");
  763. pdev->ipa_uc_op_cb = NULL;
  764. pdev->usr_ctxt = NULL;
  765. }
  766. QDF_STATUS dp_ipa_get_stat(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  767. {
  768. /* TBD */
  769. return QDF_STATUS_SUCCESS;
  770. }
  771. /**
  772. * dp_tx_send_ipa_data_frame() - send IPA data frame
  773. * @soc_hdl: datapath soc handle
  774. * @vdev_id: id of the virtual device
  775. * @skb: skb to transmit
  776. *
  777. * Return: skb/ NULL is for success
  778. */
  779. qdf_nbuf_t dp_tx_send_ipa_data_frame(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  780. qdf_nbuf_t skb)
  781. {
  782. qdf_nbuf_t ret;
  783. /* Terminate the (single-element) list of tx frames */
  784. qdf_nbuf_set_next(skb, NULL);
  785. ret = dp_tx_send(soc_hdl, vdev_id, skb);
  786. if (ret) {
  787. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  788. "%s: Failed to tx", __func__);
  789. return ret;
  790. }
  791. return NULL;
  792. }
  793. QDF_STATUS dp_ipa_enable_autonomy(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  794. {
  795. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  796. struct dp_pdev *pdev =
  797. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  798. uint32_t ix0;
  799. uint32_t ix2;
  800. if (!pdev) {
  801. dp_err("Invalid instance");
  802. return QDF_STATUS_E_FAILURE;
  803. }
  804. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  805. return QDF_STATUS_SUCCESS;
  806. if (!hif_is_target_ready(HIF_GET_SOFTC(soc->hif_handle)))
  807. return QDF_STATUS_E_AGAIN;
  808. /* Call HAL API to remap REO rings to REO2IPA ring */
  809. ix0 = HAL_REO_REMAP_IX0(REO_REMAP_TCL, 0) |
  810. HAL_REO_REMAP_IX0(REO_REMAP_SW4, 1) |
  811. HAL_REO_REMAP_IX0(REO_REMAP_SW1, 2) |
  812. HAL_REO_REMAP_IX0(REO_REMAP_SW4, 3) |
  813. HAL_REO_REMAP_IX0(REO_REMAP_SW4, 4) |
  814. HAL_REO_REMAP_IX0(REO_REMAP_RELEASE, 5) |
  815. HAL_REO_REMAP_IX0(REO_REMAP_FW, 6) |
  816. HAL_REO_REMAP_IX0(REO_REMAP_FW, 7);
  817. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  818. ix2 = HAL_REO_REMAP_IX2(REO_REMAP_SW4, 16) |
  819. HAL_REO_REMAP_IX2(REO_REMAP_SW4, 17) |
  820. HAL_REO_REMAP_IX2(REO_REMAP_SW4, 18) |
  821. HAL_REO_REMAP_IX2(REO_REMAP_SW4, 19) |
  822. HAL_REO_REMAP_IX2(REO_REMAP_SW4, 20) |
  823. HAL_REO_REMAP_IX2(REO_REMAP_SW4, 21) |
  824. HAL_REO_REMAP_IX2(REO_REMAP_SW4, 22) |
  825. HAL_REO_REMAP_IX2(REO_REMAP_SW4, 23);
  826. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  827. &ix2, &ix2);
  828. dp_ipa_reo_remap_history_add(ix0, ix2, ix2);
  829. } else {
  830. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  831. NULL, NULL);
  832. dp_ipa_reo_remap_history_add(ix0, 0, 0);
  833. }
  834. return QDF_STATUS_SUCCESS;
  835. }
  836. QDF_STATUS dp_ipa_disable_autonomy(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  837. {
  838. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  839. struct dp_pdev *pdev =
  840. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  841. uint32_t ix0;
  842. uint32_t ix2;
  843. uint32_t ix3;
  844. if (!pdev) {
  845. dp_err("Invalid instance");
  846. return QDF_STATUS_E_FAILURE;
  847. }
  848. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  849. return QDF_STATUS_SUCCESS;
  850. if (!hif_is_target_ready(HIF_GET_SOFTC(soc->hif_handle)))
  851. return QDF_STATUS_E_AGAIN;
  852. /* Call HAL API to remap REO rings to REO2IPA ring */
  853. ix0 = HAL_REO_REMAP_IX0(REO_REMAP_TCL, 0) |
  854. HAL_REO_REMAP_IX0(REO_REMAP_SW1, 1) |
  855. HAL_REO_REMAP_IX0(REO_REMAP_SW2, 2) |
  856. HAL_REO_REMAP_IX0(REO_REMAP_SW3, 3) |
  857. HAL_REO_REMAP_IX0(REO_REMAP_SW2, 4) |
  858. HAL_REO_REMAP_IX0(REO_REMAP_RELEASE, 5) |
  859. HAL_REO_REMAP_IX0(REO_REMAP_FW, 6) |
  860. HAL_REO_REMAP_IX0(REO_REMAP_FW, 7);
  861. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  862. dp_reo_remap_config(soc, &ix2, &ix3);
  863. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  864. &ix2, &ix3);
  865. dp_ipa_reo_remap_history_add(ix0, ix2, ix3);
  866. } else {
  867. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  868. NULL, NULL);
  869. dp_ipa_reo_remap_history_add(ix0, 0, 0);
  870. }
  871. return QDF_STATUS_SUCCESS;
  872. }
  873. /* This should be configurable per H/W configuration enable status */
  874. #define L3_HEADER_PADDING 2
  875. #ifdef CONFIG_IPA_WDI_UNIFIED_API
  876. #ifndef QCA_LL_TX_FLOW_CONTROL_V2
  877. static inline void dp_setup_mcc_sys_pipes(
  878. qdf_ipa_sys_connect_params_t *sys_in,
  879. qdf_ipa_wdi_conn_in_params_t *pipe_in)
  880. {
  881. /* Setup MCC sys pipe */
  882. QDF_IPA_WDI_CONN_IN_PARAMS_NUM_SYS_PIPE_NEEDED(pipe_in) =
  883. DP_IPA_MAX_IFACE;
  884. for (int i = 0; i < DP_IPA_MAX_IFACE; i++)
  885. memcpy(&QDF_IPA_WDI_CONN_IN_PARAMS_SYS_IN(pipe_in)[i],
  886. &sys_in[i], sizeof(qdf_ipa_sys_connect_params_t));
  887. }
  888. #else
  889. static inline void dp_setup_mcc_sys_pipes(
  890. qdf_ipa_sys_connect_params_t *sys_in,
  891. qdf_ipa_wdi_conn_in_params_t *pipe_in)
  892. {
  893. QDF_IPA_WDI_CONN_IN_PARAMS_NUM_SYS_PIPE_NEEDED(pipe_in) = 0;
  894. }
  895. #endif
  896. static void dp_ipa_wdi_tx_params(struct dp_soc *soc,
  897. struct dp_ipa_resources *ipa_res,
  898. qdf_ipa_wdi_pipe_setup_info_t *tx,
  899. bool over_gsi)
  900. {
  901. struct tcl_data_cmd *tcl_desc_ptr;
  902. uint8_t *desc_addr;
  903. uint32_t desc_size;
  904. if (over_gsi)
  905. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN2_CONS;
  906. else
  907. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN1_CONS;
  908. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  909. qdf_mem_get_dma_addr(soc->osdev,
  910. &ipa_res->tx_comp_ring.mem_info);
  911. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  912. qdf_mem_get_dma_size(soc->osdev,
  913. &ipa_res->tx_comp_ring.mem_info);
  914. /* WBM Tail Pointer Address */
  915. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  916. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  917. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(tx) = true;
  918. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  919. qdf_mem_get_dma_addr(soc->osdev,
  920. &ipa_res->tx_ring.mem_info);
  921. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) =
  922. qdf_mem_get_dma_size(soc->osdev,
  923. &ipa_res->tx_ring.mem_info);
  924. /* TCL Head Pointer Address */
  925. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  926. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  927. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(tx) = true;
  928. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  929. ipa_res->tx_num_alloc_buffer;
  930. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  931. /* Preprogram TCL descriptor */
  932. desc_addr =
  933. (uint8_t *)QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx);
  934. desc_size = sizeof(struct tcl_data_cmd);
  935. HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, desc_size);
  936. tcl_desc_ptr = (struct tcl_data_cmd *)
  937. (QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx) + 1);
  938. tcl_desc_ptr->buf_addr_info.return_buffer_manager =
  939. HAL_RX_BUF_RBM_SW2_BM;
  940. tcl_desc_ptr->addrx_en = 1; /* Address X search enable in ASE */
  941. tcl_desc_ptr->encap_type = HAL_TX_ENCAP_TYPE_ETHERNET;
  942. tcl_desc_ptr->packet_offset = 2; /* padding for alignment */
  943. }
  944. static void dp_ipa_wdi_rx_params(struct dp_soc *soc,
  945. struct dp_ipa_resources *ipa_res,
  946. qdf_ipa_wdi_pipe_setup_info_t *rx,
  947. bool over_gsi)
  948. {
  949. if (over_gsi)
  950. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  951. IPA_CLIENT_WLAN2_PROD;
  952. else
  953. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  954. IPA_CLIENT_WLAN1_PROD;
  955. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  956. qdf_mem_get_dma_addr(soc->osdev,
  957. &ipa_res->rx_rdy_ring.mem_info);
  958. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  959. qdf_mem_get_dma_size(soc->osdev,
  960. &ipa_res->rx_rdy_ring.mem_info);
  961. /* REO Tail Pointer Address */
  962. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  963. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  964. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(rx) = true;
  965. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  966. qdf_mem_get_dma_addr(soc->osdev,
  967. &ipa_res->rx_refill_ring.mem_info);
  968. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  969. qdf_mem_get_dma_size(soc->osdev,
  970. &ipa_res->rx_refill_ring.mem_info);
  971. /* FW Head Pointer Address */
  972. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  973. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  974. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(rx) = false;
  975. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) =
  976. RX_PKT_TLVS_LEN + L3_HEADER_PADDING;
  977. }
  978. static void
  979. dp_ipa_wdi_tx_smmu_params(struct dp_soc *soc,
  980. struct dp_ipa_resources *ipa_res,
  981. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu,
  982. bool over_gsi)
  983. {
  984. struct tcl_data_cmd *tcl_desc_ptr;
  985. uint8_t *desc_addr;
  986. uint32_t desc_size;
  987. if (over_gsi)
  988. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  989. IPA_CLIENT_WLAN2_CONS;
  990. else
  991. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  992. IPA_CLIENT_WLAN1_CONS;
  993. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(tx_smmu),
  994. &ipa_res->tx_comp_ring.sgtable,
  995. sizeof(sgtable_t));
  996. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(tx_smmu) =
  997. qdf_mem_get_dma_size(soc->osdev,
  998. &ipa_res->tx_comp_ring.mem_info);
  999. /* WBM Tail Pointer Address */
  1000. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(tx_smmu) =
  1001. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  1002. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(tx_smmu) = true;
  1003. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(tx_smmu),
  1004. &ipa_res->tx_ring.sgtable,
  1005. sizeof(sgtable_t));
  1006. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(tx_smmu) =
  1007. qdf_mem_get_dma_size(soc->osdev,
  1008. &ipa_res->tx_ring.mem_info);
  1009. /* TCL Head Pointer Address */
  1010. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(tx_smmu) =
  1011. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  1012. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(tx_smmu) = true;
  1013. QDF_IPA_WDI_SETUP_INFO_SMMU_NUM_PKT_BUFFERS(tx_smmu) =
  1014. ipa_res->tx_num_alloc_buffer;
  1015. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(tx_smmu) = 0;
  1016. /* Preprogram TCL descriptor */
  1017. desc_addr = (uint8_t *)QDF_IPA_WDI_SETUP_INFO_SMMU_DESC_FORMAT_TEMPLATE(
  1018. tx_smmu);
  1019. desc_size = sizeof(struct tcl_data_cmd);
  1020. HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, desc_size);
  1021. tcl_desc_ptr = (struct tcl_data_cmd *)
  1022. (QDF_IPA_WDI_SETUP_INFO_SMMU_DESC_FORMAT_TEMPLATE(tx_smmu) + 1);
  1023. tcl_desc_ptr->buf_addr_info.return_buffer_manager =
  1024. HAL_RX_BUF_RBM_SW2_BM;
  1025. tcl_desc_ptr->addrx_en = 1; /* Address X search enable in ASE */
  1026. tcl_desc_ptr->encap_type = HAL_TX_ENCAP_TYPE_ETHERNET;
  1027. tcl_desc_ptr->packet_offset = 2; /* padding for alignment */
  1028. }
  1029. static void
  1030. dp_ipa_wdi_rx_smmu_params(struct dp_soc *soc,
  1031. struct dp_ipa_resources *ipa_res,
  1032. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu,
  1033. bool over_gsi)
  1034. {
  1035. if (over_gsi)
  1036. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  1037. IPA_CLIENT_WLAN2_PROD;
  1038. else
  1039. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  1040. IPA_CLIENT_WLAN1_PROD;
  1041. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(rx_smmu),
  1042. &ipa_res->rx_rdy_ring.sgtable,
  1043. sizeof(sgtable_t));
  1044. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(rx_smmu) =
  1045. qdf_mem_get_dma_size(soc->osdev,
  1046. &ipa_res->rx_rdy_ring.mem_info);
  1047. /* REO Tail Pointer Address */
  1048. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(rx_smmu) =
  1049. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  1050. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(rx_smmu) = true;
  1051. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(rx_smmu),
  1052. &ipa_res->rx_refill_ring.sgtable,
  1053. sizeof(sgtable_t));
  1054. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(rx_smmu) =
  1055. qdf_mem_get_dma_size(soc->osdev,
  1056. &ipa_res->rx_refill_ring.mem_info);
  1057. /* FW Head Pointer Address */
  1058. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(rx_smmu) =
  1059. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  1060. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(rx_smmu) = false;
  1061. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(rx_smmu) =
  1062. RX_PKT_TLVS_LEN + L3_HEADER_PADDING;
  1063. }
  1064. QDF_STATUS dp_ipa_setup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1065. void *ipa_i2w_cb, void *ipa_w2i_cb,
  1066. void *ipa_wdi_meter_notifier_cb,
  1067. uint32_t ipa_desc_size, void *ipa_priv,
  1068. bool is_rm_enabled, uint32_t *tx_pipe_handle,
  1069. uint32_t *rx_pipe_handle, bool is_smmu_enabled,
  1070. qdf_ipa_sys_connect_params_t *sys_in, bool over_gsi)
  1071. {
  1072. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1073. struct dp_pdev *pdev =
  1074. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1075. struct dp_ipa_resources *ipa_res;
  1076. qdf_ipa_ep_cfg_t *tx_cfg;
  1077. qdf_ipa_ep_cfg_t *rx_cfg;
  1078. qdf_ipa_wdi_pipe_setup_info_t *tx = NULL;
  1079. qdf_ipa_wdi_pipe_setup_info_t *rx = NULL;
  1080. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu;
  1081. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu = NULL;
  1082. qdf_ipa_wdi_conn_in_params_t *pipe_in = NULL;
  1083. qdf_ipa_wdi_conn_out_params_t pipe_out;
  1084. int ret;
  1085. if (!pdev) {
  1086. dp_err("Invalid instance");
  1087. return QDF_STATUS_E_FAILURE;
  1088. }
  1089. ipa_res = &pdev->ipa_resource;
  1090. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1091. return QDF_STATUS_SUCCESS;
  1092. pipe_in = qdf_mem_malloc(sizeof(*pipe_in));
  1093. if (!pipe_in)
  1094. return QDF_STATUS_E_NOMEM;
  1095. qdf_mem_zero(&pipe_out, sizeof(pipe_out));
  1096. if (is_smmu_enabled)
  1097. QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in) = true;
  1098. else
  1099. QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in) = false;
  1100. dp_setup_mcc_sys_pipes(sys_in, pipe_in);
  1101. /* TX PIPE */
  1102. if (QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in)) {
  1103. tx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_SMMU(pipe_in);
  1104. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx_smmu);
  1105. } else {
  1106. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX(pipe_in);
  1107. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_EP_CFG(tx);
  1108. }
  1109. QDF_IPA_EP_CFG_NAT_EN(tx_cfg) = IPA_BYPASS_NAT;
  1110. QDF_IPA_EP_CFG_HDR_LEN(tx_cfg) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  1111. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(tx_cfg) = 0;
  1112. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(tx_cfg) = 0;
  1113. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(tx_cfg) = 0;
  1114. QDF_IPA_EP_CFG_MODE(tx_cfg) = IPA_BASIC;
  1115. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(tx_cfg) = true;
  1116. /**
  1117. * Transfer Ring: WBM Ring
  1118. * Transfer Ring Doorbell PA: WBM Tail Pointer Address
  1119. * Event Ring: TCL ring
  1120. * Event Ring Doorbell PA: TCL Head Pointer Address
  1121. */
  1122. if (is_smmu_enabled)
  1123. dp_ipa_wdi_tx_smmu_params(soc, ipa_res, tx_smmu, over_gsi);
  1124. else
  1125. dp_ipa_wdi_tx_params(soc, ipa_res, tx, over_gsi);
  1126. /* RX PIPE */
  1127. if (QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in)) {
  1128. rx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_SMMU(pipe_in);
  1129. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx_smmu);
  1130. } else {
  1131. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX(pipe_in);
  1132. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_EP_CFG(rx);
  1133. }
  1134. QDF_IPA_EP_CFG_NAT_EN(rx_cfg) = IPA_BYPASS_NAT;
  1135. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN;
  1136. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(rx_cfg) = 1;
  1137. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(rx_cfg) = 0;
  1138. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(rx_cfg) = 0;
  1139. QDF_IPA_EP_CFG_HDR_OFST_METADATA_VALID(rx_cfg) = 0;
  1140. QDF_IPA_EP_CFG_HDR_METADATA_REG_VALID(rx_cfg) = 1;
  1141. QDF_IPA_EP_CFG_MODE(rx_cfg) = IPA_BASIC;
  1142. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(rx_cfg) = true;
  1143. /**
  1144. * Transfer Ring: REO Ring
  1145. * Transfer Ring Doorbell PA: REO Tail Pointer Address
  1146. * Event Ring: FW ring
  1147. * Event Ring Doorbell PA: FW Head Pointer Address
  1148. */
  1149. if (is_smmu_enabled)
  1150. dp_ipa_wdi_rx_smmu_params(soc, ipa_res, rx_smmu, over_gsi);
  1151. else
  1152. dp_ipa_wdi_rx_params(soc, ipa_res, rx, over_gsi);
  1153. QDF_IPA_WDI_CONN_IN_PARAMS_NOTIFY(pipe_in) = ipa_w2i_cb;
  1154. QDF_IPA_WDI_CONN_IN_PARAMS_PRIV(pipe_in) = ipa_priv;
  1155. /* Connect WDI IPA PIPEs */
  1156. ret = qdf_ipa_wdi_conn_pipes(pipe_in, &pipe_out);
  1157. if (ret) {
  1158. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1159. "%s: ipa_wdi_conn_pipes: IPA pipe setup failed: ret=%d",
  1160. __func__, ret);
  1161. qdf_mem_free(pipe_in);
  1162. return QDF_STATUS_E_FAILURE;
  1163. }
  1164. /* IPA uC Doorbell registers */
  1165. dp_info("Tx DB PA=0x%x, Rx DB PA=0x%x",
  1166. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out),
  1167. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out));
  1168. ipa_res->tx_comp_doorbell_paddr =
  1169. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out);
  1170. ipa_res->rx_ready_doorbell_paddr =
  1171. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out);
  1172. ipa_res->is_db_ddr_mapped =
  1173. QDF_IPA_WDI_CONN_OUT_PARAMS_IS_DB_DDR_MAPPED(&pipe_out);
  1174. soc->ipa_first_tx_db_access = true;
  1175. qdf_mem_free(pipe_in);
  1176. return QDF_STATUS_SUCCESS;
  1177. }
  1178. /**
  1179. * dp_ipa_setup_iface() - Setup IPA header and register interface
  1180. * @ifname: Interface name
  1181. * @mac_addr: Interface MAC address
  1182. * @prod_client: IPA prod client type
  1183. * @cons_client: IPA cons client type
  1184. * @session_id: Session ID
  1185. * @is_ipv6_enabled: Is IPV6 enabled or not
  1186. *
  1187. * Return: QDF_STATUS
  1188. */
  1189. QDF_STATUS dp_ipa_setup_iface(char *ifname, uint8_t *mac_addr,
  1190. qdf_ipa_client_type_t prod_client,
  1191. qdf_ipa_client_type_t cons_client,
  1192. uint8_t session_id, bool is_ipv6_enabled)
  1193. {
  1194. qdf_ipa_wdi_reg_intf_in_params_t in;
  1195. qdf_ipa_wdi_hdr_info_t hdr_info;
  1196. struct dp_ipa_uc_tx_hdr uc_tx_hdr;
  1197. struct dp_ipa_uc_tx_hdr uc_tx_hdr_v6;
  1198. int ret = -EINVAL;
  1199. dp_debug("Add Partial hdr: %s, "QDF_MAC_ADDR_FMT, ifname,
  1200. QDF_MAC_ADDR_REF(mac_addr));
  1201. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  1202. qdf_ether_addr_copy(uc_tx_hdr.eth.h_source, mac_addr);
  1203. /* IPV4 header */
  1204. uc_tx_hdr.eth.h_proto = qdf_htons(ETH_P_IP);
  1205. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr;
  1206. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  1207. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(&hdr_info) = IPA_HDR_L2_ETHERNET_II;
  1208. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  1209. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  1210. QDF_IPA_WDI_REG_INTF_IN_PARAMS_NETDEV_NAME(&in) = ifname;
  1211. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v4]),
  1212. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  1213. QDF_IPA_WDI_REG_INTF_IN_PARAMS_ALT_DST_PIPE(&in) = cons_client;
  1214. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_META_DATA_VALID(&in) = 1;
  1215. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(&in) =
  1216. htonl(session_id << 16);
  1217. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(&in) = htonl(0x00FF0000);
  1218. /* IPV6 header */
  1219. if (is_ipv6_enabled) {
  1220. qdf_mem_copy(&uc_tx_hdr_v6, &uc_tx_hdr,
  1221. DP_IPA_UC_WLAN_TX_HDR_LEN);
  1222. uc_tx_hdr_v6.eth.h_proto = qdf_htons(ETH_P_IPV6);
  1223. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr_v6;
  1224. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v6]),
  1225. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  1226. }
  1227. dp_debug("registering for session_id: %u", session_id);
  1228. ret = qdf_ipa_wdi_reg_intf(&in);
  1229. if (ret) {
  1230. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1231. "%s: ipa_wdi_reg_intf: register IPA interface falied: ret=%d",
  1232. __func__, ret);
  1233. return QDF_STATUS_E_FAILURE;
  1234. }
  1235. return QDF_STATUS_SUCCESS;
  1236. }
  1237. #else /* CONFIG_IPA_WDI_UNIFIED_API */
  1238. QDF_STATUS dp_ipa_setup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1239. void *ipa_i2w_cb, void *ipa_w2i_cb,
  1240. void *ipa_wdi_meter_notifier_cb,
  1241. uint32_t ipa_desc_size, void *ipa_priv,
  1242. bool is_rm_enabled, uint32_t *tx_pipe_handle,
  1243. uint32_t *rx_pipe_handle)
  1244. {
  1245. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1246. struct dp_pdev *pdev =
  1247. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1248. struct dp_ipa_resources *ipa_res;
  1249. qdf_ipa_wdi_pipe_setup_info_t *tx;
  1250. qdf_ipa_wdi_pipe_setup_info_t *rx;
  1251. qdf_ipa_wdi_conn_in_params_t pipe_in;
  1252. qdf_ipa_wdi_conn_out_params_t pipe_out;
  1253. struct tcl_data_cmd *tcl_desc_ptr;
  1254. uint8_t *desc_addr;
  1255. uint32_t desc_size;
  1256. int ret;
  1257. if (!pdev) {
  1258. dp_err("Invalid instance");
  1259. return QDF_STATUS_E_FAILURE;
  1260. }
  1261. ipa_res = &pdev->ipa_resource;
  1262. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1263. return QDF_STATUS_SUCCESS;
  1264. qdf_mem_zero(&tx, sizeof(qdf_ipa_wdi_pipe_setup_info_t));
  1265. qdf_mem_zero(&rx, sizeof(qdf_ipa_wdi_pipe_setup_info_t));
  1266. qdf_mem_zero(&pipe_in, sizeof(pipe_in));
  1267. qdf_mem_zero(&pipe_out, sizeof(pipe_out));
  1268. /* TX PIPE */
  1269. /**
  1270. * Transfer Ring: WBM Ring
  1271. * Transfer Ring Doorbell PA: WBM Tail Pointer Address
  1272. * Event Ring: TCL ring
  1273. * Event Ring Doorbell PA: TCL Head Pointer Address
  1274. */
  1275. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX(&pipe_in);
  1276. QDF_IPA_WDI_SETUP_INFO_NAT_EN(tx) = IPA_BYPASS_NAT;
  1277. QDF_IPA_WDI_SETUP_INFO_HDR_LEN(tx) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  1278. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE_VALID(tx) = 0;
  1279. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE(tx) = 0;
  1280. QDF_IPA_WDI_SETUP_INFO_HDR_ADDITIONAL_CONST_LEN(tx) = 0;
  1281. QDF_IPA_WDI_SETUP_INFO_MODE(tx) = IPA_BASIC;
  1282. QDF_IPA_WDI_SETUP_INFO_HDR_LITTLE_ENDIAN(tx) = true;
  1283. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN1_CONS;
  1284. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  1285. ipa_res->tx_comp_ring_base_paddr;
  1286. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  1287. ipa_res->tx_comp_ring_size;
  1288. /* WBM Tail Pointer Address */
  1289. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  1290. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  1291. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  1292. ipa_res->tx_ring_base_paddr;
  1293. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) = ipa_res->tx_ring_size;
  1294. /* TCL Head Pointer Address */
  1295. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  1296. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  1297. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  1298. ipa_res->tx_num_alloc_buffer;
  1299. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  1300. /* Preprogram TCL descriptor */
  1301. desc_addr =
  1302. (uint8_t *)QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx);
  1303. desc_size = sizeof(struct tcl_data_cmd);
  1304. HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, desc_size);
  1305. tcl_desc_ptr = (struct tcl_data_cmd *)
  1306. (QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx) + 1);
  1307. tcl_desc_ptr->buf_addr_info.return_buffer_manager =
  1308. HAL_RX_BUF_RBM_SW2_BM;
  1309. tcl_desc_ptr->addrx_en = 1; /* Address X search enable in ASE */
  1310. tcl_desc_ptr->encap_type = HAL_TX_ENCAP_TYPE_ETHERNET;
  1311. tcl_desc_ptr->packet_offset = 2; /* padding for alignment */
  1312. /* RX PIPE */
  1313. /**
  1314. * Transfer Ring: REO Ring
  1315. * Transfer Ring Doorbell PA: REO Tail Pointer Address
  1316. * Event Ring: FW ring
  1317. * Event Ring Doorbell PA: FW Head Pointer Address
  1318. */
  1319. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX(&pipe_in);
  1320. QDF_IPA_WDI_SETUP_INFO_NAT_EN(rx) = IPA_BYPASS_NAT;
  1321. QDF_IPA_WDI_SETUP_INFO_HDR_LEN(rx) = DP_IPA_UC_WLAN_RX_HDR_LEN;
  1322. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE_VALID(rx) = 0;
  1323. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE(rx) = 0;
  1324. QDF_IPA_WDI_SETUP_INFO_HDR_ADDITIONAL_CONST_LEN(rx) = 0;
  1325. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_METADATA_VALID(rx) = 0;
  1326. QDF_IPA_WDI_SETUP_INFO_HDR_METADATA_REG_VALID(rx) = 1;
  1327. QDF_IPA_WDI_SETUP_INFO_MODE(rx) = IPA_BASIC;
  1328. QDF_IPA_WDI_SETUP_INFO_HDR_LITTLE_ENDIAN(rx) = true;
  1329. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) = IPA_CLIENT_WLAN1_PROD;
  1330. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  1331. ipa_res->rx_rdy_ring_base_paddr;
  1332. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  1333. ipa_res->rx_rdy_ring_size;
  1334. /* REO Tail Pointer Address */
  1335. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  1336. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  1337. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  1338. ipa_res->rx_refill_ring_base_paddr;
  1339. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  1340. ipa_res->rx_refill_ring_size;
  1341. /* FW Head Pointer Address */
  1342. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  1343. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  1344. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) = RX_PKT_TLVS_LEN +
  1345. L3_HEADER_PADDING;
  1346. QDF_IPA_WDI_CONN_IN_PARAMS_NOTIFY(&pipe_in) = ipa_w2i_cb;
  1347. QDF_IPA_WDI_CONN_IN_PARAMS_PRIV(&pipe_in) = ipa_priv;
  1348. /* Connect WDI IPA PIPE */
  1349. ret = qdf_ipa_wdi_conn_pipes(&pipe_in, &pipe_out);
  1350. if (ret) {
  1351. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1352. "%s: ipa_wdi_conn_pipes: IPA pipe setup failed: ret=%d",
  1353. __func__, ret);
  1354. return QDF_STATUS_E_FAILURE;
  1355. }
  1356. /* IPA uC Doorbell registers */
  1357. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  1358. "%s: Tx DB PA=0x%x, Rx DB PA=0x%x",
  1359. __func__,
  1360. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out),
  1361. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out));
  1362. ipa_res->tx_comp_doorbell_paddr =
  1363. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out);
  1364. ipa_res->tx_comp_doorbell_vaddr =
  1365. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_VA(&pipe_out);
  1366. ipa_res->rx_ready_doorbell_paddr =
  1367. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out);
  1368. soc->ipa_first_tx_db_access = true;
  1369. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  1370. "%s: Tx: %s=%pK, %s=%d, %s=%pK, %s=%pK, %s=%d, %s=%pK, %s=%d, %s=%pK",
  1371. __func__,
  1372. "transfer_ring_base_pa",
  1373. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx),
  1374. "transfer_ring_size",
  1375. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx),
  1376. "transfer_ring_doorbell_pa",
  1377. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx),
  1378. "event_ring_base_pa",
  1379. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx),
  1380. "event_ring_size",
  1381. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx),
  1382. "event_ring_doorbell_pa",
  1383. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx),
  1384. "num_pkt_buffers",
  1385. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx),
  1386. "tx_comp_doorbell_paddr",
  1387. (void *)ipa_res->tx_comp_doorbell_paddr);
  1388. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  1389. "%s: Rx: %s=%pK, %s=%d, %s=%pK, %s=%pK, %s=%d, %s=%pK, %s=%d, %s=%pK",
  1390. __func__,
  1391. "transfer_ring_base_pa",
  1392. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx),
  1393. "transfer_ring_size",
  1394. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx),
  1395. "transfer_ring_doorbell_pa",
  1396. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx),
  1397. "event_ring_base_pa",
  1398. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx),
  1399. "event_ring_size",
  1400. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx),
  1401. "event_ring_doorbell_pa",
  1402. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx),
  1403. "num_pkt_buffers",
  1404. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(rx),
  1405. "tx_comp_doorbell_paddr",
  1406. (void *)ipa_res->rx_ready_doorbell_paddr);
  1407. return QDF_STATUS_SUCCESS;
  1408. }
  1409. /**
  1410. * dp_ipa_setup_iface() - Setup IPA header and register interface
  1411. * @ifname: Interface name
  1412. * @mac_addr: Interface MAC address
  1413. * @prod_client: IPA prod client type
  1414. * @cons_client: IPA cons client type
  1415. * @session_id: Session ID
  1416. * @is_ipv6_enabled: Is IPV6 enabled or not
  1417. *
  1418. * Return: QDF_STATUS
  1419. */
  1420. QDF_STATUS dp_ipa_setup_iface(char *ifname, uint8_t *mac_addr,
  1421. qdf_ipa_client_type_t prod_client,
  1422. qdf_ipa_client_type_t cons_client,
  1423. uint8_t session_id, bool is_ipv6_enabled)
  1424. {
  1425. qdf_ipa_wdi_reg_intf_in_params_t in;
  1426. qdf_ipa_wdi_hdr_info_t hdr_info;
  1427. struct dp_ipa_uc_tx_hdr uc_tx_hdr;
  1428. struct dp_ipa_uc_tx_hdr uc_tx_hdr_v6;
  1429. int ret = -EINVAL;
  1430. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  1431. "%s: Add Partial hdr: %s, "QDF_MAC_ADDR_FMT,
  1432. __func__, ifname, QDF_MAC_ADDR_REF(mac_addr));
  1433. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  1434. qdf_ether_addr_copy(uc_tx_hdr.eth.h_source, mac_addr);
  1435. /* IPV4 header */
  1436. uc_tx_hdr.eth.h_proto = qdf_htons(ETH_P_IP);
  1437. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr;
  1438. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  1439. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(&hdr_info) = IPA_HDR_L2_ETHERNET_II;
  1440. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  1441. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  1442. QDF_IPA_WDI_REG_INTF_IN_PARAMS_NETDEV_NAME(&in) = ifname;
  1443. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v4]),
  1444. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  1445. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_META_DATA_VALID(&in) = 1;
  1446. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(&in) =
  1447. htonl(session_id << 16);
  1448. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(&in) = htonl(0x00FF0000);
  1449. /* IPV6 header */
  1450. if (is_ipv6_enabled) {
  1451. qdf_mem_copy(&uc_tx_hdr_v6, &uc_tx_hdr,
  1452. DP_IPA_UC_WLAN_TX_HDR_LEN);
  1453. uc_tx_hdr_v6.eth.h_proto = qdf_htons(ETH_P_IPV6);
  1454. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr_v6;
  1455. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v6]),
  1456. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  1457. }
  1458. ret = qdf_ipa_wdi_reg_intf(&in);
  1459. if (ret) {
  1460. dp_err("ipa_wdi_reg_intf: register IPA interface falied: ret=%d",
  1461. ret);
  1462. return QDF_STATUS_E_FAILURE;
  1463. }
  1464. return QDF_STATUS_SUCCESS;
  1465. }
  1466. #endif /* CONFIG_IPA_WDI_UNIFIED_API */
  1467. /**
  1468. * dp_ipa_cleanup() - Disconnect IPA pipes
  1469. * @soc_hdl: dp soc handle
  1470. * @pdev_id: dp pdev id
  1471. * @tx_pipe_handle: Tx pipe handle
  1472. * @rx_pipe_handle: Rx pipe handle
  1473. *
  1474. * Return: QDF_STATUS
  1475. */
  1476. QDF_STATUS dp_ipa_cleanup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1477. uint32_t tx_pipe_handle, uint32_t rx_pipe_handle)
  1478. {
  1479. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1480. QDF_STATUS status = QDF_STATUS_SUCCESS;
  1481. struct dp_ipa_resources *ipa_res;
  1482. struct dp_pdev *pdev;
  1483. int ret;
  1484. ret = qdf_ipa_wdi_disconn_pipes();
  1485. if (ret) {
  1486. dp_err("ipa_wdi_disconn_pipes: IPA pipe cleanup failed: ret=%d",
  1487. ret);
  1488. status = QDF_STATUS_E_FAILURE;
  1489. }
  1490. pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1491. if (qdf_unlikely(!pdev)) {
  1492. dp_err_rl("Invalid pdev for pdev_id %d", pdev_id);
  1493. status = QDF_STATUS_E_FAILURE;
  1494. goto exit;
  1495. }
  1496. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  1497. ipa_res = &pdev->ipa_resource;
  1498. /* unmap has to be the reverse order of smmu map */
  1499. ret = pld_smmu_unmap(soc->osdev->dev,
  1500. ipa_res->rx_ready_doorbell_paddr,
  1501. sizeof(uint32_t));
  1502. qdf_assert_always(!ret);
  1503. ret = pld_smmu_unmap(soc->osdev->dev,
  1504. ipa_res->tx_comp_doorbell_paddr,
  1505. sizeof(uint32_t));
  1506. qdf_assert_always(!ret);
  1507. }
  1508. exit:
  1509. return status;
  1510. }
  1511. /**
  1512. * dp_ipa_cleanup_iface() - Cleanup IPA header and deregister interface
  1513. * @ifname: Interface name
  1514. * @is_ipv6_enabled: Is IPV6 enabled or not
  1515. *
  1516. * Return: QDF_STATUS
  1517. */
  1518. QDF_STATUS dp_ipa_cleanup_iface(char *ifname, bool is_ipv6_enabled)
  1519. {
  1520. int ret;
  1521. ret = qdf_ipa_wdi_dereg_intf(ifname);
  1522. if (ret) {
  1523. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1524. "%s: ipa_wdi_dereg_intf: IPA pipe deregistration failed: ret=%d",
  1525. __func__, ret);
  1526. return QDF_STATUS_E_FAILURE;
  1527. }
  1528. return QDF_STATUS_SUCCESS;
  1529. }
  1530. #ifdef IPA_SET_RESET_TX_DB_PA
  1531. static
  1532. QDF_STATUS dp_ipa_reset_tx_doorbell_pa(struct dp_soc *soc,
  1533. struct dp_ipa_resources *ipa_res)
  1534. {
  1535. hal_ring_handle_t wbm_srng =
  1536. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1537. qdf_dma_addr_t hp_addr;
  1538. if (!wbm_srng)
  1539. return QDF_STATUS_E_FAILURE;
  1540. hp_addr = soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr;
  1541. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  1542. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  1543. return QDF_STATUS_SUCCESS;
  1544. }
  1545. #define DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res) \
  1546. dp_ipa_set_tx_doorbell_paddr((soc), (ipa_res))
  1547. #define DP_IPA_RESET_TX_DB_PA(soc, ipa_res) \
  1548. dp_ipa_reset_tx_doorbell_pa((soc), (ipa_res))
  1549. #else
  1550. #define DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res)
  1551. #define DP_IPA_RESET_TX_DB_PA(soc, ipa_res)
  1552. #endif
  1553. QDF_STATUS dp_ipa_enable_pipes(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1554. {
  1555. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1556. struct dp_pdev *pdev =
  1557. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1558. struct hal_srng *wbm_srng = (struct hal_srng *)
  1559. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1560. struct dp_ipa_resources *ipa_res;
  1561. QDF_STATUS result;
  1562. if (!pdev) {
  1563. dp_err("Invalid instance");
  1564. return QDF_STATUS_E_FAILURE;
  1565. }
  1566. ipa_res = &pdev->ipa_resource;
  1567. qdf_atomic_set(&soc->ipa_pipes_enabled, 1);
  1568. DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res);
  1569. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, true);
  1570. result = qdf_ipa_wdi_enable_pipes();
  1571. if (result) {
  1572. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1573. "%s: Enable WDI PIPE fail, code %d",
  1574. __func__, result);
  1575. qdf_atomic_set(&soc->ipa_pipes_enabled, 0);
  1576. DP_IPA_RESET_TX_DB_PA(soc, ipa_res);
  1577. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, false);
  1578. return QDF_STATUS_E_FAILURE;
  1579. }
  1580. if (soc->ipa_first_tx_db_access) {
  1581. hal_srng_dst_init_hp(
  1582. soc->hal_soc, wbm_srng,
  1583. ipa_res->tx_comp_doorbell_vaddr);
  1584. soc->ipa_first_tx_db_access = false;
  1585. }
  1586. return QDF_STATUS_SUCCESS;
  1587. }
  1588. QDF_STATUS dp_ipa_disable_pipes(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1589. {
  1590. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1591. struct dp_pdev *pdev =
  1592. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1593. QDF_STATUS result;
  1594. struct dp_ipa_resources *ipa_res;
  1595. if (!pdev) {
  1596. dp_err("Invalid instance");
  1597. return QDF_STATUS_E_FAILURE;
  1598. }
  1599. ipa_res = &pdev->ipa_resource;
  1600. qdf_sleep(TX_COMP_DRAIN_WAIT_TIMEOUT_MS);
  1601. /*
  1602. * Reset the tx completion doorbell address before invoking IPA disable
  1603. * pipes API to ensure that there is no access to IPA tx doorbell
  1604. * address post disable pipes.
  1605. */
  1606. DP_IPA_RESET_TX_DB_PA(soc, ipa_res);
  1607. result = qdf_ipa_wdi_disable_pipes();
  1608. if (result) {
  1609. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1610. "%s: Disable WDI PIPE fail, code %d",
  1611. __func__, result);
  1612. qdf_assert_always(0);
  1613. return QDF_STATUS_E_FAILURE;
  1614. }
  1615. qdf_atomic_set(&soc->ipa_pipes_enabled, 0);
  1616. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, false);
  1617. return result ? QDF_STATUS_E_FAILURE : QDF_STATUS_SUCCESS;
  1618. }
  1619. /**
  1620. * dp_ipa_set_perf_level() - Set IPA clock bandwidth based on data rates
  1621. * @client: Client type
  1622. * @max_supported_bw_mbps: Maximum bandwidth needed (in Mbps)
  1623. *
  1624. * Return: QDF_STATUS
  1625. */
  1626. QDF_STATUS dp_ipa_set_perf_level(int client, uint32_t max_supported_bw_mbps)
  1627. {
  1628. qdf_ipa_wdi_perf_profile_t profile;
  1629. QDF_STATUS result;
  1630. profile.client = client;
  1631. profile.max_supported_bw_mbps = max_supported_bw_mbps;
  1632. result = qdf_ipa_wdi_set_perf_profile(&profile);
  1633. if (result) {
  1634. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1635. "%s: ipa_wdi_set_perf_profile fail, code %d",
  1636. __func__, result);
  1637. return QDF_STATUS_E_FAILURE;
  1638. }
  1639. return QDF_STATUS_SUCCESS;
  1640. }
  1641. /**
  1642. * dp_ipa_intrabss_send - send IPA RX intra-bss frames
  1643. * @pdev: pdev
  1644. * @vdev: vdev
  1645. * @nbuf: skb
  1646. *
  1647. * Return: nbuf if TX fails and NULL if TX succeeds
  1648. */
  1649. static qdf_nbuf_t dp_ipa_intrabss_send(struct dp_pdev *pdev,
  1650. struct dp_vdev *vdev,
  1651. qdf_nbuf_t nbuf)
  1652. {
  1653. struct dp_peer *vdev_peer;
  1654. uint16_t len;
  1655. vdev_peer = dp_vdev_bss_peer_ref_n_get(pdev->soc, vdev, DP_MOD_ID_IPA);
  1656. if (qdf_unlikely(!vdev_peer))
  1657. return nbuf;
  1658. qdf_mem_zero(nbuf->cb, sizeof(nbuf->cb));
  1659. len = qdf_nbuf_len(nbuf);
  1660. if (dp_tx_send((struct cdp_soc_t *)pdev->soc, vdev->vdev_id, nbuf)) {
  1661. DP_STATS_INC_PKT(vdev_peer, rx.intra_bss.fail, 1, len);
  1662. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  1663. return nbuf;
  1664. }
  1665. DP_STATS_INC_PKT(vdev_peer, rx.intra_bss.pkts, 1, len);
  1666. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  1667. return NULL;
  1668. }
  1669. bool dp_ipa_rx_intrabss_fwd(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1670. qdf_nbuf_t nbuf, bool *fwd_success)
  1671. {
  1672. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1673. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  1674. DP_MOD_ID_IPA);
  1675. struct dp_pdev *pdev;
  1676. struct dp_peer *da_peer;
  1677. struct dp_peer *sa_peer;
  1678. qdf_nbuf_t nbuf_copy;
  1679. uint8_t da_is_bcmc;
  1680. struct ethhdr *eh;
  1681. bool status = false;
  1682. *fwd_success = false; /* set default as failure */
  1683. /*
  1684. * WDI 3.0 skb->cb[] info from IPA driver
  1685. * skb->cb[0] = vdev_id
  1686. * skb->cb[1].bit#1 = da_is_bcmc
  1687. */
  1688. da_is_bcmc = ((uint8_t)nbuf->cb[1]) & 0x2;
  1689. if (qdf_unlikely(!vdev))
  1690. return false;
  1691. pdev = vdev->pdev;
  1692. if (qdf_unlikely(!pdev))
  1693. goto out;
  1694. /* no fwd for station mode and just pass up to stack */
  1695. if (vdev->opmode == wlan_op_mode_sta)
  1696. goto out;
  1697. if (da_is_bcmc) {
  1698. nbuf_copy = qdf_nbuf_copy(nbuf);
  1699. if (!nbuf_copy)
  1700. goto out;
  1701. if (dp_ipa_intrabss_send(pdev, vdev, nbuf_copy))
  1702. qdf_nbuf_free(nbuf_copy);
  1703. else
  1704. *fwd_success = true;
  1705. /* return false to pass original pkt up to stack */
  1706. goto out;
  1707. }
  1708. eh = (struct ethhdr *)qdf_nbuf_data(nbuf);
  1709. if (!qdf_mem_cmp(eh->h_dest, vdev->mac_addr.raw, QDF_MAC_ADDR_SIZE))
  1710. goto out;
  1711. da_peer = dp_peer_find_hash_find(soc, eh->h_dest, 0, vdev->vdev_id,
  1712. DP_MOD_ID_IPA);
  1713. if (!da_peer)
  1714. goto out;
  1715. dp_peer_unref_delete(da_peer, DP_MOD_ID_IPA);
  1716. sa_peer = dp_peer_find_hash_find(soc, eh->h_source, 0, vdev->vdev_id,
  1717. DP_MOD_ID_IPA);
  1718. if (!sa_peer)
  1719. goto out;
  1720. dp_peer_unref_delete(sa_peer, DP_MOD_ID_IPA);
  1721. /*
  1722. * In intra-bss forwarding scenario, skb is allocated by IPA driver.
  1723. * Need to add skb to internal tracking table to avoid nbuf memory
  1724. * leak check for unallocated skb.
  1725. */
  1726. qdf_net_buf_debug_acquire_skb(nbuf, __FILE__, __LINE__);
  1727. if (dp_ipa_intrabss_send(pdev, vdev, nbuf))
  1728. qdf_nbuf_free(nbuf);
  1729. else
  1730. *fwd_success = true;
  1731. status = true;
  1732. out:
  1733. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_IPA);
  1734. return status;
  1735. }
  1736. #ifdef MDM_PLATFORM
  1737. bool dp_ipa_is_mdm_platform(void)
  1738. {
  1739. return true;
  1740. }
  1741. #else
  1742. bool dp_ipa_is_mdm_platform(void)
  1743. {
  1744. return false;
  1745. }
  1746. #endif
  1747. /**
  1748. * dp_ipa_frag_nbuf_linearize - linearize nbuf for IPA
  1749. * @soc: soc
  1750. * @nbuf: source skb
  1751. *
  1752. * Return: new nbuf if success and otherwise NULL
  1753. */
  1754. static qdf_nbuf_t dp_ipa_frag_nbuf_linearize(struct dp_soc *soc,
  1755. qdf_nbuf_t nbuf)
  1756. {
  1757. uint8_t *src_nbuf_data;
  1758. uint8_t *dst_nbuf_data;
  1759. qdf_nbuf_t dst_nbuf;
  1760. qdf_nbuf_t temp_nbuf = nbuf;
  1761. uint32_t nbuf_len = qdf_nbuf_len(nbuf);
  1762. bool is_nbuf_head = true;
  1763. uint32_t copy_len = 0;
  1764. dst_nbuf = qdf_nbuf_alloc(soc->osdev, RX_DATA_BUFFER_SIZE,
  1765. RX_BUFFER_RESERVATION,
  1766. RX_DATA_BUFFER_ALIGNMENT, FALSE);
  1767. if (!dst_nbuf) {
  1768. dp_err_rl("nbuf allocate fail");
  1769. return NULL;
  1770. }
  1771. if ((nbuf_len + L3_HEADER_PADDING) > RX_DATA_BUFFER_SIZE) {
  1772. qdf_nbuf_free(dst_nbuf);
  1773. dp_err_rl("nbuf is jumbo data");
  1774. return NULL;
  1775. }
  1776. /* prepeare to copy all data into new skb */
  1777. dst_nbuf_data = qdf_nbuf_data(dst_nbuf);
  1778. while (temp_nbuf) {
  1779. src_nbuf_data = qdf_nbuf_data(temp_nbuf);
  1780. /* first head nbuf */
  1781. if (is_nbuf_head) {
  1782. qdf_mem_copy(dst_nbuf_data, src_nbuf_data,
  1783. RX_PKT_TLVS_LEN);
  1784. /* leave extra 2 bytes L3_HEADER_PADDING */
  1785. dst_nbuf_data += (RX_PKT_TLVS_LEN + L3_HEADER_PADDING);
  1786. src_nbuf_data += RX_PKT_TLVS_LEN;
  1787. copy_len = qdf_nbuf_headlen(temp_nbuf) -
  1788. RX_PKT_TLVS_LEN;
  1789. temp_nbuf = qdf_nbuf_get_ext_list(temp_nbuf);
  1790. is_nbuf_head = false;
  1791. } else {
  1792. copy_len = qdf_nbuf_len(temp_nbuf);
  1793. temp_nbuf = qdf_nbuf_queue_next(temp_nbuf);
  1794. }
  1795. qdf_mem_copy(dst_nbuf_data, src_nbuf_data, copy_len);
  1796. dst_nbuf_data += copy_len;
  1797. }
  1798. qdf_nbuf_set_len(dst_nbuf, nbuf_len);
  1799. /* copy is done, free original nbuf */
  1800. qdf_nbuf_free(nbuf);
  1801. return dst_nbuf;
  1802. }
  1803. /**
  1804. * dp_ipa_handle_rx_reo_reinject - Handle RX REO reinject skb buffer
  1805. * @soc: soc
  1806. * @nbuf: skb
  1807. *
  1808. * Return: nbuf if success and otherwise NULL
  1809. */
  1810. qdf_nbuf_t dp_ipa_handle_rx_reo_reinject(struct dp_soc *soc, qdf_nbuf_t nbuf)
  1811. {
  1812. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1813. return nbuf;
  1814. /* WLAN IPA is run-time disabled */
  1815. if (!qdf_atomic_read(&soc->ipa_pipes_enabled))
  1816. return nbuf;
  1817. if (!qdf_nbuf_is_frag(nbuf))
  1818. return nbuf;
  1819. /* linearize skb for IPA */
  1820. return dp_ipa_frag_nbuf_linearize(soc, nbuf);
  1821. }
  1822. QDF_STATUS dp_ipa_tx_buf_smmu_mapping(
  1823. struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1824. {
  1825. QDF_STATUS ret;
  1826. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1827. struct dp_pdev *pdev =
  1828. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1829. if (!pdev) {
  1830. dp_err("%s invalid instance", __func__);
  1831. return QDF_STATUS_E_FAILURE;
  1832. }
  1833. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  1834. dp_debug("SMMU S1 disabled");
  1835. return QDF_STATUS_SUCCESS;
  1836. }
  1837. ret = __dp_ipa_tx_buf_smmu_mapping(soc, pdev, true);
  1838. return ret;
  1839. }
  1840. QDF_STATUS dp_ipa_tx_buf_smmu_unmapping(
  1841. struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1842. {
  1843. QDF_STATUS ret;
  1844. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1845. struct dp_pdev *pdev =
  1846. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1847. if (!pdev) {
  1848. dp_err("%s invalid instance", __func__);
  1849. return QDF_STATUS_E_FAILURE;
  1850. }
  1851. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  1852. dp_debug("SMMU S1 disabled");
  1853. return QDF_STATUS_SUCCESS;
  1854. }
  1855. ret = __dp_ipa_tx_buf_smmu_mapping(soc, pdev, false);
  1856. return ret;
  1857. }
  1858. #endif